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branch.txt
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vsim -gui work.processor
add wave -position insertpoint \
sim:/processor/clk
add wave -position insertpoint \
sim:/processor/Fetch_Decode_Stages/myfetch/pcOut
add wave -position insertpoint \
sim:/processor/Fetch_Decode_Stages/myfetch/IR
add wave -position insertpoint \
sim:/processor/Fetch_Decode_Stages/myfetch/JumpAddress
add wave -position insertpoint \
sim:/processor/Fetch_Decode_Stages/myfetch/Exception \
sim:/processor/Fetch_Decode_Stages/myfetch/Stack
add wave -position insertpoint \
sim:/processor/IN_PORT
add wave -position insertpoint \
sim:/processor/EX_MEM_WB_Stages/EX_Stage/flags
add wave -position insertpoint \
sim:/processor/Fetch_Decode_Stages/mydecode/myReg_file/SIGNAL_FROM_FF
mem load -skip 0 -filltype value -filldata 00000 -fillradix hexadecimal -startaddress 0 -endaddress 7 /processor/Fetch_Decode_Stages/mydecode/myReg_file/SIGNAL_FROM_FF
mem load -skip 0 -filltype value -filldata 000 -fillradix binary -startaddress 0 -endaddress 7 /processor/Fetch_Decode_Stages/mydecode/myReg_file/SIGNAL_FROM_FF
mem load -skip 0 -filltype value -filldata 0000000000000000 -fillradix binary -startaddress 0 -endaddress 0 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0000000000010000 -fillradix binary -startaddress 1 -endaddress 1 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0000010000000000 -fillradix binary -startaddress 2 -endaddress 2 /processor/EX_MEM_WB_Stages/MEM_Stage/DataMemAndStack/ram
mem load -skip 0 -filltype value -filldata 0000000000000000 -fillradix binary -startaddress 3 -endaddress 3 /processor/EX_MEM_WB_Stages/MEM_Stage/DataMemAndStack/ram
mem load -skip 0 -filltype value -filldata 0000010001010000 -fillradix binary -startaddress 4 -endaddress 4 /processor/EX_MEM_WB_Stages/MEM_Stage/DataMemAndStack/ram
mem load -skip 0 -filltype value -filldata 0000000000000000 -fillradix binary -startaddress 5 -endaddress 5 /processor/EX_MEM_WB_Stages/MEM_Stage/DataMemAndStack/ram
mem load -skip 0 -filltype value -filldata 0000001000000000 -fillradix binary -startaddress 6 -endaddress 6 /processor/EX_MEM_WB_Stages/MEM_Stage/DataMemAndStack/ram
mem load -skip 0 -filltype value -filldata 0000000000000000 -fillradix binary -startaddress 7 -endaddress 7 /processor/EX_MEM_WB_Stages/MEM_Stage/DataMemAndStack/ram
mem load -skip 0 -filltype value -filldata 0000001001010000 -fillradix binary -startaddress 18 -endaddress 18 /processor/EX_MEM_WB_Stages/MEM_Stage/DataMemAndStack/ram
mem load -skip 0 -filltype value -filldata 0000000000000000 -fillradix binary -startaddress 19 -endaddress 19 /processor/EX_MEM_WB_Stages/MEM_Stage/DataMemAndStack/ram
mem load -skip 0 -filltype value -filldata 0101000000000000 -fillradix binary -startaddress 512 -endaddress 512 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0010111011011000 -fillradix binary -startaddress 513 -endaddress 513 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 1100000000000000 -fillradix binary -startaddress 514 -endaddress 514 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0001000000000000 -fillradix binary -startaddress 592 -endaddress 592 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0101000000000000 -fillradix binary -startaddress 593 -endaddress 593 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0010101001001000 -fillradix binary -startaddress 594 -endaddress 594 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 1100000000000000 -fillradix binary -startaddress 595 -endaddress 595 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0011000100100100 -fillradix binary -startaddress 16 -endaddress 16 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0011001001001000 -fillradix binary -startaddress 17 -endaddress 17 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0011001101101100 -fillradix binary -startaddress 18 -endaddress 18 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0011010010010000 -fillradix binary -startaddress 19 -endaddress 19 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0110010010010000 -fillradix binary -startaddress 20 -endaddress 20 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 1011100000000000 -fillradix binary -startaddress 21 -endaddress 21 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0000000000010010 -fillradix binary -startaddress 22 -endaddress 22 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 1010000100100100 -fillradix binary -startaddress 23 -endaddress 23 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0010000100100100 -fillradix binary -startaddress 24 -endaddress 24 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0101010100110100 -fillradix binary -startaddress 48 -endaddress 48 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 1000101001001000 -fillradix binary -startaddress 49 -endaddress 49 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0001000000000000 -fillradix binary -startaddress 50 -endaddress 50 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 1000100100100100 -fillradix binary -startaddress 80 -endaddress 80 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 1001101101101100 -fillradix binary -startaddress 81 -endaddress 81 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0001110110110100 -fillradix binary -startaddress 82 -endaddress 82 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 1011100000000000 -fillradix binary -startaddress 83 -endaddress 83 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0000000000000110 -fillradix binary -startaddress 84 -endaddress 84 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0011011011011000 -fillradix binary -startaddress 85 -endaddress 85 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 1001011011011000 -fillradix binary -startaddress 86 -endaddress 86 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0010000100100100 -fillradix binary -startaddress 87 -endaddress 87 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0001000000000000 -fillradix binary -startaddress 1792 -endaddress 1792 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0110111011011000 -fillradix binary -startaddress 1793 -endaddress 1793 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 1010111011011000 -fillradix binary -startaddress 1794 -endaddress 1794 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0010011011011000 -fillradix binary -startaddress 1795 -endaddress 1795 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0000000000000000 -fillradix binary -startaddress 1796 -endaddress 1796 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0000000000000000 -fillradix binary -startaddress 1797 -endaddress 1797 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0100011001111000 -fillradix binary -startaddress 768 -endaddress 768 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0100000100101000 -fillradix binary -startaddress 769 -endaddress 769 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 1011000000000000 -fillradix binary -startaddress 770 -endaddress 770 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0001000000000000 -fillradix binary -startaddress 771 -endaddress 771 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0000000000000000 -fillradix binary -startaddress 1280 -endaddress 1280 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
mem load -skip 0 -filltype value -filldata 0000000000000000 -fillradix binary -startaddress 1281 -endaddress 1281 processor/Fetch_Decode_Stages/myfetch/INSTRUC_MEM/ram
force -freeze sim:/processor/clk 1 0, 0 {50 ps} -r 100
force -freeze sim:/processor/Fetch_Decode_Stages/myfetch/MUX1_SEL 00 0
force -freeze sim:/processor/Fetch_Decode_Stages/myfetch/HLT 0 0
force -freeze sim:/processor/reset 1 0
force -freeze sim:/processor/IN_PORT x\"0030\" 0
force -freeze sim:/processor/Fetch_Decode_Stages/MO_1 x\"00a0\" 0
force -freeze sim:/processor/Fetch_Decode_Stages/IF_ID_BUFFER/FLUSH 0 0
force -freeze sim:/processor/EX_MEM_WB_Stages/MEM_Stage/sp_register_call/D 16#FFFFF 0
# ** Warning: (vsim-8780) Forcing /processor/Fetch_Decode_Stages/FLUSH as root of /processor/Fetch_Decode_Stages/IF_ID_BUFFER/FLUSH specified in the force.
#Until we make the exception unit
#force -freeze sim:/processor/Fetch_Decode_Stages/IS_EXCEPTION 0 0
run
noforce sim:/processor/Fetch_Decode_Stages/myfetch/MUX1_SEL
noforce sim:/processor/Fetch_Decode_Stages/myfetch/HLT
noforce sim:/processor/Fetch_Decode_Stages/IF_ID_BUFFER/FLUSH
noforce sim:/processor/EX_MEM_WB_Stages/MEM_Stage/sp_register_call/D
force -freeze sim:/processor/reset 0 0
run
force -freeze sim:/processor/IN_PORT x\"0050\" 0
run
force -freeze sim:/processor/IN_PORT x\"0100\" 0
run
force -freeze sim:/processor/IN_PORT x\"0300\" 0
run