mpram.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2012 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 12.0 Build 178 05/31/2012 SJ Full Version
# Date created = 18:35:55  March 21, 2013
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		mpram_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Stratix V"
set_global_assignment -name DEVICE 5SGXMA5N1F45C1
set_global_assignment -name TOP_LEVEL_ENTITY mpram_wrp
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:35:55  MARCH 21, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION 12.0
set_global_assignment -name VERILOG_INCLUDE_FILE utils.vh
set_global_assignment -name VERILOG_INCLUDE_FILE config.vh
set_global_assignment -name VERILOG_FILE dpram.v
set_global_assignment -name VERILOG_FILE mrram.v
set_global_assignment -name VERILOG_FILE mpram_xor.v
set_global_assignment -name VERILOG_FILE mpram_reg.v
set_global_assignment -name VERILOG_FILE mpram_gen.v
set_global_assignment -name VERILOG_FILE mpram_lvt_reg.v
set_global_assignment -name VERILOG_FILE mpram_lvt_bin.v
set_global_assignment -name VERILOG_FILE mpram_lvt_1ht.v
set_global_assignment -name VERILOG_FILE mpram.v
set_global_assignment -name VERILOG_FILE mpram_wrp.v
set_global_assignment -name VERILOG_FILE lvt_reg.v
set_global_assignment -name VERILOG_FILE lvt_bin.v
set_global_assignment -name VERILOG_FILE lvt_1ht.v
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 1_H1
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top


set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top