LPC2300.lst




ARM Macro Assembler    Page 1 


    1 00000000         ;/******************************************************
                       ***********************/
    2 00000000         ;/* LPC2300.S: Startup file for Philips LPC2300 device s
                       eries                 */
    3 00000000         ;/******************************************************
                       ***********************/
    4 00000000         ;/* <<< Use Configuration Wizard in Context Menu >>>    
                                             */
    5 00000000         ;/******************************************************
                       ***********************/
    6 00000000         ;/* This file is part of the uVision/ARM development too
                       ls.                   */
    7 00000000         ;/* Copyright (c) 2007 Keil - An ARM Company. All rights
                        reserved.            */
    8 00000000         ;/* This software may only be used under the terms of a 
                       valid, current,       */
    9 00000000         ;/* end user licence from KEIL for a compatible version 
                       of KEIL software      */
   10 00000000         ;/* development tools. Nothing else gives you the right 
                       to use this software. */
   11 00000000         ;/******************************************************
                       ***********************/
   12 00000000         
   13 00000000         
   14 00000000         ;/*
   15 00000000         ; *  The LPC2300.S code is executed after CPU Reset. Thi
                       s file may be 
   16 00000000         ; *  translated with the following SET symbols. In uVisi
                       on these SET 
   17 00000000         ; *  symbols are entered under Options - ASM - Define.
   18 00000000         ; *
   19 00000000         ; *  NO_CLOCK_SETUP: when set the startup code will not 
                       initialize Clock 
   20 00000000         ; *  (used mostly when clock is already initialized from
                        script .ini 
   21 00000000         ; *  file).
   22 00000000         ; *
   23 00000000         ; *  NO_EMC_SETUP: when set the startup code will not in
                       itializes External 
   24 00000000         ; *  Memory Controller (used mostly when external memory
                        is already initialized 
   25 00000000         ; *  and loaded from script .ini file).
   26 00000000         ; *
   27 00000000         ; *  RAM_INTVEC: when set the startup code copies except
                       ion vectors 
   28 00000000         ; *  from on-chip Flash to on-chip RAM.
   29 00000000         ; *
   30 00000000         ; *  REMAP: when set the startup code initializes the re
                       gister MEMMAP 
   31 00000000         ; *  which overwrites the settings of the CPU configurat
                       ion pins. The 
   32 00000000         ; *  startup and interrupt vectors are remapped from:
   33 00000000         ; *     0x00000000  default setting (not remapped)
   34 00000000         ; *     0x40000000  when RAM_MODE is used
   35 00000000         ; *     0x80000000  when EXTMEM_MODE is used
   36 00000000         ; *
   37 00000000         ; *  EXTMEM_MODE: when set the device is configured for 
                       code execution
   38 00000000         ; *  from external memory starting at address 0x80000000



ARM Macro Assembler    Page 2 


                       .
   39 00000000         ; *
   40 00000000         ; *  RAM_MODE: when set the device is configured for cod
                       e execution
   41 00000000         ; *  from on-chip RAM starting at address 0x40000000. 
   42 00000000         ; */
   43 00000000         
   44 00000000         
   45 00000000         ; Standard definitions of Mode bits and Interrupt (I & F
                       ) flags in PSRs
   46 00000000         
   47 00000000 00000010 
                       Mode_USR
                               EQU              0x10
   48 00000000 00000011 
                       Mode_FIQ
                               EQU              0x11
   49 00000000 00000012 
                       Mode_IRQ
                               EQU              0x12
   50 00000000 00000013 
                       Mode_SVC
                               EQU              0x13
   51 00000000 00000017 
                       Mode_ABT
                               EQU              0x17
   52 00000000 0000001B 
                       Mode_UND
                               EQU              0x1B
   53 00000000 0000001F 
                       Mode_SYS
                               EQU              0x1F
   54 00000000         
   55 00000000 00000080 
                       I_Bit   EQU              0x80        ; when I bit is set
                                                            , IRQ is disabled
   56 00000000 00000040 
                       F_Bit   EQU              0x40        ; when F bit is set
                                                            , FIQ is disabled
   57 00000000         
   58 00000000         
   59 00000000         ;----------------------- Memory Definitions ------------
                       ------------------------
   60 00000000         
   61 00000000         ; Internal Memory Base Addresses
   62 00000000 00000000 
                       FLASH_BASE
                               EQU              0x00000000
   63 00000000 40000000 
                       RAM_BASE
                               EQU              0x40000000
   64 00000000 80000000 
                       EXTMEM_BASE
                               EQU              0x80000000
   65 00000000         
   66 00000000         ; External Memory Base Addresses
   67 00000000 80000000 
                       STA_MEM0_BASE
                               EQU              0x80000000



ARM Macro Assembler    Page 3 


   68 00000000 81000000 
                       STA_MEM1_BASE
                               EQU              0x81000000
   69 00000000         
   70 00000000         
   71 00000000         ;----------------------- Stack and Heap Definitions ----
                       ------------------------
   72 00000000         
   73 00000000         ;// <h> Stack Configuration (Stack Sizes in Bytes)
   74 00000000         ;//   <o0> Undefined Mode      <0x0-0xFFFFFFFF:8>
   75 00000000         ;//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF:8>
   76 00000000         ;//   <o2> Abort Mode          <0x0-0xFFFFFFFF:8>
   77 00000000         ;//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
   78 00000000         ;//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF:8>
   79 00000000         ;//   <o5> User/System Mode    <0x0-0xFFFFFFFF:8>
   80 00000000         ;// </h>
   81 00000000         
   82 00000000 00000000 
                       UND_Stack_Size
                               EQU              0x00000000
   83 00000000 00000008 
                       SVC_Stack_Size
                               EQU              0x00000008
   84 00000000 00000000 
                       ABT_Stack_Size
                               EQU              0x00000000
   85 00000000 00000000 
                       FIQ_Stack_Size
                               EQU              0x00000000
   86 00000000 00000100 
                       IRQ_Stack_Size
                               EQU              0x00000100
   87 00000000 00000400 
                       USR_Stack_Size
                               EQU              0x00000400
   88 00000000         
   90 00000000 00000108 
                       ISR_Stack_Size
                               EQU              (UND_Stack_Size + SVC_Stack_Siz
e + ABT_Stack_Size +                           FIQ_Stack_Size + IRQ_Stack_Size
)
   91 00000000         
   92 00000000                 AREA             STACK, NOINIT, READWRITE, ALIGN
=3
   93 00000000         
   94 00000000         Stack_Mem
                               SPACE            USR_Stack_Size
   95 00000400         __initial_sp
                               SPACE            ISR_Stack_Size
   96 00000508         
   97 00000508         Stack_Top
   98 00000508         
   99 00000508         
  100 00000508         ;// <h> Heap Configuration
  101 00000508         ;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF>
  102 00000508         ;// </h>
  103 00000508         
  104 00000508 00000000 
                       Heap_Size



ARM Macro Assembler    Page 4 


                               EQU              0x00000000
  105 00000508         
  106 00000508                 AREA             HEAP, NOINIT, READWRITE, ALIGN=
3
  107 00000000         __heap_base
  108 00000000         Heap_Mem
                               SPACE            Heap_Size
  109 00000000         __heap_limit
  110 00000000         
  111 00000000         
  112 00000000         ;----------------------- System Control Block (SCB) Modu
                       le Definitions ---------
  113 00000000         
  114 00000000 E01FC000 
                       SCB_BASE
                               EQU              0xE01FC000  ; SCB Base Address
  115 00000000 00000080 
                       PLLCON_OFS
                               EQU              0x80        ; PLL Control Offse
                                                            t
  116 00000000 00000084 
                       PLLCFG_OFS
                               EQU              0x84        ; PLL Configuration
                                                             Offset
  117 00000000 00000088 
                       PLLSTAT_OFS
                               EQU              0x88        ; PLL Status Offset
                                                            
  118 00000000 0000008C 
                       PLLFEED_OFS
                               EQU              0x8C        ; PLL Feed Offset
  119 00000000 00000104 
                       CCLKCFG_OFS
                               EQU              0x104       ; CPU Clock Divider
                                                             Reg Offset
  120 00000000 00000108 
                       USBCLKCFG_OFS
                               EQU              0x108       ; USB Clock Divider
                                                             Reg Offset
  121 00000000 0000010C 
                       CLKSRCSEL_OFS
                               EQU              0x10C       ; Clock Source Sele
                                                            ct Reg Offset
  122 00000000 000001A0 
                       SCS_OFS EQU              0x1A0       ; System Control an
                                                            d Status Reg Offset
                                                            
  123 00000000 000001A8 
                       PCLKSEL0_OFS
                               EQU              0x1A8       ; Peripheral Clock 
                                                            Select Reg 0 Offset
                                                            
  124 00000000 000001AC 
                       PCLKSEL1_OFS
                               EQU              0x1AC       ; Peripheral Clock 
                                                            Select Reg 1 Offset
                                                            
  125 00000000         
  126 00000000 000000C0 



ARM Macro Assembler    Page 5 


                       PCON_OFS
                               EQU              0x0C0       ; Power Mode Contro
                                                            l Reg Offset
  127 00000000 000000C4 
                       PCONP_OFS
                               EQU              0x0C4       ; Power Control for
                                                             Periphs Reg Offset
                                                            
  128 00000000         
  129 00000000         ; Constants
  130 00000000 00000010 
                       OSCRANGE
                               EQU              (1<<4)      ; Oscillator Range 
                                                            Select
  131 00000000 00000020 
                       OSCEN   EQU              (1<<5)      ; Main oscillator E
                                                            nable
  132 00000000 00000040 
                       OSCSTAT EQU              (1<<6)      ; Main Oscillator S
                                                            tatus
  133 00000000 00000001 
                       PLLCON_PLLE
                               EQU              (1<<0)      ; PLL Enable
  134 00000000 00000002 
                       PLLCON_PLLC
                               EQU              (1<<1)      ; PLL Connect
  135 00000000 00007FFF 
                       PLLSTAT_M
                               EQU              (0x7FFF<<0) ; PLL M Value
  136 00000000 00FF0000 
                       PLLSTAT_N
                               EQU              (0xFF<<16)  ; PLL N Value
  137 00000000 04000000 
                       PLLSTAT_PLOCK
                               EQU              (1<<26)     ; PLL Lock Status
  138 00000000         
  139 00000000         ;// <e> Clock Setup
  140 00000000         ;//   <h> System Controls and Status Register (SCS)
  141 00000000         ;//     <o1.4>    OSCRANGE: Main Oscillator Range Select
                       
  142 00000000         ;//                     <0=>  1 MHz to 20 MHz
  143 00000000         ;//                     <1=> 15 MHz to 24 MHz
  144 00000000         ;//     <e1.5>       OSCEN: Main Oscillator Enable
  145 00000000         ;//     </e>
  146 00000000         ;//   </h>
  147 00000000         ;//
  148 00000000         ;//   <h> Clock Source Select Register (CLKSRCSEL)
  149 00000000         ;//     <o2.0..1>   CLKSRC: PLL Clock Source Selection
  150 00000000         ;//                     <0=> Internal RC oscillator
  151 00000000         ;//                     <1=> Main oscillator
  152 00000000         ;//                     <1=> RTC oscillator
  153 00000000         ;//   </h>
  154 00000000         ;//
  155 00000000         ;//   <h> PLL Configuration Register (PLLCFG)
  156 00000000         ;//                     <i> PLL_clk = (2* M * PLL_clk_sr
                       c) / N
  157 00000000         ;//     <o3.0..14>    MSEL: PLL Multiplier Selection
  158 00000000         ;//                     <1-32768><#-1>
  159 00000000         ;//                     <i> M Value



ARM Macro Assembler    Page 6 


  160 00000000         ;//     <o3.16..23>   NSEL: PLL Divider Selection
  161 00000000         ;//                     <1-256><#-1>
  162 00000000         ;//                     <i> N Value
  163 00000000         ;//   </h>
  164 00000000         ;//
  165 00000000         ;//   <h> CPU Clock Configuration Register (CCLKCFG)
  166 00000000         ;//     <o4.0..7>  CCLKSEL: Divide Value for CPU Clock f
                       rom PLL
  167 00000000         ;//                     <1-256><#-1>
  168 00000000         ;//   </h>
  169 00000000         ;//
  170 00000000         ;//   <h> USB Clock Configuration Register (USBCLKCFG)
  171 00000000         ;//     <o5.0..3>   USBSEL: Divide Value for USB Clock f
                       rom PLL
  172 00000000         ;//                     <1-16><#-1>
  173 00000000         ;//   </h>
  174 00000000         ;//
  175 00000000         ;//   <h> Peripheral Clock Selection Register 0 (PCLKSEL
                       0)
  176 00000000         ;//     <o6.0..1>      PCLK_WDT: Peripheral Clock Select
                       ion for WDT
  177 00000000         ;//                     <0=> Pclk = Cclk / 4
  178 00000000         ;//                     <1=> Pclk = Cclk
  179 00000000         ;//                     <2=> Pclk = Cclk / 2
  180 00000000         ;//                     <3=> Pclk = Hclk / 8
  181 00000000         ;//     <o6.2..3>   PCLK_TIMER0: Peripheral Clock Select
                       ion for TIMER0
  182 00000000         ;//                     <0=> Pclk = Cclk / 4
  183 00000000         ;//                     <1=> Pclk = Cclk
  184 00000000         ;//                     <2=> Pclk = Cclk / 2
  185 00000000         ;//                     <3=> Pclk = Hclk / 8
  186 00000000         ;//     <o6.4..5>   PCLK_TIMER1: Peripheral Clock Select
                       ion for TIMER1
  187 00000000         ;//                     <0=> Pclk = Cclk / 4
  188 00000000         ;//                     <1=> Pclk = Cclk
  189 00000000         ;//                     <2=> Pclk = Cclk / 2
  190 00000000         ;//                     <3=> Pclk = Hclk / 8
  191 00000000         ;//     <o6.6..7>    PCLK_UART0: Peripheral Clock Select
                       ion for UART0
  192 00000000         ;//                     <0=> Pclk = Cclk / 4
  193 00000000         ;//                     <1=> Pclk = Cclk
  194 00000000         ;//                     <2=> Pclk = Cclk / 2
  195 00000000         ;//                     <3=> Pclk = Hclk / 8
  196 00000000         ;//     <o6.8..9>    PCLK_UART1: Peripheral Clock Select
                       ion for UART1
  197 00000000         ;//                     <0=> Pclk = Cclk / 4
  198 00000000         ;//                     <1=> Pclk = Cclk
  199 00000000         ;//                     <2=> Pclk = Cclk / 2
  200 00000000         ;//                     <3=> Pclk = Hclk / 8
  201 00000000         ;//     <o6.10..11>   PCLK_PWM0: Peripheral Clock Select
                       ion for PWM0
  202 00000000         ;//                     <0=> Pclk = Cclk / 4
  203 00000000         ;//                     <1=> Pclk = Cclk
  204 00000000         ;//                     <2=> Pclk = Cclk / 2
  205 00000000         ;//                     <3=> Pclk = Hclk / 8
  206 00000000         ;//     <o6.12..13>   PCLK_PWM1: Peripheral Clock Select
                       ion for PWM1
  207 00000000         ;//                     <0=> Pclk = Cclk / 4
  208 00000000         ;//                     <1=> Pclk = Cclk



ARM Macro Assembler    Page 7 


  209 00000000         ;//                     <2=> Pclk = Cclk / 2
  210 00000000         ;//                     <3=> Pclk = Hclk / 8
  211 00000000         ;//     <o6.14..15>   PCLK_I2C0: Peripheral Clock Select
                       ion for I2C0
  212 00000000         ;//                     <0=> Pclk = Cclk / 4
  213 00000000         ;//                     <1=> Pclk = Cclk
  214 00000000         ;//                     <2=> Pclk = Cclk / 2
  215 00000000         ;//                     <3=> Pclk = Hclk / 8
  216 00000000         ;//     <o6.16..17>    PCLK_SPI: Peripheral Clock Select
                       ion for SPI
  217 00000000         ;//                     <0=> Pclk = Cclk / 4
  218 00000000         ;//                     <1=> Pclk = Cclk
  219 00000000         ;//                     <2=> Pclk = Cclk / 2
  220 00000000         ;//                     <3=> Pclk = Hclk / 8
  221 00000000         ;//     <o6.18..19>    PCLK_RTC: Peripheral Clock Select
                       ion for RTC
  222 00000000         ;//                     <0=> Pclk = Cclk / 4
  223 00000000         ;//                     <1=> Pclk = Cclk
  224 00000000         ;//                     <2=> Pclk = Cclk / 2
  225 00000000         ;//                     <3=> Pclk = Hclk / 8
  226 00000000         ;//     <o6.20..21>   PCLK_SSP1: Peripheral Clock Select
                       ion for SSP1
  227 00000000         ;//                     <0=> Pclk = Cclk / 4
  228 00000000         ;//                     <1=> Pclk = Cclk
  229 00000000         ;//                     <2=> Pclk = Cclk / 2
  230 00000000         ;//                     <3=> Pclk = Hclk / 8
  231 00000000         ;//     <o6.22..23>    PCLK_DAC: Peripheral Clock Select
                       ion for DAC
  232 00000000         ;//                     <0=> Pclk = Cclk / 4
  233 00000000         ;//                     <1=> Pclk = Cclk
  234 00000000         ;//                     <2=> Pclk = Cclk / 2
  235 00000000         ;//                     <3=> Pclk = Hclk / 8
  236 00000000         ;//     <o6.24..25>    PCLK_ADC: Peripheral Clock Select
                       ion for ADC
  237 00000000         ;//                     <0=> Pclk = Cclk / 4
  238 00000000         ;//                     <1=> Pclk = Cclk
  239 00000000         ;//                     <2=> Pclk = Cclk / 2
  240 00000000         ;//                     <3=> Pclk = Hclk / 8
  241 00000000         ;//     <o6.26..27>   PCLK_CAN1: Peripheral Clock Select
                       ion for CAN1
  242 00000000         ;//                     <0=> Pclk = Cclk / 4
  243 00000000         ;//                     <1=> Pclk = Cclk
  244 00000000         ;//                     <2=> Pclk = Cclk / 2
  245 00000000         ;//                     <3=> Pclk = Hclk / 6
  246 00000000         ;//     <o6.28..29>   PCLK_CAN2: Peripheral Clock Select
                       ion for CAN2
  247 00000000         ;//                     <0=> Pclk = Cclk / 4
  248 00000000         ;//                     <1=> Pclk = Cclk
  249 00000000         ;//                     <2=> Pclk = Cclk / 2
  250 00000000         ;//                     <3=> Pclk = Hclk / 6
  251 00000000         ;//     <o6.30..31>    PCLK_ACF: Peripheral Clock Select
                       ion for ACF
  252 00000000         ;//                     <0=> Pclk = Cclk / 4
  253 00000000         ;//                     <1=> Pclk = Cclk
  254 00000000         ;//                     <2=> Pclk = Cclk / 2
  255 00000000         ;//                     <3=> Pclk = Hclk / 6
  256 00000000         ;//   </h>
  257 00000000         ;//
  258 00000000         ;//   <h> Peripheral Clock Selection Register 1 (PCLKSEL



ARM Macro Assembler    Page 8 


                       1)
  259 00000000         ;//     <o7.0..1>  PCLK_BAT_RAM: Peripheral Clock Select
                       ion for the Battery Supported RAM
  260 00000000         ;//                     <0=> Pclk = Cclk / 4
  261 00000000         ;//                     <1=> Pclk = Cclk
  262 00000000         ;//                     <2=> Pclk = Cclk / 2
  263 00000000         ;//                     <3=> Pclk = Hclk / 8
  264 00000000         ;//     <o7.2..3>     PCLK_GPIO: Peripheral Clock Select
                       ion for GPIOs
  265 00000000         ;//                     <0=> Pclk = Cclk / 4
  266 00000000         ;//                     <1=> Pclk = Cclk
  267 00000000         ;//                     <2=> Pclk = Cclk / 2
  268 00000000         ;//                     <3=> Pclk = Hclk / 8
  269 00000000         ;//     <o7.4..5>      PCLK_PCB: Peripheral Clock Select
                       ion for Pin Connect Block
  270 00000000         ;//                     <0=> Pclk = Cclk / 4
  271 00000000         ;//                     <1=> Pclk = Cclk
  272 00000000         ;//                     <2=> Pclk = Cclk / 2
  273 00000000         ;//                     <3=> Pclk = Hclk / 8
  274 00000000         ;//     <o7.6..7>     PCLK_I2C1: Peripheral Clock Select
                       ion for I2C1
  275 00000000         ;//                     <0=> Pclk = Cclk / 4
  276 00000000         ;//                     <1=> Pclk = Cclk
  277 00000000         ;//                     <2=> Pclk = Cclk / 2
  278 00000000         ;//                     <3=> Pclk = Hclk / 8
  279 00000000         ;//     <o7.10..11>   PCLK_SSP0: Peripheral Clock Select
                       ion for SSP0
  280 00000000         ;//                     <0=> Pclk = Cclk / 4
  281 00000000         ;//                     <1=> Pclk = Cclk
  282 00000000         ;//                     <2=> Pclk = Cclk / 2
  283 00000000         ;//                     <3=> Pclk = Hclk / 8
  284 00000000         ;//     <o7.12..13> PCLK_TIMER2: Peripheral Clock Select
                       ion for TIMER2
  285 00000000         ;//                     <0=> Pclk = Cclk / 4
  286 00000000         ;//                     <1=> Pclk = Cclk
  287 00000000         ;//                     <2=> Pclk = Cclk / 2
  288 00000000         ;//                     <3=> Pclk = Hclk / 8
  289 00000000         ;//     <o7.14..15> PCLK_TIMER3: Peripheral Clock Select
                       ion for TIMER3
  290 00000000         ;//                     <0=> Pclk = Cclk / 4
  291 00000000         ;//                     <1=> Pclk = Cclk
  292 00000000         ;//                     <2=> Pclk = Cclk / 2
  293 00000000         ;//                     <3=> Pclk = Hclk / 8
  294 00000000         ;//     <o7.16..17>  PCLK_UART2: Peripheral Clock Select
                       ion for UART2
  295 00000000         ;//                     <0=> Pclk = Cclk / 4
  296 00000000         ;//                     <1=> Pclk = Cclk
  297 00000000         ;//                     <2=> Pclk = Cclk / 2
  298 00000000         ;//                     <3=> Pclk = Hclk / 8
  299 00000000         ;//     <o7.18..19>  PCLK_UART3: Peripheral Clock Select
                       ion for UART3
  300 00000000         ;//                     <0=> Pclk = Cclk / 4
  301 00000000         ;//                     <1=> Pclk = Cclk
  302 00000000         ;//                     <2=> Pclk = Cclk / 2
  303 00000000         ;//                     <3=> Pclk = Hclk / 8
  304 00000000         ;//     <o7.20..21>   PCLK_I2C2: Peripheral Clock Select
                       ion for I2C2
  305 00000000         ;//                     <0=> Pclk = Cclk / 4
  306 00000000         ;//                     <1=> Pclk = Cclk



ARM Macro Assembler    Page 9 


  307 00000000         ;//                     <2=> Pclk = Cclk / 2
  308 00000000         ;//                     <3=> Pclk = Hclk / 8
  309 00000000         ;//     <o7.22..23>    PCLK_I2S: Peripheral Clock Select
                       ion for I2S
  310 00000000         ;//                     <0=> Pclk = Cclk / 4
  311 00000000         ;//                     <1=> Pclk = Cclk
  312 00000000         ;//                     <2=> Pclk = Cclk / 2
  313 00000000         ;//                     <3=> Pclk = Hclk / 8
  314 00000000         ;//     <o7.24..25>    PCLK_MCI: Peripheral Clock Select
                       ion for MCI
  315 00000000         ;//                     <0=> Pclk = Cclk / 4
  316 00000000         ;//                     <1=> Pclk = Cclk
  317 00000000         ;//                     <2=> Pclk = Cclk / 2
  318 00000000         ;//                     <3=> Pclk = Hclk / 8
  319 00000000         ;//     <o7.28..29> PCLK_SYSCON: Peripheral Clock Select
                       ion for System Control Block
  320 00000000         ;//                     <0=> Pclk = Cclk / 4
  321 00000000         ;//                     <1=> Pclk = Cclk
  322 00000000         ;//                     <2=> Pclk = Cclk / 2
  323 00000000         ;//                     <3=> Pclk = Hclk / 8
  324 00000000         ;//   </h>
  325 00000000         ;//   <h> Power Control for Peripherals Register (PCONP)
                       
  326 00000000         ;//     <o8.31>     PCUSB: USB interface power/clock ena
                       ble
  327 00000000         ;//     <o8.30>     PCENET: Ethernet block power/clock e
                       nable
  328 00000000         ;//     <o8.29>     PCGPDMA: GP DMA function power/clock
                        enable
  329 00000000         ;//     <o8.28>     PCSDC: SD card interface power/clock
                        enable
  330 00000000         ;//     <o8.27>     PCI2S: I2S interface power/clock ena
                       ble
  331 00000000         ;//     <o8.26>     PCI2C2: I2C interface 2 power/clock 
                       enable
  332 00000000         ;//     <o8.25>     PCUART3: UART 3 power/clock enable
  333 00000000         ;//     <o8.24>     PCUART2: UART 2 power/clock enable
  334 00000000         ;//     <o8.23>     PCTIM3: Timer 3 power/clock enable
  335 00000000         ;//     <o8.22>     PCTIM2: Timer 2 power/clock enable
  336 00000000         ;//     <o8.21>     PCSSP0: SSP interface 0 power/clock 
                       enable
  337 00000000         ;//     <o8.19>     PCI2C1: I2C interface 1 power/clock 
                       enable
  338 00000000         ;//     <o8.14>     PCAN2: CAN controller 2 power/clock 
                       enable
  339 00000000         ;//     <o8.13>     PCAN1: CAN controller 1 power/clock 
                       enable
  340 00000000         ;//     <o8.12>     PCAD: A/D converter power/clock enab
                       le
  341 00000000         ;//     <o8.11>     PCEMC: External memory controller po
                       wer/clock enable
  342 00000000         ;//     <o8.10>     PCSSP1: SSP interface 1 power/clock 
                       enable
  343 00000000         ;//     <o8.9>      PCRTC: RTC power/clock enable
  344 00000000         ;//     <o8.8>      PCSPI: SPI interface power/clock ena
                       ble
  345 00000000         ;//     <o8.7>      PCI2C0: I2C interface 0 power/clock 
                       enable
  346 00000000         ;//     <o8.6>      PCPWM1: PWM 1 power/clock enable



ARM Macro Assembler    Page 10 


  347 00000000         ;//     <o8.4>      PCUART1: UART 1 power/clock enable
  348 00000000         ;//     <o8.3>      PCUART0: UART 0 power/clock enable
  349 00000000         ;//     <o8.2>      PCTIM1: Timer/Counter 1 power/clock 
                       enable
  350 00000000         ;//     <o8.1>      PCTIM0: Timer/Counter 0 power/clock 
                       enable
  351 00000000         ;//   </h>
  352 00000000         ;// </e>
  353 00000000 00000001 
                       CLOCK_SETUP
                               EQU              1
  354 00000000 00000020 
                       SCS_Val EQU              0x00000020
  355 00000000 00000001 
                       CLKSRCSEL_Val
                               EQU              0x00000001
  356 00000000 0000000B 
                       PLLCFG_Val
                               EQU              0x0000000B
  357 00000000 00000005 
                       CCLKCFG_Val
                               EQU              0x00000005
  358 00000000 00000005 
                       USBCLKCFG_Val
                               EQU              0x00000005
  359 00000000 00000000 
                       PCLKSEL0_Val
                               EQU              0x00000000
  360 00000000 00000000 
                       PCLKSEL1_Val
                               EQU              0x00000000
  361 00000000 04280FDE 
                       PCONP_Val
                               EQU              0x04280FDE
  362 00000000         
  363 00000000         ;----------------------- Memory Accelerator Module (MAM)
                        Definitions -----------
  364 00000000         
  365 00000000 E01FC000 
                       MAM_BASE
                               EQU              0xE01FC000  ; MAM Base Address
  366 00000000 00000000 
                       MAMCR_OFS
                               EQU              0x00        ; MAM Control Offse
                                                            t
  367 00000000 00000004 
                       MAMTIM_OFS
                               EQU              0x04        ; MAM Timing Offset
                                                            
  368 00000000         
  369 00000000         ;// <e> MAM Setup
  370 00000000         ;//   <o1.0..1>   MAM Control
  371 00000000         ;//               <0=> Disabled
  372 00000000         ;//               <1=> Partially Enabled
  373 00000000         ;//               <2=> Fully Enabled
  374 00000000         ;//               <i> Mode
  375 00000000         ;//   <o2.0..2>   MAM Timing
  376 00000000         ;//               <0=> Reserved  <1=> 1   <2=> 2   <3=> 
                       3



ARM Macro Assembler    Page 11 


  377 00000000         ;//               <4=> 4         <5=> 5   <6=> 6   <7=> 
                       7
  378 00000000         ;//               <i> Fetch Cycles
  379 00000000         ;// </e>
  380 00000000 00000001 
                       MAM_SETUP
                               EQU              1
  381 00000000 00000002 
                       MAMCR_Val
                               EQU              0x00000002
  382 00000000 00000004 
                       MAMTIM_Val
                               EQU              0x00000004
  383 00000000         
  384 00000000         
  385 00000000         ;----------------------- Pin Connect Block Definitions -
                       ------------------------
  386 00000000         
  387 00000000 E002C000 
                       PCB_BASE
                               EQU              0xE002C000  ; PCB Base Address
  388 00000000 00000000 
                       PINSEL0_OFS
                               EQU              0x00        ; PINSEL0  Address 
                                                            Offset
  389 00000000 00000004 
                       PINSEL1_OFS
                               EQU              0x04        ; PINSEL1  Address 
                                                            Offset
  390 00000000 00000008 
                       PINSEL2_OFS
                               EQU              0x08        ; PINSEL2  Address 
                                                            Offset
  391 00000000 0000000C 
                       PINSEL3_OFS
                               EQU              0x0C        ; PINSEL3  Address 
                                                            Offset
  392 00000000 00000010 
                       PINSEL4_OFS
                               EQU              0x10        ; PINSEL4  Address 
                                                            Offset
  393 00000000 00000014 
                       PINSEL5_OFS
                               EQU              0x14        ; PINSEL5  Address 
                                                            Offset
  394 00000000 00000018 
                       PINSEL6_OFS
                               EQU              0x18        ; PINSEL6  Address 
                                                            Offset
  395 00000000 0000001C 
                       PINSEL7_OFS
                               EQU              0x1C        ; PINSEL7  Address 
                                                            Offset
  396 00000000 00000020 
                       PINSEL8_OFS
                               EQU              0x20        ; PINSEL8  Address 
                                                            Offset
  397 00000000 00000024 
                       PINSEL9_OFS



ARM Macro Assembler    Page 12 


                               EQU              0x24        ; PINSEL9  Address 
                                                            Offset
  398 00000000 00000028 
                       PINSEL10_OFS
                               EQU              0x28        ; PINSEL10 Address 
                                                            Offset
  399 00000000         
  400 00000000         
  401 00000000         ;----------------------- External Memory Controller (EMC
                       ) Definitons -----------
  402 00000000         
  403 00000000 FFE08000 
                       EMC_BASE
                               EQU              0xFFE08000  ; EMC Base Address
  404 00000000         
  405 00000000 00000000 
                       EMC_CTRL_OFS
                               EQU              0x000       ; EMCControl
  406 00000000 00000004 
                       EMC_STAT_OFS
                               EQU              0x004       ; EMCStatus
  407 00000000 00000008 
                       EMC_CONFIG_OFS
                               EQU              0x008       ; EMCConfig
  408 00000000 00000200 
                       EMC_STA_CFG0_OFS
                               EQU              0x200       ; EMCStaticConfig0
  409 00000000 00000204 
                       EMC_STA_WWEN0_OFS
                               EQU              0x204       ; EMCStaticWaitWen0
                                                            
  410 00000000 00000208 
                       EMC_STA_WOEN0_OFS
                               EQU              0x208       ; EMCStaticWaitOen0
                                                            
  411 00000000 0000020C 
                       EMC_STA_WRD0_OFS
                               EQU              0x20C       ; EMCStaticWaitRd0
  412 00000000 00000210 
                       EMC_STA_WPAGE0_OFS
                               EQU              0x210       ; EMCStaticWaitPage
                                                            0
  413 00000000 00000214 
                       EMC_STA_WWR0_OFS
                               EQU              0x214       ; EMCStaticWaitWr0
  414 00000000 00000218 
                       EMC_STA_WTURN0_OFS
                               EQU              0x218       ; EMCStaticWaitTurn
                                                            0
  415 00000000 00000220 
                       EMC_STA_CFG1_OFS
                               EQU              0x220       ; EMCStaticConfig1
  416 00000000 00000224 
                       EMC_STA_WWEN1_OFS
                               EQU              0x224       ; EMCStaticWaitWen1
                                                            
  417 00000000 00000228 
                       EMC_STA_WOEN1_OFS
                               EQU              0x228       ; EMCStaticWaitOen1



ARM Macro Assembler    Page 13 


                                                            
  418 00000000 0000022C 
                       EMC_STA_WRD1_OFS
                               EQU              0x22C       ; EMCStaticWaitRd1
  419 00000000 00000230 
                       EMC_STA_WPAGE1_OFS
                               EQU              0x230       ; EMCStaticWaitPage
                                                            1
  420 00000000 00000234 
                       EMC_STA_WWR1_OFS
                               EQU              0x234       ; EMCStaticWaitWr1
  421 00000000 00000238 
                       EMC_STA_WTURN1_OFS
                               EQU              0x238       ; EMCStaticWaitTurn
                                                            1
  422 00000000 00000880 
                       EMC_STA_EXT_W_OFS
                               EQU              0x880       ; EMCStaticExtended
                                                            Wait
  423 00000000         
  424 00000000 00080000 
                       BUFEN_Const
                               EQU              (1 << 19)   ; Buffer enable bit
                                                            
  425 00000000 00000800 
                       EMC_PCONP_Const
                               EQU              (1 << 11)   ; PCONP val to enab
                                                            le power for EMC
  426 00000000         
  427 00000000         ; External Memory Pins definitions
  428 00000000         ; pin functions for external memory interfacing
  429 00000000 00005555 
                       EMC_PINSEL6_Val
                               EQU              0x00005555  ; D0 .. D7
  430 00000000 55555555 
                       EMC_PINSEL8_Val
                               EQU              0x55555555  ; A0 .. A15
  431 00000000 50090000 
                       EMC_PINSEL9_Val
                               EQU              0x50090000  ;     ; !OE, !WE (B
                                                            LS0 because of erra
                                                            ta), !CS0, !CS1
  432 00000000         
  433 00000000         ;//     External Memory Controller Setup (EMC) ---------
                       ------------------------
  434 00000000         ;// <e> External Memory Controller Setup (EMC)
  435 00000000 00000001 
                       EMC_SETUP
                               EQU              1
  436 00000000         
  437 00000000         ;//   <h> EMC Control Register (EMCControl)
  438 00000000         ;//     <i> Controls operation of the memory controller
  439 00000000         ;//     <o0.2> L: Low-power mode enable
  440 00000000         ;//     <o0.1> M: Address mirror enable
  441 00000000         ;//     <o0.0> E: EMC enable
  442 00000000         ;//   </h>
  443 00000000 00000001 
                       EMC_CTRL_Val
                               EQU              0x00000001



ARM Macro Assembler    Page 14 


  444 00000000         
  445 00000000         ;//   <h> EMC Configuration Register (EMCConfig)
  446 00000000         ;//     <o0.0> Endian mode
  447 00000000         ;//       <0=> Little-endian
  448 00000000         ;//       <1=> Big-endian
  449 00000000         ;//   </h>
  450 00000000 00000000 
                       EMC_CONFIG_Val
                               EQU              0x00000000
  451 00000000         
  452 00000000         ;//       Configure External Bus Behaviour for Static CS
                       0 Area -----------------
  453 00000000         ;//   <e> Configure External Bus Behaviour for Static CS
                       0 Area
  454 00000000 00000001 
                       EMC_STACS0_SETUP
                               EQU              1
  455 00000000         
  456 00000000         ;//     <h> Static Memory Configuration Register (EMCSta
                       ticConfig0)
  457 00000000         ;//       <i> Defines the configuration information for 
                       the static memory CS0
  458 00000000         ;//       <o0.20> WP: Write protect
  459 00000000         ;//       <o0.19> B: Write buffer enable
  460 00000000         ;//       <o0.8> EW: Extended wait enable
  461 00000000         ;//       <o0.6> PC: Chip select polarity
  462 00000000         ;//         <0=> Active LOW chip select
  463 00000000         ;//         <1=> Active HIGH chip select
  464 00000000         ;//       <o0.3> PM: Async page mode enable
  465 00000000         ;//       <o0.0..1> MW: Memory width
  466 00000000         ;//         <0=> 8 bit
  467 00000000         ;//         <1=> 16 bit
  468 00000000         ;//         <2=> 32 bit
  469 00000000         ;//     </h>
  470 00000000 00000000 
                       EMC_STA_CFG0_Val
                               EQU              0x00000000
  471 00000000         
  472 00000000         ;//     <h> Static Memory Write Enable Delay Register (E
                       MCStaticWaitWen0)
  473 00000000         ;//       <i> Selects the delay from CS0 to write enable
                       
  474 00000000         ;//       <o.0..3> WAITWEN: Wait write enable <1-16> <#-
                       1>
  475 00000000         ;//         <i> The delay is in CCLK cycles
  476 00000000         ;//     </h>
  477 00000000 00000002 
                       EMC_STA_WWEN0_Val
                               EQU              0x00000002
  478 00000000         
  479 00000000         ;//     <h> Static Memory Output Enable Delay register (
                       EMCStaticWaitOen0)
  480 00000000         ;//       <i> Selects the delay from CS0 or address chan
                       ge, whichever is later, to output enable
  481 00000000         ;//       <o.0..3> WAITOEN: Wait output enable <0-15>
  482 00000000         ;//         <i> The delay is in CCLK cycles
  483 00000000         ;//     </h>
  484 00000000 00000002 
                       EMC_STA_WOEN0_Val



ARM Macro Assembler    Page 15 


                               EQU              0x00000002
  485 00000000         
  486 00000000         ;//     <h> Static Memory Read Delay Register (EMCStatic
                       WaitRd0)
  487 00000000         ;//       <i> Selects the delay from CS0 to a read acces
                       s
  488 00000000         ;//       <o.0..4> WAITRD: Non-page mode read wait state
                       s or asynchronous page mode read first access wait state
                       s <1-32> <#-1>
  489 00000000         ;//         <i> The delay is in CCLK cycles
  490 00000000         ;//     </h>
  491 00000000 0000001F 
                       EMC_STA_WRD0_Val
                               EQU              0x0000001F
  492 00000000         
  493 00000000         ;//     <h> Static Memory Page Mode Read Delay Register 
                       (EMCStaticWaitPage0)
  494 00000000         ;//       <i> Selects the delay for asynchronous page mo
                       de sequential accesses for CS0
  495 00000000         ;//       <o.0..4> WAITPAGE: Asynchronous page mode read
                        after the first read wait states <1-32> <#-1>
  496 00000000         ;//         <i> The delay is in CCLK cycles
  497 00000000         ;//     </h>
  498 00000000 0000001F 
                       EMC_STA_WPAGE0_Val
                               EQU              0x0000001F
  499 00000000         
  500 00000000         ;//     <h> Static Memory Write Delay Register (EMCStati
                       cWaitWr0)
  501 00000000         ;//       <i> Selects the delay from CS0 to a write acce
                       ss
  502 00000000         ;//       <o.0..4> WAITWR: Write wait states <2-33> <#-2
                       >
  503 00000000         ;//         <i> The delay is in CCLK cycles
  504 00000000         ;//     </h>
  505 00000000 0000001F 
                       EMC_STA_WWR0_Val
                               EQU              0x0000001F
  506 00000000         
  507 00000000         ;//     <h> Static Memory Turn Round Delay Register (EMC
                       StaticWaitTurn0)
  508 00000000         ;//       <i> Selects the number of bus turnaround cycle
                       s for CS0
  509 00000000         ;//       <o.0..4> WAITTURN: Bus turnaround cycles <1-16
                       > <#-1>
  510 00000000         ;//         <i> The delay is in CCLK cycles
  511 00000000         ;//     </h>
  512 00000000 0000000F 
                       EMC_STA_WTURN0_Val
                               EQU              0x0000000F
  513 00000000         
  514 00000000         ;//   </e> End of Static Setup for Static CS0 Area
  515 00000000         
  516 00000000         ;//       Configure External Bus Behaviour for Static CS
                       1 Area -----------------
  517 00000000         ;//   <e> Configure External Bus Behaviour for Static CS
                       1 Area
  518 00000000 00000000 
                       EMC_STACS1_SETUP



ARM Macro Assembler    Page 16 


                               EQU              0
  519 00000000         
  520 00000000         ;//     <h> Static Memory Configuration Register (EMCSta
                       ticConfig1)
  521 00000000         ;//       <i> Defines the configuration information for 
                       the static memory CS1
  522 00000000         ;//       <o0.20> WP: Write protect
  523 00000000         ;//       <o0.19> B: Write buffer enable
  524 00000000         ;//       <o0.8> EW: Extended wait enable
  525 00000000         ;//       <o0.6> PC: Chip select polarity
  526 00000000         ;//         <0=> Active LOW chip select
  527 00000000         ;//         <1=> Active HIGH chip select
  528 00000000         ;//       <o0.3> PM: Async page mode enable
  529 00000000         ;//       <o0.0..1> MW: Memory width
  530 00000000         ;//         <0=> 8 bit
  531 00000000         ;//         <1=> 16 bit
  532 00000000         ;//         <2=> 32 bit
  533 00000000         ;//     </h>
  534 00000000 00000000 
                       EMC_STA_CFG1_Val
                               EQU              0x00000000
  535 00000000         
  536 00000000         ;//     <h> Static Memory Write Enable Delay Register (E
                       MCStaticWaitWen1)
  537 00000000         ;//       <i> Selects the delay from CS1 to write enable
                       
  538 00000000         ;//       <o.0..3> WAITWEN: Wait write enable <1-16> <#-
                       1>
  539 00000000         ;//         <i> The delay is in CCLK cycles
  540 00000000         ;//     </h>
  541 00000000 00000000 
                       EMC_STA_WWEN1_Val
                               EQU              0x00000000
  542 00000000         
  543 00000000         ;//     <h> Static Memory Output Enable Delay register (
                       EMCStaticWaitOen1)
  544 00000000         ;//       <i> Selects the delay from CS1 or address chan
                       ge, whichever is later, to output enable
  545 00000000         ;//       <o.0..3> WAITOEN: Wait output enable <0-15>
  546 00000000         ;//         <i> The delay is in CCLK cycles
  547 00000000         ;//     </h>
  548 00000000 00000000 
                       EMC_STA_WOEN1_Val
                               EQU              0x00000000
  549 00000000         
  550 00000000         ;//     <h> Static Memory Read Delay Register (EMCStatic
                       WaitRd1)
  551 00000000         ;//       <i> Selects the delay from CS1 to a read acces
                       s
  552 00000000         ;//       <o.0..4> WAITRD: Non-page mode read wait state
                       s or asynchronous page mode read first access wait state
                       s <1-32> <#-1>
  553 00000000         ;//         <i> The delay is in CCLK cycles
  554 00000000         ;//     </h>
  555 00000000 0000001F 
                       EMC_STA_WRD1_Val
                               EQU              0x0000001F
  556 00000000         
  557 00000000         ;//     <h> Static Memory Page Mode Read Delay Register 



ARM Macro Assembler    Page 17 


                       (EMCStaticWaitPage0)
  558 00000000         ;//       <i> Selects the delay for asynchronous page mo
                       de sequential accesses for CS1
  559 00000000         ;//       <o.0..4> WAITPAGE: Asynchronous page mode read
                        after the first read wait states <1-32> <#-1>
  560 00000000         ;//         <i> The delay is in CCLK cycles
  561 00000000         ;//     </h>
  562 00000000 0000001F 
                       EMC_STA_WPAGE1_Val
                               EQU              0x0000001F
  563 00000000         
  564 00000000         ;//     <h> Static Memory Write Delay Register (EMCStati
                       cWaitWr1)
  565 00000000         ;//       <i> Selects the delay from CS1 to a write acce
                       ss
  566 00000000         ;//       <o.0..4> WAITWR: Write wait states <2-33> <#-2
                       >
  567 00000000         ;//         <i> The delay is in CCLK cycles
  568 00000000         ;//     </h>
  569 00000000 0000001F 
                       EMC_STA_WWR1_Val
                               EQU              0x0000001F
  570 00000000         
  571 00000000         ;//     <h> Static Memory Turn Round Delay Register (EMC
                       StaticWaitTurn1)
  572 00000000         ;//       <i> Selects the number of bus turnaround cycle
                       s for CS1
  573 00000000         ;//       <o.0..4> WAITTURN: Bus turnaround cycles <1-16
                       > <#-1>
  574 00000000         ;//         <i> The delay is in CCLK cycles
  575 00000000         ;//     </h>
  576 00000000 0000000F 
                       EMC_STA_WTURN1_Val
                               EQU              0x0000000F
  577 00000000         
  578 00000000         ;//   </e> End of Static Setup for Static CS1 Area
  579 00000000         
  580 00000000         ;//   <h> Static Memory Extended Wait Register (EMCStati
                       cExtendedWait)
  581 00000000         ;//     <i> Time long static memory read and write trans
                       fers
  582 00000000         ;//     <o.0..9> EXTENDEDWAIT: Extended wait time out <1
                       -64><#-1>
  583 00000000         ;//       <i> The delay is in (16 * CCLK) cycles
  584 00000000         ;//   </h>
  585 00000000 00000000 
                       EMC_STA_EXT_W_Val
                               EQU              0x00000000
  586 00000000         
  587 00000000         ;// </e> End of EMC Setup
  588 00000000         
  589 00000000         
  590 00000000         ; Area Definition and Entry Point
  591 00000000         ;  Startup Code must be linked first at Address at which
                        it expects to run.
  592 00000000         
  593 00000000                 AREA             RESET, CODE, READONLY
  594 00000000                 ARM
  595 00000000         



ARM Macro Assembler    Page 18 


  596 00000000         
  597 00000000         ; Exception Vectors
  598 00000000         ;  Mapped to Address 0.
  599 00000000         ;  Absolute addressing mode must be used.
  600 00000000         ;  Dummy Handlers are implemented as infinite loops whic
                       h can be modified.
  601 00000000         
  602 00000000 E59FF018 
                       Vectors LDR              PC, Reset_Addr
  603 00000004 E59FF018        LDR              PC, Undef_Addr
  604 00000008 E59FF018        LDR              PC, SWI_Addr
  605 0000000C E59FF018        LDR              PC, PAbt_Addr
  606 00000010 E59FF018        LDR              PC, DAbt_Addr
  607 00000014 E1A00000        NOP                          ; Reserved Vector 
  608 00000018         ;               LDR     PC, IRQ_Addr
  609 00000018 E51FF120        LDR              PC, [PC, #-0x0120] ; Vector fro
                                                            m VicVectAddr
  610 0000001C E59FF018        LDR              PC, FIQ_Addr
  611 00000020         
  612 00000020 00000000 
                       Reset_Addr
                               DCD              Reset_Handler
  613 00000024 00000000 
                       Undef_Addr
                               DCD              Undef_Handler
  614 00000028 00000000 
                       SWI_Addr
                               DCD              SWI_Handler
  615 0000002C 00000000 
                       PAbt_Addr
                               DCD              PAbt_Handler
  616 00000030 00000000 
                       DAbt_Addr
                               DCD              DAbt_Handler
  617 00000034 00000000        DCD              0           ; Reserved Address 
                                                            
  618 00000038 00000000 
                       IRQ_Addr
                               DCD              IRQ_Handler
  619 0000003C 00000000 
                       FIQ_Addr
                               DCD              FIQ_Handler
  620 00000040         
  621 00000040 EAFFFFFE 
                       Undef_Handler
                               B                Undef_Handler
  622 00000044 EAFFFFFE 
                       SWI_Handler
                               B                SWI_Handler
  623 00000048 EAFFFFFE 
                       PAbt_Handler
                               B                PAbt_Handler
  624 0000004C EAFFFFFE 
                       DAbt_Handler
                               B                DAbt_Handler
  625 00000050 EAFFFFFE 
                       IRQ_Handler
                               B                IRQ_Handler
  626 00000054 EAFFFFFE 



ARM Macro Assembler    Page 19 


                       FIQ_Handler
                               B                FIQ_Handler
  627 00000058         
  628 00000058         
  629 00000058         ; Reset Handler
  630 00000058         
  631 00000058                 EXPORT           Reset_Handler
  632 00000058         Reset_Handler
  633 00000058         
  634 00000058         
  635 00000058         
  636 00000058         ; Clock Setup ------------------------------------------
                       ------------------------
  637 00000058         
  638 00000058                 IF               (:LNOT:(:DEF:NO_CLOCK_SETUP)):L
AND:(CLOCK_SETUP != 0)
  639 00000058 E59F019C        LDR              R0, =SCB_BASE
  640 0000005C E3A010AA        MOV              R1, #0xAA
  641 00000060 E3A02055        MOV              R2, #0x55
  642 00000064         
  643 00000064         ;  Configure and Enable PLL
  644 00000064 E3A03020        LDR              R3, =SCS_Val ; Enable main osci
                                                            llator
  645 00000068 E58031A0        STR              R3, [R0, #SCS_OFS]
  646 0000006C         
  647 0000006C                 IF               (SCS_Val:AND:OSCEN) != 0
  648 0000006C E59031A0 
                       OSC_Loop
                               LDR              R3, [R0, #SCS_OFS] ; Wait for m
                                                            ain osc stabilize
  649 00000070 E2133040        ANDS             R3, R3, #OSCSTAT
  650 00000074 0AFFFFFC        BEQ              OSC_Loop
  651 00000078                 ENDIF
  652 00000078         
  653 00000078 E3A03001        LDR              R3, =CLKSRCSEL_Val ; Select PLL
                                                             source clock
  654 0000007C E580310C        STR              R3, [R0, #CLKSRCSEL_OFS]
  655 00000080 E3A0300B        LDR              R3, =PLLCFG_Val
  656 00000084 E5803084        STR              R3, [R0, #PLLCFG_OFS]
  657 00000088 E580108C        STR              R1, [R0, #PLLFEED_OFS]
  658 0000008C E580208C        STR              R2, [R0, #PLLFEED_OFS]
  659 00000090 E3A03001        MOV              R3, #PLLCON_PLLE
  660 00000094 E5803080        STR              R3, [R0, #PLLCON_OFS]
  661 00000098 E580108C        STR              R1, [R0, #PLLFEED_OFS]
  662 0000009C E580208C        STR              R2, [R0, #PLLFEED_OFS]
  663 000000A0         
  664 000000A0         ;  Wait until PLL Locked
  665 000000A0 E5903088 
                       PLL_Loop
                               LDR              R3, [R0, #PLLSTAT_OFS]
  666 000000A4 E2133301        ANDS             R3, R3, #PLLSTAT_PLOCK
  667 000000A8 0AFFFFFC        BEQ              PLL_Loop
  668 000000AC         
  669 000000AC E5903088 
                       M_N_Lock
                               LDR              R3, [R0, #PLLSTAT_OFS]
  670 000000B0 E59F4148        LDR              R4, =(PLLSTAT_M:OR:PLLSTAT_N)
  671 000000B4 E0033004        AND              R3, R3, R4
  672 000000B8 E3A0400B        LDR              R4, =PLLCFG_Val



ARM Macro Assembler    Page 20 


  673 000000BC E0333004        EORS             R3, R3, R4
  674 000000C0 1AFFFFF9        BNE              M_N_Lock
  675 000000C4         
  676 000000C4         ;  Setup CPU clock divider
  677 000000C4 E3A03005        MOV              R3, #CCLKCFG_Val
  678 000000C8 E5803104        STR              R3, [R0, #CCLKCFG_OFS]
  679 000000CC         
  680 000000CC         ;  Setup USB clock divider
  681 000000CC E3A03005        LDR              R3, =USBCLKCFG_Val
  682 000000D0 E5803108        STR              R3, [R0, #USBCLKCFG_OFS]
  683 000000D4         
  684 000000D4         ;  Setup Peripheral Clock
  685 000000D4 E3A03000        LDR              R3, =PCLKSEL0_Val
  686 000000D8 E58031A8        STR              R3, [R0, #PCLKSEL0_OFS]
  687 000000DC E3A03000        LDR              R3, =PCLKSEL1_Val
  688 000000E0 E58031AC        STR              R3, [R0, #PCLKSEL1_OFS]
  689 000000E4         
  690 000000E4         ;  Switch to PLL Clock
  691 000000E4 E3A03003        MOV              R3, #(PLLCON_PLLE:OR:PLLCON_PLL
C)
  692 000000E8 E5803080        STR              R3, [R0, #PLLCON_OFS]
  693 000000EC E580108C        STR              R1, [R0, #PLLFEED_OFS]
  694 000000F0 E580208C        STR              R2, [R0, #PLLFEED_OFS]
  695 000000F4         
  696 000000F4 E59F4108        LDR              R4, =PCONP_Val ; Enable Periphe
                                                            ral Clocks
  697 000000F8 E58040C4        STR              R4, [R0, #PCONP_OFS]
  698 000000FC                 ENDIF                        ; CLOCK_SETUP
  699 000000FC         
  700 000000FC         
  701 000000FC         ; Setup Memory Accelerator Module ----------------------
                       ------------------------
  702 000000FC         
  703 000000FC                 IF               MAM_SETUP != 0
  704 000000FC E59F00F8        LDR              R0, =MAM_BASE
  705 00000100 E3A01004        MOV              R1, #MAMTIM_Val
  706 00000104 E5801004        STR              R1, [R0, #MAMTIM_OFS]
  707 00000108 E3A01002        MOV              R1, #MAMCR_Val
  708 0000010C E5801000        STR              R1, [R0, #MAMCR_OFS]
  709 00000110                 ENDIF                        ; MAM_SETUP
  710 00000110         
  711 00000110         
  712 00000110         ; Setup External Memory Controller ---------------------
                       ------------------------
  713 00000110         
  714 00000110                 IF               (:DEF:NO_EMC_SETUP):LOR:(EMC_SE
TUP != 0)
  715 00000110 E59F00F0        LDR              R0, =EMC_BASE
  716 00000114 E59F10E0        LDR              R1, =SCB_BASE
  717 00000118 E59F20EC        LDR              R2, =PCB_BASE
  718 0000011C         
  719 0000011C E59140C4        LDR              R4, [R1, #PCONP_OFS]
  720 00000120 E3844B02        ORR              R4, R4, #EMC_PCONP_Const 
                                                            ; Enable EMC clock
  721 00000124 E58140C4        STR              R4, [R1, #PCONP_OFS]
  722 00000128         
  723 00000128 E3A04001        LDR              R4, =EMC_CTRL_Val
  724 0000012C E5804000        STR              R4, [R0, #EMC_CTRL_OFS]
  725 00000130 E3A04000        LDR              R4, =EMC_CONFIG_Val



ARM Macro Assembler    Page 21 


  726 00000134 E5804008        STR              R4, [R0, #EMC_CONFIG_OFS]
  727 00000138         
  728 00000138         ;  Setup pin functions for External Bus functionality
  729 00000138 E59F40D0        LDR              R4, =EMC_PINSEL6_Val
  730 0000013C E5824018        STR              R4, [R2, #PINSEL6_OFS]
  731 00000140 E59F40CC        LDR              R4, =EMC_PINSEL8_Val
  732 00000144 E5824020        STR              R4, [R2, #PINSEL8_OFS]
  733 00000148 E59F40C8        LDR              R4, =EMC_PINSEL9_Val
  734 0000014C E5824024        STR              R4, [R2, #PINSEL9_OFS]
  735 00000150         
  736 00000150 E59F60C4        LDR              R6, =1200000 ; Number of cycles
                                                             to delay
  737 00000154 E2566001 
                       Wait_0  SUBS             R6, R6, #1  ; Delay ~100 ms @ p
                                                            roc clk 48 MHz
  738 00000158 1AFFFFFD        BNE              Wait_0
  739 0000015C         
  740 0000015C                 IF               (EMC_STACS0_SETUP != 0)
  741 0000015C E3A04000        LDR              R4, =EMC_STA_CFG0_Val
  742 00000160 E5804200        STR              R4, [R0, #EMC_STA_CFG0_OFS]
  743 00000164 E3A04002        LDR              R4, =EMC_STA_WWEN0_Val
  744 00000168 E5804204        STR              R4, [R0, #EMC_STA_WWEN0_OFS]
  745 0000016C E3A04002        LDR              R4, =EMC_STA_WOEN0_Val
  746 00000170 E5804208        STR              R4, [R0, #EMC_STA_WOEN0_OFS]
  747 00000174 E3A0401F        LDR              R4, =EMC_STA_WRD0_Val
  748 00000178 E580420C        STR              R4, [R0, #EMC_STA_WRD0_OFS]
  749 0000017C E3A0401F        LDR              R4, =EMC_STA_WPAGE0_Val
  750 00000180 E5804210        STR              R4, [R0, #EMC_STA_WPAGE0_OFS]
  751 00000184 E3A0401F        LDR              R4, =EMC_STA_WWR0_Val
  752 00000188 E5804214        STR              R4, [R0, #EMC_STA_WWR0_OFS]
  753 0000018C E3A0400F        LDR              R4, =EMC_STA_WTURN0_Val
  754 00000190 E5804218        STR              R4, [R0, #EMC_STA_WTURN0_OFS]
  755 00000194                 ENDIF
  756 00000194         
  757 00000194                 IF               (EMC_STACS1_SETUP != 0)
  772                          ENDIF
  773 00000194         
  774 00000194 E59F6084        LDR              R6, =120000 ; Number of cycles 
                                                            to delay
  775 00000198 E2566001 
                       Wait_1  SUBS             R6, R6, #1  ; Delay ~10 ms @ pr
                                                            oc clk 48 MHz
  776 0000019C 1AFFFFFD        BNE              Wait_1
  777 000001A0         
  778 000001A0 E3A04000        LDR              R4, =EMC_STA_EXT_W_Val
  779 000001A4 E3A05D22        LDR              R5, =EMC_STA_EXT_W_OFS
  780 000001A8 E0855000        ADD              R5, R5, R0
  781 000001AC E5854000        STR              R4, [R5, #0]
  782 000001B0         
  783 000001B0                 ENDIF                        ; EMC_SETUP
  784 000001B0         
  785 000001B0         
  786 000001B0         ; Copy Exception Vectors to Internal RAM ---------------
                       ------------------------
  787 000001B0         
  788 000001B0                 IF               :DEF:RAM_INTVEC
  795                          ENDIF
  796 000001B0         
  797 000001B0         



ARM Macro Assembler    Page 22 


  798 000001B0         ; Memory Mapping (when Interrupt Vectors are in RAM) ---
                       ------------------------
  799 000001B0         
  800 000001B0 E01FC040 
                       MEMMAP  EQU              0xE01FC040  ; Memory Mapping Co
                                                            ntrol
  801 000001B0                 IF               :DEF:REMAP
  811                          ENDIF
  812 000001B0         
  813 000001B0         
  814 000001B0         ; Setup Stack for each mode ----------------------------
                       ------------------------
  815 000001B0         
  816 000001B0 E59F006C        LDR              R0, =Stack_Top
  817 000001B4         
  818 000001B4         ;  Enter Undefined Instruction Mode and set its Stack Po
                       inter
  819 000001B4 E321F0DB        MSR              CPSR_c, #Mode_UND:OR:I_Bit:OR:F
_Bit
  820 000001B8 E1A0D000        MOV              SP, R0
  821 000001BC E2400000        SUB              R0, R0, #UND_Stack_Size
  822 000001C0         
  823 000001C0         ;  Enter Abort Mode and set its Stack Pointer
  824 000001C0 E321F0D7        MSR              CPSR_c, #Mode_ABT:OR:I_Bit:OR:F
_Bit
  825 000001C4 E1A0D000        MOV              SP, R0
  826 000001C8 E2400000        SUB              R0, R0, #ABT_Stack_Size
  827 000001CC         
  828 000001CC         ;  Enter FIQ Mode and set its Stack Pointer
  829 000001CC E321F0D1        MSR              CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F
_Bit
  830 000001D0 E1A0D000        MOV              SP, R0
  831 000001D4 E2400000        SUB              R0, R0, #FIQ_Stack_Size
  832 000001D8         
  833 000001D8         ;  Enter IRQ Mode and set its Stack Pointer
  834 000001D8 E321F0D2        MSR              CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F
_Bit
  835 000001DC E1A0D000        MOV              SP, R0
  836 000001E0 E2400C01        SUB              R0, R0, #IRQ_Stack_Size
  837 000001E4         
  838 000001E4         ;  Enter Supervisor Mode and set its Stack Pointer
  839 000001E4 E321F0D3        MSR              CPSR_c, #Mode_SVC:OR:I_Bit:OR:F
_Bit
  840 000001E8 E1A0D000        MOV              SP, R0
  841 000001EC E2400008        SUB              R0, R0, #SVC_Stack_Size
  842 000001F0         
  843 000001F0         ;  Enter User Mode and set its Stack Pointer
  844 000001F0 E321F010        MSR              CPSR_c, #Mode_USR
  845 000001F4                 IF               :DEF:__MICROLIB
  846 000001F4         
  847 000001F4                 EXPORT           __initial_sp
  848 000001F4         
  849 000001F4                 ELSE
  854                          ENDIF
  855 000001F4         
  856 000001F4         
  857 000001F4         ; Enter the C code -------------------------------------
                       ------------------------
  858 000001F4         



ARM Macro Assembler    Page 23 


  859 000001F4                 IMPORT           __main
  860 000001F4 E59F002C        LDR              R0, =__main
  861 000001F8 E12FFF10        BX               R0
  862 000001FC         
  863 000001FC         
  864 000001FC                 IF               :DEF:__MICROLIB
  865 000001FC         
  866 000001FC                 EXPORT           __heap_base
  867 000001FC                 EXPORT           __heap_limit
  868 000001FC         
  869 000001FC                 ELSE
  882                          ENDIF
  883 000001FC         
  884 000001FC         
  885 000001FC                 END
              E01FC000 
              00FF7FFF 
              04280FDE 
              FFE08000 
              E002C000 
              00005555 
              55555555 
              50090000 
              00124F80 
              0001D4C0 
              00000000 
              00000000 
Command Line: --debug --xref --apcs=interwork --depend=LPC2300.d -oLPC2300.o -I
C:\Universidad\Keil\ARM\RV31\INC -IC:\Universidad\Keil\ARM\CMSIS\Include -IC:\U
niversidad\Keil\ARM\Inc\Philips --predefine="__EVAL SETA 1" --predefine="__MICR
OLIB SETA 1" --list=LPC2300.lst LPC2300.s



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

STACK 00000000

Symbol: STACK
   Definitions
      At line 92 in file LPC2300.s
   Uses
      None
Comment: STACK unused
Stack_Mem 00000000

Symbol: Stack_Mem
   Definitions
      At line 94 in file LPC2300.s
   Uses
      None
Comment: Stack_Mem unused
Stack_Top 00000508

Symbol: Stack_Top
   Definitions
      At line 97 in file LPC2300.s
   Uses
      At line 816 in file LPC2300.s
Comment: Stack_Top used once
__initial_sp 00000400

Symbol: __initial_sp
   Definitions
      At line 95 in file LPC2300.s
   Uses
      At line 847 in file LPC2300.s
Comment: __initial_sp used once
4 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

HEAP 00000000

Symbol: HEAP
   Definitions
      At line 106 in file LPC2300.s
   Uses
      None
Comment: HEAP unused
Heap_Mem 00000000

Symbol: Heap_Mem
   Definitions
      At line 108 in file LPC2300.s
   Uses
      None
Comment: Heap_Mem unused
__heap_base 00000000

Symbol: __heap_base
   Definitions
      At line 107 in file LPC2300.s
   Uses
      At line 866 in file LPC2300.s
Comment: __heap_base used once
__heap_limit 00000000

Symbol: __heap_limit
   Definitions
      At line 109 in file LPC2300.s
   Uses
      At line 867 in file LPC2300.s
Comment: __heap_limit used once
4 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

DAbt_Addr 00000030

Symbol: DAbt_Addr
   Definitions
      At line 616 in file LPC2300.s
   Uses
      At line 606 in file LPC2300.s
Comment: DAbt_Addr used once
DAbt_Handler 0000004C

Symbol: DAbt_Handler
   Definitions
      At line 624 in file LPC2300.s
   Uses
      At line 616 in file LPC2300.s
      At line 624 in file LPC2300.s

FIQ_Addr 0000003C

Symbol: FIQ_Addr
   Definitions
      At line 619 in file LPC2300.s
   Uses
      At line 610 in file LPC2300.s
Comment: FIQ_Addr used once
FIQ_Handler 00000054

Symbol: FIQ_Handler
   Definitions
      At line 626 in file LPC2300.s
   Uses
      At line 619 in file LPC2300.s
      At line 626 in file LPC2300.s

IRQ_Addr 00000038

Symbol: IRQ_Addr
   Definitions
      At line 618 in file LPC2300.s
   Uses
      None
Comment: IRQ_Addr unused
IRQ_Handler 00000050

Symbol: IRQ_Handler
   Definitions
      At line 625 in file LPC2300.s
   Uses
      At line 618 in file LPC2300.s
      At line 625 in file LPC2300.s

M_N_Lock 000000AC

Symbol: M_N_Lock
   Definitions
      At line 669 in file LPC2300.s
   Uses
      At line 674 in file LPC2300.s
Comment: M_N_Lock used once



ARM Macro Assembler    Page 2 Alphabetic symbol ordering
Relocatable symbols

OSC_Loop 0000006C

Symbol: OSC_Loop
   Definitions
      At line 648 in file LPC2300.s
   Uses
      At line 650 in file LPC2300.s
Comment: OSC_Loop used once
PAbt_Addr 0000002C

Symbol: PAbt_Addr
   Definitions
      At line 615 in file LPC2300.s
   Uses
      At line 605 in file LPC2300.s
Comment: PAbt_Addr used once
PAbt_Handler 00000048

Symbol: PAbt_Handler
   Definitions
      At line 623 in file LPC2300.s
   Uses
      At line 615 in file LPC2300.s
      At line 623 in file LPC2300.s

PLL_Loop 000000A0

Symbol: PLL_Loop
   Definitions
      At line 665 in file LPC2300.s
   Uses
      At line 667 in file LPC2300.s
Comment: PLL_Loop used once
RESET 00000000

Symbol: RESET
   Definitions
      At line 593 in file LPC2300.s
   Uses
      None
Comment: RESET unused
Reset_Addr 00000020

Symbol: Reset_Addr
   Definitions
      At line 612 in file LPC2300.s
   Uses
      At line 602 in file LPC2300.s
Comment: Reset_Addr used once
Reset_Handler 00000058

Symbol: Reset_Handler
   Definitions
      At line 632 in file LPC2300.s
   Uses
      At line 612 in file LPC2300.s
      At line 631 in file LPC2300.s

SWI_Addr 00000028



ARM Macro Assembler    Page 3 Alphabetic symbol ordering
Relocatable symbols


Symbol: SWI_Addr
   Definitions
      At line 614 in file LPC2300.s
   Uses
      At line 604 in file LPC2300.s
Comment: SWI_Addr used once
SWI_Handler 00000044

Symbol: SWI_Handler
   Definitions
      At line 622 in file LPC2300.s
   Uses
      At line 614 in file LPC2300.s
      At line 622 in file LPC2300.s

Undef_Addr 00000024

Symbol: Undef_Addr
   Definitions
      At line 613 in file LPC2300.s
   Uses
      At line 603 in file LPC2300.s
Comment: Undef_Addr used once
Undef_Handler 00000040

Symbol: Undef_Handler
   Definitions
      At line 621 in file LPC2300.s
   Uses
      At line 613 in file LPC2300.s
      At line 621 in file LPC2300.s

Vectors 00000000

Symbol: Vectors
   Definitions
      At line 602 in file LPC2300.s
   Uses
      None
Comment: Vectors unused
Wait_0 00000154

Symbol: Wait_0
   Definitions
      At line 737 in file LPC2300.s
   Uses
      At line 738 in file LPC2300.s
Comment: Wait_0 used once
Wait_1 00000198

Symbol: Wait_1
   Definitions
      At line 775 in file LPC2300.s
   Uses
      At line 776 in file LPC2300.s
Comment: Wait_1 used once
21 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Absolute symbols

ABT_Stack_Size 00000000

Symbol: ABT_Stack_Size
   Definitions
      At line 84 in file LPC2300.s
   Uses
      At line 90 in file LPC2300.s
      At line 826 in file LPC2300.s

BUFEN_Const 00080000

Symbol: BUFEN_Const
   Definitions
      At line 424 in file LPC2300.s
   Uses
      None
Comment: BUFEN_Const unused
CCLKCFG_OFS 00000104

Symbol: CCLKCFG_OFS
   Definitions
      At line 119 in file LPC2300.s
   Uses
      At line 678 in file LPC2300.s
Comment: CCLKCFG_OFS used once
CCLKCFG_Val 00000005

Symbol: CCLKCFG_Val
   Definitions
      At line 357 in file LPC2300.s
   Uses
      At line 677 in file LPC2300.s
Comment: CCLKCFG_Val used once
CLKSRCSEL_OFS 0000010C

Symbol: CLKSRCSEL_OFS
   Definitions
      At line 121 in file LPC2300.s
   Uses
      At line 654 in file LPC2300.s
Comment: CLKSRCSEL_OFS used once
CLKSRCSEL_Val 00000001

Symbol: CLKSRCSEL_Val
   Definitions
      At line 355 in file LPC2300.s
   Uses
      At line 653 in file LPC2300.s
Comment: CLKSRCSEL_Val used once
CLOCK_SETUP 00000001

Symbol: CLOCK_SETUP
   Definitions
      At line 353 in file LPC2300.s
   Uses
      At line 638 in file LPC2300.s
Comment: CLOCK_SETUP used once
EMC_BASE FFE08000




ARM Macro Assembler    Page 2 Alphabetic symbol ordering
Absolute symbols

Symbol: EMC_BASE
   Definitions
      At line 403 in file LPC2300.s
   Uses
      At line 715 in file LPC2300.s
Comment: EMC_BASE used once
EMC_CONFIG_OFS 00000008

Symbol: EMC_CONFIG_OFS
   Definitions
      At line 407 in file LPC2300.s
   Uses
      At line 726 in file LPC2300.s
Comment: EMC_CONFIG_OFS used once
EMC_CONFIG_Val 00000000

Symbol: EMC_CONFIG_Val
   Definitions
      At line 450 in file LPC2300.s
   Uses
      At line 725 in file LPC2300.s
Comment: EMC_CONFIG_Val used once
EMC_CTRL_OFS 00000000

Symbol: EMC_CTRL_OFS
   Definitions
      At line 405 in file LPC2300.s
   Uses
      At line 724 in file LPC2300.s
Comment: EMC_CTRL_OFS used once
EMC_CTRL_Val 00000001

Symbol: EMC_CTRL_Val
   Definitions
      At line 443 in file LPC2300.s
   Uses
      At line 723 in file LPC2300.s
Comment: EMC_CTRL_Val used once
EMC_PCONP_Const 00000800

Symbol: EMC_PCONP_Const
   Definitions
      At line 425 in file LPC2300.s
   Uses
      At line 720 in file LPC2300.s
Comment: EMC_PCONP_Const used once
EMC_PINSEL6_Val 00005555

Symbol: EMC_PINSEL6_Val
   Definitions
      At line 429 in file LPC2300.s
   Uses
      At line 729 in file LPC2300.s
Comment: EMC_PINSEL6_Val used once
EMC_PINSEL8_Val 55555555

Symbol: EMC_PINSEL8_Val
   Definitions
      At line 430 in file LPC2300.s



ARM Macro Assembler    Page 3 Alphabetic symbol ordering
Absolute symbols

   Uses
      At line 731 in file LPC2300.s
Comment: EMC_PINSEL8_Val used once
EMC_PINSEL9_Val 50090000

Symbol: EMC_PINSEL9_Val
   Definitions
      At line 431 in file LPC2300.s
   Uses
      At line 733 in file LPC2300.s
Comment: EMC_PINSEL9_Val used once
EMC_SETUP 00000001

Symbol: EMC_SETUP
   Definitions
      At line 435 in file LPC2300.s
   Uses
      At line 714 in file LPC2300.s
Comment: EMC_SETUP used once
EMC_STACS0_SETUP 00000001

Symbol: EMC_STACS0_SETUP
   Definitions
      At line 454 in file LPC2300.s
   Uses
      At line 740 in file LPC2300.s
Comment: EMC_STACS0_SETUP used once
EMC_STACS1_SETUP 00000000

Symbol: EMC_STACS1_SETUP
   Definitions
      At line 518 in file LPC2300.s
   Uses
      At line 757 in file LPC2300.s
Comment: EMC_STACS1_SETUP used once
EMC_STAT_OFS 00000004

Symbol: EMC_STAT_OFS
   Definitions
      At line 406 in file LPC2300.s
   Uses
      None
Comment: EMC_STAT_OFS unused
EMC_STA_CFG0_OFS 00000200

Symbol: EMC_STA_CFG0_OFS
   Definitions
      At line 408 in file LPC2300.s
   Uses
      At line 742 in file LPC2300.s
Comment: EMC_STA_CFG0_OFS used once
EMC_STA_CFG0_Val 00000000

Symbol: EMC_STA_CFG0_Val
   Definitions
      At line 470 in file LPC2300.s
   Uses
      At line 741 in file LPC2300.s
Comment: EMC_STA_CFG0_Val used once



ARM Macro Assembler    Page 4 Alphabetic symbol ordering
Absolute symbols

EMC_STA_CFG1_OFS 00000220

Symbol: EMC_STA_CFG1_OFS
   Definitions
      At line 415 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_CFG1_OFS unused
EMC_STA_CFG1_Val 00000000

Symbol: EMC_STA_CFG1_Val
   Definitions
      At line 534 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_CFG1_Val unused
EMC_STA_EXT_W_OFS 00000880

Symbol: EMC_STA_EXT_W_OFS
   Definitions
      At line 422 in file LPC2300.s
   Uses
      At line 779 in file LPC2300.s
Comment: EMC_STA_EXT_W_OFS used once
EMC_STA_EXT_W_Val 00000000

Symbol: EMC_STA_EXT_W_Val
   Definitions
      At line 585 in file LPC2300.s
   Uses
      At line 778 in file LPC2300.s
Comment: EMC_STA_EXT_W_Val used once
EMC_STA_WOEN0_OFS 00000208

Symbol: EMC_STA_WOEN0_OFS
   Definitions
      At line 410 in file LPC2300.s
   Uses
      At line 746 in file LPC2300.s
Comment: EMC_STA_WOEN0_OFS used once
EMC_STA_WOEN0_Val 00000002

Symbol: EMC_STA_WOEN0_Val
   Definitions
      At line 484 in file LPC2300.s
   Uses
      At line 745 in file LPC2300.s
Comment: EMC_STA_WOEN0_Val used once
EMC_STA_WOEN1_OFS 00000228

Symbol: EMC_STA_WOEN1_OFS
   Definitions
      At line 417 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_WOEN1_OFS unused
EMC_STA_WOEN1_Val 00000000

Symbol: EMC_STA_WOEN1_Val



ARM Macro Assembler    Page 5 Alphabetic symbol ordering
Absolute symbols

   Definitions
      At line 548 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_WOEN1_Val unused
EMC_STA_WPAGE0_OFS 00000210

Symbol: EMC_STA_WPAGE0_OFS
   Definitions
      At line 412 in file LPC2300.s
   Uses
      At line 750 in file LPC2300.s
Comment: EMC_STA_WPAGE0_OFS used once
EMC_STA_WPAGE0_Val 0000001F

Symbol: EMC_STA_WPAGE0_Val
   Definitions
      At line 498 in file LPC2300.s
   Uses
      At line 749 in file LPC2300.s
Comment: EMC_STA_WPAGE0_Val used once
EMC_STA_WPAGE1_OFS 00000230

Symbol: EMC_STA_WPAGE1_OFS
   Definitions
      At line 419 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_WPAGE1_OFS unused
EMC_STA_WPAGE1_Val 0000001F

Symbol: EMC_STA_WPAGE1_Val
   Definitions
      At line 562 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_WPAGE1_Val unused
EMC_STA_WRD0_OFS 0000020C

Symbol: EMC_STA_WRD0_OFS
   Definitions
      At line 411 in file LPC2300.s
   Uses
      At line 748 in file LPC2300.s
Comment: EMC_STA_WRD0_OFS used once
EMC_STA_WRD0_Val 0000001F

Symbol: EMC_STA_WRD0_Val
   Definitions
      At line 491 in file LPC2300.s
   Uses
      At line 747 in file LPC2300.s
Comment: EMC_STA_WRD0_Val used once
EMC_STA_WRD1_OFS 0000022C

Symbol: EMC_STA_WRD1_OFS
   Definitions
      At line 418 in file LPC2300.s
   Uses



ARM Macro Assembler    Page 6 Alphabetic symbol ordering
Absolute symbols

      None
Comment: EMC_STA_WRD1_OFS unused
EMC_STA_WRD1_Val 0000001F

Symbol: EMC_STA_WRD1_Val
   Definitions
      At line 555 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_WRD1_Val unused
EMC_STA_WTURN0_OFS 00000218

Symbol: EMC_STA_WTURN0_OFS
   Definitions
      At line 414 in file LPC2300.s
   Uses
      At line 754 in file LPC2300.s
Comment: EMC_STA_WTURN0_OFS used once
EMC_STA_WTURN0_Val 0000000F

Symbol: EMC_STA_WTURN0_Val
   Definitions
      At line 512 in file LPC2300.s
   Uses
      At line 753 in file LPC2300.s
Comment: EMC_STA_WTURN0_Val used once
EMC_STA_WTURN1_OFS 00000238

Symbol: EMC_STA_WTURN1_OFS
   Definitions
      At line 421 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_WTURN1_OFS unused
EMC_STA_WTURN1_Val 0000000F

Symbol: EMC_STA_WTURN1_Val
   Definitions
      At line 576 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_WTURN1_Val unused
EMC_STA_WWEN0_OFS 00000204

Symbol: EMC_STA_WWEN0_OFS
   Definitions
      At line 409 in file LPC2300.s
   Uses
      At line 744 in file LPC2300.s
Comment: EMC_STA_WWEN0_OFS used once
EMC_STA_WWEN0_Val 00000002

Symbol: EMC_STA_WWEN0_Val
   Definitions
      At line 477 in file LPC2300.s
   Uses
      At line 743 in file LPC2300.s
Comment: EMC_STA_WWEN0_Val used once
EMC_STA_WWEN1_OFS 00000224



ARM Macro Assembler    Page 7 Alphabetic symbol ordering
Absolute symbols


Symbol: EMC_STA_WWEN1_OFS
   Definitions
      At line 416 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_WWEN1_OFS unused
EMC_STA_WWEN1_Val 00000000

Symbol: EMC_STA_WWEN1_Val
   Definitions
      At line 541 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_WWEN1_Val unused
EMC_STA_WWR0_OFS 00000214

Symbol: EMC_STA_WWR0_OFS
   Definitions
      At line 413 in file LPC2300.s
   Uses
      At line 752 in file LPC2300.s
Comment: EMC_STA_WWR0_OFS used once
EMC_STA_WWR0_Val 0000001F

Symbol: EMC_STA_WWR0_Val
   Definitions
      At line 505 in file LPC2300.s
   Uses
      At line 751 in file LPC2300.s
Comment: EMC_STA_WWR0_Val used once
EMC_STA_WWR1_OFS 00000234

Symbol: EMC_STA_WWR1_OFS
   Definitions
      At line 420 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_WWR1_OFS unused
EMC_STA_WWR1_Val 0000001F

Symbol: EMC_STA_WWR1_Val
   Definitions
      At line 569 in file LPC2300.s
   Uses
      None
Comment: EMC_STA_WWR1_Val unused
EXTMEM_BASE 80000000

Symbol: EXTMEM_BASE
   Definitions
      At line 64 in file LPC2300.s
   Uses
      None
Comment: EXTMEM_BASE unused
FIQ_Stack_Size 00000000

Symbol: FIQ_Stack_Size
   Definitions



ARM Macro Assembler    Page 8 Alphabetic symbol ordering
Absolute symbols

      At line 85 in file LPC2300.s
   Uses
      At line 90 in file LPC2300.s
      At line 831 in file LPC2300.s

FLASH_BASE 00000000

Symbol: FLASH_BASE
   Definitions
      At line 62 in file LPC2300.s
   Uses
      None
Comment: FLASH_BASE unused
F_Bit 00000040

Symbol: F_Bit
   Definitions
      At line 56 in file LPC2300.s
   Uses
      At line 819 in file LPC2300.s
      At line 824 in file LPC2300.s
      At line 829 in file LPC2300.s
      At line 834 in file LPC2300.s
      At line 839 in file LPC2300.s

Heap_Size 00000000

Symbol: Heap_Size
   Definitions
      At line 104 in file LPC2300.s
   Uses
      At line 108 in file LPC2300.s
Comment: Heap_Size used once
IRQ_Stack_Size 00000100

Symbol: IRQ_Stack_Size
   Definitions
      At line 86 in file LPC2300.s
   Uses
      At line 90 in file LPC2300.s
      At line 836 in file LPC2300.s

ISR_Stack_Size 00000108

Symbol: ISR_Stack_Size
   Definitions
      At line 90 in file LPC2300.s
   Uses
      At line 95 in file LPC2300.s
Comment: ISR_Stack_Size used once
I_Bit 00000080

Symbol: I_Bit
   Definitions
      At line 55 in file LPC2300.s
   Uses
      At line 819 in file LPC2300.s
      At line 824 in file LPC2300.s
      At line 829 in file LPC2300.s



ARM Macro Assembler    Page 9 Alphabetic symbol ordering
Absolute symbols

      At line 834 in file LPC2300.s
      At line 839 in file LPC2300.s

MAMCR_OFS 00000000

Symbol: MAMCR_OFS
   Definitions
      At line 366 in file LPC2300.s
   Uses
      At line 708 in file LPC2300.s
Comment: MAMCR_OFS used once
MAMCR_Val 00000002

Symbol: MAMCR_Val
   Definitions
      At line 381 in file LPC2300.s
   Uses
      At line 707 in file LPC2300.s
Comment: MAMCR_Val used once
MAMTIM_OFS 00000004

Symbol: MAMTIM_OFS
   Definitions
      At line 367 in file LPC2300.s
   Uses
      At line 706 in file LPC2300.s
Comment: MAMTIM_OFS used once
MAMTIM_Val 00000004

Symbol: MAMTIM_Val
   Definitions
      At line 382 in file LPC2300.s
   Uses
      At line 705 in file LPC2300.s
Comment: MAMTIM_Val used once
MAM_BASE E01FC000

Symbol: MAM_BASE
   Definitions
      At line 365 in file LPC2300.s
   Uses
      At line 704 in file LPC2300.s
Comment: MAM_BASE used once
MAM_SETUP 00000001

Symbol: MAM_SETUP
   Definitions
      At line 380 in file LPC2300.s
   Uses
      At line 703 in file LPC2300.s
Comment: MAM_SETUP used once
MEMMAP E01FC040

Symbol: MEMMAP
   Definitions
      At line 800 in file LPC2300.s
   Uses
      None
Comment: MEMMAP unused



ARM Macro Assembler    Page 10 Alphabetic symbol ordering
Absolute symbols

Mode_ABT 00000017

Symbol: Mode_ABT
   Definitions
      At line 51 in file LPC2300.s
   Uses
      At line 824 in file LPC2300.s
Comment: Mode_ABT used once
Mode_FIQ 00000011

Symbol: Mode_FIQ
   Definitions
      At line 48 in file LPC2300.s
   Uses
      At line 829 in file LPC2300.s
Comment: Mode_FIQ used once
Mode_IRQ 00000012

Symbol: Mode_IRQ
   Definitions
      At line 49 in file LPC2300.s
   Uses
      At line 834 in file LPC2300.s
Comment: Mode_IRQ used once
Mode_SVC 00000013

Symbol: Mode_SVC
   Definitions
      At line 50 in file LPC2300.s
   Uses
      At line 839 in file LPC2300.s
Comment: Mode_SVC used once
Mode_SYS 0000001F

Symbol: Mode_SYS
   Definitions
      At line 53 in file LPC2300.s
   Uses
      None
Comment: Mode_SYS unused
Mode_UND 0000001B

Symbol: Mode_UND
   Definitions
      At line 52 in file LPC2300.s
   Uses
      At line 819 in file LPC2300.s
Comment: Mode_UND used once
Mode_USR 00000010

Symbol: Mode_USR
   Definitions
      At line 47 in file LPC2300.s
   Uses
      At line 844 in file LPC2300.s
Comment: Mode_USR used once
OSCEN 00000020

Symbol: OSCEN



ARM Macro Assembler    Page 11 Alphabetic symbol ordering
Absolute symbols

   Definitions
      At line 131 in file LPC2300.s
   Uses
      At line 647 in file LPC2300.s
Comment: OSCEN used once
OSCRANGE 00000010

Symbol: OSCRANGE
   Definitions
      At line 130 in file LPC2300.s
   Uses
      None
Comment: OSCRANGE unused
OSCSTAT 00000040

Symbol: OSCSTAT
   Definitions
      At line 132 in file LPC2300.s
   Uses
      At line 649 in file LPC2300.s
Comment: OSCSTAT used once
PCB_BASE E002C000

Symbol: PCB_BASE
   Definitions
      At line 387 in file LPC2300.s
   Uses
      At line 717 in file LPC2300.s
Comment: PCB_BASE used once
PCLKSEL0_OFS 000001A8

Symbol: PCLKSEL0_OFS
   Definitions
      At line 123 in file LPC2300.s
   Uses
      At line 686 in file LPC2300.s
Comment: PCLKSEL0_OFS used once
PCLKSEL0_Val 00000000

Symbol: PCLKSEL0_Val
   Definitions
      At line 359 in file LPC2300.s
   Uses
      At line 685 in file LPC2300.s
Comment: PCLKSEL0_Val used once
PCLKSEL1_OFS 000001AC

Symbol: PCLKSEL1_OFS
   Definitions
      At line 124 in file LPC2300.s
   Uses
      At line 688 in file LPC2300.s
Comment: PCLKSEL1_OFS used once
PCLKSEL1_Val 00000000

Symbol: PCLKSEL1_Val
   Definitions
      At line 360 in file LPC2300.s
   Uses



ARM Macro Assembler    Page 12 Alphabetic symbol ordering
Absolute symbols

      At line 687 in file LPC2300.s
Comment: PCLKSEL1_Val used once
PCONP_OFS 000000C4

Symbol: PCONP_OFS
   Definitions
      At line 127 in file LPC2300.s
   Uses
      At line 697 in file LPC2300.s
      At line 719 in file LPC2300.s
      At line 721 in file LPC2300.s

PCONP_Val 04280FDE

Symbol: PCONP_Val
   Definitions
      At line 361 in file LPC2300.s
   Uses
      At line 696 in file LPC2300.s
Comment: PCONP_Val used once
PCON_OFS 000000C0

Symbol: PCON_OFS
   Definitions
      At line 126 in file LPC2300.s
   Uses
      None
Comment: PCON_OFS unused
PINSEL0_OFS 00000000

Symbol: PINSEL0_OFS
   Definitions
      At line 388 in file LPC2300.s
   Uses
      None
Comment: PINSEL0_OFS unused
PINSEL10_OFS 00000028

Symbol: PINSEL10_OFS
   Definitions
      At line 398 in file LPC2300.s
   Uses
      None
Comment: PINSEL10_OFS unused
PINSEL1_OFS 00000004

Symbol: PINSEL1_OFS
   Definitions
      At line 389 in file LPC2300.s
   Uses
      None
Comment: PINSEL1_OFS unused
PINSEL2_OFS 00000008

Symbol: PINSEL2_OFS
   Definitions
      At line 390 in file LPC2300.s
   Uses
      None



ARM Macro Assembler    Page 13 Alphabetic symbol ordering
Absolute symbols

Comment: PINSEL2_OFS unused
PINSEL3_OFS 0000000C

Symbol: PINSEL3_OFS
   Definitions
      At line 391 in file LPC2300.s
   Uses
      None
Comment: PINSEL3_OFS unused
PINSEL4_OFS 00000010

Symbol: PINSEL4_OFS
   Definitions
      At line 392 in file LPC2300.s
   Uses
      None
Comment: PINSEL4_OFS unused
PINSEL5_OFS 00000014

Symbol: PINSEL5_OFS
   Definitions
      At line 393 in file LPC2300.s
   Uses
      None
Comment: PINSEL5_OFS unused
PINSEL6_OFS 00000018

Symbol: PINSEL6_OFS
   Definitions
      At line 394 in file LPC2300.s
   Uses
      At line 730 in file LPC2300.s
Comment: PINSEL6_OFS used once
PINSEL7_OFS 0000001C

Symbol: PINSEL7_OFS
   Definitions
      At line 395 in file LPC2300.s
   Uses
      None
Comment: PINSEL7_OFS unused
PINSEL8_OFS 00000020

Symbol: PINSEL8_OFS
   Definitions
      At line 396 in file LPC2300.s
   Uses
      At line 732 in file LPC2300.s
Comment: PINSEL8_OFS used once
PINSEL9_OFS 00000024

Symbol: PINSEL9_OFS
   Definitions
      At line 397 in file LPC2300.s
   Uses
      At line 734 in file LPC2300.s
Comment: PINSEL9_OFS used once
PLLCFG_OFS 00000084




ARM Macro Assembler    Page 14 Alphabetic symbol ordering
Absolute symbols

Symbol: PLLCFG_OFS
   Definitions
      At line 116 in file LPC2300.s
   Uses
      At line 656 in file LPC2300.s
Comment: PLLCFG_OFS used once
PLLCFG_Val 0000000B

Symbol: PLLCFG_Val
   Definitions
      At line 356 in file LPC2300.s
   Uses
      At line 655 in file LPC2300.s
      At line 672 in file LPC2300.s

PLLCON_OFS 00000080

Symbol: PLLCON_OFS
   Definitions
      At line 115 in file LPC2300.s
   Uses
      At line 660 in file LPC2300.s
      At line 692 in file LPC2300.s

PLLCON_PLLC 00000002

Symbol: PLLCON_PLLC
   Definitions
      At line 134 in file LPC2300.s
   Uses
      At line 691 in file LPC2300.s
Comment: PLLCON_PLLC used once
PLLCON_PLLE 00000001

Symbol: PLLCON_PLLE
   Definitions
      At line 133 in file LPC2300.s
   Uses
      At line 659 in file LPC2300.s
      At line 691 in file LPC2300.s

PLLFEED_OFS 0000008C

Symbol: PLLFEED_OFS
   Definitions
      At line 118 in file LPC2300.s
   Uses
      At line 657 in file LPC2300.s
      At line 658 in file LPC2300.s
      At line 661 in file LPC2300.s
      At line 662 in file LPC2300.s
      At line 693 in file LPC2300.s
      At line 694 in file LPC2300.s

PLLSTAT_M 00007FFF

Symbol: PLLSTAT_M
   Definitions
      At line 135 in file LPC2300.s



ARM Macro Assembler    Page 15 Alphabetic symbol ordering
Absolute symbols

   Uses
      At line 670 in file LPC2300.s
Comment: PLLSTAT_M used once
PLLSTAT_N 00FF0000

Symbol: PLLSTAT_N
   Definitions
      At line 136 in file LPC2300.s
   Uses
      At line 670 in file LPC2300.s
Comment: PLLSTAT_N used once
PLLSTAT_OFS 00000088

Symbol: PLLSTAT_OFS
   Definitions
      At line 117 in file LPC2300.s
   Uses
      At line 665 in file LPC2300.s
      At line 669 in file LPC2300.s

PLLSTAT_PLOCK 04000000

Symbol: PLLSTAT_PLOCK
   Definitions
      At line 137 in file LPC2300.s
   Uses
      At line 666 in file LPC2300.s
Comment: PLLSTAT_PLOCK used once
RAM_BASE 40000000

Symbol: RAM_BASE
   Definitions
      At line 63 in file LPC2300.s
   Uses
      None
Comment: RAM_BASE unused
SCB_BASE E01FC000

Symbol: SCB_BASE
   Definitions
      At line 114 in file LPC2300.s
   Uses
      At line 639 in file LPC2300.s
      At line 716 in file LPC2300.s

SCS_OFS 000001A0

Symbol: SCS_OFS
   Definitions
      At line 122 in file LPC2300.s
   Uses
      At line 645 in file LPC2300.s
      At line 648 in file LPC2300.s

SCS_Val 00000020

Symbol: SCS_Val
   Definitions
      At line 354 in file LPC2300.s



ARM Macro Assembler    Page 16 Alphabetic symbol ordering
Absolute symbols

   Uses
      At line 644 in file LPC2300.s
      At line 647 in file LPC2300.s

STA_MEM0_BASE 80000000

Symbol: STA_MEM0_BASE
   Definitions
      At line 67 in file LPC2300.s
   Uses
      None
Comment: STA_MEM0_BASE unused
STA_MEM1_BASE 81000000

Symbol: STA_MEM1_BASE
   Definitions
      At line 68 in file LPC2300.s
   Uses
      None
Comment: STA_MEM1_BASE unused
SVC_Stack_Size 00000008

Symbol: SVC_Stack_Size
   Definitions
      At line 83 in file LPC2300.s
   Uses
      At line 90 in file LPC2300.s
      At line 841 in file LPC2300.s

UND_Stack_Size 00000000

Symbol: UND_Stack_Size
   Definitions
      At line 82 in file LPC2300.s
   Uses
      At line 90 in file LPC2300.s
      At line 821 in file LPC2300.s

USBCLKCFG_OFS 00000108

Symbol: USBCLKCFG_OFS
   Definitions
      At line 120 in file LPC2300.s
   Uses
      At line 682 in file LPC2300.s
Comment: USBCLKCFG_OFS used once
USBCLKCFG_Val 00000005

Symbol: USBCLKCFG_Val
   Definitions
      At line 358 in file LPC2300.s
   Uses
      At line 681 in file LPC2300.s
Comment: USBCLKCFG_Val used once
USR_Stack_Size 00000400

Symbol: USR_Stack_Size
   Definitions
      At line 87 in file LPC2300.s



ARM Macro Assembler    Page 17 Alphabetic symbol ordering
Absolute symbols

   Uses
      At line 94 in file LPC2300.s
Comment: USR_Stack_Size used once
115 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
External symbols

__main 00000000

Symbol: __main
   Definitions
      At line 859 in file LPC2300.s
   Uses
      At line 860 in file LPC2300.s
Comment: __main used once
1 symbol
489 symbols in table