From d54613ac63ab962d62fab5103ddf90ea2f38f780 Mon Sep 17 00:00:00 2001 From: MMS Date: Wed, 25 Jan 2023 16:22:49 -0500 Subject: [PATCH] 2.0.2 2.0.2 2.0.2 Improved BSPs, added EK-TM4C123GXL 2.0.2 --- .gitignore | 49 +- 3rd_party/ek-tm4c123gxl/README.txt | 24 + 3rd_party/ek-tm4c123gxl/TM4C123GH6PM.h | 1830 ++++ .../ek-tm4c123gxl/arm/startup_TM4C123GH6PM.s | 716 ++ 3rd_party/ek-tm4c123gxl/cmsis_armclang.h | 1503 +++ 3rd_party/ek-tm4c123gxl/cmsis_compiler.h | 283 + 3rd_party/ek-tm4c123gxl/cmsis_gcc.h | 2211 +++++ 3rd_party/ek-tm4c123gxl/cmsis_iccarm.h | 1002 ++ 3rd_party/ek-tm4c123gxl/cmsis_version.h | 39 + 3rd_party/ek-tm4c123gxl/core_cm4.h | 2129 +++++ 3rd_party/ek-tm4c123gxl/ek-tm4c123gxl.ld | 118 + .../ek-tm4c123gxl/gnu/startup_TM4C123GH6PM.c | 518 + 3rd_party/ek-tm4c123gxl/gpio.h | 201 + .../ek-tm4c123gxl/iar/startup_TM4C123GH6PM.s | 620 ++ 3rd_party/ek-tm4c123gxl/mpu_armv7.h | 275 + 3rd_party/ek-tm4c123gxl/rom.h | 8358 +++++++++++++++++ 3rd_party/ek-tm4c123gxl/sysctl.h | 644 ++ 3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.c | 610 ++ 3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.h | 63 + .../nucleo-h743zi/arm/startup_stm32h743xx.s | 13 +- .../nucleo-h743zi/gnu/startup_stm32h743xx.c | 8 +- .../nucleo-h743zi/iar/startup_stm32h743xx.s | 12 +- .../nucleo-l053r8/arm/startup_stm32l053xx.s | 14 +- .../nucleo-l053r8/gnu/startup_stm32l053xx.c | 8 +- .../nucleo-l053r8/iar/startup_stm32l053xx.s | 12 +- README.md | 6 +- img/bd_EK-TM4C123GXL.jpg | Bin 0 -> 22820 bytes img/blinky_button.pvs | 16 +- img/sst0_ek-tm4c.sr | Bin 0 -> 5693 bytes img/sst_ek-tm4c.sr | Bin 0 -> 5481 bytes include/dbc_assert.h | 207 + include/qassert.h | 365 - include/sst.h | 6 + include/sst.hpp | 6 + .../armclang/ek-tm4c123gxl.uvoptx | 413 + .../armclang/ek-tm4c123gxl.uvprojx | 487 + .../armclang/nucleo-h743zi.uvprojx | 4 +- .../armclang/nucleo-l053r8.uvprojx | 4 +- sst0_c/examples/blinky_button/blinky1.c | 7 +- sst0_c/examples/blinky_button/blinky3.c | 7 +- sst0_c/examples/blinky_button/blinky_button.h | 2 +- .../blinky_button/bsp_ek-tm4c123gxl.c | 293 + .../blinky_button/bsp_nucleo-h743zi.c | 80 +- .../blinky_button/bsp_nucleo-l053r8.c | 74 +- sst0_c/examples/blinky_button/button2a.c | 5 +- sst0_c/examples/blinky_button/button2b.c | 4 +- .../blinky_button/gnu/ek-tm4c123gxl.mak | 241 + .../blinky_button/gnu/flash_ek-tm4c123gxl.bat | 33 + .../blinky_button/gnu/nucleo-h743zi.mak | 2 - .../blinky_button/gnu/nucleo-l053r8.mak | 2 - .../blinky_button/iar/ek-tm4c123gxl.ewd | 1530 +++ .../blinky_button/iar/ek-tm4c123gxl.ewp | 1105 +++ .../blinky_button/iar/ek-tm4c123gxl.eww | 10 + .../blinky_button/iar/nucleo-h743zi.ewp | 6 +- .../blinky_button/iar/nucleo-l053r8.ewp | 6 +- sst0_c/examples/blinky_button/main.c | 8 +- sst0_c/src/sst0.c | 12 +- .../armclang/ek-tm4c123gxl.uvoptx | 413 + .../armclang/ek-tm4c123gxl.uvprojx | 487 + .../armclang/nucleo-h743zi.uvprojx | 4 +- .../armclang/nucleo-l053r8.uvprojx | 4 +- sst0_cpp/examples/blinky_button/blinky1.cpp | 7 +- sst0_cpp/examples/blinky_button/blinky3.cpp | 7 +- .../examples/blinky_button/blinky_button.hpp | 2 +- .../blinky_button/bsp_ek-tm4c123gxl.cpp | 285 + .../blinky_button/bsp_nucleo-h743zi.cpp | 28 +- .../blinky_button/bsp_nucleo-l053r8.cpp | 30 +- sst0_cpp/examples/blinky_button/button2a.cpp | 4 +- sst0_cpp/examples/blinky_button/button2b.cpp | 4 +- .../blinky_button/gnu/ek-tm4c123gxl.mak | 241 + .../blinky_button/gnu/flash_ek-tm4c123gxl.bat | 33 + .../blinky_button/gnu/nucleo-h743zi.mak | 2 - .../blinky_button/gnu/nucleo-l053r8.mak | 2 - .../blinky_button/iar/ek-tm4c123gxl.ewd | 1530 +++ .../blinky_button/iar/ek-tm4c123gxl.ewp | 1102 +++ .../blinky_button/iar/ek-tm4c123gxl.eww | 10 + .../blinky_button/iar/nucleo-h743zi.ewp | 6 +- .../blinky_button/iar/nucleo-l053r8.ewp | 6 +- sst0_cpp/examples/blinky_button/main.cpp | 8 +- sst0_cpp/src/sst0.cpp | 12 +- .../armclang/ek-tm4c123gxl.uvoptx | 425 + .../armclang/ek-tm4c123gxl.uvprojx | 492 + .../armclang/nucleo-h743zi.uvprojx | 4 +- .../armclang/nucleo-l053r8.uvprojx | 4 +- sst_c/examples/blinky_button/blinky1.c | 7 +- sst_c/examples/blinky_button/blinky3.c | 7 +- sst_c/examples/blinky_button/blinky_button.h | 2 +- .../blinky_button/bsp_ek-tm4c123gxl.c | 292 + .../blinky_button/bsp_nucleo-h743zi.c | 100 +- .../blinky_button/bsp_nucleo-l053r8.c | 92 +- sst_c/examples/blinky_button/button2a.c | 5 +- sst_c/examples/blinky_button/button2b.c | 4 +- .../blinky_button/gnu/ek-tm4c123gxl.mak | 242 + .../blinky_button/gnu/flash_ek-tm4c123gxl.bat | 33 + .../blinky_button/gnu/nucleo-h743zi.mak | 2 - .../blinky_button/gnu/nucleo-l053r8.mak | 2 - .../blinky_button/iar/ek-tm4c123gxl.ewd | 1530 +++ .../blinky_button/iar/ek-tm4c123gxl.ewp | 1108 +++ .../blinky_button/iar/ek-tm4c123gxl.eww | 10 + .../blinky_button/iar/nucleo-h743zi.ewp | 6 +- .../blinky_button/iar/nucleo-l053r8.ewp | 6 +- sst_c/examples/blinky_button/main.c | 8 +- sst_c/ports/arm-cm/sst_port.c | 8 +- sst_c/src/sst.c | 10 +- .../armclang/ek-tm4c123gxl.uvoptx | 425 + .../armclang/ek-tm4c123gxl.uvprojx | 492 + .../armclang/nucleo-h743zi.uvprojx | 4 +- .../armclang/nucleo-l053r8.uvprojx | 4 +- sst_cpp/examples/blinky_button/blinky1.cpp | 7 +- sst_cpp/examples/blinky_button/blinky3.cpp | 7 +- .../examples/blinky_button/blinky_button.hpp | 2 +- .../blinky_button/bsp_ek-tm4c123gxl.cpp | 302 + .../blinky_button/bsp_nucleo-h743zi.cpp | 48 +- .../blinky_button/bsp_nucleo-l053r8.cpp | 38 +- sst_cpp/examples/blinky_button/button2a.cpp | 4 +- sst_cpp/examples/blinky_button/button2b.cpp | 4 +- .../blinky_button/gnu/ek-tm4c123gxl.mak | 242 + .../blinky_button/gnu/flash_ek-tm4c123gxl.bat | 33 + .../blinky_button/gnu/nucleo-h743zi.mak | 2 - .../blinky_button/gnu/nucleo-l053r8.mak | 2 - .../blinky_button/iar/ek-tm4c123gxl.ewd | 1530 +++ .../blinky_button/iar/ek-tm4c123gxl.ewp | 1105 +++ .../blinky_button/iar/ek-tm4c123gxl.eww | 10 + .../blinky_button/iar/nucleo-h743zi.ewp | 6 +- .../blinky_button/iar/nucleo-l053r8.ewp | 6 +- sst_cpp/examples/blinky_button/main.cpp | 8 +- sst_cpp/ports/arm-cm/sst_port.cpp | 10 +- sst_cpp/src/sst.cpp | 10 +- 128 files changed, 38285 insertions(+), 843 deletions(-) create mode 100644 3rd_party/ek-tm4c123gxl/README.txt create mode 100644 3rd_party/ek-tm4c123gxl/TM4C123GH6PM.h create mode 100644 3rd_party/ek-tm4c123gxl/arm/startup_TM4C123GH6PM.s create mode 100644 3rd_party/ek-tm4c123gxl/cmsis_armclang.h create mode 100644 3rd_party/ek-tm4c123gxl/cmsis_compiler.h create mode 100644 3rd_party/ek-tm4c123gxl/cmsis_gcc.h create mode 100644 3rd_party/ek-tm4c123gxl/cmsis_iccarm.h create mode 100644 3rd_party/ek-tm4c123gxl/cmsis_version.h create mode 100644 3rd_party/ek-tm4c123gxl/core_cm4.h create mode 100644 3rd_party/ek-tm4c123gxl/ek-tm4c123gxl.ld create mode 100644 3rd_party/ek-tm4c123gxl/gnu/startup_TM4C123GH6PM.c create mode 100644 3rd_party/ek-tm4c123gxl/gpio.h create mode 100644 3rd_party/ek-tm4c123gxl/iar/startup_TM4C123GH6PM.s create mode 100644 3rd_party/ek-tm4c123gxl/mpu_armv7.h create mode 100644 3rd_party/ek-tm4c123gxl/rom.h create mode 100644 3rd_party/ek-tm4c123gxl/sysctl.h create mode 100644 3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.c create mode 100644 3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.h create mode 100644 img/bd_EK-TM4C123GXL.jpg create mode 100644 img/sst0_ek-tm4c.sr create mode 100644 img/sst_ek-tm4c.sr create mode 100644 include/dbc_assert.h delete mode 100644 include/qassert.h create mode 100644 sst0_c/examples/blinky_button/armclang/ek-tm4c123gxl.uvoptx create mode 100644 sst0_c/examples/blinky_button/armclang/ek-tm4c123gxl.uvprojx create mode 100644 sst0_c/examples/blinky_button/bsp_ek-tm4c123gxl.c create mode 100644 sst0_c/examples/blinky_button/gnu/ek-tm4c123gxl.mak create mode 100644 sst0_c/examples/blinky_button/gnu/flash_ek-tm4c123gxl.bat create mode 100644 sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.ewd create mode 100644 sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.ewp create mode 100644 sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.eww create mode 100644 sst0_cpp/examples/blinky_button/armclang/ek-tm4c123gxl.uvoptx create mode 100644 sst0_cpp/examples/blinky_button/armclang/ek-tm4c123gxl.uvprojx create mode 100644 sst0_cpp/examples/blinky_button/bsp_ek-tm4c123gxl.cpp create mode 100644 sst0_cpp/examples/blinky_button/gnu/ek-tm4c123gxl.mak create mode 100644 sst0_cpp/examples/blinky_button/gnu/flash_ek-tm4c123gxl.bat create mode 100644 sst0_cpp/examples/blinky_button/iar/ek-tm4c123gxl.ewd create mode 100644 sst0_cpp/examples/blinky_button/iar/ek-tm4c123gxl.ewp create mode 100644 sst0_cpp/examples/blinky_button/iar/ek-tm4c123gxl.eww create mode 100644 sst_c/examples/blinky_button/armclang/ek-tm4c123gxl.uvoptx create mode 100644 sst_c/examples/blinky_button/armclang/ek-tm4c123gxl.uvprojx create mode 100644 sst_c/examples/blinky_button/bsp_ek-tm4c123gxl.c create mode 100644 sst_c/examples/blinky_button/gnu/ek-tm4c123gxl.mak create mode 100644 sst_c/examples/blinky_button/gnu/flash_ek-tm4c123gxl.bat create mode 100644 sst_c/examples/blinky_button/iar/ek-tm4c123gxl.ewd create mode 100644 sst_c/examples/blinky_button/iar/ek-tm4c123gxl.ewp create mode 100644 sst_c/examples/blinky_button/iar/ek-tm4c123gxl.eww create mode 100644 sst_cpp/examples/blinky_button/armclang/ek-tm4c123gxl.uvoptx create mode 100644 sst_cpp/examples/blinky_button/armclang/ek-tm4c123gxl.uvprojx create mode 100644 sst_cpp/examples/blinky_button/bsp_ek-tm4c123gxl.cpp create mode 100644 sst_cpp/examples/blinky_button/gnu/ek-tm4c123gxl.mak create mode 100644 sst_cpp/examples/blinky_button/gnu/flash_ek-tm4c123gxl.bat create mode 100644 sst_cpp/examples/blinky_button/iar/ek-tm4c123gxl.ewd create mode 100644 sst_cpp/examples/blinky_button/iar/ek-tm4c123gxl.ewp create mode 100644 sst_cpp/examples/blinky_button/iar/ek-tm4c123gxl.eww diff --git a/.gitignore b/.gitignore index d09f1f2..e53bb1b 100644 --- a/.gitignore +++ b/.gitignore @@ -1,49 +1,6 @@ -# Prerequisites -*.d - -# Object files -*.o -*.ko -*.obj -*.elf - -# Linker output -*.ilk -*.map -*.exp - -# uVision temporaries -*.uvguix.* -*.htm -*.lnp -*.sct -Debug*/ - -# IAR temporaries -*.dep - -# Executables -*.exe -*.out -*.app -*.i*86 -*.x86_64 -*.hex - -# Debug files -*.dSYM/ -*.su -*.idb -*.pdb - -# Kernel Module Compile Results -*.mod* -*.cmd -.tmp_versions/ -modules.order -Module.symvers -Mkfile.old -dkms.conf +# build directories +build*/ +bin*/ # test directories test_priv/ diff --git a/3rd_party/ek-tm4c123gxl/README.txt b/3rd_party/ek-tm4c123gxl/README.txt new file mode 100644 index 0000000..88605f0 --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/README.txt @@ -0,0 +1,24 @@ +This directory contains the support code for the EK-TM4C123GXL board +(TivaC LauchPad). + +The sub-directories contain code that is specific to the particular +ARM toolchains, such as ARM (MDK-ARM), GCC, and IAR. + + +CMSIS-Compliant Device Files +============================ +The code also includes the CMSIS-compliant interface to the TM4C123GH6PM +MCU files: + +TM4C123GH6PM.h +system_TM4C123GH6PM.h +system_TM4C123GH6PM.c +arm\startup_TM4C123GH6PM.s +gcc\startup_TM4C123GH6PM.c +iar\startup_TM4C123GH6PM.s + + +Adjusting the CPU Clock Speed +----------------------------- +The current setting is to run at 50MHz from PLL, but the CPU clock speed +can be modified by editing the file system_TM4C123GH6PM.c. diff --git a/3rd_party/ek-tm4c123gxl/TM4C123GH6PM.h b/3rd_party/ek-tm4c123gxl/TM4C123GH6PM.h new file mode 100644 index 0000000..10fb586 --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/TM4C123GH6PM.h @@ -0,0 +1,1830 @@ +/***************************************************************************** +* Modified from the original as follows: +* - defined TARGET_IS_BLIZZARD_RA1 for compatibility with the TI library +* - in GPIOA_Type struct replaced first __I RESERVED0[255] with +* __IO uint32_t DATA_Bits[255] to access the individual GPIOA bits. +* - added options for the ARMCC v6 compiler (CLANG) +* +* Quantum Leaps on 2018-01-31 +* https://www.state-machine.com +*****************************************************************************/ + +/****************************************************************************************************//** + * @file TM4C123GH6PM.h + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * TM4C123GH6PM from Texas Instruments. + * + * @version V12591 + * @date 19. February 2014 + * + * @note Generated with SVDConv V2.79v + * from CMSIS SVD File 'TM4C123GH6PM.svd.xml' Version 12591, + * + * @par + * Software License Agreement + * + * Texas Instruments (TI) is supplying this software for use solely and + * exclusively on TI's microcontroller products. The software is owned by + * TI and/or its suppliers, and is protected under applicable copyright + * laws. You may not combine this software with "viral" open-source + * software in order to form a larger program. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. + * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT + * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY + * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL + * DAMAGES, FOR ANY REASON WHATSOEVER. + * + * + * + *******************************************************************************************************/ + + + +/** @addtogroup Texas Instruments + * @{ + */ + +/** @addtogroup TM4C123GH6PM + * @{ + */ + +#ifndef TM4C123GH6PM_H +#define TM4C123GH6PM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* ------------------- TM4C123GH6PM Specific Interrupt Numbers ------------------ */ + GPIOA_IRQn = 0, /*!< 0 GPIOA */ + GPIOB_IRQn = 1, /*!< 1 GPIOB */ + GPIOC_IRQn = 2, /*!< 2 GPIOC */ + GPIOD_IRQn = 3, /*!< 3 GPIOD */ + GPIOE_IRQn = 4, /*!< 4 GPIOE */ + UART0_IRQn = 5, /*!< 5 UART0 */ + UART1_IRQn = 6, /*!< 6 UART1 */ + SSI0_IRQn = 7, /*!< 7 SSI0 */ + I2C0_IRQn = 8, /*!< 8 I2C0 */ + PWM0_FAULT_IRQn = 9, /*!< 9 PWM0_FAULT */ + PWM0_0_IRQn = 10, /*!< 10 PWM0_0 */ + PWM0_1_IRQn = 11, /*!< 11 PWM0_1 */ + PWM0_2_IRQn = 12, /*!< 12 PWM0_2 */ + QEI0_IRQn = 13, /*!< 13 QEI0 */ + ADC0SS0_IRQn = 14, /*!< 14 ADC0SS0 */ + ADC0SS1_IRQn = 15, /*!< 15 ADC0SS1 */ + ADC0SS2_IRQn = 16, /*!< 16 ADC0SS2 */ + ADC0SS3_IRQn = 17, /*!< 17 ADC0SS3 */ + WATCHDOG0_IRQn = 18, /*!< 18 WATCHDOG0 */ + TIMER0A_IRQn = 19, /*!< 19 TIMER0A */ + TIMER0B_IRQn = 20, /*!< 20 TIMER0B */ + TIMER1A_IRQn = 21, /*!< 21 TIMER1A */ + TIMER1B_IRQn = 22, /*!< 22 TIMER1B */ + TIMER2A_IRQn = 23, /*!< 23 TIMER2A */ + TIMER2B_IRQn = 24, /*!< 24 TIMER2B */ + COMP0_IRQn = 25, /*!< 25 COMP0 */ + COMP1_IRQn = 26, /*!< 26 COMP1 */ + SYSCTL_IRQn = 28, /*!< 28 SYSCTL */ + FLASH_CTRL_IRQn = 29, /*!< 29 FLASH_CTRL */ + GPIOF_IRQn = 30, /*!< 30 GPIOF */ + UART2_IRQn = 33, /*!< 33 UART2 */ + SSI1_IRQn = 34, /*!< 34 SSI1 */ + TIMER3A_IRQn = 35, /*!< 35 TIMER3A */ + TIMER3B_IRQn = 36, /*!< 36 TIMER3B */ + I2C1_IRQn = 37, /*!< 37 I2C1 */ + QEI1_IRQn = 38, /*!< 38 QEI1 */ + CAN0_IRQn = 39, /*!< 39 CAN0 */ + CAN1_IRQn = 40, /*!< 40 CAN1 */ + HIB_IRQn = 43, /*!< 43 HIB */ + USB0_IRQn = 44, /*!< 44 USB0 */ + PWM0_3_IRQn = 45, /*!< 45 PWM0_3 */ + UDMA_IRQn = 46, /*!< 46 UDMA */ + UDMAERR_IRQn = 47, /*!< 47 UDMAERR */ + ADC1SS0_IRQn = 48, /*!< 48 ADC1SS0 */ + ADC1SS1_IRQn = 49, /*!< 49 ADC1SS1 */ + ADC1SS2_IRQn = 50, /*!< 50 ADC1SS2 */ + ADC1SS3_IRQn = 51, /*!< 51 ADC1SS3 */ + SSI2_IRQn = 57, /*!< 57 SSI2 */ + SSI3_IRQn = 58, /*!< 58 SSI3 */ + UART3_IRQn = 59, /*!< 59 UART3 */ + UART4_IRQn = 60, /*!< 60 UART4 */ + UART5_IRQn = 61, /*!< 61 UART5 */ + UART6_IRQn = 62, /*!< 62 UART6 */ + UART7_IRQn = 63, /*!< 63 UART7 */ + I2C2_IRQn = 68, /*!< 68 I2C2 */ + I2C3_IRQn = 69, /*!< 69 I2C3 */ + TIMER4A_IRQn = 70, /*!< 70 TIMER4A */ + TIMER4B_IRQn = 71, /*!< 71 TIMER4B */ + TIMER5A_IRQn = 92, /*!< 92 TIMER5A */ + TIMER5B_IRQn = 93, /*!< 93 TIMER5B */ + WTIMER0A_IRQn = 94, /*!< 94 WTIMER0A */ + WTIMER0B_IRQn = 95, /*!< 95 WTIMER0B */ + WTIMER1A_IRQn = 96, /*!< 96 WTIMER1A */ + WTIMER1B_IRQn = 97, /*!< 97 WTIMER1B */ + WTIMER2A_IRQn = 98, /*!< 98 WTIMER2A */ + WTIMER2B_IRQn = 99, /*!< 99 WTIMER2B */ + WTIMER3A_IRQn = 100, /*!< 100 WTIMER3A */ + WTIMER3B_IRQn = 101, /*!< 101 WTIMER3B */ + WTIMER4A_IRQn = 102, /*!< 102 WTIMER4A */ + WTIMER4B_IRQn = 103, /*!< 103 WTIMER4B */ + WTIMER5A_IRQn = 104, /*!< 104 WTIMER5A */ + WTIMER5B_IRQn = 105, /*!< 105 WTIMER5B */ + SYSEXC_IRQn = 106, /*!< 106 SYSEXC */ + PWM1_0_IRQn = 134, /*!< 134 PWM1_0 */ + PWM1_1_IRQn = 135, /*!< 135 PWM1_1 */ + PWM1_2_IRQn = 136, /*!< 136 PWM1_2 */ + PWM1_3_IRQn = 137, /*!< 137 PWM1_3 */ + PWM1_FAULT_IRQn = 138 /*!< 138 PWM1_FAULT */ +} IRQn_Type; + +/* + * =========================================================================== + * ---------- Interrupt Handler Prototypes ----------------------------------- + * =========================================================================== + */ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void HardFault_Handler(void); + +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +void GPIOPortA_IRQHandler(void); +void GPIOPortB_IRQHandler(void); +void GPIOPortC_IRQHandler(void); +void GPIOPortD_IRQHandler(void); +void GPIOPortE_IRQHandler(void); +void UART0_IRQHandler(void); +void UART1_IRQHandler(void); +void SSI0_IRQHandler(void); +void I2C0_IRQHandler(void); +void PWMFault_IRQHandler(void); +void PWMGen0_IRQHandler(void); +void PWMGen1_IRQHandler(void); +void PWMGen2_IRQHandler(void); +void QEI0_IRQHandler(void); +void ADCSeq0_IRQHandler(void); +void ADCSeq1_IRQHandler(void); +void ADCSeq2_IRQHandler(void); +void ADCSeq3_IRQHandler(void); +void Watchdog_IRQHandler(void); +void Timer0A_IRQHandler(void); +void Timer0B_IRQHandler(void); +void Timer1A_IRQHandler(void); +void Timer1B_IRQHandler(void); +void Timer2A_IRQHandler(void); +void Timer2B_IRQHandler(void); +void Comp0_IRQHandler(void); +void Comp1_IRQHandler(void); +void Comp2_IRQHandler(void); +void SysCtrl_IRQHandler(void); +void FlashCtrl_IRQHandler(void); +void GPIOPortF_IRQHandler(void); +void GPIOPortG_IRQHandler(void); +void GPIOPortH_IRQHandler(void); +void UART2_IRQHandler(void); +void SSI1_IRQHandler(void); +void Timer3A_IRQHandler(void); +void Timer3B_IRQHandler(void); +void I2C1_IRQHandler(void); +void QEI1_IRQHandler(void); +void CAN0_IRQHandler(void); +void CAN1_IRQHandler(void); +void CAN2_IRQHandler(void); +void Hibernate_IRQHandler(void); +void USB0_IRQHandler(void); +void PWMGen3_IRQHandler(void); +void uDMAST_IRQHandler(void); +void uDMAError_IRQHandler(void); +void ADC1Seq0_IRQHandler(void); +void ADC1Seq1_IRQHandler(void); +void ADC1Seq2_IRQHandler(void); +void ADC1Seq3_IRQHandler(void); +void I2S0_IRQHandler(void); +void EBI0_IRQHandler(void); +void GPIOPortJ_IRQHandler(void); +void GPIOPortK_IRQHandler(void); +void GPIOPortL_IRQHandler(void); +void SSI2_IRQHandler(void); +void SSI3_IRQHandler(void); +void UART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void UART6_IRQHandler(void); +void UART7_IRQHandler(void); +void I2C2_IRQHandler(void); +void I2C3_IRQHandler(void); +void Timer4A_IRQHandler(void); +void Timer4B_IRQHandler(void); +void Timer5A_IRQHandler(void); +void Timer5B_IRQHandler(void); +void WideTimer0A_IRQHandler(void); +void WideTimer0B_IRQHandler(void); +void WideTimer1A_IRQHandler(void); +void WideTimer1B_IRQHandler(void); +void WideTimer2A_IRQHandler(void); +void WideTimer2B_IRQHandler(void); +void WideTimer3A_IRQHandler(void); +void WideTimer3B_IRQHandler(void); +void WideTimer4A_IRQHandler(void); +void WideTimer4B_IRQHandler(void); +void WideTimer5A_IRQHandler(void); +void WideTimer5B_IRQHandler(void); +void FPU_IRQHandler(void); +void PECI0_IRQHandler(void); +void LPC0_IRQHandler(void); +void I2C4_IRQHandler(void); +void I2C5_IRQHandler(void); +void GPIOPortM_IRQHandler(void); +void GPIOPortN_IRQHandler(void); +void QEI2_IRQHandler(void); +void Fan0_IRQHandler(void); +void GPIOPortP0_IRQHandler(void); +void GPIOPortP1_IRQHandler(void); +void GPIOPortP2_IRQHandler(void); +void GPIOPortP3_IRQHandler(void); +void GPIOPortP4_IRQHandler(void); +void GPIOPortP5_IRQHandler(void); +void GPIOPortP6_IRQHandler(void); +void GPIOPortP7_IRQHandler(void); +void GPIOPortQ0_IRQHandler(void); +void GPIOPortQ1_IRQHandler(void); +void GPIOPortQ2_IRQHandler(void); +void GPIOPortQ3_IRQHandler(void); +void GPIOPortQ4_IRQHandler(void); +void GPIOPortQ5_IRQHandler(void); +void GPIOPortQ6_IRQHandler(void); +void GPIOPortQ7_IRQHandler(void); +void GPIOPortR_IRQHandler(void); +void GPIOPortS_IRQHandler(void); +void PWM1Gen0_IRQHandler(void); +void PWM1Gen1_IRQHandler(void); +void PWM1Gen2_IRQHandler(void); +void PWM1Gen3_IRQHandler(void); +void PWM1Fault_IRQHandler(void); + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0102 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define TARGET_IS_BLIZZARD_RA1 1 /*!< Class of device (for TI library) */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#ifdef __cplusplus +} +#endif + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_TM4C123GH6PM.h" /*!< TM4C123GH6PM System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + /* anonymous unions are enabled by default */ +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + + +/* ================================================================================ */ +/* ================ WATCHDOG0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for WATCHDOG0 peripheral (WATCHDOG0) + */ + +typedef struct { /*!< WATCHDOG0 Structure */ + __IO uint32_t LOAD; /*!< Watchdog Load */ + __IO uint32_t VALUE; /*!< Watchdog Value */ + __IO uint32_t CTL; /*!< Watchdog Control */ + __O uint32_t ICR; /*!< Watchdog Interrupt Clear */ + __IO uint32_t RIS; /*!< Watchdog Raw Interrupt Status */ + __IO uint32_t MIS; /*!< Watchdog Masked Interrupt Status */ + __I uint32_t RESERVED0[256]; + __IO uint32_t TEST; /*!< Watchdog Test */ + __I uint32_t RESERVED1[505]; + __IO uint32_t LOCK; /*!< Watchdog Lock */ +} WATCHDOG0_Type; + + +/* ================================================================================ */ +/* ================ GPIOA ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for GPIOA peripheral (GPIOA) + */ + +typedef struct { /*!< GPIOA Structure */ + __IO uint32_t DATA_Bits[255]; /*!< GPIO bit combinations */ + __IO uint32_t DATA; /*!< GPIO Data */ + __IO uint32_t DIR; /*!< GPIO Direction */ + __IO uint32_t IS; /*!< GPIO Interrupt Sense */ + __IO uint32_t IBE; /*!< GPIO Interrupt Both Edges */ + __IO uint32_t IEV; /*!< GPIO Interrupt Event */ + __IO uint32_t IM; /*!< GPIO Interrupt Mask */ + __IO uint32_t RIS; /*!< GPIO Raw Interrupt Status */ + __IO uint32_t MIS; /*!< GPIO Masked Interrupt Status */ + __O uint32_t ICR; /*!< GPIO Interrupt Clear */ + __IO uint32_t AFSEL; /*!< GPIO Alternate Function Select */ + __I uint32_t RESERVED1[55]; + __IO uint32_t DR2R; /*!< GPIO 2-mA Drive Select */ + __IO uint32_t DR4R; /*!< GPIO 4-mA Drive Select */ + __IO uint32_t DR8R; /*!< GPIO 8-mA Drive Select */ + __IO uint32_t ODR; /*!< GPIO Open Drain Select */ + __IO uint32_t PUR; /*!< GPIO Pull-Up Select */ + __IO uint32_t PDR; /*!< GPIO Pull-Down Select */ + __IO uint32_t SLR; /*!< GPIO Slew Rate Control Select */ + __IO uint32_t DEN; /*!< GPIO Digital Enable */ + __IO uint32_t LOCK; /*!< GPIO Lock */ + __I uint32_t CR; /*!< GPIO Commit */ + __IO uint32_t AMSEL; /*!< GPIO Analog Mode Select */ + __IO uint32_t PCTL; /*!< GPIO Port Control */ + __IO uint32_t ADCCTL; /*!< GPIO ADC Control */ + __IO uint32_t DMACTL; /*!< GPIO DMA Control */ +} GPIOA_Type; + + +/* ================================================================================ */ +/* ================ SSI0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for SSI0 peripheral (SSI0) + */ + +typedef struct { /*!< SSI0 Structure */ + __IO uint32_t CR0; /*!< SSI Control 0 */ + __IO uint32_t CR1; /*!< SSI Control 1 */ + __IO uint32_t DR; /*!< SSI Data */ + __IO uint32_t SR; /*!< SSI Status */ + __IO uint32_t CPSR; /*!< SSI Clock Prescale */ + __IO uint32_t IM; /*!< SSI Interrupt Mask */ + __IO uint32_t RIS; /*!< SSI Raw Interrupt Status */ + __IO uint32_t MIS; /*!< SSI Masked Interrupt Status */ + __O uint32_t ICR; /*!< SSI Interrupt Clear */ + __IO uint32_t DMACTL; /*!< SSI DMA Control */ + __I uint32_t RESERVED0[1000]; + __IO uint32_t CC; /*!< SSI Clock Configuration */ +} SSI0_Type; + + +/* ================================================================================ */ +/* ================ UART0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for UART0 peripheral (UART0) + */ + +typedef struct { /*!< UART0 Structure */ + __IO uint32_t DR; /*!< UART Data */ + + union { + __IO uint32_t ECR_UART_ALT; /*!< UART Receive Status/Error Clear */ + __IO uint32_t RSR; /*!< UART Receive Status/Error Clear */ + }; + __I uint32_t RESERVED0[4]; + __IO uint32_t FR; /*!< UART Flag */ + __I uint32_t RESERVED1; + __IO uint32_t ILPR; /*!< UART IrDA Low-Power Register */ + __IO uint32_t IBRD; /*!< UART Integer Baud-Rate Divisor */ + __IO uint32_t FBRD; /*!< UART Fractional Baud-Rate Divisor */ + __IO uint32_t LCRH; /*!< UART Line Control */ + __IO uint32_t CTL; /*!< UART Control */ + __IO uint32_t IFLS; /*!< UART Interrupt FIFO Level Select */ + __IO uint32_t IM; /*!< UART Interrupt Mask */ + __IO uint32_t RIS; /*!< UART Raw Interrupt Status */ + __IO uint32_t MIS; /*!< UART Masked Interrupt Status */ + __O uint32_t ICR; /*!< UART Interrupt Clear */ + __IO uint32_t DMACTL; /*!< UART DMA Control */ + __I uint32_t RESERVED2[22]; + __IO uint32_t _9BITADDR; /*!< UART 9-Bit Self Address */ + __IO uint32_t _9BITAMASK; /*!< UART 9-Bit Self Address Mask */ + __I uint32_t RESERVED3[965]; + __IO uint32_t PP; /*!< UART Peripheral Properties */ + __I uint32_t RESERVED4; + __IO uint32_t CC; /*!< UART Clock Configuration */ +} UART0_Type; + + +/* ================================================================================ */ +/* ================ I2C0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for I2C0 peripheral (I2C0) + */ + +typedef struct { /*!< I2C0 Structure */ + __IO uint32_t MSA; /*!< I2C Master Slave Address */ + + union { + __IO uint32_t MCS_I2C0_ALT; /*!< I2C Master Control/Status */ + __IO uint32_t MCS; /*!< I2C Master Control/Status */ + }; + __IO uint32_t MDR; /*!< I2C Master Data */ + __IO uint32_t MTPR; /*!< I2C Master Timer Period */ + __IO uint32_t MIMR; /*!< I2C Master Interrupt Mask */ + __IO uint32_t MRIS; /*!< I2C Master Raw Interrupt Status */ + __IO uint32_t MMIS; /*!< I2C Master Masked Interrupt Status */ + __O uint32_t MICR; /*!< I2C Master Interrupt Clear */ + __IO uint32_t MCR; /*!< I2C Master Configuration */ + __IO uint32_t MCLKOCNT; /*!< I2C Master Clock Low Timeout Count */ + __I uint32_t RESERVED0; + __IO uint32_t MBMON; /*!< I2C Master Bus Monitor */ + __I uint32_t RESERVED1[2]; + __IO uint32_t MCR2; /*!< I2C Master Configuration 2 */ + __I uint32_t RESERVED2[497]; + __IO uint32_t SOAR; /*!< I2C Slave Own Address */ + + union { + __IO uint32_t SCSR_I2C0_ALT; /*!< I2C Slave Control/Status */ + __IO uint32_t SCSR; /*!< I2C Slave Control/Status */ + }; + __IO uint32_t SDR; /*!< I2C Slave Data */ + __IO uint32_t SIMR; /*!< I2C Slave Interrupt Mask */ + __IO uint32_t SRIS; /*!< I2C Slave Raw Interrupt Status */ + __IO uint32_t SMIS; /*!< I2C Slave Masked Interrupt Status */ + __O uint32_t SICR; /*!< I2C Slave Interrupt Clear */ + __IO uint32_t SOAR2; /*!< I2C Slave Own Address 2 */ + __IO uint32_t SACKCTL; /*!< I2C Slave ACK Control */ + __I uint32_t RESERVED3[487]; + __IO uint32_t PP; /*!< I2C Peripheral Properties */ + __IO uint32_t PC; /*!< I2C Peripheral Configuration */ +} I2C0_Type; + + +/* ================================================================================ */ +/* ================ PWM0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for PWM0 peripheral (PWM0) + */ + +typedef struct { /*!< PWM0 Structure */ + __IO uint32_t CTL; /*!< PWM Master Control */ + __IO uint32_t SYNC; /*!< PWM Time Base Sync */ + __IO uint32_t ENABLE; /*!< PWM Output Enable */ + __IO uint32_t INVERT; /*!< PWM Output Inversion */ + __IO uint32_t FAULT; /*!< PWM Output Fault */ + __IO uint32_t INTEN; /*!< PWM Interrupt Enable */ + __IO uint32_t RIS; /*!< PWM Raw Interrupt Status */ + __IO uint32_t ISC; /*!< PWM Interrupt Status and Clear */ + __IO uint32_t STATUS; /*!< PWM Status */ + __IO uint32_t FAULTVAL; /*!< PWM Fault Condition Value */ + __IO uint32_t ENUPD; /*!< PWM Enable Update */ + __I uint32_t RESERVED0[5]; + __IO uint32_t _0_CTL; /*!< PWM0 Control */ + __IO uint32_t _0_INTEN; /*!< PWM0 Interrupt and Trigger Enable */ + __IO uint32_t _0_RIS; /*!< PWM0 Raw Interrupt Status */ + __IO uint32_t _0_ISC; /*!< PWM0 Interrupt Status and Clear */ + __IO uint32_t _0_LOAD; /*!< PWM0 Load */ + __IO uint32_t _0_COUNT; /*!< PWM0 Counter */ + __IO uint32_t _0_CMPA; /*!< PWM0 Compare A */ + __IO uint32_t _0_CMPB; /*!< PWM0 Compare B */ + __IO uint32_t _0_GENA; /*!< PWM0 Generator A Control */ + __IO uint32_t _0_GENB; /*!< PWM0 Generator B Control */ + __IO uint32_t _0_DBCTL; /*!< PWM0 Dead-Band Control */ + __IO uint32_t _0_DBRISE; /*!< PWM0 Dead-Band Rising-Edge Delay */ + __IO uint32_t _0_DBFALL; /*!< PWM0 Dead-Band Falling-Edge-Delay */ + __IO uint32_t _0_FLTSRC0; /*!< PWM0 Fault Source 0 */ + __IO uint32_t _0_FLTSRC1; /*!< PWM0 Fault Source 1 */ + __IO uint32_t _0_MINFLTPER; /*!< PWM0 Minimum Fault Period */ + __IO uint32_t _1_CTL; /*!< PWM1 Control */ + __IO uint32_t _1_INTEN; /*!< PWM1 Interrupt and Trigger Enable */ + __IO uint32_t _1_RIS; /*!< PWM1 Raw Interrupt Status */ + __IO uint32_t _1_ISC; /*!< PWM1 Interrupt Status and Clear */ + __IO uint32_t _1_LOAD; /*!< PWM1 Load */ + __IO uint32_t _1_COUNT; /*!< PWM1 Counter */ + __IO uint32_t _1_CMPA; /*!< PWM1 Compare A */ + __IO uint32_t _1_CMPB; /*!< PWM1 Compare B */ + __IO uint32_t _1_GENA; /*!< PWM1 Generator A Control */ + __IO uint32_t _1_GENB; /*!< PWM1 Generator B Control */ + __IO uint32_t _1_DBCTL; /*!< PWM1 Dead-Band Control */ + __IO uint32_t _1_DBRISE; /*!< PWM1 Dead-Band Rising-Edge Delay */ + __IO uint32_t _1_DBFALL; /*!< PWM1 Dead-Band Falling-Edge-Delay */ + __IO uint32_t _1_FLTSRC0; /*!< PWM1 Fault Source 0 */ + __IO uint32_t _1_FLTSRC1; /*!< PWM1 Fault Source 1 */ + __IO uint32_t _1_MINFLTPER; /*!< PWM1 Minimum Fault Period */ + __IO uint32_t _2_CTL; /*!< PWM2 Control */ + __IO uint32_t _2_INTEN; /*!< PWM2 Interrupt and Trigger Enable */ + __IO uint32_t _2_RIS; /*!< PWM2 Raw Interrupt Status */ + __IO uint32_t _2_ISC; /*!< PWM2 Interrupt Status and Clear */ + __IO uint32_t _2_LOAD; /*!< PWM2 Load */ + __IO uint32_t _2_COUNT; /*!< PWM2 Counter */ + __IO uint32_t _2_CMPA; /*!< PWM2 Compare A */ + __IO uint32_t _2_CMPB; /*!< PWM2 Compare B */ + __IO uint32_t _2_GENA; /*!< PWM2 Generator A Control */ + __IO uint32_t _2_GENB; /*!< PWM2 Generator B Control */ + __IO uint32_t _2_DBCTL; /*!< PWM2 Dead-Band Control */ + __IO uint32_t _2_DBRISE; /*!< PWM2 Dead-Band Rising-Edge Delay */ + __IO uint32_t _2_DBFALL; /*!< PWM2 Dead-Band Falling-Edge-Delay */ + __IO uint32_t _2_FLTSRC0; /*!< PWM2 Fault Source 0 */ + __IO uint32_t _2_FLTSRC1; /*!< PWM2 Fault Source 1 */ + __IO uint32_t _2_MINFLTPER; /*!< PWM2 Minimum Fault Period */ + __IO uint32_t _3_CTL; /*!< PWM3 Control */ + __IO uint32_t _3_INTEN; /*!< PWM3 Interrupt and Trigger Enable */ + __IO uint32_t _3_RIS; /*!< PWM3 Raw Interrupt Status */ + __IO uint32_t _3_ISC; /*!< PWM3 Interrupt Status and Clear */ + __IO uint32_t _3_LOAD; /*!< PWM3 Load */ + __IO uint32_t _3_COUNT; /*!< PWM3 Counter */ + __IO uint32_t _3_CMPA; /*!< PWM3 Compare A */ + __IO uint32_t _3_CMPB; /*!< PWM3 Compare B */ + __IO uint32_t _3_GENA; /*!< PWM3 Generator A Control */ + __IO uint32_t _3_GENB; /*!< PWM3 Generator B Control */ + __IO uint32_t _3_DBCTL; /*!< PWM3 Dead-Band Control */ + __IO uint32_t _3_DBRISE; /*!< PWM3 Dead-Band Rising-Edge Delay */ + __IO uint32_t _3_DBFALL; /*!< PWM3 Dead-Band Falling-Edge-Delay */ + __IO uint32_t _3_FLTSRC0; /*!< PWM3 Fault Source 0 */ + __IO uint32_t _3_FLTSRC1; /*!< PWM3 Fault Source 1 */ + __IO uint32_t _3_MINFLTPER; /*!< PWM3 Minimum Fault Period */ + __I uint32_t RESERVED1[432]; + __IO uint32_t _0_FLTSEN; /*!< PWM0 Fault Pin Logic Sense */ + __I uint32_t _0_FLTSTAT0; /*!< PWM0 Fault Status 0 */ + __I uint32_t _0_FLTSTAT1; /*!< PWM0 Fault Status 1 */ + __I uint32_t RESERVED2[29]; + __IO uint32_t _1_FLTSEN; /*!< PWM1 Fault Pin Logic Sense */ + __I uint32_t _1_FLTSTAT0; /*!< PWM1 Fault Status 0 */ + __I uint32_t _1_FLTSTAT1; /*!< PWM1 Fault Status 1 */ + __I uint32_t RESERVED3[30]; + __I uint32_t _2_FLTSTAT0; /*!< PWM2 Fault Status 0 */ + __I uint32_t _2_FLTSTAT1; /*!< PWM2 Fault Status 1 */ + __I uint32_t RESERVED4[30]; + __I uint32_t _3_FLTSTAT0; /*!< PWM3 Fault Status 0 */ + __I uint32_t _3_FLTSTAT1; /*!< PWM3 Fault Status 1 */ + __I uint32_t RESERVED5[397]; + __IO uint32_t PP; /*!< PWM Peripheral Properties */ +} PWM0_Type; + + +/* ================================================================================ */ +/* ================ QEI0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for QEI0 peripheral (QEI0) + */ + +typedef struct { /*!< QEI0 Structure */ + __IO uint32_t CTL; /*!< QEI Control */ + __IO uint32_t STAT; /*!< QEI Status */ + __IO uint32_t POS; /*!< QEI Position */ + __IO uint32_t MAXPOS; /*!< QEI Maximum Position */ + __IO uint32_t LOAD; /*!< QEI Timer Load */ + __IO uint32_t TIME; /*!< QEI Timer */ + __IO uint32_t COUNT; /*!< QEI Velocity Counter */ + __IO uint32_t SPEED; /*!< QEI Velocity */ + __IO uint32_t INTEN; /*!< QEI Interrupt Enable */ + __IO uint32_t RIS; /*!< QEI Raw Interrupt Status */ + __IO uint32_t ISC; /*!< QEI Interrupt Status and Clear */ +} QEI0_Type; + + +/* ================================================================================ */ +/* ================ TIMER0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for TIMER0 peripheral (TIMER0) + */ + +typedef struct { /*!< TIMER0 Structure */ + __IO uint32_t CFG; /*!< GPTM Configuration */ + __IO uint32_t TAMR; /*!< GPTM Timer A Mode */ + __IO uint32_t TBMR; /*!< GPTM Timer B Mode */ + __IO uint32_t CTL; /*!< GPTM Control */ + __IO uint32_t SYNC; /*!< GPTM Synchronize */ + __I uint32_t RESERVED0; + __IO uint32_t IMR; /*!< GPTM Interrupt Mask */ + __IO uint32_t RIS; /*!< GPTM Raw Interrupt Status */ + __IO uint32_t MIS; /*!< GPTM Masked Interrupt Status */ + __O uint32_t ICR; /*!< GPTM Interrupt Clear */ + __IO uint32_t TAILR; /*!< GPTM Timer A Interval Load */ + __IO uint32_t TBILR; /*!< GPTM Timer B Interval Load */ + __IO uint32_t TAMATCHR; /*!< GPTM Timer A Match */ + __IO uint32_t TBMATCHR; /*!< GPTM Timer B Match */ + __IO uint32_t TAPR; /*!< GPTM Timer A Prescale */ + __IO uint32_t TBPR; /*!< GPTM Timer B Prescale */ + __IO uint32_t TAPMR; /*!< GPTM TimerA Prescale Match */ + __IO uint32_t TBPMR; /*!< GPTM TimerB Prescale Match */ + __IO uint32_t TAR; /*!< GPTM Timer A */ + __IO uint32_t TBR; /*!< GPTM Timer B */ + __IO uint32_t TAV; /*!< GPTM Timer A Value */ + __IO uint32_t TBV; /*!< GPTM Timer B Value */ + __IO uint32_t RTCPD; /*!< GPTM RTC Predivide */ + __IO uint32_t TAPS; /*!< GPTM Timer A Prescale Snapshot */ + __IO uint32_t TBPS; /*!< GPTM Timer B Prescale Snapshot */ + __IO uint32_t TAPV; /*!< GPTM Timer A Prescale Value */ + __IO uint32_t TBPV; /*!< GPTM Timer B Prescale Value */ + __I uint32_t RESERVED1[981]; + __IO uint32_t PP; /*!< GPTM Peripheral Properties */ +} TIMER0_Type; + + +/* ================================================================================ */ +/* ================ WTIMER0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for WTIMER0 peripheral (WTIMER0) + */ + +typedef struct { /*!< WTIMER0 Structure */ + __IO uint32_t CFG; /*!< GPTM Configuration */ + __IO uint32_t TAMR; /*!< GPTM Timer A Mode */ + __IO uint32_t TBMR; /*!< GPTM Timer B Mode */ + __IO uint32_t CTL; /*!< GPTM Control */ + __IO uint32_t SYNC; /*!< GPTM Synchronize */ + __I uint32_t RESERVED0; + __IO uint32_t IMR; /*!< GPTM Interrupt Mask */ + __IO uint32_t RIS; /*!< GPTM Raw Interrupt Status */ + __IO uint32_t MIS; /*!< GPTM Masked Interrupt Status */ + __O uint32_t ICR; /*!< GPTM Interrupt Clear */ + __IO uint32_t TAILR; /*!< GPTM Timer A Interval Load */ + __IO uint32_t TBILR; /*!< GPTM Timer B Interval Load */ + __IO uint32_t TAMATCHR; /*!< GPTM Timer A Match */ + __IO uint32_t TBMATCHR; /*!< GPTM Timer B Match */ + __IO uint32_t TAPR; /*!< GPTM Timer A Prescale */ + __IO uint32_t TBPR; /*!< GPTM Timer B Prescale */ + __IO uint32_t TAPMR; /*!< GPTM TimerA Prescale Match */ + __IO uint32_t TBPMR; /*!< GPTM TimerB Prescale Match */ + __IO uint32_t TAR; /*!< GPTM Timer A */ + __IO uint32_t TBR; /*!< GPTM Timer B */ + __IO uint32_t TAV; /*!< GPTM Timer A Value */ + __IO uint32_t TBV; /*!< GPTM Timer B Value */ + __IO uint32_t RTCPD; /*!< GPTM RTC Predivide */ + __IO uint32_t TAPS; /*!< GPTM Timer A Prescale Snapshot */ + __IO uint32_t TBPS; /*!< GPTM Timer B Prescale Snapshot */ + __IO uint32_t TAPV; /*!< GPTM Timer A Prescale Value */ + __IO uint32_t TBPV; /*!< GPTM Timer B Prescale Value */ + __I uint32_t RESERVED1[981]; + __IO uint32_t PP; /*!< GPTM Peripheral Properties */ +} WTIMER0_Type; + + +/* ================================================================================ */ +/* ================ ADC0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for ADC0 peripheral (ADC0) + */ + +typedef struct { /*!< ADC0 Structure */ + __IO uint32_t ACTSS; /*!< ADC Active Sample Sequencer */ + __IO uint32_t RIS; /*!< ADC Raw Interrupt Status */ + __IO uint32_t IM; /*!< ADC Interrupt Mask */ + __IO uint32_t ISC; /*!< ADC Interrupt Status and Clear */ + __IO uint32_t OSTAT; /*!< ADC Overflow Status */ + __IO uint32_t EMUX; /*!< ADC Event Multiplexer Select */ + __IO uint32_t USTAT; /*!< ADC Underflow Status */ + __IO uint32_t TSSEL; /*!< ADC Trigger Source Select */ + __IO uint32_t SSPRI; /*!< ADC Sample Sequencer Priority */ + __IO uint32_t SPC; /*!< ADC Sample Phase Control */ + __IO uint32_t PSSI; /*!< ADC Processor Sample Sequence Initiate */ + __I uint32_t RESERVED0; + __IO uint32_t SAC; /*!< ADC Sample Averaging Control */ + __IO uint32_t DCISC; /*!< ADC Digital Comparator Interrupt Status and Clear */ + __IO uint32_t CTL; /*!< ADC Control */ + __I uint32_t RESERVED1; + __IO uint32_t SSMUX0; /*!< ADC Sample Sequence Input Multiplexer Select 0 */ + __IO uint32_t SSCTL0; /*!< ADC Sample Sequence Control 0 */ + __IO uint32_t SSFIFO0; /*!< ADC Sample Sequence Result FIFO 0 */ + __IO uint32_t SSFSTAT0; /*!< ADC Sample Sequence FIFO 0 Status */ + __IO uint32_t SSOP0; /*!< ADC Sample Sequence 0 Operation */ + __IO uint32_t SSDC0; /*!< ADC Sample Sequence 0 Digital Comparator Select */ + __I uint32_t RESERVED2[2]; + __IO uint32_t SSMUX1; /*!< ADC Sample Sequence Input Multiplexer Select 1 */ + __IO uint32_t SSCTL1; /*!< ADC Sample Sequence Control 1 */ + __IO uint32_t SSFIFO1; /*!< ADC Sample Sequence Result FIFO 1 */ + __IO uint32_t SSFSTAT1; /*!< ADC Sample Sequence FIFO 1 Status */ + __IO uint32_t SSOP1; /*!< ADC Sample Sequence 1 Operation */ + __IO uint32_t SSDC1; /*!< ADC Sample Sequence 1 Digital Comparator Select */ + __I uint32_t RESERVED3[2]; + __IO uint32_t SSMUX2; /*!< ADC Sample Sequence Input Multiplexer Select 2 */ + __IO uint32_t SSCTL2; /*!< ADC Sample Sequence Control 2 */ + __IO uint32_t SSFIFO2; /*!< ADC Sample Sequence Result FIFO 2 */ + __IO uint32_t SSFSTAT2; /*!< ADC Sample Sequence FIFO 2 Status */ + __IO uint32_t SSOP2; /*!< ADC Sample Sequence 2 Operation */ + __IO uint32_t SSDC2; /*!< ADC Sample Sequence 2 Digital Comparator Select */ + __I uint32_t RESERVED4[2]; + __IO uint32_t SSMUX3; /*!< ADC Sample Sequence Input Multiplexer Select 3 */ + __IO uint32_t SSCTL3; /*!< ADC Sample Sequence Control 3 */ + __IO uint32_t SSFIFO3; /*!< ADC Sample Sequence Result FIFO 3 */ + __IO uint32_t SSFSTAT3; /*!< ADC Sample Sequence FIFO 3 Status */ + __IO uint32_t SSOP3; /*!< ADC Sample Sequence 3 Operation */ + __IO uint32_t SSDC3; /*!< ADC Sample Sequence 3 Digital Comparator Select */ + __I uint32_t RESERVED5[786]; + __O uint32_t DCRIC; /*!< ADC Digital Comparator Reset Initial Conditions */ + __I uint32_t RESERVED6[63]; + __IO uint32_t DCCTL0; /*!< ADC Digital Comparator Control 0 */ + __IO uint32_t DCCTL1; /*!< ADC Digital Comparator Control 1 */ + __IO uint32_t DCCTL2; /*!< ADC Digital Comparator Control 2 */ + __IO uint32_t DCCTL3; /*!< ADC Digital Comparator Control 3 */ + __IO uint32_t DCCTL4; /*!< ADC Digital Comparator Control 4 */ + __IO uint32_t DCCTL5; /*!< ADC Digital Comparator Control 5 */ + __IO uint32_t DCCTL6; /*!< ADC Digital Comparator Control 6 */ + __IO uint32_t DCCTL7; /*!< ADC Digital Comparator Control 7 */ + __I uint32_t RESERVED7[8]; + __IO uint32_t DCCMP0; /*!< ADC Digital Comparator Range 0 */ + __IO uint32_t DCCMP1; /*!< ADC Digital Comparator Range 1 */ + __IO uint32_t DCCMP2; /*!< ADC Digital Comparator Range 2 */ + __IO uint32_t DCCMP3; /*!< ADC Digital Comparator Range 3 */ + __IO uint32_t DCCMP4; /*!< ADC Digital Comparator Range 4 */ + __IO uint32_t DCCMP5; /*!< ADC Digital Comparator Range 5 */ + __IO uint32_t DCCMP6; /*!< ADC Digital Comparator Range 6 */ + __IO uint32_t DCCMP7; /*!< ADC Digital Comparator Range 7 */ + __I uint32_t RESERVED8[88]; + __IO uint32_t PP; /*!< ADC Peripheral Properties */ + __IO uint32_t PC; /*!< ADC Peripheral Configuration */ + __IO uint32_t CC; /*!< ADC Clock Configuration */ +} ADC0_Type; + + +/* ================================================================================ */ +/* ================ COMP ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for COMP peripheral (COMP) + */ + +typedef struct { /*!< COMP Structure */ + __IO uint32_t ACMIS; /*!< Analog Comparator Masked Interrupt Status */ + __IO uint32_t ACRIS; /*!< Analog Comparator Raw Interrupt Status */ + __IO uint32_t ACINTEN; /*!< Analog Comparator Interrupt Enable */ + __I uint32_t RESERVED0; + __IO uint32_t ACREFCTL; /*!< Analog Comparator Reference Voltage Control */ + __I uint32_t RESERVED1[3]; + __IO uint32_t ACSTAT0; /*!< Analog Comparator Status 0 */ + __IO uint32_t ACCTL0; /*!< Analog Comparator Control 0 */ + __I uint32_t RESERVED2[6]; + __IO uint32_t ACSTAT1; /*!< Analog Comparator Status 1 */ + __IO uint32_t ACCTL1; /*!< Analog Comparator Control 1 */ + __I uint32_t RESERVED3[990]; + __IO uint32_t PP; /*!< Analog Comparator Peripheral Properties */ +} COMP_Type; + + +/* ================================================================================ */ +/* ================ CAN0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for CAN0 peripheral (CAN0) + */ + +typedef struct { /*!< CAN0 Structure */ + __IO uint32_t CTL; /*!< CAN Control */ + __IO uint32_t STS; /*!< CAN Status */ + __IO uint32_t ERR; /*!< CAN Error Counter */ + __IO uint32_t BIT; /*!< CAN Bit Timing */ + __IO uint32_t INT; /*!< CAN Interrupt */ + __IO uint32_t TST; /*!< CAN Test */ + __IO uint32_t BRPE; /*!< CAN Baud Rate Prescaler Extension */ + __I uint32_t RESERVED0; + __IO uint32_t IF1CRQ; /*!< CAN IF1 Command Request */ + + union { + __IO uint32_t IF1CMSK_CAN0_ALT; /*!< CAN IF1 Command Mask */ + __IO uint32_t IF1CMSK; /*!< CAN IF1 Command Mask */ + }; + __IO uint32_t IF1MSK1; /*!< CAN IF1 Mask 1 */ + __IO uint32_t IF1MSK2; /*!< CAN IF1 Mask 2 */ + __IO uint32_t IF1ARB1; /*!< CAN IF1 Arbitration 1 */ + __IO uint32_t IF1ARB2; /*!< CAN IF1 Arbitration 2 */ + __IO uint32_t IF1MCTL; /*!< CAN IF1 Message Control */ + __IO uint32_t IF1DA1; /*!< CAN IF1 Data A1 */ + __IO uint32_t IF1DA2; /*!< CAN IF1 Data A2 */ + __IO uint32_t IF1DB1; /*!< CAN IF1 Data B1 */ + __IO uint32_t IF1DB2; /*!< CAN IF1 Data B2 */ + __I uint32_t RESERVED1[13]; + __IO uint32_t IF2CRQ; /*!< CAN IF2 Command Request */ + + union { + __IO uint32_t IF2CMSK_CAN0_ALT; /*!< CAN IF2 Command Mask */ + __IO uint32_t IF2CMSK; /*!< CAN IF2 Command Mask */ + }; + __IO uint32_t IF2MSK1; /*!< CAN IF2 Mask 1 */ + __IO uint32_t IF2MSK2; /*!< CAN IF2 Mask 2 */ + __IO uint32_t IF2ARB1; /*!< CAN IF2 Arbitration 1 */ + __IO uint32_t IF2ARB2; /*!< CAN IF2 Arbitration 2 */ + __IO uint32_t IF2MCTL; /*!< CAN IF2 Message Control */ + __IO uint32_t IF2DA1; /*!< CAN IF2 Data A1 */ + __IO uint32_t IF2DA2; /*!< CAN IF2 Data A2 */ + __IO uint32_t IF2DB1; /*!< CAN IF2 Data B1 */ + __IO uint32_t IF2DB2; /*!< CAN IF2 Data B2 */ + __I uint32_t RESERVED2[21]; + __IO uint32_t TXRQ1; /*!< CAN Transmission Request 1 */ + __IO uint32_t TXRQ2; /*!< CAN Transmission Request 2 */ + __I uint32_t RESERVED3[6]; + __IO uint32_t NWDA1; /*!< CAN New Data 1 */ + __IO uint32_t NWDA2; /*!< CAN New Data 2 */ + __I uint32_t RESERVED4[6]; + __IO uint32_t MSG1INT; /*!< CAN Message 1 Interrupt Pending */ + __IO uint32_t MSG2INT; /*!< CAN Message 2 Interrupt Pending */ + __I uint32_t RESERVED5[6]; + __IO uint32_t MSG1VAL; /*!< CAN Message 1 Valid */ + __IO uint32_t MSG2VAL; /*!< CAN Message 2 Valid */ +} CAN0_Type; + + +/* ================================================================================ */ +/* ================ USB0 ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for USB0 peripheral (USB0) + */ + +typedef struct { /*!< USB0 Structure */ + __IO uint8_t FADDR; /*!< USB Device Functional Address */ + __IO uint8_t POWER; /*!< USB Power */ + __IO uint16_t TXIS; /*!< USB Transmit Interrupt Status */ + __IO uint16_t RXIS; /*!< USB Receive Interrupt Status */ + __IO uint16_t TXIE; /*!< USB Transmit Interrupt Enable */ + __IO uint16_t RXIE; /*!< USB Receive Interrupt Enable */ + + union { + __IO uint8_t IS_USB0_ALT; /*!< USB General Interrupt Status */ + __IO uint8_t IS; /*!< USB General Interrupt Status */ + }; + + union { + __IO uint8_t IE_USB0_ALT; /*!< USB Interrupt Enable */ + __IO uint8_t IE; /*!< USB Interrupt Enable */ + }; + __IO uint16_t FRAME; /*!< USB Frame Value */ + __IO uint8_t EPIDX; /*!< USB Endpoint Index */ + __IO uint8_t TEST; /*!< USB Test Mode */ + __I uint32_t RESERVED0[4]; + __IO uint32_t FIFO0; /*!< USB FIFO Endpoint 0 */ + __IO uint32_t FIFO1; /*!< USB FIFO Endpoint 1 */ + __IO uint32_t FIFO2; /*!< USB FIFO Endpoint 2 */ + __IO uint32_t FIFO3; /*!< USB FIFO Endpoint 3 */ + __IO uint32_t FIFO4; /*!< USB FIFO Endpoint 4 */ + __IO uint32_t FIFO5; /*!< USB FIFO Endpoint 5 */ + __IO uint32_t FIFO6; /*!< USB FIFO Endpoint 6 */ + __IO uint32_t FIFO7; /*!< USB FIFO Endpoint 7 */ + __I uint32_t RESERVED1[8]; + __IO uint8_t DEVCTL; /*!< USB Device Control */ + __I uint8_t RESERVED2[1]; + __IO uint8_t TXFIFOSZ; /*!< USB Transmit Dynamic FIFO Sizing */ + __IO uint8_t RXFIFOSZ; /*!< USB Receive Dynamic FIFO Sizing */ + __IO uint16_t TXFIFOADD; /*!< USB Transmit FIFO Start Address */ + __IO uint16_t RXFIFOADD; /*!< USB Receive FIFO Start Address */ + __I uint32_t RESERVED3[4]; + __I uint16_t RESERVED4; + __IO uint8_t CONTIM; /*!< USB Connect Timing */ + __IO uint8_t VPLEN; /*!< USB OTG VBUS Pulse Timing */ + __I uint8_t RESERVED5[1]; + __IO uint8_t FSEOF; /*!< USB Full-Speed Last Transaction to End of Frame Timing */ + __IO uint8_t LSEOF; /*!< USB Low-Speed Last Transaction to End of Frame Timing */ + __I uint8_t RESERVED6[1]; + __IO uint8_t TXFUNCADDR0; /*!< USB Transmit Functional Address Endpoint 0 */ + __I uint8_t RESERVED7[1]; + __IO uint8_t TXHUBADDR0; /*!< USB Transmit Hub Address Endpoint 0 */ + __IO uint8_t TXHUBPORT0; /*!< USB Transmit Hub Port Endpoint 0 */ + __I uint32_t RESERVED8; + __IO uint8_t TXFUNCADDR1; /*!< USB Transmit Functional Address Endpoint 1 */ + __I uint8_t RESERVED9[1]; + __IO uint8_t TXHUBADDR1; /*!< USB Transmit Hub Address Endpoint 1 */ + __IO uint8_t TXHUBPORT1; /*!< USB Transmit Hub Port Endpoint 1 */ + __IO uint8_t RXFUNCADDR1; /*!< USB Receive Functional Address Endpoint 1 */ + __I uint8_t RESERVED10[1]; + __IO uint8_t RXHUBADDR1; /*!< USB Receive Hub Address Endpoint 1 */ + __IO uint8_t RXHUBPORT1; /*!< USB Receive Hub Port Endpoint 1 */ + __IO uint8_t TXFUNCADDR2; /*!< USB Transmit Functional Address Endpoint 2 */ + __I uint8_t RESERVED11[1]; + __IO uint8_t TXHUBADDR2; /*!< USB Transmit Hub Address Endpoint 2 */ + __IO uint8_t TXHUBPORT2; /*!< USB Transmit Hub Port Endpoint 2 */ + __IO uint8_t RXFUNCADDR2; /*!< USB Receive Functional Address Endpoint 2 */ + __I uint8_t RESERVED12[1]; + __IO uint8_t RXHUBADDR2; /*!< USB Receive Hub Address Endpoint 2 */ + __IO uint8_t RXHUBPORT2; /*!< USB Receive Hub Port Endpoint 2 */ + __IO uint8_t TXFUNCADDR3; /*!< USB Transmit Functional Address Endpoint 3 */ + __I uint8_t RESERVED13[1]; + __IO uint8_t TXHUBADDR3; /*!< USB Transmit Hub Address Endpoint 3 */ + __IO uint8_t TXHUBPORT3; /*!< USB Transmit Hub Port Endpoint 3 */ + __IO uint8_t RXFUNCADDR3; /*!< USB Receive Functional Address Endpoint 3 */ + __I uint8_t RESERVED14[1]; + __IO uint8_t RXHUBADDR3; /*!< USB Receive Hub Address Endpoint 3 */ + __IO uint8_t RXHUBPORT3; /*!< USB Receive Hub Port Endpoint 3 */ + __IO uint8_t TXFUNCADDR4; /*!< USB Transmit Functional Address Endpoint 4 */ + __I uint8_t RESERVED15[1]; + __IO uint8_t TXHUBADDR4; /*!< USB Transmit Hub Address Endpoint 4 */ + __IO uint8_t TXHUBPORT4; /*!< USB Transmit Hub Port Endpoint 4 */ + __IO uint8_t RXFUNCADDR4; /*!< USB Receive Functional Address Endpoint 4 */ + __I uint8_t RESERVED16[1]; + __IO uint8_t RXHUBADDR4; /*!< USB Receive Hub Address Endpoint 4 */ + __IO uint8_t RXHUBPORT4; /*!< USB Receive Hub Port Endpoint 4 */ + __IO uint8_t TXFUNCADDR5; /*!< USB Transmit Functional Address Endpoint 5 */ + __I uint8_t RESERVED17[1]; + __IO uint8_t TXHUBADDR5; /*!< USB Transmit Hub Address Endpoint 5 */ + __IO uint8_t TXHUBPORT5; /*!< USB Transmit Hub Port Endpoint 5 */ + __IO uint8_t RXFUNCADDR5; /*!< USB Receive Functional Address Endpoint 5 */ + __I uint8_t RESERVED18[1]; + __IO uint8_t RXHUBADDR5; /*!< USB Receive Hub Address Endpoint 5 */ + __IO uint8_t RXHUBPORT5; /*!< USB Receive Hub Port Endpoint 5 */ + __IO uint8_t TXFUNCADDR6; /*!< USB Transmit Functional Address Endpoint 6 */ + __I uint8_t RESERVED19[1]; + __IO uint8_t TXHUBADDR6; /*!< USB Transmit Hub Address Endpoint 6 */ + __IO uint8_t TXHUBPORT6; /*!< USB Transmit Hub Port Endpoint 6 */ + __IO uint8_t RXFUNCADDR6; /*!< USB Receive Functional Address Endpoint 6 */ + __I uint8_t RESERVED20[1]; + __IO uint8_t RXHUBADDR6; /*!< USB Receive Hub Address Endpoint 6 */ + __IO uint8_t RXHUBPORT6; /*!< USB Receive Hub Port Endpoint 6 */ + __IO uint8_t TXFUNCADDR7; /*!< USB Transmit Functional Address Endpoint 7 */ + __I uint8_t RESERVED21[1]; + __IO uint8_t TXHUBADDR7; /*!< USB Transmit Hub Address Endpoint 7 */ + __IO uint8_t TXHUBPORT7; /*!< USB Transmit Hub Port Endpoint 7 */ + __IO uint8_t RXFUNCADDR7; /*!< USB Receive Functional Address Endpoint 7 */ + __I uint8_t RESERVED22[1]; + __IO uint8_t RXHUBADDR7; /*!< USB Receive Hub Address Endpoint 7 */ + __IO uint8_t RXHUBPORT7; /*!< USB Receive Hub Port Endpoint 7 */ + __I uint32_t RESERVED23[16]; + __I uint16_t RESERVED24; + + union { + __O uint8_t CSRL0_USB0_ALT; /*!< USB Control and Status Endpoint 0 Low */ + __O uint8_t CSRL0; /*!< USB Control and Status Endpoint 0 Low */ + }; + __O uint8_t CSRH0; /*!< USB Control and Status Endpoint 0 High */ + __I uint16_t RESERVED25[3]; + __IO uint8_t COUNT0; /*!< USB Receive Byte Count Endpoint 0 */ + __I uint8_t RESERVED26[1]; + __IO uint8_t TYPE0; /*!< USB Type Endpoint 0 */ + __IO uint8_t NAKLMT; /*!< USB NAK Limit */ + __I uint32_t RESERVED27; + __IO uint16_t TXMAXP1; /*!< USB Maximum Transmit Data Endpoint 1 */ + + union { + __IO uint8_t TXCSRL1_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 1 Low */ + __IO uint8_t TXCSRL1; /*!< USB Transmit Control and Status Endpoint 1 Low */ + }; + __IO uint8_t TXCSRH1; /*!< USB Transmit Control and Status Endpoint 1 High */ + __IO uint16_t RXMAXP1; /*!< USB Maximum Receive Data Endpoint 1 */ + + union { + __IO uint8_t RXCSRL1_USB0_ALT; /*!< USB Receive Control and Status Endpoint 1 Low */ + __IO uint8_t RXCSRL1; /*!< USB Receive Control and Status Endpoint 1 Low */ + }; + + union { + __IO uint8_t RXCSRH1_USB0_ALT; /*!< USB Receive Control and Status Endpoint 1 High */ + __IO uint8_t RXCSRH1; /*!< USB Receive Control and Status Endpoint 1 High */ + }; + __IO uint16_t RXCOUNT1; /*!< USB Receive Byte Count Endpoint 1 */ + __IO uint8_t TXTYPE1; /*!< USB Host Transmit Configure Type Endpoint 1 */ + + union { + __IO uint8_t TXINTERVAL1_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 1 */ + __IO uint8_t TXINTERVAL1; /*!< USB Host Transmit Interval Endpoint 1 */ + }; + __IO uint8_t RXTYPE1; /*!< USB Host Configure Receive Type Endpoint 1 */ + + union { + __IO uint8_t RXINTERVAL1_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 1 */ + __IO uint8_t RXINTERVAL1; /*!< USB Host Receive Polling Interval Endpoint 1 */ + }; + __I uint16_t RESERVED28; + __IO uint16_t TXMAXP2; /*!< USB Maximum Transmit Data Endpoint 2 */ + + union { + __IO uint8_t TXCSRL2_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 2 Low */ + __IO uint8_t TXCSRL2; /*!< USB Transmit Control and Status Endpoint 2 Low */ + }; + __IO uint8_t TXCSRH2; /*!< USB Transmit Control and Status Endpoint 2 High */ + __IO uint16_t RXMAXP2; /*!< USB Maximum Receive Data Endpoint 2 */ + + union { + __IO uint8_t RXCSRL2_USB0_ALT; /*!< USB Receive Control and Status Endpoint 2 Low */ + __IO uint8_t RXCSRL2; /*!< USB Receive Control and Status Endpoint 2 Low */ + }; + + union { + __IO uint8_t RXCSRH2_USB0_ALT; /*!< USB Receive Control and Status Endpoint 2 High */ + __IO uint8_t RXCSRH2; /*!< USB Receive Control and Status Endpoint 2 High */ + }; + __IO uint16_t RXCOUNT2; /*!< USB Receive Byte Count Endpoint 2 */ + __IO uint8_t TXTYPE2; /*!< USB Host Transmit Configure Type Endpoint 2 */ + + union { + __IO uint8_t TXINTERVAL2_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 2 */ + __IO uint8_t TXINTERVAL2; /*!< USB Host Transmit Interval Endpoint 2 */ + }; + __IO uint8_t RXTYPE2; /*!< USB Host Configure Receive Type Endpoint 2 */ + + union { + __IO uint8_t RXINTERVAL2_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 2 */ + __IO uint8_t RXINTERVAL2; /*!< USB Host Receive Polling Interval Endpoint 2 */ + }; + __I uint16_t RESERVED29; + __IO uint16_t TXMAXP3; /*!< USB Maximum Transmit Data Endpoint 3 */ + + union { + __IO uint8_t TXCSRL3_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 3 Low */ + __IO uint8_t TXCSRL3; /*!< USB Transmit Control and Status Endpoint 3 Low */ + }; + __IO uint8_t TXCSRH3; /*!< USB Transmit Control and Status Endpoint 3 High */ + __IO uint16_t RXMAXP3; /*!< USB Maximum Receive Data Endpoint 3 */ + + union { + __IO uint8_t RXCSRL3_USB0_ALT; /*!< USB Receive Control and Status Endpoint 3 Low */ + __IO uint8_t RXCSRL3; /*!< USB Receive Control and Status Endpoint 3 Low */ + }; + + union { + __IO uint8_t RXCSRH3_USB0_ALT; /*!< USB Receive Control and Status Endpoint 3 High */ + __IO uint8_t RXCSRH3; /*!< USB Receive Control and Status Endpoint 3 High */ + }; + __IO uint16_t RXCOUNT3; /*!< USB Receive Byte Count Endpoint 3 */ + __IO uint8_t TXTYPE3; /*!< USB Host Transmit Configure Type Endpoint 3 */ + + union { + __IO uint8_t TXINTERVAL3_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 3 */ + __IO uint8_t TXINTERVAL3; /*!< USB Host Transmit Interval Endpoint 3 */ + }; + __IO uint8_t RXTYPE3; /*!< USB Host Configure Receive Type Endpoint 3 */ + + union { + __IO uint8_t RXINTERVAL3_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 3 */ + __IO uint8_t RXINTERVAL3; /*!< USB Host Receive Polling Interval Endpoint 3 */ + }; + __I uint16_t RESERVED30; + __IO uint16_t TXMAXP4; /*!< USB Maximum Transmit Data Endpoint 4 */ + + union { + __IO uint8_t TXCSRL4_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 4 Low */ + __IO uint8_t TXCSRL4; /*!< USB Transmit Control and Status Endpoint 4 Low */ + }; + __IO uint8_t TXCSRH4; /*!< USB Transmit Control and Status Endpoint 4 High */ + __IO uint16_t RXMAXP4; /*!< USB Maximum Receive Data Endpoint 4 */ + + union { + __IO uint8_t RXCSRL4_USB0_ALT; /*!< USB Receive Control and Status Endpoint 4 Low */ + __IO uint8_t RXCSRL4; /*!< USB Receive Control and Status Endpoint 4 Low */ + }; + + union { + __IO uint8_t RXCSRH4_USB0_ALT; /*!< USB Receive Control and Status Endpoint 4 High */ + __IO uint8_t RXCSRH4; /*!< USB Receive Control and Status Endpoint 4 High */ + }; + __IO uint16_t RXCOUNT4; /*!< USB Receive Byte Count Endpoint 4 */ + __IO uint8_t TXTYPE4; /*!< USB Host Transmit Configure Type Endpoint 4 */ + + union { + __IO uint8_t TXINTERVAL4_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 4 */ + __IO uint8_t TXINTERVAL4; /*!< USB Host Transmit Interval Endpoint 4 */ + }; + __IO uint8_t RXTYPE4; /*!< USB Host Configure Receive Type Endpoint 4 */ + + union { + __IO uint8_t RXINTERVAL4_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 4 */ + __IO uint8_t RXINTERVAL4; /*!< USB Host Receive Polling Interval Endpoint 4 */ + }; + __I uint16_t RESERVED31; + __IO uint16_t TXMAXP5; /*!< USB Maximum Transmit Data Endpoint 5 */ + + union { + __IO uint8_t TXCSRL5_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 5 Low */ + __IO uint8_t TXCSRL5; /*!< USB Transmit Control and Status Endpoint 5 Low */ + }; + __IO uint8_t TXCSRH5; /*!< USB Transmit Control and Status Endpoint 5 High */ + __IO uint16_t RXMAXP5; /*!< USB Maximum Receive Data Endpoint 5 */ + + union { + __IO uint8_t RXCSRL5_USB0_ALT; /*!< USB Receive Control and Status Endpoint 5 Low */ + __IO uint8_t RXCSRL5; /*!< USB Receive Control and Status Endpoint 5 Low */ + }; + + union { + __IO uint8_t RXCSRH5_USB0_ALT; /*!< USB Receive Control and Status Endpoint 5 High */ + __IO uint8_t RXCSRH5; /*!< USB Receive Control and Status Endpoint 5 High */ + }; + __IO uint16_t RXCOUNT5; /*!< USB Receive Byte Count Endpoint 5 */ + __IO uint8_t TXTYPE5; /*!< USB Host Transmit Configure Type Endpoint 5 */ + + union { + __IO uint8_t TXINTERVAL5_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 5 */ + __IO uint8_t TXINTERVAL5; /*!< USB Host Transmit Interval Endpoint 5 */ + }; + __IO uint8_t RXTYPE5; /*!< USB Host Configure Receive Type Endpoint 5 */ + + union { + __IO uint8_t RXINTERVAL5_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 5 */ + __IO uint8_t RXINTERVAL5; /*!< USB Host Receive Polling Interval Endpoint 5 */ + }; + __I uint16_t RESERVED32; + __IO uint16_t TXMAXP6; /*!< USB Maximum Transmit Data Endpoint 6 */ + + union { + __IO uint8_t TXCSRL6_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 6 Low */ + __IO uint8_t TXCSRL6; /*!< USB Transmit Control and Status Endpoint 6 Low */ + }; + __IO uint8_t TXCSRH6; /*!< USB Transmit Control and Status Endpoint 6 High */ + __IO uint16_t RXMAXP6; /*!< USB Maximum Receive Data Endpoint 6 */ + + union { + __IO uint8_t RXCSRL6_USB0_ALT; /*!< USB Receive Control and Status Endpoint 6 Low */ + __IO uint8_t RXCSRL6; /*!< USB Receive Control and Status Endpoint 6 Low */ + }; + + union { + __IO uint8_t RXCSRH6_USB0_ALT; /*!< USB Receive Control and Status Endpoint 6 High */ + __IO uint8_t RXCSRH6; /*!< USB Receive Control and Status Endpoint 6 High */ + }; + __IO uint16_t RXCOUNT6; /*!< USB Receive Byte Count Endpoint 6 */ + __IO uint8_t TXTYPE6; /*!< USB Host Transmit Configure Type Endpoint 6 */ + + union { + __IO uint8_t TXINTERVAL6_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 6 */ + __IO uint8_t TXINTERVAL6; /*!< USB Host Transmit Interval Endpoint 6 */ + }; + __IO uint8_t RXTYPE6; /*!< USB Host Configure Receive Type Endpoint 6 */ + + union { + __IO uint8_t RXINTERVAL6_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 6 */ + __IO uint8_t RXINTERVAL6; /*!< USB Host Receive Polling Interval Endpoint 6 */ + }; + __I uint16_t RESERVED33; + __IO uint16_t TXMAXP7; /*!< USB Maximum Transmit Data Endpoint 7 */ + + union { + __IO uint8_t TXCSRL7_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 7 Low */ + __IO uint8_t TXCSRL7; /*!< USB Transmit Control and Status Endpoint 7 Low */ + }; + __IO uint8_t TXCSRH7; /*!< USB Transmit Control and Status Endpoint 7 High */ + __IO uint16_t RXMAXP7; /*!< USB Maximum Receive Data Endpoint 7 */ + + union { + __IO uint8_t RXCSRL7_USB0_ALT; /*!< USB Receive Control and Status Endpoint 7 Low */ + __IO uint8_t RXCSRL7; /*!< USB Receive Control and Status Endpoint 7 Low */ + }; + + union { + __IO uint8_t RXCSRH7_USB0_ALT; /*!< USB Receive Control and Status Endpoint 7 High */ + __IO uint8_t RXCSRH7; /*!< USB Receive Control and Status Endpoint 7 High */ + }; + __IO uint16_t RXCOUNT7; /*!< USB Receive Byte Count Endpoint 7 */ + __IO uint8_t TXTYPE7; /*!< USB Host Transmit Configure Type Endpoint 7 */ + + union { + __IO uint8_t TXINTERVAL7_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 7 */ + __IO uint8_t TXINTERVAL7; /*!< USB Host Transmit Interval Endpoint 7 */ + }; + __IO uint8_t RXTYPE7; /*!< USB Host Configure Receive Type Endpoint 7 */ + + union { + __IO uint8_t RXINTERVAL7_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 7 */ + __IO uint8_t RXINTERVAL7; /*!< USB Host Receive Polling Interval Endpoint 7 */ + }; + __I uint16_t RESERVED34[195]; + __IO uint16_t RQPKTCOUNT1; /*!< USB Request Packet Count in Block Transfer Endpoint 1 */ + __I uint16_t RESERVED35; + __IO uint16_t RQPKTCOUNT2; /*!< USB Request Packet Count in Block Transfer Endpoint 2 */ + __I uint16_t RESERVED36; + __IO uint16_t RQPKTCOUNT3; /*!< USB Request Packet Count in Block Transfer Endpoint 3 */ + __I uint16_t RESERVED37; + __IO uint16_t RQPKTCOUNT4; /*!< USB Request Packet Count in Block Transfer Endpoint 4 */ + __I uint16_t RESERVED38; + __IO uint16_t RQPKTCOUNT5; /*!< USB Request Packet Count in Block Transfer Endpoint 5 */ + __I uint16_t RESERVED39; + __IO uint16_t RQPKTCOUNT6; /*!< USB Request Packet Count in Block Transfer Endpoint 6 */ + __I uint16_t RESERVED40; + __IO uint16_t RQPKTCOUNT7; /*!< USB Request Packet Count in Block Transfer Endpoint 7 */ + __I uint16_t RESERVED41[17]; + __IO uint16_t RXDPKTBUFDIS; /*!< USB Receive Double Packet Buffer Disable */ + __IO uint16_t TXDPKTBUFDIS; /*!< USB Transmit Double Packet Buffer Disable */ + __I uint32_t RESERVED42[47]; + __IO uint32_t EPC; /*!< USB External Power Control */ + __IO uint32_t EPCRIS; /*!< USB External Power Control Raw Interrupt Status */ + __IO uint32_t EPCIM; /*!< USB External Power Control Interrupt Mask */ + __IO uint32_t EPCISC; /*!< USB External Power Control Interrupt Status and Clear */ + __IO uint32_t DRRIS; /*!< USB Device RESUME Raw Interrupt Status */ + __IO uint32_t DRIM; /*!< USB Device RESUME Interrupt Mask */ + __O uint32_t DRISC; /*!< USB Device RESUME Interrupt Status and Clear */ + __IO uint32_t GPCS; /*!< USB General-Purpose Control and Status */ + __I uint32_t RESERVED43[4]; + __IO uint32_t VDC; /*!< USB VBUS Droop Control */ + __IO uint32_t VDCRIS; /*!< USB VBUS Droop Control Raw Interrupt Status */ + __IO uint32_t VDCIM; /*!< USB VBUS Droop Control Interrupt Mask */ + __IO uint32_t VDCISC; /*!< USB VBUS Droop Control Interrupt Status and Clear */ + __I uint32_t RESERVED44; + __IO uint32_t IDVRIS; /*!< USB ID Valid Detect Raw Interrupt Status */ + __IO uint32_t IDVIM; /*!< USB ID Valid Detect Interrupt Mask */ + __IO uint32_t IDVISC; /*!< USB ID Valid Detect Interrupt Status and Clear */ + __IO uint32_t DMASEL; /*!< USB DMA Select */ + __I uint32_t RESERVED45[731]; + __IO uint32_t PP; /*!< USB Peripheral Properties */ +} USB0_Type; + + +/* ================================================================================ */ +/* ================ EEPROM ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for EEPROM peripheral (EEPROM) + */ + +typedef struct { /*!< EEPROM Structure */ + __IO uint32_t EESIZE; /*!< EEPROM Size Information */ + __IO uint32_t EEBLOCK; /*!< EEPROM Current Block */ + __IO uint32_t EEOFFSET; /*!< EEPROM Current Offset */ + __I uint32_t RESERVED0; + __IO uint32_t EERDWR; /*!< EEPROM Read-Write */ + __IO uint32_t EERDWRINC; /*!< EEPROM Read-Write with Increment */ + __IO uint32_t EEDONE; /*!< EEPROM Done Status */ + __IO uint32_t EESUPP; /*!< EEPROM Support Control and Status */ + __IO uint32_t EEUNLOCK; /*!< EEPROM Unlock */ + __I uint32_t RESERVED1[3]; + __IO uint32_t EEPROT; /*!< EEPROM Protection */ + __IO uint32_t EEPASS0; /*!< EEPROM Password */ + __IO uint32_t EEPASS1; /*!< EEPROM Password */ + __IO uint32_t EEPASS2; /*!< EEPROM Password */ + __IO uint32_t EEINT; /*!< EEPROM Interrupt */ + __I uint32_t RESERVED2[3]; + __IO uint32_t EEHIDE; /*!< EEPROM Block Hide */ + __I uint32_t RESERVED3[11]; + __IO uint32_t EEDBGME; /*!< EEPROM Debug Mass Erase */ + __I uint32_t RESERVED4[975]; + __IO uint32_t PP; /*!< EEPROM Peripheral Properties */ +} EEPROM_Type; + + +/* ================================================================================ */ +/* ================ SYSEXC ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for SYSEXC peripheral (SYSEXC) + */ + +typedef struct { /*!< SYSEXC Structure */ + __IO uint32_t RIS; /*!< System Exception Raw Interrupt Status */ + __IO uint32_t IM; /*!< System Exception Interrupt Mask */ + __IO uint32_t MIS; /*!< System Exception Masked Interrupt Status */ + __O uint32_t IC; /*!< System Exception Interrupt Clear */ +} SYSEXC_Type; + + +/* ================================================================================ */ +/* ================ HIB ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for HIB peripheral (HIB) + */ + +typedef struct { /*!< HIB Structure */ + __IO uint32_t RTCC; /*!< Hibernation RTC Counter */ + __IO uint32_t RTCM0; /*!< Hibernation RTC Match 0 */ + __I uint32_t RESERVED0; + __IO uint32_t RTCLD; /*!< Hibernation RTC Load */ + __IO uint32_t CTL; /*!< Hibernation Control */ + __IO uint32_t IM; /*!< Hibernation Interrupt Mask */ + __IO uint32_t RIS; /*!< Hibernation Raw Interrupt Status */ + __IO uint32_t MIS; /*!< Hibernation Masked Interrupt Status */ + __IO uint32_t IC; /*!< Hibernation Interrupt Clear */ + __IO uint32_t RTCT; /*!< Hibernation RTC Trim */ + __IO uint32_t RTCSS; /*!< Hibernation RTC Sub Seconds */ + __I uint32_t RESERVED1; + __IO uint32_t DATA; /*!< Hibernation Data */ +} HIB_Type; + + +/* ================================================================================ */ +/* ================ FLASH_CTRL ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for FLASH_CTRL peripheral (FLASH_CTRL) + */ + +typedef struct { /*!< FLASH_CTRL Structure */ + __IO uint32_t FMA; /*!< Flash Memory Address */ + __IO uint32_t FMD; /*!< Flash Memory Data */ + __IO uint32_t FMC; /*!< Flash Memory Control */ + __IO uint32_t FCRIS; /*!< Flash Controller Raw Interrupt Status */ + __IO uint32_t FCIM; /*!< Flash Controller Interrupt Mask */ + __IO uint32_t FCMISC; /*!< Flash Controller Masked Interrupt Status and Clear */ + __I uint32_t RESERVED0[2]; + __IO uint32_t FMC2; /*!< Flash Memory Control 2 */ + __I uint32_t RESERVED1[3]; + __IO uint32_t FWBVAL; /*!< Flash Write Buffer Valid */ + __I uint32_t RESERVED2[51]; + __IO uint32_t FWBN; /*!< Flash Write Buffer n */ + __I uint32_t RESERVED3[943]; + __IO uint32_t FSIZE; /*!< Flash Size */ + __IO uint32_t SSIZE; /*!< SRAM Size */ + __I uint32_t RESERVED4; + + union { + __IO uint32_t ROMSWMAP_FLASH_CTRL_ALT; /*!< ROM Software Map */ + __IO uint32_t ROMSWMAP; /*!< ROM Software Map */ + }; + __I uint32_t RESERVED5[72]; + __IO uint32_t RMCTL; /*!< ROM Control */ + __I uint32_t RESERVED6[55]; + __IO uint32_t BOOTCFG; /*!< Boot Configuration */ + __I uint32_t RESERVED7[3]; + __IO uint32_t USERREG0; /*!< User Register 0 */ + __IO uint32_t USERREG1; /*!< User Register 1 */ + __IO uint32_t USERREG2; /*!< User Register 2 */ + __IO uint32_t USERREG3; /*!< User Register 3 */ + __I uint32_t RESERVED8[4]; + __IO uint32_t FMPRE0; /*!< Flash Memory Protection Read Enable 0 */ + __IO uint32_t FMPRE1; /*!< Flash Memory Protection Read Enable 1 */ + __IO uint32_t FMPRE2; /*!< Flash Memory Protection Read Enable 2 */ + __IO uint32_t FMPRE3; /*!< Flash Memory Protection Read Enable 3 */ + __I uint32_t RESERVED9[124]; + __IO uint32_t FMPPE0; /*!< Flash Memory Protection Program Enable 0 */ + __IO uint32_t FMPPE1; /*!< Flash Memory Protection Program Enable 1 */ + __IO uint32_t FMPPE2; /*!< Flash Memory Protection Program Enable 2 */ + __IO uint32_t FMPPE3; /*!< Flash Memory Protection Program Enable 3 */ +} FLASH_CTRL_Type; + + +/* ================================================================================ */ +/* ================ SYSCTL ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for SYSCTL peripheral (SYSCTL) + */ + +typedef struct { /*!< SYSCTL Structure */ + __IO uint32_t DID0; /*!< Device Identification 0 */ + __IO uint32_t DID1; /*!< Device Identification 1 */ + __IO uint32_t DC0; /*!< Device Capabilities 0 */ + __I uint32_t RESERVED0; + __IO uint32_t DC1; /*!< Device Capabilities 1 */ + __IO uint32_t DC2; /*!< Device Capabilities 2 */ + __IO uint32_t DC3; /*!< Device Capabilities 3 */ + __IO uint32_t DC4; /*!< Device Capabilities 4 */ + __IO uint32_t DC5; /*!< Device Capabilities 5 */ + __IO uint32_t DC6; /*!< Device Capabilities 6 */ + __IO uint32_t DC7; /*!< Device Capabilities 7 */ + __IO uint32_t DC8; /*!< Device Capabilities 8 */ + __IO uint32_t PBORCTL; /*!< Brown-Out Reset Control */ + __I uint32_t RESERVED1[3]; + __IO uint32_t SRCR0; /*!< Software Reset Control 0 */ + __IO uint32_t SRCR1; /*!< Software Reset Control 1 */ + __IO uint32_t SRCR2; /*!< Software Reset Control 2 */ + __I uint32_t RESERVED2; + __IO uint32_t RIS; /*!< Raw Interrupt Status */ + __IO uint32_t IMC; /*!< Interrupt Mask Control */ + __IO uint32_t MISC; /*!< Masked Interrupt Status and Clear */ + __IO uint32_t RESC; /*!< Reset Cause */ + __IO uint32_t RCC; /*!< Run-Mode Clock Configuration */ + __I uint32_t RESERVED3[2]; + __IO uint32_t GPIOHBCTL; /*!< GPIO High-Performance Bus Control */ + __IO uint32_t RCC2; /*!< Run-Mode Clock Configuration 2 */ + __I uint32_t RESERVED4[2]; + __IO uint32_t MOSCCTL; /*!< Main Oscillator Control */ + __I uint32_t RESERVED5[32]; + __IO uint32_t RCGC0; /*!< Run Mode Clock Gating Control Register 0 */ + __IO uint32_t RCGC1; /*!< Run Mode Clock Gating Control Register 1 */ + __IO uint32_t RCGC2; /*!< Run Mode Clock Gating Control Register 2 */ + __I uint32_t RESERVED6; + __IO uint32_t SCGC0; /*!< Sleep Mode Clock Gating Control Register 0 */ + __IO uint32_t SCGC1; /*!< Sleep Mode Clock Gating Control Register 1 */ + __IO uint32_t SCGC2; /*!< Sleep Mode Clock Gating Control Register 2 */ + __I uint32_t RESERVED7; + __IO uint32_t DCGC0; /*!< Deep Sleep Mode Clock Gating Control Register 0 */ + __IO uint32_t DCGC1; /*!< Deep-Sleep Mode Clock Gating Control Register 1 */ + __IO uint32_t DCGC2; /*!< Deep Sleep Mode Clock Gating Control Register 2 */ + __I uint32_t RESERVED8[6]; + __IO uint32_t DSLPCLKCFG; /*!< Deep Sleep Clock Configuration */ + __I uint32_t RESERVED9; + __IO uint32_t SYSPROP; /*!< System Properties */ + __IO uint32_t PIOSCCAL; /*!< Precision Internal Oscillator Calibration */ + __IO uint32_t PIOSCSTAT; /*!< Precision Internal Oscillator Statistics */ + __I uint32_t RESERVED10[2]; + __IO uint32_t PLLFREQ0; /*!< PLL Frequency 0 */ + __IO uint32_t PLLFREQ1; /*!< PLL Frequency 1 */ + __IO uint32_t PLLSTAT; /*!< PLL Status */ + __I uint32_t RESERVED11[7]; + __IO uint32_t SLPPWRCFG; /*!< Sleep Power Configuration */ + __IO uint32_t DSLPPWRCFG; /*!< Deep-Sleep Power Configuration */ + __IO uint32_t DC9; /*!< Device Capabilities 9 */ + __I uint32_t RESERVED12[3]; + __IO uint32_t NVMSTAT; /*!< Non-Volatile Memory Information */ + __I uint32_t RESERVED13[4]; + __IO uint32_t LDOSPCTL; /*!< LDO Sleep Power Control */ + __I uint32_t RESERVED14; + __IO uint32_t LDODPCTL; /*!< LDO Deep-Sleep Power Control */ + __I uint32_t RESERVED15[80]; + __IO uint32_t PPWD; /*!< Watchdog Timer Peripheral Present */ + __IO uint32_t PPTIMER; /*!< 16/32-Bit General-Purpose Timer Peripheral Present */ + __IO uint32_t PPGPIO; /*!< General-Purpose Input/Output Peripheral Present */ + __IO uint32_t PPDMA; /*!< Micro Direct Memory Access Peripheral Present */ + __I uint32_t RESERVED16; + __IO uint32_t PPHIB; /*!< Hibernation Peripheral Present */ + __IO uint32_t PPUART; /*!< Universal Asynchronous Receiver/Transmitter Peripheral Present */ + __IO uint32_t PPSSI; /*!< Synchronous Serial Interface Peripheral Present */ + __IO uint32_t PPI2C; /*!< Inter-Integrated Circuit Peripheral Present */ + __I uint32_t RESERVED17; + __IO uint32_t PPUSB; /*!< Universal Serial Bus Peripheral Present */ + __I uint32_t RESERVED18[2]; + __IO uint32_t PPCAN; /*!< Controller Area Network Peripheral Present */ + __IO uint32_t PPADC; /*!< Analog-to-Digital Converter Peripheral Present */ + __IO uint32_t PPACMP; /*!< Analog Comparator Peripheral Present */ + __IO uint32_t PPPWM; /*!< Pulse Width Modulator Peripheral Present */ + __IO uint32_t PPQEI; /*!< Quadrature Encoder Interface Peripheral Present */ + __I uint32_t RESERVED19[4]; + __IO uint32_t PPEEPROM; /*!< EEPROM Peripheral Present */ + __IO uint32_t PPWTIMER; /*!< 32/64-Bit Wide General-Purpose Timer Peripheral Present */ + __I uint32_t RESERVED20[104]; + __IO uint32_t SRWD; /*!< Watchdog Timer Software Reset */ + __IO uint32_t SRTIMER; /*!< 16/32-Bit General-Purpose Timer Software Reset */ + __IO uint32_t SRGPIO; /*!< General-Purpose Input/Output Software Reset */ + __IO uint32_t SRDMA; /*!< Micro Direct Memory Access Software Reset */ + __I uint32_t RESERVED21; + __IO uint32_t SRHIB; /*!< Hibernation Software Reset */ + __IO uint32_t SRUART; /*!< Universal Asynchronous Receiver/Transmitter Software Reset */ + __IO uint32_t SRSSI; /*!< Synchronous Serial Interface Software Reset */ + __IO uint32_t SRI2C; /*!< Inter-Integrated Circuit Software Reset */ + __I uint32_t RESERVED22; + __IO uint32_t SRUSB; /*!< Universal Serial Bus Software Reset */ + __I uint32_t RESERVED23[2]; + __IO uint32_t SRCAN; /*!< Controller Area Network Software Reset */ + __IO uint32_t SRADC; /*!< Analog-to-Digital Converter Software Reset */ + __IO uint32_t SRACMP; /*!< Analog Comparator Software Reset */ + __IO uint32_t SRPWM; /*!< Pulse Width Modulator Software Reset */ + __IO uint32_t SRQEI; /*!< Quadrature Encoder Interface Software Reset */ + __I uint32_t RESERVED24[4]; + __IO uint32_t SREEPROM; /*!< EEPROM Software Reset */ + __IO uint32_t SRWTIMER; /*!< 32/64-Bit Wide General-Purpose Timer Software Reset */ + __I uint32_t RESERVED25[40]; + __IO uint32_t RCGCWD; /*!< Watchdog Timer Run Mode Clock Gating Control */ + __IO uint32_t RCGCTIMER; /*!< 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control */ + __IO uint32_t RCGCGPIO; /*!< General-Purpose Input/Output Run Mode Clock Gating Control */ + __IO uint32_t RCGCDMA; /*!< Micro Direct Memory Access Run Mode Clock Gating Control */ + __I uint32_t RESERVED26; + __IO uint32_t RCGCHIB; /*!< Hibernation Run Mode Clock Gating Control */ + __IO uint32_t RCGCUART; /*!< Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating + Control */ + __IO uint32_t RCGCSSI; /*!< Synchronous Serial Interface Run Mode Clock Gating Control */ + __IO uint32_t RCGCI2C; /*!< Inter-Integrated Circuit Run Mode Clock Gating Control */ + __I uint32_t RESERVED27; + __IO uint32_t RCGCUSB; /*!< Universal Serial Bus Run Mode Clock Gating Control */ + __I uint32_t RESERVED28[2]; + __IO uint32_t RCGCCAN; /*!< Controller Area Network Run Mode Clock Gating Control */ + __IO uint32_t RCGCADC; /*!< Analog-to-Digital Converter Run Mode Clock Gating Control */ + __IO uint32_t RCGCACMP; /*!< Analog Comparator Run Mode Clock Gating Control */ + __IO uint32_t RCGCPWM; /*!< Pulse Width Modulator Run Mode Clock Gating Control */ + __IO uint32_t RCGCQEI; /*!< Quadrature Encoder Interface Run Mode Clock Gating Control */ + __I uint32_t RESERVED29[4]; + __IO uint32_t RCGCEEPROM; /*!< EEPROM Run Mode Clock Gating Control */ + __IO uint32_t RCGCWTIMER; /*!< 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control */ + __I uint32_t RESERVED30[40]; + __IO uint32_t SCGCWD; /*!< Watchdog Timer Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCTIMER; /*!< 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCGPIO; /*!< General-Purpose Input/Output Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCDMA; /*!< Micro Direct Memory Access Sleep Mode Clock Gating Control */ + __I uint32_t RESERVED31; + __IO uint32_t SCGCHIB; /*!< Hibernation Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCUART; /*!< Universal Asynchronous Receiver/Transmitter Sleep Mode Clock + Gating Control */ + __IO uint32_t SCGCSSI; /*!< Synchronous Serial Interface Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCI2C; /*!< Inter-Integrated Circuit Sleep Mode Clock Gating Control */ + __I uint32_t RESERVED32; + __IO uint32_t SCGCUSB; /*!< Universal Serial Bus Sleep Mode Clock Gating Control */ + __I uint32_t RESERVED33[2]; + __IO uint32_t SCGCCAN; /*!< Controller Area Network Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCADC; /*!< Analog-to-Digital Converter Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCACMP; /*!< Analog Comparator Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCPWM; /*!< Pulse Width Modulator Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCQEI; /*!< Quadrature Encoder Interface Sleep Mode Clock Gating Control */ + __I uint32_t RESERVED34[4]; + __IO uint32_t SCGCEEPROM; /*!< EEPROM Sleep Mode Clock Gating Control */ + __IO uint32_t SCGCWTIMER; /*!< 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating + Control */ + __I uint32_t RESERVED35[40]; + __IO uint32_t DCGCWD; /*!< Watchdog Timer Deep-Sleep Mode Clock Gating Control */ + __IO uint32_t DCGCTIMER; /*!< 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating + Control */ + __IO uint32_t DCGCGPIO; /*!< General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control */ + __IO uint32_t DCGCDMA; /*!< Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control */ + __I uint32_t RESERVED36; + __IO uint32_t DCGCHIB; /*!< Hibernation Deep-Sleep Mode Clock Gating Control */ + __IO uint32_t DCGCUART; /*!< Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode + Clock Gating Control */ + __IO uint32_t DCGCSSI; /*!< Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control */ + __IO uint32_t DCGCI2C; /*!< Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control */ + __I uint32_t RESERVED37; + __IO uint32_t DCGCUSB; /*!< Universal Serial Bus Deep-Sleep Mode Clock Gating Control */ + __I uint32_t RESERVED38[2]; + __IO uint32_t DCGCCAN; /*!< Controller Area Network Deep-Sleep Mode Clock Gating Control */ + __IO uint32_t DCGCADC; /*!< Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control */ + __IO uint32_t DCGCACMP; /*!< Analog Comparator Deep-Sleep Mode Clock Gating Control */ + __IO uint32_t DCGCPWM; /*!< Pulse Width Modulator Deep-Sleep Mode Clock Gating Control */ + __IO uint32_t DCGCQEI; /*!< Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control */ + __I uint32_t RESERVED39[4]; + __IO uint32_t DCGCEEPROM; /*!< EEPROM Deep-Sleep Mode Clock Gating Control */ + __IO uint32_t DCGCWTIMER; /*!< 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating + Control */ + __I uint32_t RESERVED40[104]; + __IO uint32_t PRWD; /*!< Watchdog Timer Peripheral Ready */ + __IO uint32_t PRTIMER; /*!< 16/32-Bit General-Purpose Timer Peripheral Ready */ + __IO uint32_t PRGPIO; /*!< General-Purpose Input/Output Peripheral Ready */ + __IO uint32_t PRDMA; /*!< Micro Direct Memory Access Peripheral Ready */ + __I uint32_t RESERVED41; + __IO uint32_t PRHIB; /*!< Hibernation Peripheral Ready */ + __IO uint32_t PRUART; /*!< Universal Asynchronous Receiver/Transmitter Peripheral Ready */ + __IO uint32_t PRSSI; /*!< Synchronous Serial Interface Peripheral Ready */ + __IO uint32_t PRI2C; /*!< Inter-Integrated Circuit Peripheral Ready */ + __I uint32_t RESERVED42; + __IO uint32_t PRUSB; /*!< Universal Serial Bus Peripheral Ready */ + __I uint32_t RESERVED43[2]; + __IO uint32_t PRCAN; /*!< Controller Area Network Peripheral Ready */ + __IO uint32_t PRADC; /*!< Analog-to-Digital Converter Peripheral Ready */ + __IO uint32_t PRACMP; /*!< Analog Comparator Peripheral Ready */ + __IO uint32_t PRPWM; /*!< Pulse Width Modulator Peripheral Ready */ + __IO uint32_t PRQEI; /*!< Quadrature Encoder Interface Peripheral Ready */ + __I uint32_t RESERVED44[4]; + __IO uint32_t PREEPROM; /*!< EEPROM Peripheral Ready */ + __IO uint32_t PRWTIMER; /*!< 32/64-Bit Wide General-Purpose Timer Peripheral Ready */ +} SYSCTL_Type; + + +/* ================================================================================ */ +/* ================ UDMA ================ */ +/* ================================================================================ */ + + +/** + * @brief Register map for UDMA peripheral (UDMA) + */ + +typedef struct { /*!< UDMA Structure */ + __IO uint32_t STAT; /*!< DMA Status */ + __O uint32_t CFG; /*!< DMA Configuration */ + __IO uint32_t CTLBASE; /*!< DMA Channel Control Base Pointer */ + __IO uint32_t ALTBASE; /*!< DMA Alternate Channel Control Base Pointer */ + __IO uint32_t WAITSTAT; /*!< DMA Channel Wait-on-Request Status */ + __O uint32_t SWREQ; /*!< DMA Channel Software Request */ + __IO uint32_t USEBURSTSET; /*!< DMA Channel Useburst Set */ + __O uint32_t USEBURSTCLR; /*!< DMA Channel Useburst Clear */ + __IO uint32_t REQMASKSET; /*!< DMA Channel Request Mask Set */ + __O uint32_t REQMASKCLR; /*!< DMA Channel Request Mask Clear */ + __IO uint32_t ENASET; /*!< DMA Channel Enable Set */ + __O uint32_t ENACLR; /*!< DMA Channel Enable Clear */ + __IO uint32_t ALTSET; /*!< DMA Channel Primary Alternate Set */ + __O uint32_t ALTCLR; /*!< DMA Channel Primary Alternate Clear */ + __IO uint32_t PRIOSET; /*!< DMA Channel Priority Set */ + __O uint32_t PRIOCLR; /*!< DMA Channel Priority Clear */ + __I uint32_t RESERVED0[3]; + __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear */ + __I uint32_t RESERVED1[300]; + __IO uint32_t CHASGN; /*!< DMA Channel Assignment */ + __IO uint32_t CHIS; /*!< DMA Channel Interrupt Status */ + __I uint32_t RESERVED2[2]; + __IO uint32_t CHMAP0; /*!< DMA Channel Map Select 0 */ + __IO uint32_t CHMAP1; /*!< DMA Channel Map Select 1 */ + __IO uint32_t CHMAP2; /*!< DMA Channel Map Select 2 */ + __IO uint32_t CHMAP3; /*!< DMA Channel Map Select 3 */ +} UDMA_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + /* anonymous unions are enabled by default */ +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define WATCHDOG0_BASE 0x40000000UL +#define WATCHDOG1_BASE 0x40001000UL +#define GPIOA_BASE 0x40004000UL +#define GPIOB_BASE 0x40005000UL +#define GPIOC_BASE 0x40006000UL +#define GPIOD_BASE 0x40007000UL +#define SSI0_BASE 0x40008000UL +#define SSI1_BASE 0x40009000UL +#define SSI2_BASE 0x4000A000UL +#define SSI3_BASE 0x4000B000UL +#define UART0_BASE 0x4000C000UL +#define UART1_BASE 0x4000D000UL +#define UART2_BASE 0x4000E000UL +#define UART3_BASE 0x4000F000UL +#define UART4_BASE 0x40010000UL +#define UART5_BASE 0x40011000UL +#define UART6_BASE 0x40012000UL +#define UART7_BASE 0x40013000UL +#define I2C0_BASE 0x40020000UL +#define I2C1_BASE 0x40021000UL +#define I2C2_BASE 0x40022000UL +#define I2C3_BASE 0x40023000UL +#define GPIOE_BASE 0x40024000UL +#define GPIOF_BASE 0x40025000UL +#define PWM0_BASE 0x40028000UL +#define PWM1_BASE 0x40029000UL +#define QEI0_BASE 0x4002C000UL +#define QEI1_BASE 0x4002D000UL +#define TIMER0_BASE 0x40030000UL +#define TIMER1_BASE 0x40031000UL +#define TIMER2_BASE 0x40032000UL +#define TIMER3_BASE 0x40033000UL +#define TIMER4_BASE 0x40034000UL +#define TIMER5_BASE 0x40035000UL +#define WTIMER0_BASE 0x40036000UL +#define WTIMER1_BASE 0x40037000UL +#define ADC0_BASE 0x40038000UL +#define ADC1_BASE 0x40039000UL +#define COMP_BASE 0x4003C000UL +#define CAN0_BASE 0x40040000UL +#define CAN1_BASE 0x40041000UL +#define WTIMER2_BASE 0x4004C000UL +#define WTIMER3_BASE 0x4004D000UL +#define WTIMER4_BASE 0x4004E000UL +#define WTIMER5_BASE 0x4004F000UL +#define USB0_BASE 0x40050000UL +#define GPIOA_AHB_BASE 0x40058000UL +#define GPIOB_AHB_BASE 0x40059000UL +#define GPIOC_AHB_BASE 0x4005A000UL +#define GPIOD_AHB_BASE 0x4005B000UL +#define GPIOE_AHB_BASE 0x4005C000UL +#define GPIOF_AHB_BASE 0x4005D000UL +#define EEPROM_BASE 0x400AF000UL +#define SYSEXC_BASE 0x400F9000UL +#define HIB_BASE 0x400FC000UL +#define FLASH_CTRL_BASE 0x400FD000UL +#define SYSCTL_BASE 0x400FE000UL +#define UDMA_BASE 0x400FF000UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define WATCHDOG0 ((WATCHDOG0_Type *) WATCHDOG0_BASE) +#define WATCHDOG1 ((WATCHDOG0_Type *) WATCHDOG1_BASE) +#define GPIOA ((GPIOA_Type *) GPIOA_BASE) +#define GPIOB ((GPIOA_Type *) GPIOB_BASE) +#define GPIOC ((GPIOA_Type *) GPIOC_BASE) +#define GPIOD ((GPIOA_Type *) GPIOD_BASE) +#define SSI0 ((SSI0_Type *) SSI0_BASE) +#define SSI1 ((SSI0_Type *) SSI1_BASE) +#define SSI2 ((SSI0_Type *) SSI2_BASE) +#define SSI3 ((SSI0_Type *) SSI3_BASE) +#define UART0 ((UART0_Type *) UART0_BASE) +#define UART1 ((UART0_Type *) UART1_BASE) +#define UART2 ((UART0_Type *) UART2_BASE) +#define UART3 ((UART0_Type *) UART3_BASE) +#define UART4 ((UART0_Type *) UART4_BASE) +#define UART5 ((UART0_Type *) UART5_BASE) +#define UART6 ((UART0_Type *) UART6_BASE) +#define UART7 ((UART0_Type *) UART7_BASE) +#define I2C0 ((I2C0_Type *) I2C0_BASE) +#define I2C1 ((I2C0_Type *) I2C1_BASE) +#define I2C2 ((I2C0_Type *) I2C2_BASE) +#define I2C3 ((I2C0_Type *) I2C3_BASE) +#define GPIOE ((GPIOA_Type *) GPIOE_BASE) +#define GPIOF ((GPIOA_Type *) GPIOF_BASE) +#define PWM0 ((PWM0_Type *) PWM0_BASE) +#define PWM1 ((PWM0_Type *) PWM1_BASE) +#define QEI0 ((QEI0_Type *) QEI0_BASE) +#define QEI1 ((QEI0_Type *) QEI1_BASE) +#define TIMER0 ((TIMER0_Type *) TIMER0_BASE) +#define TIMER1 ((TIMER0_Type *) TIMER1_BASE) +#define TIMER2 ((TIMER0_Type *) TIMER2_BASE) +#define TIMER3 ((TIMER0_Type *) TIMER3_BASE) +#define TIMER4 ((TIMER0_Type *) TIMER4_BASE) +#define TIMER5 ((TIMER0_Type *) TIMER5_BASE) +#define WTIMER0 ((WTIMER0_Type *) WTIMER0_BASE) +#define WTIMER1 ((TIMER0_Type *) WTIMER1_BASE) +#define ADC0 ((ADC0_Type *) ADC0_BASE) +#define ADC1 ((ADC0_Type *) ADC1_BASE) +#define COMP ((COMP_Type *) COMP_BASE) +#define CAN0 ((CAN0_Type *) CAN0_BASE) +#define CAN1 ((CAN0_Type *) CAN1_BASE) +#define WTIMER2 ((TIMER0_Type *) WTIMER2_BASE) +#define WTIMER3 ((TIMER0_Type *) WTIMER3_BASE) +#define WTIMER4 ((TIMER0_Type *) WTIMER4_BASE) +#define WTIMER5 ((TIMER0_Type *) WTIMER5_BASE) +#define USB0 ((USB0_Type *) USB0_BASE) +#define GPIOA_AHB ((GPIOA_Type *) GPIOA_AHB_BASE) +#define GPIOB_AHB ((GPIOA_Type *) GPIOB_AHB_BASE) +#define GPIOC_AHB ((GPIOA_Type *) GPIOC_AHB_BASE) +#define GPIOD_AHB ((GPIOA_Type *) GPIOD_AHB_BASE) +#define GPIOE_AHB ((GPIOA_Type *) GPIOE_AHB_BASE) +#define GPIOF_AHB ((GPIOA_Type *) GPIOF_AHB_BASE) +#define EEPROM ((EEPROM_Type *) EEPROM_BASE) +#define SYSEXC ((SYSEXC_Type *) SYSEXC_BASE) +#define HIB ((HIB_Type *) HIB_BASE) +#define FLASH_CTRL ((FLASH_CTRL_Type *) FLASH_CTRL_BASE) +#define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE) +#define UDMA ((UDMA_Type *) UDMA_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group TM4C123GH6PM */ +/** @} */ /* End of group Texas Instruments */ + +#ifdef __cplusplus +} +#endif + + +#endif /* TM4C123GH6PM_H */ + diff --git a/3rd_party/ek-tm4c123gxl/arm/startup_TM4C123GH6PM.s b/3rd_party/ek-tm4c123gxl/arm/startup_TM4C123GH6PM.s new file mode 100644 index 0000000..4a99552 --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/arm/startup_TM4C123GH6PM.s @@ -0,0 +1,716 @@ +;/***************************************************************************/ +; * @file startup_TM4C123GH6PM.s for ARM-KEIL ARM assembler +; * @brief CMSIS Cortex-M4F Core Device Startup File for TM4C123GH6PM +; * @version CMSIS 4.3.0 +; * @date 20 August 2015 +; * +; * Modified by Quantum Leaps: +; * Added assert_failed() and DBC_fault_handler() +; * Added relocating of the Vector Table to free up the 256B region at 0x0 +; * for NULL-pointer protection by the MPU. +; * +; * @description +; * Created from the CMSIS template for the specified device +; * Quantum Leaps, www.state-machine.com +; * +; * @note +; * The symbols Stack_Size and Heap_Size should be provided on the command- +; * line options to the assembler, for example as: +; * --pd "Stack_Size SETA 512" --pd "Heap_Size SETA 0" +; * +; * @note +; * The function assert_failed defined at the end of this file defines +; * the error/assertion handling policy for the application and might +; * need to be customized for each project. This function is defined in +; * assembly to re-set the stack pointer, in case it is corrupted by the +; * time assert_failed is called. +; * +; ***************************************************************************/ +;/* Copyright (c) 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;---------------------------------------------------------------------------*/ + +;****************************************************************************** +; +; Allocate space for the stack. +; +;****************************************************************************** + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_base +StackMem + SPACE Stack_Size ; provided in command-line option, for example: + ; --pd "Stack_Size SETA 512" +__stack_limit +__initial_sp + +;****************************************************************************** +; +; Allocate space for the heap. +; +;****************************************************************************** + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE Heap_Size ; provided in command-line option, for example: + ; --pd "Heap_Size SETA 0" +__heap_limit + +;****************************************************************************** +; +; Indicate that the code in this file preserves 8-byte alignment of the stack. +; +;****************************************************************************** + PRESERVE8 + +;****************************************************************************** +; +; Place code into the reset code section. +; +;****************************************************************************** + AREA RESET, DATA, READONLY, ALIGN=8 + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +;****************************************************************************** +; +; The vector table. +; +;****************************************************************************** +__Vectors + ; Initial Vector Table before relocation + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU fault handler + DCD BusFault_Handler ; Bus fault handler + DCD UsageFault_Handler ; Usage fault handler + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD SVC_Handler ; SVCall handler + DCD DebugMon_Handler ; Debug Monitor handler + DCD Default_Handler ; Reserved + DCD PendSV_Handler ; PendSV handler + DCD SysTick_Handler ; SysTick handler + ALIGN 256 ; Extend the initial Vector Table to the 256B boundary + + ; Relocated Vector Table beyond the 256B region around address 0. + ; That region is used for NULL-pointer protection by the MPU. +__relocated_vector_table + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU fault handler + DCD BusFault_Handler ; Bus fault handler + DCD UsageFault_Handler ; Usage fault handler + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD SVC_Handler ; SVCall handler + DCD DebugMon_Handler ; Debug Monitor handler + DCD Default_Handler ; Reserved + DCD PendSV_Handler ; PendSV handler + DCD SysTick_Handler ; SysTick handler + + ; IRQ handlers... + DCD GPIOPortA_IRQHandler ; GPIO Port A + DCD GPIOPortB_IRQHandler ; GPIO Port B + DCD GPIOPortC_IRQHandler ; GPIO Port C + DCD GPIOPortD_IRQHandler ; GPIO Port D + DCD GPIOPortE_IRQHandler ; GPIO Port E + DCD UART0_IRQHandler ; UART0 Rx and Tx + DCD UART1_IRQHandler ; UART1 Rx and Tx + DCD SSI0_IRQHandler ; SSI0 Rx and Tx + DCD I2C0_IRQHandler ; I2C0 Master and Slave + DCD PWMFault_IRQHandler ; PWM Fault + DCD PWMGen0_IRQHandler ; PWM Generator 0 + DCD PWMGen1_IRQHandler ; PWM Generator 1 + DCD PWMGen2_IRQHandler ; PWM Generator 2 + DCD QEI0_IRQHandler ; Quadrature Encoder 0 + DCD ADCSeq0_IRQHandler ; ADC Sequence 0 + DCD ADCSeq1_IRQHandler ; ADC Sequence 1 + DCD ADCSeq2_IRQHandler ; ADC Sequence 2 + DCD ADCSeq3_IRQHandler ; ADC Sequence 3 + DCD Watchdog_IRQHandler ; Watchdog timer + DCD Timer0A_IRQHandler ; Timer 0 subtimer A + DCD Timer0B_IRQHandler ; Timer 0 subtimer B + DCD Timer1A_IRQHandler ; Timer 1 subtimer A + DCD Timer1B_IRQHandler ; Timer 1 subtimer B + DCD Timer2A_IRQHandler ; Timer 2 subtimer A + DCD Timer2B_IRQHandler ; Timer 2 subtimer B + DCD Comp0_IRQHandler ; Analog Comparator 0 + DCD Comp1_IRQHandler ; Analog Comparator 1 + DCD Comp2_IRQHandler ; Analog Comparator 2 + DCD SysCtrl_IRQHandler ; System Control (PLL, OSC, BO) + DCD FlashCtrl_IRQHandler ; FLASH Control + DCD GPIOPortF_IRQHandler ; GPIO Port F + DCD GPIOPortG_IRQHandler ; GPIO Port G + DCD GPIOPortH_IRQHandler ; GPIO Port H + DCD UART2_IRQHandler ; UART2 Rx and Tx + DCD SSI1_IRQHandler ; SSI1 Rx and Tx + DCD Timer3A_IRQHandler ; Timer 3 subtimer A + DCD Timer3B_IRQHandler ; Timer 3 subtimer B + DCD I2C1_IRQHandler ; I2C1 Master and Slave + DCD QEI1_IRQHandler ; Quadrature Encoder 1 + DCD CAN0_IRQHandler ; CAN0 + DCD CAN1_IRQHandler ; CAN1 + DCD CAN2_IRQHandler ; CAN2 + DCD Default_Handler ; Reserved + DCD Hibernate_IRQHandler ; Hibernate + DCD USB0_IRQHandler ; USB0 + DCD PWMGen3_IRQHandler ; PWM Generator 3 + DCD uDMAST_IRQHandler ; uDMA Software Transfer + DCD uDMAError_IRQHandler ; uDMA Error + DCD ADC1Seq0_IRQHandler ; ADC1 Sequence 0 + DCD ADC1Seq1_IRQHandler ; ADC1 Sequence 1 + DCD ADC1Seq2_IRQHandler ; ADC1 Sequence 2 + DCD ADC1Seq3_IRQHandler ; ADC1 Sequence 3 + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD GPIOPortJ_IRQHandler ; GPIO Port J + DCD GPIOPortK_IRQHandler ; GPIO Port K + DCD GPIOPortL_IRQHandler ; GPIO Port L + DCD SSI2_IRQHandler ; SSI2 Rx and Tx + DCD SSI3_IRQHandler ; SSI3 Rx and Tx + DCD UART3_IRQHandler ; UART3 Rx and Tx + DCD UART4_IRQHandler ; UART4 Rx and Tx + DCD UART5_IRQHandler ; UART5 Rx and Tx + DCD UART6_IRQHandler ; UART6 Rx and Tx + DCD UART7_IRQHandler ; UART7 Rx and Tx + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD I2C2_IRQHandler ; I2C2 Master and Slave + DCD I2C3_IRQHandler ; I2C3 Master and Slave + DCD Timer4A_IRQHandler ; Timer 4 subtimer A + DCD Timer4B_IRQHandler ; Timer 4 subtimer B + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Timer5A_IRQHandler ; Timer 5 subtimer A + DCD Timer5B_IRQHandler ; Timer 5 subtimer B + DCD WideTimer0A_IRQHandler ; Wide Timer 0 subtimer A + DCD WideTimer0B_IRQHandler ; Wide Timer 0 subtimer B + DCD WideTimer1A_IRQHandler ; Wide Timer 1 subtimer A + DCD WideTimer1B_IRQHandler ; Wide Timer 1 subtimer B + DCD WideTimer2A_IRQHandler ; Wide Timer 2 subtimer A + DCD WideTimer2B_IRQHandler ; Wide Timer 2 subtimer B + DCD WideTimer3A_IRQHandler ; Wide Timer 3 subtimer A + DCD WideTimer3B_IRQHandler ; Wide Timer 3 subtimer B + DCD WideTimer4A_IRQHandler ; Wide Timer 4 subtimer A + DCD WideTimer4B_IRQHandler ; Wide Timer 4 subtimer B + DCD WideTimer5A_IRQHandler ; Wide Timer 5 subtimer A + DCD WideTimer5B_IRQHandler ; Wide Timer 5 subtimer B + DCD FPU_IRQHandler ; FPU + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD I2C4_IRQHandler ; I2C4 Master and Slave + DCD I2C5_IRQHandler ; I2C5 Master and Slave + DCD GPIOPortM_IRQHandler ; GPIO Port M + DCD GPIOPortN_IRQHandler ; GPIO Port N + DCD QEI2_IRQHandler ; Quadrature Encoder 2 + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD GPIOPortP0_IRQHandler ; GPIO Port P (Summary or P0) + DCD GPIOPortP1_IRQHandler ; GPIO Port P1 + DCD GPIOPortP2_IRQHandler ; GPIO Port P2 + DCD GPIOPortP3_IRQHandler ; GPIO Port P3 + DCD GPIOPortP4_IRQHandler ; GPIO Port P4 + DCD GPIOPortP5_IRQHandler ; GPIO Port P5 + DCD GPIOPortP6_IRQHandler ; GPIO Port P6 + DCD GPIOPortP7_IRQHandler ; GPIO Port P7 + DCD GPIOPortQ0_IRQHandler ; GPIO Port Q (Summary or Q0) + DCD GPIOPortQ1_IRQHandler ; GPIO Port Q1 + DCD GPIOPortQ2_IRQHandler ; GPIO Port Q2 + DCD GPIOPortQ3_IRQHandler ; GPIO Port Q3 + DCD GPIOPortQ4_IRQHandler ; GPIO Port Q4 + DCD GPIOPortQ5_IRQHandler ; GPIO Port Q5 + DCD GPIOPortQ6_IRQHandler ; GPIO Port Q6 + DCD GPIOPortQ7_IRQHandler ; GPIO Port Q7 + DCD GPIOPortR_IRQHandler ; GPIO Port R + DCD GPIOPortS_IRQHandler ; GPIO Port S + DCD PWM1Gen0_IRQHandler ; PWM 1 Generator 0 + DCD PWM1Gen1_IRQHandler ; PWM 1 Generator 1 + DCD PWM1Gen2_IRQHandler ; PWM 1 Generator 2 + DCD PWM1Gen3_IRQHandler ; PWM 1 Generator 3 + DCD PWM1Fault_IRQHandler ; PWM 1 Fault + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + +;****************************************************************************** +; +; This is the code for exception handlers. +; +;****************************************************************************** + AREA |.text|, CODE, READONLY + +;****************************************************************************** +; +; This is the code that gets called when the processor first starts execution +; following a reset event. +; +;****************************************************************************** +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ; relocate the Vector Table + LDR r0, =0xE000ED08 ; System Control Block/Vector Table Offset Reg + LDR r1, =__relocated_vector_table + STR r1,[r0] ; SCB->VTOR := __relocated_vector_table + + LDR r0, =SystemInit ; CMSIS system initialization + BLX r0 + + ; Call the C library enty point that handles startup. This will copy + ; the .data section initializers from flash to SRAM and zero fill the + ; .bss section. + LDR r0, =__main + BX r0 + + ; __main calls the main() function, which should not return, + ; but just in case jump to assert_failed() if main returns. + MOVS r0,#0 + MOVS r1,#0 ; error number + B assert_failed + ENDP + +;****************************************************************************** +; +; The NMI handler +; +;****************************************************************************** +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + MOVS r0,#0 + MOVS r1,#2 ; NMI exception number + B assert_failed + ENDP + +;****************************************************************************** +; +; The Hard Fault handler +; +;****************************************************************************** +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + MOVS r0,#0 + MOVS r1,#3 ; HardFault exception number + B assert_failed + ENDP + +;****************************************************************************** +; +; The MPU fault handler +; +;****************************************************************************** +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + MOVS r0,#0 + MOVS r1,#4 ; MemManage exception number + B assert_failed + ENDP + +;****************************************************************************** +; +; The Bus Fault handler +; +;****************************************************************************** +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + MOVS r0,#0 + MOVS r1,#5 ; BusFault exception number + B assert_failed + ENDP + +;****************************************************************************** +; +; The Usage Fault handler +; +;****************************************************************************** +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + MOVS r0,#0 + MOVS r1,#6 ; UsageFault exception number + B assert_failed + ENDP + +;****************************************************************************** +; +; The SVC handler +; +;****************************************************************************** +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + MOVS r0,#0 + MOVS r1,#11 ; SVCall exception number + B assert_failed + ENDP + +;****************************************************************************** +; +; The Debug Monitor handler +; +;****************************************************************************** +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + MOVS r0,#0 + MOVS r1,#12 ; DebugMon exception number + B assert_failed + ENDP + +;****************************************************************************** +; +; The PendSV handler +; +;****************************************************************************** +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + MOVS r0,#0 + MOVS r1,#14 ; PendSV exception number + B assert_failed + ENDP + +;****************************************************************************** +; +; The SysTick handler +; +;****************************************************************************** +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + MOVS r0,#0 + MOVS r1,#15 ; SysTick exception number + B assert_failed + ENDP + +;****************************************************************************** +; +; Define Default_Handledr as dummy for all IRQ handlers +; +;****************************************************************************** +Default_Handler PROC + EXPORT GPIOPortA_IRQHandler [WEAK] + EXPORT GPIOPortB_IRQHandler [WEAK] + EXPORT GPIOPortC_IRQHandler [WEAK] + EXPORT GPIOPortD_IRQHandler [WEAK] + EXPORT GPIOPortE_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SSI0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT PWMFault_IRQHandler [WEAK] + EXPORT PWMGen0_IRQHandler [WEAK] + EXPORT PWMGen1_IRQHandler [WEAK] + EXPORT PWMGen2_IRQHandler [WEAK] + EXPORT QEI0_IRQHandler [WEAK] + EXPORT ADCSeq0_IRQHandler [WEAK] + EXPORT ADCSeq1_IRQHandler [WEAK] + EXPORT ADCSeq2_IRQHandler [WEAK] + EXPORT ADCSeq3_IRQHandler [WEAK] + EXPORT Watchdog_IRQHandler [WEAK] + EXPORT Timer0A_IRQHandler [WEAK] + EXPORT Timer0B_IRQHandler [WEAK] + EXPORT Timer1A_IRQHandler [WEAK] + EXPORT Timer1B_IRQHandler [WEAK] + EXPORT Timer2A_IRQHandler [WEAK] + EXPORT Timer2B_IRQHandler [WEAK] + EXPORT Comp0_IRQHandler [WEAK] + EXPORT Comp1_IRQHandler [WEAK] + EXPORT Comp2_IRQHandler [WEAK] + EXPORT SysCtrl_IRQHandler [WEAK] + EXPORT FlashCtrl_IRQHandler [WEAK] + EXPORT GPIOPortF_IRQHandler [WEAK] + EXPORT GPIOPortG_IRQHandler [WEAK] + EXPORT GPIOPortH_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT SSI1_IRQHandler [WEAK] + EXPORT Timer3A_IRQHandler [WEAK] + EXPORT Timer3B_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT QEI1_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT CAN2_IRQHandler [WEAK] + EXPORT Hibernate_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT PWMGen3_IRQHandler [WEAK] + EXPORT uDMAST_IRQHandler [WEAK] + EXPORT uDMAError_IRQHandler [WEAK] + EXPORT ADC1Seq0_IRQHandler [WEAK] + EXPORT ADC1Seq1_IRQHandler [WEAK] + EXPORT ADC1Seq2_IRQHandler [WEAK] + EXPORT ADC1Seq3_IRQHandler [WEAK] + EXPORT GPIOPortJ_IRQHandler [WEAK] + EXPORT GPIOPortK_IRQHandler [WEAK] + EXPORT GPIOPortL_IRQHandler [WEAK] + EXPORT SSI2_IRQHandler [WEAK] + EXPORT SSI3_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT UART6_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT I2C3_IRQHandler [WEAK] + EXPORT Timer4A_IRQHandler [WEAK] + EXPORT Timer4B_IRQHandler [WEAK] + EXPORT Timer5A_IRQHandler [WEAK] + EXPORT Timer5B_IRQHandler [WEAK] + EXPORT WideTimer0A_IRQHandler [WEAK] + EXPORT WideTimer0B_IRQHandler [WEAK] + EXPORT WideTimer1A_IRQHandler [WEAK] + EXPORT WideTimer1B_IRQHandler [WEAK] + EXPORT WideTimer2A_IRQHandler [WEAK] + EXPORT WideTimer2B_IRQHandler [WEAK] + EXPORT WideTimer3A_IRQHandler [WEAK] + EXPORT WideTimer3B_IRQHandler [WEAK] + EXPORT WideTimer4A_IRQHandler [WEAK] + EXPORT WideTimer4B_IRQHandler [WEAK] + EXPORT WideTimer5A_IRQHandler [WEAK] + EXPORT WideTimer5B_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT I2C4_IRQHandler [WEAK] + EXPORT I2C5_IRQHandler [WEAK] + EXPORT GPIOPortM_IRQHandler [WEAK] + EXPORT GPIOPortN_IRQHandler [WEAK] + EXPORT QEI2_IRQHandler [WEAK] + EXPORT GPIOPortP0_IRQHandler [WEAK] + EXPORT GPIOPortP1_IRQHandler [WEAK] + EXPORT GPIOPortP2_IRQHandler [WEAK] + EXPORT GPIOPortP3_IRQHandler [WEAK] + EXPORT GPIOPortP4_IRQHandler [WEAK] + EXPORT GPIOPortP5_IRQHandler [WEAK] + EXPORT GPIOPortP6_IRQHandler [WEAK] + EXPORT GPIOPortP7_IRQHandler [WEAK] + EXPORT GPIOPortQ0_IRQHandler [WEAK] + EXPORT GPIOPortQ1_IRQHandler [WEAK] + EXPORT GPIOPortQ2_IRQHandler [WEAK] + EXPORT GPIOPortQ3_IRQHandler [WEAK] + EXPORT GPIOPortQ4_IRQHandler [WEAK] + EXPORT GPIOPortQ5_IRQHandler [WEAK] + EXPORT GPIOPortQ6_IRQHandler [WEAK] + EXPORT GPIOPortQ7_IRQHandler [WEAK] + EXPORT GPIOPortR_IRQHandler [WEAK] + EXPORT GPIOPortS_IRQHandler [WEAK] + EXPORT PWM1Gen0_IRQHandler [WEAK] + EXPORT PWM1Gen1_IRQHandler [WEAK] + EXPORT PWM1Gen2_IRQHandler [WEAK] + EXPORT PWM1Gen3_IRQHandler [WEAK] + EXPORT PWM1Fault_IRQHandler [WEAK] + +GPIOPortA_IRQHandler +GPIOPortB_IRQHandler +GPIOPortC_IRQHandler +GPIOPortD_IRQHandler +GPIOPortE_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SSI0_IRQHandler +I2C0_IRQHandler +PWMFault_IRQHandler +PWMGen0_IRQHandler +PWMGen1_IRQHandler +PWMGen2_IRQHandler +QEI0_IRQHandler +ADCSeq0_IRQHandler +ADCSeq1_IRQHandler +ADCSeq2_IRQHandler +ADCSeq3_IRQHandler +Watchdog_IRQHandler +Timer0A_IRQHandler +Timer0B_IRQHandler +Timer1A_IRQHandler +Timer1B_IRQHandler +Timer2A_IRQHandler +Timer2B_IRQHandler +Comp0_IRQHandler +Comp1_IRQHandler +Comp2_IRQHandler +SysCtrl_IRQHandler +FlashCtrl_IRQHandler +GPIOPortF_IRQHandler +GPIOPortG_IRQHandler +GPIOPortH_IRQHandler +UART2_IRQHandler +SSI1_IRQHandler +Timer3A_IRQHandler +Timer3B_IRQHandler +I2C1_IRQHandler +QEI1_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +CAN2_IRQHandler +Hibernate_IRQHandler +USB0_IRQHandler +PWMGen3_IRQHandler +uDMAST_IRQHandler +uDMAError_IRQHandler +ADC1Seq0_IRQHandler +ADC1Seq1_IRQHandler +ADC1Seq2_IRQHandler +ADC1Seq3_IRQHandler +GPIOPortJ_IRQHandler +GPIOPortK_IRQHandler +GPIOPortL_IRQHandler +SSI2_IRQHandler +SSI3_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +UART6_IRQHandler +UART7_IRQHandler +I2C2_IRQHandler +I2C3_IRQHandler +Timer4A_IRQHandler +Timer4B_IRQHandler +Timer5A_IRQHandler +Timer5B_IRQHandler +WideTimer0A_IRQHandler +WideTimer0B_IRQHandler +WideTimer1A_IRQHandler +WideTimer1B_IRQHandler +WideTimer2A_IRQHandler +WideTimer2B_IRQHandler +WideTimer3A_IRQHandler +WideTimer3B_IRQHandler +WideTimer4A_IRQHandler +WideTimer4B_IRQHandler +WideTimer5A_IRQHandler +WideTimer5B_IRQHandler +FPU_IRQHandler +I2C4_IRQHandler +I2C5_IRQHandler +GPIOPortM_IRQHandler +GPIOPortN_IRQHandler +QEI2_IRQHandler +GPIOPortP0_IRQHandler +GPIOPortP1_IRQHandler +GPIOPortP2_IRQHandler +GPIOPortP3_IRQHandler +GPIOPortP4_IRQHandler +GPIOPortP5_IRQHandler +GPIOPortP6_IRQHandler +GPIOPortP7_IRQHandler +GPIOPortQ0_IRQHandler +GPIOPortQ1_IRQHandler +GPIOPortQ2_IRQHandler +GPIOPortQ3_IRQHandler +GPIOPortQ4_IRQHandler +GPIOPortQ5_IRQHandler +GPIOPortQ6_IRQHandler +GPIOPortQ7_IRQHandler +GPIOPortR_IRQHandler +GPIOPortS_IRQHandler +PWM1Gen0_IRQHandler +PWM1Gen1_IRQHandler +PWM1Gen2_IRQHandler +PWM1Gen3_IRQHandler +PWM1Fault_IRQHandler + MOVS r0,#0 + MOVS r1,#-1 ; 0xFFFFFFF + B assert_failed + ENDP + + ALIGN ; make sure the end of this section is aligned + + +;****************************************************************************** +; The function expected of the C library startup code for defining the stack +; and heap memory locations. For the C library version of the startup code, +; provide this function so that the C library initialization code can find out +; the location of the stack and heap. +; +;****************************************************************************** + IF :DEF: __MICROLIB + EXPORT __initial_sp + EXPORT __stack_limit + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, =__heap_base + LDR R1, =__stack_limit + LDR R2, =__heap_limit + LDR R3, =__stack_base + BX LR + ENDP + ENDIF + +;****************************************************************************** +; The function assert_failed defines the error/assertion handling policy +; for the application. After making sure that the stack is OK, this function +; calls DBC_fault_handler(), which should NOT return (typically reset the CPU). +; +; NOTE: the function DBC_fault_handler should NOT return. +; +; The C proptotypes of assert_failed() and DBC_fault_handler() are: +; void assert_failed(char const *file, int line); +; void DBC_fault_handler(char const *file, int line); +;****************************************************************************** + EXPORT assert_failed + IMPORT DBC_fault_handler +assert_failed PROC + + LDR sp,=__initial_sp ; re-set the SP in case of stack overflow + BL DBC_fault_handler ; call the application-specific handler + + B . ; should not be reached, but just in case... + + ENDP + + ALIGN ; make sure the end of this section is aligned + + END ; end of module diff --git a/3rd_party/ek-tm4c123gxl/cmsis_armclang.h b/3rd_party/ek-tm4c123gxl/cmsis_armclang.h new file mode 100644 index 0000000..6911417 --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/3rd_party/ek-tm4c123gxl/cmsis_compiler.h b/3rd_party/ek-tm4c123gxl/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/3rd_party/ek-tm4c123gxl/cmsis_gcc.h b/3rd_party/ek-tm4c123gxl/cmsis_gcc.h new file mode 100644 index 0000000..67bda4e --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/3rd_party/ek-tm4c123gxl/cmsis_iccarm.h b/3rd_party/ek-tm4c123gxl/cmsis_iccarm.h new file mode 100644 index 0000000..65b824b --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/3rd_party/ek-tm4c123gxl/cmsis_version.h b/3rd_party/ek-tm4c123gxl/cmsis_version.h new file mode 100644 index 0000000..8b4765f --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/3rd_party/ek-tm4c123gxl/core_cm4.h b/3rd_party/ek-tm4c123gxl/core_cm4.h new file mode 100644 index 0000000..e21cd14 --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/3rd_party/ek-tm4c123gxl/ek-tm4c123gxl.ld b/3rd_party/ek-tm4c123gxl/ek-tm4c123gxl.ld new file mode 100644 index 0000000..43e1968 --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/ek-tm4c123gxl.ld @@ -0,0 +1,118 @@ +/***************************************************************************** +* Product: Linker script for EK-TM4C123GXL, GNU-ARM linker +* Last Updated for Version: 5.9.8 +* Date of the Last Update: 2017-09-13 +* +* Q u a n t u m L e a P s +* --------------------------- +* innovating embedded systems +* +* Copyright (C) Quantum Leaps, LLC. All rights reserved. +* +*****************************************************************************/ +OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Reset_Handler) /* entry Point */ + +MEMORY { /* memory map of Tiva TM4C123GH6PM */ + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 256K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K +} + +/* The size of the stack used by the application. NOTE: you need to adjust */ +STACK_SIZE = 2048; + +/* The size of the heap used by the application. NOTE: you need to adjust */ +HEAP_SIZE = 0; + +SECTIONS { + + .isr_vector : { /* the vector table goes FIRST into ROM */ + KEEP(*(.isr_vector)) /* vector table */ + . = ALIGN(4); + } >ROM + + .text : { /* code and constants */ + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + } >ROM + + .preinit_array : { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ROM + + .init_array : { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ROM + + .fini_array : { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >ROM + + _etext = .; /* global symbols at end of code */ + + .stack : { + __stack_start__ = .; + . = . + STACK_SIZE; + . = ALIGN(4); + __stack_end__ = .; + } >RAM + + .data : AT (_etext) { + __data_load = LOADADDR (.data); + __data_start = .; + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + . = ALIGN(4); + __data_end__ = .; + _edata = __data_end__; + } >RAM + + .bss : { + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = .; + } >RAM + + __exidx_start = .; + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >RAM + __exidx_end = .; + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + PROVIDE ( __end__ = _ebss ); + + .heap : { + __heap_start__ = .; + . = . + HEAP_SIZE; + . = ALIGN(4); + __heap_end__ = .; + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } +} diff --git a/3rd_party/ek-tm4c123gxl/gnu/startup_TM4C123GH6PM.c b/3rd_party/ek-tm4c123gxl/gnu/startup_TM4C123GH6PM.c new file mode 100644 index 0000000..31f4cd7 --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/gnu/startup_TM4C123GH6PM.c @@ -0,0 +1,518 @@ +/* File: startup_TM4C123GH6PM.c + * Purpose: startup file for TM4C123GH6PM Cortex-M4 device. + * Should be used with GCC 'GNU Tools ARM Embedded' + * Version: CMSIS 5.0.1 + * Date: 2017-09-13 + * + * Modified by Quantum Leaps: + * Added assert_failed() and DBC_fault_handler() + * Added relocating of the Vector Table to free up the 256B region at 0x0 + * for NULL-pointer protection by the MPU. + * + * Created from the CMSIS template for the specified device + * Quantum Leaps, www.state-machine.com + * + * NOTE: + * The function assert_failed defined at the end of this file defines + * the error/assertion handling policy for the application and might + * need to be customized for each project. This function is defined in + * assembly to re-set the stack pointer, in case it is corrupted by the + * time assert_failed is called. + */ +/* Copyright (c) 2011 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* start and end of stack defined in the linker script ---------------------*/ +/*extern int __stack_start__;*/ +extern int __stack_end__; + +/* Weak prototypes for error handlers --------------------------------------*/ +/** +* \note +* The function assert_failed defined at the end of this file defines +* the error/assertion handling policy for the application and might +* need to be customized for each project. This function is defined in +* assembly to avoid accessing the stack, which might be corrupted by +* the time assert_failed is called. +*/ +__attribute__ ((naked, noreturn)) +void assert_failed(char const *module, int loc); + +/* Function prototypes -----------------------------------------------------*/ +void Default_Handler(void); /* Default empty handler */ +void Reset_Handler(void); /* Reset Handler */ +void SystemInit(void); /* CMSIS system initialization */ +__attribute__ ((noreturn)) +void DBC_fault_handler(char const *module, int loc); + +/*---------------------------------------------------------------------------- +* weak aliases for each Exception handler to the Default_Handler. +* Any function with the same name will override these definitions. +*/ +/* Cortex-M Processor fault exceptions... */ +void NMI_Handler (void) __attribute__ ((weak)); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak)); +void BusFault_Handler (void) __attribute__ ((weak)); +void UsageFault_Handler (void) __attribute__ ((weak)); + +/* Cortex-M Processor non-fault exceptions... */ +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* external interrupts... */ +void GPIOPortA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortE_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SSI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWMFault_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWMGen0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWMGen1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWMGen2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void QEI0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADCSeq0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADCSeq1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADCSeq2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADCSeq3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Watchdog_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Timer0A_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Timer0B_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Timer1A_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Timer1B_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Timer2A_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Timer2B_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Comp0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Comp1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Comp2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysCtrl_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FlashCtrl_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortF_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortG_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortH_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SSI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Timer3A_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Timer3B_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void QEI1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CAN0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CAN1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CAN2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Hibernate_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USB0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWMGen3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void uDMAST_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void uDMAError_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC1Seq0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC1Seq1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC1Seq2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ADC1Seq3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortJ_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortK_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortL_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SSI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SSI3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Timer4A_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Timer4B_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Timer5A_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Timer5B_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void WideTimer0A_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WideTimer0B_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WideTimer1A_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WideTimer1B_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WideTimer2A_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WideTimer2B_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WideTimer3A_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WideTimer3B_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WideTimer4A_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WideTimer4B_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WideTimer5A_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WideTimer5B_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void FPU_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortM_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void QEI2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortP0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortP1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortP2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortP3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortP4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortP5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortP6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortP7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortQ0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortQ1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortQ2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortQ3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortQ4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortQ5_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortQ6_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortQ7_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortR_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIOPortS_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM1Gen0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM1Gen1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM1Gen2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM1Gen3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PWM1Fault_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*..........................................................................*/ +__attribute__ ((section(".isr_vector"))) +int const g_pfnVectors[] = { + /* Initial Vector Table before relocation */ + (int)&__stack_end__, /* Top of Stack */ + (int)&Reset_Handler, /* Reset Handler */ + (int)&NMI_Handler, /* NMI Handler */ + (int)&HardFault_Handler, /* Hard Fault Handler */ + (int)&MemManage_Handler, /* The MPU fault handler */ + (int)&BusFault_Handler, /* The bus fault handler */ + (int)&UsageFault_Handler, /* The usage fault handler */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&SVC_Handler, /* SVCall handler */ + (int)&DebugMon_Handler, /* Debug monitor handler */ + (int)&Default_Handler, /* Reserved */ + (int)&PendSV_Handler, /* The PendSV handler */ + (int)&SysTick_Handler, /* The SysTick handler */ + /* pad the initial VT to the total size of 256B */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + /* Relocated Vector Table beyond the 256B region around address 0. + * That region is used for NULL-pointer protection by the MPU. + */ + (int)&__stack_end__, /* Top of Stack */ + (int)&Reset_Handler, /* Reset Handler */ + (int)&NMI_Handler, /* NMI Handler */ + (int)&HardFault_Handler, /* Hard Fault Handler */ + (int)&MemManage_Handler, /* The MPU fault handler */ + (int)&BusFault_Handler, /* The bus fault handler */ + (int)&UsageFault_Handler, /* The usage fault handler */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&SVC_Handler, /* SVCall handler */ + (int)&DebugMon_Handler, /* Debug monitor handler */ + (int)&Default_Handler, /* Reserved */ + (int)&PendSV_Handler, /* The PendSV handler */ + (int)&SysTick_Handler, /* The SysTick handler */ + + /*IRQ handlers... */ + (int)&GPIOPortA_IRQHandler, /* GPIO Port A */ + (int)&GPIOPortB_IRQHandler, /* GPIO Port B */ + (int)&GPIOPortC_IRQHandler, /* GPIO Port C */ + (int)&GPIOPortD_IRQHandler, /* GPIO Port D */ + (int)&GPIOPortE_IRQHandler, /* GPIO Port E */ + (int)&UART0_IRQHandler, /* UART0 Rx and Tx */ + (int)&UART1_IRQHandler, /* UART1 Rx and Tx */ + (int)&SSI0_IRQHandler, /* SSI0 Rx and Tx */ + (int)&I2C0_IRQHandler, /* I2C0 Master and Slave */ + (int)&PWMFault_IRQHandler, /* PWM Fault */ + (int)&PWMGen0_IRQHandler, /* PWM Generator 0 */ + (int)&PWMGen1_IRQHandler, /* PWM Generator 1 */ + (int)&PWMGen2_IRQHandler, /* PWM Generator 2 */ + (int)&QEI0_IRQHandler, /* Quadrature Encoder 0 */ + (int)&ADCSeq0_IRQHandler, /* ADC Sequence 0 */ + (int)&ADCSeq1_IRQHandler, /* ADC Sequence 1 */ + (int)&ADCSeq2_IRQHandler, /* ADC Sequence 2 */ + (int)&ADCSeq3_IRQHandler, /* ADC Sequence 3 */ + (int)&Watchdog_IRQHandler, /* Watchdog timer */ + (int)&Timer0A_IRQHandler, /* Timer 0 subtimer A */ + (int)&Timer0B_IRQHandler, /* Timer 0 subtimer B */ + (int)&Timer1A_IRQHandler, /* Timer 1 subtimer A */ + (int)&Timer1B_IRQHandler, /* Timer 1 subtimer B */ + (int)&Timer2A_IRQHandler, /* Timer 2 subtimer A */ + (int)&Timer2B_IRQHandler, /* Timer 2 subtimer B */ + (int)&Comp0_IRQHandler, /* Analog Comparator 0 */ + (int)&Comp1_IRQHandler, /* Analog Comparator 1 */ + (int)&Comp2_IRQHandler, /* Analog Comparator 2 */ + (int)&SysCtrl_IRQHandler, /* System Control (PLL, OSC, BO) */ + (int)&FlashCtrl_IRQHandler, /* FLASH Control */ + (int)&GPIOPortF_IRQHandler, /* GPIO Port F */ + (int)&GPIOPortG_IRQHandler, /* GPIO Port G */ + (int)&GPIOPortH_IRQHandler, /* GPIO Port H */ + (int)&UART2_IRQHandler, /* UART2 Rx and Tx */ + (int)&SSI1_IRQHandler, /* SSI1 Rx and Tx */ + (int)&Timer3A_IRQHandler, /* Timer 3 subtimer A */ + (int)&Timer3B_IRQHandler, /* Timer 3 subtimer B */ + (int)&I2C1_IRQHandler, /* I2C1 Master and Slave */ + (int)&QEI1_IRQHandler, /* Quadrature Encoder 1 */ + (int)&CAN0_IRQHandler, /* CAN0 */ + (int)&CAN1_IRQHandler, /* CAN1 */ + (int)&CAN2_IRQHandler, /* CAN2 */ + (int)&Default_Handler, /* Reserved */ + (int)&Hibernate_IRQHandler, /* Hibernate */ + (int)&USB0_IRQHandler, /* USB0 */ + (int)&PWMGen3_IRQHandler, /* PWM Generator 3 */ + (int)&uDMAST_IRQHandler, /* uDMA Software Transfer */ + (int)&uDMAError_IRQHandler, /* uDMA Error */ + (int)&ADC1Seq0_IRQHandler, /* ADC1 Sequence 0 */ + (int)&ADC1Seq1_IRQHandler, /* ADC1 Sequence 1 */ + (int)&ADC1Seq2_IRQHandler, /* ADC1 Sequence 2 */ + (int)&ADC1Seq3_IRQHandler, /* ADC1 Sequence 3 */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&GPIOPortJ_IRQHandler, /* GPIO Port J */ + (int)&GPIOPortK_IRQHandler, /* GPIO Port K */ + (int)&GPIOPortL_IRQHandler, /* GPIO Port L */ + (int)&SSI2_IRQHandler, /* SSI2 Rx and Tx */ + (int)&SSI3_IRQHandler, /* SSI3 Rx and Tx */ + (int)&UART3_IRQHandler, /* UART3 Rx and Tx */ + (int)&UART4_IRQHandler, /* UART4 Rx and Tx */ + (int)&UART5_IRQHandler, /* UART5 Rx and Tx */ + (int)&UART6_IRQHandler, /* UART6 Rx and Tx */ + (int)&UART7_IRQHandler, /* UART7 Rx and Tx */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&I2C2_IRQHandler, /* I2C2 Master and Slave */ + (int)&I2C3_IRQHandler, /* I2C3 Master and Slave */ + (int)&Timer4A_IRQHandler, /* Timer 4 subtimer A */ + (int)&Timer4B_IRQHandler, /* Timer 4 subtimer B */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&Timer5A_IRQHandler, /* Timer 5 subtimer A */ + (int)&Timer5B_IRQHandler, /* Timer 5 subtimer B */ + (int)&WideTimer0A_IRQHandler, /* Wide Timer 0 subtimer A */ + (int)&WideTimer0B_IRQHandler, /* Wide Timer 0 subtimer B */ + (int)&WideTimer1A_IRQHandler, /* Wide Timer 1 subtimer A */ + (int)&WideTimer1B_IRQHandler, /* Wide Timer 1 subtimer B */ + (int)&WideTimer2A_IRQHandler, /* Wide Timer 2 subtimer A */ + (int)&WideTimer2B_IRQHandler, /* Wide Timer 2 subtimer B */ + (int)&WideTimer3A_IRQHandler, /* Wide Timer 3 subtimer A */ + (int)&WideTimer3B_IRQHandler, /* Wide Timer 3 subtimer B */ + (int)&WideTimer4A_IRQHandler, /* Wide Timer 4 subtimer A */ + (int)&WideTimer4B_IRQHandler, /* Wide Timer 4 subtimer B */ + (int)&WideTimer5A_IRQHandler, /* Wide Timer 5 subtimer A */ + (int)&WideTimer5B_IRQHandler, /* Wide Timer 5 subtimer B */ + (int)&FPU_IRQHandler, /* FPU */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&I2C4_IRQHandler, /* I2C4 Master and Slave */ + (int)&I2C5_IRQHandler, /* I2C5 Master and Slave */ + (int)&GPIOPortM_IRQHandler, /* GPIO Port M */ + (int)&GPIOPortN_IRQHandler, /* GPIO Port N */ + (int)&QEI2_IRQHandler, /* Quadrature Encoder 2 */ + (int)&Default_Handler, /* Reserved */ + (int)&Default_Handler, /* Reserved */ + (int)&GPIOPortP0_IRQHandler, /* GPIO Port P (Summary or P0) */ + (int)&GPIOPortP1_IRQHandler, /* GPIO Port P1 */ + (int)&GPIOPortP2_IRQHandler, /* GPIO Port P2 */ + (int)&GPIOPortP3_IRQHandler, /* GPIO Port P3 */ + (int)&GPIOPortP4_IRQHandler, /* GPIO Port P4 */ + (int)&GPIOPortP5_IRQHandler, /* GPIO Port P5 */ + (int)&GPIOPortP6_IRQHandler, /* GPIO Port P6 */ + (int)&GPIOPortP7_IRQHandler, /* GPIO Port P7 */ + (int)&GPIOPortQ0_IRQHandler, /* GPIO Port Q (Summary or Q0) */ + (int)&GPIOPortQ1_IRQHandler, /* GPIO Port Q1 */ + (int)&GPIOPortQ2_IRQHandler, /* GPIO Port Q2 */ + (int)&GPIOPortQ3_IRQHandler, /* GPIO Port Q3 */ + (int)&GPIOPortQ4_IRQHandler, /* GPIO Port Q4 */ + (int)&GPIOPortQ5_IRQHandler, /* GPIO Port Q5 */ + (int)&GPIOPortQ6_IRQHandler, /* GPIO Port Q6 */ + (int)&GPIOPortQ7_IRQHandler, /* GPIO Port Q7 */ + (int)&GPIOPortR_IRQHandler, /* GPIO Port R */ + (int)&GPIOPortS_IRQHandler, /* GPIO Port S */ + (int)&PWM1Gen0_IRQHandler, /* PWM 1 Generator 0 */ + (int)&PWM1Gen1_IRQHandler, /* PWM 1 Generator 1 */ + (int)&PWM1Gen2_IRQHandler, /* PWM 1 Generator 2 */ + (int)&PWM1Gen3_IRQHandler, /* PWM 1 Generator 3 */ + (int)&PWM1Fault_IRQHandler, /* PWM 1 Fault */ +}; + + +/* reset handler -----------------------------------------------------------*/ +__attribute__((naked)) void Reset_Handler(void); +void Reset_Handler(void) { + extern int main(void); + extern int __libc_init_array(void); + extern unsigned __data_start; /* start of .data in the linker script */ + extern unsigned __data_end__; /* end of .data in the linker script */ + extern unsigned const __data_load; /* initialization values for .data */ + extern unsigned __bss_start__; /* start of .bss in the linker script */ + extern unsigned __bss_end__; /* end of .bss in the linker script */ + extern void software_init_hook(void) __attribute__((weak)); + + /* relocate the Vector Table to leave room for the NULL-pointer region + * System Control Block/Vector Table Offset Reg := relocated Vector Table + */ + *(int const * volatile *)0xE000ED08 = &g_pfnVectors[256/sizeof(int)]; + + SystemInit(); /* CMSIS system initialization */ + + /* copy the data segment initializers from flash to RAM... */ + unsigned const *src = &__data_load; + unsigned *dst; + for (dst = &__data_start; dst < &__data_end__; ++dst, ++src) { + *dst = *src; + } + + /* zero fill the .bss segment in RAM... */ + for (dst = &__bss_start__; dst < &__bss_end__; ++dst) { + *dst = 0; + } + + /* init hook provided? */ + if (&software_init_hook != (void (*)(void))(0)) { + /* give control to the RTOS */ + software_init_hook(); /* this will also call __libc_init_array */ + } + else { + /* call all static constructors in C++ (harmless in C programs) */ + __libc_init_array(); + (void)main(); /* application's entry point; should never return! */ + } + + /* the previous code should not return, but assert just in case... */ + assert_failed("Reset_Handler", __LINE__); +} + + +/* fault exception handlers ------------------------------------------------*/ +__attribute__((naked)) void NMI_Handler(void); +void NMI_Handler(void) { +__asm volatile ( + " ldr r0,=str_nmi \n" + " mov r1,#1 \n" + " b assert_failed \n" + "str_nmi: .asciz \"NMI\" \n" + " .align 2 \n" +); +} +/*..........................................................................*/ +__attribute__((naked)) void MemManage_Handler(void); +void MemManage_Handler(void) { +__asm volatile ( + " ldr r0,=str_mem \n" + " mov r1,#1 \n" + " b assert_failed \n" + "str_mem: .asciz \"MemManage\"\n" + " .align 2 \n" +); +} +/*..........................................................................*/ +__attribute__((naked)) void HardFault_Handler(void); +void HardFault_Handler(void) { +__asm volatile ( + " ldr r0,=str_hrd \n" + " mov r1,#1 \n" + " b assert_failed \n" + "str_hrd: .asciz \"HardFault\"\n" + " .align 2 \n" +); +} +/*..........................................................................*/ +__attribute__((naked)) void BusFault_Handler(void); +void BusFault_Handler(void) { +__asm volatile ( + " ldr r0,=str_bus \n" + " mov r1,#1 \n" + " b assert_failed \n" + "str_bus: .asciz \"BusFault\"\n" + " .align 2 \n" +); +} +/*..........................................................................*/ +__attribute__((naked)) void UsageFault_Handler(void); +void UsageFault_Handler(void) { +__asm volatile ( + " ldr r0,=str_usage \n" + " mov r1,#1 \n" + " b assert_failed \n" + "str_usage: .asciz \"UsageFault\"\n" + " .align 2 \n" +); +} +/*..........................................................................*/ +__attribute__((naked)) void Default_Handler(void); +void Default_Handler(void) { +__asm volatile ( + " ldr r0,=str_dflt \n" + " mov r1,#1 \n" + " b assert_failed \n" + "str_dflt: .asciz \"Default\"\n" + " .align 2 \n" +); +} + +/*--------------------------------------------------------------------------*/ +/* The function assert_failed() provides a low-level handler for assertion +* failures. It ultimately transfers control to DBC_fault_handler(), which +* defines the error/assertion handling policy for the application. +* +* assert_failed() re-sets the stack pointer (MSP) to the original setting. +* This is necessary to avoid cascading exceptions in case the stack was +* OVERFLOWN. +*/ +__attribute__ ((naked, noreturn)) +void assert_failed(char const *module, int loc) { + /* re-set the SP in case of stack overflow */ + __asm volatile (" MOV sp,%0" : : "r" (&__stack_end__)); + DBC_fault_handler(module, loc); /* application-specific DBC handler */ + for (;;) { /* should not be reached, but just in case loop forever... */ + } +} diff --git a/3rd_party/ek-tm4c123gxl/gpio.h b/3rd_party/ek-tm4c123gxl/gpio.h new file mode 100644 index 0000000..41692d5 --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/gpio.h @@ -0,0 +1,201 @@ +//============================================================================* +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005-2015 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.2.111 of the Tiva Peripheral Driver Library. +// +//============================================================================* + +#ifndef __DRIVERLIB_GPIO_H__ +#define __DRIVERLIB_GPIO_H__ + +//============================================================================* +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//============================================================================* +#ifdef __cplusplus +extern "C" +{ +#endif + +//============================================================================* +// +// The following values define the bit field for the ui8Pins argument to +// several of the APIs. +// +//============================================================================* +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//============================================================================* +// +// Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and +// returned from GPIODirModeGet. +// +//============================================================================* +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//============================================================================* +// +// Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter, +// and returned from GPIOIntTypeGet. +// +//============================================================================* +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level +#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins + +//============================================================================* +// +// Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter, +// and returned by GPIOPadConfigGet in the *pui32Strength parameter. +// +//============================================================================* +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_6MA 0x00000065 // 6mA drive strength +#define GPIO_STRENGTH_8MA 0x00000066 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000006E // 8mA drive with slew rate control +#define GPIO_STRENGTH_10MA 0x00000075 // 10mA drive strength +#define GPIO_STRENGTH_12MA 0x00000077 // 12mA drive strength + +//============================================================================* +// +// Values that can be passed to GPIOPadConfigSet as the ui32PadType parameter, +// and returned by GPIOPadConfigGet in the *pui32PadType parameter. +// +//============================================================================* +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator +#define GPIO_PIN_TYPE_WAKE_HIGH 0x00000208 // Hibernate wake, high +#define GPIO_PIN_TYPE_WAKE_LOW 0x00000108 // Hibernate wake, low + +//============================================================================* +// +// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions +// in the ui32IntFlags parameter. +// +//============================================================================* +#define GPIO_INT_PIN_0 0x00000001 +#define GPIO_INT_PIN_1 0x00000002 +#define GPIO_INT_PIN_2 0x00000004 +#define GPIO_INT_PIN_3 0x00000008 +#define GPIO_INT_PIN_4 0x00000010 +#define GPIO_INT_PIN_5 0x00000020 +#define GPIO_INT_PIN_6 0x00000040 +#define GPIO_INT_PIN_7 0x00000080 +#define GPIO_INT_DMA 0x00000100 + +//============================================================================* +// +// Prototypes for the APIs. +// +//============================================================================* +extern void GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32PinIO); +extern uint32_t GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin); +extern void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32IntType); +extern uint32_t GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin); +extern void GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32Strength, uint32_t ui32PadType); +extern void GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin, + uint32_t *pui32Strength, uint32_t *pui32PadType); +extern void GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags); +extern void GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags); +extern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked); +extern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags); +extern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void)); +extern void GPIOIntUnregister(uint32_t ui32Port); +extern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val); +extern void GPIOPinConfigure(uint32_t ui32PinConfig); +extern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins); +extern uint32_t GPIOPinWakeStatus(uint32_t ui32Port); +extern void GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); + +//============================================================================* +// +// Mark the end of the C bindings section for C++ compilers. +// +//============================================================================* +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_GPIO_H__ diff --git a/3rd_party/ek-tm4c123gxl/iar/startup_TM4C123GH6PM.s b/3rd_party/ek-tm4c123gxl/iar/startup_TM4C123GH6PM.s new file mode 100644 index 0000000..181038d --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/iar/startup_TM4C123GH6PM.s @@ -0,0 +1,620 @@ +;/***************************************************************************/ +; * @file startup_TM4C123GH6PM.s for IAR ARM assembler +; * @brief CMSIS Cortex-M4F Core Device Startup File for TM4C123GH6PM +; * @version CMSIS 5.5.1 +; * @date 13 May 2019 +; * +; * Modified by Quantum Leaps: +; * Added relocating of the Vector Table to free up the 256B region at 0x0 +; * for NULL-pointer protection by the MPU. +; * +; * @description +; * Created from the CMSIS template for the specified device +; * Quantum Leaps, www.state-machine.com +; * +; * @note +; * The function assert_failed defined at the end of this file defines +; * the error/assertion handling policy for the application and might +; * need to be customized for each project. This function is defined in +; * assembly to re-set the stack pointer, in case it is corrupted by the +; * time assert_failed is called. +; * +; ***************************************************************************/ +;/* Copyright (c) 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;---------------------------------------------------------------------------*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; + DATA +__vector_table + ; Initial Vector Table before relocation + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; The MPU fault handler + DCD BusFault_Handler ; The bus fault handler + DCD UsageFault_Handler ; The usage fault handler + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD SVC_Handler ; SVCall handler + DCD DebugMon_Handler ; Debug monitor handler + DCD Default_Handler ; Reserved + DCD PendSV_Handler ; The PendSV handler + DCD SysTick_Handler ; The SysTick handler + ALIGNROM 8 ; Extend the initial Vector Table to the 2^8==256B + + ; Relocated Vector Table beyond the 256B region around address 0. + ; That region is used for NULL-pointer protection by the MPU. +__relocated_vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; The MPU fault handler + DCD BusFault_Handler ; The bus fault handler + DCD UsageFault_Handler ; The usage fault handler + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD SVC_Handler ; SVCall handler + DCD DebugMon_Handler ; Debug monitor handler + DCD Default_Handler ; Reserved + DCD PendSV_Handler ; The PendSV handler + DCD SysTick_Handler ; The SysTick handler + + ; IRQ handlers... + DCD GPIOPortA_IRQHandler ; GPIO Port A + DCD GPIOPortB_IRQHandler ; GPIO Port B + DCD GPIOPortC_IRQHandler ; GPIO Port C + DCD GPIOPortD_IRQHandler ; GPIO Port D + DCD GPIOPortE_IRQHandler ; GPIO Port E + DCD UART0_IRQHandler ; UART0 Rx and Tx + DCD UART1_IRQHandler ; UART1 Rx and Tx + DCD SSI0_IRQHandler ; SSI0 Rx and Tx + DCD I2C0_IRQHandler ; I2C0 Master and Slave + DCD PWMFault_IRQHandler ; PWM Fault + DCD PWMGen0_IRQHandler ; PWM Generator 0 + DCD PWMGen1_IRQHandler ; PWM Generator 1 + DCD PWMGen2_IRQHandler ; PWM Generator 2 + DCD QEI0_IRQHandler ; Quadrature Encoder 0 + DCD ADCSeq0_IRQHandler ; ADC Sequence 0 + DCD ADCSeq1_IRQHandler ; ADC Sequence 1 + DCD ADCSeq2_IRQHandler ; ADC Sequence 2 + DCD ADCSeq3_IRQHandler ; ADC Sequence 3 + DCD Watchdog_IRQHandler ; Watchdog timer + DCD Timer0A_IRQHandler ; Timer 0 subtimer A + DCD Timer0B_IRQHandler ; Timer 0 subtimer B + DCD Timer1A_IRQHandler ; Timer 1 subtimer A + DCD Timer1B_IRQHandler ; Timer 1 subtimer B + DCD Timer2A_IRQHandler ; Timer 2 subtimer A + DCD Timer2B_IRQHandler ; Timer 2 subtimer B + DCD Comp0_IRQHandler ; Analog Comparator 0 + DCD Comp1_IRQHandler ; Analog Comparator 1 + DCD Comp2_IRQHandler ; Analog Comparator 2 + DCD SysCtrl_IRQHandler ; System Control (PLL, OSC, BO) + DCD FlashCtrl_IRQHandler ; FLASH Control + DCD GPIOPortF_IRQHandler ; GPIO Port F + DCD GPIOPortG_IRQHandler ; GPIO Port G + DCD GPIOPortH_IRQHandler ; GPIO Port H + DCD UART2_IRQHandler ; UART2 Rx and Tx + DCD SSI1_IRQHandler ; SSI1 Rx and Tx + DCD Timer3A_IRQHandler ; Timer 3 subtimer A + DCD Timer3B_IRQHandler ; Timer 3 subtimer B + DCD I2C1_IRQHandler ; I2C1 Master and Slave + DCD QEI1_IRQHandler ; Quadrature Encoder 1 + DCD CAN0_IRQHandler ; CAN0 + DCD CAN1_IRQHandler ; CAN1 + DCD CAN2_IRQHandler ; CAN2 + DCD Default_Handler ; Reserved + DCD Hibernate_IRQHandler ; Hibernate + DCD USB0_IRQHandler ; USB0 + DCD PWMGen3_IRQHandler ; PWM Generator 3 + DCD uDMAST_IRQHandler ; uDMA Software Transfer + DCD uDMAError_IRQHandler ; uDMA Error + DCD ADC1Seq0_IRQHandler ; ADC1 Sequence 0 + DCD ADC1Seq1_IRQHandler ; ADC1 Sequence 1 + DCD ADC1Seq2_IRQHandler ; ADC1 Sequence 2 + DCD ADC1Seq3_IRQHandler ; ADC1 Sequence 3 + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD GPIOPortJ_IRQHandler ; GPIO Port J + DCD GPIOPortK_IRQHandler ; GPIO Port K + DCD GPIOPortL_IRQHandler ; GPIO Port L + DCD SSI2_IRQHandler ; SSI2 Rx and Tx + DCD SSI3_IRQHandler ; SSI3 Rx and Tx + DCD UART3_IRQHandler ; UART3 Rx and Tx + DCD UART4_IRQHandler ; UART4 Rx and Tx + DCD UART5_IRQHandler ; UART5 Rx and Tx + DCD UART6_IRQHandler ; UART6 Rx and Tx + DCD UART7_IRQHandler ; UART7 Rx and Tx + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD I2C2_IRQHandler ; I2C2 Master and Slave + DCD I2C3_IRQHandler ; I2C3 Master and Slave + DCD Timer4A_IRQHandler ; Timer 4 subtimer A + DCD Timer4B_IRQHandler ; Timer 4 subtimer B + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD Timer5A_IRQHandler ; Timer 5 subtimer A + DCD Timer5B_IRQHandler ; Timer 5 subtimer B + DCD WideTimer0A_IRQHandler ; Wide Timer 0 subtimer A + DCD WideTimer0B_IRQHandler ; Wide Timer 0 subtimer B + DCD WideTimer1A_IRQHandler ; Wide Timer 1 subtimer A + DCD WideTimer1B_IRQHandler ; Wide Timer 1 subtimer B + DCD WideTimer2A_IRQHandler ; Wide Timer 2 subtimer A + DCD WideTimer2B_IRQHandler ; Wide Timer 2 subtimer B + DCD WideTimer3A_IRQHandler ; Wide Timer 3 subtimer A + DCD WideTimer3B_IRQHandler ; Wide Timer 3 subtimer B + DCD WideTimer4A_IRQHandler ; Wide Timer 4 subtimer A + DCD WideTimer4B_IRQHandler ; Wide Timer 4 subtimer B + DCD WideTimer5A_IRQHandler ; Wide Timer 5 subtimer A + DCD WideTimer5B_IRQHandler ; Wide Timer 5 subtimer B + DCD FPU_IRQHandler ; FPU + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD I2C4_IRQHandler ; I2C4 Master and Slave + DCD I2C5_IRQHandler ; I2C5 Master and Slave + DCD GPIOPortM_IRQHandler ; GPIO Port M + DCD GPIOPortN_IRQHandler ; GPIO Port N + DCD QEI2_IRQHandler ; Quadrature Encoder 2 + DCD Default_Handler ; Reserved + DCD Default_Handler ; Reserved + DCD GPIOPortP0_IRQHandler ; GPIO Port P (Summary or P0) + DCD GPIOPortP1_IRQHandler ; GPIO Port P1 + DCD GPIOPortP2_IRQHandler ; GPIO Port P2 + DCD GPIOPortP3_IRQHandler ; GPIO Port P3 + DCD GPIOPortP4_IRQHandler ; GPIO Port P4 + DCD GPIOPortP5_IRQHandler ; GPIO Port P5 + DCD GPIOPortP6_IRQHandler ; GPIO Port P6 + DCD GPIOPortP7_IRQHandler ; GPIO Port P7 + DCD GPIOPortQ0_IRQHandler ; GPIO Port Q (Summary or Q0) + DCD GPIOPortQ1_IRQHandler ; GPIO Port Q1 + DCD GPIOPortQ2_IRQHandler ; GPIO Port Q2 + DCD GPIOPortQ3_IRQHandler ; GPIO Port Q3 + DCD GPIOPortQ4_IRQHandler ; GPIO Port Q4 + DCD GPIOPortQ5_IRQHandler ; GPIO Port Q5 + DCD GPIOPortQ6_IRQHandler ; GPIO Port Q6 + DCD GPIOPortQ7_IRQHandler ; GPIO Port Q7 + DCD GPIOPortR_IRQHandler ; GPIO Port R + DCD GPIOPortS_IRQHandler ; GPIO Port S + DCD PWM1Gen0_IRQHandler ; PWM 1 Generator 0 + DCD PWM1Gen1_IRQHandler ; PWM 1 Generator 1 + DCD PWM1Gen2_IRQHandler ; PWM 1 Generator 2 + DCD PWM1Gen3_IRQHandler ; PWM 1 Generator 3 + DCD PWM1Fault_IRQHandler ; PWM 1 Fault +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;****************************************************************************** +; +; Weak fault handlers... +; + SECTION .text:CODE:REORDER:NOROOT(2) + +;............................................................................. + PUBWEAK Reset_Handler + EXTERN SystemInit + EXTERN __iar_program_start +Reset_Handler + + ; relocate the Vector Table + LDR r0, =0xE000ED08 ; System Control Block/Vector Table Offset Reg + LDR r1, =__relocated_vector_table + STR r1,[r0] ; SCB->VTOR := __Vector_Table + + BL SystemInit ; CMSIS system initialization + + ; pre-fill the CSTACK with 0xDEADBEEF................... + LDR r0,=0xDEADBEEF + MOV r1,r0 + LDR r2,=sfb(CSTACK) + LDR r3,=sfe(CSTACK) +Reset_stackInit_fill: + STMIA r2!,{r0,r1} + CMP r2,r3 + BLT.N Reset_stackInit_fill + + BL __iar_program_start ; IAR startup code +;............................................................................. + PUBWEAK NMI_Handler +NMI_Handler + LDR r0,=str_NMI + MOVS r1,#1 + B assert_failed +str_NMI + DCB "NMI" + ALIGNROM 2 +;............................................................................. + PUBWEAK HardFault_Handler +HardFault_Handler + LDR r0,=str_HardFault + MOVS r1,#1 + B assert_failed +str_HardFault + DCB "HardFault" + ALIGNROM 2 +;............................................................................. + PUBWEAK MemManage_Handler +MemManage_Handler + LDR r0,=str_MemManage + MOVS r1,#1 + B assert_failed +str_MemManage + DCB "MemManage" + ALIGNROM 2 +;............................................................................. + PUBWEAK BusFault_Handler +BusFault_Handler + LDR r0,=str_BusFault + MOVS r1,#1 + B assert_failed +str_BusFault + DCB "BusFault" + ALIGNROM 2 +;............................................................................. + PUBWEAK UsageFault_Handler +UsageFault_Handler + LDR r0,=str_UsageFault + MOVS r1,#1 + B assert_failed +str_UsageFault + DCB "UsageFault" + ALIGNROM 2 + +;****************************************************************************** +; +; Weak non-fault handlers... +; + + PUBWEAK SVC_Handler +SVC_Handler + LDR r0,=str_SVC + MOVS r1,#1 + B assert_failed +str_SVC + DCB "SVC" + ALIGNROM 2 +;............................................................................. + PUBWEAK DebugMon_Handler +DebugMon_Handler + LDR r0,=str_DebugMon + MOVS r1,#1 + B assert_failed +str_DebugMon + DCB "DebugMon" + ALIGNROM 2 +;............................................................................. + PUBWEAK PendSV_Handler +PendSV_Handler + LDR r0,=str_PendSV + MOVS r1,#1 + B assert_failed +str_PendSV + DCB "PendSV" + ALIGNROM 2 +;............................................................................. + PUBWEAK SysTick_Handler +SysTick_Handler + LDR r0,=str_SysTick + MOVS r1,#1 + B assert_failed +str_SysTick + DCB "SysTick" + ALIGNROM 2 + +;****************************************************************************** +; +; Weak IRQ handlers... +; + + PUBWEAK Default_Handler + PUBWEAK GPIOPortA_IRQHandler + PUBWEAK GPIOPortB_IRQHandler + PUBWEAK GPIOPortC_IRQHandler + PUBWEAK GPIOPortD_IRQHandler + PUBWEAK GPIOPortE_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK SSI0_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK PWMFault_IRQHandler + PUBWEAK PWMGen0_IRQHandler + PUBWEAK PWMGen1_IRQHandler + PUBWEAK PWMGen2_IRQHandler + PUBWEAK QEI0_IRQHandler + PUBWEAK ADCSeq0_IRQHandler + PUBWEAK ADCSeq1_IRQHandler + PUBWEAK ADCSeq2_IRQHandler + PUBWEAK ADCSeq3_IRQHandler + PUBWEAK Watchdog_IRQHandler + PUBWEAK Timer0A_IRQHandler + PUBWEAK Timer0B_IRQHandler + PUBWEAK Timer1A_IRQHandler + PUBWEAK Timer1B_IRQHandler + PUBWEAK Timer2A_IRQHandler + PUBWEAK Timer2B_IRQHandler + PUBWEAK Comp0_IRQHandler + PUBWEAK Comp1_IRQHandler + PUBWEAK Comp2_IRQHandler + PUBWEAK SysCtrl_IRQHandler + PUBWEAK FlashCtrl_IRQHandler + PUBWEAK GPIOPortF_IRQHandler + PUBWEAK GPIOPortG_IRQHandler + PUBWEAK GPIOPortH_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK SSI1_IRQHandler + PUBWEAK Timer3A_IRQHandler + PUBWEAK Timer3B_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK QEI1_IRQHandler + PUBWEAK CAN0_IRQHandler + PUBWEAK CAN1_IRQHandler + PUBWEAK CAN2_IRQHandler + PUBWEAK Hibernate_IRQHandler + PUBWEAK USB0_IRQHandler + PUBWEAK PWMGen3_IRQHandler + PUBWEAK uDMAST_IRQHandler + PUBWEAK uDMAError_IRQHandler + PUBWEAK ADC1Seq0_IRQHandler + PUBWEAK ADC1Seq1_IRQHandler + PUBWEAK ADC1Seq2_IRQHandler + PUBWEAK ADC1Seq3_IRQHandler + PUBWEAK GPIOPortJ_IRQHandler + PUBWEAK GPIOPortK_IRQHandler + PUBWEAK GPIOPortL_IRQHandler + PUBWEAK SSI2_IRQHandler + PUBWEAK SSI3_IRQHandler + PUBWEAK UART3_IRQHandler + PUBWEAK UART4_IRQHandler + PUBWEAK UART5_IRQHandler + PUBWEAK UART6_IRQHandler + PUBWEAK UART7_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK I2C3_IRQHandler + PUBWEAK Timer4A_IRQHandler + PUBWEAK Timer4B_IRQHandler + PUBWEAK Timer5A_IRQHandler + PUBWEAK Timer5B_IRQHandler + PUBWEAK WideTimer0A_IRQHandler + PUBWEAK WideTimer0B_IRQHandler + PUBWEAK WideTimer1A_IRQHandler + PUBWEAK WideTimer1B_IRQHandler + PUBWEAK WideTimer2A_IRQHandler + PUBWEAK WideTimer2B_IRQHandler + PUBWEAK WideTimer3A_IRQHandler + PUBWEAK WideTimer3B_IRQHandler + PUBWEAK WideTimer4A_IRQHandler + PUBWEAK WideTimer4B_IRQHandler + PUBWEAK WideTimer5A_IRQHandler + PUBWEAK WideTimer5B_IRQHandler + PUBWEAK FPU_IRQHandler + PUBWEAK I2C4_IRQHandler + PUBWEAK I2C5_IRQHandler + PUBWEAK GPIOPortM_IRQHandler + PUBWEAK GPIOPortN_IRQHandler + PUBWEAK QEI2_IRQHandler + PUBWEAK GPIOPortP0_IRQHandler + PUBWEAK GPIOPortP1_IRQHandler + PUBWEAK GPIOPortP2_IRQHandler + PUBWEAK GPIOPortP3_IRQHandler + PUBWEAK GPIOPortP4_IRQHandler + PUBWEAK GPIOPortP5_IRQHandler + PUBWEAK GPIOPortP6_IRQHandler + PUBWEAK GPIOPortP7_IRQHandler + PUBWEAK GPIOPortQ0_IRQHandler + PUBWEAK GPIOPortQ1_IRQHandler + PUBWEAK GPIOPortQ2_IRQHandler + PUBWEAK GPIOPortQ3_IRQHandler + PUBWEAK GPIOPortQ4_IRQHandler + PUBWEAK GPIOPortQ5_IRQHandler + PUBWEAK GPIOPortQ6_IRQHandler + PUBWEAK GPIOPortQ7_IRQHandler + PUBWEAK GPIOPortR_IRQHandler + PUBWEAK GPIOPortS_IRQHandler + PUBWEAK PWM1Gen0_IRQHandler + PUBWEAK PWM1Gen1_IRQHandler + PUBWEAK PWM1Gen2_IRQHandler + PUBWEAK PWM1Gen3_IRQHandler + PUBWEAK PWM1Fault_IRQHandler + +Default_Handler +GPIOPortA_IRQHandler +GPIOPortB_IRQHandler +GPIOPortC_IRQHandler +GPIOPortD_IRQHandler +GPIOPortE_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SSI0_IRQHandler +I2C0_IRQHandler +PWMFault_IRQHandler +PWMGen0_IRQHandler +PWMGen1_IRQHandler +PWMGen2_IRQHandler +QEI0_IRQHandler +ADCSeq0_IRQHandler +ADCSeq1_IRQHandler +ADCSeq2_IRQHandler +ADCSeq3_IRQHandler +Watchdog_IRQHandler +Timer0A_IRQHandler +Timer0B_IRQHandler +Timer1A_IRQHandler +Timer1B_IRQHandler +Timer2A_IRQHandler +Timer2B_IRQHandler +Comp0_IRQHandler +Comp1_IRQHandler +Comp2_IRQHandler +SysCtrl_IRQHandler +FlashCtrl_IRQHandler +GPIOPortF_IRQHandler +GPIOPortG_IRQHandler +GPIOPortH_IRQHandler +UART2_IRQHandler +SSI1_IRQHandler +Timer3A_IRQHandler +Timer3B_IRQHandler +I2C1_IRQHandler +QEI1_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +CAN2_IRQHandler +Hibernate_IRQHandler +USB0_IRQHandler +PWMGen3_IRQHandler +uDMAST_IRQHandler +uDMAError_IRQHandler +ADC1Seq0_IRQHandler +ADC1Seq1_IRQHandler +ADC1Seq2_IRQHandler +ADC1Seq3_IRQHandler +GPIOPortJ_IRQHandler +GPIOPortK_IRQHandler +GPIOPortL_IRQHandler +SSI2_IRQHandler +SSI3_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +UART6_IRQHandler +UART7_IRQHandler +I2C2_IRQHandler +I2C3_IRQHandler +Timer4A_IRQHandler +Timer4B_IRQHandler +Timer5A_IRQHandler +Timer5B_IRQHandler +WideTimer0A_IRQHandler +WideTimer0B_IRQHandler +WideTimer1A_IRQHandler +WideTimer1B_IRQHandler +WideTimer2A_IRQHandler +WideTimer2B_IRQHandler +WideTimer3A_IRQHandler +WideTimer3B_IRQHandler +WideTimer4A_IRQHandler +WideTimer4B_IRQHandler +WideTimer5A_IRQHandler +WideTimer5B_IRQHandler +FPU_IRQHandler +I2C4_IRQHandler +I2C5_IRQHandler +GPIOPortM_IRQHandler +GPIOPortN_IRQHandler +QEI2_IRQHandler +GPIOPortP0_IRQHandler +GPIOPortP1_IRQHandler +GPIOPortP2_IRQHandler +GPIOPortP3_IRQHandler +GPIOPortP4_IRQHandler +GPIOPortP5_IRQHandler +GPIOPortP6_IRQHandler +GPIOPortP7_IRQHandler +GPIOPortQ0_IRQHandler +GPIOPortQ1_IRQHandler +GPIOPortQ2_IRQHandler +GPIOPortQ3_IRQHandler +GPIOPortQ4_IRQHandler +GPIOPortQ5_IRQHandler +GPIOPortQ6_IRQHandler +GPIOPortQ7_IRQHandler +GPIOPortR_IRQHandler +GPIOPortS_IRQHandler +PWM1Gen0_IRQHandler +PWM1Gen1_IRQHandler +PWM1Gen2_IRQHandler +PWM1Gen3_IRQHandler +PWM1Fault_IRQHandler + LDR r0,=str_Undefined + MOVS r1,#1 + B assert_failed +str_Undefined + DCB "Undefined" + ALIGNROM 2 + +;***************************************************************************** +; The function assert_failed defines the error/assertion handling policy +; for the application. After making sure that the stack is OK, this function +; calls DBC_fault_handler, which should NOT return (typically reset the CPU). +; +; NOTE: the function DBC_fault_handler should NOT return. +; +; The C proptotype of assert_failed() and DBC_fault_handler() are: +; void assert_failed(char const *file, int line); +; void DBC_fault_handler (char const *file, int line); +;***************************************************************************** + PUBLIC assert_failed + EXTERN DBC_fault_handler +assert_failed + LDR r2,=sfe(CSTACK) ; load the original top of stack + MOV sp,r2 ; re-set the SP in case of stack overflow + BL DBC_fault_handler ; call the application-specific handler + + B . ; should not be reached, but just in case... + + END ; end of module + diff --git a/3rd_party/ek-tm4c123gxl/mpu_armv7.h b/3rd_party/ek-tm4c123gxl/mpu_armv7.h new file mode 100644 index 0000000..9909f83 --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/3rd_party/ek-tm4c123gxl/rom.h b/3rd_party/ek-tm4c123gxl/rom.h new file mode 100644 index 0000000..78f3f5b --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/rom.h @@ -0,0 +1,8358 @@ +//============================================================================* +// +// rom.h - Macros to facilitate calling functions in the ROM. +// +// Copyright (c) 2007-2015 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.2.111 of the Tiva Peripheral Driver Library. +// +//============================================================================* + +#ifndef __DRIVERLIB_ROM_H__ +#define __DRIVERLIB_ROM_H__ + +#ifndef DEPRECATED +//============================================================================* +// +// ROM selection labels changed between TivaWare 2.0.1 and 2.1. The following +// labels are intended to ensure backwards compatibility for applications +// which have not yet been updated to use the replacement labels. +// +//============================================================================* +#ifdef TARGET_IS_SNOWFLAKE_RA0 +#define TARGET_IS_TM4C129_RA0 +#endif +#ifdef TARGET_IS_SNOWFLAKE_RA1 +#define TARGET_IS_TM4C129_RA1 +#endif +#ifdef TARGET_IS_SNOWFLAKE_RA2 +#define TARGET_IS_TM4C129_RA2 +#endif +#ifdef TARGET_IS_BLIZZARD_RA1 +#define TARGET_IS_TM4C123_RA1 +#endif +#ifdef TARGET_IS_BLIZZARD_RA2 +#define TARGET_IS_TM4C123_RA2 +#endif +#ifdef TARGET_IS_BLIZZARD_RA3 +#define TARGET_IS_TM4C123_RA3 +#endif +#ifdef TARGET_IS_BLIZZARD_RB0 +#define TARGET_IS_TM4C123_RB0 +#endif +#ifdef TARGET_IS_BLIZZARD_RB1 +#define TARGET_IS_TM4C123_RB1 +#endif +#endif + +//============================================================================* +// +// Pointers to the main API tables. +// +//============================================================================* +#define ROM_APITABLE ((uint32_t *)0x01000010) +#define ROM_VERSION (ROM_APITABLE[0]) +#define ROM_UARTTABLE ((uint32_t *)(ROM_APITABLE[1])) +#define ROM_SSITABLE ((uint32_t *)(ROM_APITABLE[2])) +#define ROM_I2CTABLE ((uint32_t *)(ROM_APITABLE[3])) +#define ROM_GPIOTABLE ((uint32_t *)(ROM_APITABLE[4])) +#define ROM_ADCTABLE ((uint32_t *)(ROM_APITABLE[5])) +#define ROM_COMPARATORTABLE ((uint32_t *)(ROM_APITABLE[6])) +#define ROM_FLASHTABLE ((uint32_t *)(ROM_APITABLE[7])) +#define ROM_PWMTABLE ((uint32_t *)(ROM_APITABLE[8])) +#define ROM_QEITABLE ((uint32_t *)(ROM_APITABLE[9])) +#define ROM_SYSTICKTABLE ((uint32_t *)(ROM_APITABLE[10])) +#define ROM_TIMERTABLE ((uint32_t *)(ROM_APITABLE[11])) +#define ROM_WATCHDOGTABLE ((uint32_t *)(ROM_APITABLE[12])) +#define ROM_SYSCTLTABLE ((uint32_t *)(ROM_APITABLE[13])) +#define ROM_INTERRUPTTABLE ((uint32_t *)(ROM_APITABLE[14])) +#define ROM_USBTABLE ((uint32_t *)(ROM_APITABLE[16])) +#define ROM_UDMATABLE ((uint32_t *)(ROM_APITABLE[17])) +#define ROM_CANTABLE ((uint32_t *)(ROM_APITABLE[18])) +#define ROM_HIBERNATETABLE ((uint32_t *)(ROM_APITABLE[19])) +#define ROM_MPUTABLE ((uint32_t *)(ROM_APITABLE[20])) +#define ROM_SOFTWARETABLE ((uint32_t *)(ROM_APITABLE[21])) +#define ROM_EPITABLE ((uint32_t *)(ROM_APITABLE[23])) +#define ROM_EEPROMTABLE ((uint32_t *)(ROM_APITABLE[24])) +#define ROM_FPUTABLE ((uint32_t *)(ROM_APITABLE[26])) +#define ROM_SMBUSTABLE ((uint32_t *)(ROM_APITABLE[29])) +#define ROM_SYSEXCTABLE ((uint32_t *)(ROM_APITABLE[30])) +#define ROM_ONEWIRETABLE ((uint32_t *)(ROM_APITABLE[34])) +#define ROM_SPIFLASHTABLE ((uint32_t *)(ROM_APITABLE[38])) +#define ROM_LCDTABLE ((uint32_t *)(ROM_APITABLE[41])) +#define ROM_EMACTABLE ((uint32_t *)(ROM_APITABLE[42])) +#define ROM_AESTABLE ((uint32_t *)(ROM_APITABLE[43])) +#define ROM_CRCTABLE ((uint32_t *)(ROM_APITABLE[44])) +#define ROM_DESTABLE ((uint32_t *)(ROM_APITABLE[45])) +#define ROM_SHAMD5TABLE ((uint32_t *)(ROM_APITABLE[46])) + +//============================================================================* +// +// Macros for calling ROM functions in the ADC API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDataGet \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + uint32_t *pui32Buffer))ROM_ADCTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + bool bMasked))ROM_ADCTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + uint32_t ui32Trigger, \ + uint32_t ui32Priority))ROM_ADCTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceStepConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + uint32_t ui32Step, \ + uint32_t ui32Config))ROM_ADCTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceOverflow \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceOverflowClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceUnderflow \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceUnderflowClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCProcessorTrigger \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCHardwareOversampleConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Factor))ROM_ADCTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + uint32_t ui32Config))ROM_ADCTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorRegionSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + uint32_t ui32LowRef, \ + uint32_t ui32HighRef))ROM_ADCTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorReset \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + bool bTrigger, \ + bool bInterrupt))ROM_ADCTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Status))ROM_ADCTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCReferenceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ref))ROM_ADCTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCReferenceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCPhaseDelaySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Phase))ROM_ADCTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCPhaseDelayGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ADCTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ADCTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_ADCTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCBusy \ + ((bool (*)(uint32_t ui32Base))ROM_ADCTABLE[34]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the AES API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_AESTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESAuthLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_AESTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_AESTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataAuth \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t ui32Length, \ + uint32_t *pui32Tag))ROM_AESTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t *pui32Dest, \ + uint32_t ui32Length))ROM_AESTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataProcessAuth \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t *pui32Dest, \ + uint32_t ui32Length, \ + uint32_t *pui32AuthSrc, \ + uint32_t ui32AuthLength, \ + uint32_t *pui32Tag))ROM_AESTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_AESTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataReadNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_AESTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_AESTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_AESTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_AESTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_AESTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIVSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32IVdata))ROM_AESTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESKey1Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key, \ + uint32_t ui32Keysize))ROM_AESTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESKey2Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key, \ + uint32_t ui32Keysize))ROM_AESTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESKey3Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key))ROM_AESTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Length))ROM_AESTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESReset \ + ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESTagRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32TagData))ROM_AESTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIVRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32IVdata))ROM_AESTABLE[22]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the CAN API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntClr))ROM_CANTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANInit \ + ((void (*)(uint32_t ui32Base))ROM_CANTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANEnable \ + ((void (*)(uint32_t ui32Base))ROM_CANTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANDisable \ + ((void (*)(uint32_t ui32Base))ROM_CANTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANBitTimingSet \ + ((void (*)(uint32_t ui32Base, \ + tCANBitClkParms *psClkParms))ROM_CANTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANBitTimingGet \ + ((void (*)(uint32_t ui32Base, \ + tCANBitClkParms *psClkParms))ROM_CANTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANMessageSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ObjID, \ + tCANMsgObject *psMsgObject, \ + tMsgObjType eMsgType))ROM_CANTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANMessageGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ObjID, \ + tCANMsgObject *psMsgObject, \ + bool bClrPendingInt))ROM_CANTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANStatusGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + tCANStsReg eStatusReg))ROM_CANTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANMessageClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ObjID))ROM_CANTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_CANTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_CANTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + tCANIntStsReg eIntStsReg))ROM_CANTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANRetryGet \ + ((bool (*)(uint32_t ui32Base))ROM_CANTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANRetrySet \ + ((void (*)(uint32_t ui32Base, \ + bool bAutoRetry))ROM_CANTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANErrCntrGet \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32RxCount, \ + uint32_t *pui32TxCount))ROM_CANTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANBitRateSet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SourceClock, \ + uint32_t ui32BitRate))ROM_CANTABLE[16]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the Comparator API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + uint32_t ui32Config))ROM_COMPARATORTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorRefSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ref))ROM_COMPARATORTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorValueGet \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + bool bMasked))ROM_COMPARATORTABLE[6]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the CRC API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CRCConfig))ROM_CRCTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCDataProcess \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t *pui32DataIn, \ + uint32_t ui32DataLength, \ + bool bPPResult))ROM_CRCTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_CRCTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCResultRead \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bPPResult))ROM_CRCTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCSeedSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seed))ROM_CRCTABLE[4]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the DES API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_DESTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_DESTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_DESTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataReadNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_DESTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t *pui32Dest, \ + uint32_t ui32Length))ROM_DESTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_DESTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_DESTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_DESTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_DESTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIVSet \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32IVdata))ROM_DESTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key))ROM_DESTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_DESTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESReset \ + ((void (*)(uint32_t ui32Base))ROM_DESTABLE[15]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the EEPROM API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMRead \ + ((void (*)(uint32_t *pui32Data, \ + uint32_t ui32Address, \ + uint32_t ui32Count))ROM_EEPROMTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockCountGet \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockHide \ + ((void (*)(uint32_t ui32Block))ROM_EEPROMTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockLock \ + ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockPasswordSet \ + ((uint32_t (*)(uint32_t ui32Block, \ + uint32_t *pui32Password, \ + uint32_t ui32Count))ROM_EEPROMTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockProtectGet \ + ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockProtectSet \ + ((uint32_t (*)(uint32_t ui32Block, \ + uint32_t ui32Protect))ROM_EEPROMTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockUnlock \ + ((uint32_t (*)(uint32_t ui32Block, \ + uint32_t *pui32Password, \ + uint32_t ui32Count))ROM_EEPROMTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_EEPROMTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) +#define ROM_EEPROMMassErase \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMProgram \ + ((uint32_t (*)(uint32_t *pui32Data, \ + uint32_t ui32Address, \ + uint32_t ui32Count))ROM_EEPROMTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMProgramNonBlocking \ + ((uint32_t (*)(uint32_t ui32Data, \ + uint32_t ui32Address))ROM_EEPROMTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMSizeGet \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMStatusGet \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMInit \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[17]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the EPI API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_EPITABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_EPITABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIDividerSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Divider))ROM_EPITABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigSDRAMSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32Refresh))ROM_EPITABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigGPModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32FrameCount, \ + uint32_t ui32MaxWait))ROM_EPITABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB8Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32MaxWait))ROM_EPITABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB16Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32MaxWait))ROM_EPITABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIAddressMapSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Map))ROM_EPITABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32DataSize, \ + uint32_t ui32Address))ROM_EPITABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadStart \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32Count))ROM_EPITABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadStop \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_EPITABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadCount \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_EPITABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadAvail \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadGet32 \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint32_t *pui32Buf))ROM_EPITABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadGet16 \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint16_t *pui16Buf))ROM_EPITABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadGet8 \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint8_t *pui8Buf))ROM_EPITABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIFIFOConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_EPITABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIWriteFIFOCountGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EPITABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EPITABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntErrorStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntErrorClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ErrFlags))ROM_EPITABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIDividerCSSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Divider))ROM_EPITABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIDMATxCount \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Count))ROM_EPITABLE[23]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB8CSSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB16CSSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB8TimingSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB16TimingSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32CR))ROM_EPITABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_EPITABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegGetNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t *pui32CR))ROM_EPITABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_EPITABLE[31]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the EMAC API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_EMACTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Index, \ + uint8_t *pui8MACAddr))ROM_EMACTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Index, \ + const uint8_t *pui8MACAddr))ROM_EMACTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACConfigGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Config, \ + uint32_t *pui32Mode, \ + uint32_t *pui32RxMaxFrameSize))ROM_EMACTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32ModeFlags, \ + uint32_t ui32RxMaxFrameSize))ROM_EMACTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACDMAStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACFrameFilterGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACFrameFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32FilterOpts))ROM_EMACTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACInit \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SysClk, \ + uint32_t ui32BusConfig, \ + uint32_t ui32RxBurst, \ + uint32_t ui32TxBurst, \ + uint32_t ui32DescSkipSize))ROM_EMACTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EMACTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EMACTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EMACTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_EMACTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYPowerOff \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr))ROM_EMACTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYPowerOn \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr))ROM_EMACTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint8_t ui8RegAddr))ROM_EMACTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint8_t ui8RegAddr, \ + uint16_t ui16Data))ROM_EMACTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACReset \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMACurrentBufferGet \ + ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMACurrentDescriptorGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMADescriptorListGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMADescriptorListSet \ + ((void (*)(uint32_t ui32Base, \ + tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMAPollDemand \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxWatchdogTimerSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Timeout))ROM_EMACTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACStatusGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMACurrentBufferGet \ + ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMACurrentDescriptorGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMADescriptorListGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMADescriptorListSet \ + ((void (*)(uint32_t ui32Base, \ + tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMAPollDemand \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxFlush \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrFilterGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Index))ROM_EMACTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Index, \ + uint32_t ui32Config))ROM_EMACTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACHashFilterBitCalculate \ + ((uint32_t (*)(uint8_t *pui8MACAddr))ROM_EMACTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACHashFilterGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32HashHi, \ + uint32_t *pui32HashLo))ROM_EMACTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACHashFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32HashHi, \ + uint32_t ui32HashLo))ROM_EMACTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACNumAddrGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYExtendedRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint16_t ui16RegAddr))ROM_EMACTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYExtendedWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint16_t ui16RegAddr, \ + uint16_t ui16Data))ROM_EMACTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPowerManagementControlGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPowerManagementControlSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_EMACTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPowerManagementStatusGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRemoteWakeUpFrameFilterGet \ + ((void (*)(uint32_t ui32Base, \ + tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRemoteWakeUpFrameFilterSet \ + ((void (*)(uint32_t ui32Base, \ + const tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampAddendSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds))ROM_EMACTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampConfigGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t *pui32SubSecondInc))ROM_EMACTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32SubSecondInc))ROM_EMACTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSCommand \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Cmd))ROM_EMACTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSCommandModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_EMACTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSPeriodSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Period, \ + uint32_t ui32Width))ROM_EMACTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSSimpleModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32FreqConfig))ROM_EMACTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampSysTimeGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Seconds, \ + uint32_t *pui32SubSeconds))ROM_EMACTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampSysTimeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds, \ + uint32_t ui32SubSeconds))ROM_EMACTABLE[59]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampSysTimeUpdate \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds, \ + uint32_t ui32SubSeconds, \ + bool bInc))ROM_EMACTABLE[60]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampTargetIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[61]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampTargetIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[62]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampTargetSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds, \ + uint32_t ui32Nanoseconds))ROM_EMACTABLE[63]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANHashFilterBitCalculate \ + ((uint32_t (*)(uint16_t ui16Tag))ROM_EMACTABLE[64]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANHashFilterGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[65]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANHashFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Hash))ROM_EMACTABLE[66]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANRxConfigGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint16_t *pui16Tag))ROM_EMACTABLE[67]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANRxConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint16_t ui16Tag, \ + uint32_t ui32Config))ROM_EMACTABLE[68]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANTxConfigGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint16_t *pui16Tag))ROM_EMACTABLE[69]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANTxConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint16_t ui16Tag, \ + uint32_t ui32Config))ROM_EMACTABLE[70]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateEMAC \ + ((void (*)(uint32_t ui32Clock))ROM_EMACTABLE[71]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the Flash API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProgram \ + ((int32_t (*)(uint32_t *pui32Data, \ + uint32_t ui32Address, \ + uint32_t ui32Count))ROM_FLASHTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashErase \ + ((int32_t (*)(uint32_t ui32Address))ROM_FLASHTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProtectGet \ + ((tFlashProtection (*)(uint32_t ui32Address))ROM_FLASHTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProtectSet \ + ((int32_t (*)(uint32_t ui32Address, \ + tFlashProtection eProtect))ROM_FLASHTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProtectSave \ + ((int32_t (*)(void))ROM_FLASHTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashUserGet \ + ((int32_t (*)(uint32_t *pui32User0, \ + uint32_t *pui32User1))ROM_FLASHTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashUserSet \ + ((int32_t (*)(uint32_t ui32User0, \ + uint32_t ui32User1))ROM_FLASHTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashUserSave \ + ((int32_t (*)(void))ROM_FLASHTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_FLASHTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[13]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the FPU API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUEnable \ + ((void (*)(void))ROM_FPUTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUDisable \ + ((void (*)(void))ROM_FPUTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUFlushToZeroModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUHalfPrecisionModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPULazyStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUNaNModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPURoundingModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUStackingDisable \ + ((void (*)(void))ROM_FPUTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[8]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the GPIO API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinWrite \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint8_t ui8Val))ROM_GPIOTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODirModeSet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint32_t ui32PinIO))ROM_GPIOTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODirModeGet \ + ((uint32_t (*)(uint32_t ui32Port, \ + uint8_t ui8Pin))ROM_GPIOTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntTypeSet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint32_t ui32IntType))ROM_GPIOTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntTypeGet \ + ((uint32_t (*)(uint32_t ui32Port, \ + uint8_t ui8Pin))ROM_GPIOTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_GPIOPadConfigSet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint32_t ui32Strength, \ + uint32_t ui32PadType))ROM_GPIOTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPadConfigGet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pin, \ + uint32_t *pui32Strength, \ + uint32_t *pui32PadType))ROM_GPIOTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinRead \ + ((int32_t (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_GPIOPinTypeCAN \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeComparator \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeGPIOInput \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeGPIOOutput \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeI2C \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypePWM \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeQEI \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeSSI \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeTimer \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeUART \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeGPIOOutputOD \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeADC \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeUSBDigital \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinConfigure \ + ((void (*)(uint32_t ui32PinConfig))ROM_GPIOTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeUSBAnalog \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODMATriggerEnable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODMATriggerDisable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOADCTriggerEnable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOADCTriggerDisable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeI2CSCL \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeOneWire \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeWakeHigh \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeWakeLow \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntClear \ + ((void (*)(uint32_t ui32Port, \ + uint32_t ui32IntFlags))ROM_GPIOTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntDisable \ + ((void (*)(uint32_t ui32Port, \ + uint32_t ui32IntFlags))ROM_GPIOTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntEnable \ + ((void (*)(uint32_t ui32Port, \ + uint32_t ui32IntFlags))ROM_GPIOTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntStatus \ + ((uint32_t (*)(uint32_t ui32Port, \ + bool bMasked))ROM_GPIOTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinWakeStatus \ + ((uint32_t (*)(uint32_t ui32Port))ROM_GPIOTABLE[55]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the Hibernate API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateEnableExpClk \ + ((void (*)(uint32_t ui32HibClk))ROM_HIBERNATETABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateWakeSet \ + ((void (*)(uint32_t ui32WakeFlags))ROM_HIBERNATETABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateWakeGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateLowBatSet \ + ((void (*)(uint32_t ui32LowBatFlags))ROM_HIBERNATETABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateLowBatGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSet \ + ((void (*)(uint32_t ui32RTCValue))ROM_HIBERNATETABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCTrimSet \ + ((void (*)(uint32_t ui32Trim))ROM_HIBERNATETABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCTrimGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateDataSet \ + ((void (*)(uint32_t *pui32Data, \ + uint32_t ui32Count))ROM_HIBERNATETABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateDataGet \ + ((void (*)(uint32_t *pui32Data, \ + uint32_t ui32Count))ROM_HIBERNATETABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRequest \ + ((void (*)(void))ROM_HIBERNATETABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_HIBERNATETABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIsActive \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSSGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateClockConfig \ + ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateBatCheckStart \ + ((void (*)(void))ROM_HIBERNATETABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateBatCheckDone \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateGPIORetentionEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateGPIORetentionDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateGPIORetentionGet \ + ((bool (*)(void))ROM_HIBERNATETABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCounterMode \ + ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarSet \ + ((void (*)(struct tm *psTime))ROM_HIBERNATETABLE[35]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarGet \ + ((int (*)(struct tm *psTime))ROM_HIBERNATETABLE[36]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarMatchSet \ + ((void (*)(uint32_t ui32Index, \ + struct tm *psTime))ROM_HIBERNATETABLE[37]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarMatchGet \ + ((void (*)(uint32_t ui32Index, \ + struct tm *psTime))ROM_HIBERNATETABLE[38]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEventsClear \ + ((void (*)(void))ROM_HIBERNATETABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEventsConfig \ + ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEventsGet \ + ((bool (*)(uint32_t ui32Index, \ + uint32_t *pui32RTC, \ + uint32_t *pui32Event))ROM_HIBERNATETABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperExtOscValid \ + ((bool (*)(void))ROM_HIBERNATETABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperExtOscRecover \ + ((void (*)(void))ROM_HIBERNATETABLE[45]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperIODisable \ + ((void (*)(uint32_t ui32Input))ROM_HIBERNATETABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperIOEnable \ + ((void (*)(uint32_t ui32Input, \ + uint32_t ui32Config))ROM_HIBERNATETABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperStatusGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCMatchGet \ + ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCMatchSet \ + ((void (*)(uint32_t ui32Match, \ + uint32_t ui32Value))ROM_HIBERNATETABLE[50]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSSMatchGet \ + ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSSMatchSet \ + ((void (*)(uint32_t ui32Match, \ + uint32_t ui32Value))ROM_HIBERNATETABLE[52]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the I2C API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterInitExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32I2CClk, \ + bool bFast))ROM_I2CTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveInit \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8SlaveAddr))ROM_I2CTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntClear \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntClear \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterSlaveAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8SlaveAddr, \ + bool bReceive))ROM_I2CTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBusy \ + ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBusBusy \ + ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Cmd))ROM_I2CTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterErr \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterDataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveDataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateI2C \ + ((void (*)(void))ROM_I2CTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntClearEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntClearEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterTimeoutSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Value))ROM_I2CTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveACKOverride \ + ((void (*)(uint32_t ui32Base, \ + bool bEnable))ROM_I2CTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveACKValueSet \ + ((void (*)(uint32_t ui32Base, \ + bool bACK))ROM_I2CTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveAddressSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8AddrNum, \ + uint8_t ui8SlaveAddr))ROM_I2CTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterLineStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CTxFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CTxFIFOFlush \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CRxFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CRxFIFOFlush \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFOStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataPutNonBlocking \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataGetNonBlocking \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t *pui8Data))ROM_I2CTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBurstLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Length))ROM_I2CTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBurstCountGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveFIFODisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveFIFOEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterGlitchFilterConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[54]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the Interrupt API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntEnable \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntMasterEnable \ + ((bool (*)(void))ROM_INTERRUPTTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntMasterDisable \ + ((bool (*)(void))ROM_INTERRUPTTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntDisable \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityGroupingSet \ + ((void (*)(uint32_t ui32Bits))ROM_INTERRUPTTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityGroupingGet \ + ((uint32_t (*)(void))ROM_INTERRUPTTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPrioritySet \ + ((void (*)(uint32_t ui32Interrupt, \ + uint8_t ui8Priority))ROM_INTERRUPTTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityGet \ + ((int32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPendSet \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPendClear \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityMaskSet \ + ((void (*)(uint32_t ui32PriorityMask))ROM_INTERRUPTTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityMaskGet \ + ((uint32_t (*)(void))ROM_INTERRUPTTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntIsEnabled \ + ((uint32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntTrigger \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[13]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the LCD API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_LCDTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDClockReset \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Clocks))ROM_LCDTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDDMAConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_LCDTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDCommandWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Cmd))ROM_LCDTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_LCDTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDataRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_LCDTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Data))ROM_LCDTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDMADisable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDMAWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + const uint32_t *pui32Data, \ + uint32_t ui32Count))ROM_LCDTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDIndexedRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Addr))ROM_LCDTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDIndexedWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Addr, \ + uint16_t ui16Data))ROM_LCDTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDStatusRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_LCDTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDTimingSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + const tLCDIDDTiming *pTiming))ROM_LCDTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_LCDTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_LCDTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_LCDTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDModeSet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t ui8Mode, \ + uint32_t ui32PixClk, \ + uint32_t ui32SysClk))ROM_LCDTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterACBiasIntCountSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Count))ROM_LCDTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint8_t ui8PalLoadDelay))ROM_LCDTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterDisable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterEnable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterFrameBufferSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Buffer, \ + uint32_t *pui32Addr, \ + uint32_t ui32NumBytes))ROM_LCDTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterPaletteSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Type, \ + uint32_t *pui32PalAddr, \ + const uint32_t *pui32SrcColors, \ + uint32_t ui32Start, \ + uint32_t ui32Count))ROM_LCDTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterSubPanelConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags, \ + uint32_t ui32BottomLines, \ + uint32_t ui32DefaultPixel))ROM_LCDTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterSubPanelDisable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterSubPanelEnable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterTimingSet \ + ((void (*)(uint32_t ui32Base, \ + const tLCDRasterTiming *pTiming))ROM_LCDTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterEnabled \ + ((bool (*)(uint32_t ui32Base))ROM_LCDTABLE[27]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the MPU API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPUEnable \ + ((void (*)(uint32_t ui32MPUConfig))ROM_MPUTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPUDisable \ + ((void (*)(void))ROM_MPUTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionCountGet \ + ((uint32_t (*)(void))ROM_MPUTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionEnable \ + ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionDisable \ + ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionSet \ + ((void (*)(uint32_t ui32Region, \ + uint32_t ui32Addr, \ + uint32_t ui32Flags))ROM_MPUTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionGet \ + ((void (*)(uint32_t ui32Region, \ + uint32_t *pui32Addr, \ + uint32_t *pui32Flags))ROM_MPUTABLE[6]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the OneWire API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_ONEWIRETABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireBusReset \ + ((void (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireBusStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDataGet \ + ((void (*)(uint32_t u3i2Base, \ + uint32_t *pui32Data))ROM_ONEWIRETABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDataGetNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Data))ROM_ONEWIRETABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireInit \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32InitFlags))ROM_ONEWIRETABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ONEWIRETABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ONEWIRETABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ONEWIRETABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireTransaction \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32OpFlags, \ + uint32_t ui32Data, \ + uint32_t ui32BitCnt))ROM_ONEWIRETABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[11]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the PWM API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMPulseWidthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOut, \ + uint32_t ui32Width))ROM_PWMTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Config))ROM_PWMTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenPeriodSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Period))ROM_PWMTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenPeriodGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMPulseWidthGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOut))ROM_PWMTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMDeadBandEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint16_t ui16Rise, \ + uint16_t ui16Fall))ROM_PWMTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMDeadBandDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMSyncUpdate \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenBits))ROM_PWMTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMSyncTimeBase \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenBits))ROM_PWMTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputState \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bEnable))ROM_PWMTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputInvert \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bInvert))ROM_PWMTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputFault \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bFaultSuppress))ROM_PWMTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntTrigEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32IntTrig))ROM_PWMTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntTrigDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32IntTrig))ROM_PWMTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + bool bMasked))ROM_PWMTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Ints))ROM_PWMTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenFault))ROM_PWMTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenFault))ROM_PWMTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMFaultIntClear \ + ((void (*)(uint32_t ui32Base))ROM_PWMTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_PWMTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputFaultLevel \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bDriveHigh))ROM_PWMTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMFaultIntClearExt \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32FaultInts))ROM_PWMTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32MinFaultPeriod, \ + uint32_t ui32FaultSenses))ROM_PWMTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultTriggerSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group, \ + uint32_t ui32FaultTriggers))ROM_PWMTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultTriggerGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group))ROM_PWMTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group))ROM_PWMTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group, \ + uint32_t ui32FaultTriggers))ROM_PWMTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMClockSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_PWMTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMClockGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_PWMTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputUpdateMode \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + uint32_t ui32Mode))ROM_PWMTABLE[31]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the QEI API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIPositionGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIEnable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIDisable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32MaxPosition))ROM_QEITABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIPositionSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Position))ROM_QEITABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIDirectionGet \ + ((int32_t (*)(uint32_t ui32Base))ROM_QEITABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIErrorGet \ + ((bool (*)(uint32_t ui32Base))ROM_QEITABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityEnable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityDisable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PreDiv, \ + uint32_t ui32Period))ROM_QEITABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_QEITABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_QEITABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_QEITABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_QEITABLE[14]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the SHAMD5 API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_SHAMD5TABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5ConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_SHAMD5TABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DataProcess \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32DataSrc, \ + uint32_t ui32DataLength, \ + uint32_t *pui32HashResult))ROM_SHAMD5TABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DMADisable \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DMAEnable \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HashLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_SHAMD5TABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACPPKeyGenerate \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key, \ + uint32_t *pui32PPKey))ROM_SHAMD5TABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACPPKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACProcess \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32DataSrc, \ + uint32_t ui32DataLength, \ + uint32_t *pui32HashResult))ROM_SHAMD5TABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5Reset \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5ResultRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_SHAMD5TABLE[16]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the SMBus API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterIntProcess \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPUDIDPacketDecode \ + ((void (*)(tSMBusUDID *pUDID, \ + uint8_t *pui8Address, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPUDIDPacketEncode \ + ((void (*)(tSMBusUDID *pUDID, \ + uint8_t ui8Address, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPAssignAddress \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPGetUDIDDir \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPGetUDIDGen \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPNotifyMaster \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPPrepareToARP \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPResetDeviceDir \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress))ROM_SMBUSTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPResetDeviceGen \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterBlockProcessCall \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8TxData, \ + uint8_t ui8TxSize, \ + uint8_t *pui8RxData))ROM_SMBUSTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterBlockRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterBlockWrite \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteReceive \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteSend \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Data))ROM_SMBUSTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteWordRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteWordWrite \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterHostNotify \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8OwnSlaveAddress, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterI2CRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterI2CWrite \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterI2CWriteRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8TxData, \ + uint8_t ui8TxSize, \ + uint8_t *pui8RxData, \ + uint8_t ui8RxSize))ROM_SMBUSTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterInit \ + ((void (*)(tSMBus *psSMBus, \ + uint32_t ui32I2CBase, \ + uint32_t ui32SMBusClock))ROM_SMBUSTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterIntEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterProcessCall \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8TxData, \ + uint8_t *pui8RxData))ROM_SMBUSTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterQuickCommand \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + bool bData))ROM_SMBUSTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusPECDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusPECEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusRxPacketSizeGet \ + ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveACKSend \ + ((void (*)(tSMBus *psSMBus, \ + bool bACK))ROM_SMBUSTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveAddressSet \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t ui8AddressNum, \ + uint8_t ui8SlaveAddress))ROM_SMBUSTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagARGet \ + ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagARSet \ + ((void (*)(tSMBus *psSMBus, \ + bool bValue))ROM_SMBUSTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagAVGet \ + ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagAVSet \ + ((void (*)(tSMBus *psSMBus, \ + bool bValue))ROM_SMBUSTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveBlockTransferDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveBlockTransferEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveCommandGet \ + ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveI2CDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveI2CEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveInit \ + ((void (*)(tSMBus *psSMBus, \ + uint32_t ui32I2CBase))ROM_SMBUSTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveIntAddressGet \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveIntEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveIntProcess \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveManualACKDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveManualACKEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveManualACKStatusGet \ + ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveProcessCallDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveProcessCallEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveRxBufferSet \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveTransferInit \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveTxBufferSet \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveUDIDSet \ + ((void (*)(tSMBus *psSMBus, \ + tSMBusUDID *pUDID))ROM_SMBUSTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusStatusGet \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveDataSend \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusFIFOEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusFIFODisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusDMAEnable \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t ui8TxChannel, \ + uint8_t ui8RxChannel))ROM_SMBUSTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusDMADisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[59]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the SPIFlash API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashIntHandler \ + ((uint32_t (*)(tSPIFlashState *pState))ROM_SPIFLASHTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashInit \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Clock, \ + uint32_t ui32BitRate))ROM_SPIFLASHTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashWriteStatus \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Status))ROM_SPIFLASHTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashPageProgram \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashPageProgramNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel))ROM_SPIFLASHTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashWriteDisable \ + ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashReadStatus \ + ((uint8_t (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashWriteEnable \ + ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashFastRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashFastReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashSectorErase \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr))ROM_SPIFLASHTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashDualRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashDualReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashBlockErase32 \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr))ROM_SPIFLASHTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashQuadRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashQuadReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashReadID \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8ManufacturerID, \ + uint16_t *pui16DeviceID))ROM_SPIFLASHTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashChipErase \ + ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashBlockErase64 \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr))ROM_SPIFLASHTABLE[20]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the SSI API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SSIClk, \ + uint32_t ui32Protocol, \ + uint32_t ui32Mode, \ + uint32_t ui32BitRate, \ + uint32_t ui32DataWidth))ROM_SSITABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIEnable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDisable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SSITABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SSITABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_SSITABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SSITABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataPutNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Data))ROM_SSITABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t *pui32Data))ROM_SSITABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateSSI \ + ((void (*)(void))ROM_SSITABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_SSITABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_SSITABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIBusy \ + ((bool (*)(uint32_t ui32Base))ROM_SSITABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIClockSourceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_SSITABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIClockSourceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Source))ROM_SSITABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_SSITABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvDataPutFrameEnd \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvDataPutFrameEndNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvFrameHoldEnable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvFrameHoldDisable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[21]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the SysCtl API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlSRAMSizeGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlFlashSizeGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralPresent \ + ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralReset \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralEnable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralDisable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralSleepEnable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralSleepDisable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralDeepSleepEnable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralDeepSleepDisable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralClockGating \ + ((void (*)(bool bEnable))ROM_SYSCTLTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntEnable \ + ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntDisable \ + ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntClear \ + ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_SYSCTLTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlReset \ + ((void (*)(void))ROM_SYSCTLTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlDeepSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetCauseGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetCauseClear \ + ((void (*)(uint32_t ui32Causes))ROM_SYSCTLTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlClockSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlClockGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlPWMClockSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlPWMClockGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlUSBPLLEnable \ + ((void (*)(void))ROM_SYSCTLTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlUSBPLLDisable \ + ((void (*)(void))ROM_SYSCTLTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlDelay \ + ((void (*)(uint32_t ui32Count))ROM_SYSCTLTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralReady \ + ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralPowerOn \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralPowerOff \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlMOSCConfigSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPIOSCCalibrate \ + ((uint32_t (*)(uint32_t ui32Type))ROM_SYSCTLTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlDeepSleepClockSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlDeepSleepClockConfigSet \ + ((void (*)(uint32_t ui32Div, \ + uint32_t ui32Config))ROM_SYSCTLTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlClockFreqSet \ + ((uint32_t (*)(uint32_t ui32Config, \ + uint32_t ui32SysClock))ROM_SYSCTLTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetBehaviorSet \ + ((void (*)(uint32_t ui32Behavior))ROM_SYSCTLTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetBehaviorGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlFlashSectorSizeGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlVoltageEventConfig \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlVoltageEventStatus \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlVoltageEventClear \ + ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlNMIStatus \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlNMIClear \ + ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[59]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlClockOutConfig \ + ((void (*)(uint32_t ui32Config, \ + uint32_t ui32Div))ROM_SYSCTLTABLE[60]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlAltClkConfig \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[61]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the SysExc API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_SYSEXCTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[3]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the SysTick API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickValueGet \ + ((uint32_t (*)(void))ROM_SYSTICKTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickIntEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickIntDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickPeriodSet \ + ((void (*)(uint32_t ui32Period))ROM_SYSTICKTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickPeriodGet \ + ((uint32_t (*)(void))ROM_SYSTICKTABLE[6]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the Timer API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_TIMERTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_TIMERTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlLevel \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bInvert))ROM_TIMERTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA1) +#define ROM_TimerControlTrigger \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bEnable))ROM_TIMERTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlEvent \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Event))ROM_TIMERTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlStall \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bStall))ROM_TIMERTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerRTCEnable \ + ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerRTCDisable \ + ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleMatchSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleMatchGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerLoadSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerLoadGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerValueGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerMatchSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerMatchGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_TIMERTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_TIMERTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_TIMERTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlWaitOnTrigger \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bWait))ROM_TIMERTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerLoadSet64 \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Value))ROM_TIMERTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerLoadGet64 \ + ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerValueGet64 \ + ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerMatchSet64 \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Value))ROM_TIMERTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerMatchGet64 \ + ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerClockSourceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerClockSourceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Source))ROM_TIMERTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerADCEventGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerADCEventSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ADCEvent))ROM_TIMERTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerDMAEventGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerDMAEventSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAEvent))ROM_TIMERTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerSynchronize \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timers))ROM_TIMERTABLE[34]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the UART API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharPut \ + ((void (*)(uint32_t ui32Base, \ + unsigned char ucData))ROM_UARTTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTParityModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Parity))ROM_UARTTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTParityModeGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFOLevelSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32TxLevel, \ + uint32_t ui32RxLevel))ROM_UARTTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32TxLevel, \ + uint32_t *pui32RxLevel))ROM_UARTTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32UARTClk, \ + uint32_t ui32Baud, \ + uint32_t ui32Config))ROM_UARTTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32UARTClk, \ + uint32_t *pui32Baud, \ + uint32_t *pui32Config))ROM_UARTTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTEnableSIR \ + ((void (*)(uint32_t ui32Base, \ + bool bLowPower))ROM_UARTTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDisableSIR \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharsAvail \ + ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTSpaceAvail \ + ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharGet \ + ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharPutNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + unsigned char ucData))ROM_UARTTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTBreakCtl \ + ((void (*)(uint32_t ui32Base, \ + bool bBreakState))ROM_UARTTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_UARTTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_UARTTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_UARTTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_UARTTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateUART \ + ((void (*)(void))ROM_UARTTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_UARTTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_UARTTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFOEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFODisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTBusy \ + ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTTxIntModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_UARTTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTTxIntModeGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTRxErrorGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTRxErrorClear \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTClockSourceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Source))ROM_UARTTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTClockSourceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitDisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Addr, \ + uint8_t ui8Mask))ROM_UARTTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitAddrSend \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Addr))ROM_UARTTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTSmartCardDisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTSmartCardEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemControlClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Control))ROM_UARTTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemControlGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemControlSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Control))ROM_UARTTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemStatusGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFlowControlGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFlowControlSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_UARTTABLE[44]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the uDMA API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelTransferSet \ + ((void (*)(uint32_t ui32ChannelStructIndex, \ + uint32_t ui32Mode, \ + void *pvSrcAddr, \ + void *pvDstAddr, \ + uint32_t ui32TransferSize))ROM_UDMATABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAEnable \ + ((void (*)(void))ROM_UDMATABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMADisable \ + ((void (*)(void))ROM_UDMATABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAErrorStatusGet \ + ((uint32_t (*)(void))ROM_UDMATABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAErrorStatusClear \ + ((void (*)(void))ROM_UDMATABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelEnable \ + ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelDisable \ + ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelIsEnabled \ + ((bool (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAControlBaseSet \ + ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAControlBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelRequest \ + ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(uint32_t ui32ChannelNum, \ + uint32_t ui32Attr))ROM_UDMATABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(uint32_t ui32ChannelNum, \ + uint32_t ui32Attr))ROM_UDMATABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAttributeGet \ + ((uint32_t (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelControlSet \ + ((void (*)(uint32_t ui32ChannelStructIndex, \ + uint32_t ui32Control))ROM_UDMATABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelSizeGet \ + ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelModeGet \ + ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelSelectSecondary \ + ((void (*)(uint32_t ui32SecPeriphs))ROM_UDMATABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelSelectDefault \ + ((void (*)(uint32_t ui32DefPeriphs))ROM_UDMATABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAIntStatus \ + ((uint32_t (*)(void))ROM_UDMATABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAIntClear \ + ((void (*)(uint32_t ui32ChanMask))ROM_UDMATABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAControlAlternateBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(uint32_t ui32ChannelNum, \ + uint32_t ui32TaskCount, \ + void *pvTaskList, \ + uint32_t ui32IsPeriphSG))ROM_UDMATABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAssign \ + ((void (*)(uint32_t ui32Mapping))ROM_UDMATABLE[23]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the USB API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevAddrGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Address))ROM_USBTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevConnect \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevDisconnect \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32MaxPacketSize, \ + uint32_t ui32Flags))ROM_USBTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointDataAck \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + bool bIsLastPacket))ROM_USBTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointStall \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointStallClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointStatusClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataGet \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint8_t *pui8Data, \ + uint32_t *pui32Size))ROM_USBTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataPut \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint8_t *pui8Data, \ + uint32_t ui32Size))ROM_USBTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataSend \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32TransType))ROM_USBTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataToggleClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOAddrGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOConfigGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t *pui32FIFOAddress, \ + uint32_t *pui32FIFOSize, \ + uint32_t ui32Flags))ROM_USBTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32FIFOAddress, \ + uint32_t ui32FIFOSize, \ + uint32_t ui32Flags))ROM_USBTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOFlush \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFrameNumberGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostAddrGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Addr, \ + uint32_t ui32Flags))ROM_USBTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32MaxPacketSize, \ + uint32_t ui32NAKPollInterval, \ + uint32_t ui32TargetEndpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointDataAck \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointDataToggle \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + bool bDataToggle, \ + uint32_t ui32Flags))ROM_USBTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointStatusClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostHubAddrGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostHubAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Addr, \ + uint32_t ui32Flags))ROM_USBTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_USBTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrFaultDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrFaultEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostRequestIN \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostRequestStatus \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostReset \ + ((void (*)(uint32_t ui32Base, \ + bool bStart))ROM_USBTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostResume \ + ((void (*)(uint32_t ui32Base, \ + bool bStart))ROM_USBTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostSpeedGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostSuspend \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointConfigGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t *pui32MaxPacketSize, \ + uint32_t *pui32Flags))ROM_USBTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataAvail \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBModeGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMAChannel \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Channel))ROM_USBTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntDisableControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntEnableControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntStatusControl \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntDisableEndpoint \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntEnableEndpoint \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntStatusEndpoint \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostMode \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevMode \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBPHYPowerOff \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBPHYPowerOn \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateUSB \ + ((void (*)(uint8_t *pui8DescriptorInfo))ROM_USBTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBOTGMode \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[59]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostRequestINClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[60]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBNumEndpointsGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[61]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBClockDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[62]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBClockEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Div, \ + uint32_t ui32Flags))ROM_USBTABLE[63]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBControllerVersion \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[64]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_USBTABLE[65]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[66]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[67]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMRemoteWake \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[68]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevSpeedGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[69]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelAddressGet \ + ((void * (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[70]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelAddressSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + void *pvAddress))ROM_USBTABLE[71]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Config))ROM_USBTABLE[72]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[73]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[74]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[75]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[76]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelCountGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[77]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelCountSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint32_t ui32Channel))ROM_USBTABLE[78]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[79]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[80]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelStatusClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32Status))ROM_USBTABLE[81]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHighSpeed \ + ((void (*)(uint32_t ui32Base, \ + bool bEnable))ROM_USBTABLE[82]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointPing \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + bool bEnable))ROM_USBTABLE[83]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointSpeed \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[84]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostLPMConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ResumeTime, \ + uint32_t ui32Config))ROM_USBTABLE[85]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostLPMResume \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[86]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostLPMSend \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Address, \ + uint32_t uiEndpoint))ROM_USBTABLE[87]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ints))ROM_USBTABLE[88]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ints))ROM_USBTABLE[89]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[90]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMLinkStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[91]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointPacketCountSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Count))ROM_USBTABLE[92]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_USBTABLE[93]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[94]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[95]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIRegRead \ + ((uint8_t (*)(uint32_t ui32Base, \ + uint8_t ui8Reg))ROM_USBTABLE[96]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIRegWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Reg, \ + uint8_t ui8Data))ROM_USBTABLE[97]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBOTGSessionRequest \ + ((void (*)(uint32_t ui32Base, \ + bool bStart))ROM_USBTABLE[98]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMANumChannels \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[99]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMAConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Config))ROM_USBTABLE[100]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMRemoteWakeEnabled \ + ((bool (*)(uint32_t ui32Base))ROM_USBTABLE[102]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBModeConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_USBTABLE[103]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the Watchdog API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntClear \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogRunning \ + ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogResetEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogResetDisable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogLock \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogUnlock \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogLockState \ + ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogReloadSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32LoadVal))ROM_WATCHDOGTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogReloadGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogValueGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_WATCHDOGTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogStallEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogStallDisable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntTypeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Type))ROM_WATCHDOGTABLE[15]) +#endif + +//============================================================================* +// +// Macros for calling ROM functions in the Software API. +// +//============================================================================* +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc16Array \ + ((uint16_t (*)(uint32_t ui32WordLen, \ + const uint32_t *pui32Data))ROM_SOFTWARETABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc16Array3 \ + ((void (*)(uint32_t ui32WordLen, \ + const uint32_t *pui32Data, \ + uint16_t *pui16Crc3))ROM_SOFTWARETABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc16 \ + ((uint16_t (*)(uint16_t ui16Crc, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SOFTWARETABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc8CCITT \ + ((uint8_t (*)(uint8_t ui8Crc, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SOFTWARETABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc32 \ + ((uint32_t (*)(uint32_t ui32Crc, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SOFTWARETABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_pvAESTable \ + ((void *)&(ROM_SOFTWARETABLE[7])) +#endif + +#endif // __DRIVERLIB_ROM_H__ diff --git a/3rd_party/ek-tm4c123gxl/sysctl.h b/3rd_party/ek-tm4c123gxl/sysctl.h new file mode 100644 index 0000000..d834d33 --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/sysctl.h @@ -0,0 +1,644 @@ +//============================================================================* +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 9453 of the Stellaris Peripheral Driver Library. +// +//============================================================================* + +#ifndef __SYSCTL_H__ +#define __SYSCTL_H__ + +//============================================================================* +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//============================================================================* +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef unsigned char tBoolean; + +//============================================================================* +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ulPeripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//============================================================================* +#ifndef DEPRECATED +#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog +#endif +#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0 +#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module +#ifndef DEPRECATED +#define SYSCTL_PERIPH_ADC 0x00100001 // ADC +#endif +#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0 +#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_PWM 0x00100010 // PWM +#endif +#define SYSCTL_PERIPH_PWM0 0x00100010 // PWM +#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 +#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 +#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2 +#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1 +#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 +#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 +#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_SSI 0x10000010 // SSI +#endif +#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 +#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_QEI 0x10000100 // QEI +#endif +#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 +#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 +#ifndef DEPRECATED +#define SYSCTL_PERIPH_I2C 0x10001000 // I2C +#endif +#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 +#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 +#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 +#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 +#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 +#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 +#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 +#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0 +#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0 +#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E +#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F +#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G +#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H +#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J +#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA +#define SYSCTL_PERIPH_USB0 0x20100001 // USB0 +#define SYSCTL_PERIPH_ETH 0x20105000 // Ethernet +#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588 +#define SYSCTL_PERIPH_PLL 0x30000010 // PLL +#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor +#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU +#define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0 +#define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1 +#define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0 +#define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1 +#define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2 +#define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0 +#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0 +#define SYSCTL_PERIPH2_EPI0 0xf0001000 // EPI0 +#define SYSCTL_PERIPH2_ETH 0xf0002c00 // ETH +#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0 +#define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A +#define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B +#define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C +#define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D +#define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E +#define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F +#define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G +#define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H +#define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J +#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K +#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L +#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M +#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N +#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P +#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q +#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R +#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S +#define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module +#define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0 +#define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1 +#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2 +#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3 +#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4 +#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5 +#define SYSCTL_PERIPH2_I2S0 0xf0002400 // I2S0 +#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0 +#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0 +#define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0 +#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1 +#define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0 +#define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1 +#define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0 +#define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1 +#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2 +#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3 +#define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0 +#define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1 +#define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2 +#define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3 +#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4 +#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5 +#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0 +#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1 +#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2 +#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3 +#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4 +#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5 +#define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0 +#define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1 +#define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2 +#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3 +#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4 +#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5 +#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6 +#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7 +#define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA +#define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0 +#define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0 +#define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1 +#define SYSCTL_PERIPH2_HIBERNATE \ + 0xf0001400 // Hibernate + +//============================================================================* +// +// The following are values that can be passed to the SysCtlPinPresent() API +// as the ulPin parameter. +// +//============================================================================* +#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin +#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin +#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin +#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin +#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin +#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin +#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin +#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin +#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin +#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin +#define SYSCTL_PIN_C0O 0x00000100 // C0o pin +#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin +#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin +#define SYSCTL_PIN_C1O 0x00000800 // C1o pin +#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin +#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin +#define SYSCTL_PIN_C2O 0x00004000 // C2o pin +#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin +#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin +#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin +#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin +#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin +#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin +#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin +#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin +#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin +#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin +#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin +#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin +#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin +#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin +#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin +#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin + +//============================================================================* +// +// The following are values that can be passed to the SysCtlLDOSet() API as +// the ulVoltage value, or returned by the SysCtlLDOGet() API. +// +//============================================================================* +#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V +#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V +#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V +#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V +#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V +#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V +#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V +#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V +#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V +#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V +#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V + +//============================================================================* +// +// The following are values that can be passed to the SysCtlLDOConfigSet() API. +// +//============================================================================* +#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset +#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure + +//============================================================================* +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//============================================================================* +#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt +#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt +#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt +#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt + +//============================================================================* +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//============================================================================* +#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset +#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset +#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//============================================================================* +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ulConfig parameter. +// +//============================================================================* +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//============================================================================* +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//============================================================================* +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//============================================================================* +// +// The following are values that can be passed to the SysCtlADCSpeedSet() API +// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() +// API. +// +//============================================================================* +#define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second +#define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second +#define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second +#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second + +//============================================================================* +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ulConfig parameter. +// +//============================================================================* +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 +#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 +#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 +#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 +#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 +#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 +#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 +#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 +#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 +#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 +#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 +#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 +#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 +#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 +#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 +#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 +#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 +#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 +#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 +#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 +#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 +#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 +#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 +#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 +#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 +#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 +#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 +#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 +#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 +#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 +#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 +#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 +#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 +#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 +#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 +#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 +#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 +#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 +#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 +#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 +#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 +#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 +#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 +#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 +#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 +#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 +#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 +#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 +#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5 +#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5 +#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5 +#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5 +#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5 +#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5 +#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5 +#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5 +#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5 +#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5 +#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5 +#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5 +#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5 +#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5 +#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5 +#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5 +#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5 +#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5 +#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5 +#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5 +#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5 +#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5 +#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5 +#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5 +#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5 +#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5 +#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5 +#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5 +#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5 +#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5 +#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5 +#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5 +#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5 +#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5 +#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5 +#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5 +#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5 +#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5 +#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5 +#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5 +#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5 +#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5 +#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5 +#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5 +#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5 +#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5 +#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5 +#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5 +#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5 +#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5 +#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5 +#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5 +#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5 +#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5 +#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5 +#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5 +#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5 +#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5 +#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5 +#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5 +#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5 +#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5 +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz +#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz +#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz +#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz +#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz +#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz +#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz +#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz +#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz +#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz +#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz +#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz +#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz +#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4 +#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz +#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//============================================================================* +// +// The following are values that can be passed to the SysCtlDeepSleepClockSet() +// API as the ulConfig parameter. +// +//============================================================================* +#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1 +#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2 +#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3 +#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4 +#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5 +#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6 +#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7 +#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8 +#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9 +#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10 +#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11 +#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12 +#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13 +#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14 +#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15 +#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16 +#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17 +#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18 +#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19 +#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20 +#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21 +#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22 +#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23 +#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24 +#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25 +#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26 +#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27 +#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28 +#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29 +#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30 +#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31 +#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32 +#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33 +#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34 +#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35 +#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36 +#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37 +#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38 +#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39 +#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40 +#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41 +#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42 +#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43 +#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44 +#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45 +#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46 +#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47 +#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48 +#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49 +#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50 +#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51 +#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52 +#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53 +#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54 +#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55 +#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56 +#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57 +#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58 +#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59 +#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60 +#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61 +#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62 +#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63 +#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64 +#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz +#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep + +//============================================================================* +// +// Prototypes for the APIs. +// +//============================================================================* +extern unsigned long SysCtlSRAMSizeGet(void); +extern unsigned long SysCtlFlashSizeGet(void); +extern tBoolean SysCtlPinPresent(unsigned long ulPin); +extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); +extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral); +extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral); +extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral); +extern void SysCtlPeripheralReset(unsigned long ulPeripheral); +extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); +extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); +extern void SysCtlPeripheralClockGating(tBoolean bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(unsigned long ulInts); +extern void SysCtlIntDisable(unsigned long ulInts); +extern void SysCtlIntClear(unsigned long ulInts); +extern unsigned long SysCtlIntStatus(tBoolean bMasked); +extern void SysCtlLDOSet(unsigned long ulVoltage); +extern unsigned long SysCtlLDOGet(void); +extern void SysCtlLDOConfigSet(unsigned long ulConfig); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern unsigned long SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(unsigned long ulCauses); +extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, + unsigned long ulDelay); +extern void SysCtlDelay(unsigned long ulCount); +extern void SysCtlMOSCConfigSet(unsigned long ulConfig); +extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType); +extern void SysCtlClockSet(unsigned long ulConfig); +extern unsigned long SysCtlClockGet(void); +extern void SysCtlDeepSleepClockSet(unsigned long ulConfig); +extern void SysCtlPWMClockSet(unsigned long ulConfig); +extern unsigned long SysCtlPWMClockGet(void); +extern void SysCtlADCSpeedSet(unsigned long ulSpeed); +extern unsigned long SysCtlADCSpeedGet(void); +extern void SysCtlIOSCVerificationSet(tBoolean bEnable); +extern void SysCtlMOSCVerificationSet(tBoolean bEnable); +extern void SysCtlPLLVerificationSet(tBoolean bEnable); +extern void SysCtlClkVerificationClear(void); +extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral); +extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral); +extern void SysCtlUSBPLLEnable(void); +extern void SysCtlUSBPLLDisable(void); +extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock, + unsigned long ulMClk); + +//============================================================================* +// +// Mark the end of the C bindings section for C++ compilers. +// +//============================================================================* +#ifdef __cplusplus +} +#endif + +#endif // __SYSCTL_H__ diff --git a/3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.c b/3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.c new file mode 100644 index 0000000..389266d --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.c @@ -0,0 +1,610 @@ +/**************************************************************************//** + * @file system_TM4C123GH6PM.c + * @brief CMSIS Device System Source File for + * Texas Instruments TIVA TM4C123 Device Series + * @version V1.00 + * @date 27. March 2013 + * + * @note + * modified by Keil + ******************************************************************************/ + +#include +#include "TM4C123GH6PM.h" + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +// +// This file can be used by the Keil uVision configuration wizard to set +// the following system clock configuration values. Or the value of the +// macros can be directly edited below if not using the uVision configuration +// wizard. +// +//--------------------- Clock Configuration ---------------------------------- +// +// Clock Configuration +// Uncheck this box to skip the clock configuration. +// +// The following controls whether the system clock is configured in the +// SystemInit() function. If it is defined to be 1 then the system clock +// will be configured according to the macros in the rest of this file. +// If it is defined to be 0, then the system clock configuration is bypassed. +// +#define CLOCK_SETUP 1 + +//********************************* RCC *************************************** +// +// Run-Mode Clock Configuration (RCC) + +// SYSDIV: System Clock Divisor <2-16> +// Specifies the divisor used to generate the system clock from +// either the PLL output of 200 MHz, or the chosen oscillator. +// +// The following value is the system clock divisor. This will be applied if +// USESYSDIV (see below) is enabled. The valid range of dividers is 2-16. +// +#define CFG_RCC_SYSDIV 4 + +// USESYSDIV: Enable System Clock Divider +// Check this box to use the System Clock Divider +// +// The following controls whether the system clock divider is used. If the +// value is 1, then the system clock divider is used, and the value of the +// system divider is defined by SYSDIV (see above). If the value is 0, then +// the system clock divider is not used. +// +#define CFG_RCC_USESYSDIV 1 + +// USEPWMDIV: Enable PWM Clock Divider +// Check this box to use the PWM Clock Divider +// +// The following controls whether the PWM clock divider is used. If the +// value is 1, then the PWM clock divider is used, and the value of the +// PWM divider is defined by PWMDIV (see below). If the value is 0, then +// the PWM clock divider is not used. +// +#define CFG_RCC_USEPWMDIV 1 + +// PWMDIV: PWM Unit Clock Divisor +// <0=> 0: SysClk / 2 +// <1=> 1: SysClk / 4 +// <2=> 2: SysClk / 8 +// <3=> 3: SysClk / 16 +// <4=> 4: SysClk / 32 +// <5=> 5: SysClk / 64 +// <6=> 6: SysClk / 64 +// <7=> 7: SysClk / 64 (default) +// Specifies the divisor used to generate the PWM time base, +// from the System Clock +// +// The following value determines the PWM clock divider. It is used if +// USEPWMDIV is enabled (see above). Otherwise the PWM clock is the same as +// the system clock. The value of the divider is determined by the table +// above. +// +#define CFG_RCC_PWMDIV 7 + +// PWRDN: PLL Power Down +// Check this box to disable the PLL. You must also choose +// PLL Bypass. +// +// If the following value is 1, then the PLL is powered down. Keep this value +// as 1 if you do not need to use the PLL. In this case, BYPASS (see below) +// must also be set to 1. If you are using the PLL, then this value must be +// set to 0. +// +#define CFG_RCC_PWRDN 0 + +// BYPASS: PLL Bypass +// Check this box to not use the PLL for the System Clock +// +// Set the following value to 1 to bypass the PLL and not use it for the +// system clock. You must set this to 1 if PWRDN (above) is set to 1. Set +// this to 0 if you are using the PLL. +// +#define CFG_RCC_BYPASS 0 + +// XTAL: Crystal Value +// < 0=> 0: 1.0000 MHz (can not be used with PLL) +// < 1=> 1: 1.8432 MHz (can not be used with PLL) +// < 2=> 2: 2.0000 MHz (can not be used with PLL) +// < 3=> 3: 2.4576 MHz (can not be used with PLL) +// < 4=> 4: 3.579545 MHz +// < 5=> 5: 3.6864 MHz +// < 6=> 6: 4.0000 MHz +// < 7=> 7: 4.096 MHz +// < 8=> 8: 4.9152 MHz +// < 9=> 9: 5.0000 MHz +// <10=> 10: 5.12 MHz +// <11=> 11: 6.0000 MHz (default) +// <12=> 12: 6.144 MHz +// <13=> 13: 7.3728 MHz +// <14=> 14: 8.0000 MHz +// <15=> 15: 8.192 MHz +// <16=> 16: 10.0 MHz +// <17=> 17: 12.0 MHz +// <18=> 18: 12.288 MHz +// <19=> 19: 13.56 MHz +// <20=> 20: 14.31818 MHz +// <21=> 21: 16.0 MHz +// <22=> 22: 16.384 MHz +// This is the crystal frequency used for the main oscillator +// +// This value defines the crystal frequency for the main oscillator, according +// to the table in the comments above. If an external crystal is used, then +// this value must be set to match the value of the crystal. +// +#define CFG_RCC_XTAL 21 + +// OSCSRC: Oscillator Source +// <0=> 0: MOSC Main oscillator +// <1=> 1: IOSC Internal oscillator (default) +// <2=> 2: IOSC/4 Internal oscillator / 4 (this is necessary if used as input to PLL) +// <3=> 3: 30kHz 30-KHz internal oscillator +// Chooses the oscillator that is used for the system clock, +// or the PLL input. +// +// The following value chooses the oscillator source according to the table in +// the comments above. +// +#define CFG_RCC_OSCSRC 0 + +// IOSCDIS: Internal Oscillator Disable +// Check this box to turn off the internal oscillator +// +// Set the following value to 1 to turn off the internal oscillator. This +// value can be set to 1 if you are not using the internal oscillator. +// +#define CFG_RCC_IOSCDIS 1 + +// MOSCDIS: Main Oscillator Disable +// Check this box to turn off the main oscillator +// +// Set the following value to 1 to turn off the main oscillator. This +// value can be set to 1 if you are not using the main oscillator. +// +#define CFG_RCC_MOSCDIS 0 + +// + +//********************************* RCC2 ************************************** +// +// Run-Mode Clock Configuration 2 (RCC2) + +// USERCC2: Use RCC2 +// Check this box to override some fields in RCC. RCC2 provides +// more bits for the system clock divider, and provides an +// additional oscillator source. If you do not need these +// additional features, then leave this box unchecked. +// +// Set the following value to 1 to use the RCC2 register. The RCC2 register +// overrides some of the fields in the RCC register if it is used. +// +#define CFG_RCC2_USERCC2 0 + +// SYSDIV2: System Clock Divisor <2-64> +// Specifies the divisor used to generate the system clock from +// either the PLL output of 200 MHz, or the oscillator. +// +// The following value is the system clock divisor. This will be applied if +// USESYSDIV in RCC is enabled. The valid range of dividers is 2-64. +// +#define CFG_RCC_SYSDIV2 4 + +// PWRDN2: Power Down PLL +// Check this box to disable the PLL. You must also choose +// PLL Bypass. +// +// If the following value is 1, then the PLL is powered down. Keep this value +// as 1 if you do not need to use the PLL. In this case, BYPASS2 (see below) +// must also be set to 1. If you are using the PLL, then this value must be +// set to 0. +// +#define CFG_RCC_PWRDN2 0 + +// BYPASS2: Bypass PLL +// Check this box to not use the PLL for the System Clock +// +// Set the following value to 1 to bypass the PLL and not use it for the +// system clock. You must set this to 1 if PWRDN2 (above) is set to 1. Set +// this to 0 if you are using the PLL. +// +#define CFG_RCC_BYPASS2 0 + +// OSCSRC2: Oscillator Source +// <0=> 0: MOSC Main oscillator +// <1=> 1: IOSC Internal oscillator (default) +// <2=> 2: IOSC/4 Internal oscillator / 4 (this is necessary if used as input to PLL) +// <3=> 3: 30kHz 30-kHz internal oscillator +// <7=> 7: 32kHz 32.768-kHz external oscillator +// The oscillator that is used for the system clock, or the PLL input. +// +// The following value chooses the oscillator source according to the table in +// the comments above. +// +#define CFG_RCC_OSCSRC2 0 + +// +// +// + +//-------- <<< end of configuration section >>> ------------------------------ + +// +// The following macros are used to program the RCC and RCC2 registers in +// the SystemInit() function. Edit the macros above to change these values. +// +#define RCC_Val \ +( \ + ((CFG_RCC_SYSDIV - 1) << 23) | \ + (CFG_RCC_USESYSDIV << 22) | \ + (CFG_RCC_USEPWMDIV << 20) | \ + (CFG_RCC_PWMDIV << 17) | \ + (CFG_RCC_PWRDN << 13) | \ + (CFG_RCC_BYPASS << 11) | \ + (CFG_RCC_XTAL << 6) | \ + (CFG_RCC_OSCSRC << 4) | \ + (CFG_RCC_IOSCDIS << 1) | \ + (CFG_RCC_MOSCDIS << 1)\ +) + +#define RCC2_Val \ +( \ + (CFG_RCC2_USERCC2 << 31) | \ + ((CFG_RCC_SYSDIV2 - 1) << 23) | \ + (CFG_RCC_PWRDN2 << 13) | \ + (CFG_RCC_BYPASS2 << 11) | \ + (CFG_RCC_OSCSRC2 << 4)\ +) + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTALM (16000000UL) /* Main oscillator freq */ +#define XTALI (12000000UL) /* Internal oscillator freq */ +#define XTAL30K ( 30000UL) /* Internal 30K oscillator freq */ +#define XTAL32K ( 32768UL) /* external 32K oscillator freq */ + +#define PLL_CLK (400000000UL) +#define ADC_CLK (PLL_CLK/25) +#define CAN_CLK (PLL_CLK/50) + + /* Determine clock frequency according to clock register values */ + #if (RCC2_Val & (1UL<<31)) /* is rcc2 used ? */ + #if (RCC2_Val & (1UL<<11)) /* check BYPASS */ + #if (((RCC2_Val>>4) & 0x07) == 0x0) + #if (((RCC_Val>>6) & 0x1F) == 0x0) + #define __CORE_CLK_PRE 1000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x1) + #define __CORE_CLK_PRE 1843200UL + #elif (((RCC_Val>>6) & 0x1F) == 0x2) + #define __CORE_CLK_PRE 2000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x3) + #define __CORE_CLK_PRE 2457600UL + #elif (((RCC_Val>>6) & 0x1F) == 0x4) + #define __CORE_CLK_PRE 3579545UL + #elif (((RCC_Val>>6) & 0x1F) == 0x5) + #define __CORE_CLK_PRE 3686400UL + #elif (((RCC_Val>>6) & 0x1F) == 0x6) + #define __CORE_CLK_PRE 4000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x7) + #define __CORE_CLK_PRE 4096000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x8) + #define __CORE_CLK_PRE 4915200UL + #elif (((RCC_Val>>6) & 0x1F) == 0x9) + #define __CORE_CLK_PRE 5000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0xA) + #define __CORE_CLK_PRE 5120000UL + #elif (((RCC_Val>>6) & 0x1F) == 0xB) + #define __CORE_CLK_PRE 6000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0xC) + #define __CORE_CLK_PRE 6144000UL + #elif (((RCC_Val>>6) & 0x1F) == 0xD) + #define __CORE_CLK_PRE 7372800UL + #elif (((RCC_Val>>6) & 0x1F) == 0xE) + #define __CORE_CLK_PRE 8000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0xF) + #define __CORE_CLK_PRE 8192000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x10) + #define __CORE_CLK_PRE 10000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x11) + #define __CORE_CLK_PRE 12000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x12) + #define __CORE_CLK_PRE 12288000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x13) + #define __CORE_CLK_PRE 13560000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x14) + #define __CORE_CLK_PRE 14318180UL + #elif (((RCC_Val>>6) & 0x1F) == 0x15) + #define __CORE_CLK_PRE 16000000UL + #else + #define __CORE_CLK_PRE 16384000UL + #endif + #elif (((RCC2_Val>>4) & 0x07) == 0x1) + #define __CORE_CLK_PRE XTALI + #elif (((RCC2_Val>>4) & 0x07) == 0x2) + #define __CORE_CLK_PRE (XTALI/4) + #else + #define __CORE_CLK_PRE XTAL30K + #endif + #else + #define __CORE_CLK_PRE PLL_CLK + #endif + #if (RCC_Val & (1UL<<22)) /* check USESYSDIV */ + #if (RCC2_Val & (1UL<<11)) + #define __CORE_CLK (__CORE_CLK_PRE / (((RCC2_Val>>23) & (0x3F)) + 1)) + #else + #define __CORE_CLK (__CORE_CLK_PRE / (((RCC2_Val>>23) & (0x3F)) + 1) / 2) + #endif + #else + #define __CORE_CLK __CORE_CLK_PRE + #endif + #else + #if (RCC_Val & (1UL<<11)) /* check BYPASS */ + #if (((RCC_Val>>4) & 0x03) == 0x0) + #if (((RCC_Val>>6) & 0x1F) == 0x0) + #define __CORE_CLK_PRE 1000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x1) + #define __CORE_CLK_PRE 1843200UL + #elif (((RCC_Val>>6) & 0x1F) == 0x2) + #define __CORE_CLK_PRE 2000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x3) + #define __CORE_CLK_PRE 2457600UL + #elif (((RCC_Val>>6) & 0x1F) == 0x4) + #define __CORE_CLK_PRE 3579545UL + #elif (((RCC_Val>>6) & 0x1F) == 0x5) + #define __CORE_CLK_PRE 3686400UL + #elif (((RCC_Val>>6) & 0x1F) == 0x6) + #define __CORE_CLK_PRE 4000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x7) + #define __CORE_CLK_PRE 4096000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x8) + #define __CORE_CLK_PRE 4915200UL + #elif (((RCC_Val>>6) & 0x1F) == 0x9) + #define __CORE_CLK_PRE 5000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0xA) + #define __CORE_CLK_PRE 5120000UL + #elif (((RCC_Val>>6) & 0x1F) == 0xB) + #define __CORE_CLK_PRE 6000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0xC) + #define __CORE_CLK_PRE 6144000UL + #elif (((RCC_Val>>6) & 0x1F) == 0xD) + #define __CORE_CLK_PRE 7372800UL + #elif (((RCC_Val>>6) & 0x1F) == 0xE) + #define __CORE_CLK_PRE 8000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0xF) + #define __CORE_CLK_PRE 8192000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x10) + #define __CORE_CLK_PRE 10000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x11) + #define __CORE_CLK_PRE 12000000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x12) + #define __CORE_CLK_PRE 12288000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x13) + #define __CORE_CLK_PRE 13560000UL + #elif (((RCC_Val>>6) & 0x1F) == 0x14) + #define __CORE_CLK_PRE 14318180UL + #elif (((RCC_Val>>6) & 0x1F) == 0x15) + #define __CORE_CLK_PRE 16000000UL + #else + #define __CORE_CLK_PRE 16384000UL + #endif + #elif (((RCC_Val>>4) & 0x03) == 0x1) + #define __CORE_CLK_PRE XTALI + #elif (((RCC_Val>>4) & 0x03) == 0x2) + #define __CORE_CLK_PRE (XTALI/4) + #else + #define __CORE_CLK_PRE XTAL30K + #endif + #else + #define __CORE_CLK_PRE PLL_CLK + #endif + #if (RCC_Val & (1UL<<22)) /* check USESYSDIV */ + #if (RCC_Val & (1UL<<11)) /* check BYPASS */ + #define __CORE_CLK (__CORE_CLK_PRE / (((RCC_Val>>23) & (0x0F)) + 1)) + #else + #define __CORE_CLK (__CORE_CLK_PRE / (((RCC_Val>>23) & (0x0F)) + 1) / 2) + #endif + #else + #define __CORE_CLK __CORE_CLK_PRE + #endif + #endif + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __CORE_CLK; /*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Get the OSC clock + *----------------------------------------------------------------------------*/ +static uint32_t getOscClk (uint32_t xtal, uint32_t oscSrc) { + uint32_t oscClk = XTALI; + + switch (oscSrc) { /* switch OSCSRC */ + case 0: /* MOSC Main oscillator */ + switch (xtal) { /* switch XTAL */ + case 0x0: + oscClk = 1000000UL; + break; + case 0x1: + oscClk = 1843200UL; + break; + case 0x2: + oscClk = 2000000UL; + break; + case 0x3: + oscClk = 2457600UL; + break; + case 0x4: + oscClk = 3579545UL; + break; + case 0x5: + oscClk = 3686400UL; + break; + case 0x6: + oscClk = 4000000UL; + break; + case 0x7: + oscClk = 4096000UL; + break; + case 0x8: + oscClk = 4915200UL; + break; + case 0x9: + oscClk = 5000000UL; + break; + case 0xA: + oscClk = 5120000UL; + break; + case 0xB: + oscClk = 6000000UL; + break; + case 0xC: + oscClk = 6144000UL; + break; + case 0xD: + oscClk = 7372800UL; + break; + case 0xE: + oscClk = 8000000UL; + break; + case 0xF: + oscClk = 8192000UL; + break; + case 0x10: + oscClk = 10000000UL; + break; + case 0x11: + oscClk = 12000000UL; + break; + case 0x12: + oscClk = 12288000UL; + break; + case 0x13: + oscClk = 13560000UL; + break; + case 0x14: + oscClk = 14318180UL; + break; + case 0x15: + oscClk = 16000000UL; + break; + case 0x16: + oscClk = 16384000UL; + break; + } + break; + case 1: /* IOSC Internal oscillator */ + oscClk = XTALI; + break; + case 2: /* IOSC/4 Internal oscillator/4 */ + oscClk = XTALI/4; + break; + case 3: /* 30kHz internal oscillator */ + oscClk = XTAL30K; + break; + } + + return oscClk; +} + +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t rcc, rcc2; + + /* Determine clock frequency according to clock register values */ + rcc = SYSCTL->RCC; + rcc2 = SYSCTL->RCC2; + + //if (rcc2 & SYSCTL_RCC2_USERCC2) + if (rcc2 & (1UL<<31)) { /* is rcc2 is used ? */ + // if (rcc2 & SYSCTL_RCC2_BYPASS2) + if (rcc2 & (1UL<<11)) { /* check BYPASS */ + SystemCoreClock = getOscClk (((rcc>>6) & 0x0F),((rcc2>>4) & 0x07)); + } else { + SystemCoreClock = PLL_CLK; + } + if (rcc & (1UL<<22)) { /* check USESYSDIV */ + if (rcc2 & (1UL<<11)) { + SystemCoreClock = SystemCoreClock / (((rcc2>>23) & (0x3F)) + 1); + } else { + SystemCoreClock = SystemCoreClock / (((rcc2>>23) & (0x3F)) + 1) / 2; + } + } + } else { + // if (RCC_Val & (1UL<<11)) { /* check BYPASS */ + if (rcc & (1UL<<11)) { /* check BYPASS */ /* Simulation does not work at this point */ + SystemCoreClock = getOscClk (((rcc>>6) & 0x1F),((rcc>>4) & 0x03)); + } else { + SystemCoreClock = PLL_CLK; + } + // if (rcc & SYSCTL_RCC_USE_SYSDIV) + if (rcc & (1UL<<22)) { /* check USESYSDIV */ + // if (rcc2 & SYSCTL_RCC_BYPASS) + if (rcc & (1UL<<11)) { /* check BYPASS */ /* Simulation does not work at this point */ + // if (RCC_Val & (1UL<<11)) { /* check BYPASS */ + SystemCoreClock = SystemCoreClock / (((rcc>>23) & (0x0F)) + 1); + } else { + SystemCoreClock = SystemCoreClock / (((rcc>>23) & (0x0F)) + 1) / 2; + } + } + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ +#if(CLOCK_SETUP) + volatile uint32_t i; +#endif + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ + #endif + +#if(CLOCK_SETUP) + SYSCTL->RCC2 = 0x07802810; /* set default value */ + SYSCTL->RCC = 0x078E3AD1; /* set default value */ + + SYSCTL->RCC = (RCC_Val | (1UL<<11) | (1UL<<13)) & ~(1UL<<22); /* set value with BYPASS, PWRDN set, USESYSDIV reset */ + SYSCTL->RCC2 = (RCC2_Val | (1UL<<11) | (1UL<<13)); /* set value with BYPASS, PWRDN set */ + for (i = 0; i < 1000; i++); /* wait a while */ + + SYSCTL->RCC = (RCC_Val | (1UL<<11)) & ~(1UL<<22); /* set value with BYPASS, USESYSDIV reset */ + SYSCTL->RCC2 = (RCC2_Val | (1UL<<11)); /* set value with BYPASS */ + for (i = 0; i < 1000; i++); /* wait a while */ + + SYSCTL->RCC = (RCC_Val | (1<<11)); /* set value with BYPASS */ + + if ( (((RCC_Val & (1UL<<13)) == 0) && ((RCC2_Val & (1UL<<31)) == 0)) || + (((RCC2_Val & (1UL<<13)) == 0) && ((RCC2_Val & (1UL<<31)) != 0)) ) { + while ((SYSCTL->RIS & (1UL<<6)) != (1UL<<6)); /* wait until PLL is locked */ + } + + SYSCTL->RCC = (RCC_Val); /* set value */ + SYSCTL->RCC2 = (RCC2_Val); /* set value */ + for (i = 0; i < 10000; i++); /* wait a while */ + +#endif +} diff --git a/3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.h b/3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.h new file mode 100644 index 0000000..3ee4ff2 --- /dev/null +++ b/3rd_party/ek-tm4c123gxl/system_TM4C123GH6PM.h @@ -0,0 +1,63 @@ +/**************************************************************************//** + * @file system_TM4C123GH6PM.h + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for + * TI Tiva TM4C123 Class Devices + * @version V3.1 + * @date 15. May 2013 + * + * @note + * Copyright (C) 2010-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + ******************************************************************************/ + + +#ifndef SYSTEM_TM4C123_H +#define SYSTEM_TM4C123_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_TM4C123_H */ diff --git a/3rd_party/nucleo-h743zi/arm/startup_stm32h743xx.s b/3rd_party/nucleo-h743zi/arm/startup_stm32h743xx.s index 66d0a6a..fdb0518 100644 --- a/3rd_party/nucleo-h743zi/arm/startup_stm32h743xx.s +++ b/3rd_party/nucleo-h743zi/arm/startup_stm32h743xx.s @@ -6,6 +6,7 @@ ; * ; * @description ; * Created from the CMSIS template for the specified device +; * Added assert_failed() and DBC_fault_handler() ; * Quantum Leaps, www.state-machine.com ; * ; * @note @@ -760,20 +761,20 @@ __user_initial_stackheap PROC ; ; The function assert_failed defines the error/assertion handling policy ; for the application. After making sure that the stack is OK, this function -; calls Q_onAssert, which should NOT return (typically reset the CPU). +; calls DBC_fault_handler, which should NOT return (typically reset the CPU). ; -; NOTE: the function Q_onAssert should NOT return. +; NOTE: the function DBC_fault_handler should NOT return. ; -; The C proptotype of the assert_failed() and Q_onAssert() functions are: +; The C proptotype of assert_failed() and DBC_fault_handler() are: ; void assert_failed(char const *file, int line); -; void Q_onAssert (char const *file, int line); +; void DBC_fault_handler (char const *file, int line); ;****************************************************************************** EXPORT assert_failed - IMPORT Q_onAssert + IMPORT DBC_fault_handler assert_failed PROC LDR sp,=__initial_sp ; re-set the SP in case of stack overflow - BL Q_onAssert ; call the application-specific handler + BL DBC_fault_handler ; call the application-specific handler B . ; should not be reached, but just in case... diff --git a/3rd_party/nucleo-h743zi/gnu/startup_stm32h743xx.c b/3rd_party/nucleo-h743zi/gnu/startup_stm32h743xx.c index 58aea4c..d5b5a56 100644 --- a/3rd_party/nucleo-h743zi/gnu/startup_stm32h743xx.c +++ b/3rd_party/nucleo-h743zi/gnu/startup_stm32h743xx.c @@ -62,7 +62,7 @@ void Default_Handler(void); /* Default empty handler */ void Reset_Handler(void); /* Reset Handler */ void SystemInit(void); /* CMSIS system initialization */ __attribute__ ((noreturn)) -void Q_onAssert(char const *module, int loc); /* QP assertion handler */ +void DBC_fault_handler(char const *module, int loc); /* QP assertion handler */ /*---------------------------------------------------------------------------- * weak aliases for each Exception handler to the Default_Handler. @@ -522,9 +522,9 @@ void Default_Handler(void) { /***************************************************************************** * The function assert_failed defines the error/assertion handling policy * for the application. After making sure that the stack is OK, this function -* calls Q_onAssert, which should NOT return (typically reset the CPU). +* calls DBC_fault_handler, which should NOT return (typically reset the CPU). * -* NOTE: the function Q_onAssert should NOT return. +* NOTE: the function DBC_fault_handler should NOT return. *****************************************************************************/ __attribute__ ((naked, noreturn)) void assert_failed(char const *module, int loc) { @@ -533,7 +533,7 @@ void assert_failed(char const *module, int loc) { " MOV sp,%0\n\t" : : "r" (&__stack_end__)); - Q_onAssert(module, loc); /* call the application-specific QP handler */ + DBC_fault_handler(module, loc); /* call the application-specific handler */ for (;;) { /* should not be reached, but just in case loop forever... */ } diff --git a/3rd_party/nucleo-h743zi/iar/startup_stm32h743xx.s b/3rd_party/nucleo-h743zi/iar/startup_stm32h743xx.s index 321644d..ed0ee4c 100644 --- a/3rd_party/nucleo-h743zi/iar/startup_stm32h743xx.s +++ b/3rd_party/nucleo-h743zi/iar/startup_stm32h743xx.s @@ -683,20 +683,20 @@ str_Undefined ;***************************************************************************** ; The function assert_failed defines the error/assertion handling policy ; for the application. After making sure that the stack is OK, this function -; calls Q_onAssert, which should NOT return (typically reset the CPU). +; calls DBC_fault_handler, which should NOT return (typically reset the CPU). ; -; NOTE: the function Q_onAssert should NOT return. +; NOTE: the function DBC_fault_handler should NOT return. ; -; The C proptotype of the assert_failed() and Q_onAssert() functions are: +; The C proptotypes of assert_failed() and DBC_fault_handler() are: ; void assert_failed(char const *file, int line); -; void Q_onAssert (char const *file, int line); +; void DBC_fault_handler(char const *file, int line); ;***************************************************************************** PUBLIC assert_failed - EXTERN Q_onAssert + EXTERN DBC_fault_handler assert_failed LDR r2,=sfe(CSTACK) ; load the original top of stack MOV sp,r2 ; re-set the SP in case of stack overflow - BL Q_onAssert ; call the application-specific handler + BL DBC_fault_handler ; call the application-specific handler B . ; should not be reached, but just in case... diff --git a/3rd_party/nucleo-l053r8/arm/startup_stm32l053xx.s b/3rd_party/nucleo-l053r8/arm/startup_stm32l053xx.s index b914f78..72122e5 100644 --- a/3rd_party/nucleo-l053r8/arm/startup_stm32l053xx.s +++ b/3rd_party/nucleo-l053r8/arm/startup_stm32l053xx.s @@ -5,7 +5,7 @@ ; with this file ; - replaced endless loops in exception handlers (denial of service) with ; branches to assert_failed -; - provided definitions of assert_failed and Q_onAssert +; - provided definitions of assert_failed and DBC_fault_handler ; ; ; Quantum Leaps, LLC; www.state-machine.com @@ -321,20 +321,20 @@ __user_initial_stackheap ;****************************************************************************** ; The function assert_failed defines the error/assertion handling policy ; for the application. After making sure that the stack is OK, this function -; calls Q_onAssert, which should NOT return (typically reset the CPU). +; calls DBC_fault_handler, which should NOT return (typically reset the CPU). ; -; NOTE: the function Q_onAssert should NOT return. +; NOTE: the function DBC_fault_handler should NOT return. ; -; The C proptotype of the assert_failed() and Q_onAssert() functions are: +; The C proptotypes of assert_failed() and DBC_fault_handler() are: ; void assert_failed(char const *file, int line); -; void Q_onAssert (char const *file, int line); +; void DBC_fault_handler (char const *file, int line); ;****************************************************************************** EXPORT assert_failed - IMPORT Q_onAssert + IMPORT DBC_fault_handler assert_failed PROC LDR r2,=__initial_sp ; load the original top of stack MOV sp,r2 ; re-set the SP in case of stack overflow - BL Q_onAssert ; call the application-specific handler + BL DBC_fault_handler ; call the application-specific handler B . ; should never be reached diff --git a/3rd_party/nucleo-l053r8/gnu/startup_stm32l053xx.c b/3rd_party/nucleo-l053r8/gnu/startup_stm32l053xx.c index dcaae2f..600b60f 100644 --- a/3rd_party/nucleo-l053r8/gnu/startup_stm32l053xx.c +++ b/3rd_party/nucleo-l053r8/gnu/startup_stm32l053xx.c @@ -62,7 +62,7 @@ void Default_Handler(void); /* Default empty handler */ void Reset_Handler(void); /* Reset Handler */ void SystemInit(void); /* CMSIS system initialization */ __attribute__ ((noreturn)) -void Q_onAssert(char const *module, int loc); /* QP assertion handler */ +void DBC_fault_handler(char const * module, int label); /*---------------------------------------------------------------------------- * weak aliases for each Exception handler to the Default_Handler. @@ -283,8 +283,8 @@ __asm volatile ( /*--------------------------------------------------------------------------*/ /* The function assert_failed() provides a low-level handler for assertion -* failures. It ultimately transfers control to Q_onAssert(), which defines -* the error/assertion handling policy for the application. +* failures. It ultimately transfers control to DBC_fault_handler(), which +* defines the error/assertion handling policy for the application. * * assert_failed() re-sets the stack pointer (MSP) to the original setting. * This is necessary to avoid cascading exceptions in case the stack was @@ -294,7 +294,7 @@ __attribute__ ((naked, noreturn)) void assert_failed(char const *module, int loc) { /* re-set the SP in case of stack overflow */ __asm volatile (" MOV sp,%0" : : "r" (&__stack_end__)); - Q_onAssert(module, loc); /* call the app-specific handler */ + DBC_fault_handler(module, loc); /* call the app-specific handler */ for (;;) { } } diff --git a/3rd_party/nucleo-l053r8/iar/startup_stm32l053xx.s b/3rd_party/nucleo-l053r8/iar/startup_stm32l053xx.s index 1074b9a..286b664 100644 --- a/3rd_party/nucleo-l053r8/iar/startup_stm32l053xx.s +++ b/3rd_party/nucleo-l053r8/iar/startup_stm32l053xx.s @@ -314,20 +314,20 @@ str_Undefined ;***************************************************************************** ; The function assert_failed defines the error/assertion handling policy ; for the application. After making sure that the stack is OK, this function -; calls Q_onAssert, which should NOT return (typically reset the CPU). +; calls DBC_fault_handler, which should NOT return (typically reset the CPU). ; -; NOTE: the function Q_onAssert should NOT return. +; NOTE: the function DBC_fault_handler should NOT return. ; -; The C proptotype of the assert_failed() and Q_onAssert() functions are: +; The C proptotypes of assert_failed() and DBC_fault_handler() are: ; void assert_failed(char const *file, int line); -; void Q_onAssert (char const *file, int line); +; void DBC_fault_handler (char const *file, int line); ;***************************************************************************** PUBLIC assert_failed - EXTERN Q_onAssert + EXTERN DBC_fault_handler assert_failed LDR r2,=sfe(CSTACK) ; load the original top of stack MOV sp,r2 ; re-set the SP in case of stack overflow - BL Q_onAssert ; call the application-specific handler + BL DBC_fault_handler ; call the application-specific handler B . ; should not be reached, but just in case... diff --git a/README.md b/README.md index 683685e..1ed6ecf 100644 --- a/README.md +++ b/README.md @@ -148,10 +148,14 @@ Super-Simple-Tasker/ For **every** of these cases the examples are built for the following embedded boards: -

+

+ + +

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sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +============================================================================*/ +#ifndef DBC_ASSERT_H_ +#define DBC_ASSERT_H_ + +/*! @file +* @brief Memory-efficient Design by Contract (DBC) for embedded C and C++. +* +* @note +* The runtime checking of the DBC assertions can be disabled by defining +* the macro #DBC_DISABLE. However, it is generally **not** advisable to +* disable assertions, *especially* in the production code. Instead, the +* assertion fault handler DBC_fault_handler() should be very carefully +* designed and tested under all fault conditions. +*/ + +/* Active DbC macros -------------------------------------------------------*/ +#ifndef DBC_DISABLE + +/*! Define the user-specified module name for assertions in this file. +* +* @details +* Macro to be placed at the top of each C/C++ module to define the +* single instance of the module name string to be used in reporting +* assertions in this module. This macro takes the user-supplied parameter +* `name_`. +* +* @param[in] name_ string constant representing the module name +* +* @note +* This macro should **not** be terminated by a semicolon. +*/ +#define DBC_MODULE_NAME(name_) \ + static char const DBC_module_name_[] = name_; + +/*! General purpose assertion with user-specified ID number. +* +* @details +* Makes sure the `expr_` parameter is TRUE. Calls the DBC_fault_handler() +* callback if the `expr_` evaluates to FALSE. This assertion takes the +* user-supplied parameter `label_` to identify the location of this +* assertion within the module. This avoids the volatility of using line +* numbers, which change whenever a line of code is added or removed +* upstream from the assertion. +* +* @param[in] label_ numeric label of the assertion (unique within the module) +* @param[in] expr_ Boolean expression to check +* +* @note +* The `expr_` expression is **not** evaluated if assertions are +* disabled with the ::DBC_DISABLE switch. +*/ +#define DBC_ASSERT(label_, expr_) ((expr_) \ + ? ((void)0) : DBC_fault_handler(&DBC_module_name_[0], (label_))) + +/*! General purpose assertion with user-specified ID number that +* evaluates the `expr_` expression even when assertions are disabled. +* +* @details +* Like the DBC_ASSERT() macro, except it **always** evaluates the +* `expr_` expression even when DBC assertions are disabled with the +* #DBC_DISABLE macro. +* +* @param[in] label_ numeric label of the assertion (unique within the module) +* @param[in] expr_ Boolean expression to check +*/ +#define DBC_ALLEGE(label_, expr_) DBC_ASSERT(label_, expr_) + +/*! Assertion for a wrong path through the code +* +* @details +* Calls the DBC_fault_handler() callback if ever executed. This assertion +* takes the user-supplied parameter `id_` to identify the location of +* this assertion within the file. This avoids the volatility of using +* line numbers, which change whenever a line of code is added or removed +* upstream from the assertion. +* +* @param[in] label_ numeric label of the assertion (unique within the module) +*/ +#define DBC_ERROR(label_) DBC_fault_handler(&DBC_module_name_[0], (label_)) + +/*! Assertion for checking preconditions. +* +* @details +* Equivalent to DBC_ASSERT(), except the name provides a better +* documentation of the intention of this assertion. +* +* @param[in] label_ numeric label of the assertion (unique within the module) +* @param[in] expr_ Boolean expression to check +* +* @note +* The `expr_` expression is **not** evaluated if assertions are +* disabled with the ::DBC_DISABLE switch. +*/ +#define DBC_REQUIRE(label_, expr_) DBC_ASSERT((label_), (expr_)) + +/*! Assertion for checking postconditions. +* +* @details +* Equivalent to DBC_ASSERT(), except the name provides a better +* documentation of the intention of this assertion. +* +* @param[in] label_ numeric label of the assertion (unique within the module) +* @param[in] expr_ Boolean expression to check +* +* @note +* The `expr_` expression is **not** evaluated if assertions are +* disabled with the ::DBC_DISABLE switch. +*/ +#define DBC_ENSURE(label_, expr_) DBC_ASSERT((label_), (expr_)) + +/*! Assertion for checking invariants. +* +* @details +* Equivalent to DBC_ASSERT(), except the name provides a better +* documentation of the intention of this assertion. +* +* @param[in] label_ numeric label of the assertion (unique within the module) +* @param[in] expr_ Boolean expression to check +* +* @note +* The `expr_` expression is **not** evaluated if assertions are +* disabled with the ::DBC_DISABLE switch. +*/ +#define DBC_INVARIANT(label_, expr_) DBC_ASSERT((label_), (expr_)) + +#ifndef DBC_NORETURN +#define DBC_NORETURN +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! DBC assertion fault handler. +* +* @details +* This is an application-specific callback function needs to be defined in +* the application to perform the clean system shutdown and perhaps a reset. +* The DBC_fault_handler() function is the last line of defense after the +* system failure and its implementation should be very **carefully** +* designed and **tested** under various fault conditions, including but +* not limited to: stack overflow, stack corruption, or calling +* DBC_fault_handler() from ISRs. + +* @param[in] module name of the file/module in which the assertion failed +* (constant, zero-terminated C string) +* @param[in] label unique label of the assertion within the module. +* This could be a line number or a user-defined label. +* +* @returns +* This callback function should **not return** (see #NORETURN), +* as continuation after an assertion failure does not make sense. +* +* @note +* It is typically a **bad idea** to implement DBC_fault_handler() as an +* endless loop that ties up the CPU. During debugging, DBC_fault_handler() +* is an ideal place to put a breakpoint. +*/ +DBC_NORETURN void DBC_fault_handler(char const * module, int label); + +#ifdef __cplusplus +} +#endif + +/* Inactive DbC macros -----------------------------------------------------*/ +#else + +#define DBC_MODULE_NAME(dummy_) +#define DBC_ASSERT(label_, expr_) ((void)0) +#define DBC_ERROR(label_) ((void)0) +#define DBC_REQUIRE(label_, expr_) ((void)0) +#define DBC_ENSURE(label_, expr_) ((void)0) +#define DBC_INVARIANT(label_, expr_) ((void)0) +#define DBC_ALLEGE(label_, expr_) ((void)(expr_)) + +#endif /* Inactive DBC macros */ + +#endif /* DBC_ASSERT_ */ diff --git a/include/qassert.h b/include/qassert.h deleted file mode 100644 index bab12b7..0000000 --- a/include/qassert.h +++ /dev/null @@ -1,365 +0,0 @@ -/*=========================================================================== -* (HA)rdware Real-Time Operating System (HARTOS) for ARM Cortex-M -* -* Copyright (C) 2006-2023 Quantum Leaps, -* -* SPDX-License-Identifier: MIT -* -* See the accompanying LICENSE file or visit . -===========================================================================*/ -#ifndef QP_INC_QASSERT_H_ -#define QP_INC_QASSERT_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -/*$declare${DbC} vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv*/ - -/*${DbC::Q_NORETURN} .......................................................*/ -#ifndef Q_NORETURN -/*! No-return function specifier for the Q_onAssert() callback function. -* -* The `Q_NORETURN` macro is supposed to be defined in the QP/C port -* (file `qep_port.h`). If such definition is NOT porvided, the default -* definition assumes only `void` type returned from Q_onAssert(). -* -* @tr{PQA01_4} -*/ -#define Q_NORETURN void -#endif /* ndef Q_NORETURN */ - -/*${DbC::Q_DEFINE_THIS_FILE} ...............................................*/ -/*! Define the file name (with `__FILE__`) for assertions in this file -* -* @details -* Macro to be placed at the top of each C/C++ module to define the -* single instance of the file name string to be used in reporting -* assertions in this module. -* -* @note -* The file name string literal is defined by means of the standard -* preprocessor macro `__FILE__`. However, please note that, depending -* on the compiler, the `__FILE__` macro might contain the whole path name -* to the file, which might be inconvenient to log assertions. -* -* @attention -* This macro should **not** be terminated by a semicolon. -* -* @sa Q_DEFINE_THIS_MODULE() -*/ -#define Q_DEFINE_THIS_FILE Q_DEFINE_THIS_MODULE(__FILE__) - -/*${DbC::Q_DEFINE_THIS_MODULE} .............................................*/ -#ifndef Q_NASSERT -/*! Define the user-specified module name for assertions in this file. -* -* @details -* Macro to be placed at the top of each C/C++ module to define the -* single instance of the module name string to be used in reporting -* assertions in this module. This macro takes the user-supplied parameter -* `name_` instead of `__FILE__` to precisely control the name of the -* module. -* -* @param[in] name_ string constant representing the module name -* -* @note -* This macro should **not** be terminated by a semicolon. -*/ -#define Q_DEFINE_THIS_MODULE(name_) \ - static char const Q_this_module_[] = name_; -#endif /* ndef Q_NASSERT */ - -/*${DbC::Q_DEFINE_THIS_MODULE} .............................................*/ -#ifdef Q_NASSERT -/*! inactive version of Q_DEFINE_THIS_MODULE() */ -#define Q_DEFINE_THIS_MODULE(name_) -#endif /* def Q_NASSERT */ - -/*${DbC::Q_ASSERT_ID} ......................................................*/ -#ifndef Q_NASSERT -/*! General purpose assertion with user-specified ID number. -* -* @details -* Makes sure the `test_` parameter is TRUE. Calls the Q_onAssert() -* callback if the `test_` evaluates to FALSE. This assertion takes the -* user-supplied parameter `id_` to identify the location of this -* assertion within the file. This avoids the volatility of using line -* numbers, which change whenever a line of code is added or removed -* upstream from the assertion. -* -* @param[in] id_ ID number (unique within the module) of the assertion -* @param[in] expr_ Boolean expression to check -* -* @note -* The `test_` expression is **not** evaluated if assertions are -* disabled with the ::Q_NASSERT switch. -*/ -#define Q_ASSERT_ID(id_, expr_) ((expr_) \ - ? ((void)0) : Q_onAssert(&Q_this_module_[0], (id_))) -#endif /* ndef Q_NASSERT */ - -/*${DbC::Q_ASSERT_ID} ......................................................*/ -#ifdef Q_NASSERT -/*! inactive version of Q_ASSERT_ID() */ -#define Q_ASSERT_ID(id_, expr_) ((void)0) -#endif /* def Q_NASSERT */ - -/*${DbC::Q_ERROR_ID} .......................................................*/ -#ifndef Q_NASSERT -/*! Assertion with user-specified ID for a wrong path through the code -* -* @details -* Calls the Q_onAssert() callback if ever executed. This assertion -* takes the user-supplied parameter `id_` to identify the location of -* this assertion within the file. This avoids the volatility of using -* line numbers, which change whenever a line of code is added or removed -* upstream from the assertion. -* -* @param[in] id_ ID number (unique within the module) of the assertion -* -* @note -* Does noting if assertions are disabled with the ::Q_NASSERT switch. -*/ -#define Q_ERROR_ID(id_) Q_onAssert(&Q_this_module_[0], (id_)) -#endif /* ndef Q_NASSERT */ - -/*${DbC::Q_ERROR_ID} .......................................................*/ -#ifdef Q_NASSERT -/*! inactive version of Q_ERROR_ID() */ -#define Q_ERROR_ID(id_) ((void)0) -#endif /* def Q_NASSERT */ - -/*${DbC::Q_ALLEGE_ID} ......................................................*/ -#ifndef Q_NASSERT -/*! General purpose assertion with user-specified ID number that -* **always** evaluates the `expr_` expression. -* -* @details -* Like the Q_ASSERT_ID() macro, except it **always** evaluates the -* `expr_` expression even when assertions are disabled with the -* ::Q_NASSERT macro. However, when the ::Q_NASSERT macro is defined, the -* Q_onAssert() callback is **not** called, even if `expr_` evaluates -* to FALSE. -* -* @param[in] id_ ID number (unique within the module) of the assertion -* @param[in] expr_ Boolean expression to check -*/ -#define Q_ALLEGE_ID(id_, expr_) Q_ASSERT_ID((id_), (expr_)) -#endif /* ndef Q_NASSERT */ - -/*${DbC::Q_ALLEGE_ID} ......................................................*/ -#ifdef Q_NASSERT -/*! inactive version of Q_ALLEGE_ID() -* -* @attention -* The expression `expr_` **is** executed. -*/ -#define Q_ALLEGE_ID(id_, expr_) ((void)(expr_)) -#endif /* def Q_NASSERT */ - -/*${DbC::Q_REQUIRE_ID} .....................................................*/ -/*! Assertion for checking preconditions. -* -* @details -* This macro is equivalent to Q_ASSERT_ID(), except the name provides a better -* documentation of the intention of this assertion. -* -* @param[in] id_ ID number (unique within the module) of the assertion -* @param[in] expr_ Boolean expression -*/ -#define Q_REQUIRE_ID(id_, expr_) Q_ASSERT_ID((id_), (expr_)) - -/*${DbC::Q_REQUIRE} ........................................................*/ -/*! Assertion for checking preconditions (based on __LINE__). -* -* @details -* Equivalent to Q_ASSERT(), except the name provides a better documentation -* of the intention of this assertion. -* -* @param[in] expr_ Boolean expression -*/ -#define Q_REQUIRE(expr_) Q_REQUIRE_ID(__LINE__, (expr_)) - -/*${DbC::Q_ENSURE_ID} ......................................................*/ -/*! Assertion for checking postconditions. -* -* @details -* This macro is equivalent to Q_ASSERT_ID(), except the name provides a better -* documentation of the intention of this assertion. -* -* @param[in] id_ ID number (unique within the module) of the assertion -* @param[in] expr_ Boolean expression -*/ -#define Q_ENSURE_ID(id_, expr_) Q_ASSERT_ID((id_), (expr_)) - -/*${DbC::Q_ENSURE} .........................................................*/ -/*! Assertion for checking postconditions. -* -* @details -* Equivalent to Q_ASSERT(), except the name provides a better documentation -* of the intention of this assertion. -* -* @param[in] expr_ Boolean expression -*/ -#define Q_ENSURE(expr_) Q_ENSURE_ID(__LINE__, (expr_)) - -/*${DbC::Q_INVARIANT_ID} ...................................................*/ -/*! Assertion for checking invariants. -* -* @details -* Equivalent to Q_ASSERT(), except the name provides a better documentation -* of the intention of this assertion. -* -* @param[in] id_ ID number (unique within the module) of the assertion -* @param[in] expr_ Boolean expression -*/ -#define Q_INVARIANT_ID(id_, expr_) Q_ASSERT_ID((id_), (expr_)) - -/*${DbC::Q_INVARIANT} ......................................................*/ -/*! Assertion for checking invariants. -* -* @details -* Equivalent to Q_ASSERT(), except the name provides a better documentation -* of the intention of this assertion. -* -* @param[in] expr_ Boolean expression -*/ -#define Q_INVARIANT(expr_) Q_INVARIANT_ID(__LINE__, (expr_)) - -/*${DbC::Q_ASSERT} .........................................................*/ -/*! Assertion for a wrong path through the code (based on __LINE__) -* -* @details -* Calls the Q_onAssert() callback if ever executed. -* -* @note -* This macro identifies the problem location with the line number, -* which might change as the code is modified. -* -* @sa Q_ASSERT_ID() -*/ -#define Q_ASSERT(expr_) Q_ASSERT_ID(__LINE__, (expr_)) - -/*${DbC::Q_ERROR} ..........................................................*/ -/*! Assertion for a wrong path through the code -* -* @details -* Calls the Q_onAssert() callback if ever executed. -* -* @note -* This macro identifies the problem location with the line number, -* which might change as the code is modified. -* -* @sa Q_ERROR_ID() -*/ -#define Q_ERROR() Q_ERROR_ID(__LINE__) - -/*${DbC::Q_ALLEGE} .........................................................*/ -/*! General purpose assertion with user-specified ID number that -* **always** evaluates the `expr_` expression. -* -* @details -* Like the Q_ASSERT_ID() macro, except it **always** evaluates the -* `expr_` expression even when assertions are disabled with the -* ::Q_NASSERT macro. However, when the ::Q_NASSERT macro is defined, the -* Q_onAssert() callback is **not** called, even if `expr_` evaluates -* to FALSE. -* -* @param[in] expr_ Boolean expression to check -* -* @sa Q_ALLEGE_ID() -*/ -#define Q_ALLEGE(expr_) Q_ALLEGE_ID(__LINE__, (expr_)) - -/*${DbC::Q_ASSERT_STATIC} ..................................................*/ -/*! Static (compile-time) assertion. -* -* @details -* This type of assertion deliberately causes a compile-time error when -* the `expr_` Boolean expression evaluates to FALSE. The macro exploits -* the fact that in C/C++ a dimension of an array cannot be negative. -* The compile-time assertion has no runtime side effects. -* -* @param[in] expr_ Compile-time Boolean expression -* -* @note -* The static assertion macro is provided for backwards compatibility with -* older C standards. Newer C11 supports `_Static_assert()`, which should -* be used instead of Q_ASSERT_STATIC(). -*/ -#define Q_ASSERT_STATIC(expr_) extern char Q_static_assert_[(expr_) ? 1 : -1] - -/*${DbC::Q_ASSERT_COMPILE} .................................................*/ -/*! Static (compile-time) assertion. -* -* @deprecated -* Use Q_ASSERT_STATIC() or better yet `_Static_assert()` instead. -*/ -#define Q_ASSERT_COMPILE(expr_) Q_ASSERT_STATIC(expr_) - -/*${DbC::int_t} ............................................................*/ -#ifndef QP_VERSION -/*! typedef for assertions-ids and line numbers in assertions. -* -* @details -* This typedef specifies integer type for exclusive use in assertions. -* Use of this type, rather than plain 'int', is in compliance -* with the MISRA-C 2012 Dir 4.6 (adv). -*/ -typedef int int_t; -#endif /* ndef QP_VERSION */ - -/*${DbC::Q_onAssert} .......................................................*/ -/*! Callback function invoked in case of an assertion failure. -* -* @details -* This is an application-specific callback function needs to be defined in -* the application to perform the clean system shutdown and perhaps a reset. -* The Q_onAssert() function is the last line of defense after the -* system failure and its implementation shouild be very **carefully** -* designed and **tested** under various fault conditions, including but -* not limited to: stack overflow, stack corruption, or calling Q_onAssert() -* from an interrupt. - -* @param[in] module name of the file/module in which the assertion failed -* (constant, zero-terminated C string) -* @param[in] location location of the assertion within the module. This could -* be a line number or a user-specified ID-number. -* -* @returns -* This callback function should **not return** (see ::Q_NORETURN), -* as continuation after an assertion failure does not make sense. -* -* @note -* It is typically a **bad idea** to implement Q_onAssert() as an endless -* loop that ties up the CPU. During debuggin, Q_onAssert() is an ideal -* place to put a breakpoint. -* -* @tr{PQA01_4} -* -* Called by the following: Q_ASSERT_ID(), Q_ERROR_ID(), Q_REQUIRE_ID(), -* Q_ENSURE_ID(), Q_INVARIANT_ID() and Q_ALLEGE_ID() as well as: -* Q_ASSERT(), Q_ERROR(), Q_REQUIRE(), Q_ENSURE(), Q_INVARIANT(), -* and Q_ALLEGE(). -*/ -Q_NORETURN Q_onAssert( - char const * module, - int_t location); - -/*${DbC::Q_DIM} ............................................................*/ -#ifndef QP_VERSION -/*! Helper macro to calculate static dimension of a 1-dim `array_` -* -* @param array_ 1-dimensional array -* @returns the length of the array (number of elements it can hold) -*/ -#define Q_DIM(array_) (sizeof(array_) / sizeof((array_)[0U])) -#endif /* ndef QP_VERSION */ -/*$enddecl${DbC} ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ - -#ifdef __cplusplus - } -#endif - -#endif /* QP_INC_QASSERT_H_ */ diff --git a/include/sst.h b/include/sst.h index 5c8e4be..71042ca 100644 --- a/include/sst.h +++ b/include/sst.h @@ -125,4 +125,10 @@ static inline uint_fast8_t SST_LOG2(uint32_t x) { } #endif +/* general convenience utilities -------------------------------------------*/ +#ifndef ARRAY_NELEM +/*! convenience macro to provide the number of elements in the array a_ */ +#define ARRAY_NELEM(a_) (sizeof(a_) / sizeof((a_)[0])) +#endif /* ARRAY_NELEM */ + #endif /* SST_H_ */ diff --git a/include/sst.hpp b/include/sst.hpp index 54b0494..e82c949 100644 --- a/include/sst.hpp +++ b/include/sst.hpp @@ -124,4 +124,10 @@ inline uint_fast8_t SST_LOG2(std::uint32_t x) { } // namespace SST +// general convenience utilities --------------------------------------------- +#ifndef ARRAY_NELEM +//! convenience macro to provide the number of elements in the array a_ +#define ARRAY_NELEM(a_) (sizeof(a_) / sizeof((a_)[0])) +#endif /* ARRAY_NELEM */ + #endif // SST_HPP_ diff --git a/sst0_c/examples/blinky_button/armclang/ek-tm4c123gxl.uvoptx b/sst0_c/examples/blinky_button/armclang/ek-tm4c123gxl.uvoptx new file mode 100644 index 0000000..ea490fe --- /dev/null +++ b/sst0_c/examples/blinky_button/armclang/ek-tm4c123gxl.uvoptx @@ -0,0 +1,413 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ek-tm4c123gxl + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build_ek-tm4c123gxl\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 4 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 19 + + + + + + + + + + + BIN\lmidk-agdi.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + UL2CM3 + UL2CM3(-O207 -S0 -C0 -FO7 -FN1 -FC1000 -FD20000000 -FF0TM4C123_256 -FL040000 -FS00 -FP0($$Device:TM4C123GH6PM$Flash\TM4C123_256.FLM) + + + 0 + DLGTARM + (1010=1120,219,1570,776,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=1881,651,2358,966,0) + + + 0 + ARMDBGFLAGS + + + + 0 + lmidk-agdi + -U0E10259B -O4686 -S5 -FO29 + + + + + 0 + 0 + 247 + 1 +
2900
+ 0 + 0 + 0 + 0 + 0 + 1 + ..\bsp_ek-tm4c123gxl.c + + \\build_ek_tm4c123gxl\../bsp_ek-tm4c123gxl.c\247 + + + + + 1 + 2 + 0x20000200 + 0 + + + + + 2 + 0 + 0x400 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Applicatioin + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\main.c + main.c + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + ..\blinky_button.h + blinky_button.h + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\blinky1.c + blinky1.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\blinky3.c + blinky3.c + 0 + 0 + + + 1 + 5 + 5 + 0 + 0 + 0 + ..\bsp.h + bsp.h + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 0 + ..\bsp_ek-tm4c123gxl.c + bsp_ek-tm4c123gxl.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + ..\button2a.c + button2a.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + ..\button2b.c + button2b.c + 0 + 0 + + + + + ek-tm4c123gxl + 1 + 0 + 0 + 0 + + 2 + 9 + 2 + 0 + 0 + 0 + ..\..\..\..\3rd_party\ek-tm4c123gxl\arm\startup_TM4C123GH6PM.s + startup_TM4C123GH6PM.s + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\3rd_party\ek-tm4c123gxl\system_TM4C123GH6PM.c + system_TM4C123GH6PM.c + 0 + 0 + + + 2 + 11 + 5 + 0 + 0 + 0 + ..\..\..\..\3rd_party\ek-tm4c123gxl\TM4C123GH6PM.h + TM4C123GH6PM.h + 0 + 0 + + + + + sst + 1 + 0 + 0 + 0 + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\src\sst0.c + sst0.c + 0 + 0 + + + + + sst_port + 1 + 0 + 0 + 0 + + 4 + 13 + 5 + 0 + 0 + 0 + ..\..\..\ports\arm-cm\sst_port.h + sst_port.h + 0 + 0 + + + + diff --git a/sst0_c/examples/blinky_button/armclang/ek-tm4c123gxl.uvprojx b/sst0_c/examples/blinky_button/armclang/ek-tm4c123gxl.uvprojx new file mode 100644 index 0000000..6196298 --- /dev/null +++ b/sst0_c/examples/blinky_button/armclang/ek-tm4c123gxl.uvprojx @@ -0,0 +1,487 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ek-tm4c123gxl + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + TM4C123GH6PM + Texas Instruments + Keil.TM4C_DFP.1.1.0 + http://www.keil.com/pack/ + IROM(0x00000000,0x040000) IRAM(0x20000000,0x008000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C123_256 -FS00 -FL040000 -FP0($$Device:TM4C123GH6PM$Flash\TM4C123_256.FLM)) + 0 + $$Device:TM4C123GH6PM$Device\Include\TM4C123\TM4C123.h + + + + + + + + + + $$Device:TM4C123GH6PM$SVD\TM4C123\TM4C123GH6PM.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build_ek-tm4c123gxl\ + blinky_button + 1 + 0 + 0 + 1 + 1 + .\build_ek-tm4c123gxl\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin --output .\build_ek-tm4c123gxl\blinky_button.bin .\build_ek-tm4c123gxl\blinky_button.axf + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + + + __FPU_PRESENT + + ..;..\..\..\..\include;..\..\..\ports\arm-cm;..\..\..\..\3rd_party\ek-tm4c123gxl + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 4 + + + Stack_Size=2048 Heap_Size=16 + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + --entry Reset_Handler + + + + + + + + Applicatioin + + + main.c + 1 + ..\main.c + + + blinky_button.h + 5 + ..\blinky_button.h + + + blinky1.c + 1 + ..\blinky1.c + + + blinky3.c + 1 + ..\blinky3.c + + + bsp.h + 5 + ..\bsp.h + + + bsp_ek-tm4c123gxl.c + 1 + ..\bsp_ek-tm4c123gxl.c + + + button2a.c + 1 + ..\button2a.c + + + button2b.c + 1 + ..\button2b.c + + + + + ek-tm4c123gxl + + + startup_TM4C123GH6PM.s + 2 + ..\..\..\..\3rd_party\ek-tm4c123gxl\arm\startup_TM4C123GH6PM.s + + + system_TM4C123GH6PM.c + 1 + ..\..\..\..\3rd_party\ek-tm4c123gxl\system_TM4C123GH6PM.c + + + TM4C123GH6PM.h + 5 + ..\..\..\..\3rd_party\ek-tm4c123gxl\TM4C123GH6PM.h + + + + + sst + + + sst0.c + 1 + ..\..\..\src\sst0.c + + + + + sst_port + + + sst_port.h + 5 + ..\..\..\ports\arm-cm\sst_port.h + + + + + + + + + + + + + + + + + ek-tm4c123gxl + 1 + + + + + diff --git a/sst0_c/examples/blinky_button/armclang/nucleo-h743zi.uvprojx b/sst0_c/examples/blinky_button/armclang/nucleo-h743zi.uvprojx index 537076d..128a136 100644 --- a/sst0_c/examples/blinky_button/armclang/nucleo-h743zi.uvprojx +++ b/sst0_c/examples/blinky_button/armclang/nucleo-h743zi.uvprojx @@ -49,7 +49,7 @@ 1 .\build_nucleo-h743zi\ - blinky-button + blinky_button 1 0 0 @@ -82,7 +82,7 @@ 1 0 - fromelf --bin --output .\build_nucleo-h743zi\blinky-button.bin .\build_nucleo-h743zi\blinky-button.axf + fromelf --bin --output .\build_nucleo-h743zi\blinky_button.bin .\build_nucleo-h743zi\blinky_button.axf 0 0 diff --git a/sst0_c/examples/blinky_button/armclang/nucleo-l053r8.uvprojx b/sst0_c/examples/blinky_button/armclang/nucleo-l053r8.uvprojx index 1c7d1c6..2d4d2af 100644 --- a/sst0_c/examples/blinky_button/armclang/nucleo-l053r8.uvprojx +++ b/sst0_c/examples/blinky_button/armclang/nucleo-l053r8.uvprojx @@ -49,7 +49,7 @@ 1 .\build_nucleo-l053r8\ - blinky-button + blinky_button 1 0 0 @@ -82,7 +82,7 @@ 1 0 - fromelf --bin --output .\build_nucleo-l053r8\blinky-button.bin .\build_nucleo-l053r8\blinky-button.axf + fromelf --bin --output .\build_nucleo-l053r8\blinky_button.bin .\build_nucleo-l053r8\blinky_button.axf 0 0 diff --git a/sst0_c/examples/blinky_button/blinky1.c b/sst0_c/examples/blinky_button/blinky1.c index d8283fc..f14c1de 100644 --- a/sst0_c/examples/blinky_button/blinky1.c +++ b/sst0_c/examples/blinky_button/blinky1.c @@ -27,7 +27,7 @@ #include "bsp.h" /* Board Support Package interface */ #include "blinky_button.h" /* application shared interface */ -Q_DEFINE_THIS_FILE +DBC_MODULE_NAME("blinky1") /*..........................................................................*/ typedef struct { /* Blinky active object */ @@ -56,7 +56,8 @@ void Blinky1_ctor(void) { /*..........................................................................*/ static void Blinky1_init(Blinky1 * const me, SST_Evt const * const ie) { /* the initial event must be provided and must be WORKLOAD_SIG */ - Q_REQUIRE((ie != (SST_Evt const *)0) && (ie->sig == BLINKY_WORK_SIG)); + DBC_REQUIRE(300, + (ie != (SST_Evt const *)0) && (ie->sig == BLINKY_WORK_SIG)); me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->toggles; me->ticks = SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks; @@ -84,7 +85,7 @@ static void Blinky1_dispatch(Blinky1 * const me, SST_Evt const * const e) { break; } default: { - Q_ERROR(); /* unexpected event */ + DBC_ERROR(500); /* unexpected event */ break; } } diff --git a/sst0_c/examples/blinky_button/blinky3.c b/sst0_c/examples/blinky_button/blinky3.c index 07902d7..c4988c4 100644 --- a/sst0_c/examples/blinky_button/blinky3.c +++ b/sst0_c/examples/blinky_button/blinky3.c @@ -27,7 +27,7 @@ #include "bsp.h" /* Board Support Package interface */ #include "blinky_button.h" /* application shared interface */ -Q_DEFINE_THIS_FILE +DBC_MODULE_NAME("blinky3") /*..........................................................................*/ typedef struct { /* Blinky3 active object */ @@ -55,7 +55,8 @@ void Blinky3_ctor(void) { /*..........................................................................*/ static void Blinky3_init(Blinky3 * const me, SST_Evt const * const ie) { /* the initial event must be provided and must be WORKLOAD_SIG */ - Q_REQUIRE((ie != (SST_Evt const *)0) && (ie->sig == BLINKY_WORK_SIG)); + DBC_REQUIRE(300, + (ie != (SST_Evt const *)0) && (ie->sig == BLINKY_WORK_SIG)); me->toggles = SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->toggles; me->ticks = SST_EVT_DOWNCAST(BlinkyWorkEvt, ie)->ticks; @@ -83,7 +84,7 @@ static void Blinky3_dispatch(Blinky3 * const me, SST_Evt const * const e) { break; } default: { - Q_ERROR(); /* unexpected event */ + DBC_ERROR(500); /* unexpected event */ break; } } diff --git a/sst0_c/examples/blinky_button/blinky_button.h b/sst0_c/examples/blinky_button/blinky_button.h index b6527c7..ac3edc8 100644 --- a/sst0_c/examples/blinky_button/blinky_button.h +++ b/sst0_c/examples/blinky_button/blinky_button.h @@ -26,7 +26,7 @@ #ifndef BLINKY_BUTTON_H_ #define BLINKY_BUTTON_H_ -#include "qassert.h" /* embedded systems assertions */ +#include "dbc_assert.h" /* Design By Contract (DBC) assertions */ enum Signals { TICK_SIG, diff --git a/sst0_c/examples/blinky_button/bsp_ek-tm4c123gxl.c b/sst0_c/examples/blinky_button/bsp_ek-tm4c123gxl.c new file mode 100644 index 0000000..fe3adad --- /dev/null +++ b/sst0_c/examples/blinky_button/bsp_ek-tm4c123gxl.c @@ -0,0 +1,293 @@ +/*============================================================================ +* Super-Simple Tasker (SST0/C) Example for TivaC TM4C123GXL +* +* Copyright (C) 2006-2023 Quantum Leaps, . +* +* SPDX-License-Identifier: MIT +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +* DEALINGS IN THE SOFTWARE. +============================================================================*/ +#include "sst.h" +#include "bsp.h" +#include "blinky_button.h" + +#include "TM4C123GH6PM.h" /* the device specific header (TI) */ +#include /* to exercise the FPU */ +/* add other drivers if necessary... */ + +DBC_MODULE_NAME("bsp_ek-tm4c123gxl") /* for DBC assertions in this module */ + +/* Local-scope defines -----------------------------------------------------*/ + +/* test pins on GPIOF */ +#define TST1_PIN (1U << 1U) /* LED Red */ +#define TST2_PIN (1U << 2U) /* LED Blue */ + +/* test pins on GPIOD */ +#define TST3_PIN (1U << 0U) +#define TST4_PIN (1U << 1U) +#define TST5_PIN (1U << 2U) + +/* test pins on GPIOF */ +#define TST6_PIN (1U << 3U) /* LED Green */ + +/* Button on the board on GPIOF */ +#define BTN_SW1 (1U << 4) + +/* ISRs used in the application ============================================*/ +void SysTick_Handler(void); /* prototype */ + +void SysTick_Handler(void) { /* system clock tick ISR */ + BSP_d1on(); + + /* immutable timeout event */ + static SST_Evt const tickEvt = { TICK_SIG }; + SST_Task_post(AO_Blinky1, &tickEvt); /* every tick is fast for Blinky1 */ + SST_Task_post(AO_Blinky3, &tickEvt); + + /* get state of the user button */ + /* Perform the debouncing of buttons. The algorithm for debouncing + * adapted from the book "Embedded Systems Dictionary" by Jack Ganssle + * and Michael Barr, page 71. + */ + static struct ButtonsDebouncing { + uint32_t depressed; + uint32_t previous; + } buttons = { 0U, 0U }; + uint32_t current = ~GPIOF_AHB->DATA_Bits[BTN_SW1]; + uint32_t tmp = buttons.depressed; /* save the debounced depressed */ + buttons.depressed |= (buttons.previous & current); /* set depressed */ + buttons.depressed &= (buttons.previous | current); /* clear released */ + buttons.previous = current; /* update the history */ + tmp ^= buttons.depressed; /* changed debounced depressed */ + if ((tmp & BTN_SW1) != 0U) { /* debounced SW1 state changed? */ + if ((buttons.depressed & BTN_SW1) != 0U) { /* is SW1 depressed? */ + /* immutable button-press event */ + static ButtonWorkEvt const pressEvt = { + .super.sig = BUTTON_PRESSED_SIG, + .toggles = 60U + }; + /* immutable forward-press event */ + static ButtonWorkEvt const fPressEvt = { + .super.sig = FORWARD_PRESSED_SIG, + .toggles = 60U + }; + SST_Task_post(AO_Button2a, &fPressEvt.super); + SST_Task_post(AO_Button2a, &pressEvt.super); + } + else { /* B1 is released */ + /* immutable button-release event */ + static ButtonWorkEvt const releaseEvt = { + .super.sig = BUTTON_RELEASED_SIG, + .toggles = 80U + }; + /* immutable forward-release event */ + static ButtonWorkEvt const fReleaseEvt = { + .super.sig = FORWARD_RELEASED_SIG, + .toggles = 80U + }; + SST_Task_post(AO_Button2a, &fReleaseEvt.super); + SST_Task_post(AO_Button2a, &releaseEvt.super); + } + } + + BSP_d1off(); +} + +/* Assertion handler ======================================================*/ +void DBC_fault_handler(char const * const module, int const label) { + /* + * NOTE: add here your application-specific error handling + */ + (void)module; + (void)label; + + /* set PRIMASK to disable interrupts and stop SST right here */ + __asm volatile ("cpsid i"); + +#ifndef NDEBUG + for (;;) { /* keep blinking LED2 */ + BSP_d6on(); /* turn LED2 on */ + uint32_t volatile ctr; + for (ctr = 1000000U; ctr > 0U; --ctr) { + } + BSP_d6off(); /* turn LED2 off */ + for (ctr = 1000000U; ctr > 0U; --ctr) { + } + } +#endif + NVIC_SystemReset(); +} +/* BSP functions ===========================================================*/ +void BSP_init(void) { + + SYSCTL->RCGCGPIO |= (1U << 5U); /* enable Run mode for GPIOF */ + SYSCTL->RCGCGPIO |= (1U << 3U); /* enable Run mode for GPIOD */ + __ISB(); + __DSB(); + + SYSCTL->GPIOHBCTL |= (1U << 5); /* enable AHB for GPIOF */ + SYSCTL->GPIOHBCTL |= (1U << 3); /* enable AHB for GPIOD */ + __ISB(); + __DSB(); + + /* configure test pins on GPIOF (digital output) */ + GPIOF_AHB->DIR |= (TST1_PIN | TST2_PIN | TST6_PIN); + GPIOF_AHB->DEN |= (TST1_PIN | TST2_PIN | TST6_PIN); + + /* configure button on GPIOF (digital input) */ + GPIOF_AHB->DIR &= ~(BTN_SW1); /* input */ + GPIOF_AHB->DEN |= (BTN_SW1); /* digital enable */ + GPIOF_AHB->PUR |= (BTN_SW1); /* pull-up resistor enable */ + + /* configure test pins on GPIOD (digital output) */ + GPIOD_AHB->DIR |= (TST3_PIN | TST4_PIN | TST5_PIN); + GPIOD_AHB->DEN |= (TST3_PIN | TST4_PIN | TST5_PIN); +} + +/*..........................................................................*/ +#if defined __ARMCC_VERSION +#elif defined __GNUC__ +uint32_t __errno; /* GNU-ARM needs this to link sqrtf() */ +#endif + +static void exerciseFPU(float x) { + /* exercise the single-precision FPU by calculating the identity: + * sqrt(x) == x / sqrt(x) for x > 0 + */ + float tmp1 = sqrtf(x); /* single-precision sqrt() */ + float tmp2 = x / tmp1; + DBC_ENSURE(200, (tmp1 - 1e-4f <= tmp2) && (tmp2 <= tmp1 + 1e-4f)); +} + +/*..........................................................................*/ +void BSP_d1on(void) { /* LED-Red */ + GPIOF_AHB->DATA_Bits[TST1_PIN] = 0xFFU; + /* don't use the FPU in the ISR */ +} +void BSP_d1off(void) { + GPIOF_AHB->DATA_Bits[TST1_PIN] = 0x00U; +} +/*..........................................................................*/ +void BSP_d2on(void) { /* LED-Blue */ + GPIOF_AHB->DATA_Bits[TST2_PIN] = 0xFFU; + exerciseFPU(1.2345f); +} +void BSP_d2off(void) { + GPIOF_AHB->DATA_Bits[TST2_PIN] = 0x00U; +} +/*..........................................................................*/ +void BSP_d3on(void) { + GPIOD_AHB->DATA_Bits[TST3_PIN] = 0xFFU; + exerciseFPU(0.345f); +} +void BSP_d3off(void) { + GPIOD_AHB->DATA_Bits[TST3_PIN] = 0x00U; +} +/*..........................................................................*/ +void BSP_d4on(void) { + GPIOD_AHB->DATA_Bits[TST4_PIN] = 0xFFU; + exerciseFPU(0.456f); +} +void BSP_d4off(void) { + GPIOD_AHB->DATA_Bits[TST4_PIN] = 0x00U; +} +/*..........................................................................*/ +void BSP_d5on(void) { + GPIOD_AHB->DATA_Bits[TST5_PIN] = 0xFFU; + exerciseFPU(1.567f); +} +void BSP_d5off(void) { + GPIOD_AHB->DATA_Bits[TST5_PIN] = 0x00U; +} +/*..........................................................................*/ +void BSP_d6on(void) { /* LED2-Green */ + GPIOF_AHB->DATA_Bits[TST6_PIN] = 0xFFU; + exerciseFPU(1.2345f); +} +void BSP_d6off(void) { + GPIOF_AHB->DATA_Bits[TST6_PIN] = 0x00U; +} + +/*..........................................................................*/ +SST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num) { + /* immutable work events for Blinky1 */ + static BlinkyWorkEvt const workBliny1[] = { + { + .super.sig = BLINKY_WORK_SIG, + .toggles = 40U, + .ticks = 5U, + }, + { + .super.sig = BLINKY_WORK_SIG, + .toggles = 30U, + .ticks = 7U, + } + }; + DBC_REQUIRE(500, + num < ARRAY_NELEM(workBliny1)); /* num must be in range */ + return &workBliny1[num].super; +} +/*..........................................................................*/ +SST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num) { + /* immutable work events for Blinky3 */ + static BlinkyWorkEvt const workBlinky3[] = { + { + .super.sig = BLINKY_WORK_SIG, + .toggles = 20U, + .ticks = 5U, + }, + { + .super.sig = BLINKY_WORK_SIG, + .toggles = 10U, + .ticks = 3U, + } + }; + DBC_REQUIRE(600, + num < ARRAY_NELEM(workBlinky3)); /* num must be in range */ + return &workBlinky3[num].super; +} + +/* SST callbacks ===========================================================*/ +void SST_onStart(void) { + SystemCoreClockUpdate(); + + /* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate */ + SysTick_Config((SystemCoreClock / BSP_TICKS_PER_SEC) + 1U); + + /* set priorities of ISRs used in the system */ + NVIC_SetPriority(SysTick_IRQn, 0U); + /* ... */ +} +/*..........................................................................*/ +void SST_onIdleCond(void) { /* NOTE: called with interrupts DISABLED */ + BSP_d6on(); /* turn LED-Green on */ +#ifdef NDEBUG + /* Put the CPU and peripherals to the low-power mode. + * you might need to customize the clock management for your application, + * see the datasheet for your particular Cortex-M MCU. + */ + BSP_d6off(); /* turn LED-Green off */ + __WFI(); /* Wait-For-Interrupt */ + BSP_d6on(); /* turn LED-Green on */ +#endif + BSP_d6off(); /* turn LED-Green off */ + SST_PORT_INT_ENABLE(); /* NOTE: enable interrupts for SS0 */ +} + diff --git a/sst0_c/examples/blinky_button/bsp_nucleo-h743zi.c b/sst0_c/examples/blinky_button/bsp_nucleo-h743zi.c index 2ea95b6..21c31a5 100644 --- a/sst0_c/examples/blinky_button/bsp_nucleo-h743zi.c +++ b/sst0_c/examples/blinky_button/bsp_nucleo-h743zi.c @@ -31,7 +31,7 @@ #include /* to exercise the FPU */ /* add other drivers if necessary... */ -Q_DEFINE_THIS_FILE +DBC_MODULE_NAME("bsp_nucleo-h743zi") /* for DBC assertions in this module */ /* Local-scope defines -----------------------------------------------------*/ @@ -106,6 +106,30 @@ void SysTick_Handler(void) { /* system clock tick ISR */ BSP_d1off(); } +/* Assertion handler ======================================================*/ +void DBC_fault_handler(char const * const module, int const loc) { + /* + * NOTE: add here your application-specific error handling + */ + (void)module; + (void)loc; + + /* set PRIMASK to disable interrupts and stop SST right here */ + __asm volatile ("cpsid i"); + +#ifndef NDEBUG + for (;;) { /* keep blinking LED2 */ + BSP_d6on(); /* turn LED2 on */ + uint32_t volatile ctr; + for (ctr = 1000000U; ctr > 0U; --ctr) { + } + BSP_d6off(); /* turn LED2 off */ + for (ctr = 1000000U; ctr > 0U; --ctr) { + } + } +#endif + NVIC_SystemReset(); +} /* BSP functions ===========================================================*/ void BSP_init(void) { SCB_EnableICache(); /* Enable I-Cache */ @@ -139,9 +163,11 @@ void BSP_init(void) { /*..........................................................................*/ static void exerciseFPU(double x) { - /* exercise the FPU by calculating trigonometric identity */ + /* exercise the double-precision FPU by calculating the identity: + * sin(x)^2 + cos(x)^2 == 1.0 for any x + */ double tmp = pow(sin(x), 2.0) + pow(cos(x), 2.0); - Q_ENSURE(((1.0 - 1e-4) < tmp) && (tmp < (1.0 + 1e-4))); + DBC_ENSURE(200, ((1.0 - 1e-4) < tmp) && (tmp < (1.0 + 1e-4))); } /*..........................................................................*/ @@ -208,7 +234,8 @@ SST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num) { .ticks = 7U, } }; - Q_REQUIRE(num < Q_DIM(workBliny1)); /* num must be in range */ + DBC_REQUIRE(500, + num < ARRAY_NELEM(workBliny1)); /* num must be in range */ return &workBliny1[num].super; } /*..........................................................................*/ @@ -226,7 +253,8 @@ SST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num) { .ticks = 3U, } }; - Q_REQUIRE(num < Q_DIM(workBlinky3)); /* num must be in range */ + DBC_REQUIRE(600, + num < ARRAY_NELEM(workBlinky3)); /* num must be in range */ return &workBlinky3[num].super; } @@ -243,50 +271,16 @@ void SST_onStart(void) { } /*..........................................................................*/ void SST_onIdleCond(void) { /* NOTE: called with interrupts DISABLED */ + BSP_d6on(); /* turn LED2 on */ #ifdef NDEBUG /* Put the CPU and peripherals to the low-power mode. * you might need to customize the clock management for your application, * see the datasheet for your particular Cortex-M MCU. */ - /* !!!CAUTION!!! - * The WFI instruction stops the CPU clock, which unfortunately disables - * the JTAG port, so the ST-Link debugger can no longer connect to the - * board. For that reason, the call to __WFI() has to be used with CAUTION. - * - * NOTE: If you find your board "frozen" like this, strap BOOT0 to VDD and - * reset the board, then connect with ST-Link Utilities and erase the part. - * The trick with BOOT(0) is it gets the part to run the System Loader - * instead of your broken code. When done disconnect BOOT0, and start over. - */ + BSP_d6off(); /* turn LED2 off */ __WFI(); /* Wait-For-Interrupt */ -#else BSP_d6on(); /* turn LED2 on */ - BSP_d6off(); /* turn LED2 off */ -#endif - SST_PORT_INT_ENABLE(); /* NOTE: enable interrupts in every path */ -} - -/* Assertion handler ======================================================*/ -void Q_onAssert(char const * const module, int const loc) { - /* - * NOTE: add here your application-specific error handling - */ - (void)module; - (void)loc; - - /* set PRIMASK to disable interrupts and stop SST right here */ - __asm volatile ("cpsid i"); - -#ifndef NDEBUG - for (;;) { /* keep blinking LED2 */ - BSP_d6on(); /* turn LED2 on */ - uint32_t volatile ctr; - for (ctr = 1000000U; ctr != 0U; --ctr) { - } - BSP_d6off(); /* turn LED2 off */ - for (ctr = 1000000U; ctr != 0U; --ctr) { - } - } #endif - NVIC_SystemReset(); + BSP_d6off(); /* turn LED2 off */ + SST_PORT_INT_ENABLE(); /* NOTE: enable interrupts for SS0 */ } diff --git a/sst0_c/examples/blinky_button/bsp_nucleo-l053r8.c b/sst0_c/examples/blinky_button/bsp_nucleo-l053r8.c index 9bb146f..d013a34 100644 --- a/sst0_c/examples/blinky_button/bsp_nucleo-l053r8.c +++ b/sst0_c/examples/blinky_button/bsp_nucleo-l053r8.c @@ -30,7 +30,7 @@ #include "stm32l0xx.h" /* CMSIS-compliant header file for the MCU used */ /* add other drivers if necessary... */ -Q_DEFINE_THIS_FILE /* for assertions in this file */ +DBC_MODULE_NAME("bsp_nucleo-l053r8") /* for DBC assertions in this module */ /* Local-scope defines -----------------------------------------------------*/ @@ -105,6 +105,30 @@ void SysTick_Handler(void) { /* system clock tick ISR */ BSP_d1off(); } +/* Assertion handler ======================================================*/ +void DBC_fault_handler(char const * const module, int const loc) { + /* + * NOTE: add here your application-specific error handling + */ + (void)module; + (void)loc; + + /* set PRIMASK to disable interrupts and stop SST right here */ + __asm volatile ("cpsid i"); + +#ifndef NDEBUG + for (;;) { /* keep blinking LED2 */ + BSP_d6on(); /* turn LED2 on */ + uint32_t volatile ctr; + for (ctr = 10000U; ctr > 0U; --ctr) { + } + BSP_d6off(); /* turn LED2 off */ + for (ctr = 10000U; ctr > 0U; --ctr) { + } + } +#endif + NVIC_SystemReset(); +} /* BSP functions ===========================================================*/ void BSP_init(void) { @@ -167,7 +191,8 @@ SST_Evt const *BSP_getWorkEvtBlinky1(uint8_t num) { .ticks = 7U, } }; - Q_REQUIRE(num < Q_DIM(workBliny1)); /* num must be in range */ + DBC_REQUIRE(500, + num < ARRAY_NELEM(workBliny1)); /* num must be in range */ return &workBliny1[num].super; } /*..........................................................................*/ @@ -185,7 +210,8 @@ SST_Evt const *BSP_getWorkEvtBlinky3(uint8_t num) { .ticks = 3U, } }; - Q_REQUIRE(num < Q_DIM(workBlinky3)); /* num must be in range */ + DBC_REQUIRE(600, + num < ARRAY_NELEM(workBlinky3)); /* num must be in range */ return &workBlinky3[num].super; } @@ -202,50 +228,16 @@ void SST_onStart(void) { } /*..........................................................................*/ void SST_onIdleCond(void) { /* NOTE: called with interrupts DISABLED */ + BSP_d6on(); /* turn LED2 on */ #ifdef NDEBUG /* Put the CPU and peripherals to the low-power mode. * you might need to customize the clock management for your application, * see the datasheet for your particular Cortex-M MCU. */ - /* !!!CAUTION!!! - * The WFI instruction stops the CPU clock, which unfortunately disables - * the JTAG port, so the ST-Link debugger can no longer connect to the - * board. For that reason, the call to __WFI() has to be used with CAUTION. - * - * NOTE: If you find your board "frozen" like this, strap BOOT0 to VDD and - * reset the board, then connect with ST-Link Utilities and erase the part. - * The trick with BOOT(0) is it gets the part to run the System Loader - * instead of your broken code. When done disconnect BOOT0, and start over. - */ + BSP_d6off(); /* turn LED2 off */ __WFI(); /* Wait-For-Interrupt */ -#else BSP_d6on(); /* turn LED2 on */ - BSP_d6off(); /* turn LED2 off */ #endif - SST_PORT_INT_ENABLE(); /* NOTE: enable interrupts in every path */ -} - -/* Assertion handler ======================================================*/ -void Q_onAssert(char const * const module, int const loc) { - /* - * NOTE: add here your application-specific error handling - */ - (void)module; - (void)loc; - - /* set PRIMASK to disable interrupts and stop SST right here */ - __asm volatile ("cpsid i"); - -#ifndef NDEBUG - for (;;) { /* keep blinking LED2 */ - BSP_d6on(); /* turn LED2 on */ - uint32_t volatile ctr; - for (ctr = 10000U; ctr != 0U; --ctr) { - } - BSP_d6off(); /* turn LED2 off */ - for (ctr = 10000U; ctr != 0U; --ctr) { - } - } -#endif - NVIC_SystemReset(); + BSP_d6off(); /* turn LED2 off */ + SST_PORT_INT_ENABLE(); /* NOTE: enable interrupts for SS0 */ } diff --git a/sst0_c/examples/blinky_button/button2a.c b/sst0_c/examples/blinky_button/button2a.c index f533b93..cb6b99b 100644 --- a/sst0_c/examples/blinky_button/button2a.c +++ b/sst0_c/examples/blinky_button/button2a.c @@ -27,7 +27,7 @@ #include "bsp.h" /* Board Support Package interface */ #include "blinky_button.h" /* application shared interface */ -Q_DEFINE_THIS_FILE +DBC_MODULE_NAME("button2a") /*..........................................................................*/ typedef struct { /* Button2a active object */ @@ -58,6 +58,7 @@ static void Button2a_init(Button2a * const me, SST_Evt const * const ie) { } /*..........................................................................*/ static void Button2a_dispatch(Button2a * const me, SST_Evt const * const e) { + (void)me; switch (e->sig) { case BUTTON_PRESSED_SIG: { BSP_d4on(); @@ -102,7 +103,7 @@ static void Button2a_dispatch(Button2a * const me, SST_Evt const * const e) { break; } default: { - Q_ERROR(); /* unexpected event */ + DBC_ERROR(500); /* unexpected event */ break; } } diff --git a/sst0_c/examples/blinky_button/button2b.c b/sst0_c/examples/blinky_button/button2b.c index 153b85b..d9fef59 100644 --- a/sst0_c/examples/blinky_button/button2b.c +++ b/sst0_c/examples/blinky_button/button2b.c @@ -27,7 +27,7 @@ #include "bsp.h" /* Board Support Package interface */ #include "blinky_button.h" /* application shared interface */ -Q_DEFINE_THIS_FILE +DBC_MODULE_NAME("button2b") /*..........................................................................*/ typedef struct { /* Button2b active object */ @@ -88,7 +88,7 @@ static void Button2b_dispatch(Button2b * const me, SST_Evt const * const e) { break; } default: { - Q_ERROR(); /* unexpected event */ + DBC_ERROR(500); /* unexpected event */ break; } } diff --git a/sst0_c/examples/blinky_button/gnu/ek-tm4c123gxl.mak b/sst0_c/examples/blinky_button/gnu/ek-tm4c123gxl.mak new file mode 100644 index 0000000..a5eccda --- /dev/null +++ b/sst0_c/examples/blinky_button/gnu/ek-tm4c123gxl.mak @@ -0,0 +1,241 @@ +############################################################################## +# Makefile for Super-Simple Tasker (SST/C) on TM4C123GXL, GNU-ARM +# Last Updated for Version: 2.0.0 +# Date of the Last Update: 2023-01-25 +# +# Q u a n t u m L e a P s +# ------------------------ +# Modern Embedded Software +# +# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved. +# +# SPDX-License-Identifier: MIT +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to +# deal in the Software without restriction, including without limitation the +# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +# sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +############################################################################## +# examples of invoking this Makefile: +# make -f gnu_ek-tm4c123gxl +# make -f gnu_ek-tm4c123gxl clean +# +# NOTE: +# To use this Makefile on Windows, you will need the GNU make utility, which +# is included in the QTools collection for Windows, see: +# https://github.com/QuantumLeaps/qtools +# + +#----------------------------------------------------------------------------- +# project and target names +# +PROJECT := blinky_button +TARGET := ek-tm4c123gxl + +#----------------------------------------------------------------------------- +# project directories +# +SST_DIR := ../../.. +SST_PORT_DIR := $(SST_DIR)/ports/arm-cm +TARGET_DIR := $(SST_DIR)/../3rd_party/$(TARGET) + +# list of all source directories used by this project +VPATH = .. \ + $(SST_DIR)/src \ + $(SST_PORT_DIR) \ + $(TARGET_DIR) \ + $(TARGET_DIR)/gnu \ + +# list of all include directories needed by this project +INCLUDES = -I. \ + -I$(SST_DIR)/../include \ + -I$(SST_PORT_DIR) \ + -I$(TARGET_DIR) + +#----------------------------------------------------------------------------- +# project files +# + +# assembler source files +ASM_SRCS := + +# C source files +C_SRCS := \ + sst0.c \ + main.c \ + blinky1.c \ + blinky3.c \ + button2a.c \ + button2b.c \ + bsp_ek-tm4c123gxl.c \ + system_TM4C123GH6PM.c \ + startup_TM4C123GH6PM.c + +# C++ source files +CPP_SRCS := + +LD_SCRIPT := $(TARGET_DIR)/$(TARGET).ld + +OUTPUT := $(PROJECT) + +LIB_DIRS := +LIBS := + +# defines +DEFINES := -DTARGET_IS_TM4C123_RB1 + +# ARM CPU, ARCH, FPU, and Float-ABI types... +# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4] +# ARM_FPU: [ | vfp] +# FLOAT_ABI: [ | soft | softfp | hard] +# +ARM_CPU := -mcpu=cortex-m4 +ARM_FPU := -mfpu=vfp +FLOAT_ABI := -mfloat-abi=softfp + +#----------------------------------------------------------------------------- +# GNU-ARM toolset (NOTE: You need to adjust to your machine) +# see https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads +# +ifeq ($(GNU_ARM),) +GNU_ARM := $(QTOOLS)/gnu_arm-none-eabi +endif + +# make sure that the GNU-ARM toolset exists... +ifeq ("$(wildcard $(GNU_ARM))","") +$(error GNU_ARM toolset not found. Please adjust the Makefile) +endif + +CC := $(GNU_ARM)/bin/arm-none-eabi-gcc +CPP := $(GNU_ARM)/bin/arm-none-eabi-g++ +AS := $(GNU_ARM)/bin/arm-none-eabi-as +LINK := $(GNU_ARM)/bin/arm-none-eabi-gcc +BIN := $(GNU_ARM)/bin/arm-none-eabi-objcopy + +############################################################################## +# Typically you should not need to change anything below this line + +# basic utilities (included in QTools for Windows), see: +# https://www.state-machine.com/qtools + +MKDIR := mkdir +RM := rm + +#----------------------------------------------------------------------------- +# build options +# + +# combine all the soruces... +C_SRCS += $(QP_SRCS) +ASM_SRCS += $(QP_ASMS) + +BIN_DIR := build_$(TARGET) + +ASFLAGS = -g $(ARM_CPU) $(ARM_FPU) $(ASM_CPU) $(ASM_FPU) + +CFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c99 -mthumb -Wall \ + -ffunction-sections -fdata-sections \ + -O $(INCLUDES) $(DEFINES) + +CPPFLAGS = -c -g $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -std=c++11 -mthumb -Wall \ + -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions \ + -O $(INCLUDES) $(DEFINES) + +LINKFLAGS = -T$(LD_SCRIPT) $(ARM_CPU) $(ARM_FPU) $(FLOAT_ABI) -mthumb \ + -specs=nosys.specs -specs=nano.specs \ + -Wl,-Map,$(BIN_DIR)/$(OUTPUT).map,--cref,--gc-sections $(LIB_DIRS) + +ASM_OBJS := $(patsubst %.s,%.o, $(notdir $(ASM_SRCS))) +C_OBJS := $(patsubst %.c,%.o, $(notdir $(C_SRCS))) +CPP_OBJS := $(patsubst %.cpp,%.o,$(notdir $(CPP_SRCS))) + +TARGET_BIN := $(BIN_DIR)/$(OUTPUT).bin +TARGET_ELF := $(BIN_DIR)/$(OUTPUT).elf +ASM_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(ASM_OBJS)) +C_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(C_OBJS)) +C_DEPS_EXT := $(patsubst %.o, %.d, $(C_OBJS_EXT)) +CPP_OBJS_EXT := $(addprefix $(BIN_DIR)/, $(CPP_OBJS)) +CPP_DEPS_EXT := $(patsubst %.o, %.d, $(CPP_OBJS_EXT)) + +# create $(BIN_DIR) if it does not exist +ifeq ("$(wildcard $(BIN_DIR))","") +$(shell $(MKDIR) $(BIN_DIR)) +endif + +#----------------------------------------------------------------------------- +# rules +# + +.PHONY : run norun flash + +ifeq ($(MAKECMDGOALS),norun) +all : $(TARGET_BIN) +norun : all +else +all : $(TARGET_BIN) run +endif + +$(TARGET_BIN): $(TARGET_ELF) + $(BIN) -O binary $< $@ + +$(TARGET_ELF) : $(ASM_OBJS_EXT) $(C_OBJS_EXT) $(CPP_OBJS_EXT) + $(LINK) $(LINKFLAGS) -o $@ $^ $(LIBS) + +$(BIN_DIR)/%.d : %.c + $(CC) -MM -MT $(@:.d=.o) $(CFLAGS) $< > $@ + +$(BIN_DIR)/%.d : %.cpp + $(CPP) -MM -MT $(@:.d=.o) $(CPPFLAGS) $< > $@ + +$(BIN_DIR)/%.o : %.s + $(AS) $(ASFLAGS) $< -o $@ + +$(BIN_DIR)/%.o : %.c + $(CC) $(CFLAGS) $< -o $@ + +$(BIN_DIR)/%.o : %.cpp + $(CPP) $(CPPFLAGS) $< -o $@ + +.PHONY : clean show + +# include dependency files only if our goal depends on their existence +ifneq ($(MAKECMDGOALS),clean) + ifneq ($(MAKECMDGOALS),show) +-include $(C_DEPS_EXT) $(CPP_DEPS_EXT) + endif +endif + + +clean : + -$(RM) $(BIN_DIR)/*.o \ + $(BIN_DIR)/*.d \ + $(BIN_DIR)/*.bin \ + $(BIN_DIR)/*.elf \ + $(BIN_DIR)/*.map + +show: + @echo PROJECT = $(PROJECT) + @echo CONF = $(CONF) + @echo DEFINES = $(DEFINES) + @echo ASM_FPU = $(ASM_FPU) + @echo ASM_SRCS = $(ASM_SRCS) + @echo C_SRCS = $(C_SRCS) + @echo CPP_SRCS = $(CPP_SRCS) + @echo ASM_OBJS_EXT = $(ASM_OBJS_EXT) + @echo C_OBJS_EXT = $(C_OBJS_EXT) + @echo C_DEPS_EXT = $(C_DEPS_EXT) + @echo CPP_DEPS_EXT = $(CPP_DEPS_EXT) + @echo TARGET_ELF = $(TARGET_ELF) diff --git a/sst0_c/examples/blinky_button/gnu/flash_ek-tm4c123gxl.bat b/sst0_c/examples/blinky_button/gnu/flash_ek-tm4c123gxl.bat new file mode 100644 index 0000000..cb2a388 --- /dev/null +++ b/sst0_c/examples/blinky_button/gnu/flash_ek-tm4c123gxl.bat @@ -0,0 +1,33 @@ +::============================================================================ +:: Batch file to program the flash of EK-TM4C123GXL +:: +:: NOTE: requires the LMFlash programmer (included in QTools for Windows) +:: +@echo off +setlocal + +@echo Load a given binary file to the flash of EK-TM4C123GXL +@echo usage: flash binary-file +@echo example: flash dbg\blinky-qk.bin + +::---------------------------------------------------------------------------- +:: NOTE: The following symbol LMFLASH assumes that LMFlash.exe can +:: be found on the PATH. You might need to adjust this symbol to the +:: location of the LMFlash utility on your machine +:: +set LMFLASH=LMFlash.exe + +if ["%~1"]==[""] ( + @echo The binary file missing + @goto end +) +if not exist %~s1 ( + @echo The binary file '%1' does not exist + @goto end +) + +%LMFLASH% -q ek-tm4c123gxl -e -v -r %1 + +:end + +endlocal \ No newline at end of file diff --git a/sst0_c/examples/blinky_button/gnu/nucleo-h743zi.mak b/sst0_c/examples/blinky_button/gnu/nucleo-h743zi.mak index d7820a6..7244127 100644 --- a/sst0_c/examples/blinky_button/gnu/nucleo-h743zi.mak +++ b/sst0_c/examples/blinky_button/gnu/nucleo-h743zi.mak @@ -133,8 +133,6 @@ BIN := $(GNU_ARM)/bin/arm-none-eabi-objcopy MKDIR := mkdir RM := rm -CP := cp -SLEEP := sleep #----------------------------------------------------------------------------- # build options diff --git a/sst0_c/examples/blinky_button/gnu/nucleo-l053r8.mak b/sst0_c/examples/blinky_button/gnu/nucleo-l053r8.mak index aa6649d..bde9430 100644 --- a/sst0_c/examples/blinky_button/gnu/nucleo-l053r8.mak +++ b/sst0_c/examples/blinky_button/gnu/nucleo-l053r8.mak @@ -133,8 +133,6 @@ BIN := $(GNU_ARM)/bin/arm-none-eabi-objcopy MKDIR := mkdir RM := rm -CP := cp -SLEEP := sleep #----------------------------------------------------------------------------- # build options diff --git a/sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.ewd b/sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.ewd new file mode 100644 index 0000000..086b901 --- /dev/null +++ b/sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.ewd @@ -0,0 +1,1530 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 7 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.ewp b/sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.ewp new file mode 100644 index 0000000..908f1e1 --- /dev/null +++ b/sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.ewp @@ -0,0 +1,1105 @@ + + + 3 + + Debug + + ARM + + 1 + + General + 3 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 1 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 25 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + Coder + 0 + + + + + Application + + $PROJ_DIR$\..\blinky1.c + + + $PROJ_DIR$\..\blinky3.c + + + $PROJ_DIR$\..\blinky_button.h + + + $PROJ_DIR$\..\bsp.h + + + $PROJ_DIR$\..\bsp_ek-tm4c123gxl.c + + + $PROJ_DIR$\..\button2a.c + + + $PROJ_DIR$\..\button2b.c + + + $PROJ_DIR$\..\main.c + + + + ek-tm4c123gxl + + $PROJ_DIR$\..\..\..\..\3rd_party\ek-tm4c123gxl\iar\startup_TM4C123GH6PM.s + + + $PROJ_DIR$\..\..\..\..\3rd_party\ek-tm4c123gxl\system_TM4C123GH6PM.c + + + $PROJ_DIR$\..\..\..\..\3rd_party\ek-tm4c123gxl\TM4C123GH6PM.h + + + + sst + + $PROJ_DIR$\..\..\..\src\sst0.c + + + + sst_port + + $PROJ_DIR$\..\..\..\ports\arm-cm\sst_port.h + + + diff --git a/sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.eww b/sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.eww new file mode 100644 index 0000000..869fa1a --- /dev/null +++ b/sst0_c/examples/blinky_button/iar/ek-tm4c123gxl.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\ek-tm4c123gxl.ewp + + + + + diff --git a/sst0_c/examples/blinky_button/iar/nucleo-h743zi.ewp b/sst0_c/examples/blinky_button/iar/nucleo-h743zi.ewp index fc4fe29..9ea909c 100644 --- a/sst0_c/examples/blinky_button/iar/nucleo-h743zi.ewp +++ b/sst0_c/examples/blinky_button/iar/nucleo-h743zi.ewp @@ -632,11 +632,11 @@