midgetv is a RISC-V implementation written specifically for ice40* FPGAs. The base ISA is RV32I. Standard extensions Zicsr and Zifencei are always included. Standard extension C, M can be compiled in.
midgetv uses Wishbone b4 for interconnect.
Include midgetv.v into your project, and instantiate
m_midgetv_core. The program to run on the core is given by
parameters prg00 through prg0F, usually generated by transforming
a binary RISC-V program with the utility midgetv_bin2ebr.
More (rather unstructured) information is available here.
- Signal interface to module
m_midgetv_coreis part of the API. - The coarse memory map of midgetv is part of the API.
- The way a binary file is mapped to
localparamspecifications by the utilitymidgetv_bin2ebris part of the API.