So What's Going On?

[devbisme]

It's been silent for the past few months, so I thought I'd at least give an update on what I've been doing w.r.t. SKiDL.

My main effort has been to refactor and extend @shanemmattner 's code that generates an EESCHEMA schematic from SKiDL:

• Changed the scanning of the tools subdirectory so each tool has a separate directory that can contain multiple files. That way, everything for KiCad doesn't have to be stored in a single, multi-thousand line file.
• Refactored the code to make it a bit more object-oriented and use some pre-existing objects like the BBox for bounding boxes.
• Replaced Shane's approximate method for calculating part bounding boxes with some pre-existing code that handles graphic elements in addition to pin locations.
• Made the handling of schematic hierarchy more flexible. Now it uses an adjustable parameter to control flatness so all the circuitry can be forced onto a single page, or made completely hierarchical with all circuitry forced into the leaves, or anywhere in between.
• Currently I'm implementing the routing engine for generating the wiring between parts. I've built the global router that divides the routing area between parts into boxes to which nets are assigned as they connect from pin to pin. I'm now implementing the switchbox router that will do the detailed routing in each box. To get an idea of how this works, the image below shows some diagnostic output of the global routing phase for one page of Shane's STM32 example design (green boxes are schematic parts; the rest are routing boxes):

• After the switchbox router is done, I still have to handle multi-unit parts (e.g., resistor arrays). Then it should be ready for merging into the development branch and eventual release.

I also added a new feature to SKiDL called Group which lets you easily add hierarchy to a design without having to encapsulate it into a separate function. The example below groups the resistor and capacitor of a lowpass filter so they'll be placed together in the initial PCB layout if you use the HierPlace plugin.

    vin = Net()
    vout = Net()
    with Group("Lowpass"):
        r = Part("Device", "R", value="1K")
        c = Part("Device", "C", value="1uF")
        vin & r & vout & c & gnd

Unfortunately, Group is stuck in the gen_sch branch so it won't appear until I finish the cuurent version of the schematic generator.