diff --git a/devicetree/mainline/rk3588-rock-5-itx-fixup.dts b/devicetree/mainline/rk3588-rock-5-itx-fixup.dts
new file mode 100644
index 00000000..4872409a
--- /dev/null
+++ b/devicetree/mainline/rk3588-rock-5-itx-fixup.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-rock-5-itx.dts"
+
+/ {
+	/delete-node/ pcie-oscillator;
+};
+
+/*
+ * Remove the "pcie30_refclk" gated-fixed-clock to maintain compatibility
+ * with kernels older than v6.13-rc1. It is backed by a GPIO regulator
+ * anyway, so simply referencing it in vpcie3v3-supply also addresses
+ * the potential issue where pcie3x2 might probe earlier than pcie3x4 and
+ * hang on DBI access because the clock didn't have a chance to be enabled.
+ */
+&pcie3x2 {
+	clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+		 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+		 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk",
+		      "aux", "pipe";
+	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
+};
+
+&pcie3x4 {
+	clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+		 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+		 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk",
+		      "aux", "pipe";
+};
diff --git a/edk2-rockchip/Platform/Radxa/ROCK5ITX/DeviceTree/Mainline.inf b/edk2-rockchip/Platform/Radxa/ROCK5ITX/DeviceTree/Mainline.inf
index 5c3b4fa1..3290bb17 100644
--- a/edk2-rockchip/Platform/Radxa/ROCK5ITX/DeviceTree/Mainline.inf
+++ b/edk2-rockchip/Platform/Radxa/ROCK5ITX/DeviceTree/Mainline.inf
@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts
+  devicetree/mainline/rk3588-rock-5-itx-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec