From b95e0718720c52dba164d40899ae01d278d4c936 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 24 Oct 2024 17:31:59 +0300 Subject: [PATCH] Add new test to make sure no overflows --- verify/uvm-python/Makefile | 2 +- .../sram_write_read_all_mem_seq.py | 66 +++++++++++++++++++ verify/uvm-python/test_lib.py | 18 +++++ 3 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 verify/uvm-python/sram_seq_lib/sram_write_read_all_mem_seq.py diff --git a/verify/uvm-python/Makefile b/verify/uvm-python/Makefile index 7ec2fc0..05cca71 100644 --- a/verify/uvm-python/Makefile +++ b/verify/uvm-python/Makefile @@ -19,7 +19,7 @@ YAML_FILE = $(PWD)/../../EF_SRAM_1024x32.yaml # TODO: update yaml file path MAKEFLAGS += --no-print-directory # List of tests -TESTS := sram_corners_test sram_write_read_test +TESTS := sram_corners_test sram_write_read_test sram_write_read_all_test # Variable for tag - set this as required SIM_TAG ?= default_tag diff --git a/verify/uvm-python/sram_seq_lib/sram_write_read_all_mem_seq.py b/verify/uvm-python/sram_seq_lib/sram_write_read_all_mem_seq.py new file mode 100644 index 0000000..22fc230 --- /dev/null +++ b/verify/uvm-python/sram_seq_lib/sram_write_read_all_mem_seq.py @@ -0,0 +1,66 @@ +from uvm.seq import UVMSequence +from uvm.macros.uvm_object_defines import uvm_object_utils +from uvm.macros.uvm_message_defines import uvm_fatal +from uvm.base.uvm_config_db import UVMConfigDb +from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base +from cocotb.triggers import Timer +from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do +import random +from EF_UVM.bus_env.bus_item import bus_item +from sram_seq_lib.sram_bus_base_seq import sram_bus_base_seq +from sram_seq_lib.sram_init_seq import sram_init_seq +import cocotb + +class sram_write_read_all_mem_seq(sram_bus_base_seq): + # use this sequence write or read from register by the bus interface + # this sequence should be connected to the bus sequencer in the testbench + # you should create as many sequences as you need not only this one + def __init__(self, name="sram_corners_seq", mem_size=0x400): + super().__init__(name, mem_size) + self.mem_size = mem_size + + async def body(self): + await super().body() + all_addresses = [i * 4 for i in range(self.mem_size)] + # test all is accessable + for address in all_addresses: + await self.write_to_mem(address=address, data=address) + for address in all_addresses: + await self.read_from_mem(address=address, size=bus_item.WORD_ACCESS) + # write 0 to all + for address in all_addresses: + await self.write_to_mem(address=address, data=0) + # read from all + for address in all_addresses: + await self.read_from_mem(address=address, size=bus_item.WORD_ACCESS) + # write 1 to all bits + for address in all_addresses: + await self.write_to_mem(address=address, data=0xFFFFFFFF) + # read from all + for address in all_addresses: + await self.read_from_mem(address=address, size=bus_item.WORD_ACCESS) + # write 01 to all + for address in all_addresses: + await self.write_to_mem(address=address, data=0x55555555) + # read from all + for address in all_addresses: + await self.read_from_mem(address=address, size=bus_item.WORD_ACCESS) + # write 10 to all + for address in all_addresses: + await self.write_to_mem(address=address, data=0xaaaaaaaa) + # read from all + for address in all_addresses: + await self.read_from_mem(address=address, size=bus_item.WORD_ACCESS) + for i in range(10): + await self.send_nop() + + async def _write_read_seq(self, iterations, write_priority): + for _ in range(iterations): + address, size = self.rand_addr_size() + if random.random() >= write_priority: + await self.write_to_mem(address=address, size=size) + else: + await self.read_from_mem(address=address, size=size) + + +uvm_object_utils(sram_write_read_all_mem_seq) diff --git a/verify/uvm-python/test_lib.py b/verify/uvm-python/test_lib.py index 2be655a..a4fcc03 100644 --- a/verify/uvm-python/test_lib.py +++ b/verify/uvm-python/test_lib.py @@ -20,6 +20,7 @@ from sram_seq_lib.sram_corners_seq import sram_corners_seq from sram_seq_lib.sram_write_read_seq import sram_write_read_seq from sram_seq_lib.sram_ip_seq import sram_ip_seq +from sram_seq_lib.sram_write_read_all_mem_seq import sram_write_read_all_mem_seq # override classes from EF_UVM.ip_env.ip_agent.ip_driver import ip_driver @@ -129,3 +130,20 @@ async def main_phase(self, phase): uvm_component_utils(sram_write_read_test) + +class sram_write_read_all_test(sram_base_test): + def __init__(self, name="sram__first_test", parent=None): + super().__init__(name, parent=parent) + self.tag = name + + async def main_phase(self, phase): + uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW) + phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED") + # TODO: conntect sequence with sequencer here + # for example if you need to run the 2 sequence sequentially + bus_seq = sram_write_read_all_mem_seq("sram_corners_seq", mem_size=self.memory_size) + await bus_seq.start(self.bus_sqr) + phase.drop_objection(self, f"{self.__class__.__name__} drop objection") + + +uvm_component_utils(sram_write_read_all_test)