From 03954d1369f9dc36ae0031a32814b0eefaa96da1 Mon Sep 17 00:00:00 2001 From: Fan YANG Date: Fri, 12 May 2023 13:38:24 +0800 Subject: [PATCH] RT-Thread BSP v1.1.0 for HPM6300EVK - Integrated hpm_sdk v1.1.0 - Bugfixes for drivers and samples Signed-off-by: Fan YANG --- .gitattributes | 8 - .gitignore | 2 +- ChangeLog.md | 15 + ChangeLog_zh.md | 20 +- HPMicro-HPM6300EVK.yaml | 2 +- board/board.c | 15 +- board/board.h | 5 +- board/linker_scripts/flash_rtt.ld | 2 + board/linker_scripts/flash_rtt_enet.ld | 20 +- board/linker_scripts/ram_rtt.ld | 6 +- board/linker_scripts/ram_rtt_enet.ld | 218 + board/pinmux.c | 21 +- board/pinmux.h | 5 +- common/.gitattributes | 2 - common/.gitignore | 64 - common/libraries/drivers/SConscript | 6 + common/libraries/drivers/drv_adc.c | 29 +- common/libraries/drivers/drv_adc.h | 4 +- common/libraries/drivers/drv_can.c | 4 +- common/libraries/drivers/drv_can.h | 2 +- common/libraries/drivers/drv_dao.c | 2 +- common/libraries/drivers/drv_dao.h | 2 +- common/libraries/drivers/drv_enet.c | 63 +- common/libraries/drivers/drv_enet.h | 15 + common/libraries/drivers/drv_gpio.c | 7 +- common/libraries/drivers/drv_gpio.h | 2 +- common/libraries/drivers/drv_hwtimer.c | 6 +- common/libraries/drivers/drv_hwtimer.h | 2 +- common/libraries/drivers/drv_i2c.c | 16 +- common/libraries/drivers/drv_i2c.h | 2 +- common/libraries/drivers/drv_i2s.c | 4 +- common/libraries/drivers/drv_i2s.h | 2 +- common/libraries/drivers/drv_mcan.c | 728 + common/libraries/drivers/drv_mcan.h | 12 + common/libraries/drivers/drv_pdm.c | 2 +- common/libraries/drivers/drv_pdm.h | 2 +- common/libraries/drivers/drv_pwm.c | 21 +- common/libraries/drivers/drv_pwm.h | 2 +- common/libraries/drivers/drv_rtc.c | 14 +- common/libraries/drivers/drv_rtc.h | 4 +- common/libraries/drivers/drv_sdio.c | 58 +- common/libraries/drivers/drv_sdio.h | 4 +- common/libraries/drivers/drv_spi.c | 323 +- common/libraries/drivers/drv_spi.h | 3 +- common/libraries/drivers/drv_uart.c | 2 +- common/libraries/drivers/drv_uart.h | 2 +- common/libraries/drivers/drv_uart_v2.c | 51 +- common/libraries/drivers/drv_uart_v2.h | 8 +- common/libraries/drivers/drv_usb.c | 2 +- common/libraries/drivers/drv_usb.h | 2 +- common/libraries/drivers/drv_wdt.c | 2 +- common/libraries/drivers/drv_wdt.h | 2 +- common/libraries/hpm_sdk/CHANGELOG.md | 223 +- common/libraries/hpm_sdk/CMakeLists.txt | 72 +- common/libraries/hpm_sdk/LICENSE | 2 +- common/libraries/hpm_sdk/README.md | 51 +- common/libraries/hpm_sdk/README_zh.md | 52 +- common/libraries/hpm_sdk/SConscript | 11 +- common/libraries/hpm_sdk/VERSION | 6 +- common/libraries/hpm_sdk/arch/CMakeLists.txt | 2 +- .../libraries/hpm_sdk/arch/riscv/riscv_core.h | 27 +- .../libraries/hpm_sdk/boards/CMakeLists.txt | 2 +- .../hpm_sdk/boards/hpm6300evk/CMakeLists.txt | 2 +- .../hpm_sdk/boards/hpm6300evk/README.md | 75 - .../hpm_sdk/boards/hpm6300evk/README_zh.md | 73 - .../hpm_sdk/boards/hpm6300evk/SConscript | 14 - .../hpm_sdk/boards/hpm6300evk/board.c | 149 +- .../hpm_sdk/boards/hpm6300evk/board.h | 57 +- .../hpm_sdk/boards/hpm6300evk/pinmux.c | 52 +- .../hpm_sdk/boards/hpm6300evk/pinmux.h | 4 +- .../hpm_sdk/boards/hpm6750evk/CMakeLists.txt | 16 +- .../hpm_sdk/boards/hpm6750evk/README.md | 104 - .../hpm_sdk/boards/hpm6750evk/README_zh.md | 107 - .../hpm_sdk/boards/hpm6750evk/SConscript | 14 - .../hpm_sdk/boards/hpm6750evk/board.c | 309 +- .../hpm_sdk/boards/hpm6750evk/board.h | 116 +- .../hpm_sdk/boards/hpm6750evk/pinmux.c | 89 +- .../hpm_sdk/boards/hpm6750evk/pinmux.h | 8 +- .../boards/hpm6750evkmini/CMakeLists.txt | 16 +- .../hpm_sdk/boards/hpm6750evkmini/README.md | 86 - .../boards/hpm6750evkmini/README_zh.md | 86 - .../hpm_sdk/boards/hpm6750evkmini/SConscript | 14 - .../hpm_sdk/boards/hpm6750evkmini/board.c | 272 +- .../hpm_sdk/boards/hpm6750evkmini/board.h | 111 +- .../hpm_sdk/boards/hpm6750evkmini/pinmux.c | 157 +- .../hpm_sdk/boards/hpm6750evkmini/pinmux.h | 5 +- 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.../components/camera/mt9m114/CMakeLists.txt | 6 + .../camera/mt9m114/hpm_camera_mt9m114.c | 43 + .../components/camera/mt9m114/hpm_mt9m114.c | 484 + .../components/camera/mt9m114/hpm_mt9m114.h | 867 + .../camera/ov5640/hpm_camera_ov5640.c | 10 + .../components/camera/ov5640/hpm_ov5640.c | 9 +- .../camera/ov7725/hpm_camera_ov7725.c | 10 + .../components/camera/ov7725/hpm_ov7725.c | 13 +- .../components/codec/wm8960/hpm_wm8960.c | 6 +- .../debug_console/hpm_debug_console.c | 2 +- .../debug_console/hpm_debug_console.h | 6 +- .../components/enet_phy/CMakeLists.txt | 9 + .../enet_phy/dp83848/CMakeLists.txt | 6 +- .../components/enet_phy/dp83848/hpm_dp83848.c | 71 +- .../components/enet_phy/dp83848/hpm_dp83848.h | 37 +- .../enet_phy/dp83848/hpm_dp83848_regs.h | 1590 +- .../enet_phy/dp83867/CMakeLists.txt | 7 +- .../components/enet_phy/dp83867/hpm_dp83867.c | 138 +- .../components/enet_phy/dp83867/hpm_dp83867.h | 48 +- .../enet_phy/dp83867/hpm_dp83867_regs.h | 2556 +- .../components/enet_phy/hpm_enet_phy.h | 34 + .../components/enet_phy/hpm_enet_phy_common.h | 30 +- .../enet_phy/rtl8201/CMakeLists.txt | 6 +- .../components/enet_phy/rtl8201/hpm_rtl8201.c | 84 +- .../components/enet_phy/rtl8201/hpm_rtl8201.h | 36 +- .../enet_phy/rtl8201/hpm_rtl8201_regs.h | 434 +- .../enet_phy/rtl8211/CMakeLists.txt | 7 +- .../components/enet_phy/rtl8211/hpm_rtl8211.c | 94 +- .../components/enet_phy/rtl8211/hpm_rtl8211.h | 36 +- .../enet_phy/rtl8211/hpm_rtl8211_regs.h | 423 +- .../components/ipc_event_mgr/CMakeLists.txt | 7 + .../ipc_event_mgr/hpm_ipc_event_mgr.c | 97 + .../ipc_event_mgr/hpm_ipc_event_mgr.h | 94 + .../ipc_event_mgr/mbx/CMakeLists.txt | 6 + .../mbx/hpm_ipc_event_mgr_mbx_config.h | 21 + .../mbx/hpm_ipc_event_mgr_mbx_internal.c | 76 + .../mbx/hpm_ipc_event_mgr_mbx_internal.h | 47 + .../hpm_sdk/components/serial_nor/sfdp_def.h | 226 +- .../hpm_sdk/components/spi/hpm_spi.c | 15 +- .../hpm_sdk/components/spi/hpm_spi.h | 3 + .../components/touch/gt911/hpm_gt911.c | 7 +- .../libraries/hpm_sdk/drivers/CMakeLists.txt | 5 + .../hpm_sdk/drivers/inc/hpm_adc12_drv.h | 23 +- .../hpm_sdk/drivers/inc/hpm_adc16_drv.h | 34 +- .../hpm_sdk/drivers/inc/hpm_cam_drv.h | 22 + .../hpm_sdk/drivers/inc/hpm_can_drv.h | 12 +- .../hpm_sdk/drivers/inc/hpm_common.h | 2 +- .../hpm_sdk/drivers/inc/hpm_crc_drv.h | 240 + .../hpm_sdk/drivers/inc/hpm_csr_drv.h | 102 + .../hpm_sdk/drivers/inc/hpm_display_common.h | 3 + .../hpm_sdk/drivers/inc/hpm_dma_drv.h | 21 +- .../hpm_sdk/drivers/inc/hpm_enet_drv.h | 177 +- .../hpm_sdk/drivers/inc/hpm_gptmr_drv.h | 11 +- .../hpm_sdk/drivers/inc/hpm_i2c_drv.h | 68 +- .../hpm_sdk/drivers/inc/hpm_i2s_drv.h | 28 +- .../hpm_sdk/drivers/inc/hpm_lin_drv.h | 340 + .../hpm_sdk/drivers/inc/hpm_mcan_drv.h | 1577 + .../hpm_sdk/drivers/inc/hpm_pla_drv.h | 550 + .../hpm_sdk/drivers/inc/hpm_pwm_drv.h | 226 +- .../hpm_sdk/drivers/inc/hpm_qei_drv.h | 19 +- .../hpm_sdk/drivers/inc/hpm_rtc_drv.h | 3 +- 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| 2 +- .../hpm_sdk/soc/HPM6280/hpm_clock_drv.c | 498 + .../hpm_sdk/soc/HPM6280/hpm_clock_drv.h | 324 + .../hpm_sdk/soc/HPM6280/hpm_csr_regs.h | 6512 + .../hpm_sdk/soc/HPM6280/hpm_dmamux_src.h | 88 + .../hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h | 105 + .../hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h | 29 + .../hpm_sdk/soc/HPM6280/hpm_interrupt.h | 1018 + .../hpm_sdk/soc/HPM6280/hpm_ioc_regs.h | 311 + .../libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h | 958 + .../hpm_sdk/soc/HPM6280/hpm_l1c_drv.c | 135 + .../hpm_sdk/soc/HPM6280/hpm_l1c_drv.h | 485 + .../hpm_sdk/soc/HPM6280/hpm_mcan_soc.h | 91 + .../libraries/hpm_sdk/soc/HPM6280/hpm_misc.h | 38 + .../hpm_sdk/soc/HPM6280/hpm_otp_drv.c | 181 + .../hpm_sdk/soc/HPM6280/hpm_otp_drv.h | 137 + .../inc => soc/HPM6280}/hpm_pcfg_drv.h | 0 .../hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h | 925 + .../soc/{ip => HPM6280}/hpm_pgpr_regs.h | 2 +- .../hpm_sdk/soc/HPM6280/hpm_plic_drv.h | 186 + .../hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h | 61 + .../inc => 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.../hw/bsp/fomu/regions.ld | 0 .../hw/bsp/frdm_k32l2b/board.h | 0 .../hw/bsp/frdm_k32l2b/board.mk | 0 .../hw/bsp/frdm_k32l2b/frdm_k32l2b.c | 0 .../hw/bsp/frdm_kl25z/board.mk | 0 .../hw/bsp/frdm_kl25z/frdm_kl25z.c | 0 .../boards/sipeed_longan_nano/board.h | 0 .../boards/sipeed_longan_nano/board.mk | 0 .../hw/bsp/gd32vf103/family.c | 0 .../hw/bsp/gd32vf103/family.mk | 0 .../hw/bsp/gd32vf103/system_gd32vf103.c | 0 .../bsp/imxrt/boards/mimxrt1010_evk/board.h | 0 .../bsp/imxrt/boards/mimxrt1010_evk/board.mk | 0 .../evkmimxrt1010_flexspi_nor_config.c | 0 .../evkmimxrt1010_flexspi_nor_config.h | 0 .../bsp/imxrt/boards/mimxrt1015_evk/board.h | 0 .../bsp/imxrt/boards/mimxrt1015_evk/board.mk | 0 .../evkmimxrt1015_flexspi_nor_config.c | 0 .../evkmimxrt1015_flexspi_nor_config.h | 0 .../bsp/imxrt/boards/mimxrt1020_evk/board.h | 0 .../bsp/imxrt/boards/mimxrt1020_evk/board.mk | 0 .../evkmimxrt1020_flexspi_nor_config.c | 0 .../evkmimxrt1020_flexspi_nor_config.h | 0 .../bsp/imxrt/boards/mimxrt1050_evkb/board.h | 0 .../bsp/imxrt/boards/mimxrt1050_evkb/board.mk | 0 .../evkbimxrt1050_flexspi_nor_config.c | 0 .../evkbimxrt1050_flexspi_nor_config.h | 0 .../bsp/imxrt/boards/mimxrt1060_evk/board.h | 0 .../bsp/imxrt/boards/mimxrt1060_evk/board.mk | 0 .../evkmimxrt1060_flexspi_nor_config.c | 0 .../evkmimxrt1060_flexspi_nor_config.h | 0 .../bsp/imxrt/boards/mimxrt1064_evk/board.h | 0 .../bsp/imxrt/boards/mimxrt1064_evk/board.mk | 0 .../evkmimxrt1064_flexspi_nor_config.c | 0 .../evkmimxrt1064_flexspi_nor_config.h | 0 .../hw/bsp/imxrt/boards/teensy_40/board.h | 0 .../hw/bsp/imxrt/boards/teensy_40/board.mk | 0 .../teensy_40/teensy40_flexspi_nor_config.c | 0 .../teensy_40/teensy40_flexspi_nor_config.h | 0 .../hw/bsp/imxrt/family.c | 0 .../hw/bsp/imxrt/family.mk | 0 .../hw/bsp/kuiic/K32L2B31xxxxA_flash.ld | 0 .../hw/bsp/kuiic/board.h | 0 .../hw/bsp/kuiic/board.mk | 0 .../hw/bsp/kuiic/kuiic.c | 0 .../bsp/lpc15/boards/lpcxpresso1549/board.h | 0 .../bsp/lpc15/boards/lpcxpresso1549/board.mk | 0 .../lpc15/boards/lpcxpresso1549/lpc1549.ld | 0 .../hw/bsp/lpc15/family.c | 0 .../hw/bsp/lpc15/family.mk | 0 .../bsp/lpc18/boards/lpcxpresso18s37/board.h | 0 .../bsp/lpc18/boards/lpcxpresso18s37/board.mk | 0 .../lpc18/boards/lpcxpresso18s37/lpc1837.ld | 0 .../hw/bsp/lpc18/boards/mcb1800/board.h | 0 .../hw/bsp/lpc18/boards/mcb1800/board.mk | 0 .../hw/bsp/lpc18/boards/mcb1800/lpc1857.ld | 0 .../hw/bsp/lpc18/family.c | 0 .../hw/bsp/lpc18/family.mk | 0 .../bsp/lpc54/boards/lpcxpresso54114/board.h | 0 .../bsp/lpc54/boards/lpcxpresso54114/board.mk | 0 .../bsp/lpc54/boards/lpcxpresso54628/board.h | 0 .../bsp/lpc54/boards/lpcxpresso54628/board.mk | 0 .../hw/bsp/lpc54/family.c | 0 .../hw/bsp/lpc54/family.mk | 0 .../LPC55S69_cm33_core0_uf2.ld | 0 .../lpc55/boards/double_m33_express/board.h | 0 .../lpc55/boards/double_m33_express/board.mk | 0 .../bsp/lpc55/boards/lpcxpresso55s28/board.h | 0 .../bsp/lpc55/boards/lpcxpresso55s28/board.mk | 0 .../bsp/lpc55/boards/lpcxpresso55s69/board.h | 0 .../bsp/lpc55/boards/lpcxpresso55s69/board.mk | 0 .../hw/bsp/lpc55/boards/mcu_link/board.h | 0 .../hw/bsp/lpc55/boards/mcu_link/board.mk | 0 .../hw/bsp/lpc55/family.c | 0 .../hw/bsp/lpc55/family.mk | 0 .../hw/bsp/lpcxpresso11u37/board.mk | 0 .../hw/bsp/lpcxpresso11u37/lpc11u37.ld | 0 .../hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c | 0 .../hw/bsp/lpcxpresso11u68/board.mk | 0 .../hw/bsp/lpcxpresso11u68/lpc11u68.ld | 0 .../hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c | 0 .../hw/bsp/lpcxpresso1347/board.mk | 0 .../hw/bsp/lpcxpresso1347/lpc1347.ld | 0 .../hw/bsp/lpcxpresso1347/lpcxpresso1347.c | 0 .../hw/bsp/lpcxpresso1769/board.mk | 0 .../hw/bsp/lpcxpresso1769/lpc1769.ld | 0 .../hw/bsp/lpcxpresso1769/lpcxpresso1769.c | 0 .../hw/bsp/lpcxpresso51u68/board.mk | 0 .../hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c | 0 .../hw/bsp/mbed1768/board.mk | 0 .../hw/bsp/mbed1768/lpc1768.ld | 0 .../hw/bsp/mbed1768/mbed1768.c | 0 .../bsp/mm32/boards/mm32f327x_mb39/board.mk | 0 .../bsp/mm32/boards/mm32f327x_mb39/flash.ld | 0 .../boards/mm32f327x_mb39/mm32f327x_mb39.c | 0 .../hw/bsp/mm32/family.mk | 0 .../msp430/boards/msp_exp430f5529lp/board.h | 0 .../hw/bsp/msp430/family.c | 0 .../hw/bsp/msp430/family.mk | 0 .../msp432e4/boards/msp_exp432e401y/board.h | 0 .../hw/bsp/msp432e4/family.c | 0 .../hw/bsp/msp432e4/family.mk | 0 .../hw/bsp/ngx4330/board.mk | 0 .../hw/bsp/ngx4330/ngx4330.c | 0 .../hw/bsp/ngx4330/ngx4330.ld | 0 .../hw/bsp/nrf/boards/adafruit_clue/board.h | 0 .../hw/bsp/nrf/boards/adafruit_clue/board.mk | 0 .../boards/adafruit_clue/nrf52840_s140_v6.ld | 0 .../arduino_nano33_ble/arduino_nano33_ble.ld | 0 .../bsp/nrf/boards/arduino_nano33_ble/board.h | 0 .../nrf/boards/arduino_nano33_ble/board.mk | 0 .../circuitplayground_bluefruit/board.h | 0 .../circuitplayground_bluefruit/board.mk | 0 .../nrf52840_s140_v6.ld | 0 .../boards/feather_nrf52840_express/board.h | 0 .../boards/feather_nrf52840_express/board.mk | 0 .../nrf52840_s140_v6.ld | 0 .../nrf/boards/feather_nrf52840_sense/board.h | 0 .../boards/feather_nrf52840_sense/board.mk | 0 .../nrf52840_s140_v6.ld | 0 .../bsp/nrf/boards/itsybitsy_nrf52840/board.h | 0 .../nrf/boards/itsybitsy_nrf52840/board.mk | 0 .../itsybitsy_nrf52840/nrf52840_s140_v6.ld | 0 .../nrf/boards/nrf52840_mdk_dongle/board.h | 0 .../nrf/boards/nrf52840_mdk_dongle/board.mk | 0 .../nrf52840_mdk_dongle.ld | 0 .../hw/bsp/nrf/boards/pca10056/board.h | 0 .../hw/bsp/nrf/boards/pca10056/board.mk | 0 .../hw/bsp/nrf/boards/pca10059/board.h | 0 .../hw/bsp/nrf/boards/pca10059/board.mk | 0 .../hw/bsp/nrf/boards/pca10059/pca10059.ld | 0 .../hw/bsp/nrf/boards/pca10100/board.h | 0 .../hw/bsp/nrf/boards/pca10100/board.mk | 0 .../bsp/nrf/boards/raytac_mdbt50q_rx/board.h | 0 .../bsp/nrf/boards/raytac_mdbt50q_rx/board.mk | 0 .../hw/bsp/nrf/family.c | 0 .../hw/bsp/nrf/family.mk | 0 .../hw/bsp/nutiny_nuc121s/board.mk | 0 .../hw/bsp/nutiny_nuc121s/nuc121_flash.ld | 0 .../hw/bsp/nutiny_nuc121s/nutiny_nuc121.c | 0 .../hw/bsp/nutiny_nuc125s/board.mk | 0 .../hw/bsp/nutiny_nuc125s/nuc125_flash.ld | 0 .../hw/bsp/nutiny_nuc125s/nutiny_nuc125.c | 0 .../hw/bsp/nutiny_nuc126v/board.mk | 0 .../hw/bsp/nutiny_nuc126v/nuc126_flash.ld | 0 .../hw/bsp/nutiny_nuc126v/nutiny_nuc126.c | 0 .../hw/bsp/nutiny_sdk_nuc120/board.mk | 0 .../hw/bsp/nutiny_sdk_nuc120/nuc120_flash.ld | 0 .../bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c | 0 .../hw/bsp/nutiny_sdk_nuc505/board.mk | 0 .../nutiny_sdk_nuc505/nuc505_flashtoram.ld | 0 .../bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c | 0 .../bsp/pic32mz/boards/olimex_emz64/board.mk | 0 .../boards/olimex_emz64/olimex_emz64.c | 0 .../bsp/pic32mz/boards/olimex_hmz144/board.mk | 0 .../boards/olimex_hmz144/olimex_hmz144.c | 0 .../hw/bsp/pic32mz/family.c | 0 .../hw/bsp/pic32mz/family.mk | 0 .../hw/bsp/rp2040/board.h | 0 .../adafruit_feather_rp2040/board.cmake | 0 .../adafruit_itsybitsy_rp2040/board.cmake | 0 .../boards/adafruit_qtpy_rp2040/board.cmake | 0 .../hw/bsp/rp2040/boards/pico_sdk/board.cmake | 0 .../boards/raspberry_pi_pico/board.cmake | 0 .../hw/bsp/rp2040/family.c | 0 .../hw/bsp/rp2040/family.cmake | 0 .../hw/bsp/rp2040/family.mk | 0 .../hw/bsp/rp2040/pico_sdk_import.cmake | 0 .../hw/bsp/rx/boards/gr_citrus/board.mk | 0 .../hw/bsp/rx/boards/gr_citrus/gr_citrus.c | 0 .../hw/bsp/rx/boards/gr_citrus/hwinit.c | 0 .../hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld | 0 .../hw/bsp/rx/boards/rx65n_target/board.mk | 0 .../hw/bsp/rx/boards/rx65n_target/r5f565ne.ld | 0 .../bsp/rx/boards/rx65n_target/rx65n_target.c | 0 .../hw/bsp/rx/family.mk | 0 .../hw/bsp/samd11/boards/luna_d11/board.h | 0 .../hw/bsp/samd11/boards/luna_d11/board.mk | 0 .../boards/luna_d11/samd11d14am_flash.ld | 0 .../bsp/samd11/boards/samd11_xplained/board.h | 0 .../samd11/boards/samd11_xplained/board.mk | 0 .../samd11_xplained/samd11d14am_flash.ld | 0 .../hw/bsp/samd11/family.c | 0 .../hw/bsp/samd11/family.mk | 0 .../bsp/samd21/boards/atsamd21_xpro/board.h | 0 .../bsp/samd21/boards/atsamd21_xpro/board.mk | 0 .../boards/atsamd21_xpro/samd21j18a_flash.ld | 0 .../boards/circuitplayground_express/board.h | 0 .../boards/circuitplayground_express/board.mk | 0 .../circuitplayground_express.ld | 0 .../bsp/samd21/boards/curiosity_nano/board.h | 0 .../bsp/samd21/boards/curiosity_nano/board.mk | 0 .../boards/curiosity_nano/samd21g17a_flash.ld | 0 .../samd21/boards/feather_m0_express/board.h | 0 .../samd21/boards/feather_m0_express/board.mk | 0 .../feather_m0_express/feather_m0_express.ld | 0 .../hw/bsp/samd21/boards/itsybitsy_m0/board.h | 0 .../bsp/samd21/boards/itsybitsy_m0/board.mk | 0 .../boards/itsybitsy_m0/itsybitsy_m0.ld | 0 .../hw/bsp/samd21/boards/luna_d21/board.h | 0 .../hw/bsp/samd21/boards/luna_d21/board.mk | 0 .../boards/luna_d21/samd21g18a_flash.ld | 0 .../samd21/boards/metro_m0_express/board.h | 0 .../samd21/boards/metro_m0_express/board.mk | 0 .../metro_m0_express/metro_m0_express.ld | 0 .../hw/bsp/samd21/boards/qtpy/board.h | 0 .../hw/bsp/samd21/boards/qtpy/board.mk | 0 .../hw/bsp/samd21/boards/qtpy/qtpy.ld | 0 .../bsp/samd21/boards/seeeduino_xiao/board.h | 0 .../bsp/samd21/boards/seeeduino_xiao/board.mk | 0 .../boards/seeeduino_xiao/seeeduino_xiao.ld | 0 .../hw/bsp/samd21/boards/trinket_m0/board.h | 0 .../hw/bsp/samd21/boards/trinket_m0/board.mk | 0 .../samd21/boards/trinket_m0/trinket_m0.ld | 0 .../hw/bsp/samd21/family.c | 0 .../hw/bsp/samd21/family.mk | 0 .../samd51/boards/feather_m4_express/board.h | 0 .../samd51/boards/feather_m4_express/board.mk | 0 .../feather_m4_express/feather_m4_express.ld | 0 .../hw/bsp/samd51/boards/itsybitsy_m4/board.h | 0 .../bsp/samd51/boards/itsybitsy_m4/board.mk | 0 .../boards/itsybitsy_m4/itsybitsy_m4.ld | 0 .../samd51/boards/metro_m4_express/board.h | 0 .../samd51/boards/metro_m4_express/board.mk | 0 .../metro_m4_express/metro_m4_express.ld | 0 .../hw/bsp/samd51/boards/pybadge/board.h | 0 .../hw/bsp/samd51/boards/pybadge/board.mk | 0 .../hw/bsp/samd51/boards/pybadge/pybadge.ld | 0 .../hw/bsp/samd51/boards/pyportal/board.h | 0 .../hw/bsp/samd51/boards/pyportal/board.mk | 0 .../hw/bsp/samd51/boards/pyportal/pyportal.ld | 0 .../hw/bsp/samd51/family.c | 0 .../hw/bsp/samd51/family.mk | 0 .../hw/bsp/same54xplainedpro/board.mk | 0 .../bsp/same54xplainedpro/same54p20a_flash.ld | 0 .../bsp/same54xplainedpro/same54p20a_sram.ld | 0 .../bsp/same54xplainedpro/same54xplainedpro.c | 0 .../hw/bsp/same70_qmtech/board.mk | 0 .../hw/bsp/same70_qmtech/hpl_pmc_config.h | 0 .../hw/bsp/same70_qmtech/hpl_usart_config.h | 0 .../hw/bsp/same70_qmtech/hpl_xdmac_config.h | 0 .../bsp/same70_qmtech/peripheral_clk_config.h | 0 .../hw/bsp/same70_qmtech/same70_qmtech.c | 0 .../hw/bsp/same70_xplained/board.mk | 0 .../hw/bsp/same70_xplained/hpl_pmc_config.h | 0 .../hw/bsp/same70_xplained/hpl_usart_config.h | 0 .../hw/bsp/same70_xplained/hpl_xdmac_config.h | 0 .../same70_xplained/peripheral_clk_config.h | 0 .../hw/bsp/same70_xplained/same70_xplained.c | 0 .../hw/bsp/samg55xplained/board.mk | 0 .../hw/bsp/samg55xplained/hpl_usart_config.h | 0 .../samg55xplained/peripheral_clk_config.h | 0 .../hw/bsp/samg55xplained/samg55j19_flash.ld | 0 .../hw/bsp/samg55xplained/samg55xplained.c | 0 .../bsp/saml2x/boards/atsaml21_xpro/board.h | 0 .../bsp/saml2x/boards/atsaml21_xpro/board.mk | 0 .../boards/atsaml21_xpro/saml21j18b_flash.ld | 0 .../bsp/saml2x/boards/saml22_feather/board.h | 0 .../bsp/saml2x/boards/saml22_feather/board.mk | 0 .../boards/saml22_feather/saml22_feather.ld | 0 .../bsp/saml2x/boards/sensorwatch_m0/board.h | 0 .../bsp/saml2x/boards/sensorwatch_m0/board.mk | 0 .../boards/sensorwatch_m0/sensorwatch_m0.ld | 0 .../hw/bsp/saml2x/family.c | 0 .../hw/bsp/saml2x/family.mk | 0 .../hw/bsp/sltb009a/board.mk | 0 .../hw/bsp/sltb009a/sltb009a.c | 0 .../hw/bsp/spresense/board.mk | 0 .../hw/bsp/spresense/board_spresense.c | 0 .../stm32f0/boards/stm32f070rbnucleo/board.h | 0 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projects/usb_device_generic_hid/packages/{TinyUSB-v0.13.0 => TinyUSB-v0.13.1}/tools/usb_drivers/tinyusb_win_usbser.inf (100%) rename projects/usb_device_generic_hid/packages/{TinyUSB-v0.13.0 => TinyUSB-v0.13.1}/version.yml (100%) diff --git a/.gitattributes b/.gitattributes deleted file mode 100644 index f4068013..00000000 --- a/.gitattributes +++ /dev/null @@ -1,8 +0,0 @@ -.gitattributes export-ignore -.gitignore export-ignore -.gitmodules export-ignore - -common/.gitattributes export-ignore -common/.gitignore export-ignore -common/README.md export-ignore -common/README_zh.md export-ignore diff --git a/.gitignore b/.gitignore index a4f2015c..4cb89876 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,6 @@ # Prerequisites *.d - +.sconsign.dblite # Object files *.o *.ko diff --git a/ChangeLog.md b/ChangeLog.md index 5776231e..0abc1148 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,5 +1,20 @@ # Change Log +## v1.1.0 +- Integrated hpm_sdk v1.1.0 + - Note: + - the docs, middleware, scripts, samples folder in SDK root directory were removed +- Fixed: + - typos in the drv_i2c.c + - hw_timer cannot work due to SDK driver update + - RT-Thread Studio project compiling error after enabling C++ support + - iperf performance is low if working as client mode + - ethernet throughput is not optimized + - adc driver may return incorrect value + - pwm channel may not work as expected + - uart_dma_demo doesn't work + - eMMC to TF card doesn't work + ## v1.0.0 - Integrated the SDK v1.0.0 release - Note: diff --git a/ChangeLog_zh.md b/ChangeLog_zh.md index eaed310b..fb0dc0c4 100644 --- a/ChangeLog_zh.md +++ b/ChangeLog_zh.md @@ -1,7 +1,23 @@ # 更新 +## v1.1.0 -## 1.0.0 +- 整合了hpm_sdk v1.1.0 + - 注： + - SDK根目录下的docs,middleware,samples, scripts等目录被移除 +- 修复： + - drv_i2c.c 中的拼写错误 + - hw_timer 工作异常 + - 开启C++支持后RT-Thread Studio工程编译失败 + - iperf 作为客户端时性能低下 + - 网络性能未优化 + - ADC 驱动可能会返回错误的数据 + - PWM 通道可能会工作不正常 + - uart_dma_demo示例不工作 + - eMMC转TF卡不工作 + + +## v1.0.0 - 整合了SDK v1.0.0 - 注： - SDK根目录下的doc, middleware,samples,cmake目录被删除 @@ -18,7 +34,7 @@ - usb_host_msc_udisk -## 0.7.0 +## v0.7.0 - 整合了SDK v0.12.1 - 注： - SDK根目录下的doc, middleware,samples,cmake 目录被删除 diff --git a/HPMicro-HPM6300EVK.yaml b/HPMicro-HPM6300EVK.yaml index 699960e2..b06853de 100644 --- a/HPMicro-HPM6300EVK.yaml +++ b/HPMicro-HPM6300EVK.yaml @@ -49,7 +49,7 @@ features_zh: - '调试接口: 板载FT2232' pkg_type: Board_Support_Packages pkg_vendor: HPMicro -pkg_version: 1.0.0 +pkg_version: 1.1.0 template_projects: - project_name: blink_led diff --git a/board/board.c b/board/board.c index 4fff2eeb..2b85b31d 100644 --- a/board/board.c +++ b/board/board.c @@ -91,7 +91,7 @@ ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATU void board_init_console(void) { -#if BOARD_CONSOLE_TYPE == console_type_uart +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART console_config_t cfg; /* Configure the UART clock to 24MHz */ @@ -350,10 +350,6 @@ void board_init_clock(void) clock_add_to_group(clock_gptmr1, 0); clock_add_to_group(clock_gptmr2, 0); clock_add_to_group(clock_gptmr3, 0); - clock_add_to_group(clock_uart0, 0); - clock_add_to_group(clock_uart1, 0); - clock_add_to_group(clock_uart2, 0); - clock_add_to_group(clock_uart3, 0); clock_add_to_group(clock_i2c0, 0); clock_add_to_group(clock_i2c1, 0); clock_add_to_group(clock_i2c2, 0); @@ -592,6 +588,7 @@ void _init_ext_ram(void) void board_init_sd_pins(SDXC_Type *ptr) { init_sdxc_pins(ptr, false); + init_sdxc_card_detection_pin(ptr); } uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) @@ -643,6 +640,11 @@ void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) /* This feature is not supported */ } +void board_sd_power_switch(SDXC_Type *ptr, bool on_off) +{ + /* This feature is not supported */ +} + bool board_sd_detect_card(SDXC_Type *ptr) { return sdxc_is_card_inserted(ptr); @@ -707,12 +709,15 @@ uint32_t board_init_uart_clock(UART_Type *ptr) uint32_t freq = 0U; if (ptr == HPM_UART0) { clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + clock_add_to_group(clock_uart0, 0); freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART1) { clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); + clock_add_to_group(clock_uart1, 0); freq = clock_get_frequency(clock_uart1); } else if (ptr == HPM_UART2) { clock_set_source_divider(clock_uart2, clk_src_osc24m, 1); + clock_add_to_group(clock_uart2, 0); freq = clock_get_frequency(clock_uart2); } else { /* Not supported */ diff --git a/board/board.h b/board/board.h index 03f6a588..7410b1b2 100644 --- a/board/board.h +++ b/board/board.h @@ -41,10 +41,10 @@ #define BOARD_APP_UART_CLK_NAME clock_uart0 #ifndef BOARD_CONSOLE_TYPE -#define BOARD_CONSOLE_TYPE console_type_uart +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif -#if BOARD_CONSOLE_TYPE == console_type_uart +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 #define BOARD_CONSOLE_BASE HPM_UART0 @@ -370,6 +370,7 @@ void board_init_sd_pins(SDXC_Type *ptr); uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); bool board_sd_detect_card(SDXC_Type *ptr); +void board_sd_power_switch(SDXC_Type *ptr, bool on_off); void board_init_usb_pins(void); void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); diff --git a/board/linker_scripts/flash_rtt.ld b/board/linker_scripts/flash_rtt.ld index e6bc1456..faecf039 100644 --- a/board/linker_scripts/flash_rtt.ld +++ b/board/linker_scripts/flash_rtt.ld @@ -180,10 +180,12 @@ SECTIONS PROVIDE(__finit_array_end = .); . = ALIGN(8); + PROVIDE(__ctors_start__ = .); KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); . = ALIGN(8); KEEP(*crtbegin*.o(.dtors)) diff --git a/board/linker_scripts/flash_rtt_enet.ld b/board/linker_scripts/flash_rtt_enet.ld index 52839eeb..38365bde 100644 --- a/board/linker_scripts/flash_rtt_enet.ld +++ b/board/linker_scripts/flash_rtt_enet.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021 - 2022 hpmicro + * Copyright 2021-2022 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,16 +9,16 @@ STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 1M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 256K SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01100000, LENGTH = NONCACHEABLE_SIZE + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = NONCACHEABLE_SIZE } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -84,7 +84,11 @@ SECTIONS . = ALIGN(8); __ramfunc_end__ = .; } > AXI_SRAM - + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { . = ALIGN(8); *(.text) @@ -182,10 +186,12 @@ SECTIONS PROVIDE(__finit_array_end = .); . = ALIGN(8); + PROVIDE(__ctors_start__ = .); KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); . = ALIGN(8); KEEP(*crtbegin*.o(.dtors)) diff --git a/board/linker_scripts/ram_rtt.ld b/board/linker_scripts/ram_rtt.ld index 391235bd..df2307bc 100644 --- a/board/linker_scripts/ram_rtt.ld +++ b/board/linker_scripts/ram_rtt.ld @@ -27,7 +27,7 @@ SECTIONS . = ALIGN(8); KEEP(*(.start)) } > AXI_SRAM - + .vectors : { . = ALIGN(8); KEEP(*(.isr_vector)) @@ -133,10 +133,12 @@ SECTIONS PROVIDE(__finit_array_end = .); . = ALIGN(8); + PROVIDE(__ctors_start__ = .); KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); . = ALIGN(8); KEEP(*crtbegin*.o(.dtors)) @@ -158,7 +160,7 @@ SECTIONS . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ . = ALIGN(8); __noncacheable_init_start__ = .; diff --git a/board/linker_scripts/ram_rtt_enet.ld b/board/linker_scripts/ram_rtt_enet.ld new file mode 100644 index 00000000..1abe2970 --- /dev/null +++ b/board/linker_scripts/ram_rtt_enet.ld @@ -0,0 +1,218 @@ +/* + * Copyright 2021 - 2022 hpmicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + /* It's alias address of core0 ILM+DLM, but accessing via system bus */ + CORE0_LM_SLV (wx) : ORIGIN = 0x1040000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE + NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > AXI_SRAM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > AXI_SRAM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE + __noncacheable_start__ = ORIGIN(NONCACHEABLE); + __noncacheable_end__ = ORIGIN(NONCACHEABLE) + LENGTH(NONCACHEABLE); + + .bss : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .stack : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + } > DLM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > SDRAM + + .heap : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > SDRAM +} diff --git a/board/pinmux.c b/board/pinmux.c index ad981801..1f1f8d77 100644 --- a/board/pinmux.c +++ b/board/pinmux.c @@ -241,6 +241,23 @@ void init_can_pins(CAN_Type *ptr) } } +void init_sdxc_power_pin(SDXC_Type *ptr) +{ + +} + +void init_sdxc_vsel_pin(SDXC_Type *ptr) +{ + +} + +void init_sdxc_card_detection_pin(SDXC_Type *ptr) +{ + /* SDXC0.CD */ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); +} + void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) { uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); @@ -255,10 +272,6 @@ void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = func_ctl; HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = pad_ctl; - /* SDXC0.CD */ - HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = func_ctl; - HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = pad_ctl; - /* SDXC0.DATA0 */ HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = func_ctl; HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = pad_ctl; diff --git a/board/pinmux.h b/board/pinmux.h index 10022a88..5dd98741 100644 --- a/board/pinmux.h +++ b/board/pinmux.h @@ -1,5 +1,5 @@ /* - *Copyright (c) 2022 HPMicro + *Copyright (c) 2022-2023 HPMicro * *SPDX-License-Identifier: BSD-3-Clause * @@ -28,6 +28,9 @@ void init_adc_pins(void); void init_dac_pins(DAC_Type *ptr); void init_usb_pins(void); void init_can_pins(CAN_Type *ptr); +void init_sdxc_power_pin(SDXC_Type *ptr); +void init_sdxc_vsel_pin(SDXC_Type *ptr); +void init_sdxc_card_detection_pin(SDXC_Type *ptr); void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); diff --git a/common/.gitattributes b/common/.gitattributes deleted file mode 100644 index d1564d72..00000000 --- a/common/.gitattributes +++ /dev/null @@ -1,2 +0,0 @@ -.gitattributes export-ignore -.gitignore export-ignore \ No newline at end of file diff --git a/common/.gitignore b/common/.gitignore deleted file mode 100644 index 87f056ac..00000000 --- a/common/.gitignore +++ /dev/null @@ -1,64 +0,0 @@ -# Prerequisites -*.d - -# Object files -*.o -*.ko -*.obj -*.elf - -# Linker output -*.ilk -*.map -*.exp - -# Precompiled Headers -*.gch -*.pch - -# Libraries -*.lib -*.a -*.la -*.lo - -# Shared objects (inc. Windows DLLs) -*.dll -*.so -*.so.* -*.dylib - -# Executables -*.exe -*.out -*.app -*.i*86 -*.x86_64 -*.hex - -# Debug files -*.dSYM/ -*.su -*.idb -*.pdb - -# Kernel Module Compile Results -*.mod* -*.cmd -.tmp_versions/ -modules.order -Module.symvers -Mkfile.old -dkms.conf - -# Paython cache -*.pyc - -# Scons cache -*.dbsqlite - -# hpm_sdk docs -libraries/hpm_sdk/**/doc -libraries/hpm_sdk/**/docs -libraries/hpm_sdk/**/test -*.yaml \ No newline at end of file diff --git a/common/libraries/drivers/SConscript b/common/libraries/drivers/SConscript index a58760f3..1eae2a51 100644 --- a/common/libraries/drivers/SConscript +++ b/common/libraries/drivers/SConscript @@ -34,6 +34,9 @@ if GetDepend('BSP_USING_GPTMR'): if GetDepend('BSP_USING_CAN'): src += ['drv_can.c'] +if GetDepend('BSP_USING_MCAN'): + src += ['drv_mcan.c'] + if GetDepend('BSP_USING_UART'): if GetDepend(['RT_USING_SERIAL_V2']): src += ['drv_uart_v2.c'] @@ -55,6 +58,9 @@ if GetDepend('BSP_USING_PDM'): if GetDepend('BSP_USING_I2S'): src += ['drv_i2s.c'] +if GetDepend('BSP_USING_MCAN'): + src += ['drv_mcan.c'] + path = [cwd] diff --git a/common/libraries/drivers/drv_adc.c b/common/libraries/drivers/drv_adc.c index b9b308e3..2a4e2da1 100644 --- a/common/libraries/drivers/drv_adc.c +++ b/common/libraries/drivers/drv_adc.c @@ -1,11 +1,7 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause - * - * Change Logs: - * Date Author Notes - * 2022-05-08 hpmicro the first version */ #include @@ -111,6 +107,7 @@ static rt_err_t init_adc_config(hpm_rtt_adc *adc) cfg.conv_mode = adc16_conv_mode_oneshot; cfg.adc_clk_div = 3; cfg.sel_sync_ahb = true; + cfg.wait_dis = 0; ret = adc16_init(adc->adc_base, &cfg); if (ret != status_success) { return RT_ERROR; @@ -158,14 +155,16 @@ static rt_err_t hpm_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe RT_ASSERT(device != RT_NULL); hpm_adc_handler = (hpm_rtt_adc *)device->parent.user_data; - ret = init_adc_config(hpm_adc_handler); - if (ret != RT_EOK) { - return RT_ERROR; - } - hpm_adc_handler->channel = channel; - ret = init_channel_config(hpm_adc_handler); - if (ret != RT_EOK) { - return RT_ERROR; + if (enabled == RT_TRUE) { + ret = init_adc_config(hpm_adc_handler); + if (ret != RT_EOK) { + return RT_ERROR; + } + hpm_adc_handler->channel = channel; + ret = init_channel_config(hpm_adc_handler); + if (ret != RT_EOK) { + return RT_ERROR; + } } return RT_EOK; @@ -184,7 +183,7 @@ static rt_err_t hpm_get_adc_value(struct rt_adc_device *device, rt_uint32_t chan hpm_adc_handler.channel = channel; #ifdef BSP_USING_ADC12 adc12_get_oneshot_result(hpm_adc_handler.adc_base, hpm_adc_handler.channel, &val); - *value = (val >> 4); + *value = val; #endif #ifdef BSP_USING_ADC16 @@ -216,4 +215,4 @@ int rt_hw_adc_init(void) } INIT_BOARD_EXPORT(rt_hw_adc_init); -#endif +#endif /* BSP_USING_ADC */ diff --git a/common/libraries/drivers/drv_adc.h b/common/libraries/drivers/drv_adc.h index ab524bfd..e3f8cc7e 100644 --- a/common/libraries/drivers/drv_adc.h +++ b/common/libraries/drivers/drv_adc.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-05-08 hpmicro the first version + * 2022-05-08 HPMicro the first version */ #ifndef LIBRARIES_DRIVERS_DRV_ADC_H_ #define LIBRARIES_DRIVERS_DRV_ADC_H_ diff --git a/common/libraries/drivers/drv_can.c b/common/libraries/drivers/drv_can.c index b520ce90..4840c1d1 100644 --- a/common/libraries/drivers/drv_can.c +++ b/common/libraries/drivers/drv_can.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021 - 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-05-08 hpmicro the first version + * 2022-05-08 HPMicro the first version */ #include diff --git a/common/libraries/drivers/drv_can.h b/common/libraries/drivers/drv_can.h index 32024811..cc528ec5 100644 --- a/common/libraries/drivers/drv_can.h +++ b/common/libraries/drivers/drv_can.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/drivers/drv_dao.c b/common/libraries/drivers/drv_dao.c index d28423c8..f92b34ae 100644 --- a/common/libraries/drivers/drv_dao.c +++ b/common/libraries/drivers/drv_dao.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/drivers/drv_dao.h b/common/libraries/drivers/drv_dao.h index 3a7915b2..dcd79d66 100644 --- a/common/libraries/drivers/drv_dao.h +++ b/common/libraries/drivers/drv_dao.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/common/libraries/drivers/drv_enet.c b/common/libraries/drivers/drv_enet.c index d108e9c1..cb667bc6 100644 --- a/common/libraries/drivers/drv_enet.c +++ b/common/libraries/drivers/drv_enet.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2021 - 2022 HPMicro + * Copyright (c) 2021 - 2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-01-11 hpmicro First version - * 2022-07-10 hpmicro Driver optimization for multiple instances + * 2022-01-11 HPMicro First version + * 2022-07-10 HPMicro Driver optimization for multiple instances */ #include @@ -24,10 +24,10 @@ __RW enet_rx_desc_t enet0_dma_rx_desc_tab[ENET0_RX_BUFF_COUNT] ; /* Ethernet0 Rx ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_DESC_ADDR_ALIGNMENT) __RW enet_tx_desc_t enet0_dma_tx_desc_tab[ENET0_TX_BUFF_COUNT] ; /* Ethernet0 Tx DMA Descriptor */ -ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT) +ATTR_PLACE_AT_WITH_ALIGNMENT(".fast_ram", ENET_SOC_BUFF_ADDR_ALIGNMENT) __RW uint8_t enet0_rx_buff[ENET0_RX_BUFF_COUNT][ENET0_RX_BUFF_SIZE]; /* Ethernet0 Receive Buffer */ -ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(ENET_SOC_BUFF_ADDR_ALIGNMENT) +ATTR_PLACE_AT_WITH_ALIGNMENT(".fast_ram", ENET_SOC_BUFF_ADDR_ALIGNMENT) __RW uint8_t enet0_tx_buff[ENET0_TX_BUFF_COUNT][ENET0_TX_BUFF_SIZE]; /* Ethernet0 Transmit Buffer */ struct eth_device eth0_dev; @@ -146,18 +146,14 @@ static hpm_enet_t *s_geths[] = { ATTR_WEAK void enet_get_mac_address(uint8_t *mac) { - bool invalid = true; - - uint32_t uuid[(ENET_MAC + (ENET_MAC - 1)) / sizeof(uint32_t)]; + uint32_t uuid[OTP_SOC_UUID_LEN / sizeof(uint32_t)]; for (int i = 0; i < ARRAY_SIZE(uuid); i++) { uuid[i] = otp_read_from_shadow(OTP_SOC_UUID_IDX + i); - if (uuid[i] != 0xFFFFFFFFUL && uuid[i] != 0) { - invalid = false; - } } - if (invalid == false) { + if (!IS_UUID_INVALID(uuid)) { + uuid[0] &= 0xfc; memcpy(mac, &uuid, ENET_MAC); } else { mac[0] = MAC_ADDR0; @@ -169,7 +165,7 @@ ATTR_WEAK void enet_get_mac_address(uint8_t *mac) } } -static hpm_stat_t hpm_enet_init(enet_device *init) +static rt_err_t hpm_enet_init(enet_device *init) { /* Initialize eth controller */ enet_controller_init(init->instance, init->media_interface, &init->desc, &init->mac_config, &init->int_config); @@ -204,6 +200,8 @@ static hpm_stat_t hpm_enet_init(enet_device *init) /* enable irq */ intc_m_enable_irq(init->irq_number); + + return RT_EOK; } static rt_err_t rt_hpm_eth_init(rt_device_t dev) @@ -227,11 +225,16 @@ static rt_err_t rt_hpm_eth_init(rt_device_t dev) enet_dev->mac_config.valid_max_count = 1; /* Initialize MAC and DMA */ - if (hpm_enet_init(enet_dev) == 0) { + if (hpm_enet_init(enet_dev) == 0) + { LOG_D("Ethernet control initialize successfully\n"); + return RT_EOK; + } + else + { + LOG_D("Ethernet control initialize unsuccessfully\n"); + return RT_ERROR; } - - return RT_EOK; } static rt_err_t rt_hpm_eth_open(rt_device_t dev, rt_uint16_t oflag) @@ -296,6 +299,7 @@ static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) dma_tx_desc = tx_desc_list_cur; buffer = (uint8_t *)(dma_tx_desc->tdes2_bm.buffer1); buffer_offset = 0; + rt_tick_t t_start; /* copy frame from pbufs to driver buffers */ for (q = p; q != NULL; q = q->next) @@ -307,6 +311,16 @@ static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) /* Check if the length of data to copy is bigger than Tx buffer size*/ while ((bytes_left_to_copy + buffer_offset) > tx_buff_size) { + /* check DMA own status within timeout */ + t_start = rt_tick_get(); + while (dma_tx_desc->tdes0_bm.own) + { + if (rt_tick_get() - t_start > RT_TICK_PER_SECOND / 100) + { + return ERR_TIMEOUT; + } + } + /* Copy data to Tx buffer*/ SMEMCPY((uint8_t *)((uint8_t *)buffer + buffer_offset), (uint8_t *)((uint8_t *)q->payload + payload_offset), @@ -319,7 +333,7 @@ static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) if (dma_tx_desc->tdes0_bm.own != 0) { LOG_E("DMA tx desc buffer is not valid\n"); - return ERR_USE; + return ERR_BUF; } buffer = (uint8_t *)(dma_tx_desc->tdes2_bm.buffer1); @@ -330,7 +344,18 @@ static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) buffer_offset = 0; } + /* check DMA own status within timeout */ + t_start = rt_tick_get(); + while (dma_tx_desc->tdes0_bm.own) + { + if (rt_tick_get() - t_start > RT_TICK_PER_SECOND / 100) + { + return ERR_TIMEOUT; + } + } + /* Copy the remaining bytes */ + buffer = (void *)sys_address_to_core_local_mem(0, (uint32_t)buffer); SMEMCPY((uint8_t *)((uint8_t *)buffer + buffer_offset), (uint8_t *)((uint8_t *)q->payload + payload_offset), bytes_left_to_copy); @@ -407,7 +432,7 @@ static struct pbuf *rt_hpm_eth_rx(rt_device_t dev) buffer_offset = 0; } /* Copy remaining data in pbuf */ - SMEMCPY((uint8_t *)((uint8_t *)q->payload + payload_offset), (uint8_t *)((uint8_t *)buffer + buffer_offset), bytes_left_to_copy); + q->payload = (void *)sys_address_to_core_local_mem(0, (uint32_t)buffer); buffer_offset = buffer_offset + bytes_left_to_copy; } } @@ -450,7 +475,7 @@ void isr_enet(hpm_enet_t *obj) status = obj->base->DMA_STATUS; if (ENET_DMA_STATUS_GLPII_GET(status)) { - obj->base->DMA_STATUS |= ENET_DMA_STATUS_GLPII_SET(ENET_DMA_STATUS_GLPII_GET(status)); + obj->base->LPI_CSR; } if (ENET_DMA_STATUS_RI_GET(status)) { diff --git a/common/libraries/drivers/drv_enet.h b/common/libraries/drivers/drv_enet.h index d2f94053..7f72ba6d 100644 --- a/common/libraries/drivers/drv_enet.h +++ b/common/libraries/drivers/drv_enet.h @@ -54,6 +54,20 @@ typedef struct _hpm_enet #endif } hpm_enet_t; +#define IS_UUID_INVALID(UUID) (UUID[0] == 0 && \ + UUID[1] == 0 && \ + UUID[2] == 0 && \ + UUID[3] == 0) + +#if ENET_SOC_RGMII_EN +#ifndef ENET0_TX_BUFF_COUNT +#define ENET0_TX_BUFF_COUNT (50U) +#endif + +#ifndef ENET0_RX_BUFF_COUNT +#define ENET0_RX_BUFF_COUNT (60U) +#endif +#else #ifndef ENET0_TX_BUFF_COUNT #define ENET0_TX_BUFF_COUNT (10U) #endif @@ -61,6 +75,7 @@ typedef struct _hpm_enet #ifndef ENET0_RX_BUFF_COUNT #define ENET0_RX_BUFF_COUNT (20U) #endif +#endif #ifndef ENET0_RX_BUFF_SIZE #define ENET0_RX_BUFF_SIZE ENET_MAX_FRAME_SIZE diff --git a/common/libraries/drivers/drv_gpio.c b/common/libraries/drivers/drv_gpio.c index 520dfa18..cde6b8d6 100644 --- a/common/libraries/drivers/drv_gpio.c +++ b/common/libraries/drivers/drv_gpio.c @@ -5,8 +5,8 @@ * * Change Logs: * Date Author Notes - * 2022-01-11 hpmicro First version - * 2022-07-28 hpmicro Fixed compiling warnings + * 2022-01-11 HPMicro First version + * 2022-07-28 HPMicro Fixed compiling warnings */ #include @@ -19,6 +19,7 @@ #include "hpm_gpio_drv.h" #include "hpm_gpiom_drv.h" #include "hpm_clock_drv.h" +#include "hpm_soc_feature.h" typedef struct { @@ -56,7 +57,7 @@ static const gpio_irq_map_t hpm_gpio_irq_map[] = { #endif }; -static struct rt_pin_irq_hdr hpm_gpio_pin_hdr_tbl[IOC_PAD_PZ11]; +static struct rt_pin_irq_hdr hpm_gpio_pin_hdr_tbl[IOC_SOC_PAD_MAX]; static int hpm_get_gpi_irq_num(uint32_t gpio_idx) { diff --git a/common/libraries/drivers/drv_gpio.h b/common/libraries/drivers/drv_gpio.h index 87778370..17070cb6 100644 --- a/common/libraries/drivers/drv_gpio.h +++ b/common/libraries/drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/drivers/drv_hwtimer.c b/common/libraries/drivers/drv_hwtimer.c index 935698dd..64198914 100644 --- a/common/libraries/drivers/drv_hwtimer.c +++ b/common/libraries/drivers/drv_hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -196,7 +196,7 @@ static rt_err_t hpm_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtim gptmr_channel_config_t config; gptmr_channel_get_default_config(base, &config); - config.cmp[0] = cnt; + config.cmp[0] = 0; config.reload = cnt; timer->mode = mode; @@ -204,7 +204,7 @@ static rt_err_t hpm_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtim gptmr_channel_config(base, hpm_gptmr->channel, &config, true); gptmr_clear_status(base, 0xFU); - gptmr_enable_irq(base, GPTMR_CH_CMP_IRQ_MASK(0, 0)); + gptmr_enable_irq(base, GPTMR_CH_RLD_IRQ_MASK(hpm_gptmr->channel)); gptmr_channel_update_count(base, hpm_gptmr->channel, 0); gptmr_start_counter(base, hpm_gptmr->channel); diff --git a/common/libraries/drivers/drv_hwtimer.h b/common/libraries/drivers/drv_hwtimer.h index e04e22ef..29739f06 100644 --- a/common/libraries/drivers/drv_hwtimer.h +++ b/common/libraries/drivers/drv_hwtimer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/drivers/drv_i2c.c b/common/libraries/drivers/drv_i2c.c index 4d837072..f4912e29 100644 --- a/common/libraries/drivers/drv_i2c.c +++ b/common/libraries/drivers/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -41,16 +41,16 @@ static struct hpm_i2c hpm_i2cs[] = #endif #if defined(BSP_USING_I2C2) { - .base = HPM_I2C1, - .bus_name = "i2c1", - .clk_name = clock_i2c1, + .base = HPM_I2C2, + .bus_name = "i2c2", + .clk_name = clock_i2c2, }, #endif #if defined(BSP_USING_I2C3) { - .base = HPM_I2C1, - .bus_name = "i2c1", - .clk_name = clock_i2c1, + .base = HPM_I2C3, + .bus_name = "i2c3", + .clk_name = clock_i2c3, }, #endif }; @@ -74,7 +74,7 @@ static rt_size_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct r struct hpm_i2c *i2c_info = (struct hpm_i2c *)bus; hpm_stat_t i2c_stat = status_success; - rt_err_t ret = RT_ERROR; + rt_size_t ret = 0; rt_uint32_t i; for (i = 0; i < num; i++) diff --git a/common/libraries/drivers/drv_i2c.h b/common/libraries/drivers/drv_i2c.h index 4072da82..ef3d4573 100644 --- a/common/libraries/drivers/drv_i2c.h +++ b/common/libraries/drivers/drv_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/common/libraries/drivers/drv_i2s.c b/common/libraries/drivers/drv_i2s.c index 55dbd044..dafee03b 100644 --- a/common/libraries/drivers/drv_i2s.c +++ b/common/libraries/drivers/drv_i2s.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -391,7 +391,7 @@ static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio //i2s dma方式仅支持采样位宽为：16bit, 32bit assert(hpm_audio->audio_config.samplebits == 16 || hpm_audio->audio_config.samplebits == 32); - hpm_audio->transfer.audio_depth = (hpm_audio->audio_config.samplebits - 16) >> 3; + hpm_audio->transfer.audio_depth = hpm_audio->audio_config.samplebits; if (status_success != i2s_config_transfer(hpm_audio->base, clock_get_frequency(hpm_audio->clk_name), &hpm_audio->transfer)) { diff --git a/common/libraries/drivers/drv_i2s.h b/common/libraries/drivers/drv_i2s.h index ff9a3691..8034b1d2 100644 --- a/common/libraries/drivers/drv_i2s.h +++ b/common/libraries/drivers/drv_i2s.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/common/libraries/drivers/drv_mcan.c b/common/libraries/drivers/drv_mcan.c new file mode 100644 index 00000000..30c499b8 --- /dev/null +++ b/common/libraries/drivers/drv_mcan.c @@ -0,0 +1,728 @@ +/* + * Copyright (c) 2021 - 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2023-04-07 HPMicro the first version + */ + +#include +#include +#include +#include "board.h" +#include "hpm_mcan_drv.h" + + +#define CAN_SEND_WAIT_MS_MAX (1000U) /* CAN maximum wait time for transmission */ +#define CAN_SENDBOX_NUM (1U) /* CAN Hardware Transmission buffer number */ +#define CAN_STD_FILTER_NUM_MAX (128U) /* std Filter number */ +#define CAN_EXT_FILTER_NUM_MAX (64U) /* ext Filter number */ + +#ifdef RT_USING_CAN + +typedef struct _hpm_can_struct +{ + MCAN_Type *can_base; /**< CAN Base address */ + const char *name; /**< CAN device name */ + int32_t irq_num; /**< CAN IRQ index */ + uint32_t fifo_index; /**< FIFO index, it is a fake value to satisfy the driver framework */ + mcan_config_t can_config; /**< CAN configuration for IP */ + struct rt_can_device can_dev; /**< CAN device configuration in rt-thread */ + uint32_t irq_txrx_err_enable_mask; /**< CAN TX and RX IRQ Enable Mask */ + uint32_t std_filter_num; /**< std Filter number */ + mcan_filter_elem_t std_can_filters[CAN_STD_FILTER_NUM_MAX]; + uint32_t ext_filter_num; /**< ext Filter number */ + mcan_filter_elem_t ext_can_filters[CAN_EXT_FILTER_NUM_MAX]; +} hpm_can_t; + +static const mcan_filter_elem_t k_default_std_id_filter = { + /* Use classic filter */ + .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, + /* Store message into RXFIFO0 if matching */ + .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, + /* For Standard Identify only */ + .can_id_type = MCAN_CAN_ID_TYPE_STANDARD, + /* Sync Message, only evaluated when "CCCR.UTSU" is set */ + .sync_message = 0U, + /* Don't care if mask is set to all 1s */ + .filter_id = 0U, + /* Accept all messages */ + .filter_mask = 0x7FFU, +}; + +static const mcan_filter_elem_t k_default_ext_id_filter = { + /* Use classic filter */ + .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, + /* Store message into RXFIFO0 if matching */ + .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, + /* For Standard Identify only */ + .can_id_type = MCAN_CAN_ID_TYPE_EXTENDED, + /* Sync Message, only evaluated when "CCCR.UTSU" is set */ + .sync_message = 0, + /* Don't care if mask is set to all 1s */ + .filter_id = 0, + /* Accept all messages */ + .filter_mask = 0x1FFFFFFFUL, +}; + + +/** + * @brief Configure CAN controller + * @param [in/out] can CAN device pointer + * @param [in] cfg CAN configuration pointer + * @retval RT_EOK for valid configuration + * @retval -RT_ERROR for invalid configuration + */ +static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configure *cfg); + +/** + * @brief Control/Get CAN state + * including:interrupt, mode, priority, baudrate, filter, status + * @param [in/out] can CAN device pointer + * @param [in] cmd Control command + * @param [in/out] arg Argument pointer + * @retval RT_EOK for valid control command and arg + * @retval -RT_ERROR for invalid control command or arg + */ +static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg); + +/** + * @brief Send out CAN message + * @param [in] can CAN device pointer + * @param [in] buf CAN message buffer + * @param [in] boxno Mailbox number, it is not used in this porting + * @retval RT_EOK No error + * @retval -RT_ETIMEOUT timeout happened + * @retval -RT_EFULL Transmission buffer is full + */ +static int hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno); + +/** + * @brief Receive message from CAN + * @param [in] can CAN device pointer + * @param [out] buf CAN receive buffer + * @param [in] boxno Mailbox Number, it is not used in this porting + * @retval RT_EOK no error + * @retval -RT_ERROR Error happened during reading receive FIFO + * @retval -RT_EMPTY no data in receive FIFO + */ +static int hpm_mcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno); + +/** + * @brief Common Interrupt Service routine + * @param [in] hpm_can HPM CAN pointer + */ +static void hpm_mcan_isr(hpm_can_t *hpm_can); + +/** + * @brief Decode data bytes from DLC + * @param [in] dlc Data Length Code + * @return decoded data bytes + */ +static uint8_t can_get_data_bytes_from_dlc(uint32_t dlc); + +#if defined(HPM_MCAN0_BASE) && defined(BSP_USING_MCAN0) +static hpm_can_t dev_can0 = +{ + .can_base = HPM_MCAN0, + .name = "can0", + .irq_num = IRQn_CAN0, + .fifo_index = 0, +}; + +void can0_isr(void) +{ + hpm_mcan_isr(&dev_can0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_CAN0, can0_isr); + +#endif + +#if defined(HPM_MCAN1_BASE) && defined(BSP_USING_MCAN1) +static hpm_can_t dev_can1 = +{ + .can_base = HPM_MCAN1, + .name = "can1", + .irq_num = IRQn_CAN1, + .fifo_index = 1, +}; +void can1_isr(void) +{ + hpm_mcan_isr(&dev_can1); +} +SDK_DECLARE_EXT_ISR_M(IRQn_CAN1, can1_isr); +#endif + +#if defined(HPM_MCAN2_BASE) && defined(BSP_USING_MCAN2) +static hpm_can_t dev_can2 = +{ + .can_base = HPM_MCAN2, + .name = "can2", + .irq_num = IRQn_CAN2, + .fifo_index = 2, +}; +void can2_isr(void) +{ + hpm_mcan_isr(&dev_can2); +} +SDK_DECLARE_EXT_ISR_M(IRQn_CAN2, can2_isr); +#endif + +#if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3) +static hpm_can_t dev_can3 = +{ + .can_base = HPM_MCAN3, + .name = "can3", + .irq_num = IRQn_CAN3, + .fifo_index = 3, +}; +void can3_isr(void) +{ + hpm_mcan_isr(&dev_can3); +} +SDK_DECLARE_EXT_ISR_M(IRQn_CAN3, can3_isr); +#endif + +static hpm_can_t *hpm_cans[] = { +#if defined(HPM_MCAN0_BASE) && defined(BSP_USING_MCAN0) + &dev_can0, +#endif +#if defined(HPM_MCAN1_BASE) && defined(BSP_USING_MCAN1) + &dev_can1, +#endif +#if defined(HPM_MCAN2_BASE) && defined(BSP_USING_MCAN2) + &dev_can2, +#endif +#if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3) + &dev_can3, +#endif + }; + + +static const struct rt_can_ops hpm_can_ops = { + .configure = hpm_mcan_configure, + .control = hpm_mcan_control, + .sendmsg = hpm_mcan_sendmsg, + .recvmsg = hpm_mcan_recvmsg, +}; + + + +static void hpm_mcan_isr(hpm_can_t *hpm_can) +{ + uint8_t error_flags = mcan_get_last_error_code(hpm_can->can_base); + uint32_t flags = mcan_get_interrupt_flags(hpm_can->can_base); + mcan_error_count_t err_cnt; + /* Transmit completed */ + if ((flags & (MCAN_EVENT_TRANSMIT)) != 0U) { + rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_TX_DONE | (0UL << 8)); + } + + /* Data available in FIFO */ + if ((flags & MCAN_EVENT_RECEIVE) != 0) + { + rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RX_IND | (hpm_can->fifo_index << 8)); + } + + /* RX FIFO overflow */ + if ((flags & MCAN_INT_RXFIFO0_FULL) != 0U) + { + rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RXOF_IND | (hpm_can->fifo_index << 8)); + } + + if ((flags & MCAN_INT_RXFIFO1_FULL) != 0U) + { + rt_hw_can_isr(&hpm_can->can_dev, RT_CAN_EVENT_RXOF_IND | (hpm_can->fifo_index << 8)); + } + + /* Error happened on CAN Bus */ + if (((flags & MCAN_EVENT_ERROR) != 0U) || (error_flags != 0U)) + { + mcan_get_error_counter(hpm_can->can_base, &err_cnt); + switch(error_flags) + { + case 3: + hpm_can->can_dev.status.ackerrcnt++; + break; + case 4: + hpm_can->can_dev.status.biterrcnt++; + break; + case 6: + hpm_can->can_dev.status.crcerrcnt++; + break; + case 2: + hpm_can->can_dev.status.formaterrcnt++; + break; + case 1: + hpm_can->can_dev.status.bitpaderrcnt++; + break; + } + + hpm_can->can_dev.status.rcverrcnt = err_cnt.receive_error_count; + hpm_can->can_dev.status.snderrcnt = err_cnt.transmit_error_count; + hpm_can->can_dev.status.lasterrtype = mcan_get_last_error_code(hpm_can->can_base); + hpm_can->can_dev.status.errcode = 0; + if ((error_flags & MCAN_INT_WARNING_STATUS) != 0U) + { + hpm_can->can_dev.status.errcode |= ERRWARNING; + } + if ((error_flags & MCAN_INT_ERROR_PASSIVE) != 0U) + { + hpm_can->can_dev.status.errcode |= ERRPASSIVE; + } + if (mcan_is_in_busoff_state(hpm_can->can_base)) + { + hpm_can->can_dev.status.errcode |= BUSOFF; + } + } + + mcan_clear_interrupt_flags(hpm_can->can_base, flags); +} + +static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configure *cfg) +{ + RT_ASSERT(can); + RT_ASSERT(cfg); + + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + RT_ASSERT(drv_can); + +#ifdef RT_CAN_USING_CANFD + drv_can->can_config.enable_canfd = (cfg->enable_canfd != 0) ? true : false; + if (cfg->use_bit_timing != 0U) + { + drv_can->can_config.use_lowlevel_timing_setting = true; + drv_can->can_config.can_timing.prescaler = cfg->can_timing.prescaler; + drv_can->can_config.can_timing.num_seg1 = cfg->can_timing.num_seg1; + drv_can->can_config.can_timing.num_seg2 = cfg->can_timing.num_seg2; + drv_can->can_config.can_timing.num_sjw = cfg->can_timing.num_sjw; + + drv_can->can_config.canfd_timing.prescaler = cfg->canfd_timing.prescaler; + drv_can->can_config.canfd_timing.num_seg1 = cfg->canfd_timing.num_seg1; + drv_can->can_config.canfd_timing.num_seg2 = cfg->canfd_timing.num_seg2; + drv_can->can_config.canfd_timing.num_sjw = cfg->canfd_timing.num_sjw; + } + else +#endif + { + drv_can->can_config.use_lowlevel_timing_setting = false; + drv_can->can_config.baudrate = cfg->baud_rate; +#ifdef RT_CAN_USING_CANFD + drv_can->can_config.baudrate_fd = cfg->baud_rate_fd; +#endif + } + + + switch (cfg->mode) + { + case RT_CAN_MODE_NORMAL: + drv_can->can_config.mode = mcan_mode_normal; + break; + case RT_CAN_MODE_LISTEN: + drv_can->can_config.mode = mcan_mode_listen_only; + break; + case RT_CAN_MODE_LOOPBACK: + drv_can->can_config.mode = mcan_mode_loopback_internal; + break; + default: + return -RT_ERROR; + break; + } + + init_can_pins(drv_can->can_base); + uint32_t can_clk = board_init_can_clock(drv_can->can_base); + + drv_can->can_config.all_filters_config.std_id_filter_list.filter_elem_list = &drv_can->std_can_filters[0]; + drv_can->can_config.all_filters_config.std_id_filter_list.mcan_filter_elem_count = drv_can->std_filter_num; + drv_can->can_config.all_filters_config.ext_id_filter_list.filter_elem_list = &drv_can->ext_can_filters[0]; + drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = drv_can->ext_filter_num; + drv_can->can_config.all_filters_config.ext_id_mask = (1UL << 30) - 1UL; + + hpm_stat_t status = mcan_init(drv_can->can_base, &drv_can->can_config, can_clk); + if (status != status_success) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) +{ + RT_ASSERT(can); + + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + RT_ASSERT(drv_can); + + uint32_t arg_val; + rt_err_t err = RT_EOK; + + uint32_t temp; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + arg_val = (uint32_t) arg; + intc_m_disable_irq(drv_can->irq_num); + if (arg_val == RT_DEVICE_FLAG_INT_RX) + { + uint32_t irq_txrx_mask = MCAN_EVENT_RECEIVE; + drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; + mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); + } + else if (arg_val == RT_DEVICE_FLAG_INT_TX) + { + uint32_t irq_txrx_mask = MCAN_EVENT_TRANSMIT; + drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; + mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); + mcan_disable_txbuf_interrupt(drv_can->can_base, ~0UL); + } else if (arg_val == RT_DEVICE_CAN_INT_ERR) { + uint32_t irq_txrx_mask = MCAN_EVENT_ERROR; + drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; + mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); + } else { + err = -RT_ERROR; + } + break; + case RT_DEVICE_CTRL_SET_INT: + arg_val = (uint32_t) arg; + if (arg_val == RT_DEVICE_FLAG_INT_RX) + { + uint32_t irq_txrx_mask = MCAN_EVENT_RECEIVE; + drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; + mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); + intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + } + else if (arg_val == RT_DEVICE_FLAG_INT_TX) + { + uint32_t irq_txrx_mask = MCAN_EVENT_TRANSMIT; + drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; + mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); + mcan_enable_txbuf_interrupt(drv_can->can_base, ~0UL); + intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + } + else if (arg_val == RT_DEVICE_CAN_INT_ERR) + { + uint32_t irq_txrx_mask = MCAN_EVENT_ERROR; + drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; + mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); + intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + } + else + { + err = -RT_ERROR; + } + break; + case RT_CAN_CMD_SET_FILTER: + { + /* Convert the RT-Thread Filter format to the filter format supported by HPM CAN */ + struct rt_can_filter_config *filter = (struct rt_can_filter_config*)arg; + drv_can->std_filter_num = 0; + drv_can->ext_filter_num = 0; + if (filter != NULL) + { + for (uint32_t i = 0; i < filter->count; i++) + { + if (filter->items[i].ide != 0) + { + drv_can->ext_can_filters[drv_can->ext_filter_num].filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER; + drv_can->ext_can_filters[drv_can->ext_filter_num].filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH; + drv_can->ext_can_filters[drv_can->ext_filter_num].can_id_type = MCAN_CAN_ID_TYPE_EXTENDED; + drv_can->ext_can_filters[drv_can->ext_filter_num].filter_id = filter->items[i].id; + drv_can->ext_can_filters[drv_can->ext_filter_num].filter_mask = filter->items[i].mask; + drv_can->ext_filter_num++; + RT_ASSERT(drv_can->ext_filter_num <= CAN_EXT_FILTER_NUM_MAX); + } + else + { + drv_can->std_can_filters[drv_can->std_filter_num].filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER; + drv_can->std_can_filters[drv_can->std_filter_num].filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH; + drv_can->std_can_filters[drv_can->std_filter_num].can_id_type = MCAN_CAN_ID_TYPE_STANDARD; + drv_can->std_can_filters[drv_can->std_filter_num].filter_id = filter->items[i].id; + drv_can->std_can_filters[drv_can->std_filter_num].filter_mask = filter->items[i].mask; + drv_can->std_filter_num++; + RT_ASSERT(drv_can->std_filter_num <= CAN_STD_FILTER_NUM_MAX); + + } + if (filter->items[i].rtr != 0) + { + if (drv_can->ext_filter_num) + { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = false; + } + else + { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = true; + } + if (drv_can->std_filter_num) + { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = false; + } + else + { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = true; + } + } + } + + if (filter->actived != 0U) + { + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT; + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT; + } + else + { + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + } + } + else + { + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_ext_frame = false; + drv_can->can_config.all_filters_config.global_filter_config.reject_remote_std_frame = false; + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_std_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + drv_can->can_config.all_filters_config.global_filter_config.accept_non_matching_ext_frame_option = MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + drv_can->can_config.all_filters_config.ext_id_mask = 0x1FFFFFFFUL; + drv_can->can_config.all_filters_config.std_id_filter_list.filter_elem_list = &k_default_std_id_filter; + drv_can->can_config.all_filters_config.std_id_filter_list.mcan_filter_elem_count = 1; + drv_can->can_config.all_filters_config.ext_id_filter_list.filter_elem_list = &k_default_ext_id_filter; + drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = 1; + } + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } + break; + case RT_CAN_CMD_SET_MODE: + arg_val = (uint32_t) arg; + if ((arg_val != RT_CAN_MODE_NORMAL) && (arg_val != RT_CAN_MODE_LISTEN) && (arg_val != RT_CAN_MODE_LOOPBACK)) + { + err = -RT_ERROR; + break; + } + if (arg_val != drv_can->can_dev.config.mode) + { + drv_can->can_dev.config.mode = arg_val; + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } + + break; + case RT_CAN_CMD_SET_BAUD: + arg_val = (uint32_t) arg; + if (arg_val != drv_can->can_dev.config.baud_rate) + { + drv_can->can_dev.config.baud_rate = arg_val; + } + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + break; +#ifdef RT_CAN_USING_CANFD + case RT_CAN_CMD_SET_CANFD: + arg_val = (uint32_t) arg; + if (arg_val != drv_can->can_dev.config.enable_canfd) + { + drv_can->can_dev.config.enable_canfd = arg_val; + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } + break; + case RT_CAN_CMD_SET_BAUD_FD: + arg_val = (uint32_t) arg; + if (arg_val != drv_can->can_dev.config.baud_rate_fd) + { + drv_can->can_dev.config.baud_rate_fd = arg_val; + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } + break; + case RT_CAN_CMD_SET_BITTIMING: + { + struct rt_can_bit_timing_config *timing_configs = (struct rt_can_bit_timing_config*)arg; + if ((timing_configs == RT_NULL) || (timing_configs->count < 1) || (timing_configs->count > 2)) + { + return -RT_ERROR; + } + + if (timing_configs->count != 0U) + { + drv_can->can_dev.config.can_timing = timing_configs->items[0]; + } + if (timing_configs->count == 2) + { + drv_can->can_dev.config.canfd_timing = timing_configs->items[1]; + } + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } + break; +#endif + case RT_CAN_CMD_SET_PRIV: + arg_val = (uint32_t)arg; + if ((arg_val != RT_CAN_MODE_PRIV) && (arg_val != RT_CAN_MODE_NOPRIV)) + { + return -RT_ERROR; + } + if (arg_val != drv_can->can_dev.config.privmode) + { + drv_can->can_dev.config.privmode = arg_val; + err = hpm_mcan_configure(can, &drv_can->can_dev.config); + } + break; + case RT_CAN_CMD_GET_STATUS: + mcan_error_count_t err_cnt; + mcan_get_error_counter(drv_can->can_base, &err_cnt); + drv_can->can_dev.status.rcverrcnt = err_cnt.receive_error_count; + drv_can->can_dev.status.snderrcnt = err_cnt.transmit_error_count; + drv_can->can_dev.status.lasterrtype = mcan_get_last_error_code(drv_can->can_base); + temp = mcan_get_interrupt_flags(drv_can->can_base); + drv_can->can_dev.status.errcode = 0; + if ((temp & MCAN_INT_WARNING_STATUS) != 0U) + { + drv_can->can_dev.status.errcode |= ERRWARNING; + } + if ((temp & MCAN_INT_ERROR_PASSIVE) != 0U) + { + drv_can->can_dev.status.errcode |= ERRPASSIVE; + } + if (mcan_is_in_busoff_state(drv_can->can_base)) + { + drv_can->can_dev.status.errcode |= BUSOFF; + } + rt_memcpy(arg, &drv_can->can_dev.status, sizeof(drv_can->can_dev.status)); + break; + } +} + +static int hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) +{ + RT_ASSERT(can); + + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + RT_ASSERT(drv_can); + + struct rt_can_msg *can_msg = (struct rt_can_msg *) buf; + + mcan_tx_frame_t tx_frame = {0}; + memset(&tx_frame, 0, sizeof(tx_frame)); + if (can_msg->ide == RT_CAN_STDID) + { + tx_frame.use_ext_id = 0; + tx_frame.std_id = can_msg->id; + } + else + { + tx_frame.use_ext_id = 1; + tx_frame.ext_id = can_msg->id; + } + if (can_msg->rtr == RT_CAN_DTR) + { + tx_frame.rtr = false; + } + else + { + tx_frame.rtr = true; + } + + #ifdef RT_CAN_USING_CANFD + if (can_msg->fd_frame != 0) + { + tx_frame.canfd_frame = 1; + tx_frame.bitrate_switch = 1; + RT_ASSERT(can_msg->len <= 15); + } + else + #endif + { + RT_ASSERT(can_msg->len <= 8); + } + + uint32_t msg_len = mcan_get_message_size_from_dlc(can_msg->len); + for (uint32_t i = 0; i < msg_len; i++) + { + tx_frame.data_8[i] = can_msg->data[i]; + } + tx_frame.dlc = can_msg->len; + + uint32_t delay_cnt = 0; + while (mcan_is_txfifo_full(drv_can->can_base)) + { + rt_thread_mdelay(1); + delay_cnt++; + if (delay_cnt >= CAN_SEND_WAIT_MS_MAX) + { + return -RT_ETIMEOUT; + } + } + hpm_stat_t status = mcan_transmit_via_txbuf_nonblocking(drv_can->can_base, 0, &tx_frame); + if (status != status_success) + { + return -RT_EFULL; + } + + return RT_EOK; +} + +static int hpm_mcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno) +{ + RT_ASSERT(can); + + hpm_can_t *drv_can = (hpm_can_t*) can->parent.user_data; + RT_ASSERT(drv_can); + + rt_can_msg_t can_msg = (rt_can_msg_t)buf; + mcan_rx_message_t rx_buf; + hpm_stat_t status = mcan_read_rxfifo(drv_can->can_base, 0, &rx_buf); + if (status == status_success) + { + if (rx_buf.use_ext_id) + { + can_msg->ide = RT_CAN_EXTID; + can_msg->id = rx_buf.ext_id; + } + else + { + can_msg->ide = RT_CAN_STDID; + can_msg->id = rx_buf.std_id; + } + + + if (rx_buf.rtr != 0) { + can_msg->rtr = RT_CAN_RTR; + } + else { + can_msg->rtr = RT_CAN_DTR; + } + + can_msg->len = rx_buf.dlc; + uint32_t msg_len = mcan_get_message_size_from_dlc(can_msg->len); + for(uint32_t i = 0; i < msg_len; i++) { + can_msg->data[i] = rx_buf.data_8[i]; + } + + } + else + { + return -RT_EEMPTY; + } + + return RT_EOK; +} + +int rt_hw_mcan_init(void) +{ + struct can_configure config = CANDEFAULTCONFIG; + config.privmode = RT_CAN_MODE_NOPRIV; + config.sndboxnumber = CAN_SENDBOX_NUM; + config.ticks = 50; + + for (uint32_t i = 0; i < ARRAY_SIZE(hpm_cans); i++) + { + hpm_cans[i]->can_dev.config = config; + hpm_cans[i]->ext_filter_num = 0; + hpm_cans[i]->std_filter_num = 0; + mcan_get_default_config(hpm_cans[i]->can_base, &hpm_cans[i]->can_config); + rt_hw_can_register(&hpm_cans[i]->can_dev, hpm_cans[i]->name, &hpm_can_ops, hpm_cans[i]); + } + return RT_EOK; +} + +INIT_BOARD_EXPORT(rt_hw_mcan_init); + +#endif + diff --git a/common/libraries/drivers/drv_mcan.h b/common/libraries/drivers/drv_mcan.h new file mode 100644 index 00000000..e5535c7c --- /dev/null +++ b/common/libraries/drivers/drv_mcan.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef DRV_MCAN_H +#define DRV_MCAN_H + +int rt_hw_mcan_init(void); + +#endif /* DRV_CAN_H */ diff --git a/common/libraries/drivers/drv_pdm.c b/common/libraries/drivers/drv_pdm.c index dbbe164b..172191bc 100644 --- a/common/libraries/drivers/drv_pdm.c +++ b/common/libraries/drivers/drv_pdm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/drivers/drv_pdm.h b/common/libraries/drivers/drv_pdm.h index 5f76402b..b450d108 100644 --- a/common/libraries/drivers/drv_pdm.h +++ b/common/libraries/drivers/drv_pdm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/common/libraries/drivers/drv_pwm.c b/common/libraries/drivers/drv_pwm.c index 268a917c..03c43f27 100644 --- a/common/libraries/drivers/drv_pwm.c +++ b/common/libraries/drivers/drv_pwm.c @@ -1,11 +1,8 @@ /* - * Copyright (c) 2022 hpm + * Copyright (c) 2022 - 2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * - * Change Logs: - * Date Author Notes - * 2022-01-11 will First version */ #include @@ -23,7 +20,6 @@ static const clock_name_t pwm_clock_tbl[4] = {clock_mot0, clock_mot1, clock_mot2 rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse) { - uint8_t cmp_index = 0; uint32_t duty; pwm_cmp_config_t cmp_config[4] = {0}; pwm_config_t pwm_config = {0}; @@ -74,8 +70,7 @@ rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channe if (status_success != pwm_setup_waveform(pwm_name_index, channel, &pwm_config, channel * 2, cmp_config, 2)) { return RT_FALSE; } - pwm_load_cmp_shadow_on_capture(pwm_name_index, cmp_index + 17, 0); - pwm_config_cmp(pwm_name_index, cmp_index + 17, &cmp_config[3]); + pwm_load_cmp_shadow_on_match(pwm_name_index, 17, &cmp_config[3]); pwm_start_counter(pwm_name_index); pwm_issue_shadow_register_lock_event(pwm_name_index); duty = (uint64_t)freq * pulse / 1000000000; @@ -88,7 +83,6 @@ rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channe rt_err_t hpm_set_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse) { - uint8_t cmp_index = 0; uint32_t duty; pwm_cmp_config_t cmp_config[4] = {0}; pwm_config_t pwm_config = {0}; @@ -107,23 +101,16 @@ rt_err_t hpm_set_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, ui } pwm_get_default_pwm_config(pwm_name_index, &pwm_config); - pwm_set_reload(pwm_name_index, 0, reload); - cmp_config[3].mode = pwm_cmp_mode_output_compare; cmp_config[3].cmp = reload; cmp_config[3].update_trigger = pwm_shadow_register_update_on_modify; - -// pwm_load_cmp_shadow_on_capture(pwm_name_index, cmp_index + 4, 0); - pwm_config_cmp(pwm_name_index, cmp_index + 4, &cmp_config[3]); - + pwm_config_cmp(pwm_name_index, 17, &cmp_config[3]); pwm_issue_shadow_register_lock_event(pwm_name_index); duty = (uint64_t)freq * pulse / 1000000000; - pwm_update_raw_cmp_central_aligned(pwm_name_index, channel * 2, channel * 2 + 1, (reload - duty) >> 1, (reload + duty) >> 1); return RT_TRUE; - } rt_err_t hpm_disable_pwm(uint8_t pwm_index, uint8_t channel) @@ -274,5 +261,5 @@ int rt_hw_pwm_init(void) INIT_BOARD_EXPORT(rt_hw_pwm_init); -#endif /* BSP_USING_GPIO */ +#endif /* BSP_USING_PWM */ diff --git a/common/libraries/drivers/drv_pwm.h b/common/libraries/drivers/drv_pwm.h index 8a99e119..badbb0da 100644 --- a/common/libraries/drivers/drv_pwm.h +++ b/common/libraries/drivers/drv_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/drivers/drv_rtc.c b/common/libraries/drivers/drv_rtc.c index 3eb1f660..67831cf4 100644 --- a/common/libraries/drivers/drv_rtc.c +++ b/common/libraries/drivers/drv_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -18,9 +18,9 @@ #ifdef RT_USING_RTC /******************************************************************************************* - * + * * Prototypes - * + * ******************************************************************************************/ static rt_err_t hpm_rtc_init(rt_device_t dev); static rt_err_t hpm_rtc_open(rt_device_t dev, rt_uint16_t oflag); @@ -33,9 +33,9 @@ static time_t get_timestamp(void); static int set_timestamp(time_t timestamp); /******************************************************************************************* - * + * * Variables - * + * ******************************************************************************************/ static struct rt_device hpm_rtc= { .type = RT_Device_Class_RTC, @@ -48,9 +48,9 @@ static struct rt_device hpm_rtc= { }; /******************************************************************************************* - * + * * Codes - * + * ******************************************************************************************/ static rt_err_t hpm_rtc_init(rt_device_t dev) { diff --git a/common/libraries/drivers/drv_rtc.h b/common/libraries/drivers/drv_rtc.h index b92d4469..64bcff89 100644 --- a/common/libraries/drivers/drv_rtc.h +++ b/common/libraries/drivers/drv_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -14,4 +14,4 @@ int rt_hw_rtc_init(void); -#endif /* DRV_RTC_H */ \ No newline at end of file +#endif /* DRV_RTC_H */ diff --git a/common/libraries/drivers/drv_sdio.c b/common/libraries/drivers/drv_sdio.c index e8a22501..5cd53664 100644 --- a/common/libraries/drivers/drv_sdio.c +++ b/common/libraries/drivers/drv_sdio.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-02-23 hpmicro First version - * 2022-07-19 hpmicro Fixed the multi-block read/write issue + * 2022-02-23 HPMicro First version + * 2022-07-19 HPMicro Fixed the multi-block read/write issue */ #include @@ -277,29 +277,49 @@ static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_c vdd = io_cfg->vdd; - static bool has_init = false; + switch(io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + board_sd_power_switch(mmcsd->sdxc_base, false); + break; + case MMCSD_POWER_ON: + board_sd_power_switch(mmcsd->sdxc_base, true); + break; + case MMCSD_POWER_UP: + board_sd_power_switch(mmcsd->sdxc_base, false); + rt_thread_mdelay(10); + board_sd_power_switch(mmcsd->sdxc_base, true); + break; + default: + /* Do nothing */ + break; + } + + switch (io_cfg->bus_width) + { + case MMCSD_BUS_WIDTH_4: + sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_4bit); + break; + case MMCSD_BUS_WIDTH_8: + sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_8bit); + break; + default: + sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_1bit); + break; + } - init_sdxc_pins(mmcsd->sdxc_base, false); - uint32_t sdxc_clock = io_cfg->clock; + static bool has_init = false; + if (!has_init) { + board_init_sd_pins(mmcsd->sdxc_base); + has_init = true; + } + uint32_t sdxc_clock = io_cfg->clock; if (sdxc_clock != 0U) { - switch (io_cfg->bus_width) - { - case MMCSD_BUS_WIDTH_4: - sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_4bit); - break; - case MMCSD_BUS_WIDTH_8: - sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_8bit); - break; - default: - sdxc_set_data_bus_width(mmcsd->sdxc_base, sdxc_bus_width_1bit); - break; - } board_sd_configure_clock(mmcsd->sdxc_base, sdxc_clk); } - rt_thread_mdelay(5); } static void hpm_sdmmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en) diff --git a/common/libraries/drivers/drv_sdio.h b/common/libraries/drivers/drv_sdio.h index 12bb7383..64f81f6a 100644 --- a/common/libraries/drivers/drv_sdio.h +++ b/common/libraries/drivers/drv_sdio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021 - 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,4 +9,4 @@ int rt_hw_sdio_init(void); -#endif /* DRV_SDIO_H */ \ No newline at end of file +#endif /* DRV_SDIO_H */ diff --git a/common/libraries/drivers/drv_spi.c b/common/libraries/drivers/drv_spi.c index 7dd6def0..78350bd9 100644 --- a/common/libraries/drivers/drv_spi.c +++ b/common/libraries/drivers/drv_spi.c @@ -1,8 +1,13 @@ /* - * Copyright (c) 2021 hpm + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * + * Change Logs: + * Date Author Notes + * 2022-02-01 HPMicro First version + * 2023-02-15 HPMicro Add DMA support + * */ #include @@ -12,6 +17,11 @@ #include "drv_spi.h" #include "hpm_spi_drv.h" #include "hpm_sysctl_drv.h" +#include "hpm_dma_manager.h" +#include "hpm_dmamux_drv.h" + +#include "hpm_l1c_drv.h" + struct hpm_spi { @@ -21,7 +31,11 @@ struct hpm_spi spi_control_config_t control_config; struct rt_spi_bus spi_bus; rt_sem_t xfer_sem; - /* TODO: add DMA support later */ + rt_bool_t enable_dma; + rt_uint8_t tx_dmamux; + rt_uint8_t rx_dmamux; + hpm_dma_resource_t tx_dma; + hpm_dma_resource_t rx_dma; }; static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg); @@ -33,24 +47,36 @@ static struct hpm_spi hpm_spis[] = { .bus_name = "spi0", .spi_base = HPM_SPI0, + .enable_dma = RT_TRUE, + .tx_dmamux = HPM_DMA_SRC_SPI0_TX, + .rx_dmamux = HPM_DMA_SRC_SPI0_RX, }, #endif #if defined(BSP_USING_SPI1) { .bus_name = "spi1", .spi_base = HPM_SPI1, + .enable_dma = RT_TRUE, + .tx_dmamux = HPM_DMA_SRC_SPI1_TX, + .rx_dmamux = HPM_DMA_SRC_SPI1_RX, }, #endif #if defined(BSP_USING_SPI2) { .bus_name = "spi2", .spi_base = HPM_SPI2, + .enable_dma = RT_TRUE, + .tx_dmamux = HPM_DMA_SRC_SPI2_TX, + .rx_dmamux = HPM_DMA_SRC_SPI2_RX, }, #endif #if defined(BSP_USING_SPI3) { .bus_name = "spi3", .spi_base = HPM_SPI3, + .enable_dma = RT_TRUE, + .tx_dmamux = HPM_DMA_SRC_SPI3_TX, + .rx_dmamux = HPM_DMA_SRC_SPI3_RX, }, #endif }; @@ -108,24 +134,13 @@ static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_co return RT_EOK; } -static rt_uint32_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *msg) -{ - RT_ASSERT(device != RT_NULL); - RT_ASSERT(msg != RT_NULL); - RT_ASSERT(device->bus != RT_NULL); - RT_ASSERT(device->bus->parent.user_data != RT_NULL); - cs_ctrl_callback_t cs_pin_control = (cs_ctrl_callback_t) device->parent.user_data; +static hpm_stat_t hpm_spi_xfer_polling(struct rt_spi_device *device, struct rt_spi_message *msg) +{ struct hpm_spi *spi = (struct hpm_spi *) (device->bus->parent.user_data); - hpm_stat_t spi_stat = status_success; - if ((cs_pin_control != NULL) && msg->cs_take) - { - cs_pin_control(SPI_CS_TAKE); - } - uint32_t remaining_size = msg->length; uint32_t transfer_len; uint8_t *tx_buf = (uint8_t*) msg->send_buf; @@ -133,35 +148,211 @@ static rt_uint32_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess while (remaining_size > 0) { transfer_len = MIN(512, remaining_size); + spi->control_config.common_config.tx_dma_enable = false; + spi->control_config.common_config.rx_dma_enable = false; if (msg->send_buf != NULL && msg->recv_buf != NULL) { spi->control_config.common_config.trans_mode = spi_trans_write_read_together; - spi_stat = spi_transfer(spi->spi_base, - &spi->control_config, - NULL, - NULL, - tx_buf, transfer_len, - rx_buf, transfer_len); + spi_stat = spi_transfer(spi->spi_base, &spi->control_config, + NULL, + NULL, tx_buf, transfer_len, rx_buf, transfer_len); } else if (msg->send_buf != NULL) { spi->control_config.common_config.trans_mode = spi_trans_write_only; spi_stat = spi_transfer(spi->spi_base, &spi->control_config, - NULL, - NULL, - (uint8_t*) tx_buf, transfer_len, - NULL, 0); + NULL, + NULL, (uint8_t*) tx_buf, transfer_len, + NULL, 0); } else { spi->control_config.common_config.trans_mode = spi_trans_read_only; spi_stat = spi_transfer(spi->spi_base, &spi->control_config, - NULL, - NULL, - NULL, 0, - rx_buf, transfer_len); + NULL, + NULL, + NULL, 0, rx_buf, transfer_len); + } + + if (spi_stat != status_success) + { + break; + } + + if (tx_buf != NULL) + { + tx_buf += transfer_len; + } + if (rx_buf != NULL) + { + rx_buf += transfer_len; + } + remaining_size -= transfer_len; + } + + return spi_stat; +} + +hpm_stat_t spi_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t src, uint8_t data_width, uint32_t size) +{ + dma_handshake_config_t config; + config.ch_index = ch_num; + config.dst = (uint32_t)&spi_ptr->DATA; + config.dst_fixed = true; + config.src = src; + config.src_fixed = false; + config.data_width = data_width; + config.size_in_byte = size; + + return dma_setup_handshake(dma_ptr, &config, true); +} + +hpm_stat_t spi_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, uint8_t data_width, uint32_t size) +{ + dma_handshake_config_t config; + config.ch_index = ch_num; + config.dst = dst; + config.dst_fixed = false; + config.src = (uint32_t)&spi_ptr->DATA; + config.src_fixed = true; + config.data_width = data_width; + config.size_in_byte = size; + + return dma_setup_handshake(dma_ptr, &config, true); +} + + +static hpm_stat_t hpm_spi_wait_idle(SPI_Type *ptr) +{ + hpm_stat_t status = status_success; + rt_tick_t start_tick = rt_tick_get(); + while(ptr->STATUS & SPI_STATUS_SPIACTIVE_MASK) + { + if ((rt_tick_get() - start_tick) > RT_TICK_PER_SECOND) + { + status = status_timeout; + break; + } + } + return status; +} +static rt_uint32_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_message *msg) +{ + struct hpm_spi *spi = (struct hpm_spi *) (device->bus->parent.user_data); + hpm_stat_t spi_stat = status_success; + uint32_t remaining_size = msg->length; + uint32_t transfer_len; + uint8_t *aligned_tx_buf = RT_NULL; + uint8_t *aligned_rx_buf = RT_NULL; + uint32_t aligned_len = 0; + if (msg->length > 0) + { + aligned_len = (msg->length + HPM_L1C_CACHELINE_SIZE - 1U) & ~(HPM_L1C_CACHELINE_SIZE - 1U); + if (msg->send_buf != RT_NULL) + { + if (l1c_dc_is_enabled()) + { + aligned_tx_buf = (uint8_t*) rt_malloc_align(aligned_len, HPM_L1C_CACHELINE_SIZE); + RT_ASSERT(aligned_tx_buf != RT_NULL); + rt_memcpy(aligned_tx_buf, msg->send_buf, msg->length); + l1c_dc_flush((uint32_t) aligned_tx_buf, aligned_len); + } + else + { + aligned_tx_buf = (uint8_t*) msg->send_buf; + } } + if (msg->recv_buf != RT_NULL) + { + if (l1c_dc_is_enabled()) + { + aligned_rx_buf = (uint8_t*) rt_malloc_align(aligned_len, HPM_L1C_CACHELINE_SIZE); + RT_ASSERT(aligned_rx_buf != RT_NULL); + } + else + { + aligned_rx_buf = msg->recv_buf; + } + } + } + uint8_t *tx_buf = aligned_tx_buf; + uint8_t *rx_buf = aligned_rx_buf; + uint32_t core_id = read_csr(CSR_MHARTID); + spi->spi_base->CTRL &= ~(SPI_CTRL_TXDMAEN_MASK | SPI_CTRL_RXDMAEN_MASK); + while (remaining_size > 0) + { + transfer_len = MIN(512, remaining_size); + spi->control_config.common_config.tx_dma_enable = false; + spi->control_config.common_config.rx_dma_enable = false; + if (msg->send_buf != NULL && msg->recv_buf != NULL) + { + spi->control_config.common_config.trans_mode = spi_trans_write_read_together; + spi->control_config.common_config.tx_dma_enable = true; + spi->control_config.common_config.rx_dma_enable = true; + spi->control_config.common_config.trans_mode = spi_trans_write_read_together; + spi_stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, NULL, NULL, transfer_len, + transfer_len); + if (spi_stat != status_success) + { + break; + } + + dmamux_config(HPM_DMAMUX, spi->tx_dma.channel, spi->tx_dmamux, true); + spi_stat = spi_tx_trigger_dma(spi->tx_dma.base, spi->tx_dma.channel, spi->spi_base, + core_local_mem_to_sys_address(core_id, (uint32_t) tx_buf), + DMA_TRANSFER_WIDTH_BYTE, transfer_len); + + /* setup spi rx trigger dma transfer*/ + dmamux_config(HPM_DMAMUX, spi->rx_dma.channel, spi->rx_dmamux, true); + spi_stat = spi_rx_trigger_dma(spi->rx_dma.base, spi->rx_dma.channel, spi->spi_base, + core_local_mem_to_sys_address(core_id, (uint32_t) rx_buf), + DMA_TRANSFER_WIDTH_BYTE, transfer_len); + if (spi_stat != status_success) + { + break; + } + } + else if (msg->send_buf != NULL) + { + spi->control_config.common_config.tx_dma_enable = true; + spi->control_config.common_config.trans_mode = spi_trans_write_only; + spi_stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, NULL, NULL, transfer_len, 0); + if (spi_stat != status_success) + { + break; + } + + dmamux_config(HPM_DMAMUX, spi->tx_dma.channel, spi->tx_dmamux, true); + spi_stat = spi_tx_trigger_dma(spi->tx_dma.base, spi->tx_dma.channel, spi->spi_base, + core_local_mem_to_sys_address(core_id, (uint32_t) tx_buf), + DMA_TRANSFER_WIDTH_BYTE, transfer_len); + if (spi_stat != status_success) + { + break; + } + } + else + { + spi->control_config.common_config.rx_dma_enable = true; + spi->control_config.common_config.trans_mode = spi_trans_read_only; + spi_stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, NULL, NULL, 0, transfer_len); + if (spi_stat != status_success) + { + break; + } + + /* setup spi rx trigger dma transfer*/ + dmamux_config(HPM_DMAMUX, spi->rx_dma.channel, spi->rx_dmamux, true); + spi_stat = spi_rx_trigger_dma(spi->rx_dma.base, spi->rx_dma.channel, spi->spi_base, + core_local_mem_to_sys_address(core_id, (uint32_t) rx_buf), + DMA_TRANSFER_WIDTH_BYTE, transfer_len); + if (spi_stat != status_success) + { + break; + } + } + spi_stat = hpm_spi_wait_idle(spi->spi_base); if (spi_stat != status_success) { break; @@ -176,7 +367,59 @@ static rt_uint32_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess rx_buf += transfer_len; } remaining_size -= transfer_len; + spi->spi_base->CTRL &= ~(SPI_CTRL_TXDMAEN_MASK | SPI_CTRL_RXDMAEN_MASK); } + + if (l1c_dc_is_enabled() && (msg->length > 0)) + { + /* cache invalidate for receive buff */ + if (aligned_tx_buf != RT_NULL) + { + rt_free_align(aligned_tx_buf); + aligned_tx_buf = RT_NULL; + } + + if (aligned_rx_buf != RT_NULL) + { + l1c_dc_invalidate((uint32_t) aligned_rx_buf, aligned_len); + rt_memcpy(msg->recv_buf, aligned_rx_buf, msg->length); + rt_free_align(aligned_rx_buf); + aligned_rx_buf = RT_NULL; + } + } + + return spi_stat; +} + + + +static rt_uint32_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *msg) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(msg != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + + cs_ctrl_callback_t cs_pin_control = (cs_ctrl_callback_t) device->parent.user_data; + + struct hpm_spi *spi = (struct hpm_spi *) (device->bus->parent.user_data); + + hpm_stat_t spi_stat = status_success; + + if ((cs_pin_control != NULL) && msg->cs_take) + { + cs_pin_control(SPI_CS_TAKE); + } + + if (spi->enable_dma) + { + spi_stat = hpm_spi_xfer_dma(device, msg); + } + else + { + spi_stat = hpm_spi_xfer_polling(device, msg); + } + if (spi_stat != status_success) { msg->length = 0; @@ -214,12 +457,29 @@ int rt_hw_spi_init(void) { rt_err_t ret = RT_EOK; + hpm_stat_t stat; for (uint32_t i = 0; i < sizeof(hpm_spis) / sizeof(hpm_spis[0]); i++) { - hpm_spis[i].spi_bus.parent.user_data = &hpm_spis[i]; + struct hpm_spi *spi = &hpm_spis[i]; - ret = rt_spi_bus_register(&hpm_spis[i].spi_bus, hpm_spis[i].bus_name, &hpm_spi_ops); + spi->spi_bus.parent.user_data = spi; + if (spi->enable_dma) + { + stat = dma_manager_request_resource(&spi->tx_dma); + if (stat != status_success) + { + return -RT_ERROR; + } + + stat = dma_manager_request_resource(&spi->rx_dma); + if (stat != status_success) + { + return -RT_ERROR; + } + } + + ret = rt_spi_bus_register(&spi->spi_bus, spi->bus_name, &hpm_spi_ops); if (ret != RT_EOK) { break; @@ -236,4 +496,3 @@ int rt_hw_spi_init(void) INIT_BOARD_EXPORT(rt_hw_spi_init); #endif /*BSP_USING_SPI*/ - diff --git a/common/libraries/drivers/drv_spi.h b/common/libraries/drivers/drv_spi.h index b03349de..9218ca48 100644 --- a/common/libraries/drivers/drv_spi.h +++ b/common/libraries/drivers/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,4 +25,3 @@ int rt_hw_spi_init(void); #endif /* DRV_SPI_H */ - diff --git a/common/libraries/drivers/drv_uart.c b/common/libraries/drivers/drv_uart.c index df93fb6c..31ba9885 100644 --- a/common/libraries/drivers/drv_uart.c +++ b/common/libraries/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/drivers/drv_uart.h b/common/libraries/drivers/drv_uart.h index 6b514512..4c4a67db 100644 --- a/common/libraries/drivers/drv_uart.h +++ b/common/libraries/drivers/drv_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/drivers/drv_uart_v2.c b/common/libraries/drivers/drv_uart_v2.c index 26e31586..50a25f09 100644 --- a/common/libraries/drivers/drv_uart_v2.c +++ b/common/libraries/drivers/drv_uart_v2.c @@ -1,13 +1,14 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes - * 2022-03-08 hpmicro First version - * 2022-07-28 hpmicro Fix compiling warning if RT_SERIAL_USING_DMA was not defined - * 2022-08-08 hpmicro Integrate DMA Manager and support dynamic DMA resource assignment + * 2022-03-08 HPMicro First version + * 2022-07-28 HPMicro Fix compiling warning if RT_SERIAL_USING_DMA was not defined + * 2022-08-08 HPMicro Integrate DMA Manager and support dynamic DMA resource assignment' + * 2023-03-07 HPMicro Fix the issue that the data_width was not initialized before setup dma handshake * */ #include @@ -55,6 +56,9 @@ struct hpm_uart { hpm_dma_channel_handle_t rx_chn_ctx; bool tx_resource_allocated; bool rx_resource_allocated; +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA) + ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t rx_idle_tmp_buffer[1024]; +#endif #endif }; @@ -578,10 +582,22 @@ static void uart_rx_done(struct rt_serial_device *serial) struct rt_serial_rx_fifo *rx_fifo; rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA) + uint32_t uart_recv_data_count = 0; + struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; + uint32_t rx_idle_tmp_buffer_size = sizeof(uart->rx_idle_tmp_buffer); + uart_recv_data_count = rx_idle_tmp_buffer_size - dma_get_residue_transfer_size(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel); + if (l1c_dc_is_enabled()) { + l1c_dc_invalidate((uint32_t)uart->rx_idle_tmp_buffer, rx_idle_tmp_buffer_size); + } + rt_ringbuffer_put(&(rx_fifo->rb), uart->rx_idle_tmp_buffer, uart_recv_data_count); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE); +#else if (l1c_dc_is_enabled()) { l1c_dc_invalidate((uint32_t)rx_fifo->buffer, serial->config.rx_bufsz); } rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (serial->config.rx_bufsz << 8)); +#endif /* prepare for next read */ hpm_uart_dma_config(serial, (void *)RT_DEVICE_FLAG_DMA_RX); } @@ -631,6 +647,13 @@ static void hpm_uart_isr(struct rt_serial_device *serial) } } } + #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA) + if (uart_is_rxline_idle(uart->uart_base)) { + uart_rx_done(serial); + uart_clear_rxline_idle_flag(uart->uart_base); + uart_flush(uart->uart_base); + } +#endif /* leave interrupt */ rt_interrupt_leave(); } @@ -662,7 +685,14 @@ static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct seria if (uart->dma_flags & RT_DEVICE_FLAG_DMA_RX) { uart_config.rx_fifo_level = uart_rx_fifo_trg_not_empty; } +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + uart_config.rxidle_config.detect_enable = true; + uart_config.rxidle_config.detect_irq_enable = true; + uart_config.rxidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one; + uart_config.rxidle_config.threshold = 10U; /* 10bit */ +#endif } + #endif uart_config.word_length = cfg->data_bits - DATA_BITS_5; @@ -714,18 +744,30 @@ static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg) if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; config.ch_index = uart->rx_chn_ctx.resource.channel; +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + config.dst = (uint32_t)uart->rx_idle_tmp_buffer; +#else config.dst = (uint32_t) rx_fifo->buffer; +#endif + config.dst_fixed = false; config.src = (uint32_t)&(uart->uart_base->RBR); config.src_fixed = true; + config.data_width = DMA_TRANSFER_WIDTH_BYTE; +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + config.size_in_byte = sizeof(uart->rx_idle_tmp_buffer); +#else config.size_in_byte = serial->config.rx_bufsz; +#endif if (status_success != dma_setup_handshake(uart->rx_chn_ctx.resource.base, &config, true)) { return RT_ERROR; } uint32_t mux = DMA_SOC_CHN_TO_DMAMUX_CHN(uart->rx_chn_ctx.resource.base, uart->rx_dma_mux); dmamux_config(BOARD_UART_DMAMUX, uart->rx_chn_ctx.resource.channel, mux, true); + #if !defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) || (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 0) hpm_uart_dma_register_channel(serial, false, uart_rx_done, RT_NULL, RT_NULL); intc_m_enable_irq(uart->rx_chn_ctx.resource.irq_num); +#endif } else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { uint32_t mux = DMA_SOC_CHN_TO_DMAMUX_CHN(uart->tx_chn_ctx.resource.base, uart->tx_dma_mux); dmamux_config(BOARD_UART_DMAMUX, uart->tx_chn_ctx.resource.channel, mux, true); @@ -745,6 +787,7 @@ static void hpm_uart_transmit_dma(DMA_Type *dma, uint32_t ch_num, UART_Type *uar config.src = (uint32_t) src; config.src_fixed = false; config.size_in_byte = size; + config.data_width = DMA_TRANSFER_WIDTH_BYTE; dma_setup_handshake(dma, &config, true); } diff --git a/common/libraries/drivers/drv_uart_v2.h b/common/libraries/drivers/drv_uart_v2.h index 6b514512..34ca294f 100644 --- a/common/libraries/drivers/drv_uart_v2.h +++ b/common/libraries/drivers/drv_uart_v2.h @@ -1,14 +1,14 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -#ifndef DRV_UART_H -#define DRV_UART_H +#ifndef DRV_UART_V2_H +#define DRV_UART_V2_H int rt_hw_uart_init(void); -#endif /* DRV_UART_H */ \ No newline at end of file +#endif /* DRV_UART_H */ diff --git a/common/libraries/drivers/drv_usb.c b/common/libraries/drivers/drv_usb.c index 946a9f3a..5a79c9c1 100644 --- a/common/libraries/drivers/drv_usb.c +++ b/common/libraries/drivers/drv_usb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/drivers/drv_usb.h b/common/libraries/drivers/drv_usb.h index dea46136..16522599 100644 --- a/common/libraries/drivers/drv_usb.h +++ b/common/libraries/drivers/drv_usb.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/drivers/drv_wdt.c b/common/libraries/drivers/drv_wdt.c index 5b211026..5cf2274d 100644 --- a/common/libraries/drivers/drv_wdt.c +++ b/common/libraries/drivers/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021 - 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/drivers/drv_wdt.h b/common/libraries/drivers/drv_wdt.h index 4c429387..4c69255a 100644 --- a/common/libraries/drivers/drv_wdt.h +++ b/common/libraries/drivers/drv_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/CHANGELOG.md b/common/libraries/hpm_sdk/CHANGELOG.md index 0c5e5cdb..397387d7 100644 --- a/common/libraries/hpm_sdk/CHANGELOG.md +++ b/common/libraries/hpm_sdk/CHANGELOG.md @@ -1,25 +1,222 @@ # Change Log -## [0.13.1] - 2022-08-23: +## [1.1.0] - 2023-03-31: + +Main changes since 1.0.0 + +Tested Segger Embedded Studio Version: 7.10 + +### Changed: + - docs: add new docs for rtd project. + - soc: ip: enet: update the enet register file + - soc: ip: adc16: update the adc16 header file + - soc: hpm_romapi - Add APIs for configuring remapping, exip regions + - drivers: enet: improve APIs related to PPS + - drivers: adc: change adc bus blocking interface + - drivers: adc: optimize getting oneshot result + - drivers: src: update the default config for ADC12&ADC16 + - boards: rename board-level APIs related to enet + - components: enet_phy: rtl8201: update the register file + - middleware: hpm_math: update dsp version + - middleware: erpc: update to v1.10.0 + - samples: uart: rename uart_dma_rx_idle to uart_software_rx_idle + - samples: uart: add hardware rx idle detection sample + - samples: multicore: erpc: core1 add sdk_compile_options(-O1) + - samples: drivers: gptmr: update sample output. + - samples: lwip: common: arch: ethernetif: update a calling function name + - samples:drivers: adc: optimize oneshot handler + +### Added: + - arch: add FPU related APIs + - soc/board: add HPM6280 support + - soc: HPM6750: acmp: add ACMP section + - components: add mt9m114 support + - drivers: add raw8 pixel format support + - drivers: csr - Implement CSR driver + - drivers: adc: adc16: support resolution setting + - drivers/samples: add SDM/PLA/CRC/MCAN + - drivers: I2C: add new API + - drivers: adc: adc16: support resolution setting + - drivers: enet: add enet control config for transmission + - middleware: cherryusb: audio: update class driver and demo template + - middleware: add mbedtls lib files with SDP acceleration + - freeRTOS: add support for static allocation + - samples: drivers: enet: add a pps demo + - samples: cherryusb: add audio samples + - samples: add the resolution parameter in all demos with ADC16 + - samples: add rfft demo + - sampels: i2c: add interrupt b2b samples + - samples: drivers: i2s: add an i2s_master demo + - samples: drivers: i2s: add an i2s_slave demo + - samples : rom_api : add sw_gm_api filter + - samples: add the resolution parameter in all demos with ADC16 + +### Fixed: + - openocd: hpm6300evk: update sdram initialization. + - drivers: trgmux: trigmux edge filter setting error + - drivers: enet: fix register access error + - drivers: adc16: fix the config error of ADC16_CONFIG1 + - drivers: i2c: fix i2c timing configuration + - drivers: SPI: fix SPI status API + - drivers: fix gptmr cmp value don't minus one + - drivers: mcan: correct the mcan ext_id filter issue + - drivers: I2C: fix issue in i2c_master_address_read API + - drivers: Self_ACK cannot be set in CAN driver + - drivers: rtc rtc_config_alarm always return error code + - cmake: correct source code compilation + - soc: toolchain: gcc: initialize heap for SES + - soc: gcc linker files: add NOLOAD keyword to noncacheable.bss section + - soc: HPM6360: gcc: ld: correct noncacheable region name. + - drivers: qei: Fix speed display always zero + - middleware: freertos: disable global irq before vTaskStartScheduler + - freeRTOS: fix trap when enable float feature + - freeRTOS: fix tick lost + - freeRTOS: fix segger project build warning + - samples: drivers: i2s: fix CFGR config + - samples: drivers: fix acmp toggle error + - samples: lwip: fix the DHCP issue + - samples: uart: fix irq_id judgment + - samples: fix the order of uart pin configuration and clock configuration + - samples: update spi dma sample + - samples: drivers: sysctl: correct reset enable approach. + - samples: fix dma_general_transfer sample memory out of bounds + - samples: drivers: wdog: Fix logic issue on finding the nearest interrupt interval + - sample: audio_codec: decoder_wav: add '\0' to fatfs path + +## [1.00.0] - 2022-12-31: + +Main changes since 0.14.0 + +Tested Segger Embedded Studio Version: 7.10 + +### Changed: + - boards: add version info in banner. + - board: lcdc: move panel para to board + - components: spi component to support to transfer different width of data in dma handshake mode + - drivers: rename dram to femc + - middleware: cherryusb update to v0.7.0 + - middleware: erpc: update for support rtos + - middleware: hpm_mcl: update api naming + - samples: erpc: rename erpc_matrix_multiply_rpmsg to erpc_matrix_multiply_rpmsg_bm + - samples: erpc: reorganize erpc_matrix_multiply_rpmsg samples + - samples: erpc: move samples folder to erpc_matrix_multiply_rpmsg + - samples: update i2c/spi dma channel and dmamux channel definition + - ses: project template: use demo.* as output file naming. + - soc: HPM6750: toolchains: update linker files + - soc: HPM6360: toolchains: update linker files + +### Added: + - arch: riscv: add read_clear_csr() API + - component: add wm8960 support + - component: add usb device iso transfer support + - drivers: hpm_common: include hpm_sdk_version.h. + - drivers: common: add NOP and WFI. + - drivers: uart: add api to recv/send byte directly. + - soc: HPM6750 linker files: rename rpmsg_sh_mem to sh_mem + - cmake: add sdk version header file generation. + - middleware: tinyusb: add audio class + - middleware: hpm_math: add NN library + - samples: erpc: add erpc_two_way_rpc_rpmsg_rtos sample + - samples: erpc: add erpc_matrix_multiply_rpmsg_rtos sample + - samples: add power mode switch demo. #282 + - samples: drivers: adc: add a temperature measurement demo + - samples: drviers: femc: add sram sample + - samples: lwip demo for FreeRTOS + - samples: lwip demo of interrupt usage + - samples: tinyusb: add uac2 demo + - samples: tflm: add face detection demo + - samples: tflm: add MLPerf Tiny benchmark demo + - samples: lwip: common: feature: add a LPI interrupt process + +### Fixed: + - drivers:interrupt: Fix FPU context crashing in nested irq case + - drivers: src: adc: fix adc result in period mode + - segger: update app directory structure in SES. + - soc: disable irq during cache maintenance + - middleware: lvgl: fps calculation to No. + - samples: get off level based on board api. + - samples: multicore: hello: core1 rgb led does not change correctly. + +## [0.14.0] - 2022-10-31: Main changes since 0.13.0 +Tested Segger Embedded Studio Version: 6.34a + ### Changed: - - Driver:I2S: update i2s drivers - - middleware: lwip: optimize variable_name definition - - samples: lwip: lwip_iperf: update readme files - - samples: lwip: common: arch: add LWIP_MEM_SECTION declartion + - drivers: inc: update adc driver + - drivers: gptmr: update reload value + - components: enet_phy: optimize APIs + - components: enet_phy: dp83867: rename functions + - components: conditionally add debug_console + - middleware: add cherryusb (0.6.0) + - middleware: littlevgl: update to v8.3.1 + - middleware: fatfs: file name encoding in utf-8 + - middleware: freertos: support nested irq handling + - middleware: hpm_mcl: Optimized motor control foc speed + - samples: drivers: dma src move to dma_general_transfer folder + - samples: lwip: update all static addresses and all gateway addresses + - samples: lwip: lwip_iperf: optimize the interactive log + - samples: tinyusb: device: hid_generic_inout: optimize the python script + - openocd: HPM6750A1 silicon in hpm6750-dual-core.cfg + - header file: update the enet/conctl register files + - header file: Update TRGMUX0 pin input source definition + - header file: update the ADC12 header files + - scripts: ses: organize file in ses according to real path. + - cmake: split gcc and ses source + - board: bump HPM6750 DCDC voltage to 1200mv ### Fixed: + - drivers: pdma: fix scale api issue + - drivers: i2c: update DATACNT processing + - drivers: i2s: fix i2s interrupt workaround in i2s_init + - drivers: pwm: fix pwm capture function error + - drivers: pwm: fix pwm capture configuration error + - drivers: clock: fix error in clock_set_xxx_source + - drivers: wdg: timeout calculation error + - drivers: trgm_drv: bugfix: include error + - drivers: romapi: call fencei after flash erase/write operation + - drivers: watchdog: overflow + - drivers: usb: host controller initialization issue + - drivers: i2s: i2s_enable() issue fix + - middleware: tinyusb: src: class: fix the HID report desc macro + - samples: drivers: adc: optimize all ADC demos + - samples: drivers: adc: fix all channel initializations without a default value + - samples: motor_ctrl: hardware trigger api usage error + - samples: audio_codec: update clock process for 44100 sample rate + - samples: lcdc: boundary pixel is incorrenct - samples: multicore: BOOT_HEADER was missing in multicore core0 example - - samples: jpeg: Fix encoding and decoding problem - - samples: audio codec: wav decoder: fix 32bit wave file playback - - I2S_DMA: fix wav channel not align problem - - i2s_interrupt: fix I2S FIFO overflow - - fix lack of interrupt claim for swi - - driver: watchdog: overflow - - Fix critical section logic issue in dma manager - - Fix the core1 application debugging issue + - samples: drivers: i2s: correct audio data if depth < 32bit. + - samples: hpm_math: fft_perf_test: Fix error printing information + - samples: fix pdm2dao noise problem + - samples: lwip: fix the enet throughput degradation + - soc: correct address overlapping SES XIP linker file + - soc: correct the interrupt context switch issue + - soc: fix Lack of interrupt claim for swi + - boards: fix some rmii reference clock APIs + +### Added: + - boards: add hpm6750evk2 support + - soc: add initfini.c + - drivers: lcdc: add y8 support + - drivers: spi: update data_length processing + - drivers: spi: add api to enable/disable spi dma request + - drivers: pmp: Add pmp_config_entry API + - components: add ipc_event_mgr + - component: spi: add cache maintain + - middleware: add erpc + - samples: lwip: support self-adaptive port speed and duplex mode + - samples: jpeg: support grayscale + - samples: drivers: spi: use api to get data length + - samples: drivers: spi: add interrupt b2b sample + - samples: drivers: mbx: add singlecore samples + - samples: drivers: add dma circle transfer + - samples: drivers: pwm: add pwm capture demo + - samples: provide OTP API demo + - samples: add cherryusb hid/msc/cdc samples + - samples: add Guomi API example + - samples: add erpc sample + - samples: add segger_rtt ## [0.13.0] - 2022-07-31: diff --git a/common/libraries/hpm_sdk/CMakeLists.txt b/common/libraries/hpm_sdk/CMakeLists.txt index af2b422e..5995ac17 100644 --- a/common/libraries/hpm_sdk/CMakeLists.txt +++ b/common/libraries/hpm_sdk/CMakeLists.txt @@ -1,27 +1,20 @@ -# Copyright 2021 hpmicro +# Copyright 2021-2022 HPMicro # SPDX-License-Identifier: BSD-3-Clause cmake_minimum_required(VERSION 3.13) if(${CMAKE_VERSION} VERSION_GREATER_EQUAL 3.20) cmake_policy(SET CMP0116 OLD) endif() +cmake_policy(SET CMP0079 NEW) -set(LIBRARY_OUTPUT_PATH ${PROJECT_BINARY_DIR}/lib) -set(EXECUTABLE_OUTPUT_PATH ${PROJECT_BINARY_DIR}) - -# to store all options -add_library(${HPM_SDK_LIB_ITF} INTERFACE) - -add_library(${HPM_SDK_LIB} STATIC "") -target_link_libraries(${HPM_SDK_LIB} PUBLIC ${HPM_SDK_LIB_ITF}) - -include(cmake/extra_flags.cmake) +if(flash_size) + sdk_linker_global_symbols("_flash_size=${flash_size}") +endif() -include(${HPM_SDK_BASE}/cmake/toolchain.cmake) -enable_language(C CXX ASM) +if(extram_size) + sdk_linker_global_symbols("_extram_size=${extram_size}") +endif() -sdk_linker_global_symbols("_flash_size=${flash_size}") -sdk_linker_global_symbols("_extram_size=${extram_size}") sdk_linker_global_symbols("_heap_size=${HEAP_SIZE}") sdk_linker_global_symbols("_stack_size=${STACK_SIZE}") @@ -96,9 +89,9 @@ else() endif() if(NOT DEFINED USE_PRESET_FLASH_LINKER OR "${USE_PRESET_FLASH_LINKER}" EQUAL "0") - if(DEFINED CUSTOM_LINKER_FILE) + if(DEFINED CUSTOM_GCC_LINKER_FILE) set(USE_CUSTOM_LINKER 1) - set(LINKER_SCRIPT ${CUSTOM_LINKER_FILE}) + set(LINKER_SCRIPT ${CUSTOM_GCC_LINKER_FILE}) else() if(DEFINED USE_LINKER_TEMPLATE) set(USE_CUSTOM_LINKER 1) @@ -111,9 +104,14 @@ if(${EXCLUDE_SDK_STARTUP}) set(USE_CUSTOM_STARTUP 1) endif() -if(DEFINED CUSTOM_STARTUP_FILE) +if(DEFINED CUSTOM_GCC_STARTUP_FILE) set(USE_CUSTOM_STARTUP 1) - sdk_src(${CUSTOM_STARTUP_FILE}) + sdk_gcc_src(${CUSTOM_GCC_STARTUP_FILE}) +endif() + +if(DEFINED CUSTOM_SES_STARTUP_FILE) + set(USE_CUSTOM_STARTUP 1) + sdk_ses_src(${CUSTOM_SES_STARTUP_FILE}) endif() sdk_sys_inc(${SYSROOT_DIR}/include) @@ -156,29 +154,49 @@ endif() sdk_ld_options("-T ${LINKER_SCRIPT}") -file(WRITE ${PROJECT_BINARY_DIR}/misc/empty.c "") -add_executable(${APP_ELF_NAME} ${PROJECT_BINARY_DIR}/misc/empty.c) +set(generated_file_path "${PROJECT_BINARY_DIR}/generated") +# prepare dummy file +set(EMPTY_FILE ${generated_file_path}/misc/empty.c) +file(WRITE ${EMPTY_FILE} "") + +add_executable(${APP_ELF_NAME} ${EMPTY_FILE}) + +# generate SDK version file +execute_process( + COMMAND ${CMAKE_COMMAND} -DHPM_SDK_BASE=${HPM_SDK_BASE} + -DOUT_FILE=${generated_file_path}/include/hpm_sdk_version.h + -P ${HPM_SDK_BASE}/cmake/gen_version_h.cmake + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +sdk_inc(${generated_file_path}/include) set_target_properties(${APP_ELF_NAME} PROPERTIES LINK_DEPENDS ${LINKER_SCRIPT}) if("${TOOLCHAIN_VARIANT}" STREQUAL "nds-gcc") target_link_libraries(${APP_ELF_NAME} - "-Wl,-Map=${PROJECT_BINARY_DIR}/${APP_MAP_NAME}" - ${HPM_SDK_LIB} ${HPM_SDK_LIB_ITF} hpm_sdk_nds_lib_itf app) + "-Wl,-Map=${EXECUTABLE_OUTPUT_PATH}/${APP_MAP_NAME}" + "-Wl,--whole-archive" + ${HPM_SDK_NDSGCC_LIB_ITF} + ${HPM_SDK_GCC_LIB} ${HPM_SDK_GCC_LIB_ITF} + ${HPM_SDK_LIB} ${HPM_SDK_LIB_ITF} app + "-Wl,--no-whole-archive") else() target_link_libraries(${APP_ELF_NAME} - "-Wl,-Map=${PROJECT_BINARY_DIR}/${APP_MAP_NAME}" - ${HPM_SDK_LIB} ${HPM_SDK_LIB_ITF} app) + "-Wl,-Map=${EXECUTABLE_OUTPUT_PATH}/${APP_MAP_NAME}" + "-Wl,--whole-archive" + ${HPM_SDK_GCC_LIB} ${HPM_SDK_GCC_LIB_ITF} + ${HPM_SDK_LIB} ${HPM_SDK_LIB_ITF} app + "-Wl,--no-whole-archive") endif() add_custom_command( TARGET ${APP_ELF_NAME} - COMMAND "${CROSS_COMPILE}objcopy" -O binary -S ${PROJECT_BINARY_DIR}/${APP_ELF_NAME} ${PROJECT_BINARY_DIR}/${APP_BIN_NAME} + COMMAND "${CROSS_COMPILE}objcopy" -O binary -S ${EXECUTABLE_OUTPUT_PATH}/${APP_ELF_NAME} ${EXECUTABLE_OUTPUT_PATH}/${APP_BIN_NAME} ) add_custom_command( TARGET ${APP_ELF_NAME} - COMMAND "${CROSS_COMPILE}objdump" -S -d ${PROJECT_BINARY_DIR}/${APP_ELF_NAME} > ${PROJECT_BINARY_DIR}/${APP_ASM_NAME} + COMMAND "${CROSS_COMPILE}objdump" -S -d ${EXECUTABLE_OUTPUT_PATH}/${APP_ELF_NAME} > ${EXECUTABLE_OUTPUT_PATH}/${APP_ASM_NAME} ) diff --git a/common/libraries/hpm_sdk/LICENSE b/common/libraries/hpm_sdk/LICENSE index d5c5c0ac..fcbba7db 100644 --- a/common/libraries/hpm_sdk/LICENSE +++ b/common/libraries/hpm_sdk/LICENSE @@ -1,7 +1,7 @@ BSD 3-Clause "New" or "Revised" License https://spdx.org/licenses/BSD-3-Clause.html -Copyright (c) 2021-2022, HPMicro. All rights reserved. +Copyright (c) 2021-2023, HPMicro. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/common/libraries/hpm_sdk/README.md b/common/libraries/hpm_sdk/README.md index 886e6b48..87cf018a 100644 --- a/common/libraries/hpm_sdk/README.md +++ b/common/libraries/hpm_sdk/README.md @@ -1,16 +1,55 @@ +``` mermaid +gantt + title HPM SDK Release Plan + dateFormat YYYY-MM-DD + section Mainline Release + v1.1.0 :a1, 2023-01-01, 2023-03-31 + v1.2.0 :a2, 2023-04-01, 2023-06-30 + v1.3.0 :a3, 2023-07-01, 2023-09-30 + v1.4.0 :a4, 2023-10-01, 2023-12-31 +``` + +[中文](README_zh.md) + # HPM SDK Overview The HPM SDK Project is a software development kit based on HPMicro's MCUs, which supports a wide range of MCUs, based on the BSD license, including drivers, middleware and RTOS, such as littlevgl/ lwIP/ TinyUSB/ FreeRTOS, etc. It supports a large number of Boards. -# HPM SDK Quick Start Guide - -## Minium required version of dependencies are: +## SDK Directory Structure + +| Name | Description | +|--------|--------| +| /arch | cpu architecture | +| /boards | board support files | +| /cmake | cmake extensions | +| /components | software components | +| /docs | documentation | +| /drivers | low level driver files | +| /middleware | middleware files | +| /samples | sample source for drivers, middleware, components | +| /scripts | util scripts | +| /soc | SoC specific source | +| /utils | util source | + +## SDK Documentation +- Local: + SDK documentation can be built locally, once it's done, it can be accessed with the following entries: + - >/docs/index.html + - >/docs/index_zh.html + > Please refer to /docs/README.md for more details about documentation building. +- Online: + - http://hpm-sdk.readthedocs.io/ + - http://hpm-sdk-zh.readthedocs.io/ + +## HPM SDK Quick Start Guide + +### Minimum required version of dependencies are: | Name | Version | | -------|---------- | |CMake | 3.13 | | Python | 3.8 | -## Install Dependencies +### Install Dependencies - Ubuntu - install tools @@ -248,3 +287,7 @@ The HPM SDK Project is a software development kit based on HPMicro's MCUs, which Note: openocd executable needs to be found in the PATH variable of current console, otherwise debug configuration will not be generated to project file and needs to be configured manually in Segger Embedded Studio later. # Community Support +- github page: https://hpmicro.github.io +- github: https://github.com/hpmicro/hpm_sdk +- gitee: https://gitee.com/hpmicro/hpm_sdk + diff --git a/common/libraries/hpm_sdk/README_zh.md b/common/libraries/hpm_sdk/README_zh.md index 23904214..85115ee8 100644 --- a/common/libraries/hpm_sdk/README_zh.md +++ b/common/libraries/hpm_sdk/README_zh.md @@ -1,16 +1,55 @@ +``` mermaid +gantt + title HPM SDK Release Plan + dateFormat YYYY-MM-DD + section Mainline Release + v1.1.0 :a1, 2023-01-01, 2023-03-31 + v1.2.0 :a2, 2023-04-01, 2023-06-30 + v1.3.0 :a3, 2023-07-01, 2023-09-30 + v1.4.0 :a4, 2023-10-01, 2023-12-31 +``` + +[English](README.md) + # HPM SDK 概述 HPM SDK项目是基于HPMicro 公司的MCU编写的软件开发包，支持多种MCU。基于BSD许可证，包含了底层驱动，中间件和RTOS，例如littlevgl/ lwIP/ TinyUSB/ FreeRTOS等，支持大量评估板。 -# HPM SDK使用说明 - -## 依赖软件最低版本要求 +## HPM SDK 目录结构 + +| 目录名称 | 描述 | +|--------|--------| +| /arch | cpu架构相关文件 | +| /boards | 板级文件 | +| /cmake | cmake扩展 | +| /components | 软件组件 | +| /docs | 文档 | +| /drivers | 底层驱动文件| +| /middleware | 中间件 | +| /samples | 驱动、中间件以及软件组件示例代码 | +| /scripts | 辅助脚本 | +| /soc | SoC相关文件 | +| /utils | 辅助文件 | + +## SDK文档 +- 本地文档: + SDK文档可以进行本地编译，成功编译之后可以通过以下入口访问本地文档: + - >/docs/index.html + - >/docs/index_zh.html + > 文档编译方式请参考/docs/README.md +- 在线文档： + - http://hpm-sdk.readthedocs.io/ + - http://hpm-sdk-zh.readthedocs.io/ + +## HPM SDK使用说明 + +### 依赖软件最低版本要求 | 软件名称 | 版本号 | |--- | --- | | CMake | 3.13 | | Python | 3.8 | -## 安装依赖 +### 安装依赖 - Ubuntu: - 安装工具: @@ -255,4 +294,7 @@ HPM SDK项目是基于HPMicro 公司的MCU编写的软件开发包，支持多 注意：openocd可执行文件应该可以通过当前终端的PATH环境变量中可以找到, 否则无法在工程文件中生成相应的调试配置，需要之后在Segger Embedded Studio中手工配置。 -# 社区支持 \ No newline at end of file +## 社区支持 +- github page: https://hpmicro.github.io +- github: https://github.com/hpmicro/hpm_sdk +- gitee: https://gitee.com/hpmicro/hpm_sdk diff --git a/common/libraries/hpm_sdk/SConscript b/common/libraries/hpm_sdk/SConscript index f3846c39..0dc79ca7 100644 --- a/common/libraries/hpm_sdk/SConscript +++ b/common/libraries/hpm_sdk/SConscript @@ -36,14 +36,17 @@ if GetDepend(['BSP_USING_WDG']): src += ['drivers/src/hpm_wdg_drv.c'] if GetDepend(['BSP_USING_ADC']): - if GetDepend(['BSP_USING_ADC12']): - src += ['drivers/src/hpm_adc12_drv.c'] - if GetDepend(['BSP_USING_ADC16']): - src += ['drivers/src/hpm_adc16_drv.c'] + if GetDepend(['BSP_USING_ADC12']): + src += ['drivers/src/hpm_adc12_drv.c'] + if GetDepend(['BSP_USING_ADC16']): + src += ['drivers/src/hpm_adc16_drv.c'] if GetDepend(['BSP_USING_CAN']): src += ['drivers/src/hpm_can_drv.c'] +if GetDepend(['BSP_USING_MCAN']): + src += ['drivers/src/hpm_mcan_drv.c'] + if GetDepend(['BSP_USING_ETH']): src += ['drivers/src/hpm_enet_drv.c'] diff --git a/common/libraries/hpm_sdk/VERSION b/common/libraries/hpm_sdk/VERSION index 7be09ab3..85aa594d 100644 --- a/common/libraries/hpm_sdk/VERSION +++ b/common/libraries/hpm_sdk/VERSION @@ -1,5 +1,5 @@ -VERSION_MAJOR = 0 -VERSION_MINOR = 13 -PATCHLEVEL = 1 +VERSION_MAJOR = 1 +VERSION_MINOR = 1 +PATCHLEVEL = 0 VERSION_TWEAK = 0 EXTRAVERSION = 0 diff --git a/common/libraries/hpm_sdk/arch/CMakeLists.txt b/common/libraries/hpm_sdk/arch/CMakeLists.txt index d3b401f3..dbb695b6 100644 --- a/common/libraries/hpm_sdk/arch/CMakeLists.txt +++ b/common/libraries/hpm_sdk/arch/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause sdk_inc(.) diff --git a/common/libraries/hpm_sdk/arch/riscv/riscv_core.h b/common/libraries/hpm_sdk/arch/riscv/riscv_core.h index 21e0343d..4f95f4db 100644 --- a/common/libraries/hpm_sdk/arch/riscv/riscv_core.h +++ b/common/libraries/hpm_sdk/arch/riscv/riscv_core.h @@ -37,7 +37,17 @@ extern "C" { * * @return csr value before cleared */ -#define read_clear_csr(csr_num, bit) ({ uint32_t v; __asm volatile("csrrc %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; }) +#define read_clear_csr(csr_num, bit) ({ volatile uint32_t v = 0; __asm volatile("csrrc %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; }) + +/** + * @brief read and set bits in csr + * + * @param csr_num specific csr + * @param bit bits to be set + * + * @return csr value before set + */ +#define read_set_csr(csr_num, bit) ({ volatile uint32_t v = 0; __asm volatile("csrrs %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; }) /** * @brief set bits in csr @@ -77,6 +87,21 @@ extern "C" { */ #define fencei() __asm volatile("fence.i") +/** + * @brief enable fpu + */ +#define enable_fpu() read_set_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK) + +/** + * @brief disable fpu + */ +#define disable_fpu() read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK) + +/** + * @brief clear fcsr + */ +#define clear_fcsr() write_fcsr(0) + #ifdef __cplusplus } #endif diff --git a/common/libraries/hpm_sdk/boards/CMakeLists.txt b/common/libraries/hpm_sdk/boards/CMakeLists.txt index f940f2cc..b5b77b80 100644 --- a/common/libraries/hpm_sdk/boards/CMakeLists.txt +++ b/common/libraries/hpm_sdk/boards/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause add_subdirectory(${HPM_BOARD_DIR}) diff --git a/common/libraries/hpm_sdk/boards/hpm6300evk/CMakeLists.txt b/common/libraries/hpm_sdk/boards/hpm6300evk/CMakeLists.txt index 120a0326..c4ccc137 100644 --- a/common/libraries/hpm_sdk/boards/hpm6300evk/CMakeLists.txt +++ b/common/libraries/hpm_sdk/boards/hpm6300evk/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2022 hpmicro +# Copyright (c) 2022 HPMicro # SPDX-License-Identifier: BSD-3-Clause sdk_inc(.) diff --git a/common/libraries/hpm_sdk/boards/hpm6300evk/README.md b/common/libraries/hpm_sdk/boards/hpm6300evk/README.md deleted file mode 100644 index 3f8bb834..00000000 --- a/common/libraries/hpm_sdk/boards/hpm6300evk/README.md +++ /dev/null @@ -1,75 +0,0 @@ -# HPM6300EVK - - -::::{important} -:::{note} -Need to supplement the content of each module -::: -:::: - -## Overview - -version -Board overall -Board overall hpm6300evk - -- Console serial port parameters: - - - Baud rate: 115200 - - Data bits: 8 bits - - Check Digit: None - - Stop bit: 1 - - Flow Control Bits: None - - Data encoding method: ASCII - -## DIP Switch S1 - -- Bit 1 and 2 controls boot mode - -| bit[2:1] | Description | -| -------- | ---------------------------- | -| OFF, OFF | Boot from Quad SPI NOR flash | -| OFF, ON | Serial boot | -| ON, OFF | ISP | - -(lab_hpm6300_evk_board)= -## Button - -(lab_hpm6300_evk_board_buttons)= -| Function | Position | -| ---- | -------- | -|PBUTN (sw3) |Power Button, TinyUF2 Boot Button, GPIO Button | -|WBUTN (sw1) | WAKE UP Button | -|RESET (sw2) | Reset Button | - -## Pin Description - -- SPI Pin： - -| Function | Position | -| ---- | -------- | -| SPI3.CSN | J28[24] | -| SPI3.SCLK | J28[23] | -| SPI3.MISO | J28[21] | -| SPI3.MOSI | J28[19] | - -- I2C Pin： - -| Function | Position | -| ---- | -------- | -| I2C0.SCL | J28[13] | -| I2C0.SDA | J28[15] | - -- ACMP Pin - -| Function | Position | -| ---- | -------- | -| CMP.INN5 | J26[7] | -| CMP.COMP_1 | J26[5] | - -- GPTMR Pin - -| Function | Position | -| ---- | -------- | -| GPTMR2.CAPT_2 | J28[40] | -| GPTMR2.COMP_2 | J28[35] | \ No newline at end of file diff --git a/common/libraries/hpm_sdk/boards/hpm6300evk/README_zh.md b/common/libraries/hpm_sdk/boards/hpm6300evk/README_zh.md deleted file mode 100644 index e5d3b3fc..00000000 --- a/common/libraries/hpm_sdk/boards/hpm6300evk/README_zh.md +++ /dev/null @@ -1,73 +0,0 @@ -# HPM6300EVK开发板 - - -::::{important} -:::{note} -添加内容 -::: -:::: - -## 概述 - - -- 控制台串口参数： - - - 波特率：115200 - - 数据位：8位 - - 校验位：无 - - 停止位：1 - - 流控位：无 - - 数据编码方式：ASCII - -## 拨码开关 S1 - -- Bit 1，2控制启动模式 - -| Bit[2:1] | 功能描述 | -| -------- | ----------------------- | -| OFF, OFF | Quad SPI NOR flash 启动 | -| OFF, ON | 串行启动 | -| ON, OFF | 在系统编程 | - -(lab_hpm6300_evk_board)= -## 按键 - -(lab_hpm6300_evk_board_buttons)= -| 名称 | 功能 | -| ---- | -------- | -|PBUTN (sw3) | 电源按键, TinyUF2 Boot按键, GPIO 按键| -|WBUTN (sw1) | WAKE UP 按键| -|RESET (sw2) | Reset 按键| - - -## 引脚描述 - -- SPI引脚： - -| 功能 | 位置 | -| ---- | -------- | -| SPI3.CSN | J28[24] | -| SPI3.SCLK | J28[23] | -| SPI3.MISO | J28[21] | -| SPI3.MOSI | J28[19] | - -- I2C引脚： - -| 功能 | 位置 | -| ---- | -------- | -| I2C0.SCL | J28[13] | -| I2C0.SDA | J28[15] | - -- ACMP引脚 - -| 功能 | 位置 | -| ---- | -------- | -| CMP.INN5 | J26[7] | -| CMP.COMP_1 | J26[5] | - -- GPTMR引脚 - -| 功能 | 位置 | -| ---- | -------- | -| GPTMR2.CAPT_2 | J28[40] | -| GPTMR2.COMP_2 | J28[35] | diff --git a/common/libraries/hpm_sdk/boards/hpm6300evk/SConscript b/common/libraries/hpm_sdk/boards/hpm6300evk/SConscript deleted file mode 100644 index 7c742f69..00000000 --- a/common/libraries/hpm_sdk/boards/hpm6300evk/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -import rtconfig - -from building import * - -cwd = GetCurrentDir() - -src = Glob('*.c') - -CPPDEFINES=[] -CPPPATH = [cwd] - -group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) - -Return('group') diff --git a/common/libraries/hpm_sdk/boards/hpm6300evk/board.c b/common/libraries/hpm_sdk/boards/hpm6300evk/board.c index 28e3168d..dcd21e57 100644 --- a/common/libraries/hpm_sdk/boards/hpm6300evk/board.c +++ b/common/libraries/hpm_sdk/boards/hpm6300evk/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 HPMicro + * Copyright (c) 2022-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -10,7 +10,6 @@ #include "hpm_lcdc_drv.h" #include "hpm_i2c_drv.h" #include "hpm_gpio_drv.h" -#include "hpm_debug_console.h" #include "hpm_femc_drv.h" #include "pinmux.h" #include "hpm_pmp_drv.h" @@ -21,7 +20,9 @@ #include "hpm_pwm_drv.h" #include "hpm_trgm_drv.h" #include "hpm_pllctlv2_drv.h" +#include "hpm_enet_drv.h" #include "hpm_pcfg_drv.h" +#include "hpm_sdk_version.h" static board_timer_cb timer_cb; @@ -88,19 +89,24 @@ ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATU void board_init_console(void) { -#if console_type_uart == BOARD_CONSOLE_TYPE +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if CONSOLE_TYPE_UART == BOARD_CONSOLE_TYPE console_config_t cfg; + /* uart needs to configure pin function before enabling clock, otherwise the level change of + uart rx pin when configuring pin function will cause a wrong data to be received. + And a uart rx dma request will be generated by default uart fifo dma trigger level. */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_BASE); + /* Configure the UART clock to 24MHz */ clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; cfg.base = (uint32_t) BOARD_CONSOLE_BASE; cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); cfg.baudrate = BOARD_CONSOLE_BAUDRATE; - init_uart_pins((UART_Type *) cfg.base); - if (status_success != console_init(&cfg)) { /* failed to initialize debug console */ while (1) { @@ -110,6 +116,7 @@ void board_init_console(void) while (1) { } #endif +#endif } void board_print_clock_freq(void) @@ -123,18 +130,15 @@ void board_print_clock_freq(void) printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); - printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram)); + printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); printf("==============================\n"); } void board_init_uart(UART_Type *ptr) { + /* configure uart's pin before opening uart's clock */ init_uart_pins(ptr); -} - -void board_init_ahb(void) -{ - clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2);/*200m hz*/ + board_init_uart_clock(ptr); } void board_print_banner(void) @@ -150,6 +154,9 @@ void board_print_banner(void) $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ ----------------------------------------------------------------------\n"}; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif printf("%s", banner); } @@ -165,7 +172,6 @@ void board_init(void) board_init_clock(); board_init_console(); board_init_pmp(); - board_init_ahb(); #if BOARD_SHOW_CLOCK board_print_clock_freq(); #endif @@ -179,13 +185,13 @@ void board_init_sdram_pins(void) init_sdram_pins(); } -uint32_t board_init_dram_clock(void) +uint32_t board_init_femc_clock(void) { - clock_add_to_group(clock_dram, 0); - /* Configure the SDRAM to 133MHz */ - clock_set_source_divider(clock_dram, clk_src_pll0_clk1, 2U); + clock_add_to_group(clock_femc, 0); + /* Configure the SDRAM to 166MHz */ + clock_set_source_divider(clock_femc, clk_src_pll0_clk1, 2U); - return clock_get_frequency(clock_dram); + return clock_get_frequency(clock_femc); } void board_delay_us(uint32_t us) @@ -240,7 +246,7 @@ uint32_t board_init_spi_clock(SPI_Type *ptr) if (ptr == HPM_SPI3) { /* SPI3 clock configure */ clock_add_to_group(clock_spi3, 0); - clock_set_source_divider(clock_spi3, clk_src_osc24m, 1U); + clock_set_source_divider(clock_spi3, clk_src_pll0_clk0, 5U); /* 80MHz */ return clock_get_frequency(clock_spi3); } @@ -269,10 +275,15 @@ void board_write_spi_cs(uint32_t pin, uint8_t state) gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); } +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + void board_init_led_pins(void) { init_led_pins(); - gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); + gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level()); } void board_led_toggle(void) @@ -345,24 +356,23 @@ void board_init_clock(void) /* Select clock setting preset1 */ sysctl_clock_set_preset(HPM_SYSCTL, 2); } + + /* Add most Clocks to group 0 */ + /* not open uart clock in this API, uart should configure pin function before opening clock */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_ahbp, 0); clock_add_to_group(clock_axic, 0); clock_add_to_group(clock_axis, 0); clock_add_to_group(clock_mchtmr0, 0); - clock_add_to_group(clock_dram, 0); + clock_add_to_group(clock_femc, 0); clock_add_to_group(clock_xpi0, 0); clock_add_to_group(clock_xpi1, 0); clock_add_to_group(clock_gptmr0, 0); clock_add_to_group(clock_gptmr1, 0); clock_add_to_group(clock_gptmr2, 0); clock_add_to_group(clock_gptmr3, 0); - clock_add_to_group(clock_uart0, 0); - clock_add_to_group(clock_uart1, 0); - clock_add_to_group(clock_uart2, 0); - clock_add_to_group(clock_uart3, 0); clock_add_to_group(clock_i2c0, 0); clock_add_to_group(clock_i2c1, 0); clock_add_to_group(clock_i2c2, 0); @@ -410,10 +420,25 @@ void board_init_clock(void) /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); - /* Configure CPU0 to 480MHz */ + /* + * Configure CPU0 to 480MHz + * + * NOTE: The PLL2 is disabled by default, and it will be enabled automatically if + * it is required by any nodes. + * Here the PLl2 clock is enabled after switching CPU clock source to it + */ clock_set_source_divider(clock_cpu0, clk_src_pll1_clk0, 1); + /* Configure PLL1_CLK0 Post Divider to 1.2 */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 1); + /* Configure PLL1 clock frequencey to 576MHz, the PLL1_CLK0 frequency =- 576MHz / 1.2 = 480MHz */ + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 576000000); clock_update_core_clock(); + + /* Configure AHB to 200MHz */ + clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); + + clock_set_source_divider(clock_aud1, clk_src_pll2_clk0, 46); /* config clock_aud1 for 44100*n sample rate */ } uint32_t board_init_adc12_clock(ADC16_Type *ptr) @@ -456,6 +481,11 @@ uint32_t board_init_pdm_clock(void) return clock_get_frequency(clock_pdm); } +hpm_stat_t board_set_audio_pll_clock(uint32_t freq) +{ + return pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 2, freq); /* pll2clk */ +} + uint32_t board_init_i2s_clock(I2S_Type *ptr) { return 0; @@ -472,7 +502,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) if (ptr == HPM_DAC) { if (clk_src_ahb == true) { - /* Configure the DAC clock to 133MHz */ + /* Configure the DAC clock to 160MHz */ clock_set_dac_source(clock_dac0, clk_dac_src_ahb); } else { /* Configure the DAC clock to 166MHz */ @@ -514,23 +544,23 @@ uint32_t board_init_can_clock(CAN_Type *ptr) */ void _init_ext_ram(void) { - uint32_t dram_clk_in_hz; + uint32_t femc_clk_in_hz; board_init_sdram_pins(); - dram_clk_in_hz = board_init_dram_clock(); + femc_clk_in_hz = board_init_femc_clock(); - dram_config_t config = {0}; - dram_sdram_config_t sdram_config = {0}; + femc_config_t config = {0}; + femc_sdram_config_t sdram_config = {0}; - dram_default_config(HPM_DRAM, &config); - config.dqs = DRAM_DQS_INTERNAL; - dram_init(HPM_DRAM, &config); + femc_default_config(HPM_FEMC, &config); + config.dqs = FEMC_DQS_INTERNAL; + femc_init(HPM_FEMC, &config); - sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; + sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4; sdram_config.prescaler = 0x3; sdram_config.burst_len_in_byte = 8; sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; - sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; sdram_config.precharge_to_act_in_ns = 18; /* Trp */ sdram_config.act_to_rw_in_ns = 18; /* Trcd */ @@ -543,7 +573,7 @@ void _init_ext_ram(void) sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ sdram_config.act_to_act_in_ns = 12; /* Trrd */ sdram_config.idle_timeout_in_ns = 6; - sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; + sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED; sdram_config.cs = BOARD_SDRAM_CS; sdram_config.base_address = BOARD_SDRAM_ADDRESS; @@ -554,7 +584,7 @@ void _init_ext_ram(void) sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; sdram_config.delay_cell_value = 29; - dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); + femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } #endif @@ -643,6 +673,9 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) } else { return status_invalid_argument; } + + enet_rmii_enable_clock(ptr, internal); + return status_success; } @@ -658,6 +691,11 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) return status_success; } +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) +{ + return status_success; +} + void board_init_dac_pins(DAC_Type *ptr) { init_dac_pins(ptr); @@ -668,15 +706,50 @@ uint32_t board_init_uart_clock(UART_Type *ptr) uint32_t freq = 0U; if (ptr == HPM_UART0) { clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + clock_add_to_group(clock_uart0, 0); freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART1) { clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); + clock_add_to_group(clock_uart1, 0); freq = clock_get_frequency(clock_uart1); } else if (ptr == HPM_UART2) { clock_set_source_divider(clock_uart2, clk_src_osc24m, 1); + clock_add_to_group(clock_uart2, 0); freq = clock_get_frequency(clock_uart2); } else { /* Not supported */ } return freq; } + +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) +{ + return enet_pbl_16; +} + +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_enable_irq(IRQn_ENET0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_disable_irq(IRQn_ENET0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +void board_init_enet_pps_pins(ENET_Type *ptr) +{ + init_enet_pps_pins(); +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/boards/hpm6300evk/board.h b/common/libraries/hpm_sdk/boards/hpm6300evk/board.h index 72d774d7..27bed40c 100644 --- a/common/libraries/hpm_sdk/boards/hpm6300evk/board.h +++ b/common/libraries/hpm_sdk/boards/hpm6300evk/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,6 +13,9 @@ #include "hpm_soc.h" #include "hpm_soc_feature.h" #include "pinmux.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif #define BOARD_NAME "hpm6300evk" #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) @@ -39,12 +42,14 @@ #define BOARD_APP_UART_BAUDRATE (115200UL) #define BOARD_APP_UART_CLK_NAME clock_uart0 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX #ifndef BOARD_CONSOLE_TYPE -#define BOARD_CONSOLE_TYPE console_type_uart +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif -#if console_type_uart == BOARD_CONSOLE_TYPE +#if CONSOLE_TYPE_UART == BOARD_CONSOLE_TYPE #ifndef BOARD_CONSOLE_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 #define BOARD_CONSOLE_BASE HPM_UART0 @@ -80,8 +85,8 @@ /* sdram section */ #define BOARD_SDRAM_ADDRESS (0x40000000UL) #define BOARD_SDRAM_SIZE (32*SIZE_1MB) -#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS #define BOARD_SDRAM_REFRESH_COUNT (8192UL) #define BOARD_SDRAM_REFRESH_IN_MS (64UL) #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) @@ -93,11 +98,11 @@ /* i2c section */ #define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 #define BOARD_APP_I2C_CLK_NAME clock_i2c0 #define BOARD_APP_I2C_DMA HPM_HDMA #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX #define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 -#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 /* ACMP desction */ #define BOARD_ACMP HPM_ACMP @@ -119,6 +124,7 @@ #define BOARD_GPTMR_CHANNEL 0 #define BOARD_GPTMR_PWM HPM_GPTMR2 #define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr2 /* gpio section */ #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ @@ -141,14 +147,13 @@ /* spi section */ #define BOARD_APP_SPI_BASE HPM_SPI3 -#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) -#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) +#define BOARD_APP_SPI_CLK_NAME clock_spi3 +#define BOARD_APP_SPI_IRQ IRQn_SPI3 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) #define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI3_RX -#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI3_TX -#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 #define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 #define BOARD_SPI_CS_PIN IOC_PAD_PC18 #define BOARD_SPI_CS_ACTIVE_LEVEL (0U) @@ -167,6 +172,10 @@ #define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0 /* enet section */ +#define BOARD_ENET_PPS HPM_ENET0 +#define BOARD_ENET_PPS_IDX enet_pps_0 +#define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 + #define BOARD_ENET_RMII HPM_ENET0 #define BOARD_ENET_RMII_RST_GPIO #define BOARD_ENET_RMII_RST_GPIO_INDEX @@ -241,15 +250,16 @@ #define BOARD_BLDCPWM_CMP_INDEX_3 (3U) #define BOARD_BLDCPWM_CMP_INDEX_4 (4U) #define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) /*HALL define*/ #define BOARD_BLDC_HALL_BASE HPM_HALL0 #define BOARD_BLDC_HALL_TRGM HPM_TRGM0 #define BOARD_BLDC_HALL_IRQ IRQn_HALL0 -#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN8 -#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN7 -#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN6 +#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P8 +#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 +#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 #define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) @@ -259,8 +269,8 @@ #define BOARD_BLDC_QEI_BASE HPM_QEI0 #define BOARD_BLDC_QEI_IRQ IRQn_QEI0 #define BOARD_BLDC_QEI_TRGM HPM_TRGM0 -#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN9 -#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM0_INPUT_SRC_TRGM0_IN10 +#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P9 +#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P10 #define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) #define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 #define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) @@ -280,7 +290,7 @@ #define BOARD_BLDC_ADC_W_BASE HPM_ADC2 #define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete -#define BOARD_BLDC_ADC_CH_U (14U) +#define BOARD_BLDC_ADC_CH_U (7U) #define BOARD_BLDC_ADC_CH_V (12U) #define BOARD_BLDC_ADC_CH_W (5U) #define BOARD_BLDC_ADC_IRQn IRQn_ADC1 @@ -297,6 +307,7 @@ #define BOARD_APP_PWM_OUT1 0 #define BOARD_APP_PWM_OUT2 1 #define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM0 #define BOARD_CPU_FREQ (480000000UL) @@ -328,7 +339,7 @@ void board_init_i2c(I2C_Type *ptr); void board_init_can(CAN_Type *ptr); -uint32_t board_init_dram_clock(void); +uint32_t board_init_femc_clock(void); void board_init_sdram_pins(void); void board_init_gpio_pins(void); @@ -355,6 +366,7 @@ void board_init_dac_pins(DAC_Type *ptr); uint32_t board_init_can_clock(CAN_Type *ptr); +hpm_stat_t board_set_audio_pll_clock(uint32_t freq); uint32_t board_init_i2s_clock(I2S_Type *ptr); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); @@ -368,10 +380,14 @@ void board_init_usb_pins(void); void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); uint8_t board_get_usb_id_status(void); +void board_init_enet_pps_pins(ENET_Type *ptr); +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); - +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); /* * @brief Initialize PMP and PMA for but not limited to the following purposes: * -- non-cacheable memory initialization @@ -387,6 +403,11 @@ void board_ungate_mchtmr_at_lp_mode(void); /* Initialize the UART clock */ uint32_t board_init_uart_clock(UART_Type *ptr); +/* + * Get GPIO pin level of onboard LED + */ +uint8_t board_get_led_gpio_off_level(void); + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/common/libraries/hpm_sdk/boards/hpm6300evk/pinmux.c b/common/libraries/hpm_sdk/boards/hpm6300evk/pinmux.c index 202a4779..0a73518a 100644 --- a/common/libraries/hpm_sdk/boards/hpm6300evk/pinmux.c +++ b/common/libraries/hpm_sdk/boards/hpm6300evk/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -28,6 +28,9 @@ void init_uart_pins(UART_Type *ptr) } else if (ptr == HPM_UART2) { HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_UART2_TXD; HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_UART2_RXD; + } else if (ptr == HPM_PUART) { + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_PUART_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_PUART_TXD; } } @@ -110,6 +113,43 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); } +void init_sram_pins(void) +{ + /* Non-MUX */ /* MUX */ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A0 */ /* A16 */ + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A1 */ /* A17 */ + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A2 */ /* A18 */ + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A3 */ /* A19 */ + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A4 */ /* A20 */ + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A5 */ /* A21 */ + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A6 */ /* A22 */ + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A7 */ /* A23 */ + + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D0 */ /* AD0 */ + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D1 */ /* AD1 */ + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D2 */ /* AD2 */ + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D3 */ /* AD3 */ + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D4 */ /* AD4 */ + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D5 */ /* AD5 */ + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D6 */ /* AD6 */ + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D7 */ /* AD7 */ + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D8 */ /* AD8 */ + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D9 */ /* AD9 */ + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D10 */ /* AD10 */ + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D11 */ /* AD11 */ + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D12 */ /* AD12 */ + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D13 */ /* AD13 */ + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D14 */ /* AD14 */ + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D15 */ /* AD15 */ + + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #CE */ + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #OE */ + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #WE */ + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #UB */ + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #LB */ + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #ADV */ +} + void init_gpio_pins(void) { /* configure pad setting: pull enable and pull up, schmitt trigger enable */ @@ -287,11 +327,7 @@ void init_clk_obs_pins(void) void init_led_pins(void) { - /* Pull up */ - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); - HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_GPIO_A_07; - HPM_IOC->PAD[IOC_PAD_PA07].PAD_CTL = pad_ctl; } void init_dac_pins(DAC_Type *ptr) @@ -306,3 +342,9 @@ void init_trgmux_pins(uint32_t pin) /* all trgmux pin ALT_SELECT fixed to 16*/ HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16); } + +void init_enet_pps_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_ETH0_EVTO_0; + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_ETH0_EVTO_1; +} diff --git a/common/libraries/hpm_sdk/boards/hpm6300evk/pinmux.h b/common/libraries/hpm_sdk/boards/hpm6300evk/pinmux.h index 66b1413d..e2701eb6 100644 --- a/common/libraries/hpm_sdk/boards/hpm6300evk/pinmux.h +++ b/common/libraries/hpm_sdk/boards/hpm6300evk/pinmux.h @@ -1,5 +1,5 @@ /* - *Copyright (c) 2022 hpmicro + *Copyright (c) 2022 HPMicro * *SPDX-License-Identifier: BSD-3-Clause * @@ -14,6 +14,7 @@ extern "C" { void init_uart_pins(UART_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_sdram_pins(void); +void init_sram_pins(void); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); @@ -35,6 +36,7 @@ void init_rgb_pwm_pins(void); void init_i2c_pins_as_gpio(I2C_Type *ptr); void init_led_pins(void); void init_trgmux_pins(uint32_t pin); +void init_enet_pps_pins(void); #ifdef __cplusplus } #endif diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk/CMakeLists.txt b/common/libraries/hpm_sdk/boards/hpm6750evk/CMakeLists.txt index 1fadcae5..b24aa55f 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evk/CMakeLists.txt +++ b/common/libraries/hpm_sdk/boards/hpm6750evk/CMakeLists.txt @@ -1,17 +1,9 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause -if(BOARD_LCD_WIDTH) -sdk_compile_definitions("-DBOARD_LCD_WIDTH=${BOARD_LCD_WIDTH}") -endif() - -if(BOARD_LCD_HEIGHT) -sdk_compile_definitions("-DBOARD_LCD_HEIGHT=${BOARD_LCD_HEIGHT}") -endif() - -if(BUILD_FOR_SECONDARY_CORE) -sdk_compile_definitions(BOARD_RUNNING_CORE=HPM_CORE1) -endif() +sdk_compile_definitions_ifdef(BOARD_LCD_WIDTH "-DBOARD_LCD_WIDTH=${BOARD_LCD_WIDTH}") +sdk_compile_definitions_ifdef(BOARD_LCD_HEIGHT "-DBOARD_LCD_HEIGHT=${BOARD_LCD_HEIGHT}") +sdk_compile_definitions_ifdef(BUILD_FOR_SECONDARY_CORE BOARD_RUNNING_CORE=HPM_CORE1) sdk_inc(.) sdk_src(pinmux.c) diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk/README.md b/common/libraries/hpm_sdk/boards/hpm6750evk/README.md deleted file mode 100644 index 97772a5b..00000000 --- a/common/libraries/hpm_sdk/boards/hpm6750evk/README.md +++ /dev/null @@ -1,104 +0,0 @@ -# HPM6750EVK - -## Overview - -The HPM6750 is a dual-core flashless MCU running 816Mhz. It has a 2MB continuous on-chip ram. Also, it provides various memory interfaces, including SDRAM, Quad SPI NOR Flash, SD/eMMC. It integrates rich audio and video interfaces, including LCD, pixel DMA, camera， and I2S audio interfaces. - - ![hpm6750evk](../../doc/images/boards/hpm6750evk/hpm6750evk.png "hpm6750evk") - -## Hardware - -- HPM6750IVM MCU (816Mhz, 2MB OCRAM) -- Onboard Memory - - 256Mb SDRAM - - 128Mb Quad SPI NOR Flash -- Display & Camera - - LCD connector - - Camera (DVP) -- Ethernet - - 1000 Mbits PHY - - 100 Mbits PHY -- USB - - USB type C (USB 2.0 OTG) connector x3 -- Audio - - Line in - - Mic - - Speaker - - DAO -- Others - - TF Slot - - FT2232 - - Beeper - - RGB LED - - CAN -- Expansion port - - Motor control - -## DIP Switch S1 - -- Bit 1 and 2 controls boot mode - -| bit[2:1] | Description | -| -------- | ---------------------------- | -| OFF, OFF | Boot from Quad SPI NOR flash | -| OFF, ON | Serial boot | -| ON, OFF | ISP | - -- Change the position of bit 3 to select between PWM and 1000Mbit ethernet - -| Bit3 | Description | -| ---- | -------------- | -| OFF | 1000Mbits ENET | -| ON | PWM | - -(lab_hpm6750_evk_board)= -## Button -(lab_hpm6750_evk_board_buttons)= -| Name | FUNCTIONS | -| ---- | -------- | -|PBUTN (S2) | Power Button, TinyUF2 Boot Button, GPIO Button | -|WBUTN (S3) | WAKE UP Button | -|RESET (S4) | Reset Button | - -## Pin Description - -- PWM Pin: - - ![image-1](../../doc/images/boards/hpm6750evk/hpm6750evk_pwm_output_pin.png "image-1") - -- SPI Pin： - -| Function | Position | -| ---- | -------- | -| SPI2.CSN | J20[6] | -| SPI2.SCLK | J20[7] | -| SPI2.MISO | J20[8] | -| SPI2.MOSI | J20[9] | - -- I2C Pin： - -| Function | Position | -| ---- | -------- | -| I2C0.SCL | J20[3] | -| I2C0.SDA | J20[4] | - -- UART for core1 debug console - -| Function | Position | -| ---- | -------- | -| UART13.TXD | J20[5] | -| UART13.RXD | J20[6] | - -- ACMP Pin - -| Function | Position | -| ---- | -------- | -| CMP.INN6 | J12[8] | -| CMP.COMP_1 | J12[6] | - -- GPTMR Pin - -| Function | Function | -| ---- | -------- | -| GPTMR4.CAPT_1 | J12[6] | -| GPTMR3.COMP_1 | J12[7] | diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk/README_zh.md b/common/libraries/hpm_sdk/boards/hpm6750evk/README_zh.md deleted file mode 100644 index 80dfcabb..00000000 --- a/common/libraries/hpm_sdk/boards/hpm6750evk/README_zh.md +++ /dev/null @@ -1,107 +0,0 @@ -# HPM6750EVK开发板 - -## 概述 - -HPM6750是一款主频达816Mhz的双核微控制器。该芯片拥有最大2M字节的连续片上RAM，并集成了丰富的存储接口，如SDRAM，Quad SPI NOR flash， SD/eMMC卡。同时它也提供多种音视频接口包括LCD显示，像素DMA，摄像头以及I2S音频接口。 - - ![hpm6750evk](../../doc/images/boards/hpm6750evk/hpm6750evk.png "hpm6750evk") - -## 板上硬件资源 - -- HPM6750IVM 微控制器 (主频816Mhz, 2MB片上内存) -- 板载存储 - - 256Mb SDRAM - - 128Mb Quad SPI NOR Flash -- 显示/摄像头 - - LCD接口 - - 摄像头(DVP)接口 -- 以太网 - - 1000 Mbits PHY - - 100 Mbits PHY -- USB - - USB type C (USB 2.0 OTG) connector x3 -- 音频 - - Line in - - Mic - - Speaker - - DAO -- 其他 - - TF卡槽 - - FT2232 - - 蜂鸣器 - - RGB LED - - CAN -- 扩展口 - - 电机控制 - -## 拨码开关 S1 - -- Bit 1，2控制启动模式 - -| Bit[2:1] | 功能描述 | -| -------- | ----------------------- | -| OFF, OFF | Quad SPI NOR flash 启动 | -| OFF, ON | 串行启动 | -| ON, OFF | 在系统编程 | - -- Bit 3用于选择PWM或是千兆网口 - -| Bit3 | 功能描述 | -| ---- | -------- | -| OFF | 千兆网口 | -| ON | PWM | - -(lab_hpm6750_evk_board)= -## 按键 - -(lab_hpm6750_evk_board_buttons)= -| 名称 | 功能 | -| ---- | -------- | -|PBUTN (S2) | 电源按键, TinyUF2 Boot按键, GPIO 按键| -|WBUTN (S3) | WAKE UP 按键| -|RESET (S4) | Reset 按键| - -## 引脚描述 - -- J12端子的 `P-UH 、P-UL`引脚为PWM输出引脚，如下图所示 - - ![image-1](../../doc/images/boards/hpm6750evk/hpm6750evk_pwm_output_pin.png "image-1") - -- SPI引脚： - -| 功能 | 位置 | -| ---- | -------- | -| SPI2.CSN | J20[6] | -| SPI2.SCLK | J20[7] | -| SPI2.MISO | J20[8] | -| SPI2.MOSI | J20[9] | - -- I2C引脚： - -| 功能 | 位置 | -| ---- | -------- | -| I2C0.SCL | J20[3] | -| I2C0.SDA | J20[4] | - -- CORE1调试串口引脚： - -| 功能 | 位置 | -| ---- | -------- | -| UART13.TXD | J20[5] | -| UART13.RXD | J20[6] | - -- ACMP引脚 - -| 功能 | 位置 | -| ---- | -------- | -| CMP.INN6 | J12[8] | -| CMP.COMP_1 | J12[6] | - -- GPTMR引脚 - -| 功能 | 位置 | -| ---- | -------- | -| GPTMR4.CAPT_1 | J12[6] | -| GPTMR3.COMP_1 | J12[7] | - - diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk/SConscript b/common/libraries/hpm_sdk/boards/hpm6750evk/SConscript deleted file mode 100644 index 7c742f69..00000000 --- a/common/libraries/hpm_sdk/boards/hpm6750evk/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -import rtconfig - -from building import * - -cwd = GetCurrentDir() - -src = Glob('*.c') - -CPPDEFINES=[] -CPPPATH = [cwd] - -group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) - -Return('group') diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk/board.c b/common/libraries/hpm_sdk/boards/hpm6750evk/board.c index 7dabe862..36b2c752 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evk/board.c +++ b/common/libraries/hpm_sdk/boards/hpm6750evk/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -10,7 +10,6 @@ #include "hpm_lcdc_drv.h" #include "hpm_i2c_drv.h" #include "hpm_gpio_drv.h" -#include "hpm_debug_console.h" #include "hpm_femc_drv.h" #include "pinmux.h" #include "hpm_pmp_drv.h" @@ -22,8 +21,11 @@ #include "hpm_trgm_drv.h" #include "hpm_pllctl_drv.h" #include "hpm_enet_drv.h" +#include "hpm_pcfg_drv.h" +#include "hpm_sdk_version.h" static board_timer_cb timer_cb; +static bool invert_led_level; /** * @brief FLASH configuration option definitions: @@ -79,7 +81,7 @@ static board_timer_cb timer_cb; * 0 - 4MB / 1 - 8MB / 2 - 16MB */ #if defined(FLASH_XIP) && FLASH_XIP -__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; +__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x1000, 0x0}; #endif #if defined(FLASH_UF2) && FLASH_UF2 @@ -88,26 +90,33 @@ ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATU void board_init_console(void) { -#if BOARD_CONSOLE_TYPE == console_type_uart +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART console_config_t cfg; + /* uart needs to configure pin function before enabling clock, otherwise the level change of + uart rx pin when configuring pin function will cause a wrong data to be received. + And a uart rx dma request will be generated by default uart fifo dma trigger level. */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_BASE); + /* Configure the UART clock to 24MHz */ clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; cfg.base = (uint32_t) BOARD_CONSOLE_BASE; cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); cfg.baudrate = BOARD_CONSOLE_BAUDRATE; - init_uart_pins((UART_Type *) cfg.base); - if (status_success != console_init(&cfg)) { /* failed to initialize debug console */ while (1) { } } #else - while(1); + while (1) { + } +#endif #endif } @@ -126,7 +135,7 @@ void board_print_clock_freq(void) printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); - printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram)); + printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); printf("display:\t %luHz\n", clock_get_frequency(clock_display)); printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); @@ -137,12 +146,9 @@ void board_print_clock_freq(void) void board_init_uart(UART_Type *ptr) { + /* configure uart's pin before opening uart's clock */ init_uart_pins(ptr); -} - -void board_init_ahb(void) -{ - clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/ + board_init_uart_clock(ptr); } void board_print_banner(void) @@ -158,11 +164,17 @@ void board_print_banner(void) $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ ----------------------------------------------------------------------\n"}; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif printf("%s", banner); } static void board_turnoff_rgb_led(void) { + uint8_t p11_stat; + uint8_t p12_stat; + uint8_t p13_stat; uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; @@ -171,6 +183,23 @@ static void board_turnoff_rgb_led(void) HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; + + p11_stat = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 11); + p12_stat = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 12); + p13_stat = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 13); + + invert_led_level = false; + /* + * check led gpio level + */ + if ((p11_stat & p12_stat & p13_stat) == 0) { + /* Rev B */ + invert_led_level = true; + pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); + HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; + } } void board_ungate_mchtmr_at_lp_mode(void) @@ -185,7 +214,6 @@ void board_init(void) board_init_clock(); board_init_console(); board_init_pmp(); - board_init_ahb(); #if BOARD_SHOW_CLOCK board_print_clock_freq(); #endif @@ -199,12 +227,12 @@ void board_init_sdram_pins(void) init_sdram_pins(); } -uint32_t board_init_dram_clock(void) +uint32_t board_init_femc_clock(void) { - clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */ - /* clock_set_source_divider(clock_dram, clk_src_pll1_clk1, 2U); [> 200Mhz <] */ + clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); /* 166Mhz */ + /* clock_set_source_divider(clock_femc, clk_src_pll1_clk1, 2U); [> 200Mhz <] */ - return clock_get_frequency(clock_dram); + return clock_get_frequency(clock_femc); } void board_power_cycle_lcd(void) @@ -234,11 +262,38 @@ void board_init_lcd(void) board_power_cycle_lcd(); } +void board_panel_para_to_lcdc(lcdc_config_t *config) +{ + const uint16_t panel_timing_para[] = BOARD_PANEL_TIMING_PARA; + + config->resolution_x = BOARD_LCD_WIDTH; + config->resolution_y = BOARD_LCD_HEIGHT; + + config->hsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSPW_INDEX]; + config->hsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HBP_INDEX]; + config->hsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HFP_INDEX]; + + config->vsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSPW_INDEX]; + config->vsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VBP_INDEX]; + config->vsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VFP_INDEX]; + + config->control.invert_hsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSSP_INDEX]; + config->control.invert_vsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSSP_INDEX]; + config->control.invert_href = panel_timing_para[BOARD_PANEL_TIMEING_PARA_DESP_INDEX]; + config->control.invert_pixel_data = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PDSP_INDEX]; + config->control.invert_pixel_clock = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PCSP_INDEX]; +} + void board_delay_ms(uint32_t ms) { clock_cpu_delay_ms(ms); } +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -275,7 +330,8 @@ void board_i2c_bus_clear(I2C_Type *ptr) gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) { printf("CLK is low, please power cycle the board\n"); - while (1) {} + while (1) { + } } if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) { printf("SDA is low, try to issue I2C bus clear\n"); @@ -320,7 +376,8 @@ void board_init_i2c(I2C_Type *ptr) stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); if (stat != status_success) { printf("failed to initialize i2c 0x%lx\n", (uint32_t)BOARD_CAP_I2C_BASE); - while (1) {} + while (1) { + } } } @@ -329,15 +386,19 @@ uint32_t board_init_uart_clock(UART_Type *ptr) uint32_t freq = 0U; if (ptr == HPM_UART0) { clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + clock_add_to_group(clock_uart0, 0); freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART6) { clock_set_source_divider(clock_uart6, clk_src_osc24m, 1); + clock_add_to_group(clock_uart6, 0); freq = clock_get_frequency(clock_uart6); } else if (ptr == HPM_UART13) { clock_set_source_divider(clock_uart13, clk_src_osc24m, 1); + clock_add_to_group(clock_uart13, 0); freq = clock_get_frequency(clock_uart13); } else if (ptr == HPM_UART14) { clock_set_source_divider(clock_uart14, clk_src_osc24m, 1); + clock_add_to_group(clock_uart14, 0); freq = clock_get_frequency(clock_uart14); } else { /* Not supported */ @@ -350,7 +411,7 @@ uint32_t board_init_spi_clock(SPI_Type *ptr) if (ptr == HPM_SPI2) { /* SPI2 clock configure */ clock_add_to_group(clock_spi2, 0); - clock_set_source_divider(clock_spi2, clk_src_osc24m, 1U); + clock_set_source_divider(clock_spi2, clk_src_pll1_clk1, 5U); /* 80MHz */ return clock_get_frequency(clock_spi2); } @@ -374,7 +435,12 @@ void board_init_cap_touch(void) void board_init_gpio_pins(void) { - init_gpio_pins(); + uint8_t led_pin_pull_selsect; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + led_pin_pull_selsect = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 12); + init_gpio_pins(led_pin_pull_selsect); } void board_init_spi_pins(SPI_Type *ptr) @@ -394,19 +460,37 @@ void board_write_spi_cs(uint32_t pin, uint8_t state) gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); } +uint8_t board_get_led_pwm_off_level(void) +{ + if (invert_led_level) { + return BOARD_LED_ON_LEVEL; + } else { + return BOARD_LED_OFF_LEVEL; + } +} + +uint8_t board_get_led_gpio_off_level(void) +{ + if (invert_led_level) { + return BOARD_LED_ON_LEVEL; + } else { + return BOARD_LED_OFF_LEVEL; + } +} + void board_init_led_pins(void) { init_led_pins_as_gpio(); - gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); - gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); - gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level()); } void board_led_toggle(void) { #ifdef BOARD_LED_TOGGLE_RGB static uint8_t i; - gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_R_GPIO_PIN); + gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, invert_led_level ? ((1 << i) << BOARD_R_GPIO_PIN) : ((7 & ~(1 << i)) << BOARD_R_GPIO_PIN)); i++; i = i % 3; #else @@ -452,28 +536,47 @@ void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) void board_init_pmp(void) { + uint32_t start_addr; + uint32_t end_addr; + uint32_t length; + pmp_entry_t pmp_entry[16]; + uint8_t index = 0; + + /* Init noncachable memory */ extern uint32_t __noncacheable_start__[]; extern uint32_t __noncacheable_end__[]; - - uint32_t start_addr = (uint32_t) __noncacheable_start__; - uint32_t end_addr = (uint32_t) __noncacheable_end__; - uint32_t length = end_addr - start_addr; - - if (length == 0) { - return; + start_addr = (uint32_t) __noncacheable_start__; + end_addr = (uint32_t) __noncacheable_end__; + length = end_addr - start_addr; + if (length > 0) { + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + index++; } - /* Ensure the address and the length are power of 2 aligned */ - assert((length & (length - 1U)) == 0U); - assert((start_addr & (length - 1U)) == 0U); - - pmp_entry_t pmp_entry[1]; - pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); - pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); - pmp_entry[0].pma_addr = PMA_NAPOT_ADDR(start_addr, length); - pmp_entry[0].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + /* Init share memory */ + extern uint32_t __share_mem_start__[]; + extern uint32_t __share_mem_end__[]; + start_addr = (uint32_t)__share_mem_start__; + end_addr = (uint32_t)__share_mem_end__; + length = end_addr - start_addr; + if (length > 0) { + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + index++; + } - pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); + pmp_config(&pmp_entry[0], index); } void board_init_clock(void) @@ -488,13 +591,14 @@ void board_init_clock(void) } /* Add most Clocks to group 0 */ + /* not open uart clock in this API, uart should configure pin function before opening clock */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_axi0, 0); clock_add_to_group(clock_axi1, 0); clock_add_to_group(clock_axi2, 0); clock_add_to_group(clock_ahb, 0); - clock_add_to_group(clock_dram, 0); + clock_add_to_group(clock_femc, 0); clock_add_to_group(clock_xpi0, 0); clock_add_to_group(clock_xpi1, 0); clock_add_to_group(clock_gptmr0, 0); @@ -505,11 +609,6 @@ void board_init_clock(void) clock_add_to_group(clock_gptmr5, 0); clock_add_to_group(clock_gptmr6, 0); clock_add_to_group(clock_gptmr7, 0); - clock_add_to_group(clock_uart0, 0); - clock_add_to_group(clock_uart1, 0); - clock_add_to_group(clock_uart2, 0); - clock_add_to_group(clock_uart3, 0); - clock_add_to_group(clock_uart13, 0); clock_add_to_group(clock_i2c0, 0); clock_add_to_group(clock_i2c1, 0); clock_add_to_group(clock_i2c2, 0); @@ -555,6 +654,7 @@ void board_init_clock(void) clock_add_to_group(clock_msyn, 0); clock_add_to_group(clock_lmm0, 0); clock_add_to_group(clock_lmm1, 0); + clock_add_to_group(clock_pdm, 0); clock_add_to_group(clock_adc0, 0); clock_add_to_group(clock_adc1, 0); @@ -565,25 +665,33 @@ void board_init_clock(void) clock_add_to_group(clock_i2s1, 0); clock_add_to_group(clock_i2s2, 0); clock_add_to_group(clock_i2s3, 0); + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); /* Add the CPU1 clock to Group1 */ clock_add_to_group(clock_mchtmr1, 1); clock_add_to_group(clock_mbx1, 1); + /* Connect Group1 to CPU1 */ + clock_connect_group_to_cpu(1, 1); - /* Connect Group0 to CPU0 */ - clock_connect_group_to_cpu(0, 0); + /* Bump up DCDC voltage to 1200mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1200); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); - while(1); + while (1) { + } } clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); - /* Connect Group1 to CPU1 */ - clock_connect_group_to_cpu(1, 1); - clock_update_core_clock(); + + clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/ + + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 44100*n sample rate */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); + clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); } uint32_t board_init_cam_clock(CAM_Type *ptr) @@ -663,6 +771,16 @@ uint32_t board_init_pdm_clock(void) return clock_get_frequency(clock_pdm); } +hpm_stat_t board_set_audio_pll_clock(uint32_t freq) +{ + return pllctl_init_frac_pll_with_freq(HPM_PLLCTL, 3, freq); /* pll3clk */ +} + +void board_init_i2s_pins(I2S_Type *ptr) +{ + init_i2s_pins(ptr); +} + uint32_t board_init_i2s_clock(I2S_Type *ptr) { if (ptr == HPM_I2S0) { @@ -725,23 +843,24 @@ uint32_t board_init_can_clock(CAN_Type *ptr) */ void _init_ext_ram(void) { - uint32_t dram_clk_in_hz; + uint32_t femc_clk_in_hz; + clock_add_to_group(clock_femc, 0); board_init_sdram_pins(); - dram_clk_in_hz = board_init_dram_clock(); + femc_clk_in_hz = board_init_femc_clock(); - dram_config_t config = {0}; - dram_sdram_config_t sdram_config = {0}; + femc_config_t config = {0}; + femc_sdram_config_t sdram_config = {0}; - dram_default_config(HPM_DRAM, &config); - config.dqs = DRAM_DQS_INTERNAL; - dram_init(HPM_DRAM, &config); + femc_default_config(HPM_FEMC, &config); + config.dqs = FEMC_DQS_INTERNAL; + femc_init(HPM_FEMC, &config); - sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; + sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4; sdram_config.prescaler = 0x3; sdram_config.burst_len_in_byte = 8; sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; - sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; sdram_config.precharge_to_act_in_ns = 18; /* Trp */ sdram_config.act_to_rw_in_ns = 18; /* Trcd */ @@ -754,7 +873,7 @@ void _init_ext_ram(void) sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ sdram_config.act_to_act_in_ns = 12; /* Trrd */ sdram_config.idle_timeout_in_ns = 6; - sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; + sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED; sdram_config.cs = BOARD_SDRAM_CS; sdram_config.base_address = BOARD_SDRAM_ADDRESS; @@ -765,7 +884,7 @@ void _init_ext_ram(void) sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; sdram_config.delay_cell_value = 29; - dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); + femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } #endif @@ -977,10 +1096,23 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) if (ptr == HPM_ENET0) { gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + } else if (ptr == HPM_ENET1) { + gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); board_delay_ms(1); gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1); } else if (ptr == HPM_ENET1) { - gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); + gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); board_delay_ms(1); gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 1); } else { @@ -989,3 +1121,44 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) return status_success; } + +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) +{ + return enet_pbl_32; +} + +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_enable_irq(IRQn_ENET0); + } else if (ptr == HPM_ENET1) { + intc_m_enable_irq(IRQn_ENET1); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_disable_irq(IRQn_ENET0); + } else if (ptr == HPM_ENET1) { + intc_m_disable_irq(IRQn_ENET1); + } else { + return status_invalid_argument; + } + + return status_success; +} + +void board_init_enet_pps_pins(ENET_Type *ptr) +{ + init_enet_pps_pins(); +} + +void board_init_dao_pins(void) +{ + init_dao_pins(); +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk/board.h b/common/libraries/hpm_sdk/boards/hpm6750evk/board.h index 9f7d3250..bd57f2c7 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evk/board.h +++ b/common/libraries/hpm_sdk/boards/hpm6750evk/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,10 +13,16 @@ #include "hpm_soc.h" #include "hpm_soc_feature.h" #include "pinmux.h" +#include "hpm_lcdc_drv.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif #define BOARD_NAME "hpm6750evk" #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) +#define SEC_CORE_IMG_START ILM_LOCAL_BASE + /* uart section */ #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE HPM_CORE0 @@ -48,12 +54,14 @@ #define BOARD_APP_UART_BAUDRATE (115200UL) #define BOARD_APP_UART_CLK_NAME clock_uart0 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX #ifndef BOARD_CONSOLE_TYPE -#define BOARD_CONSOLE_TYPE console_type_uart +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif -#if BOARD_CONSOLE_TYPE == console_type_uart +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 #define BOARD_CONSOLE_BASE HPM_UART0 @@ -74,8 +82,8 @@ /* sdram section */ #define BOARD_SDRAM_ADDRESS (0x40000000UL) #define BOARD_SDRAM_SIZE (32*SIZE_1MB) -#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_32_BITS +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS #define BOARD_SDRAM_REFRESH_COUNT (8192UL) #define BOARD_SDRAM_REFRESH_IN_MS (64UL) #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) @@ -95,11 +103,11 @@ /* i2c section */ #define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 #define BOARD_APP_I2C_CLK_NAME clock_i2c0 #define BOARD_APP_I2C_DMA HPM_HDMA #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX #define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 -#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 #define BOARD_CAM_I2C_BASE HPM_I2C0 #define BOARD_CAM_I2C_CLK_NAME clock_i2c0 @@ -143,6 +151,7 @@ #define BOARD_GPTMR_CHANNEL 1 #define BOARD_GPTMR_PWM HPM_GPTMR3 #define BOARD_GPTMR_PWM_CHANNEL 1 +#define BOARD_GPTMR_CLK_NAME clock_gptmr4 /* gpio section */ #define BOARD_R_GPIO_CTRL HPM_GPIO0 @@ -184,14 +193,13 @@ /* spi section */ #define BOARD_APP_SPI_BASE HPM_SPI2 -#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) -#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) +#define BOARD_APP_SPI_CLK_NAME clock_spi2 +#define BOARD_APP_SPI_IRQ IRQn_SPI2 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) #define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX -#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX -#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 #define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 #define BOARD_SPI_CS_PIN IOC_PAD_PE31 #define BOARD_SPI_CS_ACTIVE_LEVEL (0U) @@ -203,11 +211,58 @@ #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) /* lcd section */ + +/* + * BOARD_PANEL_TIMING_PARA {HSPW, HBP, HFP, VSPW, VBP, VFP, HSSP, VSSP, DESP, PDSP, PCSP} + * + * HSPW: Horizontal Synchronization Pulse width + * HBP: Horizontal Back Porch + * HFP: Horizontal Front Porch + * VSPW: Vertical Synchronization Pulse width + * VBP: Vertical Back Porch + * VFP: Vertical Front Porch + * HSSP: Horizontal Synchronization Signal Polarity, 0: High Active, 1: Low Active + * VSSP: Vertical Synchronization Signal Polarity, 0: High Active, 1: Low Active + * DESP: Data Enable Signal Polarity, 0: High Active, 1: Low Active + * PDSP: Pixel Data Signal Polarity, 0: High Active, 1: Low Active + * PCSP: Pixel Clock Signal Polarity, 0: High Active, 1: Low Active + */ +#define BOARD_PANEL_TIMEING_PARA_HSPW_INDEX 0 +#define BOARD_PANEL_TIMEING_PARA_HBP_INDEX 1 +#define BOARD_PANEL_TIMEING_PARA_HFP_INDEX 2 +#define BOARD_PANEL_TIMEING_PARA_VSPW_INDEX 3 +#define BOARD_PANEL_TIMEING_PARA_VBP_INDEX 4 +#define BOARD_PANEL_TIMEING_PARA_VFP_INDEX 5 +#define BOARD_PANEL_TIMEING_PARA_HSSP_INDEX 6 +#define BOARD_PANEL_TIMEING_PARA_VSSP_INDEX 7 +#define BOARD_PANEL_TIMEING_PARA_DESP_INDEX 8 +#define BOARD_PANEL_TIMEING_PARA_PDSP_INDEX 9 +#define BOARD_PANEL_TIMEING_PARA_PCSP_INDEX 10 + +#if defined(PANEL_TM070RDH13) + +#ifndef BOARD_LCD_WIDTH +#define BOARD_LCD_WIDTH 800 +#endif +#ifndef BOARD_LCD_HEIGHT +#define BOARD_LCD_HEIGHT 480 +#endif +#ifndef BOARD_PANEL_TIMING_PARA +#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} +#endif + +#else + #ifndef BOARD_LCD_WIDTH -#define BOARD_LCD_WIDTH (800) +#define BOARD_LCD_WIDTH 800 #endif #ifndef BOARD_LCD_HEIGHT -#define BOARD_LCD_HEIGHT (480) +#define BOARD_LCD_HEIGHT 480 +#endif +#ifndef BOARD_PANEL_TIMING_PARA +#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} +#endif + #endif /* pdma section */ @@ -221,23 +276,24 @@ #define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 /* enet section */ +#define BOARD_ENET_PPS HPM_ENET0 +#define BOARD_ENET_PPS_IDX enet_pps_0 +#define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 + #define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 #define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF #define BOARD_ENET_RGMII_RST_GPIO_PIN (0U) #define BOARD_ENET_RGMII HPM_ENET0 #define BOARD_ENET_RGMII_TX_DLY (22U) #define BOARD_ENET_RGMII_RX_DLY (19U) - -#define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0) - +#define BOARD_ENET_RGMII_PTP_CLOCK clock_ptp0 #define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 #define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOE #define BOARD_ENET_RMII_RST_GPIO_PIN (26U) #define BOARD_ENET_RMII HPM_ENET1 #define BOARD_ENET_RMII_INT_REF_CLK (1U) - -#define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp1) +#define BOARD_ENET_RMII_PTP_CLOCK clock_ptp1 /* ADC section */ #define BOARD_APP_ADC12_NAME "ADC0" @@ -323,6 +379,7 @@ #define BOARD_BLDCPWM_CMP_INDEX_3 (3U) #define BOARD_BLDCPWM_CMP_INDEX_4 (4U) #define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) /*HALL define*/ @@ -386,6 +443,7 @@ #define BOARD_APP_PWM_OUT1 0 #define BOARD_APP_PWM_OUT2 1 #define BOARD_APP_TRGM HPM_TRGM2 +#define BOARD_APP_PWM_IRQ IRQn_PWM2 /* RGB LED Section */ #define BOARD_RED_PWM_IRQ IRQn_PWM1 @@ -436,10 +494,10 @@ void board_init_console(void); void board_init_uart(UART_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); - +void board_panel_para_to_lcdc(lcdc_config_t *config); void board_init_can(CAN_Type *ptr); -uint32_t board_init_dram_clock(void); +uint32_t board_init_femc_clock(void); void board_init_sdram_pins(void); void board_init_gpio_pins(void); @@ -479,6 +537,9 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr); uint32_t board_init_can_clock(CAN_Type *ptr); +hpm_stat_t board_set_audio_pll_clock(uint32_t freq); + +void board_init_i2s_pins(I2S_Type *ptr); uint32_t board_init_i2s_clock(I2S_Type *ptr); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); @@ -488,16 +549,23 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); bool board_sd_detect_card(SDXC_Type *ptr); +void board_init_dao_pins(void); + void board_init_adc12_pins(void); void board_init_adc16_pins(void); void board_init_usb_pins(void); void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +void board_init_enet_pps_pins(ENET_Type *ptr); +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); /* * @brief Initialize PMP and PMA for but not limited to the following purposes: @@ -506,6 +574,7 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); void board_init_pmp(void); void board_delay_ms(uint32_t ms); +void board_delay_us(uint32_t us); void board_timer_create(uint32_t ms, board_timer_cb cb); @@ -518,6 +587,15 @@ void board_disable_output_rgb_led(uint8_t color); */ void board_ungate_mchtmr_at_lp_mode(void); +/* + * Get PWM output level of onboard LED + */ +uint8_t board_get_led_pwm_off_level(void); + +/* + * Get GPIO pin level of onboard LED + */ +uint8_t board_get_led_gpio_off_level(void); #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk/pinmux.c b/common/libraries/hpm_sdk/boards/hpm6750evk/pinmux.c index 44fdc7cc..6fe4e485 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evk/pinmux.c +++ b/common/libraries/hpm_sdk/boards/hpm6750evk/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -21,8 +21,8 @@ void init_uart_pins(UART_Type *ptr) HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; /* PY port IO needs to configure PIOC as well */ - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; } else if (ptr == HPM_UART2) { HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_UART2_TXD; HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_UART2_RXD; @@ -32,6 +32,9 @@ void init_uart_pins(UART_Type *ptr) /* PZ port IO needs to configure BIOC as well */ HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08; HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09; + } else if (ptr == HPM_PUART) { + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_PUART_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_PUART_TXD; } } @@ -98,7 +101,8 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr) HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3; HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3; } else { - while(1); + while (1) { + } } } @@ -115,7 +119,8 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PZ11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; HPM_IOC->PAD[IOC_PAD_PZ10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; } else { - while(1); + while (1) { + } } } @@ -183,15 +188,67 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); } -void init_gpio_pins(void) +void init_sram_pins(void) +{ + /* Non-MUX */ /* MUX */ + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A0 */ /* A16 */ + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A1 */ /* A17 */ + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A2 */ /* A18 */ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A3 */ /* A19 */ + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A4 */ /* A20 */ + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A5 */ /* A21 */ + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A6 */ /* A22 */ + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A7 */ /* A23 */ + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A8 */ + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A9 */ + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A10 */ + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A11 */ + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A12 */ + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A13 */ + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A14 */ + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A15 */ + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A16 */ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A17 */ + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A18 */ + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A19 */ + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A20 */ + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A21 */ + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A22 */ + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A23 */ + + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D0 */ /* AD0 */ + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D1 */ /* AD1 */ + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D2 */ /* AD2 */ + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D3 */ /* AD3 */ + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D4 */ /* AD4 */ + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D5 */ /* AD5 */ + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D6 */ /* AD6 */ + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D7 */ /* AD7 */ + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D8 */ /* AD8 */ + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D9 */ /* AD9 */ + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D10 */ /* AD10 */ + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D11 */ /* AD11 */ + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D12 */ /* AD12 */ + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D13 */ /* AD13 */ + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D14 */ /* AD14 */ + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D15 */ /* AD15 */ + + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #CE */ + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #OE */ + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #WE */ + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #UB */ + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #LB */ + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #ADV */ +} + +void init_gpio_pins(uint8_t led_pull_select) { - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; - HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(led_pull_select); #ifdef USING_GPIO0_FOR_GPIOZ HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; - HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); /* PZ port IO needs to configure BIOC as well */ HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_PZ_02; #endif @@ -426,9 +483,9 @@ void init_can_pins(CAN_Type *ptr) } } -void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8) +void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8) { - uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);; + uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17); uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); @@ -481,12 +538,12 @@ void init_rgb_pwm_pins(void) void init_led_pins_as_gpio(void) { - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; - HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; - HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13; - HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; } + +void init_enet_pps_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_ETH0_EVTO_0; +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk/pinmux.h b/common/libraries/hpm_sdk/boards/hpm6750evk/pinmux.h index 11d6a0df..2fb75175 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evk/pinmux.h +++ b/common/libraries/hpm_sdk/boards/hpm6750evk/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -16,7 +16,8 @@ void init_lcd_pins(LCDC_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_cap_pins(void); void init_sdram_pins(void); -void init_gpio_pins(void); +void init_sram_pins(void); +void init_gpio_pins(uint8_t pin_stat); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); void init_pins(void); @@ -36,12 +37,13 @@ void init_adc12_pins(void); void init_adc16_pins(void); void init_usb_pins(void); void init_can_pins(CAN_Type *ptr); -void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8); +void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); void init_i2c_pins_as_gpio(I2C_Type *ptr); void init_led_pins_as_gpio(void); void init_trgmux_pins(uint32_t pin); +void init_enet_pps_pins(void); #ifdef __cplusplus } diff --git a/common/libraries/hpm_sdk/boards/hpm6750evkmini/CMakeLists.txt b/common/libraries/hpm_sdk/boards/hpm6750evkmini/CMakeLists.txt index 1fadcae5..b24aa55f 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evkmini/CMakeLists.txt +++ b/common/libraries/hpm_sdk/boards/hpm6750evkmini/CMakeLists.txt @@ -1,17 +1,9 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause -if(BOARD_LCD_WIDTH) -sdk_compile_definitions("-DBOARD_LCD_WIDTH=${BOARD_LCD_WIDTH}") -endif() - -if(BOARD_LCD_HEIGHT) -sdk_compile_definitions("-DBOARD_LCD_HEIGHT=${BOARD_LCD_HEIGHT}") -endif() - -if(BUILD_FOR_SECONDARY_CORE) -sdk_compile_definitions(BOARD_RUNNING_CORE=HPM_CORE1) -endif() +sdk_compile_definitions_ifdef(BOARD_LCD_WIDTH "-DBOARD_LCD_WIDTH=${BOARD_LCD_WIDTH}") +sdk_compile_definitions_ifdef(BOARD_LCD_HEIGHT "-DBOARD_LCD_HEIGHT=${BOARD_LCD_HEIGHT}") +sdk_compile_definitions_ifdef(BUILD_FOR_SECONDARY_CORE BOARD_RUNNING_CORE=HPM_CORE1) sdk_inc(.) sdk_src(pinmux.c) diff --git a/common/libraries/hpm_sdk/boards/hpm6750evkmini/README.md b/common/libraries/hpm_sdk/boards/hpm6750evkmini/README.md deleted file mode 100644 index 97e3a3e9..00000000 --- a/common/libraries/hpm_sdk/boards/hpm6750evkmini/README.md +++ /dev/null @@ -1,86 +0,0 @@ -# HPM6750EVKMINI - -## Overview - -The HPM6750 is a dual-core flashless MCU running 816Mhz. It has a 2MB continuous on-chip ram. Also, it provides various memory interfaces, including SDRAM, Quad SPI NOR Flash, SD/eMMC. It integrates rich audio and video interfaces, including LCD, pixel DMA, camera， and I2S audio interfaces. - - ![hpm6750evkmini](../../doc/images/boards/hpm6750evkmini/hpm6750evkmini.png "hpm6750evkmini") -## Hardware -- HPM6750IVM MCU (816Mhz, 2MB OCRAM) -- Onboard Memory - - 128Mb SDRAM - - 64Mb Quad SPI NOR Flash -- Display & Camera - - LCD connector - - Camera (DVP) -- WiFi - - RW007 over SPI -- USB - - USB type C (USB 2.0 OTG) connector x2 -- Audio - - Mic - - DAO -- Others - - TF Slot - - FT2232 - - Beeper - - RGB LED -- Expansion port - - ART-PI extension port -## DIP Switch S1 -- Bit 1 and 2 controls boot mode - -| bit[2:1] | Description| -|----------|------------| -|OFF, OFF| Boot from Quad SPI NOR flash | -|OFF, ON| Serial boot | -|ON, OFF| ISP | - -(lab_hpm6750_evkmini_board)= -## Button -(lab_hpm6750_evkmini_board_buttons)= -| Name | FUNCTIONS | -|----------|------------| -|PBUTN (S2) | Power Button, TinyUF2 Boot Button, GPIO Button | -|WBUTN (S3) | WAKE UP Button | -|RESET (S4) | Reset Button | - -## Pin Description - - -- SPI Pin - -| Function | Position | -| ---- | -------- | -| SPI2.CSN | P1[24] | -| SPI2.SCLK | P1[23] | -| SPI2.MISO | P1[21] | -| SPI2.MOSI | P1[19] | - -- I2C Pin： - -| Function | Position | -| ---- | -------- | -| I2C0.SCL | P1[13] | -| I2C0.SDA | P1[15] | - -- UART for core1 debug console： - -| Function | Position | -| ---- | -------- | -| UART13.TXD | P1[8] | -| UART13.RXD | P1[10] | - -- ACMP Pin - -| Function | Position | -| ---- | -------- | -| CMP.INN6 | P2[11] | -| CMP.COMP_1 | P1[7] | - -- GPTMR Pin - -| Function | Position | -| ---- | -------- | -| GPTMR2.CAPT_2 | P2[15] | -| GPTMR2.COMP_2 | P2[19] | \ No newline at end of file diff --git a/common/libraries/hpm_sdk/boards/hpm6750evkmini/README_zh.md b/common/libraries/hpm_sdk/boards/hpm6750evkmini/README_zh.md deleted file mode 100644 index c17fe961..00000000 --- a/common/libraries/hpm_sdk/boards/hpm6750evkmini/README_zh.md +++ /dev/null @@ -1,86 +0,0 @@ -# HPM6750EVKMINI开发板 - -## 概述 -HPM6750是一款主频达816Mhz的双核微控制器。该芯片拥有最大2M字节的连续片上RAM，并集成了丰富的存储接口，如SDRAM，Quad SPI NOR flash， SD/eMMC卡。同时它也提供多种音视频接口包括LCD显示，像素DMA，摄像头以及I2S音频接口。 - - ![hpm6750evkmini](../../doc/images/boards/hpm6750evkmini/hpm6750evkmini.png "hpm6750evkmini") -## 板上硬件资源 -- HPM6750IVM 微控制器 (主频816Mhz, 2MB片上内存) -- 板载存储 - - 128Mb SDRAM - - 64Mb Quad SPI NOR Flash -- 显示/摄像头 - - LCD接口 - - 摄像头(DVP)接口 -- WiFi - - RW007 -- USB - - USB type C (USB 2.0 OTG) connector x2 -- 音频 - - Mic - - DAO -- 其他 - - TF卡槽 - - FT2232 - - 蜂鸣器 - - RGB LED -- 扩展口 - - ART-PI -## 拨码开关 S1 -- Bit 1，2控制启动模式 - -| Bit[2:1] | 功能描述| -|----------|------------| -|OFF, OFF| Quad SPI NOR flash 启动 | -|OFF, ON| 串行启动 | -|ON, OFF| 在系统编程 | - -(lab_hpm6750_evkmini_board)= -## 按键 -(lab_hpm6750_evkmini_board_buttons)= -| 名称 | 功能 | -|----------|------------| -|PBUTN (S2) | 电源按键, TinyUF2 Boot按键, GPIO 按键| -|WBUTN (S3) | WAKE UP 按键| -|RESET (S4) | Reset 按键| - - -## 引脚描述 - - -- SPI引脚： - -| 功能 | 位置 | -| ---- | -------- | -| SPI2.CSN | P1[24] | -| SPI2.SCLK | P1[23] | -| SPI2.MISO | P1[21] | -| SPI2.MOSI | P1[19] | - -- I2C引脚： - -| 功能 | 位置 | -| ---- | -------- | -| I2C0.SCL | P1[13] | -| I2C0.SDA | P1[15] | - -- CORE1调试串口引脚： - -| 功能 | 位置 | -| ---- | -------- | -| UART13.TXD | P1[8] | -| UART13.RXD | P1[10] | - -- ACMP引脚 - -| 功能 | 位置 | -| ---- | -------- | -| CMP.INN6 | P2[11] | -| CMP.COMP_1 | P1[7] | - -- GPTMR引脚 - -| 功能 | 位置 | -| ---- | -------- | -| GPTMR2.CAPT_2 | P2[15] | -| GPTMR2.COMP_2 | P2[19] | \ No newline at end of file diff --git a/common/libraries/hpm_sdk/boards/hpm6750evkmini/SConscript b/common/libraries/hpm_sdk/boards/hpm6750evkmini/SConscript deleted file mode 100644 index 7c742f69..00000000 --- a/common/libraries/hpm_sdk/boards/hpm6750evkmini/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -import rtconfig - -from building import * - -cwd = GetCurrentDir() - -src = Glob('*.c') - -CPPDEFINES=[] -CPPPATH = [cwd] - -group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) - -Return('group') diff --git a/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.c b/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.c index 4ce8af45..89cbe9a8 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.c +++ b/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -10,7 +10,6 @@ #include "hpm_lcdc_drv.h" #include "hpm_i2c_drv.h" #include "hpm_gpio_drv.h" -#include "hpm_debug_console.h" #include "hpm_femc_drv.h" #include "pinmux.h" #include "hpm_pmp_drv.h" @@ -21,8 +20,12 @@ #include "hpm_sdxc_soc_drv.h" #include "hpm_pllctl_drv.h" #include "hpm_pwm_drv.h" +#include "hpm_pcfg_drv.h" +#include "hpm_enet_drv.h" +#include "hpm_sdk_version.h" static board_timer_cb timer_cb; +static bool invert_led_level; /** * @brief FLASH configuration option definitions: @@ -87,26 +90,33 @@ ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATU void board_init_console(void) { -#if BOARD_CONSOLE_TYPE == console_type_uart +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART console_config_t cfg; + /* uart needs to configure pin function before enabling clock, otherwise the level change of + uart rx pin when configuring pin function will cause a wrong data to be received. + And a uart rx dma request will be generated by default uart fifo dma trigger level. */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_BASE); + /* Configure the UART clock to 24MHz */ clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; cfg.base = (uint32_t) BOARD_CONSOLE_BASE; cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); cfg.baudrate = BOARD_CONSOLE_BAUDRATE; - init_uart_pins((UART_Type *) cfg.base); - if (status_success != console_init(&cfg)) { /* failed to initialize debug console */ while (1) { } } #else - while(1); + while (1) { + } +#endif #endif } @@ -125,7 +135,7 @@ void board_print_clock_freq(void) printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); - printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram)); + printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); printf("display:\t %luHz\n", clock_get_frequency(clock_display)); printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); @@ -136,12 +146,9 @@ void board_print_clock_freq(void) void board_init_uart(UART_Type *ptr) { + /* configure uart's pin before opening uart's clock */ init_uart_pins(ptr); -} - -void board_init_ahb(void) -{ - clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/ + board_init_uart_clock(ptr); } void board_print_banner(void) @@ -157,6 +164,9 @@ void board_print_banner(void) $$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ \\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ ----------------------------------------------------------------------\n"}; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif printf("%s", banner); } @@ -177,12 +187,14 @@ static void board_turnoff_rgb_led(void) port_pin18_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 18); port_pin19_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 19); port_pin20_status = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 20); + invert_led_level = false; /** * hpm board evkmini Rev. B led light modification, resulting in two versions of rgb led processing different * */ if ((port_pin18_status & port_pin19_status & port_pin20_status) == 0) { - /*Mini Rev B*/ + /* Mini Rev B */ + invert_led_level = true; pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = pad_ctl; @@ -190,6 +202,20 @@ static void board_turnoff_rgb_led(void) } } +uint8_t board_get_led_pwm_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +uint8_t board_get_led_gpio_off_level(void) +{ + if (invert_led_level) { + return BOARD_LED_ON_LEVEL; + } else { + return BOARD_LED_OFF_LEVEL; + } +} + void board_ungate_mchtmr_at_lp_mode(void) { /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ @@ -202,7 +228,6 @@ void board_init(void) board_init_clock(); board_init_console(); board_init_pmp(); - board_init_ahb(); #if BOARD_SHOW_CLOCK board_print_clock_freq(); #endif @@ -216,10 +241,10 @@ void board_init_sdram_pins(void) init_sdram_pins(); } -uint32_t board_init_dram_clock(void) +uint32_t board_init_femc_clock(void) { - clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */ - return clock_get_frequency(clock_dram); + clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); /* 166Mhz */ + return clock_get_frequency(clock_femc); } void board_power_cycle_lcd(void) @@ -248,11 +273,38 @@ void board_init_lcd(void) board_power_cycle_lcd(); } +void board_panel_para_to_lcdc(lcdc_config_t *config) +{ + const uint16_t panel_timing_para[] = BOARD_PANEL_TIMING_PARA; + + config->resolution_x = BOARD_LCD_WIDTH; + config->resolution_y = BOARD_LCD_HEIGHT; + + config->hsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSPW_INDEX]; + config->hsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HBP_INDEX]; + config->hsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HFP_INDEX]; + + config->vsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSPW_INDEX]; + config->vsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VBP_INDEX]; + config->vsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VFP_INDEX]; + + config->control.invert_hsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSSP_INDEX]; + config->control.invert_vsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSSP_INDEX]; + config->control.invert_href = panel_timing_para[BOARD_PANEL_TIMEING_PARA_DESP_INDEX]; + config->control.invert_pixel_data = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PDSP_INDEX]; + config->control.invert_pixel_clock = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PCSP_INDEX]; +} + void board_delay_ms(uint32_t ms) { clock_cpu_delay_ms(ms); } +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -289,7 +341,8 @@ void board_i2c_bus_clear(I2C_Type *ptr) gpio_set_pin_input(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN); if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_CLK_GPIO_INDEX, BOARD_CAP_I2C_CLK_GPIO_PIN)) { printf("CLK is low, please power cycle the board\n"); - while (1) {} + while (1) { + } } if (!gpio_read_pin(BOARD_LED_GPIO_CTRL, BOARD_CAP_I2C_SDA_GPIO_INDEX, BOARD_CAP_I2C_SDA_GPIO_PIN)) { printf("SDA is low, try to issue I2C bus clear\n"); @@ -333,8 +386,9 @@ void board_init_i2c(I2C_Type *ptr) freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME); stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); if (stat != status_success) { - printf("failed to initialize i2c 0x%lx\n", (uint32_t)BOARD_CAP_I2C_BASE); - while (1) {} + printf("failed to initialize i2c 0x%lx\n", (uint32_t) BOARD_CAP_I2C_BASE); + while (1) { + } } } @@ -343,18 +397,23 @@ uint32_t board_init_uart_clock(UART_Type *ptr) uint32_t freq = 0U; if (ptr == HPM_UART0) { clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + clock_add_to_group(clock_uart0, 0); freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART6) { clock_set_source_divider(clock_uart6, clk_src_osc24m, 1); + clock_add_to_group(clock_uart6, 0); freq = clock_get_frequency(clock_uart6); } else if (ptr == HPM_UART7) { clock_set_source_divider(clock_uart7, clk_src_osc24m, 1); + clock_add_to_group(clock_uart7, 0); freq = clock_get_frequency(clock_uart7); } else if (ptr == HPM_UART13) { clock_set_source_divider(clock_uart13, clk_src_osc24m, 1); + clock_add_to_group(clock_uart13, 0); freq = clock_get_frequency(clock_uart13); } else if (ptr == HPM_UART14) { clock_set_source_divider(clock_uart14, clk_src_osc24m, 1); + clock_add_to_group(clock_uart14, 0); freq = clock_get_frequency(clock_uart14); } else { /* Not supported */ @@ -367,7 +426,7 @@ uint32_t board_init_spi_clock(SPI_Type *ptr) if (ptr == HPM_SPI2) { /* SPI2 clock configure */ clock_add_to_group(clock_spi2, 0); - clock_set_source_divider(clock_spi2, clk_src_osc24m, 1U); + clock_set_source_divider(clock_spi2, clk_src_pll1_clk1, 5U); /* 80MHz */ return clock_get_frequency(clock_spi2); } else { @@ -416,19 +475,18 @@ void board_write_spi_cs(uint32_t pin, uint8_t state) void board_init_led_pins(void) { init_led_pins_as_gpio(); - gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL); - gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL); - gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL); + gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level()); + gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level()); } void board_led_toggle(void) { static uint8_t i; - if(BOARD_LED_PULL_STATUS){ + if (BOARD_LED_PULL_STATUS) { /* hpm6750 Mini Rev A led configure*/ gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_G_GPIO_PIN); - } - else{ + } else { /* hpm6750 Mini Rev B led configure*/ gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, ((1 << i)) << BOARD_G_GPIO_PIN); } @@ -464,28 +522,47 @@ void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) void board_init_pmp(void) { + uint32_t start_addr; + uint32_t end_addr; + uint32_t length; + pmp_entry_t pmp_entry[16]; + uint8_t index = 0; + + /* Init noncachable memory */ extern uint32_t __noncacheable_start__[]; extern uint32_t __noncacheable_end__[]; - - uint32_t start_addr = (uint32_t) __noncacheable_start__; - uint32_t end_addr = (uint32_t) __noncacheable_end__; - uint32_t length = end_addr - start_addr; - - if (length == 0) { - return; + start_addr = (uint32_t) __noncacheable_start__; + end_addr = (uint32_t) __noncacheable_end__; + length = end_addr - start_addr; + if (length > 0) { + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + index++; } - /* Ensure the address and the length are power of 2 aligned */ - assert((length & (length - 1U)) == 0U); - assert((start_addr & (length - 1U)) == 0U); - - pmp_entry_t pmp_entry[1]; - pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); - pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); - pmp_entry[0].pma_addr = PMA_NAPOT_ADDR(start_addr, length); - pmp_entry[0].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + /* Init share memory */ + extern uint32_t __share_mem_start__[]; + extern uint32_t __share_mem_end__[]; + start_addr = (uint32_t)__share_mem_start__; + end_addr = (uint32_t)__share_mem_end__; + length = end_addr - start_addr; + if (length > 0) { + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + index++; + } - pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); + pmp_config(&pmp_entry[0], index); } void board_init_clock(void) @@ -500,13 +577,14 @@ void board_init_clock(void) } /* Add most Clocks to group 0 */ + /* not open uart clock in this API, uart should configure pin function before opening clock */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_axi0, 0); clock_add_to_group(clock_axi1, 0); clock_add_to_group(clock_axi2, 0); clock_add_to_group(clock_ahb, 0); - clock_add_to_group(clock_dram, 0); + clock_add_to_group(clock_femc, 0); clock_add_to_group(clock_xpi0, 0); clock_add_to_group(clock_xpi1, 0); clock_add_to_group(clock_gptmr0, 0); @@ -517,14 +595,6 @@ void board_init_clock(void) clock_add_to_group(clock_gptmr5, 0); clock_add_to_group(clock_gptmr6, 0); clock_add_to_group(clock_gptmr7, 0); - clock_add_to_group(clock_uart0, 0); - clock_add_to_group(clock_uart1, 0); - clock_add_to_group(clock_uart2, 0); - clock_add_to_group(clock_uart3, 0); - clock_add_to_group(clock_uart6, 0); - clock_add_to_group(clock_uart7, 0); - clock_add_to_group(clock_uart13, 0); - clock_add_to_group(clock_uart14, 0); clock_add_to_group(clock_i2c0, 0); clock_add_to_group(clock_i2c1, 0); clock_add_to_group(clock_i2c2, 0); @@ -570,6 +640,7 @@ void board_init_clock(void) clock_add_to_group(clock_msyn, 0); clock_add_to_group(clock_lmm0, 0); clock_add_to_group(clock_lmm1, 0); + clock_add_to_group(clock_pdm, 0); clock_add_to_group(clock_adc0, 0); clock_add_to_group(clock_adc1, 0); @@ -580,25 +651,33 @@ void board_init_clock(void) clock_add_to_group(clock_i2s1, 0); clock_add_to_group(clock_i2s2, 0); clock_add_to_group(clock_i2s3, 0); + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); /* Add the CPU1 clock to Group1 */ clock_add_to_group(clock_mchtmr1, 1); clock_add_to_group(clock_mbx1, 1); + /* Connect Group1 to CPU1 */ + clock_connect_group_to_cpu(1, 1); - /* Connect Group0 to CPU0 */ - clock_connect_group_to_cpu(0, 0); + /* Bump up DCDC voltage to 1200mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1200); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); - while(1); + while (1) { + } } clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); - /* Connect Group1 to CPU1 */ - clock_connect_group_to_cpu(1, 1); - clock_update_core_clock(); + + clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/ + + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 44100*n sample rate */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); + clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); } uint32_t board_init_cam_clock(CAM_Type *ptr) @@ -678,6 +757,16 @@ uint32_t board_init_pdm_clock(void) return clock_get_frequency(clock_pdm); } +hpm_stat_t board_set_audio_pll_clock(uint32_t freq) +{ + return pllctl_init_frac_pll_with_freq(HPM_PLLCTL, 3, freq); /* pll3clk */ +} + +void board_init_i2s_pins(I2S_Type *ptr) +{ + init_i2s_pins(ptr); +} + uint32_t board_init_i2s_clock(I2S_Type *ptr) { if (ptr == HPM_I2S0) { @@ -741,23 +830,24 @@ uint32_t board_init_can_clock(CAN_Type *ptr) */ void _init_ext_ram(void) { - uint32_t dram_clk_in_hz; + uint32_t femc_clk_in_hz; + clock_add_to_group(clock_femc, 0); board_init_sdram_pins(); - dram_clk_in_hz = board_init_dram_clock(); + femc_clk_in_hz = board_init_femc_clock(); - dram_config_t config = {0}; - dram_sdram_config_t sdram_config = {0}; + femc_config_t config = {0}; + femc_sdram_config_t sdram_config = {0}; - dram_default_config(HPM_DRAM, &config); - config.dqs = DRAM_DQS_INTERNAL; - dram_init(HPM_DRAM, &config); + femc_default_config(HPM_FEMC, &config); + config.dqs = FEMC_DQS_INTERNAL; + femc_init(HPM_FEMC, &config); - sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4; + sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4; sdram_config.prescaler = 0x3; sdram_config.burst_len_in_byte = 8; sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS; - sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3; + sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; sdram_config.precharge_to_act_in_ns = 18; /* Trp */ sdram_config.act_to_rw_in_ns = 18; /* Trcd */ @@ -770,7 +860,7 @@ void _init_ext_ram(void) sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */ sdram_config.act_to_act_in_ns = 12; /* Trrd */ sdram_config.idle_timeout_in_ns = 6; - sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED; + sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED; sdram_config.cs = BOARD_SDRAM_CS; sdram_config.base_address = BOARD_SDRAM_ADDRESS; @@ -781,7 +871,7 @@ void _init_ext_ram(void) sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE; sdram_config.delay_cell_value = 29; - dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config); + femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } #endif @@ -796,7 +886,6 @@ void board_init_sd_pins(SDXC_Type *ptr) } } - uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq) { uint32_t actual_freq = 0; @@ -926,6 +1015,9 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) } else { return status_invalid_argument; } + + enet_rmii_enable_clock(ptr, internal); + return status_success; } @@ -945,6 +1037,17 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) if (ptr == HPM_ENET1) { gpio_set_pin_output_with_initial(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) +{ + if (ptr == HPM_ENET1) { + gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 0); board_delay_ms(1); gpio_write_pin(BOARD_ENET_RMII_RST_GPIO, BOARD_ENET_RMII_RST_GPIO_INDEX, BOARD_ENET_RMII_RST_GPIO_PIN, 1); } else { @@ -953,3 +1056,28 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr) return status_success; } + +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) +{ + return enet_pbl_32; +} + +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr) +{ + return status_success; +} + +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr) +{ + return status_success; +} + +void board_init_enet_pps_pins(ENET_Type *ptr) +{ + init_enet_pps_pins(); +} + +void board_init_dao_pins(void) +{ + init_dao_pins(); +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.h b/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.h index e61ab02a..f3846236 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.h +++ b/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,10 +13,16 @@ #include "hpm_soc_feature.h" #include "hpm_clock_drv.h" #include "pinmux.h" +#include "hpm_lcdc_drv.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif #define BOARD_NAME "hpm6750evkmini" #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) +#define SEC_CORE_IMG_START ILM_LOCAL_BASE + /* uart section */ #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE HPM_CORE0 @@ -48,12 +54,14 @@ #define BOARD_APP_UART_BAUDRATE (115200UL) #define BOARD_APP_UART_CLK_NAME clock_uart0 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX #ifndef BOARD_CONSOLE_TYPE -#define BOARD_CONSOLE_TYPE console_type_uart +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif -#if BOARD_CONSOLE_TYPE == console_type_uart +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 #define BOARD_CONSOLE_BASE HPM_UART0 @@ -73,8 +81,8 @@ /* sdram section */ #define BOARD_SDRAM_ADDRESS (0x40000000UL) #define BOARD_SDRAM_SIZE (16*SIZE_1MB) -#define BOARD_SDRAM_CS DRAM_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS #define BOARD_SDRAM_REFRESH_COUNT (4096UL) #define BOARD_SDRAM_REFRESH_IN_MS (64UL) #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (2UL) @@ -92,11 +100,11 @@ /* i2c section */ #define BOARD_APP_I2C_BASE HPM_I2C0 #define BOARD_APP_I2C_IRQ IRQn_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 #define BOARD_APP_I2C_CLK_NAME clock_i2c0 #define BOARD_APP_I2C_DMA HPM_HDMA #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX #define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 -#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 #define BOARD_CAM_I2C_BASE HPM_I2C0 #define BOARD_CAM_I2C_CLK_NAME clock_i2c0 @@ -136,6 +144,7 @@ #define BOARD_GPTMR_CHANNEL 0 #define BOARD_GPTMR_PWM HPM_GPTMR2 #define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr2 /* gpio section */ #define BOARD_R_GPIO_CTRL HPM_GPIO0 @@ -180,14 +189,13 @@ /* spi section */ #define BOARD_APP_SPI_BASE HPM_SPI2 -#define BOARD_APP_SPI_CLK_SRC_FREQ (24000000UL) -#define BOARD_APP_SPI_SCLK_FREQ (1562500UL) +#define BOARD_APP_SPI_CLK_NAME clock_spi2 +#define BOARD_APP_SPI_IRQ IRQn_SPI2 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) #define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX -#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX -#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 #define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 #define BOARD_SPI_CS_PIN IOC_PAD_PB24 #define BOARD_SPI_CS_ACTIVE_LEVEL (0U) @@ -202,11 +210,58 @@ #define BOARD_FLASH_SIZE (8 << 20) /* lcd section */ + +/* + * BOARD_PANEL_TIMING_PARA {HSPW, HBP, HFP, VSPW, VBP, VFP, HSSP, VSSP, DESP, PDSP, PCSP} + * + * HSPW: Horizontal Synchronization Pulse width + * HBP: Horizontal Back Porch + * HFP: Horizontal Front Porch + * VSPW: Vertical Synchronization Pulse width + * VBP: Vertical Back Porch + * VFP: Vertical Front Porch + * HSSP: Horizontal Synchronization Signal Polarity, 0: High Active, 1: Low Active + * VSSP: Vertical Synchronization Signal Polarity, 0: High Active, 1: Low Active + * DESP: Data Enable Signal Polarity, 0: High Active, 1: Low Active + * PDSP: Pixel Data Signal Polarity, 0: High Active, 1: Low Active + * PCSP: Pixel Clock Signal Polarity, 0: High Active, 1: Low Active + */ +#define BOARD_PANEL_TIMEING_PARA_HSPW_INDEX 0 +#define BOARD_PANEL_TIMEING_PARA_HBP_INDEX 1 +#define BOARD_PANEL_TIMEING_PARA_HFP_INDEX 2 +#define BOARD_PANEL_TIMEING_PARA_VSPW_INDEX 3 +#define BOARD_PANEL_TIMEING_PARA_VBP_INDEX 4 +#define BOARD_PANEL_TIMEING_PARA_VFP_INDEX 5 +#define BOARD_PANEL_TIMEING_PARA_HSSP_INDEX 6 +#define BOARD_PANEL_TIMEING_PARA_VSSP_INDEX 7 +#define BOARD_PANEL_TIMEING_PARA_DESP_INDEX 8 +#define BOARD_PANEL_TIMEING_PARA_PDSP_INDEX 9 +#define BOARD_PANEL_TIMEING_PARA_PCSP_INDEX 10 + +#if defined(PANEL_TM070RDH13) + +#ifndef BOARD_LCD_WIDTH +#define BOARD_LCD_WIDTH 800 +#endif +#ifndef BOARD_LCD_HEIGHT +#define BOARD_LCD_HEIGHT 480 +#endif +#ifndef BOARD_PANEL_TIMING_PARA +#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} +#endif + +#else + #ifndef BOARD_LCD_WIDTH -#define BOARD_LCD_WIDTH (800) +#define BOARD_LCD_WIDTH 800 #endif #ifndef BOARD_LCD_HEIGHT -#define BOARD_LCD_HEIGHT (480) +#define BOARD_LCD_HEIGHT 480 +#endif +#ifndef BOARD_PANEL_TIMING_PARA +#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0} +#endif + #endif /* pdma section */ @@ -219,12 +274,16 @@ /* enet section */ +#define BOARD_ENET_PPS HPM_ENET0 +#define BOARD_ENET_PPS_IDX enet_pps_0 +#define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 + #define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 #define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOD #define BOARD_ENET_RMII_RST_GPIO_PIN (15U) #define BOARD_ENET_RMII HPM_ENET1 #define BOARD_ENET_RMII_INT_REF_CLK (0U) -#define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp1) +#define BOARD_ENET_RMII_PTP_CLOCK clock_ptp1 /* adc section */ #define BOARD_APP_ADC12_NAME "ADC0" @@ -292,6 +351,7 @@ #define BOARD_APP_PWM_OUT1 4 #define BOARD_APP_PWM_OUT2 5 #define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM0 /* RGB LED Section */ #define BOARD_RED_PWM_IRQ IRQn_PWM1 @@ -342,6 +402,7 @@ #define BOARD_BLDCPWM_CMP_INDEX_3 (3U) #define BOARD_BLDCPWM_CMP_INDEX_4 (4U) #define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) /*HALL define*/ @@ -427,10 +488,10 @@ void board_init_console(void); void board_init_uart(UART_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); - +void board_panel_para_to_lcdc(lcdc_config_t *config); void board_init_can(CAN_Type *ptr); -uint32_t board_init_dram_clock(void); +uint32_t board_init_femc_clock(void); void board_init_sdram_pins(void); void board_init_gpio_pins(void); @@ -469,6 +530,9 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr); uint32_t board_init_can_clock(CAN_Type *ptr); +hpm_stat_t board_set_audio_pll_clock(uint32_t freq); + +void board_init_i2s_pins(I2S_Type *ptr); uint32_t board_init_i2s_clock(I2S_Type *ptr); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); @@ -478,15 +542,22 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq); void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); bool board_sd_detect_card(SDXC_Type *ptr); +void board_init_dao_pins(void); + void board_init_adc12_pins(void); void board_init_adc16_pins(void); void board_init_usb_pins(void); void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +void board_init_enet_pps_pins(ENET_Type *ptr); +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); /* * @brief Initialize PMP and PMA for but not limited to the following purposes: @@ -495,6 +566,7 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); void board_init_pmp(void); void board_delay_ms(uint32_t ms); +void board_delay_us(uint32_t us); void board_init_beep_pwm_pins(void); void board_init_rgb_pwm_pins(void); @@ -508,6 +580,15 @@ void board_disable_output_rgb_led(uint8_t color); */ void board_ungate_mchtmr_at_lp_mode(void); +/* + * Get PWM output level of onboard LED + */ +uint8_t board_get_led_pwm_off_level(void); + +/* + * Get GPIO pin level of onboard LED + */ +uint8_t board_get_led_gpio_off_level(void); #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/common/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c b/common/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c index 0dc8b5ff..1f92b468 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c +++ b/common/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 - 2022 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -41,6 +41,9 @@ void init_uart_pins(UART_Type *ptr) /* PZ port IO needs to configure BIOC as well */ HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_SOC_PZ_10; HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_SOC_PZ_11; + } else if (ptr == HPM_PUART) { + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_PUART_RXD; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_PUART_TXD; } } @@ -104,7 +107,8 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPIO_B_10; } else { - while(1); + while (1) { + } } } @@ -125,63 +129,113 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB14].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; } else { - while(1); + while (1) { + } } } void init_sdram_pins(void) { - HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_DRAM_DQ_14; - HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_DRAM_DQ_15; - HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_DRAM_DQ_12; - HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_DRAM_DQ_13; - HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_DRAM_DQ_00; - HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_DRAM_DQ_10; - HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_DRAM_DQ_11; - HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_DRAM_DQ_01; - HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_DRAM_DQ_08; - HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_DRAM_DQ_09; - HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_DRAM_DQ_04; - HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_DRAM_DQ_03; - HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_DRAM_DQ_02; - HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_DRAM_DQ_07; - HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_DRAM_DQ_06; - HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_DRAM_DQ_05; - - HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_DRAM_A_11; - HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_DRAM_A_09; - HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_DRAM_A_10; - HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_DRAM_A_08; - HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_DRAM_A_07; - HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_DRAM_A_06; - HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_DRAM_A_01; - HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_DRAM_A_00; - HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_DRAM_A_05; - HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_DRAM_A_04; - HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_DRAM_A_03; - HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_DRAM_A_02; - - HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_DRAM_BA1; - HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_DRAM_BA0; - HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_DRAM_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_DRAM_CLK; - HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_DRAM_CKE; - HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_DRAM_CS_0; - HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_DRAM_RAS; - HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_DRAM_CAS; - HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_DRAM_WE; - HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_DRAM_DM_0; - HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_DRAM_DM_1; + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_FEMC_DQ_14; + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_FEMC_DQ_15; + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_FEMC_DQ_12; + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_FEMC_DQ_13; + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_FEMC_DQ_00; + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_FEMC_DQ_10; + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_FEMC_DQ_11; + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_FEMC_DQ_01; + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_FEMC_DQ_08; + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_FEMC_DQ_09; + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_FEMC_DQ_04; + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_FEMC_DQ_03; + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_FEMC_DQ_02; + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_FEMC_DQ_07; + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_FEMC_DQ_06; + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_FEMC_DQ_05; + + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_FEMC_A_11; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_FEMC_A_09; + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_FEMC_A_10; + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_FEMC_A_08; + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_FEMC_A_07; + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_FEMC_A_06; + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_FEMC_A_01; + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_FEMC_A_00; + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_FEMC_A_05; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_FEMC_A_04; + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_FEMC_A_03; + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_FEMC_A_02; + + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_FEMC_BA1; + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_FEMC_BA0; + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_FEMC_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_FEMC_CLK; + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_FEMC_CKE; + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_FEMC_CS_0; + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_FEMC_RAS; + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_FEMC_CAS; + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_FEMC_WE; + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_FEMC_DM_0; + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_FEMC_DM_1; +} + +void init_sram_pins(void) +{ + /* Non-MUX */ /* MUX */ + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A0 */ /* A16 */ + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A1 */ /* A17 */ + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A2 */ /* A18 */ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A3 */ /* A19 */ + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A4 */ /* A20 */ + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A5 */ /* A21 */ + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A6 */ /* A22 */ + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A7 */ /* A23 */ + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A8 */ + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A9 */ + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A10 */ + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A11 */ + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A12 */ + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A13 */ + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A14 */ + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A15 */ + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A16 */ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A17 */ + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A18 */ + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A19 */ + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A20 */ + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A21 */ + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A22 */ + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A23 */ + + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D0 */ /* AD0 */ + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D1 */ /* AD1 */ + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D2 */ /* AD2 */ + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D3 */ /* AD3 */ + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D4 */ /* AD4 */ + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D5 */ /* AD5 */ + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D6 */ /* AD6 */ + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D7 */ /* AD7 */ + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D8 */ /* AD8 */ + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D9 */ /* AD9 */ + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D10 */ /* AD10 */ + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D11 */ /* AD11 */ + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D12 */ /* AD12 */ + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D13 */ /* AD13 */ + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D14 */ /* AD14 */ + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D15 */ /* AD15 */ + + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #CE */ + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #OE */ + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #WE */ + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #UB */ + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #LB */ + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #ADV */ } void init_gpio_pins(void) { uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - /* Green LED*/ - HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_GPIO_B_18; - HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL = pad_ctl; - #ifdef USING_GPIO0_FOR_GPIOZ HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl; @@ -488,3 +542,10 @@ void init_led_pins_as_gpio(void) HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19; HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20; } + +void init_enet_pps_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_ETH0_EVTO_0; + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_ETH0_EVTO_1; + HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_ETH0_EVTO_2; +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.h b/common/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.h index f772a0fc..de7de09f 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.h +++ b/common/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -17,6 +17,7 @@ void init_lcd_pins(LCDC_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_cap_pins(void); void init_sdram_pins(void); +void init_sram_pins(void); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); @@ -48,6 +49,8 @@ void init_beep_pwm_pins(void); void init_led_pins_as_pwm(void); void init_led_pins_as_gpio(void); void init_trgmux_pins(uint32_t pin); +void init_enet_pps_pins(void); + #ifdef __cplusplus } #endif diff --git a/common/libraries/hpm_sdk/boards/index.md b/common/libraries/hpm_sdk/boards/index.md deleted file mode 100644 index 06e9ecf9..00000000 --- a/common/libraries/hpm_sdk/boards/index.md +++ /dev/null @@ -1,41 +0,0 @@ -# HPM Development Board Introduction - -This chapter describes the board-related configuration - -:::{eval-rst} -.. toctree:: - :maxdepth: 3 - :numbered: - - hpm6750evk/README - hpm6750evkmini/README - hpm6300evk/README - ../doc/boards/README - -::: - -**Board level vocabulary cross-reference table** - -(lab_board_resource)= - -:::{tab} HPM6750EVK -Click [here](lab_hpm6750_evk_board) to view the HPM6750EVK development board -::: -:::{tab} HPM6750EVKMINI -Click [here](lab_hpm6750_evkmini_board) to view the HPM6750EVKMINI development board -::: -:::{tab} HPM6300EVK -Click [here](lab_hpm6300_evk_board) to view the HPM6300EVK development board -::: - -(lab_board_lcd_pin)= -(lab_board_app_i2c_pin)= -(lab_board_cam_i2c_pin)= -(lab_board_cap_i2c_pin)= -(lab_board_rgb_pin)= -(lab_board_app_spi_pin)= -(lab_board_drv_pwm_pin)= -(lab_board_motor_ctrl_pin)= -(lab_board_overiew)= -(lab_board_app_acmp_pin)= -(lab_board_app_gptmr_pin)= diff --git a/common/libraries/hpm_sdk/boards/index_zh.md b/common/libraries/hpm_sdk/boards/index_zh.md deleted file mode 100644 index 138303ea..00000000 --- a/common/libraries/hpm_sdk/boards/index_zh.md +++ /dev/null @@ -1,38 +0,0 @@ -# HPM 开发板介绍 - -:::{eval-rst} -.. toctree:: - :maxdepth: 3 - :numbered: - - hpm6750evk/README_zh - hpm6750evkmini/README_zh - hpm6300evk/README_zh - ../doc/boards/README_zh - -::: - -**开发板引脚对照表** - -:::{tab} HPM6750EVK -点击{ref}`此处 `查看HPM6750EVK开发板 -::: -:::{tab} HPM6750EVKMINI -点击{ref}`此处 `查看HPM6750EVKMINI开发板 -::: -:::{tab} HPM6300EVK -点击{ref}`此处 `查看HPM6300EVK开发板 -::: - -(lab_board_resource)= -(lab_board_lcd_pin)= -(lab_board_app_i2c_pin)= -(lab_board_cam_i2c_pin)= -(lab_board_cap_i2c_pin)= -(lab_board_rgb_pin)= -(lab_board_app_spi_pin)= -(lab_board_drv_pwm_pin)= -(lab_board_motor_ctrl_pin)= -(lab_board_overiew)= -(lab_board_app_acmp_pin)= -(lab_board_app_gptmr_pin)= diff --git a/common/libraries/hpm_sdk/boards/openocd/boards/hpm6300evk.cfg b/common/libraries/hpm_sdk/boards/openocd/boards/hpm6300evk.cfg index bca3b8dc..b572d4a0 100644 --- a/common/libraries/hpm_sdk/boards/openocd/boards/hpm6300evk.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/boards/hpm6300evk.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 @@ -25,144 +25,132 @@ proc init_clock {} { } proc init_sdram { } { -# configure dram frequency -# 133Mhz pll1_clk0: 266Mhz divide by 2 - #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 +# configure femc frequency +# 166Mhz pll0_clk1: 333Mhz divide by 2 + $::_TARGET0 riscv dmi_write 0x39 0xF4001808 $::_TARGET0 riscv dmi_write 0x3C 0x201 -# 166Mhz pll2_clk0: 333Mhz divide by 2 - $::_TARGET0 riscv dmi_write 0x39 0xF4001820 - $::_TARGET0 riscv dmi_write 0x3C 0x401 - # PD13 - $::_TARGET0 riscv dmi_write 0x39 0xF4040368 + # PA25 + $::_TARGET0 riscv dmi_write 0x39 0xF40400C8 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD12 - $::_TARGET0 riscv dmi_write 0x39 0xF4040360 + # PA26 + $::_TARGET0 riscv dmi_write 0x39 0xF40400D0 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD10 - $::_TARGET0 riscv dmi_write 0x39 0xF4040350 + # PA27 + $::_TARGET0 riscv dmi_write 0x39 0xF40400D8 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD09 - $::_TARGET0 riscv dmi_write 0x39 0xF4040348 + # PA28 + $::_TARGET0 riscv dmi_write 0x39 0xF40400E0 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD08 - $::_TARGET0 riscv dmi_write 0x39 0xF4040340 + # PA29 + $::_TARGET0 riscv dmi_write 0x39 0xF40400E8 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD07 - $::_TARGET0 riscv dmi_write 0x39 0xF4040338 + # PA30 + $::_TARGET0 riscv dmi_write 0x39 0xF40400F0 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD06 - $::_TARGET0 riscv dmi_write 0x39 0xF4040330 + # PA31 + $::_TARGET0 riscv dmi_write 0x39 0xF40400F8 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD05 - $::_TARGET0 riscv dmi_write 0x39 0xF4040328 + # PB00 + $::_TARGET0 riscv dmi_write 0x39 0xF4040100 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD04 - $::_TARGET0 riscv dmi_write 0x39 0xF4040320 + # PB01 + $::_TARGET0 riscv dmi_write 0x39 0xF4040108 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD03 - $::_TARGET0 riscv dmi_write 0x39 0xF4040318 + # PB02 + $::_TARGET0 riscv dmi_write 0x39 0xF4040110 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD02 - $::_TARGET0 riscv dmi_write 0x39 0xF4040310 + # PB03 + $::_TARGET0 riscv dmi_write 0x39 0xF4040118 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD01 - $::_TARGET0 riscv dmi_write 0x39 0xF4040308 + # PB04 + $::_TARGET0 riscv dmi_write 0x39 0xF4040120 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PD00 - $::_TARGET0 riscv dmi_write 0x39 0xF4040300 + # PB05 + $::_TARGET0 riscv dmi_write 0x39 0xF4040128 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC29 - $::_TARGET0 riscv dmi_write 0x39 0xF40402E8 + # PB06 + $::_TARGET0 riscv dmi_write 0x39 0xF4040130 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC28 - $::_TARGET0 riscv dmi_write 0x39 0xF40402E0 + # PB07 + $::_TARGET0 riscv dmi_write 0x39 0xF4040138 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC27 - $::_TARGET0 riscv dmi_write 0x39 0xF40402D8 + # PB08 + $::_TARGET0 riscv dmi_write 0x39 0xF4040140 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC22 - $::_TARGET0 riscv dmi_write 0x39 0xF40402B0 + # PB09 + $::_TARGET0 riscv dmi_write 0x39 0xF4040148 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC21 - $::_TARGET0 riscv dmi_write 0x39 0xF40402A8 + # PB10 + $::_TARGET0 riscv dmi_write 0x39 0xF4040150 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC17 - $::_TARGET0 riscv dmi_write 0x39 0xF4040288 + # PB11 + $::_TARGET0 riscv dmi_write 0x39 0xF4040158 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC15 - $::_TARGET0 riscv dmi_write 0x39 0xF4040278 + # PB12 + $::_TARGET0 riscv dmi_write 0x39 0xF4040160 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC12 - $::_TARGET0 riscv dmi_write 0x39 0xF4040260 + # PB13 + $::_TARGET0 riscv dmi_write 0x39 0xF4040168 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC11 - $::_TARGET0 riscv dmi_write 0x39 0xF4040258 + # PB14 + $::_TARGET0 riscv dmi_write 0x39 0xF4040170 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC10 - $::_TARGET0 riscv dmi_write 0x39 0xF4040250 + # PB15 + $::_TARGET0 riscv dmi_write 0x39 0xF4040178 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC09 - $::_TARGET0 riscv dmi_write 0x39 0xF4040248 + # PB16 + $::_TARGET0 riscv dmi_write 0x39 0xF4040180 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC08 - $::_TARGET0 riscv dmi_write 0x39 0xF4040240 + # PB17 + $::_TARGET0 riscv dmi_write 0x39 0xF4040188 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC07 - $::_TARGET0 riscv dmi_write 0x39 0xF4040238 + # PB18 + $::_TARGET0 riscv dmi_write 0x39 0xF4040190 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC06 - $::_TARGET0 riscv dmi_write 0x39 0xF4040230 + # PB19 + $::_TARGET0 riscv dmi_write 0x39 0xF4040198 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC05 - $::_TARGET0 riscv dmi_write 0x39 0xF4040228 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC04 - $::_TARGET0 riscv dmi_write 0x39 0xF4040220 + # PB20 + $::_TARGET0 riscv dmi_write 0x39 0xF40401A0 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC14 - $::_TARGET0 riscv dmi_write 0x39 0xF4040270 - $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC13 - $::_TARGET0 riscv dmi_write 0x39 0xF4040268 + # PB21 + $::_TARGET0 riscv dmi_write 0x39 0xF40401A8 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC16 - # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 - $::_TARGET0 riscv dmi_write 0x3C 0x1000C - # PC26 - $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 + # PB22 + $::_TARGET0 riscv dmi_write 0x39 0xF40401B0 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC25 - $::_TARGET0 riscv dmi_write 0x39 0xF40402C8 + # PB23 + $::_TARGET0 riscv dmi_write 0x39 0xF40401B8 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC19 - $::_TARGET0 riscv dmi_write 0x39 0xF4040298 + # PB24 + $::_TARGET0 riscv dmi_write 0x39 0xF40401C0 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC18 - $::_TARGET0 riscv dmi_write 0x39 0xF4040290 + # PB25 + $::_TARGET0 riscv dmi_write 0x39 0xF40401C8 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC23 - $::_TARGET0 riscv dmi_write 0x39 0xF40402B8 + # PB26 + $::_TARGET0 riscv dmi_write 0x39 0xF40401D0 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC24 - $::_TARGET0 riscv dmi_write 0x39 0xF40402C0 + # PB27 + $::_TARGET0 riscv dmi_write 0x39 0xF40401D8 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC30 - $::_TARGET0 riscv dmi_write 0x39 0xF40402F0 + # PB28 + $::_TARGET0 riscv dmi_write 0x39 0xF40401E0 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC31 - $::_TARGET0 riscv dmi_write 0x39 0xF40402F8 + # PB29 + $::_TARGET0 riscv dmi_write 0x39 0xF40401E8 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC02 - $::_TARGET0 riscv dmi_write 0x39 0xF4040210 + # PB30 + $::_TARGET0 riscv dmi_write 0x39 0xF40401F0 $::_TARGET0 riscv dmi_write 0x3C 0xC - # PC03 - $::_TARGET0 riscv dmi_write 0x39 0xF4040218 + # PB31 + $::_TARGET0 riscv dmi_write 0x39 0xF40401F8 $::_TARGET0 riscv dmi_write 0x3C 0xC - # dramc configuration + # femc configuration $::_TARGET0 riscv dmi_write 0x39 0xF3050000 $::_TARGET0 riscv dmi_write 0x3C 0x1 sleep 10 @@ -184,9 +172,6 @@ proc init_sdram { } { $::_TARGET0 riscv dmi_write 0x39 0xF3050040 $::_TARGET0 riscv dmi_write 0x3C 0xf31 - # 133Mhz configuration - #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 - $::_TARGET0 riscv dmi_write 0x3C 0x884e22 # 166Mhz configuration $::_TARGET0 riscv dmi_write 0x39 0xF3050044 $::_TARGET0 riscv dmi_write 0x3C 0x884e33 diff --git a/common/libraries/hpm_sdk/boards/openocd/boards/hpm6750evk.cfg b/common/libraries/hpm_sdk/boards/openocd/boards/hpm6750evk.cfg index 9f15d4c2..2953e08f 100644 --- a/common/libraries/hpm_sdk/boards/openocd/boards/hpm6750evk.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/boards/hpm6750evk.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause # openocd flash driver argument: @@ -71,10 +71,10 @@ proc init_clock {} { } proc init_sdram { } { -# configure dram frequency +# configure femc frequency # 133Mhz pll1_clk0: 266Mhz divide by 2 #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 - $::_TARGET0 riscv dmi_write 0x3C 0x201 + #$::_TARGET0 riscv dmi_write 0x3C 0x201 # 166Mhz pll2_clk0: 333Mhz divide by 2 $::_TARGET0 riscv dmi_write 0x39 0xF4001820 $::_TARGET0 riscv dmi_write 0x3C 0x401 @@ -256,7 +256,7 @@ proc init_sdram { } { $::_TARGET0 riscv dmi_write 0x39 0xF4040218 $::_TARGET0 riscv dmi_write 0x3C 0xC - # dramc configuration + # femc configuration $::_TARGET0 riscv dmi_write 0x39 0xF3050000 $::_TARGET0 riscv dmi_write 0x3C 0x1 sleep 10 @@ -278,7 +278,7 @@ proc init_sdram { } { # 133Mhz configuration #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 - $::_TARGET0 riscv dmi_write 0x3C 0x884e22 + #$::_TARGET0 riscv dmi_write 0x3C 0x884e22 # 166Mhz configuration $::_TARGET0 riscv dmi_write 0x39 0xF3050044 $::_TARGET0 riscv dmi_write 0x3C 0x884e33 diff --git a/common/libraries/hpm_sdk/boards/openocd/boards/hpm6750evkmini.cfg b/common/libraries/hpm_sdk/boards/openocd/boards/hpm6750evkmini.cfg index 686495c1..caa44037 100644 --- a/common/libraries/hpm_sdk/boards/openocd/boards/hpm6750evkmini.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/boards/hpm6750evkmini.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause # # openocd flash driver argument: @@ -71,10 +71,10 @@ proc init_clock {} { } proc init_sdram { } { -# configure dram frequency +# configure femc frequency # 133Mhz pll1_clk0: 266Mhz divide by 2 #$::_TARGET0 riscv dmi_write 0x39 0xF4001820 - $::_TARGET0 riscv dmi_write 0x3C 0x201 + #$::_TARGET0 riscv dmi_write 0x3C 0x201 # 166Mhz pll2_clk0: 333Mhz divide by 2 $::_TARGET0 riscv dmi_write 0x39 0xF4001820 $::_TARGET0 riscv dmi_write 0x3C 0x401 @@ -176,7 +176,7 @@ proc init_sdram { } { $::_TARGET0 riscv dmi_write 0x3C 0xC # PC16 # $::_TARGET0 riscv dmi_write 0x39 0xF4040280 - $::_TARGET0 riscv dmi_write 0x3C 0x1000C + #$::_TARGET0 riscv dmi_write 0x3C 0x1000C # PC26 $::_TARGET0 riscv dmi_write 0x39 0xF40402D0 $::_TARGET0 riscv dmi_write 0x3C 0xC @@ -208,7 +208,7 @@ proc init_sdram { } { $::_TARGET0 riscv dmi_write 0x39 0xF4040218 $::_TARGET0 riscv dmi_write 0x3C 0xC - # dramc configuration + # femc configuration $::_TARGET0 riscv dmi_write 0x39 0xF3050000 $::_TARGET0 riscv dmi_write 0x3C 0x1 sleep 10 @@ -232,7 +232,7 @@ proc init_sdram { } { # 133Mhz configuration #$::_TARGET0 riscv dmi_write 0x39 0xF3050044 - $::_TARGET0 riscv dmi_write 0x3C 0x884e22 + #$::_TARGET0 riscv dmi_write 0x3C 0x884e22 # 166Mhz configuration $::_TARGET0 riscv dmi_write 0x39 0xF3050044 $::_TARGET0 riscv dmi_write 0x3C 0x884e33 diff --git a/common/libraries/hpm_sdk/boards/openocd/hpm6300_all_in_one.cfg b/common/libraries/hpm_sdk/boards/openocd/hpm6300_all_in_one.cfg index f7fff1cb..6e388282 100644 --- a/common/libraries/hpm_sdk/boards/openocd/hpm6300_all_in_one.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/hpm6300_all_in_one.cfg @@ -1,4 +1,4 @@ -# Copyright 2022 hpmicro +# Copyright (c) 2022 HPMicro # SPDX-License-Identifier: BSD-3-Clause # # assumptions: diff --git a/common/libraries/hpm_sdk/boards/openocd/hpm6750_all_in_one.cfg b/common/libraries/hpm_sdk/boards/openocd/hpm6750_all_in_one.cfg index cc78b453..04d164bd 100644 --- a/common/libraries/hpm_sdk/boards/openocd/hpm6750_all_in_one.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/hpm6750_all_in_one.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause # # assumptions: diff --git a/common/libraries/hpm_sdk/boards/openocd/probes/cmsis_dap.cfg b/common/libraries/hpm_sdk/boards/openocd/probes/cmsis_dap.cfg index b9ae1121..0aa1eed3 100644 --- a/common/libraries/hpm_sdk/boards/openocd/probes/cmsis_dap.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/probes/cmsis_dap.cfg @@ -1,8 +1,8 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 -adapter speed 10000 +adapter speed 8000 adapter srst delay 500 source [find interface/cmsis-dap.cfg] diff --git a/common/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg b/common/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg index 580d98ef..782edbcf 100644 --- a/common/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 diff --git a/common/libraries/hpm_sdk/boards/openocd/probes/ft232.cfg b/common/libraries/hpm_sdk/boards/openocd/probes/ft232.cfg index 4fb0fba2..e2c01a2d 100644 --- a/common/libraries/hpm_sdk/boards/openocd/probes/ft232.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/probes/ft232.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 diff --git a/common/libraries/hpm_sdk/boards/openocd/probes/jlink.cfg b/common/libraries/hpm_sdk/boards/openocd/probes/jlink.cfg index fd8f0442..5d565c0e 100644 --- a/common/libraries/hpm_sdk/boards/openocd/probes/jlink.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/probes/jlink.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 diff --git a/common/libraries/hpm_sdk/boards/openocd/probes/nds_aice_micro.cfg b/common/libraries/hpm_sdk/boards/openocd/probes/nds_aice_micro.cfg index e9d6e6d6..a9421a83 100644 --- a/common/libraries/hpm_sdk/boards/openocd/probes/nds_aice_micro.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/probes/nds_aice_micro.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause bindto 0.0.0.0 diff --git a/common/libraries/hpm_sdk/boards/openocd/soc/hpm6360.cfg b/common/libraries/hpm_sdk/boards/openocd/soc/hpm6360.cfg index bfce20c2..472466ce 100644 --- a/common/libraries/hpm_sdk/boards/openocd/soc/hpm6360.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/soc/hpm6360.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause set _CHIP hpm6360 diff --git a/common/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg b/common/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg index 601b6809..32b87da2 100644 --- a/common/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause # @@ -36,8 +36,15 @@ proc dmi_read_memory {addr} { } proc release_core1 {} { - # set start point for core1 - dmi_write_memory 0xF4002C08 0x20016284 + + set chip_rev [dmi_read_memory 0x2001FF00] + + if {$chip_rev != 0x56010100 } { + # set start point for core1 + dmi_write_memory 0xF4002C08 0x20016284 + } else { + dmi_write_memory 0xF4002C08 0x2001660c + } # set boot flag for core1 dmi_write_memory 0xF4002C0C 0xC1BEF1A9 @@ -46,16 +53,15 @@ proc release_core1 {} { dmi_write_memory 0xF4002C00 0x1000 } -$_TARGET0 configure -event examine-end { - release_core1 -} - set _TARGET1 $_CHIP.cpu1 target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 $_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 -$_TARGET1 configure -event reset-deassert-pre { - $::_TARGET1 arp_poll +$_TARGET1 configure -event examine-start { release_core1 } +$_TARGET1 configure -event reset-deassert-pre { + $::_TARGET0 arp_poll + release_core1 +} diff --git a/common/libraries/hpm_sdk/boards/openocd/soc/hpm6750-single-core.cfg b/common/libraries/hpm_sdk/boards/openocd/soc/hpm6750-single-core.cfg index 8e2bbe5f..f873527f 100644 --- a/common/libraries/hpm_sdk/boards/openocd/soc/hpm6750-single-core.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/soc/hpm6750-single-core.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause set _CHIP hpm6750 diff --git a/common/libraries/hpm_sdk/components/SConscript b/common/libraries/hpm_sdk/components/SConscript index 112e98c3..5fe6980b 100644 --- a/common/libraries/hpm_sdk/components/SConscript +++ b/common/libraries/hpm_sdk/components/SConscript @@ -8,13 +8,14 @@ cwd = GetCurrentDir() CPPDEFINES=[] # Update include path -path = [ os.path.join(cwd, 'debug_console'), os.path.join(cwd, 'touch'), os.path.join(cwd, 'usb'), os.path.join(cwd, 'dma_manager') ] +path = [ os.path.join(cwd, 'debug_console'), os.path.join(cwd, 'touch'), os.path.join(cwd, 'usb'), os.path.join(cwd, 'dma_manager')] # The set of source files associated with this SConscript file. src = [] src += [ os.path.join(cwd, 'debug_console', 'hpm_debug_console.c') ] src += [ os.path.join(cwd, 'dma_manager', 'hpm_dma_manager.c') ] + if GetDepend(['BSP_USING_TOUCH_GT911']): src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_touch_gt911.c') ] src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_gt911.c') ] @@ -31,7 +32,12 @@ if GetDepend(['BSP_USING_USB_DEVICE']): if GetDepend(['BSP_USING_USB_HOST']): src += [ os.path.join(cwd, 'usb', 'host', 'hpm_usb_host.c') ] path += [ os.path.join(cwd, 'usb', 'host') ] - +if GetDepend(['BSP_USING_ETH1']): + if GetDepend(['BSP_USING_ENET_PHY_RTL8201']): + src += [ os.path.join(cwd, 'enet_phy/rtl8201/hpm_rtl8201.c') ] + path += [ os.path.join(cwd, 'enet_phy') ] + path += [ os.path.join(cwd, 'enet_phy/rtl8201') ] + group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) Return ('group') diff --git a/common/libraries/hpm_sdk/components/adc/hpm_adc.h b/common/libraries/hpm_sdk/components/adc/hpm_adc.h index 28a5043b..27198476 100644 --- a/common/libraries/hpm_sdk/components/adc/hpm_adc.h +++ b/common/libraries/hpm_sdk/components/adc/hpm_adc.h @@ -386,52 +386,63 @@ static inline void hpm_adc_init_seq_dma(adc_dma_config_t *config) } } - /** - * @brief Get ADC status flags. + * @brief Reset value of the WAIT_DIS bit. ADC blocks access to the associated peripheral bus + * until the ADC completes the conversion. * - * This function gets all ADC status flags. - * @param[in] ptr An ADC peripheral base address. - * @retval Status The ADC interrupt status flags. + * @param[in] config A pointer to configuration struct of "adc_dma_config_t". */ -static inline uint32_t hpm_adc_get_status_flags(adc_type *ptr) +static inline void hpm_adc_disable_busywait(adc_dma_config_t *config) { - if (ptr->module == adc_module_adc12) { + if (config->module == adc_module_adc12) { #ifdef CONFIG_HAS_HPMSDK_ADC12 - return adc12_get_status_flags(ptr->adc_base.adc12); -#else - return status_invalid_argument; + adc12_disable_busywait(config->adc_base.adc12); #endif - } else if (ptr->module == adc_module_adc16) { + } else if (config->module == adc_module_adc16) { #ifdef CONFIG_HAS_HPMSDK_ADC16 - return adc16_get_status_flags(ptr->adc_base.adc16); -#else - return status_invalid_argument; + adc16_disable_busywait(config->adc_base.adc16); #endif - } else { - return status_invalid_argument; } } /** - * @brief Get the setting value of wait disable. + * @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus + * until the ADC has completed its conversion. * - * This status flag is only used when wait_dis is set to disable. + * @param[in] config A pointer to configuration struct of "adc_dma_config_t". + */ +static inline void hpm_adc_enable_busywait(adc_dma_config_t *config) +{ + if (config->module == adc_module_adc12) { +#ifdef CONFIG_HAS_HPMSDK_ADC12 + adc12_enable_busywait(config->adc_base.adc12); +#endif + } else if (config->module == adc_module_adc16) { +#ifdef CONFIG_HAS_HPMSDK_ADC16 + adc16_enable_busywait(config->adc_base.adc16); +#endif + } +} + + +/** + * @brief Get ADC status flags. * + * This function gets all ADC status flags. * @param[in] ptr An ADC peripheral base address. - * @retval Status It means whether the current setting of wait disable is disable. + * @retval Status The ADC interrupt status flags. */ -static inline bool hpm_adc_get_wait_dis_status(adc_type *ptr) +static inline uint32_t hpm_adc_get_status_flags(adc_type *ptr) { if (ptr->module == adc_module_adc12) { #ifdef CONFIG_HAS_HPMSDK_ADC12 - return adc12_get_wait_dis_status(ptr->adc_base.adc12); + return adc12_get_status_flags(ptr->adc_base.adc12); #else return status_invalid_argument; #endif } else if (ptr->module == adc_module_adc16) { #ifdef CONFIG_HAS_HPMSDK_ADC16 - return adc16_get_wait_dis_status(ptr->adc_base.adc16); + return adc16_get_status_flags(ptr->adc_base.adc16); #else return status_invalid_argument; #endif diff --git a/common/libraries/hpm_sdk/components/camera/CMakeLists.txt b/common/libraries/hpm_sdk/components/camera/CMakeLists.txt index ebe911bc..917995fb 100644 --- a/common/libraries/hpm_sdk/components/camera/CMakeLists.txt +++ b/common/libraries/hpm_sdk/components/camera/CMakeLists.txt @@ -3,8 +3,8 @@ string(TOUPPER ${CONFIG_CAMERA} CONFIG_CAMERA_UPPER) string(TOLOWER ${CONFIG_CAMERA} CONFIG_CAMERA_LOWER) -if((NOT ${CONFIG_CAMERA_LOWER} STREQUAL "ov7725") AND (NOT ${CONFIG_CAMERA_LOWER} STREQUAL "ov5640")) -message(FATAL_ERROR "${CONFIG_CAMERA} is not supported, only \"ov7725\" or \"ov5640\" is supported") +if((NOT ${CONFIG_CAMERA_LOWER} STREQUAL "ov7725") AND (NOT ${CONFIG_CAMERA_LOWER} STREQUAL "ov5640") AND (NOT ${CONFIG_CAMERA_LOWER} STREQUAL "mt9m114")) +message(FATAL_ERROR "${CONFIG_CAMERA} is not supported, only \"ov7725\", \"ov5640\", \"mt9m114\" is supported") else() sdk_compile_definitions(-DCONFIG_CAMERA_${CONFIG_CAMERA_UPPER}=1) sdk_inc(.) diff --git a/common/libraries/hpm_sdk/components/camera/hpm_camera.h b/common/libraries/hpm_sdk/components/camera/hpm_camera.h index 86810128..e55587bf 100644 --- a/common/libraries/hpm_sdk/components/camera/hpm_camera.h +++ b/common/libraries/hpm_sdk/components/camera/hpm_camera.h @@ -8,14 +8,21 @@ #ifndef HPM_CAMERA_H #define HPM_CAMERA_H -#if CONFIG_CAMERA_OV7725 +#if defined(CONFIG_CAMERA_OV7725) && CONFIG_CAMERA_OV7725 #include "hpm_ov7725.h" #define CAMERA_MAX_IMAGE_OUTPUT_WIDTH OV7725_ACTIVE_IMAGE_WIDTH #define CAMERA_MAX_IMAGE_OUTPUT_HEIGHT OV7725_ACTIVE_IMAGE_HEIGHT -#elif CONFIG_CAMERA_OV5640 +#define CAMERA_DEVICE_ADDR OV7725_I2C_ADDR +#elif defined(CONFIG_CAMERA_OV5640) && CONFIG_CAMERA_OV5640 #include "hpm_ov5640.h" #define CAMERA_MAX_IMAGE_OUTPUT_WIDTH OV5640_ACTIVE_IMAGE_WIDTH #define CAMERA_MAX_IMAGE_OUTPUT_HEIGHT OV5640_ACTIVE_IMAGE_HEIGHT +#define CAMERA_DEVICE_ADDR OV5640_I2C_ADDR +#elif defined(CONFIG_CAMERA_MT9M114) && CONFIG_CAMERA_MT9M114 +#include "hpm_mt9m114.h" +#define CAMERA_MAX_IMAGE_OUTPUT_WIDTH MT9M114_ACTIVE_IMAGE_WIDTH +#define CAMERA_MAX_IMAGE_OUTPUT_HEIGHT MT9M114_ACTIVE_IMAGE_HEIGHT +#define CAMERA_DEVICE_ADDR MT9M114_I2C_ADDR #else #error "unknown camera type, either have CONFIG_CAMERA_OV7725 or CONFIG_CAMERA_OV5640 defined" #endif diff --git a/common/libraries/hpm_sdk/components/camera/hpm_camera_config.h b/common/libraries/hpm_sdk/components/camera/hpm_camera_config.h index f78f1436..c40b4fe3 100644 --- a/common/libraries/hpm_sdk/components/camera/hpm_camera_config.h +++ b/common/libraries/hpm_sdk/components/camera/hpm_camera_config.h @@ -20,8 +20,14 @@ typedef struct { void (*delay_ms)(uint32_t ms); void (*write_rst)(uint8_t state); void (*write_pwdn)(uint8_t state); + uint16_t i2c_device_addr; } camera_context_t; +typedef struct { + bool hsync_active_low; + bool vsync_active_low; +} camera_param_dvp_t; + typedef enum { camera_interface_dvp, camera_interface_mipi, @@ -32,6 +38,7 @@ typedef struct { uint32_t height; display_pixel_format_t pixel_format; camera_interface_t interface; + void *interface_param; } camera_config_t; /* Video Resolution definition. */ @@ -77,7 +84,7 @@ extern "C" { * camera device initialization */ hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config); - +hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config); #ifdef __cplusplus } #endif diff --git a/common/libraries/hpm_sdk/components/camera/mt9m114/CMakeLists.txt b/common/libraries/hpm_sdk/components/camera/mt9m114/CMakeLists.txt new file mode 100644 index 00000000..2dd7ceb6 --- /dev/null +++ b/common/libraries/hpm_sdk/components/camera/mt9m114/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +sdk_inc(.) +sdk_src(hpm_mt9m114.c) +sdk_src_ifdef(CONFIG_HPM_CAMERA hpm_camera_mt9m114.c) diff --git a/common/libraries/hpm_sdk/components/camera/mt9m114/hpm_camera_mt9m114.c b/common/libraries/hpm_sdk/components/camera/mt9m114/hpm_camera_mt9m114.c new file mode 100644 index 00000000..b6c12e37 --- /dev/null +++ b/common/libraries/hpm_sdk/components/camera/mt9m114/hpm_camera_mt9m114.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_mt9m114.h" + +static camera_param_dvp_t camera_dvp_param = { + .hsync_active_low = true, + .vsync_active_low = true, +}; + +hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config) +{ + assert(camera_context->delay_ms != NULL); + + hpm_stat_t stat = status_success; + + /* first check chipid */ + stat = mt9m114_check_chip_id(camera_context); + if (stat != status_success) { + return stat; + } + + /* software reset */ + stat = mt9m114_software_reset(camera_context); + if (stat != status_success) { + return stat; + } + camera_context->delay_ms(20); + + stat = mt9m114_init(camera_context, camera_config); + + return stat; +} + +hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config) +{ + camera_config->interface_param = (void *)&camera_dvp_param; + return status_success; +} diff --git a/common/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.c b/common/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.c new file mode 100644 index 00000000..9571a8f6 --- /dev/null +++ b/common/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.c @@ -0,0 +1,484 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_mt9m114.h" +#include "board.h" +#include "hpm_clock_drv.h" +#include + +#if defined(MT9M114_SHOW_DEBUG_INFO) && MT9M114_SHOW_DEBUG_INFO +#define DEBUG_INFO(...) printf(__VA_ARGS__) +#else +#define DEBUG_INFO(...) +#endif + +#if MT9M114_ERROR_ACTION_BLOCK +#define ERROR_ACTION() do { \ + DEBUG_INFO("[ERROR]:%s %d\n", __func__, __LINE__); \ + for (;;) { \ + } \ + } while (0) +#else +#define ERROR_ACTION() return (status_fail) +#endif + +const mt9m114_reg_t mt9m114_vga[] = { + {MT9M114_VAR_CAM_SENSOR_CFG_Y_ADDR_START, 2, 0x0000}, /* cam_sensor_cfg_y_addr_start = 0 */ + {MT9M114_VAR_CAM_SENSOR_CFG_X_ADDR_START, 2, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MT9M114_VAR_CAM_SENSOR_CFG_Y_ADDR_END, 2, 0x03CD}, /* cam_sensor_cfg_y_addr_end = 973 */ + {MT9M114_VAR_CAM_SENSOR_CFG_X_ADDR_END, 2, 0x050D}, /* cam_sensor_cfg_x_addr_end = 1293 */ + {MT9M114_VAR_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 0x01E3}, /* cam_sensor_cfg_cpipe_last_row = 483 */ + {MT9M114_VAR_CAM_CROP_WINDOW_WIDTH, 2, 0x0280}, /* cam_crop_window_width = 640 */ + {MT9M114_VAR_CAM_CROP_WINDOW_HEIGHT, 2, 0x01E0}, /* cam_crop_window_height = 480 */ + {MT9M114_VAR_CAM_OUTPUT_WIDTH, 2, 0x0280}, /* cam_output_width = 640 */ + {MT9M114_VAR_CAM_OUTPUT_HEIGHT, 2, 0x01E0}, /* cam_output_height = 480 */ + {MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 0x027F}, /* cam_stat_awb_clip_window_xend = 639 */ + {MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 0x01DF}, /* cam_stat_awb_clip_window_yend = 479 */ + {MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 0x007F}, /* cam_stat_ae_initial_window_xend = 127 */ + {MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 0x005F}, /* cam_stat_ae_initial_window_yend = 95 */ +}; + +const mt9m114_reg_t mt9m114_init_config[] = { + {MT9M114_REG_LOGICAL_ADDRESS_ACCESS, 2u, 0x1000}, + /* PLL Fout = (Fin * 2 * m) / ((n + 1) * (p + 1)) */ + {MT9M114_VAR_CAM_SYSCTL_PLL_ENABLE, 1u, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MT9M114_VAR_CAM_SYSCTL_PLL_DIVIDER_M_N, 2u, 0x0120}, /* cam_sysctl_pll_divider_m_n = 288 */ + {MT9M114_VAR_CAM_SYSCTL_PLL_DIVIDER_P, 2u, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MT9M114_VAR_CAM_SENSOR_CFG_PIXCLK, 4u, 0x2DC6C00}, /* cam_sensor_cfg_pixclk = 48000000 */ + {0x316A, 2, 0x8270}, /* auto txlo_row for hot pixel and linear full well optimization */ + {0x316C, 2, 0x8270}, /* auto txlo for hot pixel and linear full well optimization */ + {0x3ED0, 2, 0x2305}, /* eclipse setting, ecl range=1, ecl value=2, ivln=3 */ + {0x3ED2, 2, 0x77CF}, /* TX_hi=12 */ + {0x316E, 2, 0x8202}, /* auto ecl , threshold 2x, ecl=0 at high gain, ecl=2 for low gain */ + {0x3180, 2, 0x87FF}, /* enable delta dark */ + {0x30D4, 2, 0x6080}, /* disable column correction due to AE oscillation problem */ + {0xA802, 2, 0x0008}, /* RESERVED_AE_TRACK_02 */ + {0x3E14, 2, 0xFF39}, /* Enabling pixout clamping to VAA during ADC streaming to solve column band issue */ + /* APGA */ + {0xC95E, 2u, 0x0000}, + + {MT9M114_VAR_CAM_SENSOR_CFG_ROW_SPEED, 2u, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + {MT9M114_VAR_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN, 2u, 0x01C3}, /* cam_sensor_cfg_fine_integ_time_min = 451 */ + {MT9M114_VAR_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX, 2u, 0x03BA}, /* cam_sensor_cfg_fine_integ_time_max = 954 */ + {MT9M114_VAR_CAM_SENSOR_CFG_FRAME_LENGTH_LINES, 2u, 0x02DE}, /* cam_sensor_cfg_frame_length_lines = 734 */ + {MT9M114_VAR_CAM_SENSOR_CFG_LINE_LENGTH_PCK, 2u, 0x04A5}, /* cam_sensor_cfg_line_length_pck = 1189 */ + {MT9M114_VAR_CAM_SENSOR_CFG_FINE_CORRECTION, 2u, 0x00E0}, /* cam_sensor_cfg_fine_correction = 224 */ + {MT9M114_VAR_CAM_SENSOR_CFG_REG_0_DATA, 2u, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MT9M114_VAR_CAM_SENSOR_CONTROL_READ_MODE, 2u, 0x0332}, /* cam_sensor_control_read_mode = 816 */ + {MT9M114_VAR_CAM_CROP_WINDOW_XOFFSET, 2u, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MT9M114_VAR_CAM_CROP_WINDOW_YOFFSET, 2u, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MT9M114_VAR_CAM_CROP_CROPMODE, 1u, 0x03}, /* cam_crop_cropmode = 3 */ + {MT9M114_VAR_CAM_AET_AEMODE, 1u, 0x00}, /* cam_aet_aemode = 0 */ + {MT9M114_VAR_CAM_AET_MAX_FRAME_RATE, 2u, 0x3700}, /* cam_aet_max_frame_rate = 14080 */ + {MT9M114_VAR_CAM_AET_MIN_FRAME_RATE, 2u, 0x3700}, /* cam_aet_min_frame_rate = 14080 */ + + /* Camera control module */ + {0xC892, 2u, 0x0267}, + {0xC894, 2u, 0xFF1A}, + {0xC896, 2u, 0xFFB3}, + {0xC898, 2u, 0xFF80}, + {0xC89A, 2u, 0x0166}, + {0xC89C, 2u, 0x0003}, + {0xC89E, 2u, 0xFF9A}, + {0xC8A0, 2u, 0xFEB4}, + {0xC8A2, 2u, 0x024D}, + {0xC8A4, 2u, 0x01BF}, + {0xC8A6, 2u, 0xFF01}, + {0xC8A8, 2u, 0xFFF3}, + {0xC8AA, 2u, 0xFF75}, + {0xC8AC, 2u, 0x0198}, + {0xC8AE, 2u, 0xFFFD}, + {0xC8B0, 2u, 0xFF9A}, + {0xC8B2, 2u, 0xFEE7}, + {0xC8B4, 2u, 0x02A8}, + {0xC8B6, 2u, 0x01D9}, + {0xC8B8, 2u, 0xFF26}, + {0xC8BA, 2u, 0xFFF3}, + {0xC8BC, 2u, 0xFFB3}, + {0xC8BE, 2u, 0x0132}, + {0xC8C0, 2u, 0xFFE8}, + {0xC8C2, 2u, 0xFFDA}, + {0xC8C4, 2u, 0xFECD}, + {0xC8C6, 2u, 0x02C2}, + {0xC8C8, 2u, 0x0075}, + {0xC8CA, 2u, 0x011C}, + {0xC8CC, 2u, 0x009A}, + {0xC8CE, 2u, 0x0105}, + {0xC8D0, 2u, 0x00A4}, + {0xC8D2, 2u, 0x00AC}, + {0xC8D4, 2u, 0x0A8C}, + {0xC8D6, 2u, 0x0F0A}, + {0xC8D8, 2u, 0x1964}, + + /* Automatic White balance */ + {MT9M114_VAR_CAM_AWB_AWB_XSHIFT_PRE_ADJ, 2u, 0x0033}, + {MT9M114_VAR_CAM_AWB_AWB_YSHIFT_PRE_ADJ, 2u, 0x003C}, + {MT9M114_VAR_CAM_AWB_AWB_XSCALE, 1u, 0x03}, + {MT9M114_VAR_CAM_AWB_AWB_YSCALE, 1u, 0x02}, + {0xC8F4, 2u, 0x0000}, + {0xC8F6, 2u, 0x0000}, + {0xC8F8, 2u, 0x0000}, + {0xC8FA, 2u, 0xE724}, + {0xC8FC, 2u, 0x1583}, + {0xC8FE, 2u, 0x2045}, + {0xC900, 2u, 0x03FF}, + {0xC902, 2u, 0x007C}, + {0xC90C, 1u, 0x80}, + {0xC90D, 1u, 0x80}, + {0xC90E, 1u, 0x80}, + {0xC90F, 1u, 0x88}, + {0xC910, 1u, 0x80}, + {0xC911, 1u, 0x80}, + + /* CPIPE Preference */ + {0xC926, 2u, 0x0020}, + {0xC928, 2u, 0x009A}, + {0xC946, 2u, 0x0070}, + {0xC948, 2u, 0x00F3}, + {0xC944, 1u, 0x20}, + {0xC945, 1u, 0x9A}, + {0xC92A, 1u, 0x80}, + {0xC92B, 1u, 0x4B}, + {0xC92C, 1u, 0x00}, + {0xC92D, 1u, 0xFF}, + {0xC92E, 1u, 0x3C}, + {0xC92F, 1u, 0x02}, + {0xC930, 1u, 0x06}, + {0xC931, 1u, 0x64}, + {0xC932, 1u, 0x01}, + {0xC933, 1u, 0x0C}, + {0xC934, 1u, 0x3C}, + {0xC935, 1u, 0x3C}, + {0xC936, 1u, 0x3C}, + {0xC937, 1u, 0x0F}, + {0xC938, 1u, 0x64}, + {0xC939, 1u, 0x64}, + {0xC93A, 1u, 0x64}, + {0xC93B, 1u, 0x32}, + {0xC93C, 2u, 0x0020}, + {0xC93E, 2u, 0x009A}, + {0xC940, 2u, 0x00DC}, + {0xC942, 1u, 0x38}, + {0xC943, 1u, 0x30}, + {0xC944, 1u, 0x50}, + {0xC945, 1u, 0x19}, + {0xC94A, 2u, 0x0230}, + {0xC94C, 2u, 0x0010}, + {0xC94E, 2u, 0x01CD}, + {0xC950, 1u, 0x05}, + {0xC951, 1u, 0x40}, + {0xC87B, 1u, 0x1B}, + {0xC890, 2u, 0x0080}, + {0xC886, 2u, 0x0100}, + {0xC87C, 2u, 0x005A}, + {0xB42A, 1u, 0x05}, + {0xA80A, 1u, 0x20}, + + {MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_XSTART, 2u, 0x0000}, /* cam_stat_awb_clip_window_xstart = 0 */ + {MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_YSTART, 2u, 0x0000}, /* cam_stat_awb_clip_window_ystart = 0 */ + {MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_XSTART, 2u, 0x0000}, /* cam_stat_ae_initial_window_xstart = 0 */ + {MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_YSTART, 2u, 0x0000}, /* cam_stat_ae_initial_window_ystart = 0 */ + {MT9M114_REG_PAD_SLEW, 2u, 0x0777}, /* Pad slew rate */ + {MT9M114_VAR_CAM_OUTPUT_FORMAT_YUV, 2u, 0x0038}, /* Must set cam_output_format_yuv_clip for CSI */ +}; + +hpm_stat_t mt9m114_read_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, void *value) +{ + hpm_stat_t status; + uint16_t subaddr = ((reg & 0xff) << 8) | ((reg & 0xff00) >> 8); + uint8_t data[4]; + uint8_t i = 0; + + status = i2c_master_address_read(context->ptr, context->i2c_device_addr, \ + (uint8_t *)&subaddr, MT9M114_REG_ADDR_LEN, \ + data, reg_size); + if (status_success == status) { + while (reg_size--) { + ((uint8_t *)value)[i++] = data[reg_size]; + } + } + return status; +} + +hpm_stat_t mt9m114_write_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, uint32_t value) +{ + uint16_t subaddr = ((reg & 0xff) << 8) | ((reg & 0xff00) >> 8); + uint8_t data[4]; + uint8_t i; + + i = reg_size; + while (i--) { + data[i] = (uint8_t)value; + value >>= 8; + } + return i2c_master_address_write(context->ptr, context->i2c_device_addr, \ + (uint8_t *)&subaddr, MT9M114_REG_ADDR_LEN, \ + data, reg_size); +} + +hpm_stat_t mt9m114_modify_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, uint32_t mask, uint32_t value) +{ + hpm_stat_t status; + uint32_t reg_value; + + status = mt9m114_read_register(context, reg, reg_size, ®_value); + + if (status_success != status) { + return status; + } + + reg_value = (reg_value & ~(mask)) | (value & mask); + + return mt9m114_write_register(context, reg, reg_size, reg_value); +} + +hpm_stat_t mt9m114_multiwrite(camera_context_t *context, const mt9m114_reg_t regs[], uint32_t num) +{ + hpm_stat_t status = status_success; + + for (uint32_t i = 0; i < num; i++) { + status = mt9m114_write_register(context, regs[i].reg, regs[i].size, regs[i].value); + if (status_success != status) { + ERROR_ACTION(); + } + } + + return status; +} + +hpm_stat_t mt9m114_host_command(camera_context_t *context, uint16_t command) +{ + if (mt9m114_write_register(context, MT9M114_REG_COMMAND_REGISTER, 2, (command | MT9M114_COMMAND_OK)) != 0) { + return status_fail; + } + + for (int i = 0; i < MT9M114_HOST_CMD_TIMEOUT; i++, context->delay_ms(1)) { + uint16_t reg_data; + + if (mt9m114_read_register(context, MT9M114_REG_COMMAND_REGISTER, 2, ®_data) != 0) { + return status_fail; + } + + if ((reg_data & command) == 0) { + return (reg_data & MT9M114_COMMAND_OK) ? 0 : -1; + } + + if (i == (MT9M114_HOST_CMD_TIMEOUT - 1)) { + return status_fail; + } + } + + return status_success; +} + +hpm_stat_t mt9m114_refresh(camera_context_t *context) +{ + hpm_stat_t ret = mt9m114_host_command(context, MT9M114_COMMAND_REFRESH); + + if (ret != status_success) { + return ret; + } + + uint8_t reg_data; + + if (mt9m114_read_register(context, MT9M114_VAR_SEQ_ERROR_CODE, 1, ®_data) != 0) { + return status_fail; + } + + return reg_data == 0 ? status_success : status_fail; +} + +hpm_stat_t mt9m114_get_current_state(camera_context_t *context, uint8_t *state) +{ + return mt9m114_read_register(context, MT9M114_VAR_SYSMGR_CURRENT_STATE, 1u, state); +} + +hpm_stat_t mt9m114_software_reset(camera_context_t *context) +{ + hpm_stat_t status; + uint16_t value; + assert(context->delay_ms != NULL); + + mt9m114_modify_register(context, MT9M114_REG_RESET_AND_MISC_CONTROL, 2, 0x01, 0x01); + context->delay_ms(1); + mt9m114_modify_register(context, MT9M114_REG_RESET_AND_MISC_CONTROL, 2, 0x01, 0x00); + context->delay_ms(50); + + /* forever loop if softreset is not done. Loop until reg 0x80's bit 1 is 0 */ + while (1) { + status = mt9m114_read_register(context, MT9M114_REG_COMMAND_REGISTER, 2u, &value); + if (status != status_success) { + ERROR_ACTION(); + } + if (!(value & MT9M114_COMMAND_SET_STATE)) { + DEBUG_INFO("[Camera]:sw reset finish\n"); + break; + } + } + return status_success; +} + +hpm_stat_t mt9m114_setstate(camera_context_t *context, uint16_t next_state) +{ + uint16_t value; + hpm_stat_t status = status_success; + + /* Set the desired next state. */ + status = mt9m114_write_register(context, MT9M114_VAR_SYSMGR_NEXT_STATE, 1, next_state); + if (status_success != status) { + ERROR_ACTION(); + } + + /* Check that the FW is ready to accept a new command. */ + context->delay_ms(1); + while (1) { + status = mt9m114_read_register(context, MT9M114_REG_COMMAND_REGISTER, 2u, &value); + if (status_success != status) { + ERROR_ACTION(); + } + if (!(value & MT9M114_COMMAND_SET_STATE)) { + break; + } + DEBUG_INFO("[Camera]:Set State cmd bit is already set\n"); + } + DEBUG_INFO("[Camera]:Issue the Set State command 0x%x\n", next_state); + + /* Issue the Set State command. */ + return mt9m114_host_command(context, MT9M114_COMMAND_SET_STATE); +} + +hpm_stat_t mt9m114_set_pixformat(camera_context_t *context, display_pixel_format_t pixformat) +{ + uint16_t reg = 0; + + switch (pixformat) { + case display_pixel_format_yuv422: + reg = MT9M114_OUTPUT_FORMAT_YUV | MT9M114_OUTPUT_FORMAT_SWAP_BYTES; + break; + case display_pixel_format_rgb565: + reg = MT9M114_OUTPUT_FORMAT_RGB | MT9M114_OUTPUT_FORMAT_RGB565 | MT9M114_OUTPUT_FORMAT_SWAP_BYTES; + break; + default: + return status_invalid_argument; + } + + if (mt9m114_write_register(context, MT9M114_VAR_CAM_OUTPUT_FORMAT, 2, reg) != 0) { + return status_fail; + } + + return mt9m114_setstate(context, MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE); +} + +hpm_stat_t mt9m114_set_framerate(camera_context_t *context, int framerate) +{ + if (mt9m114_write_register(context, MT9M114_VAR_CAM_AET_MAX_FRAME_RATE, 2, framerate * 256) != 0) { + return status_fail; + } + + if (mt9m114_write_register(context, MT9M114_VAR_CAM_AET_MIN_FRAME_RATE, 2, framerate * 128) != 0) { + return status_fail; + } + + return mt9m114_setstate(context, MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE); +} + +hpm_stat_t mt9m114_set_brightness(camera_context_t *context, int level) /* -16 to +16 */ +{ + int new_level = level * 2; + + if ((new_level < -32) || (32 < new_level)) { + return status_fail; + } + + if (mt9m114_write_register(context, MT9M114_VAR_UVC_BRIGHTNESS_CONTROL, 2, new_level + 55) != 0) { + return status_fail; + } + + return mt9m114_refresh(context); +} + +hpm_stat_t mt9m114_start(camera_context_t *handle) +{ + return mt9m114_setstate(handle, MT9M114_SYS_STATE_START_STREAMING); +} + +hpm_stat_t mt9m114_stop(camera_context_t *handle) +{ + return mt9m114_setstate(handle, MT9M114_SYS_STATE_ENTER_SUSPEND); +} + +hpm_stat_t mt9m114_check_chip_id(camera_context_t *handle) +{ + hpm_stat_t status = status_success; + uint16_t chip_id; + + status = mt9m114_read_register(handle, MT9M114_REG_CHIP_ID, 2u, &chip_id); + if (status_success != status) { + DEBUG_INFO("[ERROR] read MT9M114 chipid register failed %d\n", status); + return status_fail; + } + if (MT9M114_CHIP_ID != chip_id) { + DEBUG_INFO("[ERROR] chipid is %04x(expect %04x)\n", chip_id, MT9M114_CHIP_ID); + return status_fail; + } + return status_success; +} + +hpm_stat_t mt9m114_enable_mono(camera_context_t *handle, bool enable) +{ + uint16_t value = 0; + mt9m114_read_register(handle, 0x332E, 2u, &value); + if (enable) + value = value | 0x0004; + else + value = value & 0xFFFB; + mt9m114_write_register(handle, 0x332E, 2u, value); + return 0; +} + +hpm_stat_t mt9m114_init(camera_context_t *context, camera_config_t *camera_config) +{ + hpm_stat_t status = status_success; + + /* set init configs */ + DEBUG_INFO("[Camera]:set frame per sec ...\n"); + mt9m114_multiwrite(context, mt9m114_init_config, ARRAY_SIZE(mt9m114_init_config)); + + /* Pixel format. */ + DEBUG_INFO("[Camera]:set format...\n"); + status = mt9m114_set_pixformat(context, camera_config->pixel_format); + if (status_success != status) { + DEBUG_INFO("[ERROR] set output format %d\n", status); + ERROR_ACTION(); + } + + /* set cam port output control... */ + DEBUG_INFO("[Camera]:set cam port output control...\n"); + status = mt9m114_write_register(context, MT9M114_VAR_CAM_PORT_OUTPUT_CONTROL, 2, 0x8008); + if (status_success != status) { + DEBUG_INFO("[ERROR] set cam port output control... %d\n", status); + ERROR_ACTION(); + } + + /* set resolution... */ + DEBUG_INFO("[Camera]:set resolution...\n"); + status = mt9m114_multiwrite(context, mt9m114_vga, ARRAY_SIZE(mt9m114_vga)); + if (status_success != status) { + DEBUG_INFO("[ERROR] set resolution... %d\n", status); + ERROR_ACTION(); + } + + /* set change command */ + DEBUG_INFO("[Camera]:set change command...\n"); + status = mt9m114_setstate(context, MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE); + if (status_success != status) { + DEBUG_INFO("[ERROR] set change command... %d\n", status); + ERROR_ACTION(); + } + DEBUG_INFO("MT9M114 init done\n"); + return status; +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.h b/common/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.h new file mode 100644 index 00000000..a8e2bf7a --- /dev/null +++ b/common/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.h @@ -0,0 +1,867 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MT9M114_H +#define HPM_MT9M114_H +#include "hpm_camera_config.h" +#include "hpm_common.h" + +/* MT9M114_ERROR_ACTION_BLOCK + * 0 : return fail + * 1 : print error message to console and block + */ +#define MT9M114_ERROR_ACTION_BLOCK 0 +#define MT9M114_HOST_CMD_TIMEOUT 100 + +#ifndef MT9M114_ACTIVE_IMAGE_WIDTH +#define MT9M114_ACTIVE_IMAGE_WIDTH (640U) +#endif + +#ifndef MT9M114_ACTIVE_IMAGE_HEIGHT +#define MT9M114_ACTIVE_IMAGE_HEIGHT (480U) +#endif + +#define DUMMY_LINES 8 +#define DUMMY_COLUMNS 8 + +#define SENSOR_WIDTH 1296 +#define SENSOR_HEIGHT 976 + +#define DUMMY_WIDTH_BUFFER 8 +#define DUMMY_HEIGHT_BUFFER 8 + +#define ACTIVE_SENSOR_WIDTH (SENSOR_WIDTH - (2 * DUMMY_COLUMNS)) +#define ACTIVE_SENSOR_HEIGHT (SENSOR_HEIGHT - (2 * DUMMY_LINES)) + +/** + * @brief MT9M114 sensor driver APIs + * @defgroup MT9M114_interface sensor driver APIs + * @ingroup component_interfaces + * @{ + * + + */ +/*********************************************************************************************************************** + * + * Definitions + * + **********************************************************************************************************************/ + +/** + * @brief MT9M114 definition + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(MT9M114_DUAL_CAMERA) +#define MT9M114_I2C_ADDR 0x48 +#define MT9M114_I2C_ADDR_IR 0x5D +#else +#define MT9M114_I2C_ADDR 0x48 +#endif +#define MT9M114_CHIP_ID 0x2481 + +#define MT9M114_REG_ADDR_LEN (2) + +/*! @brief MT9M114 register definitions.*/ + +/* 1.Core registers */ +#define MT9M114_REG_Y_ADDR_START 0x3002 +#define MT9M114_REG_X_ADDR_START 0x3004 +#define MT9M114_REG_Y_ADDR_END 0x3006 +#define MT9M114_REG_X_ADDR_END 0x3008 +#define MT9M114_REG_FRAME_LENGTH_LINES 0x300A +#define MT9M114_REG_LINE_LENGTH_PCK_ 0x300C +#define MT9M114_REG_COARSE_INTEGRATION_TIME 0x3012 +#define MT9M114_REG_FINE_INTEGRATION_TIME 0x3014 +#define MT9M114_REG_RESET_REGISTER 0x301A +#define MT9M114_REG_FLASH 0x3046 +#define MT9M114_REG_FLASH_COUNT 0x3048 +#define MT9M114_REG_GREEN1_GAIN 0x3056 +#define MT9M114_REG_BLUE_GAIN 0x3058 +#define MT9M114_REG_RED_GAIN 0x305A +#define MT9M114_REG_GREEN2_GAIN 0x305C +#define MT9M114_REG_GLOBAL_GAIN 0x305E +#define MT9M114_REG_FUSE_ID1 0x31F4 +#define MT9M114_REG_FUSE_ID2 0x31F6 +#define MT9M114_REG_FUSE_ID3 0x31F8 +#define MT9M114_REG_FUSE_ID4 0x31FA +#define MT9M114_REG_CHAIN_CONTROL 0x31FC +#define MT9M114_REG_CUSTOMER_REV 0x31FE + +/* 2.SOC1 registers */ +#define MT9M114_REG_COLOR_PIPELINE_CONTROL 0x3210 + +/* 3.SOC2 registers */ +#define MT9M114_REG_P_G1_P0Q0 0x3640 +#define MT9M114_REG_P_G1_P0Q1 0x3642 +#define MT9M114_REG_P_G1_P0Q2 0x3644 +#define MT9M114_REG_P_G1_P0Q3 0x3646 +#define MT9M114_REG_P_G1_P0Q4 0x3648 +#define MT9M114_REG_P_R_P0Q0 0x364A +#define MT9M114_REG_P_R_P0Q1 0x364C +#define MT9M114_REG_P_R_P0Q2 0x364E +#define MT9M114_REG_P_R_P0Q3 0x3650 +#define MT9M114_REG_P_R_P0Q4 0x3652 +#define MT9M114_REG_P_B_P0Q0 0x3654 +#define MT9M114_REG_P_B_P0Q1 0x3656 +#define MT9M114_REG_P_B_P0Q2 0x3658 +#define MT9M114_REG_P_B_P0Q3 0x365A +#define MT9M114_REG_P_B_P0Q4 0x365C +#define MT9M114_REG_P_G2_P0Q0 0x365E +#define MT9M114_REG_P_G2_P0Q1 0x3660 +#define MT9M114_REG_P_G2_P0Q2 0x3662 +#define MT9M114_REG_P_G2_P0Q3 0x3664 +#define MT9M114_REG_P_G2_P0Q4 0x3666 +#define MT9M114_REG_P_G1_P1Q0 0x3680 +#define MT9M114_REG_P_G1_P1Q1 0x3682 +#define MT9M114_REG_P_G1_P1Q2 0x3684 +#define MT9M114_REG_P_G1_P1Q3 0x3686 +#define MT9M114_REG_P_G1_P1Q4 0x3688 +#define MT9M114_REG_P_R_P1Q0 0x368A +#define MT9M114_REG_P_R_P1Q1 0x368C +#define MT9M114_REG_P_R_P1Q2 0x368E +#define MT9M114_REG_P_R_P1Q3 0x3690 +#define MT9M114_REG_P_R_P1Q4 0x3692 +#define MT9M114_REG_P_B_P1Q0 0x3694 +#define MT9M114_REG_P_B_P1Q1 0x3696 +#define MT9M114_REG_P_B_P1Q2 0x3698 +#define MT9M114_REG_P_B_P1Q3 0x369A +#define MT9M114_REG_P_B_P1Q4 0x369C +#define MT9M114_REG_P_G2_P1Q0 0x369E +#define MT9M114_REG_P_G2_P1Q1 0x36A0 +#define MT9M114_REG_P_G2_P1Q2 0x36A2 +#define MT9M114_REG_P_G2_P1Q3 0x36A4 +#define MT9M114_REG_P_G2_P1Q4 0x36A6 +#define MT9M114_REG_P_G1_P2Q0 0x36C0 +#define MT9M114_REG_P_G1_P2Q1 0x36C2 +#define MT9M114_REG_P_G1_P2Q2 0x36C4 +#define MT9M114_REG_P_G1_P2Q3 0x36C6 +#define MT9M114_REG_P_G1_P2Q4 0x36C8 +#define MT9M114_REG_P_R_P2Q0 0x36CA +#define MT9M114_REG_P_R_P2Q1 0x36CC +#define MT9M114_REG_P_R_P2Q2 0x36CE +#define MT9M114_REG_P_R_P2Q3 0x36D0 +#define MT9M114_REG_P_R_P2Q4 0x36D2 +#define MT9M114_REG_P_B_P2Q0 0x36D4 +#define MT9M114_REG_P_B_P2Q1 0x36D6 +#define MT9M114_REG_P_B_P2Q2 0x36D8 +#define MT9M114_REG_P_B_P2Q3 0x36DA +#define MT9M114_REG_P_B_P2Q4 0x36DC +#define MT9M114_REG_P_G2_P2Q0 0x36DE +#define MT9M114_REG_P_G2_P2Q1 0x36E0 +#define MT9M114_REG_P_G2_P2Q2 0x36E2 +#define MT9M114_REG_P_G2_P2Q3 0x36E4 +#define MT9M114_REG_P_G2_P2Q4 0x36E6 +#define MT9M114_REG_P_G1_P3Q0 0x3700 +#define MT9M114_REG_P_G1_P3Q1 0x3702 +#define MT9M114_REG_P_G1_P3Q2 0x3704 +#define MT9M114_REG_P_G1_P3Q3 0x3706 +#define MT9M114_REG_P_G1_P3Q4 0x3708 +#define MT9M114_REG_P_R_P3Q0 0x370A +#define MT9M114_REG_P_R_P3Q1 0x370C +#define MT9M114_REG_P_R_P3Q2 0x370E +#define MT9M114_REG_P_R_P3Q3 0x3710 +#define MT9M114_REG_P_R_P3Q4 0x3712 +#define MT9M114_REG_P_B_P3Q0 0x3714 +#define MT9M114_REG_P_B_P3Q1 0x3716 +#define MT9M114_REG_P_B_P3Q2 0x3718 +#define MT9M114_REG_P_B_P3Q3 0x371A +#define MT9M114_REG_P_B_P3Q4 0x371C +#define MT9M114_REG_P_G2_P3Q0 0x371E +#define MT9M114_REG_P_G2_P3Q1 0x3720 +#define MT9M114_REG_P_G2_P3Q2 0x3722 +#define MT9M114_REG_P_G2_P3Q3 0x3724 +#define MT9M114_REG_P_G2_P3Q4 0x3726 +#define MT9M114_REG_P_G1_P4Q0 0x3740 +#define MT9M114_REG_P_G1_P4Q1 0x3742 +#define MT9M114_REG_P_G1_P4Q2 0x3744 +#define MT9M114_REG_P_G1_P4Q3 0x3746 +#define MT9M114_REG_P_G1_P4Q4 0x3748 +#define MT9M114_REG_P_R_P4Q0 0x374A +#define MT9M114_REG_P_R_P4Q1 0x374C +#define MT9M114_REG_P_R_P4Q2 0x374E +#define MT9M114_REG_P_R_P4Q3 0x3750 +#define MT9M114_REG_P_R_P4Q4 0x3752 +#define MT9M114_REG_P_B_P4Q0 0x3754 +#define MT9M114_REG_P_B_P4Q1 0x3756 +#define MT9M114_REG_P_B_P4Q2 0x3758 +#define MT9M114_REG_P_B_P4Q3 0x375A +#define MT9M114_REG_P_B_P4Q4 0x375C +#define MT9M114_REG_P_G2_P4Q0 0x375E +#define MT9M114_REG_P_G2_P4Q1 0x3760 +#define MT9M114_REG_P_G2_P4Q2 0x3762 +#define MT9M114_REG_P_G2_P4Q3 0x3764 +#define MT9M114_REG_P_G2_P4Q4 0x3766 +#define MT9M114_REG_CENTER_ROW 0x3782 +#define MT9M114_REG_CENTER_COLUMN 0x3784 + +/* 4.SYSCTL registers */ +#define MT9M114_REG_CHIP_ID 0x0000 +#define MT9M114_REG_CLOCKS_CONTROL 0x0016 +#define MT9M114_REG_RESET_AND_MISC_CONTROL 0x001A +#define MT9M114_REG_PAD_SLEW 0x001E +#define MT9M114_REG_USER_DEFINED_DEVICE_ADDRESS_ID 0x002E +#define MT9M114_REG_PAD_CONTROL 0x0032 +#define MT9M114_REG_COMMAND_REGISTER 0x0080 + +/* 5.XDMA registers */ +#define MT9M114_REG_ACCESS_CTL_STAT 0x0982 +#define MT9M114_REG_PHYSICAL_ADDRESS_ACCESS 0x098A +#define MT9M114_REG_LOGICAL_ADDRESS_ACCESS 0x098E +#define MT9M114_REG_MCU_VARIABLE_DATA0 0x0990 +#define MT9M114_REG_MCU_VARIABLE_DATA1 0x0992 +#define MT9M114_REG_MCU_VARIABLE_DATA2 0x0994 +#define MT9M114_REG_MCU_VARIABLE_DATA3 0x0996 +#define MT9M114_REG_MCU_VARIABLE_DATA4 0x0998 +#define MT9M114_REG_MCU_VARIABLE_DATA5 0x099A +#define MT9M114_REG_MCU_VARIABLE_DATA6 0x099C +#define MT9M114_REG_MCU_VARIABLE_DATA7 0x099E + +/*! @brief MT9M114 variables definitions.*/ + +/* 01.Monitor variables */ +#define MT9M114_VAR_MON_MAJOR_VERSION 0x8000 +#define MT9M114_VAR_MON_MINOR_VERSION 0x8002 +#define MT9M114_VAR_MON_RELEASE_VERSION 0x8004 +#define MT9M114_VAR_MON_HEARTBEAT 0x8006 + +/* 02.Sequencer variables */ +#define MT9M114_VAR_SEQ_ERROR_CODE 0x8406 + +/* 03.AE_Rule variables */ +#define MT9M114_VAR_AE_RULE_ALGO 0xA404 +#define MT9M114_VAR_AE_RULE_AVG_Y_FROM_STATS 0xA406 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_0 0xA407 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_1 0xA408 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_2 0xA409 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_3 0xA40A +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_4 0xA40B +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_0 0xA40C +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_1 0xA40D +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_2 0xA40E +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_3 0xA40F +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_4 0xA410 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_0 0xA411 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_1 0xA412 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_2 0xA413 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_3 0xA414 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_4 0xA415 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_0 0xA416 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_1 0xA417 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_2 0xA418 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_3 0xA419 +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_4 0xA41A +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_0 0xA41B +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_1 0xA41C +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_2 0xA41D +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_3 0xA41E +#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_4 0xA41F +#define MT9M114_VAR_AE_RULE_AE_ADAPTIVE_STRENGTH 0xA420 + +/* 04.AE_Track variables */ +#define MT9M114_VAR_AE_TRACK_STATUS 0xA800 +#define MT9M114_VAR_AE_TRACK_ALGO 0xA804 +#define MT9M114_VAR_AE_TRACK_TARGET_AVERAGE_LUMA 0xA807 +#define MT9M114_VAR_AE_TRACK_GATE_PERCENTAGE 0xA808 +#define MT9M114_VAR_AE_TRACK_CURRENT_AVERAGE_LUMA 0xA809 +#define MT9M114_VAR_AE_TRACK_AE_TRACKING_DAMPENING_SPEED 0xA80A +#define MT9M114_VAR_AE_TRACK_AE_DAMPENING_SPEED 0xA80B +#define MT9M114_VAR_AE_TRACK_SKIP_FRAMES_COUNTER 0xA80D +#define MT9M114_VAR_AE_TRACK_CURRENT_FLICKER_LINES 0xA80E +#define MT9M114_VAR_AE_TRACK_FDZONE 0xA818 +#define MT9M114_VAR_AE_TRACK_ZONE 0xA81B +#define MT9M114_VAR_AE_TRACK_FLICKER_LINES_50HZ 0xA826 +#define MT9M114_VAR_AE_TRACK_VIRT_EXPOSURE_LOG 0xA828 +#define MT9M114_VAR_AE_TRACK_MIN_VIRT_EXPOSURE_LOG_ZONE0 0xA82A +#define MT9M114_VAR_AE_TRACK_MAX_VIRT_EXPOSURE_LOG_ZONE0 0xA82C +#define MT9M114_VAR_AE_TRACK_MAX_VIRT_EXPOSURE_LOG_ZONE1 0xA82E +#define MT9M114_VAR_AE_TRACK_VIRT_GAIN 0xA838 + +/* 05.AWB variables */ +#define MT9M114_VAR_AWB_STATUS 0xAC00 +#define MT9M114_VAR_AWB_MODE 0xAC02 +#define MT9M114_VAR_AWB_R_RATIO_LOWER 0xAC06 +#define MT9M114_VAR_AWB_R_RATIO_UPPER 0xAC07 +#define MT9M114_VAR_AWB_B_RATIO_LOWER 0xAC08 +#define MT9M114_VAR_AWB_B_RATIO_UPPER 0xAC09 +#define MT9M114_VAR_AWB_R_SCENE_RATIO_LOWER 0xAC0A +#define MT9M114_VAR_AWB_R_SCENE_RATIO_UPPER 0xAC0B +#define MT9M114_VAR_AWB_B_SCENE_RATIO_LOWER 0xAC0C +#define MT9M114_VAR_AWB_B_SCENE_RATIO_UPPER 0xAC0D +#define MT9M114_VAR_AWB_R_RATIO_PRE_AWB 0xAC0E +#define MT9M114_VAR_AWB_B_RATIO_PRE_AWB 0xAC0F +#define MT9M114_VAR_AWB_R_GAIN 0xAC12 +#define MT9M114_VAR_AWB_B_GAIN 0xAC14 +#define MT9M114_VAR_AWB_PRE_AWB_RATIOS_TRACKING_SPEED 0xAC16 +#define MT9M114_VAR_AWB_PIXEL_THRESHOLD_COUNT 0xAC18 + +/* 06.BlackLevel variables */ +#define MT9M114_VAR_BLACKLEVEL_ALGO 0xB004 +#define MT9M114_VAR_BLACKLEVEL_MAX_BLACK_LEVEL 0xB00C +#define MT9M114_VAR_BLACKLEVEL_BLACK_LEVEL_DAMPENING 0xB00D + +/* 07.CCM variables */ +#define MT9M114_VAR_CCM_ALGO 0xB404 +#define MT9M114_VAR_CCM_0 0xB406 +#define MT9M114_VAR_CCM_1 0xB408 +#define MT9M114_VAR_CCM_2 0xB40A +#define MT9M114_VAR_CCM_3 0xB40C +#define MT9M114_VAR_CCM_4 0xB40E +#define MT9M114_VAR_CCM_5 0xB410 +#define MT9M114_VAR_CCM_6 0xB412 +#define MT9M114_VAR_CCM_7 0xB414 +#define MT9M114_VAR_CCM_8 0xB416 +#define MT9M114_VAR_CCM_LL_DELTA_CCM_0 0xB418 +#define MT9M114_VAR_CCM_LL_DELTA_CCM_1 0xB41A +#define MT9M114_VAR_CCM_LL_DELTA_CCM_2 0xB41C +#define MT9M114_VAR_CCM_LL_DELTA_CCM_3 0xB41E +#define MT9M114_VAR_CCM_LL_DELTA_CCM_4 0xB420 +#define MT9M114_VAR_CCM_LL_DELTA_CCM_5 0xB422 +#define MT9M114_VAR_CCM_LL_DELTA_CCM_6 0xB424 +#define MT9M114_VAR_CCM_LL_DELTA_CCM_7 0xB426 +#define MT9M114_VAR_CCM_LL_DELTA_CCM_8 0xB428 +#define MT9M114_VAR_CCM_DELTA_GAIN 0xB42A +#define MT9M114_VAR_CCM_DELTA_THRESH 0xB42B + +/* 08.LowLight variables */ +#define MT9M114_VAR_LL_MODE 0xBC02 +#define MT9M114_VAR_LL_ALGO 0xBC04 +#define MT9M114_VAR_LL_GAMMA_SELECT 0xBC07 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_0 0xBC0A +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_1 0xBC0B +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_2 0xBC0C +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_3 0xBC0D +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_4 0xBC0E +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_5 0xBC0F +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_6 0xBC10 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_7 0xBC11 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_8 0xBC12 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_9 0xBC13 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_10 0xBC14 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_11 0xBC15 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_12 0xBC16 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_13 0xBC17 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_14 0xBC18 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_15 0xBC19 +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_16 0xBC1A +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_17 0xBC1B +#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_18 0xBC1C +#define MT9M114_VAR_LL_GAMMA_NRCURVE_0 0xBC1D +#define MT9M114_VAR_LL_GAMMA_NRCURVE_1 0xBC1E +#define MT9M114_VAR_LL_GAMMA_NRCURVE_2 0xBC1F +#define MT9M114_VAR_LL_GAMMA_NRCURVE_3 0xBC20 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_4 0xBC21 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_5 0xBC22 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_6 0xBC23 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_7 0xBC24 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_8 0xBC25 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_9 0xBC26 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_10 0xBC27 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_11 0xBC28 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_12 0xBC29 +#define MT9M114_VAR_LL_GAMMA_NRCURVE_13 0xBC2A +#define MT9M114_VAR_LL_GAMMA_NRCURVE_14 0xBC2B +#define MT9M114_VAR_LL_GAMMA_NRCURVE_15 0xBC2C +#define MT9M114_VAR_LL_GAMMA_NRCURVE_16 0xBC2D +#define MT9M114_VAR_LL_GAMMA_NRCURVE_17 0xBC2E +#define MT9M114_VAR_LL_GAMMA_NRCURVE_18 0xBC2F +#define MT9M114_VAR_LL_BM_PRECISION_BITS 0xBC31 +#define MT9M114_VAR_LL_AVERAGE_LUMA_FADE_TO_BLACK 0xBC3A +#define MT9M114_VAR_LL_FADE_TO_BLACK_DAMPENING_SPEED 0xBC3C + +/* 09.CameraControl variables */ +#define MT9M114_VAR_CAM_SENSOR_CFG_Y_ADDR_START 0xC800 +#define MT9M114_VAR_CAM_SENSOR_CFG_X_ADDR_START 0xC802 +#define MT9M114_VAR_CAM_SENSOR_CFG_Y_ADDR_END 0xC804 +#define MT9M114_VAR_CAM_SENSOR_CFG_X_ADDR_END 0xC806 +#define MT9M114_VAR_CAM_SENSOR_CFG_PIXCLK 0xC808 +#define MT9M114_VAR_CAM_SENSOR_CFG_ROW_SPEED 0xC80C +#define MT9M114_VAR_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN 0xC80E +#define MT9M114_VAR_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX 0xC810 +#define MT9M114_VAR_CAM_SENSOR_CFG_FRAME_LENGTH_LINES 0xC812 +#define MT9M114_VAR_CAM_SENSOR_CFG_LINE_LENGTH_PCK 0xC814 +#define MT9M114_VAR_CAM_SENSOR_CFG_FINE_CORRECTION 0xC816 +#define MT9M114_VAR_CAM_SENSOR_CFG_CPIPE_LAST_ROW 0xC818 +#define MT9M114_VAR_CAM_SENSOR_CFG_REG_0_DATA 0xC826 +#define MT9M114_VAR_CAM_SENSOR_CONTROL_READ_MODE 0xC834 +#define MT9M114_VAR_CAM_SENSOR_CONTROL_ANALOG_GAIN 0xC836 +#define MT9M114_VAR_CAM_SENSOR_CONTROL_VIRT_COLUMN_GAIN 0xC838 +#define MT9M114_VAR_CAM_SENSOR_CONTROL_FRAME_LENGTH_LINES 0xC83A +#define MT9M114_VAR_CAM_SENSOR_CONTROL_COARSE_INTEGRATION_TIME 0xC83C +#define MT9M114_VAR_CAM_SENSOR_CONTROL_FINE_INTEGRATION_TIME 0xC83E +#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_RED 0xC840 +#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_GREEN1 0xC842 +#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_GREEN2 0xC844 +#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_BLUE 0xC846 +#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_SECOND 0xC848 +#define MT9M114_VAR_CAM_CPIPE_CONTROL_SECOND_BLACK_LEVEL 0xC84B +#define MT9M114_VAR_CAM_MODE_SELECT 0xC84C +#define MT9M114_VAR_CAM_MODE_TEST_PATTERN_SELECT 0xC84D +#define MT9M114_VAR_CAM_MODE_TEST_PATTERN_RED 0xC84E +#define MT9M114_VAR_CAM_MODE_TEST_PATTERN_GREEN 0xC850 +#define MT9M114_VAR_CAM_MODE_TEST_PATTERN_BLUE 0xC852 +#define MT9M114_VAR_CAM_CROP_WINDOW_XOFFSET 0xC854 +#define MT9M114_VAR_CAM_CROP_WINDOW_YOFFSET 0xC856 +#define MT9M114_VAR_CAM_CROP_WINDOW_WIDTH 0xC858 +#define MT9M114_VAR_CAM_CROP_WINDOW_HEIGHT 0xC85A +#define MT9M114_VAR_CAM_CROP_CROPMODE 0xC85C +#define MT9M114_VAR_CAM_SCALE_VERTICAL_TC_MODE 0xC85E +#define MT9M114_VAR_CAM_SCALE_VERTICAL_TC_PERCENTAGE 0xC860 +#define MT9M114_VAR_CAM_SCALE_VERTICAL_TC_STRETCH_FACTOR 0xC862 +#define MT9M114_VAR_CAM_OUTPUT_WIDTH 0xC868 +#define MT9M114_VAR_CAM_OUTPUT_HEIGHT 0xC86A +#define MT9M114_VAR_CAM_OUTPUT_FORMAT 0xC86C +#define MT9M114_VAR_CAM_OUTPUT_FORMAT_YUV 0xC86E +#define MT9M114_VAR_CAM_OUTPUT_Y_OFFSET 0xC870 +#define MT9M114_VAR_CAM_HUE_ANGLE 0xC873 +#define MT9M114_VAR_CAM_SFX_CONTROL 0xC874 +#define MT9M114_VAR_CAM_SFX_SOLARIZATION_THRESH 0xC875 +#define MT9M114_VAR_CAM_SFX_SEPIA_CR 0xC876 +#define MT9M114_VAR_CAM_SFX_SEPIA_CB 0xC877 +#define MT9M114_VAR_CAM_AET_AEMODE 0xC878 +#define MT9M114_VAR_CAM_AET_SKIP_FRAMES 0xC879 +#define MT9M114_VAR_CAM_AET_TARGET_AVERAGE_LUMA 0xC87A +#define MT9M114_VAR_CAM_AET_TARGET_AVERAGE_LUMA_DARK 0xC87B +#define MT9M114_VAR_CAM_AET_BLACK_CLIPPING_TARGET 0xC87C +#define MT9M114_VAR_CAM_AET_AE_MIN_VIRT_INT_TIME_PCLK 0xC87E +#define MT9M114_VAR_CAM_AET_AE_MIN_VIRT_DGAIN 0xC880 +#define MT9M114_VAR_CAM_AET_AE_MAX_VIRT_DGAIN 0xC882 +#define MT9M114_VAR_CAM_AET_AE_MIN_VIRT_AGAIN 0xC884 +#define MT9M114_VAR_CAM_AET_AE_MAX_VIRT_AGAIN 0xC886 +#define MT9M114_VAR_CAM_AET_AE_VIRT_GAIN_TH_EG 0xC888 +#define MT9M114_VAR_CAM_AET_AE_EG_GATE_PERCENTAGE 0xC88A +#define MT9M114_VAR_CAM_AET_FLICKER_FREQ_HZ 0xC88B +#define MT9M114_VAR_CAM_AET_MAX_FRAME_RATE 0xC88C +#define MT9M114_VAR_CAM_AET_MIN_FRAME_RATE 0xC88E +#define MT9M114_VAR_CAM_AET_TARGET_GAIN 0xC890 +#define MT9M114_VAR_CAM_AWB_CCM_L_0 0xC892 +#define MT9M114_VAR_CAM_AWB_CCM_L_1 0xC894 +#define MT9M114_VAR_CAM_AWB_CCM_L_2 0xC896 +#define MT9M114_VAR_CAM_AWB_CCM_L_3 0xC898 +#define MT9M114_VAR_CAM_AWB_CCM_L_4 0xC89A +#define MT9M114_VAR_CAM_AWB_CCM_L_5 0xC89C +#define MT9M114_VAR_CAM_AWB_CCM_L_6 0xC89E +#define MT9M114_VAR_CAM_AWB_CCM_L_7 0xC8A0 +#define MT9M114_VAR_CAM_AWB_CCM_L_8 0xC8A2 +#define MT9M114_VAR_CAM_AWB_CCM_M_0 0xC8A4 +#define MT9M114_VAR_CAM_AWB_CCM_M_1 0xC8A6 +#define MT9M114_VAR_CAM_AWB_CCM_M_2 0xC8A8 +#define MT9M114_VAR_CAM_AWB_CCM_M_3 0xC8AA +#define MT9M114_VAR_CAM_AWB_CCM_M_4 0xC8AC +#define MT9M114_VAR_CAM_AWB_CCM_M_5 0xC8AE +#define MT9M114_VAR_CAM_AWB_CCM_M_6 0xC8B0 +#define MT9M114_VAR_CAM_AWB_CCM_M_7 0xC8B2 +#define MT9M114_VAR_CAM_AWB_CCM_M_8 0xC8B4 +#define MT9M114_VAR_CAM_AWB_CCM_R_0 0xC8B6 +#define MT9M114_VAR_CAM_AWB_CCM_R_1 0xC8B8 +#define MT9M114_VAR_CAM_AWB_CCM_R_2 0xC8BA +#define MT9M114_VAR_CAM_AWB_CCM_R_3 0xC8BC +#define MT9M114_VAR_CAM_AWB_CCM_R_4 0xC8BE +#define MT9M114_VAR_CAM_AWB_CCM_R_5 0xC8C0 +#define MT9M114_VAR_CAM_AWB_CCM_R_6 0xC8C2 +#define MT9M114_VAR_CAM_AWB_CCM_R_7 0xC8C4 +#define MT9M114_VAR_CAM_AWB_CCM_R_8 0xC8C6 +#define MT9M114_VAR_CAM_AWB_CCM_L_RG_GAIN 0xC8C8 +#define MT9M114_VAR_CAM_AWB_CCM_L_BG_GAIN 0xC8CA +#define MT9M114_VAR_CAM_AWB_CCM_M_RG_GAIN 0xC8CC +#define MT9M114_VAR_CAM_AWB_CCM_M_BG_GAIN 0xC8CE +#define MT9M114_VAR_CAM_AWB_CCM_R_RG_GAIN 0xC8D0 +#define MT9M114_VAR_CAM_AWB_CCM_R_BG_GAIN 0xC8D2 +#define MT9M114_VAR_CAM_AWB_CCM_L_CTEMP 0xC8D4 +#define MT9M114_VAR_CAM_AWB_CCM_M_CTEMP 0xC8D6 +#define MT9M114_VAR_CAM_AWB_CCM_R_CTEMP 0xC8D8 +#define MT9M114_VAR_CAM_AWB_LL_CCM_0 0xC8DA +#define MT9M114_VAR_CAM_AWB_LL_CCM_1 0xC8DC +#define MT9M114_VAR_CAM_AWB_LL_CCM_2 0xC8DE +#define MT9M114_VAR_CAM_AWB_LL_CCM_3 0xC8E0 +#define MT9M114_VAR_CAM_AWB_LL_CCM_4 0xC8E2 +#define MT9M114_VAR_CAM_AWB_LL_CCM_5 0xC8E4 +#define MT9M114_VAR_CAM_AWB_LL_CCM_6 0xC8E6 +#define MT9M114_VAR_CAM_AWB_LL_CCM_7 0xC8E8 +#define MT9M114_VAR_CAM_AWB_LL_CCM_8 0xC8EA +#define MT9M114_VAR_CAM_AWB_COLOR_TEMPERATURE_MIN 0xC8EC +#define MT9M114_VAR_CAM_AWB_COLOR_TEMPERATURE_MAX 0xC8EE +#define MT9M114_VAR_CAM_AWB_COLOR_TEMPERATURE 0xC8F0 +#define MT9M114_VAR_CAM_AWB_AWB_XSCALE 0xC8F2 +#define MT9M114_VAR_CAM_AWB_AWB_YSCALE 0xC8F3 +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_0 0xC8F4 +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_1 0xC8F6 +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_2 0xC8F8 +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_3 0xC8FA +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_4 0xC8FC +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_5 0xC8FE +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_6 0xC900 +#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_7 0xC902 +#define MT9M114_VAR_CAM_AWB_AWB_XSHIFT_PRE_ADJ 0xC904 +#define MT9M114_VAR_CAM_AWB_AWB_YSHIFT_PRE_ADJ 0xC906 +#define MT9M114_VAR_CAM_AWB_AWBMODE 0xC909 +#define MT9M114_VAR_CAM_AWB_TINTS_CTEMP_THRESHOLD 0xC90A +#define MT9M114_VAR_CAM_AWB_K_R_L 0xC90C +#define MT9M114_VAR_CAM_AWB_K_G_L 0xC90D +#define MT9M114_VAR_CAM_AWB_K_B_L 0xC90E +#define MT9M114_VAR_CAM_AWB_K_R_R 0xC90F +#define MT9M114_VAR_CAM_AWB_K_G_R 0xC910 +#define MT9M114_VAR_CAM_AWB_K_B_R 0xC911 +#define MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_XSTART 0xC914 +#define MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_YSTART 0xC916 +#define MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_XEND 0xC918 +#define MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_YEND 0xC91A +#define MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_XSTART 0xC91C +#define MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_YSTART 0xC91E +#define MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_XEND 0xC920 +#define MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_YEND 0xC922 +#define MT9M114_VAR_CAM_LL_LLMODE 0xC924 +#define MT9M114_VAR_CAM_LL_START_BRIGHTNESS 0xC926 +#define MT9M114_VAR_CAM_LL_STOP_BRIGHTNESS 0xC928 +#define MT9M114_VAR_CAM_LL_START_SATURATION 0xC92A +#define MT9M114_VAR_CAM_LL_END_SATURATION 0xC92B +#define MT9M114_VAR_CAM_LL_START_DESATURATION 0xC92C +#define MT9M114_VAR_CAM_LL_END_DESATURATION 0xC92D +#define MT9M114_VAR_CAM_LL_START_DEMOSAIC 0xC92E +#define MT9M114_VAR_CAM_LL_START_AP_GAIN 0xC92F +#define MT9M114_VAR_CAM_LL_START_AP_THRESH 0xC930 +#define MT9M114_VAR_CAM_LL_STOP_DEMOSAIC 0xC931 +#define MT9M114_VAR_CAM_LL_STOP_AP_GAIN 0xC932 +#define MT9M114_VAR_CAM_LL_STOP_AP_THRESH 0xC933 +#define MT9M114_VAR_CAM_LL_START_NR_RED 0xC934 +#define MT9M114_VAR_CAM_LL_START_NR_GREEN 0xC935 +#define MT9M114_VAR_CAM_LL_START_NR_BLUE 0xC936 +#define MT9M114_VAR_CAM_LL_START_NR_THRESH 0xC937 +#define MT9M114_VAR_CAM_LL_STOP_NR_RED 0xC938 +#define MT9M114_VAR_CAM_LL_STOP_NR_GREEN 0xC939 +#define MT9M114_VAR_CAM_LL_STOP_NR_BLUE 0xC93A +#define MT9M114_VAR_CAM_LL_STOP_NR_THRESH 0xC93B +#define MT9M114_VAR_CAM_LL_START_CONTRAST_BM 0xC93C +#define MT9M114_VAR_CAM_LL_STOP_CONTRAST_BM 0xC93E +#define MT9M114_VAR_CAM_LL_GAMMA 0xC940 +#define MT9M114_VAR_CAM_LL_START_CONTRAST_GRADIENT 0xC942 +#define MT9M114_VAR_CAM_LL_STOP_CONTRAST_GRADIENT 0xC943 +#define MT9M114_VAR_CAM_LL_START_CONTRAST_LUMA_PERCENTAGE 0xC944 +#define MT9M114_VAR_CAM_LL_STOP_CONTRAST_LUMA_PERCENTAGE 0xC945 +#define MT9M114_VAR_CAM_LL_START_GAIN_METRIC 0xC946 +#define MT9M114_VAR_CAM_LL_STOP_GAIN_METRIC 0xC948 +#define MT9M114_VAR_CAM_LL_START_FADE_TO_BLACK_LUMA 0xC94A +#define MT9M114_VAR_CAM_LL_STOP_FADE_TO_BLACK_LUMA 0xC94C +#define MT9M114_VAR_CAM_LL_CLUSTER_DC_TH_BM 0xC94E +#define MT9M114_VAR_CAM_LL_CLUSTER_DC_GATE_PERCENTAGE 0xC950 +#define MT9M114_VAR_CAM_LL_SUMMING_SENSITIVITY_FACTOR 0xC951 +#define MT9M114_VAR_CAM_LL_START_TARGET_LUMA_BM 0xC952 +#define MT9M114_VAR_CAM_LL_STOP_TARGET_LUMA_BM 0xC954 +#define MT9M114_VAR_CAM_LL_INV_BRIGHTNESS_METRIC 0xC956 +#define MT9M114_VAR_CAM_LL_GAIN_METRIC 0xC958 +#define MT9M114_VAR_CAM_SEQ_UV_COLOR_BOOST 0xC95A +#define MT9M114_VAR_CAM_PGA_PGA_CONTROL 0xC95E +#define MT9M114_VAR_CAM_PGA_L_CONFIG_COLOUR_TEMP 0xC960 +#define MT9M114_VAR_CAM_PGA_L_CONFIG_GREEN_RED_Q14 0xC962 +#define MT9M114_VAR_CAM_PGA_L_CONFIG_RED_Q14 0xC964 +#define MT9M114_VAR_CAM_PGA_L_CONFIG_GREEN_BLUE_Q14 0xC966 +#define MT9M114_VAR_CAM_PGA_L_CONFIG_BLUE_Q14 0xC968 +#define MT9M114_VAR_CAM_PGA_M_CONFIG_COLOUR_TEMP 0xC96A +#define MT9M114_VAR_CAM_PGA_M_CONFIG_GREEN_RED_Q14 0xC96C +#define MT9M114_VAR_CAM_PGA_M_CONFIG_RED_Q14 0xC96E +#define MT9M114_VAR_CAM_PGA_M_CONFIG_GREEN_BLUE_Q14 0xC970 +#define MT9M114_VAR_CAM_PGA_M_CONFIG_BLUE_Q14 0xC972 +#define MT9M114_VAR_CAM_PGA_R_CONFIG_COLOUR_TEMP 0xC974 +#define MT9M114_VAR_CAM_PGA_R_CONFIG_GREEN_RED_Q14 0xC976 +#define MT9M114_VAR_CAM_PGA_R_CONFIG_RED_Q14 0xC978 +#define MT9M114_VAR_CAM_PGA_R_CONFIG_GREEN_BLUE_Q14 0xC97A +#define MT9M114_VAR_CAM_PGA_R_CONFIG_BLUE_Q14 0xC97C +#define MT9M114_VAR_CAM_SYSCTL_PLL_ENABLE 0xC97E +#define MT9M114_VAR_CAM_SYSCTL_PLL_DIVIDER_M_N 0xC980 +#define MT9M114_VAR_CAM_SYSCTL_PLL_DIVIDER_P 0xC982 +#define MT9M114_VAR_CAM_PORT_OUTPUT_CONTROL 0xC984 +#define MT9M114_VAR_CAM_PORT_PORCH 0xC986 +#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_HS_ZERO 0xC988 +#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_HS_EXIT_HS_TRAIL 0xC98A +#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_CLK_POST_CLK_PRE 0xC98C +#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_CLK_TRAIL_CLK_ZERO 0xC98E +#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_LPX 0xC990 +#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_INIT_TIMING 0xC992 + +/* 10.UVC_Control variables */ +#define MT9M114_VAR_UVC_AE_MODE_CONTROL 0xCC00 +#define MT9M114_VAR_UVC_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0xCC01 +#define MT9M114_VAR_UVC_AE_PRIORITY_CONTROL 0xCC02 +#define MT9M114_VAR_UVC_POWER_LINE_FREQUENCY_CONTROL 0xCC03 +#define MT9M114_VAR_UVC_EXPOSURE_TIME_ABSOLUTE_CONTROL 0xCC04 +#define MT9M114_VAR_UVC_BACKLIGHT_COMPENSATION_CONTROL 0xCC08 +#define MT9M114_VAR_UVC_BRIGHTNESS_CONTROL 0xCC0A +#define MT9M114_VAR_UVC_CONTRAST_CONTROL 0xCC0C +#define MT9M114_VAR_UVC_GAIN_CONTROL 0xCC0E +#define MT9M114_VAR_UVC_HUE_CONTROL 0xCC10 +#define MT9M114_VAR_UVC_SATURATION_CONTROL 0xCC12 +#define MT9M114_VAR_UVC_SHARPNESS_CONTROL 0xCC14 +#define MT9M114_VAR_UVC_GAMMA_CONTROL 0xCC16 +#define MT9M114_VAR_UVC_WHITE_BALANCE_TEMPERATURE_CONTROL 0xCC18 +#define MT9M114_VAR_UVC_FRAME_INTERVAL_CONTROL 0xCC1C +#define MT9M114_VAR_UVC_MANUAL_EXPOSURE_CONFIGURATION 0xCC20 +#define MT9M114_VAR_UVC_FLICKER_AVOIDANCE_CONFIGURATION 0xCC21 +#define MT9M114_VAR_UVC_ALGO 0xCC22 +#define MT9M114_VAR_UVC_RESULT_STATUS 0xCC24 + +/* 11.SystemManager variables */ +#define MT9M114_VAR_SYSMGR_NEXT_STATE 0xDC00 +#define MT9M114_VAR_SYSMGR_CURRENT_STATE 0xDC01 +#define MT9M114_VAR_SYSMGR_CMD_STATUS 0xDC02 + +/* 12.PatchLoader variables */ +#define MT9M114_VAR_PATCHLDR_LOADER_ADDRESS 0xE000 +#define MT9M114_VAR_PATCHLDR_PATCH_ID 0xE002 +#define MT9M114_VAR_PATCHLDR_FIRMWARE_ID 0xE004 +#define MT9M114_VAR_PATCHLDR_APPLY_STATUS 0xE008 +#define MT9M114_VAR_PATCHLDR_NUM_PATCHES 0xE009 +#define MT9M114_VAR_PATCHLDR_PATCH_ID_0 0xE00A +#define MT9M114_VAR_PATCHLDR_PATCH_ID_1 0xE00C +#define MT9M114_VAR_PATCHLDR_PATCH_ID_2 0xE00E +#define MT9M114_VAR_PATCHLDR_PATCH_ID_3 0xE010 +#define MT9M114_VAR_PATCHLDR_PATCH_ID_4 0xE012 +#define MT9M114_VAR_PATCHLDR_PATCH_ID_5 0xE014 +#define MT9M114_VAR_PATCHLDR_PATCH_ID_6 0xE016 +#define MT9M114_VAR_PATCHLDR_PATCH_ID_7 0xE018 + +/* 13.Patch variables */ +#define MT9M114_VAR_PATCHVARS_DELTA_DK_CORRECTION_FACTOR 0xE400 +#define MT9M114_VAR_CAM_AUTO_BINNING_MODE (0xE801) + +/* 14.CommandHandler variables */ +#define MT9M114_VAR_CMD_HANDLER_WAIT_EVENT_ID 0xFC00 +#define MT9M114_VAR_CMD_HANDLER_NUM_EVENTS 0xFC02 + +/*! @brief MT9M114 command definitions. */ +#define MT9M114_COMMAND_APPLY_PATCH 0x0001 +#define MT9M114_COMMAND_SET_STATE 0x0002 +#define MT9M114_COMMAND_REFRESH 0x0004 +#define MT9M114_COMMAND_WAIT_FOR_EVENT 0x0008 +#define MT9M114_COMMAND_OK 0x8000 + +/*! @brief MT9M114 system state definitions. */ +#define MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE 0x28 +#define MT9M114_SYS_STATE_STREAMING 0x31 +#define MT9M114_SYS_STATE_START_STREAMING 0x34 +#define MT9M114_SYS_STATE_ENTER_SUSPEND 0x40 +#define MT9M114_SYS_STATE_SUSPENDED 0x41 +#define MT9M114_SYS_STATE_ENTER_STANDBY 0x50 +#define MT9M114_SYS_STATE_STANDBY 0x52 +#define MT9M114_SYS_STATE_LEAVE_STANDBY 0x54 + +/*! @brief MT9M114 system set-state command retults. */ +#define MT9M114_SYS_STATE_SET_RESULT_ENOERR 0x00 /* command successful */ +#define MT9M114_SYS_STATE_SET_RESULTEINVAL 0x0C /* invalid configuration */ +#define MT9M114_SYS_STATE_SET_RESULTENOSPC 0x0D /* resource not available */ + +#define MT9M114_OUTPUT_FORMAT_SWAP_RB (1 << 0) +#define MT9M114_OUTPUT_FORMAT_SWAP_BYTES (1 << 1) +#define MT9M114_OUTPUT_FORMAT_MONO (1 << 2) +#define MT9M114_OUTPUT_FORMAT_BT656 (1 << 3) +#define MT9M114_OUTPUT_FORMAT_BT656_FIXED (1 << 4) +#define MT9M114_OUTPUT_FORMAT_YUV (0 << 8) +#define MT9M114_OUTPUT_FORMAT_RGB (1 << 8) +#define MT9M114_OUTPUT_FORMAT_BAYER (2 << 8) +#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10 (0 << 10) +#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10_PRE (1 << 10) +#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10_POST (2 << 10) +#define MT9M114_OUTPUT_FORMAT_PROCESSED_BAYER (3 << 10) +#define MT9M114_OUTPUT_FORMAT_RGB565 (0 << 12) +#define MT9M114_OUTPUT_FORMAT_RGB555 (1 << 12) +#define MT9M114_OUTPUT_FORMAT_XRGB444 (2 << 12) +#define MT9M114_OUTPUT_FORMAT_RGB444X (3 << 12) + +#define MT9M114_SENSOR_CONTROL_READ_MODE_HMIRROR (0x1) +#define MT9M114_SENSOR_CONTROL_READ_MODE_VFLIP (0x2) +#define MT9M114_SENSOR_CONTROL_READ_MODE_HBIN_MASK (0x30) +#define MT9M114_SENSOR_CONTROL_READ_MODE_HBIN (0x30) +#define MT9M114_SENSOR_CONTROL_READ_MODE_VBIN_MASK (0x300) +#define MT9M114_SENSOR_CONTROL_READ_MODE_VBIN (0x300) + +#ifdef __cplusplus +extern "C" { +#endif +typedef struct { + uint16_t reg; /* 16bit reg address */ + uint8_t size; /* reg size in byte */ + uint32_t value; /* reg value */ +} mt9m114_reg_t; + +/*! + * @brief MT9M114 read register. + * + * @param[in] context camera_operate_context. + * @param[in] reg reg address(16 bits) + * @param[in] reg_size reg size in bytes + * @param[out] value reg data from device + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_read_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, void *value); + +/*! + * @brief MT9M114 write register. + * + * @param[in] context camera_operate_context. + * @param[in] reg reg address(16 bits) + * @param[in] reg_size reg size in bytes + * @param[in] value reg data to device + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_write_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, uint32_t value); + +/*! + * @brief MT9M114 modify register. + * + * @param[in] context camera_operate_context. + * @param[in] reg reg address(16 bits) + * @param[in] reg_size reg size in bytes + * @param[in] mask bits can be modified + * @param[in] value value should be set + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_modify_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, uint32_t mask, uint32_t value); + +/*! + * @brief MT9M114 multiwrite registers. + * + * @param[in] context camera_operate_context. + * @param[in] regs pointer to array of mt9m114_reg_t, include reg addr, reg size and value + * @param[in] num array size of [regs] + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_multiwrite(camera_context_t *context, const mt9m114_reg_t regs[], uint32_t num); + +/*! + * @brief MT9M114 check chipid. + * + * @param[in] context camera_operate_context. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_check_chip_id(camera_context_t *context); + +/*! + * @brief MT9M114 set next state and switch to it. + * + * @param[in] context camera_operate_context. + * @param[in] next_state next device state. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_setstate(camera_context_t *context, uint16_t next_state); + +/*! + * @brief MT9M114 get current state. + * + * @param[in] context camera_operate_context. + * @param[out] state current device state. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_get_current_state(camera_context_t *context, uint8_t *state); + +/*! + * @brief MT9M114 soft reset. + * + * @param[in] context camera_operate_context. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_software_reset(camera_context_t *context); + +/*! + * @brief MT9M114 set pixformat. + * + * @param[in] context camera_operate_context. + * @param[in] pixformat pixformat. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_set_pixformat(camera_context_t *context, display_pixel_format_t pixformat); + +/*! + * @brief MT9M114 set framerate. + * + * @param[in] context camera_operate_context. + * @param[in] framerate framerate. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_set_framerate(camera_context_t *context, int framerate); + +/*! + * @brief MT9M114 set brightness. + * + * @param[in] context camera_operate_context. + * @param[in] level brightness. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_set_brightness(camera_context_t *context, int level); + +/*! + * @brief MT9M114 start to transfer image data. + * + * @param[in] context camera_operate_context. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_start(camera_context_t *context); + +/*! + * @brief MT9M114 stop working and enter SUSPEND mode. + * + * @param[in] context camera_operate_context. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_stop(camera_context_t *context); + +/*! + * @brief MT9M114 enable or disable MONO mode. + * + * @param[in] context camera_operate_context. + * @param[in] enable enable or disable mono. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_enable_mono(camera_context_t *context, bool enable); + +/*! + * @brief MT9M114 initialization. + * + * @param[in] context camera_operate_context. + * + * @retval status_success if success. + * @retval status_fail if fail. + */ +hpm_stat_t mt9m114_init(camera_context_t *context, camera_config_t *camera_config); +#ifdef __cplusplus +} +#endif + +/** + * @} + * + */ + +#endif /* HPM_MT9M114_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c b/common/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c index 2a525d76..5832531c 100644 --- a/common/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c +++ b/common/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c @@ -7,6 +7,11 @@ #include "hpm_ov5640.h" +static camera_param_dvp_t camera_dvp_param = { + .hsync_active_low = true, + .vsync_active_low = false, +}; + hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config) { assert(camera_context->delay_ms != NULL); @@ -30,3 +35,8 @@ hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t return stat; } +hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config) +{ + camera_config->interface_param = (void *)&camera_dvp_param; + return status_success; +} diff --git a/common/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c b/common/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c index 85694709..30c195c2 100644 --- a/common/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c +++ b/common/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c @@ -472,7 +472,12 @@ hpm_stat_t ov5640_read_register(camera_context_t *context, uint16_t reg, uint8_t uint8_t r[2]; r[0] = reg >> 8; r[1] = reg & 0xFF; - return i2c_master_address_read(context->ptr, OV5640_I2C_ADDR, r, sizeof(r), buf, 1); + + hpm_stat_t stat = i2c_master_write(context->ptr, context->i2c_device_addr, r, 2); + if (stat != status_success) { + return stat; + } + return i2c_master_read(context->ptr, context->i2c_device_addr, buf, 1); } hpm_stat_t ov5640_write_register(camera_context_t *context, uint16_t reg, uint8_t val) @@ -480,7 +485,7 @@ hpm_stat_t ov5640_write_register(camera_context_t *context, uint16_t reg, uint8_ uint8_t r[2]; r[0] = reg >> 8; r[1] = reg & 0xFF; - return i2c_master_address_write(context->ptr, OV5640_I2C_ADDR, r, sizeof(r), &val, 1); + return i2c_master_address_write(context->ptr, context->i2c_device_addr, r, sizeof(r), &val, 1); } hpm_stat_t ov5640_write_multi_registers(camera_context_t *context, const ov5640_reg_val_t regval[], uint32_t len) diff --git a/common/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c b/common/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c index 122fc743..f140ad2c 100644 --- a/common/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c +++ b/common/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c @@ -7,6 +7,11 @@ #include "hpm_ov7725.h" +static camera_param_dvp_t camera_dvp_param = { + .hsync_active_low = true, + .vsync_active_low = false, +}; + hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config) { assert(camera_context->delay_ms != NULL); @@ -30,3 +35,8 @@ hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t return stat; } +hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config) +{ + camera_config->interface_param = (void *)&camera_dvp_param; + return status_success; +} diff --git a/common/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c b/common/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c index 7a7463ee..675fab0a 100644 --- a/common/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c +++ b/common/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c @@ -184,12 +184,17 @@ static const uint8_t ov7725_default_yuv_regs[][2] = { hpm_stat_t ov7725_read_register(camera_context_t *context, uint8_t reg, uint8_t *buf) { - return i2c_master_address_read(context->ptr, OV7725_I2C_ADDR, ®, 1, buf, 1); + hpm_stat_t stat = i2c_master_write(context->ptr, context->i2c_device_addr, ®, 1); + if (stat != status_success) { + return stat; + } + return i2c_master_read(context->ptr, context->i2c_device_addr, buf, 1); + } hpm_stat_t ov7725_write_register(camera_context_t *context, uint8_t reg, uint8_t val) { - return i2c_master_address_write(context->ptr, OV7725_I2C_ADDR, ®, 1, &val, 1); + return i2c_master_address_write(context->ptr, context->i2c_device_addr, ®, 1, &val, 1); } hpm_stat_t ov7725_load_settings(camera_context_t *context, uint8_t *reg_values, uint32_t count) @@ -279,6 +284,10 @@ hpm_stat_t ov7725_set_pixel_format(camera_context_t *context, display_pixel_form case display_pixel_format_y8: val |= COM7_FMT_YUV; break; + case display_pixel_format_raw8: + stat |= ov7725_write_register(context, DSP_CTRL4, DSP_CTRL4_RAW8); + val |= COM7_FMT_R_BAYER; + break; default: stat = status_invalid_argument; break; diff --git a/common/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c b/common/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c index e90e1bcf..1c855b5a 100644 --- a/common/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c +++ b/common/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c @@ -52,9 +52,9 @@ hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config) HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL1, 0xC0)); HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL4, 0x40)); - /* ADC volume, 0dB */ - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, 0x1C3)); - HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, 0x1C3)); + /* ADC volume, 8dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, 0x1D3)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, 0x1D3)); /* Digital DAC volume, 0dB */ HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, 0x1E0)); diff --git a/common/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c b/common/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c index 5b63b139..cf9b6065 100644 --- a/common/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c +++ b/common/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c @@ -15,7 +15,7 @@ hpm_stat_t console_init(console_config_t *cfg) { hpm_stat_t stat = status_fail; - if (cfg->type == console_type_uart) { + if (cfg->type == CONSOLE_TYPE_UART) { uart_config_t config = {0}; uart_default_config((UART_Type *)cfg->base, &config); config.src_freq_in_hz = cfg->src_freq_in_hz; diff --git a/common/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h b/common/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h index 8e9a7861..936627fc 100644 --- a/common/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h +++ b/common/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h @@ -10,12 +10,10 @@ #include #include "hpm_common.h" -typedef enum console_type { - console_type_uart = 0, -} console_type_t; +#define CONSOLE_TYPE_UART 0 typedef struct { - console_type_t type; + uint32_t type; uint32_t base; uint32_t src_freq_in_hz; uint32_t baudrate; diff --git a/common/libraries/hpm_sdk/components/enet_phy/CMakeLists.txt b/common/libraries/hpm_sdk/components/enet_phy/CMakeLists.txt new file mode 100644 index 00000000..a5489131 --- /dev/null +++ b/common/libraries/hpm_sdk/components/enet_phy/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2022 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +sdk_inc(.) + +add_subdirectory_ifdef(CONFIG_ENET_PHY_RTL8211 rtl8211) +add_subdirectory_ifdef(CONFIG_ENET_PHY_RTL8201 rtl8201) +add_subdirectory_ifdef(CONFIG_ENET_PHY_DP83867 dp83867) +add_subdirectory_ifdef(CONFIG_ENET_PHY_DP83848 dp83848) \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/enet_phy/dp83848/CMakeLists.txt b/common/libraries/hpm_sdk/components/enet_phy/dp83848/CMakeLists.txt index 952dc8b2..baf6ffba 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/dp83848/CMakeLists.txt +++ b/common/libraries/hpm_sdk/components/enet_phy/dp83848/CMakeLists.txt @@ -1,5 +1,9 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause +sdk_compile_definitions(-DRGMII=0) +sdk_compile_definitions(-D__USE_DP83848=1) + sdk_inc(.) +sdk_inc(../) sdk_src(hpm_dp83848.c) diff --git a/common/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c b/common/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c index 5805e3d5..0a09b889 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c +++ b/common/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c @@ -1,69 +1,69 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_enet_drv.h" #include "hpm_dp83848_regs.h" #include "hpm_dp83848.h" -#include "board.h" - -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Internal API - *---------------------------------------------------------------------*/ -static bool dp83848_id_check(ENET_Type *ptr) + *--------------------------------------------------------------------- + */ +static bool dp83848_check_id(ENET_Type *ptr) { uint16_t id1, id2; - id1 = enet_read_phy(ptr, PHY_ADDR, DP83848_REG_PHYID1); - id2 = enet_read_phy(ptr, PHY_ADDR, DP83848_REG_PHYID2); + id1 = enet_read_phy(ptr, PHY_ADDR, DP83848_PHYIDR1); + id2 = enet_read_phy(ptr, PHY_ADDR, DP83848_PHYIDR2); - if (DP83848_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && DP83848_PHYID2_OUI_MSB_GET(id2) == PHY_ID2) { + if (DP83848_PHYIDR1_OUI_MSB_GET(id1) == PHY_ID1 && DP83848_PHYIDR2_OUI_LSB_GET(id2) == PHY_ID2) { return true; } else { return false; } } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * API - *---------------------------------------------------------------------*/ -uint16_t dp83848_register_check(ENET_Type *ptr, uint32_t addr) -{ - return enet_read_phy(ptr, PHY_ADDR, addr); -} - + *--------------------------------------------------------------------- + */ void dp83848_reset(ENET_Type *ptr) { uint16_t data; /* PHY reset */ - enet_write_phy(ptr, PHY_ADDR, DP83848_REG_BMCR, DP83848_BMCR_RESET_SET(1)); + enet_write_phy(ptr, PHY_ADDR, DP83848_BMCR, DP83848_BMCR_RESET_SET(1)); /* wait until the reset is completed */ do { - data = enet_read_phy(ptr, PHY_ADDR, DP83848_REG_BMCR); + data = enet_read_phy(ptr, PHY_ADDR, DP83848_BMCR); } while (DP83848_BMCR_RESET_GET(data)); } void dp83848_basic_mode_default_config(ENET_Type *ptr, dp83848_config_t *config) { - config->loopback = 1; /* Enable PCS loopback mode */ - config->speed = 2; /* reserved:3/2; 100mbps: 1; 10mbps: 0 */ - config->auto_negotiation = 1; /* Enable Auto-Negotiation */ - config->duplex_mode = 1; /* Full duplex mode */ + config->loopback = false; /* Disable PCS loopback mode */ + #if __DISABLE_AUTO_NEGO + config->auto_negotiation = false; /* Disable Auto-Negotiation */ + config->speed = enet_phy_port_speed_100mbps; + config->duplex = enet_phy_duplex_full; + #else + config->auto_negotiation = true; /* Enable Auto-Negotiation */ + #endif } bool dp83848_basic_mode_init(ENET_Type *ptr, dp83848_config_t *config) { - uint16_t para = 0; + uint16_t data = 0; - para |= DP83848_BMCR_RESET_SET(0) /* Normal operation */ + data |= DP83848_BMCR_RESET_SET(0) /* Normal operation */ | DP83848_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ | DP83848_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ | DP83848_BMCR_PWD_SET(0) /* Normal operation */ @@ -71,22 +71,27 @@ bool dp83848_basic_mode_init(ENET_Type *ptr, dp83848_config_t *config) | DP83848_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ | DP83848_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ - if (config->auto_negotiation == 0) { - para |= DP83848_BMCR_SPEED0_SET(config->speed) | DP83848_BMCR_SPEED1_SET(config->speed >> 1); + if (config->auto_negotiation == false) { + data |= DP83848_BMCR_SPEED0_SET(config->speed); /* Set port speed */ + data |= DP83848_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ } /* check the id of dp83848 */ - if (dp83848_id_check(ptr) == false) { + if (dp83848_check_id(ptr) == false) { return false; } - para = enet_read_phy(ptr, PHY_ADDR, DP83848_REG_BMCR) & ~ DP83848_BMCR_SPEED0_MASK; - enet_write_phy(ptr, PHY_ADDR, DP83848_REG_BMCR, para); + enet_write_phy(ptr, PHY_ADDR, DP83848_BMCR, data); return true; } - -void dp83848_init_auto_negotiation(void) +void dp83848_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) { + uint16_t data; + + data = enet_read_phy(ptr, PHY_ADDR, DP83848_PHYSTS); + status->enet_phy_link = DP83848_PHYSTS_LINK_STATUS_GET(data); + status->enet_phy_speed = DP83848_PHYSTS_SPEED_STATUS_GET(data) ? enet_phy_port_speed_10mbps : enet_phy_port_speed_100mbps; + status->enet_phy_duplex = DP83848_PHYSTS_DUPLEX_STATUS_GET(data); } diff --git a/common/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h b/common/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h index e19f70b1..ec933d78 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h +++ b/common/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,44 +8,45 @@ #ifndef HPM_DP83848_H #define HPM_DP83848_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ -#include "stdint.h" - -/*---------------------------------------------------------------------* + *--------------------------------------------------------------------- + */ +#include "hpm_enet_phy.h" +#include "hpm_common.h" +#include "hpm_enet_regs.h" +/*--------------------------------------------------------------------- * Macro Const Definitions - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #define PHY_ADDR (1U) #define PHY_ID1 (0x2000U) #define PHY_ID2 (0x17U) -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Typedef Struct Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ typedef struct { bool loopback; uint8_t speed; bool auto_negotiation; - uint8_t duplex_mode; + uint8_t duplex; } dp83848_config_t; #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Exported Functions - *---------------------------------------------------------------------*/ -uint16_t dp83848_check(ENET_Type *ptr, uint32_t addr); + *--------------------------------------------------------------------- + */ void dp83848_reset(ENET_Type *ptr); void dp83848_basic_mode_default_config(ENET_Type *ptr, dp83848_config_t *config); bool dp83848_basic_mode_init(ENET_Type *ptr, dp83848_config_t *config); -void dp83848_read_status(ENET_Type *ptr); -void dp83848_control_config(ENET_Type *ptr); -void dp83867_ctl_config(ENET_Type *ptr); -void dp83867_bist_config(ENET_Type *ptr); +void dp83848_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); #if defined(__cplusplus) } #endif /* __cplusplus */ -#endif /* HPM_DP83848_H */ \ No newline at end of file +#endif /* HPM_DP83848_H */ diff --git a/common/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h b/common/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h index b8483f63..9c96c235 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h +++ b/common/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h @@ -1,212 +1,1524 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -#ifndef HPM_RTL83848_REGS_H -#define HPM_RTL83848_REGS_H - - /* RTL Register Definitions */ -#define DP83848_REG_BMCR (0U) /* Basic Mode Control Register */ -#define DP83848_REG_BMSR (1U) /* Basic Mode Status Register */ -#define DP83848_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ -#define DP83848_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ -#define DP83848_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ -#define DP83848_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ -#define DP83848_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ -#define DP83848_REG_ANNPTR (7U) /* Auto-Negotiation Next Page Transmit Register */ -#define DP83848_REG_ANNPRR (8U) /* Auto-Negotiation Next Page Receive Register */ -#define DP83848_REG_GBCR (9U) /* 1000Base-T Control Register */ -#define DP83848_REG_GBSR (10U) /* 1000Base-T Status Register */ - -#define DP83848_REG_MACR (13U) /* MMD Access Control Register */ -#define DP83848_REG_MAADR (14U) /* MMD Access Address Data Register */ -#define DP83848_REG_GBESR (15U) /* 1000Base-T Extended Status Register */ -#define DP83848_REG_PHYCR (16U) /* PHY Specific Control Register */ -#define DP83848_REG_PHYSR (17U) /* PHY Specific Status Register */ -#define DP83848_REG_INER (18U) /* Interrupt Enable Register */ -#define DP83848_REG_INSR (19U) /* Interrupt Status Register */ -#define DP83848_REG_RXERC (24U) /* Receive Error Counter */ -#define DP83848_REG_PAGSEL (31U) /* Page Select Register */ - -/* RTL MMD Register Definitions */ -#define DP83848_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ -#define DP83848_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ -#define DP83848_MMD_REG_EEECR (20U) /* EEE Capability Register */ -#define DP83848_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ -#define DP83848_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ -#define DP83848_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ - -#define DP83867_REGCR_FUNCTION_ADDR (0 << 14) -#define DP83867_REGCR_FUNCTION_DATA (1 << 14) -#define DP83867_REGCR_DEVAD (0x1f) + +#ifndef HPM_DP83848_REGS_H +#define HPM_DP83848_REGS_H + +typedef enum { + DP83848_BMCR = 0, /* 0x0: Basic Mode Control Register */ + DP83848_BMSR = 1, /* 0x1: Basic Mode Status Register */ + DP83848_PHYIDR1 = 2, /* 0x2: PHY Identifier Register #1 */ + DP83848_PHYIDR2 = 3, /* 0x3: PHY Identifier Register #2 */ + DP83848_ANAR = 4, /* 0x4: Auto-Negotiation Advertisement Register */ + DP83848_ANLPAR_BP = 5, /* 0x5: Auto-Negotiation Link Partner Ability Register */ + DP83848_ANER = 6, /* 0x6: Auto-Negotiate Expansion Register */ + DP83848_ANNPTR = 7, /* 0x7: Auto-Negotiation Next Page Transmit Register */ + DP83848_PHYSTS = 16, /* 0x10: PHY Status Register */ + DP83848_FCSCR = 20, /* 0x14: False Carrier Sense Counter Register */ + DP83848_RECR = 21, /* 0x15: Receiver Error Counter Register */ + DP83848_PCSR = 22, /* 0x16: 100 Mb/s PCS Configuration and Status Register */ + DP83848_RBR = 23, /* 0x17: RMII and Bypass Register */ + DP83848_LEDCR = 24, /* 0x18: LED Direct Control Register */ + DP83848_PHYCR = 25, /* 0x19: PHY Control Register */ + DP83848_10BTSCR = 26, /* 0x1A: 10BASE-T Status/Control Register */ + DP83848_CDCTRL1 = 27, /* 0x1B: CD Test and BIST Extensions Register */ + DP83848_EDCR = 29, /* 0x1D: Energy Detect Control */ +} DP83848_REG_Type; + /* Bitfield definition for register: BMCR */ /* - * Reset (RW) + * RESET (RW/SC) * - * 1: PHY reset - * 0: Normal operation - * Register 0 (BMCR) and register 1 (BMSR) will return to default - * values after a software reset (set Bit15 to 1). - * This action may change the internal PHY state and the state of the - * physical link associated with the PHY. + * Reset: + * 1 = Initiate software Reset / Reset in Process. + * 0 = Normal operation. + * This bit, which is self-clearing, returns a value of one until the reset process is complete. The + * configuration is re-strapped. */ -#define DP83848_BMCR_RESET_MASK (0x8000U) +#define DP83848_BMCR_RESET_MASK (0x8000U) #define DP83848_BMCR_RESET_SHIFT (15U) -#define DP83848_BMCR_RESET_SET(x) (((uint32_t)(x) << DP83848_BMCR_RESET_SHIFT) & DP83848_BMCR_RESET_MASK) -#define DP83848_BMCR_RESET_GET(x) (((uint32_t)(x) & DP83848_BMCR_RESET_MASK) >> DP83848_BMCR_RESET_SHIFT) +#define DP83848_BMCR_RESET_SET(x) (((uint16_t)(x) << DP83848_BMCR_RESET_SHIFT) & DP83848_BMCR_RESET_MASK) +#define DP83848_BMCR_RESET_GET(x) (((uint16_t)(x) & DP83848_BMCR_RESET_MASK) >> DP83848_BMCR_RESET_SHIFT) /* - * Loopback (RW) + * LOOPBACK (RW) * - * Loopback Mode. - * 1: Enable PCS loopback mode - * 0: Disable PCS loopback mode + * Loopback: + * 1 = Loopback enabled. + * 0 = Normal operation. + * The loopback function enables MII transmit data to be routed to the MII receive data path. + * Setting this bit may cause the descrambler to lose synchronization and produce a 500 µs “dead + * time” before any valid data will appear at the MII receive outputs. */ -#define DP83848_BMCR_LOOPBACK_MASK (0x4000U) +#define DP83848_BMCR_LOOPBACK_MASK (0x4000U) #define DP83848_BMCR_LOOPBACK_SHIFT (14U) -#define DP83848_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << DP83848_BMCR_LOOPBACK_SHIFT) & DP83848_BMCR_LOOPBACK_MASK) -#define DP83848_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & DP83848_BMCR_LOOPBACK_MASK) >> DP83848_BMCR_LOOPBACK_SHIFT) +#define DP83848_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << DP83848_BMCR_LOOPBACK_SHIFT) & DP83848_BMCR_LOOPBACK_MASK) +#define DP83848_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & DP83848_BMCR_LOOPBACK_MASK) >> DP83848_BMCR_LOOPBACK_SHIFT) /* - * Speed[0] (RW) + * SPEED0 (RW) * - * Speed Select Bit 0. - * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 - * determine device speed selection. + * Speed Select: + * When auto-negotiation is disabled writing to this bit allows the port speed to be selected. + * 1 = 100 Mb/s. + * 0 = 10 Mb/s. */ -#define DP83848_BMCR_SPEED0_MASK (0x2000U) +#define DP83848_BMCR_SPEED0_MASK (0x2000U) #define DP83848_BMCR_SPEED0_SHIFT (13U) -#define DP83848_BMCR_SPEED0_SET(x) (((uint32_t)(x) << DP83848_BMCR_SPEED0_SHIFT) & DP83848_BMCR_SPEED0_MASK) -#define DP83848_BMCR_SPEED0_GET(x) (((uint32_t)(x) & DP83848_BMCR_SPEED0_MASK) >> DP83848_BMCR_SPEED0_SHIFT) +#define DP83848_BMCR_SPEED0_SET(x) (((uint16_t)(x) << DP83848_BMCR_SPEED0_SHIFT) & DP83848_BMCR_SPEED0_MASK) +#define DP83848_BMCR_SPEED0_GET(x) (((uint16_t)(x) & DP83848_BMCR_SPEED0_MASK) >> DP83848_BMCR_SPEED0_SHIFT) /* * ANE (RW) * - * Auto-Negotiation Enable. - * 1: Enable Auto-Negotiation - * 0: Disable Auto-Negotiation + * Auto-Negotiation Enable: + * Strap controls initial value at reset. + * 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set. + * 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode. */ -#define DP83848_BMCR_ANE_MASK (0x1000U) +#define DP83848_BMCR_ANE_MASK (0x1000U) #define DP83848_BMCR_ANE_SHIFT (12U) -#define DP83848_BMCR_ANE_SET(x) (((uint32_t)(x) << DP83848_BMCR_ANE_SHIFT) & DP83848_BMCR_ANE_MASK) -#define DP83848_BMCR_ANE_GET(x) (((uint32_t)(x) & DP83848_BMCR_ANE_MASK) >> DP83848_BMCR_ANE_SHIFT) +#define DP83848_BMCR_ANE_SET(x) (((uint16_t)(x) << DP83848_BMCR_ANE_SHIFT) & DP83848_BMCR_ANE_MASK) +#define DP83848_BMCR_ANE_GET(x) (((uint16_t)(x) & DP83848_BMCR_ANE_MASK) >> DP83848_BMCR_ANE_SHIFT) /* * PWD (RW) * - * Power Down. - * 1: Power down (only Management Interface and logic are active; link - * is down) - * 0: Normal operation + * Power Down: + * 1 = Power down. + * 0 = Normal operation. + * Setting this bit powers down the PHY. Only the register block is enabled during a power-down + * condition. */ -#define DP83848_BMCR_PWD_MASK (0x0800U) +#define DP83848_BMCR_PWD_MASK (0x800U) #define DP83848_BMCR_PWD_SHIFT (11U) -#define DP83848_BMCR_PWD_SET(x) (((uint32_t)(x) << DP83848_BMCR_PWD_SHIFT) & DP83848_BMCR_PWD_MASK) -#define DP83848_BMCR_PWD_GET(x) (((uint32_t)(x) & DP83848_BMCR_PWD_MASK) >> DP83848_BMCR_PWD_SHIFT) +#define DP83848_BMCR_PWD_SET(x) (((uint16_t)(x) << DP83848_BMCR_PWD_SHIFT) & DP83848_BMCR_PWD_MASK) +#define DP83848_BMCR_PWD_GET(x) (((uint16_t)(x) & DP83848_BMCR_PWD_MASK) >> DP83848_BMCR_PWD_SHIFT) /* - * Isolate (RW) + * ISOLATE (RW) * - * Isolate. - * 1: RGMII/GMII interface is isolated; the serial management interface - * (MDC, MDIO) is still active. When this bit is asserted, the - * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and - * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. - * 0: Normal operation + * Isolate: + * 1 = Isolates the Port from the MII with the exception of the serial management. + * 0 = Normal operation. */ -#define DP83848_BMCR_ISOLATE_MASK (0x0400U) +#define DP83848_BMCR_ISOLATE_MASK (0x400U) #define DP83848_BMCR_ISOLATE_SHIFT (10U) -#define DP83848_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << DP83848_BMCR_ISOLATE_SHIFT) & DP83848_BMCR_ISOLATE_MASK) -#define DP83848_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & DP83848_BMCR_ISOLATE_MASK) >> DP83848_BMCR_ISOLATE_SHIFT) +#define DP83848_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << DP83848_BMCR_ISOLATE_SHIFT) & DP83848_BMCR_ISOLATE_MASK) +#define DP83848_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & DP83848_BMCR_ISOLATE_MASK) >> DP83848_BMCR_ISOLATE_SHIFT) /* - * Restart_AN (RW) + * RESTART_AN (RW/SC) * - * Restart Auto-Negotiation. - * 1: Restart Auto-Negotiation - * 0: Normal operation + * Restart Auto-Negotiation: + * 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-Negotiation is + * disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until + * Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation + * process is not affected by the management entity clearing this bit. + * 0 = Normal operation. */ -#define DP83848_BMCR_RESTART_AN_MASK (0x0200U) +#define DP83848_BMCR_RESTART_AN_MASK (0x200U) #define DP83848_BMCR_RESTART_AN_SHIFT (9U) -#define DP83848_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << DP83848_BMCR_RESTART_AN_SHIFT) & DP83848_BMCR_RESTART_AN_MASK) -#define DP83848_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & DP83848_BMCR_RESTART_AN_MASK) >> DP83848_BMCR_RESTART_AN_SHIFT) +#define DP83848_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << DP83848_BMCR_RESTART_AN_SHIFT) & DP83848_BMCR_RESTART_AN_MASK) +#define DP83848_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & DP83848_BMCR_RESTART_AN_MASK) >> DP83848_BMCR_RESTART_AN_SHIFT) /* - * Duplex (RW) + * DUPLEX (RW) * - * Duplex Mode. - * 1: Full Duplex operation - * 0: Half Duplex operation - * This bit is valid only in force mode, i.e., NWay is disabled. + * Duplex Mode: + * When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be + * selected. + * 1 = Full Duplex operation. + * 0 = Half Duplex operation. */ -#define DP83848_BMCR_DUPLEX_MASK (0x0100U) +#define DP83848_BMCR_DUPLEX_MASK (0x100U) #define DP83848_BMCR_DUPLEX_SHIFT (8U) -#define DP83848_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << DP83848_BMCR_DUPLEX_SHIFT) & DP83848_BMCR_DUPLEX_MASK) -#define DP83848_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & DP83848_BMCR_DUPLEX_MASK) >> DP83848_BMCR_DUPLEX_SHIFT) +#define DP83848_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << DP83848_BMCR_DUPLEX_SHIFT) & DP83848_BMCR_DUPLEX_MASK) +#define DP83848_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMCR_DUPLEX_MASK) >> DP83848_BMCR_DUPLEX_SHIFT) /* - * Collision Test (RW) + * COLLISION_TEST (RW) * - * Collision Test. - * 1: Collision test enabled - * 0: Normal operation - * When set, this bit will cause the COL signal to be asserted in response - * to the assertion of TXEN within 512-bit times. The COL signal will be - * de-asserted within 4-bit times in response to the de-assertion of - * TXEN. + * Collision Test: + * 1 = Collision test enabled. + * 0 = Normal operation. + * When set, this bit will cause the COL signal to be asserted in response to the assertion of + * TX_EN within 512-bit times. The COL signal will be deasserted within 4-bit times in response to + * the deassertion of TX_EN. */ -#define DP83848_BMCR_COLLISION_TEST_MASK (0x0080U) +#define DP83848_BMCR_COLLISION_TEST_MASK (0x80U) #define DP83848_BMCR_COLLISION_TEST_SHIFT (7U) -#define DP83848_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << DP83848_BMCR_COLLISION_TEST_SHIFT) & DP83848_BMCR_COLLISION_TEST_MASK) -#define DP83848_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & DP83848_BMCR_COLLISION_TEST_MASK) >> DP83848_BMCR_COLLISION_TEST_SHIFT) +#define DP83848_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << DP83848_BMCR_COLLISION_TEST_SHIFT) & DP83848_BMCR_COLLISION_TEST_MASK) +#define DP83848_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & DP83848_BMCR_COLLISION_TEST_MASK) >> DP83848_BMCR_COLLISION_TEST_SHIFT) + +/* Bitfield definition for register: BMSR */ +/* + * 100BASE_TX_FULL_DUPLEX (RO) + * + * 100BASE-TX Full Duplex Capable: + * 1 = Device able to perform 100BASE-TX in full duplex mode. + */ +#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK (0x4000U) +#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT (14U) +#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK) >> DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT) + +/* + * 100BASE_TX_HALF (RO) + * + * 100BASE-TX Half Duplex Capable: + * 1 = Device able to perform 100BASE-TX in half duplex mode. + */ +#define DP83848_BMSR_100BASE_TX_HALF_MASK (0x2000U) +#define DP83848_BMSR_100BASE_TX_HALF_SHIFT (13U) +#define DP83848_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & DP83848_BMSR_100BASE_TX_HALF_MASK) >> DP83848_BMSR_100BASE_TX_HALF_SHIFT) + +/* + * 10BASE_T_FULL_DUPLEX (RO) + * + * 10BASE-T Full Duplex Capable: + * 1 = Device able to perform 10BASE-T in full duplex mode. + */ +#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK (0x1000U) +#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT (12U) +#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK) >> DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT) + +/* + * 10BASE_T_HALF_DUPLEX (RO) + * + * 10BASE-T Half Duplex Capable: + * 1 = Device able to perform 10BASE-T in half duplex mode. + */ +#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK (0x800U) +#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT (11U) +#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK) >> DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT) + +/* + * MF_PREAMBLE_SUPPRESSION (RO) + * + * Preamble suppression Capable: + * 1 = Device able to perform management transaction with preamble suppressed, 32-bits of + * preamble needed only once after reset, invalid opcode or invalid turnaround. + * 0 = Normal management operation. + */ +#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK (0x40U) +#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT (6U) +#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK) >> DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT) + +/* + * AUTO_NEGOTIATION_COMPLETE (RO) + * + * Auto-Negotiation Complete: + * 1 = Auto-Negotiation process complete. + * 0 = Auto-Negotiation process not complete. + */ +#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) +#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) +#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) /* - * Speed[1] (RW) + * REMOTE_FAULT (RO) * - * Speed Select Bit 1. - * Refer to bit 0.13. + * Remote Fault: + * 1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Notification from + * Link Partner of Remote Fault. + * 0 = No remote fault condition detected. */ -#define DP83848_BMCR_SPEED1_MASK (0x0040U) -#define DP83848_BMCR_SPEED1_SHIFT (6U) -#define DP83848_BMCR_SPEED1_SET(x) (((uint32_t)(x) << DP83848_BMCR_SPEED1_SHIFT) & DP83848_BMCR_SPEED1_MASK) -#define DP83848_BMCR_SPEED1_GET(x) (((uint32_t)(x) & DP83848_BMCR_SPEED1_MASK) >> DP83848_BMCR_SPEED1_SHIFT) +#define DP83848_BMSR_REMOTE_FAULT_MASK (0x10U) +#define DP83848_BMSR_REMOTE_FAULT_SHIFT (4U) +#define DP83848_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & DP83848_BMSR_REMOTE_FAULT_MASK) >> DP83848_BMSR_REMOTE_FAULT_SHIFT) -/* Bitfield definition for register: PHYID1 */ +/* + * AUTO_NEGOTIATION_ABILITY (RO) + * + * Auto Negotiation Ability: + * 1 = Device is able to perform Auto-Negotiation. + * 0 = Device is not able to perform Auto-Negotiation. + */ +#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) +#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) +#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) + +/* + * LINK_STATUS (RO) + * + * Link Status: + * 1 = Valid link established (for either 10 or 100 Mb/s operation). + * 0 = Link not established. + * The criteria for link validity is implementation specific. The occurrence of a link failure condition + * will causes the Link Status bit to clear. Once cleared, this bit may only be set by establishing a + * good link condition and a read through the management interface. + */ +#define DP83848_BMSR_LINK_STATUS_MASK (0x4U) +#define DP83848_BMSR_LINK_STATUS_SHIFT (2U) +#define DP83848_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83848_BMSR_LINK_STATUS_MASK) >> DP83848_BMSR_LINK_STATUS_SHIFT) + +/* + * JABBER_DETECT (RO) + * + * Jabber Detect: This bit only has meaning in 10 Mb/s mode. + * 1 = Jabber condition detected. + * 0 = No Jabber. + * This bit is implemented with a latching function, such that the occurrence of a jabber condition + * causes it to set until it is cleared by a read to this register by the management interface or by a + * reset. + */ +#define DP83848_BMSR_JABBER_DETECT_MASK (0x2U) +#define DP83848_BMSR_JABBER_DETECT_SHIFT (1U) +#define DP83848_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83848_BMSR_JABBER_DETECT_MASK) >> DP83848_BMSR_JABBER_DETECT_SHIFT) + +/* + * EXTENDED_CAPABILITY (RO) + * + * Extended Capability: + * 1 = Extended register capabilities. + * 0 = Basic register set capabilities only. + */ +#define DP83848_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) +#define DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) +#define DP83848_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & DP83848_BMSR_EXTENDED_CAPABILITY_MASK) >> DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT) + +/* Bitfield definition for register: PHYIDR1 */ /* * OUI_MSB (RO) * - * Organizationally Unique Identifier Bit 3:18. - * Always 0000000000011100. + * OUI Most Significant Bits: + * Bits 3 to 18 of the OUI (080017h) are stored in bits 15 to 0 of this register. The most + * significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and + * 2). */ -#define DP83848_PHYID1_OUI_MSB_MASK (0xFFFFU) -#define DP83848_PHYID1_OUI_MSB_SHIFT (0U) -#define DP83848_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & DP83848_PHYID1_OUI_MSB_MASK) >> DP83848_PHYID1_OUI_MSB_SHIFT) +#define DP83848_PHYIDR1_OUI_MSB_MASK (0xFFFFU) +#define DP83848_PHYIDR1_OUI_MSB_SHIFT (0U) +#define DP83848_PHYIDR1_OUI_MSB_GET(x) (((uint16_t)(x) & DP83848_PHYIDR1_OUI_MSB_MASK) >> DP83848_PHYIDR1_OUI_MSB_SHIFT) -/* Bitfield definition for register: PHYID2 */ +/* Bitfield definition for register: PHYIDR2 */ /* * OUI_LSB (RO) * - * Organizationally Unique Identifier Bit 19:24. - * Always 110010. + * OUI Least Significant Bits: + * Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of this register + * respectively. + */ +#define DP83848_PHYIDR2_OUI_LSB_MASK (0xFC00U) +#define DP83848_PHYIDR2_OUI_LSB_SHIFT (10U) +#define DP83848_PHYIDR2_OUI_LSB_GET(x) (((uint16_t)(x) & DP83848_PHYIDR2_OUI_LSB_MASK) >> DP83848_PHYIDR2_OUI_LSB_SHIFT) + +/* + * VNDR_MDL (RO) + * + * Vendor Model Number: + * The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit + * 9). + */ +#define DP83848_PHYIDR2_VNDR_MDL_MASK (0x3F0U) +#define DP83848_PHYIDR2_VNDR_MDL_SHIFT (4U) +#define DP83848_PHYIDR2_VNDR_MDL_GET(x) (((uint16_t)(x) & DP83848_PHYIDR2_VNDR_MDL_MASK) >> DP83848_PHYIDR2_VNDR_MDL_SHIFT) + +/* + * MDL_REV (RO) + * + * Model Revision Number: + * Four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant + * bit to bit 3). This field will be incremented for all major device changes. + */ +#define DP83848_PHYIDR2_MDL_REV_MASK (0xFU) +#define DP83848_PHYIDR2_MDL_REV_SHIFT (0U) +#define DP83848_PHYIDR2_MDL_REV_GET(x) (((uint16_t)(x) & DP83848_PHYIDR2_MDL_REV_MASK) >> DP83848_PHYIDR2_MDL_REV_SHIFT) + +/* Bitfield definition for register: ANAR */ +/* + * NP (RW) + * + * Next Page Indication: + * 0 = Next Page Transfer not desired. + * 1 = Next Page Transfer desired. + */ +#define DP83848_ANAR_NP_MASK (0x8000U) +#define DP83848_ANAR_NP_SHIFT (15U) +#define DP83848_ANAR_NP_SET(x) (((uint16_t)(x) << DP83848_ANAR_NP_SHIFT) & DP83848_ANAR_NP_MASK) +#define DP83848_ANAR_NP_GET(x) (((uint16_t)(x) & DP83848_ANAR_NP_MASK) >> DP83848_ANAR_NP_SHIFT) + +/* + * RF (RW) + * + * Remote Fault: + * 1 = Advertises that this device has detected a Remote Fault. + * 0 = No Remote Fault detected. + */ +#define DP83848_ANAR_RF_MASK (0x2000U) +#define DP83848_ANAR_RF_SHIFT (13U) +#define DP83848_ANAR_RF_SET(x) (((uint16_t)(x) << DP83848_ANAR_RF_SHIFT) & DP83848_ANAR_RF_MASK) +#define DP83848_ANAR_RF_GET(x) (((uint16_t)(x) & DP83848_ANAR_RF_MASK) >> DP83848_ANAR_RF_SHIFT) + +/* + * ASM_DIR (RW) + * + * Asymmetric PAUSE Support for Full Duplex Links: + * The ASM_DIR bit indicates that asymmetric PAUSE is supported. + * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and + * 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12]. + * 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer + * and the pause function as specified in clause 31 and annex 31B of 802.3. + * 0= No MAC based full duplex flow control. + */ +#define DP83848_ANAR_ASM_DIR_MASK (0x800U) +#define DP83848_ANAR_ASM_DIR_SHIFT (11U) +#define DP83848_ANAR_ASM_DIR_SET(x) (((uint16_t)(x) << DP83848_ANAR_ASM_DIR_SHIFT) & DP83848_ANAR_ASM_DIR_MASK) +#define DP83848_ANAR_ASM_DIR_GET(x) (((uint16_t)(x) & DP83848_ANAR_ASM_DIR_MASK) >> DP83848_ANAR_ASM_DIR_SHIFT) + +/* + * PAUSE (RW) + * + * PAUSE Support for Full Duplex Links: + * The PAUSE bit indicates that the device is capable of providing the symmetric PAUSE + * functions as defined in Annex 31B. + * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and + * 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12]. + * 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer + * and the pause function as specified in clause 31 and annex 31B of 802.3. + * 0= No MAC based full duplex flow control. + */ +#define DP83848_ANAR_PAUSE_MASK (0x400U) +#define DP83848_ANAR_PAUSE_SHIFT (10U) +#define DP83848_ANAR_PAUSE_SET(x) (((uint16_t)(x) << DP83848_ANAR_PAUSE_SHIFT) & DP83848_ANAR_PAUSE_MASK) +#define DP83848_ANAR_PAUSE_GET(x) (((uint16_t)(x) & DP83848_ANAR_PAUSE_MASK) >> DP83848_ANAR_PAUSE_SHIFT) + +/* + * T4 (RO) + * + * 100BASE-T4 Support: + * 1= 100BASE-T4 is supported by the local device. + * 0 = 100BASE-T4 not supported. + */ +#define DP83848_ANAR_T4_MASK (0x200U) +#define DP83848_ANAR_T4_SHIFT (9U) +#define DP83848_ANAR_T4_GET(x) (((uint16_t)(x) & DP83848_ANAR_T4_MASK) >> DP83848_ANAR_T4_SHIFT) + +/* + * TX_FD (RW) + * + * 100BASE-TX Full Duplex Support: + * 1 = 100BASE-TX Full Duplex is supported by the local device. + * 0 = 100BASE-TX Full Duplex not supported. + */ +#define DP83848_ANAR_TX_FD_MASK (0x100U) +#define DP83848_ANAR_TX_FD_SHIFT (8U) +#define DP83848_ANAR_TX_FD_SET(x) (((uint16_t)(x) << DP83848_ANAR_TX_FD_SHIFT) & DP83848_ANAR_TX_FD_MASK) +#define DP83848_ANAR_TX_FD_GET(x) (((uint16_t)(x) & DP83848_ANAR_TX_FD_MASK) >> DP83848_ANAR_TX_FD_SHIFT) + +/* + * TX (RW) + * + * 100BASE-TX Support: + * 1 = 100BASE-TX is supported by the local device. + * 0 = 100BASE-TX not supported. + */ +#define DP83848_ANAR_TX_MASK (0x80U) +#define DP83848_ANAR_TX_SHIFT (7U) +#define DP83848_ANAR_TX_SET(x) (((uint16_t)(x) << DP83848_ANAR_TX_SHIFT) & DP83848_ANAR_TX_MASK) +#define DP83848_ANAR_TX_GET(x) (((uint16_t)(x) & DP83848_ANAR_TX_MASK) >> DP83848_ANAR_TX_SHIFT) + +/* + * 10_FD (RW) + * + * 10BASE-T Full Duplex Support: + * 1 = 10BASE-T Full Duplex is supported by the local device. + * 0 = 10BASE-T Full Duplex not supported. + */ +#define DP83848_ANAR_10_FD_MASK (0x40U) +#define DP83848_ANAR_10_FD_SHIFT (6U) +#define DP83848_ANAR_10_FD_SET(x) (((uint16_t)(x) << DP83848_ANAR_10_FD_SHIFT) & DP83848_ANAR_10_FD_MASK) +#define DP83848_ANAR_10_FD_GET(x) (((uint16_t)(x) & DP83848_ANAR_10_FD_MASK) >> DP83848_ANAR_10_FD_SHIFT) + +/* + * 10 (RW) + * + * 10BASE-T Support: + * 1 = 10BASE-T is supported by the local device. + * 0 = 10BASE-T not supported. + */ +#define DP83848_ANAR_10_MASK (0x20U) +#define DP83848_ANAR_10_SHIFT (5U) +#define DP83848_ANAR_10_SET(x) (((uint16_t)(x) << DP83848_ANAR_10_SHIFT) & DP83848_ANAR_10_MASK) +#define DP83848_ANAR_10_GET(x) (((uint16_t)(x) & DP83848_ANAR_10_MASK) >> DP83848_ANAR_10_SHIFT) + +/* + * SELECTOR (RW) + * + * Protocol Selection Bits: + * These bits contain the binary encoded protocol selector supported by this port. <00001> + * indicates that this device supports IEEE 802.3. + */ +#define DP83848_ANAR_SELECTOR_MASK (0x1FU) +#define DP83848_ANAR_SELECTOR_SHIFT (0U) +#define DP83848_ANAR_SELECTOR_SET(x) (((uint16_t)(x) << DP83848_ANAR_SELECTOR_SHIFT) & DP83848_ANAR_SELECTOR_MASK) +#define DP83848_ANAR_SELECTOR_GET(x) (((uint16_t)(x) & DP83848_ANAR_SELECTOR_MASK) >> DP83848_ANAR_SELECTOR_SHIFT) + +/* Bitfield definition for register: ANLPAR_BP */ +/* + * NP (RO) + * + * Next Page Indication: + * 0 = Link Partner does not desire Next Page Transfer. + * 1 = Link Partner desires Next Page Transfer. + */ +#define DP83848_ANLPAR_BP_NP_MASK (0x8000U) +#define DP83848_ANLPAR_BP_NP_SHIFT (15U) +#define DP83848_ANLPAR_BP_NP_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_NP_MASK) >> DP83848_ANLPAR_BP_NP_SHIFT) + +/* + * ACK (RO) + * + * Acknowledge: + * 1 = Link Partner acknowledges reception of the ability data word. + * 0 = Not acknowledged. + * The Auto-Negotiation state machine will automatically control the this bit based on the incoming + * FLP bursts. + */ +#define DP83848_ANLPAR_BP_ACK_MASK (0x4000U) +#define DP83848_ANLPAR_BP_ACK_SHIFT (14U) +#define DP83848_ANLPAR_BP_ACK_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_ACK_MASK) >> DP83848_ANLPAR_BP_ACK_SHIFT) + +/* + * RF (RO) + * + * Remote Fault: + * 1 = Remote Fault indicated by Link Partner. + * 0 = No Remote Fault indicated by Link Partner. + */ +#define DP83848_ANLPAR_BP_RF_MASK (0x2000U) +#define DP83848_ANLPAR_BP_RF_SHIFT (13U) +#define DP83848_ANLPAR_BP_RF_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_RF_MASK) >> DP83848_ANLPAR_BP_RF_SHIFT) + +/* + * ASM_DIR (RO) + * + * ASYMMETRIC PAUSE: + * 1 = Asymmetric pause is supported by the Link Partner. + * 0 = Asymmetric pause is not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_ASM_DIR_MASK (0x800U) +#define DP83848_ANLPAR_BP_ASM_DIR_SHIFT (11U) +#define DP83848_ANLPAR_BP_ASM_DIR_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_ASM_DIR_MASK) >> DP83848_ANLPAR_BP_ASM_DIR_SHIFT) + +/* + * PAUSE (RO) + * + * PAUSE: + * 1 = Pause function is supported by the Link Partner. + * 0 = Pause function is not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_PAUSE_MASK (0x400U) +#define DP83848_ANLPAR_BP_PAUSE_SHIFT (10U) +#define DP83848_ANLPAR_BP_PAUSE_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_PAUSE_MASK) >> DP83848_ANLPAR_BP_PAUSE_SHIFT) + +/* + * T4 (RO) + * + * 100BASE-T4 Support: + * 1 = 100BASE-T4 is supported by the Link Partner. + * 0 = 100BASE-T4 not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_T4_MASK (0x200U) +#define DP83848_ANLPAR_BP_T4_SHIFT (9U) +#define DP83848_ANLPAR_BP_T4_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_T4_MASK) >> DP83848_ANLPAR_BP_T4_SHIFT) + +/* + * TX_FD (RO) + * + * 100BASE-TX Full Duplex Support: + * 1 = 100BASE-TX Full Duplex is supported by the Link Partner. + * 0 = 100BASE-TX Full Duplex not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_TX_FD_MASK (0x100U) +#define DP83848_ANLPAR_BP_TX_FD_SHIFT (8U) +#define DP83848_ANLPAR_BP_TX_FD_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_TX_FD_MASK) >> DP83848_ANLPAR_BP_TX_FD_SHIFT) + +/* + * TX (RO) + * + * 100BASE-TX Support: + * 1 = 100BASE-TX is supported by the Link Partner. + * 0 = 100BASE-TX not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_TX_MASK (0x80U) +#define DP83848_ANLPAR_BP_TX_SHIFT (7U) +#define DP83848_ANLPAR_BP_TX_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_TX_MASK) >> DP83848_ANLPAR_BP_TX_SHIFT) + +/* + * 10_FD (RO) + * + * 10BASE-T Full Duplex Support: + * 1 = 10BASE-T Full Duplex is supported by the Link Partner. + * 0 = 10BASE-T Full Duplex not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_10_FD_MASK (0x40U) +#define DP83848_ANLPAR_BP_10_FD_SHIFT (6U) +#define DP83848_ANLPAR_BP_10_FD_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_10_FD_MASK) >> DP83848_ANLPAR_BP_10_FD_SHIFT) + +/* + * 10 (RO) + * + * 10BASE-T Support: + * 1 = 10BASE-T is supported by the Link Partner. + * 0 = 10BASE-T not supported by the Link Partner. + */ +#define DP83848_ANLPAR_BP_10_MASK (0x20U) +#define DP83848_ANLPAR_BP_10_SHIFT (5U) +#define DP83848_ANLPAR_BP_10_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_10_MASK) >> DP83848_ANLPAR_BP_10_SHIFT) + +/* + * SELECTOR (RO) + * + * Protocol Selection Bits: + * Link Partner’s binary encoded protocol selector. + */ +#define DP83848_ANLPAR_BP_SELECTOR_MASK (0x1FU) +#define DP83848_ANLPAR_BP_SELECTOR_SHIFT (0U) +#define DP83848_ANLPAR_BP_SELECTOR_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_SELECTOR_MASK) >> DP83848_ANLPAR_BP_SELECTOR_SHIFT) + +/* Bitfield definition for register: ANER */ +/* + * PDF (RO) + * + * Parallel Detection Fault: + * 1 = A fault has been detected through the Parallel Detection function. + * 0 = A fault has not been detected. + */ +#define DP83848_ANER_PDF_MASK (0x10U) +#define DP83848_ANER_PDF_SHIFT (4U) +#define DP83848_ANER_PDF_GET(x) (((uint16_t)(x) & DP83848_ANER_PDF_MASK) >> DP83848_ANER_PDF_SHIFT) + +/* + * LP_NP_ABLE (RO) + * + * Link Partner Next Page Able: + * 1 = Link Partner does support Next Page. + * 0 = Link Partner does not support Next Page. + */ +#define DP83848_ANER_LP_NP_ABLE_MASK (0x8U) +#define DP83848_ANER_LP_NP_ABLE_SHIFT (3U) +#define DP83848_ANER_LP_NP_ABLE_GET(x) (((uint16_t)(x) & DP83848_ANER_LP_NP_ABLE_MASK) >> DP83848_ANER_LP_NP_ABLE_SHIFT) + +/* + * NP_ABLE (RO) + * + * Next Page Able: + * 1 = Indicates local device is able to send additional “Next Pages”. + */ +#define DP83848_ANER_NP_ABLE_MASK (0x4U) +#define DP83848_ANER_NP_ABLE_SHIFT (2U) +#define DP83848_ANER_NP_ABLE_GET(x) (((uint16_t)(x) & DP83848_ANER_NP_ABLE_MASK) >> DP83848_ANER_NP_ABLE_SHIFT) + +/* + * PAGE_RX (RO) + * + * Link Code Word Page Received: + * 1 = Link Code Word has been received, cleared on a read. + * 0 = Link Code Word has not been received. + */ +#define DP83848_ANER_PAGE_RX_MASK (0x2U) +#define DP83848_ANER_PAGE_RX_SHIFT (1U) +#define DP83848_ANER_PAGE_RX_GET(x) (((uint16_t)(x) & DP83848_ANER_PAGE_RX_MASK) >> DP83848_ANER_PAGE_RX_SHIFT) + +/* + * LP_AN_ABLE (RO) + * + * Link Partner Auto-Negotiation Able: + * 1 = indicates that the Link Partner supports Auto-Negotiation. + * 0 = indicates that the Link Partner does not support Auto-Negotiation. + */ +#define DP83848_ANER_LP_AN_ABLE_MASK (0x1U) +#define DP83848_ANER_LP_AN_ABLE_SHIFT (0U) +#define DP83848_ANER_LP_AN_ABLE_GET(x) (((uint16_t)(x) & DP83848_ANER_LP_AN_ABLE_MASK) >> DP83848_ANER_LP_AN_ABLE_SHIFT) + +/* Bitfield definition for register: ANNPTR */ +/* + * NP (RW) + * + * Next Page Indication: + * 0 = No other Next Page Transfer desired. + * 1 = Another Next Page desired. + */ +#define DP83848_ANNPTR_NP_MASK (0x8000U) +#define DP83848_ANNPTR_NP_SHIFT (15U) +#define DP83848_ANNPTR_NP_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_NP_SHIFT) & DP83848_ANNPTR_NP_MASK) +#define DP83848_ANNPTR_NP_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_NP_MASK) >> DP83848_ANNPTR_NP_SHIFT) + +/* + * MP (RW) + * + * Message Page: + * 1 = Message Page. + * 0 = Unformatted Page. + */ +#define DP83848_ANNPTR_MP_MASK (0x2000U) +#define DP83848_ANNPTR_MP_SHIFT (13U) +#define DP83848_ANNPTR_MP_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_MP_SHIFT) & DP83848_ANNPTR_MP_MASK) +#define DP83848_ANNPTR_MP_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_MP_MASK) >> DP83848_ANNPTR_MP_SHIFT) + +/* + * ACK2 (RW) + * + * Acknowledge2: + * 1 = Will comply with message. + * 0 = Cannot comply with message. + * Acknowledge2 is used by the next page function to indicate that Local Device has the ability + * to comply with the message received. + */ +#define DP83848_ANNPTR_ACK2_MASK (0x1000U) +#define DP83848_ANNPTR_ACK2_SHIFT (12U) +#define DP83848_ANNPTR_ACK2_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_ACK2_SHIFT) & DP83848_ANNPTR_ACK2_MASK) +#define DP83848_ANNPTR_ACK2_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_ACK2_MASK) >> DP83848_ANNPTR_ACK2_SHIFT) + +/* + * TOG_TX (RW) + * + * Toggle: + * 1 = Value of toggle bit in previously transmitted Link Code Word was 0. + * 0 = Value of toggle bit in previously transmitted Link Code Word was 1. + * Toggle is used by the Arbitration function within Auto-Negotiation to ensure synchronization + * with the Link Partner during Next Page exchange. This bit shall always take the opposite + * value of the Toggle bit in the previously exchanged Link Code Word. + */ +#define DP83848_ANNPTR_TOG_TX_MASK (0x800U) +#define DP83848_ANNPTR_TOG_TX_SHIFT (11U) +#define DP83848_ANNPTR_TOG_TX_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_TOG_TX_SHIFT) & DP83848_ANNPTR_TOG_TX_MASK) +#define DP83848_ANNPTR_TOG_TX_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_TOG_TX_MASK) >> DP83848_ANNPTR_TOG_TX_SHIFT) + +/* + * CODE (RW) + * + * This field represents the code field of the next page transmission. If the MP bit is set (bit 13 + * of this register), then the code shall be interpreted as a "Message Page”, as defined in annex + * 28C of IEEE 802.3. Otherwise, the code shall be interpreted as an "Unformatted Page”, and + * the interpretation is application specific. + * The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE + * 802.3. + */ +#define DP83848_ANNPTR_CODE_MASK (0x400U) +#define DP83848_ANNPTR_CODE_SHIFT (10U) +#define DP83848_ANNPTR_CODE_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_CODE_SHIFT) & DP83848_ANNPTR_CODE_MASK) +#define DP83848_ANNPTR_CODE_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_CODE_MASK) >> DP83848_ANNPTR_CODE_SHIFT) + +/* Bitfield definition for register: PHYSTS */ +/* + * MDI_X_MODE (RO) + * + * MDI-X mode as reported by the Auto-Negotiation logic: + * This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the + * PHYCR register. When MDIX is enabled, but not forced, this bit will update dynamically as + * the Auto-MDIX algorithm swaps between MDI and MDI-X configurations. + * 1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair) + * 0 = MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair) + */ +#define DP83848_PHYSTS_MDI_X_MODE_MASK (0x4000U) +#define DP83848_PHYSTS_MDI_X_MODE_SHIFT (14U) +#define DP83848_PHYSTS_MDI_X_MODE_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_MDI_X_MODE_MASK) >> DP83848_PHYSTS_MDI_X_MODE_SHIFT) + +/* + * RECEIVE_ERRORLATCH (RO) + * + * Receive Error Latch: + * This bit will be cleared upon a read of the RECR register. + * 1 = Receive error event has occurred since last read of RXERCNT (address 0x15, Page 0). + * 0 = No receive error event has occurred. + */ +#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK (0x2000U) +#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT (13U) +#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK) >> DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT) + +/* + * POLARITY_STATUS (RO) + * + * Polarity Status: + * This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared upon a read + * of the 10BTSCR register, but not upon a read of the PHYSTS register. + * 1 = Inverted Polarity detected. + * 0 = Correct Polarity detected. + */ +#define DP83848_PHYSTS_POLARITY_STATUS_MASK (0x1000U) +#define DP83848_PHYSTS_POLARITY_STATUS_SHIFT (12U) +#define DP83848_PHYSTS_POLARITY_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_POLARITY_STATUS_MASK) >> DP83848_PHYSTS_POLARITY_STATUS_SHIFT) + +/* + * FALSE_CARRIER_SENSE_LATCH (RO) + * + * False Carrier Sense Latch: + * This bit will be cleared upon a read of the FCSR register. + * 1 = False Carrier event has occurred since last read of FCSCR (address 0x14). + * 0 = No False Carrier event has occurred. + */ +#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK (0x800U) +#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT (11U) +#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK) >> DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT) + +/* + * SIGNAL_DETECT (RO) + * + * 100Base-TX unconditional Signal Detect from PMD. + */ +#define DP83848_PHYSTS_SIGNAL_DETECT_MASK (0x400U) +#define DP83848_PHYSTS_SIGNAL_DETECT_SHIFT (10U) +#define DP83848_PHYSTS_SIGNAL_DETECT_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_SIGNAL_DETECT_MASK) >> DP83848_PHYSTS_SIGNAL_DETECT_SHIFT) + +/* + * DESCRAMBLER_LOCK (RO) + * + * 100Base-TX Descrambler Lock from PMD. + */ +#define DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK (0x200U) +#define DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT (9U) +#define DP83848_PHYSTS_DESCRAMBLER_LOCK_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK) >> DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT) + +/* + * PAGE_RECEIVED (RO) + * + * Link Code Word Page Received: + * This is a duplicate of the Page Received bit in the ANER register, but this bit will not be + * cleared upon a read of the PHYSTS register. + * 1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address + * 0x06, bit 1). + * 0 = Link Code Word Page has not been received. */ -#define DP83848_PHYID2_OUI_MSB_MASK (0xFC00U) -#define DP83848_PHYID2_OUI_MSB_SHIFT (10U) -#define DP83848_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & DP83848_PHYID2_OUI_MSB_MASK) >> DP83848_PHYID2_OUI_MSB_SHIFT) +#define DP83848_PHYSTS_PAGE_RECEIVED_MASK (0x100U) +#define DP83848_PHYSTS_PAGE_RECEIVED_SHIFT (8U) +#define DP83848_PHYSTS_PAGE_RECEIVED_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_PAGE_RECEIVED_MASK) >> DP83848_PHYSTS_PAGE_RECEIVED_SHIFT) -/* Bitfield definition for register: RGMIICTL */ /* - * RGMII_EN (RW) + * REMOTE_FAULT (RO) * - * RGMII Enable: - * 1 = Enable RGMII interface. - * 0 = Disable RGMII interface + * Remote Fault: + * 1 = Remote Fault condition detected (cleared on read of BMSR (address 01h) register or by + * reset). Fault criteria: notification from Link Partner of Remote Fault through Auto-Negotiation. + * 0 = No remote fault condition detected. */ -#define DP83867_RGMIICTL_RGMII_EN_MASK (0x80) -#define DP83867_RGMIICTL_RGMII_EN_SHIFT (7U) -#define DP83867_RGMIICTL_RGMII_EN_SET(x) (((uint32_t)(x) << DP83867_RGMIICTL_RGMII_EN_SHIFT) & DP83867_RGMIICTL_RGMII_EN_MASK) -#define DP83867_RGMIICTL_RGMII_EN_GET(x) (((uint32_t)(x) & DP83867_RGMIICTL_RGMII_EN_SHIFT) >> DP83867_RGMIICTL_RGMII_EN_MASK) +#define DP83848_PHYSTS_REMOTE_FAULT_MASK (0x40U) +#define DP83848_PHYSTS_REMOTE_FAULT_SHIFT (6U) +#define DP83848_PHYSTS_REMOTE_FAULT_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_REMOTE_FAULT_MASK) >> DP83848_PHYSTS_REMOTE_FAULT_SHIFT) + +/* + * JABBER_DETECT (RO) + * + * Jabber Detect: This bit only has meaning in 10 Mb/s mode + * This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not + * cleared upon a read of the PHYSTS register. + * 1 = Jabber condition detected. + * 0 = No Jabber. + */ +#define DP83848_PHYSTS_JABBER_DETECT_MASK (0x20U) +#define DP83848_PHYSTS_JABBER_DETECT_SHIFT (5U) +#define DP83848_PHYSTS_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_JABBER_DETECT_MASK) >> DP83848_PHYSTS_JABBER_DETECT_SHIFT) + +/* + * AUTO_NEG_COMPLETE (RO) + * + * Auto-Negotiation Complete: + * 1 = Auto-Negotiation complete. + * 0 = Auto-Negotiation not complete. + */ +#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK (0x10U) +#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT (4U) +#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK) >> DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT) + +/* + * LOOPBACK_STATUS (RO) + * + * Loopback: + * 1 = Loopback enabled. + * 0 = Normal operation. + */ +#define DP83848_PHYSTS_LOOPBACK_STATUS_MASK (0x8U) +#define DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT (3U) +#define DP83848_PHYSTS_LOOPBACK_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_LOOPBACK_STATUS_MASK) >> DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT) + +/* + * DUPLEX_STATUS (RO) + * + * Duplex: + * This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes. + * 1 = Full duplex mode. + * 0 = Half duplex mode. + * Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid + * link or if Auto-Negotiation is disabled and there is a valid link. + */ +#define DP83848_PHYSTS_DUPLEX_STATUS_MASK (0x4U) +#define DP83848_PHYSTS_DUPLEX_STATUS_SHIFT (2U) +#define DP83848_PHYSTS_DUPLEX_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_DUPLEX_STATUS_MASK) >> DP83848_PHYSTS_DUPLEX_STATUS_SHIFT) + +/* + * SPEED_STATUS (RO) + * + * Speed10: + * This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced + * Modes. + * 1 = 10 Mb/s mode. + * 0 = 100 Mb/s mode. + * Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid + * link or if Auto-Negotiation is disabled and there is a valid link. + */ +#define DP83848_PHYSTS_SPEED_STATUS_MASK (0x2U) +#define DP83848_PHYSTS_SPEED_STATUS_SHIFT (1U) +#define DP83848_PHYSTS_SPEED_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_SPEED_STATUS_MASK) >> DP83848_PHYSTS_SPEED_STATUS_SHIFT) + +/* + * LINK_STATUS (RO) + * + * Link Status: + * This bit is a duplicate of the Link Status bit in the BMSR register, except that it will not be + * cleared upon a read of the PHYSTS register. + * 1 = Valid link established (for either 10 or 100 Mb/s operation) + * 0 = Link not established. + */ +#define DP83848_PHYSTS_LINK_STATUS_MASK (0x1U) +#define DP83848_PHYSTS_LINK_STATUS_SHIFT (0U) +#define DP83848_PHYSTS_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_LINK_STATUS_MASK) >> DP83848_PHYSTS_LINK_STATUS_SHIFT) + +/* Bitfield definition for register: FCSCR */ +/* + * FCSCNT_7_0 (RO) + * + * False Carrier Event Counter: + * This 8-bit counter increments on every false carrier event. This counter sticks when it + * reaches its max count (FFh). + */ +#define DP83848_FCSCR_FCSCNT_7_0_MASK (0xFFU) +#define DP83848_FCSCR_FCSCNT_7_0_SHIFT (0U) +#define DP83848_FCSCR_FCSCNT_7_0_GET(x) (((uint16_t)(x) & DP83848_FCSCR_FCSCNT_7_0_MASK) >> DP83848_FCSCR_FCSCNT_7_0_SHIFT) + +/* Bitfield definition for register: RECR */ +/* + * RXERCNT_7_0 (RO) + * + * RX_ER Counter: + * When a valid carrier is present and there is at least one occurrence of an invalid data + * symbol, this 8-bit counter increments for each receive error detected. This event can + * increment only once per valid carrier event. If a collision is present, the attribute will not + * increment. The counter sticks when it reaches its max count. + */ +#define DP83848_RECR_RXERCNT_7_0_MASK (0xFFU) +#define DP83848_RECR_RXERCNT_7_0_SHIFT (0U) +#define DP83848_RECR_RXERCNT_7_0_GET(x) (((uint16_t)(x) & DP83848_RECR_RXERCNT_7_0_MASK) >> DP83848_RECR_RXERCNT_7_0_SHIFT) + +/* Bitfield definition for register: PCSR */ +/* + * TQ_EN (RW) + * + * 100Mbs True Quiet Mode Enable: + * 1 = Transmit True Quiet Mode. + * 0 = Normal Transmit Mode. + */ +#define DP83848_PCSR_TQ_EN_MASK (0x400U) +#define DP83848_PCSR_TQ_EN_SHIFT (10U) +#define DP83848_PCSR_TQ_EN_SET(x) (((uint16_t)(x) << DP83848_PCSR_TQ_EN_SHIFT) & DP83848_PCSR_TQ_EN_MASK) +#define DP83848_PCSR_TQ_EN_GET(x) (((uint16_t)(x) & DP83848_PCSR_TQ_EN_MASK) >> DP83848_PCSR_TQ_EN_SHIFT) + +/* + * SD_FORCE_PMA (RW) + * + * Signal Detect Force PMA: + * 1 = Forces Signal Detection in PMA. + * 0 = Normal SD operation. + */ +#define DP83848_PCSR_SD_FORCE_PMA_MASK (0x200U) +#define DP83848_PCSR_SD_FORCE_PMA_SHIFT (9U) +#define DP83848_PCSR_SD_FORCE_PMA_SET(x) (((uint16_t)(x) << DP83848_PCSR_SD_FORCE_PMA_SHIFT) & DP83848_PCSR_SD_FORCE_PMA_MASK) +#define DP83848_PCSR_SD_FORCE_PMA_GET(x) (((uint16_t)(x) & DP83848_PCSR_SD_FORCE_PMA_MASK) >> DP83848_PCSR_SD_FORCE_PMA_SHIFT) + +/* + * SD_OPTION (RW) + * + * Signal Detect Option: + * 1 = Enhanced signal detect algorithm. + * 0 = Reduced signal detect algorithm. + */ +#define DP83848_PCSR_SD_OPTION_MASK (0x100U) +#define DP83848_PCSR_SD_OPTION_SHIFT (8U) +#define DP83848_PCSR_SD_OPTION_SET(x) (((uint16_t)(x) << DP83848_PCSR_SD_OPTION_SHIFT) & DP83848_PCSR_SD_OPTION_MASK) +#define DP83848_PCSR_SD_OPTION_GET(x) (((uint16_t)(x) & DP83848_PCSR_SD_OPTION_MASK) >> DP83848_PCSR_SD_OPTION_SHIFT) + +/* + * DESC_TIME (RW) + * + * Descrambler Timeout: + * Increase the descrambler timeout. When set this should allow the device to receive larger + * packets (>9k bytes) without loss of synchronization. + * 1 = 2ms + * 0 = 722us (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e) + */ +#define DP83848_PCSR_DESC_TIME_MASK (0x80U) +#define DP83848_PCSR_DESC_TIME_SHIFT (7U) +#define DP83848_PCSR_DESC_TIME_SET(x) (((uint16_t)(x) << DP83848_PCSR_DESC_TIME_SHIFT) & DP83848_PCSR_DESC_TIME_MASK) +#define DP83848_PCSR_DESC_TIME_GET(x) (((uint16_t)(x) & DP83848_PCSR_DESC_TIME_MASK) >> DP83848_PCSR_DESC_TIME_SHIFT) + +/* + * FORCE_100_OK (RW) + * + * Force 100Mb/s Good Link: + * 1 = Forces 100Mb/s Good Link. + * 0 = Normal 100Mb/s operation. + */ +#define DP83848_PCSR_FORCE_100_OK_MASK (0x20U) +#define DP83848_PCSR_FORCE_100_OK_SHIFT (5U) +#define DP83848_PCSR_FORCE_100_OK_SET(x) (((uint16_t)(x) << DP83848_PCSR_FORCE_100_OK_SHIFT) & DP83848_PCSR_FORCE_100_OK_MASK) +#define DP83848_PCSR_FORCE_100_OK_GET(x) (((uint16_t)(x) & DP83848_PCSR_FORCE_100_OK_MASK) >> DP83848_PCSR_FORCE_100_OK_SHIFT) + +/* + * NRZI_BYPASS (RW) + * + * NRZI Bypass Enable: + * 1 = NRZI Bypass Enabled. + * 0 = NRZI Bypass Disabled. + */ +#define DP83848_PCSR_NRZI_BYPASS_MASK (0x4U) +#define DP83848_PCSR_NRZI_BYPASS_SHIFT (2U) +#define DP83848_PCSR_NRZI_BYPASS_SET(x) (((uint16_t)(x) << DP83848_PCSR_NRZI_BYPASS_SHIFT) & DP83848_PCSR_NRZI_BYPASS_MASK) +#define DP83848_PCSR_NRZI_BYPASS_GET(x) (((uint16_t)(x) & DP83848_PCSR_NRZI_BYPASS_MASK) >> DP83848_PCSR_NRZI_BYPASS_SHIFT) + +/* Bitfield definition for register: RBR */ +/* + * RMII_MODE (RW) + * + * Reduced MII Mode: + * 0 = Standard MII Mode + * 1 = Reduced MII Mode + */ +#define DP83848_RBR_RMII_MODE_MASK (0x20U) +#define DP83848_RBR_RMII_MODE_SHIFT (5U) +#define DP83848_RBR_RMII_MODE_SET(x) (((uint16_t)(x) << DP83848_RBR_RMII_MODE_SHIFT) & DP83848_RBR_RMII_MODE_MASK) +#define DP83848_RBR_RMII_MODE_GET(x) (((uint16_t)(x) & DP83848_RBR_RMII_MODE_MASK) >> DP83848_RBR_RMII_MODE_SHIFT) + +/* + * RMII_REV1_0 (RW) + * + * Reduce MII Revision 1.0: + * 0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate deassertion of + * CRS. + * 1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred. CRS_DV + * will not toggle at the end of a packet. + */ +#define DP83848_RBR_RMII_REV1_0_MASK (0x10U) +#define DP83848_RBR_RMII_REV1_0_SHIFT (4U) +#define DP83848_RBR_RMII_REV1_0_SET(x) (((uint16_t)(x) << DP83848_RBR_RMII_REV1_0_SHIFT) & DP83848_RBR_RMII_REV1_0_MASK) +#define DP83848_RBR_RMII_REV1_0_GET(x) (((uint16_t)(x) & DP83848_RBR_RMII_REV1_0_MASK) >> DP83848_RBR_RMII_REV1_0_SHIFT) + +/* + * RX_OVF_STS (RO) + * + * RX FIFO Over Flow Status: + * 0 = Normal + * 1 = Overflow detected + */ +#define DP83848_RBR_RX_OVF_STS_MASK (0x8U) +#define DP83848_RBR_RX_OVF_STS_SHIFT (3U) +#define DP83848_RBR_RX_OVF_STS_GET(x) (((uint16_t)(x) & DP83848_RBR_RX_OVF_STS_MASK) >> DP83848_RBR_RX_OVF_STS_SHIFT) + +/* + * RX_UNF_STS (RO) + * + * RX FIFO Under Flow Status: + * 0 = Normal + * 1 = Underflow detected + */ +#define DP83848_RBR_RX_UNF_STS_MASK (0x4U) +#define DP83848_RBR_RX_UNF_STS_SHIFT (2U) +#define DP83848_RBR_RX_UNF_STS_GET(x) (((uint16_t)(x) & DP83848_RBR_RX_UNF_STS_MASK) >> DP83848_RBR_RX_UNF_STS_SHIFT) + +/* + * ELAST_BUF_1_0 (RW) + * + * Receive Elasticity Buffer. This field controls the Receive Elasticity Buffer which allows for + * frequency variation tolerance between the 50-MHz RMII clock and the recovered data. The + * following value indicate the tolerance in bits for a single packet. The minimum setting allows + * for standard Ethernet frame sizes at ±50 ppm accuracy for both RMII and Receive clocks. For + * greater frequency tolerance the packet lengths may be scaled (that is, for ±100 ppm, the + * packet lengths need to be divided by 2). + * 00 = 14 bit tolerance (up to 16800 byte packets) + * 01 = 2 bit tolerance (up to 2400 byte packets) + * 10 = 6 bit tolerance (up to 7200 byte packets) + * 11 = 10 bit tolerance (up to 12000 byte packets) + */ +#define DP83848_RBR_ELAST_BUF_1_0_MASK (0x3U) +#define DP83848_RBR_ELAST_BUF_1_0_SHIFT (0U) +#define DP83848_RBR_ELAST_BUF_1_0_SET(x) (((uint16_t)(x) << DP83848_RBR_ELAST_BUF_1_0_SHIFT) & DP83848_RBR_ELAST_BUF_1_0_MASK) +#define DP83848_RBR_ELAST_BUF_1_0_GET(x) (((uint16_t)(x) & DP83848_RBR_ELAST_BUF_1_0_MASK) >> DP83848_RBR_ELAST_BUF_1_0_SHIFT) + +/* Bitfield definition for register: LEDCR */ +/* + * DRV_SPDLED (RW) + * + * 1 = Drive value of SPDLED bit onto LED_SPEED output + * 0 = Normal operation + */ +#define DP83848_LEDCR_DRV_SPDLED_MASK (0x20U) +#define DP83848_LEDCR_DRV_SPDLED_SHIFT (5U) +#define DP83848_LEDCR_DRV_SPDLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_DRV_SPDLED_SHIFT) & DP83848_LEDCR_DRV_SPDLED_MASK) +#define DP83848_LEDCR_DRV_SPDLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_DRV_SPDLED_MASK) >> DP83848_LEDCR_DRV_SPDLED_SHIFT) + +/* + * DRV_LNKLED (RW) + * + * 1 = Drive value of LNKLED bit onto LED_LINK output + * 0 = Normal operation + */ +#define DP83848_LEDCR_DRV_LNKLED_MASK (0x10U) +#define DP83848_LEDCR_DRV_LNKLED_SHIFT (4U) +#define DP83848_LEDCR_DRV_LNKLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_DRV_LNKLED_SHIFT) & DP83848_LEDCR_DRV_LNKLED_MASK) +#define DP83848_LEDCR_DRV_LNKLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_DRV_LNKLED_MASK) >> DP83848_LEDCR_DRV_LNKLED_SHIFT) + +/* + * SPDLED (RW) + * + * Value to force on LED_SPEED output + */ +#define DP83848_LEDCR_SPDLED_MASK (0x4U) +#define DP83848_LEDCR_SPDLED_SHIFT (2U) +#define DP83848_LEDCR_SPDLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_SPDLED_SHIFT) & DP83848_LEDCR_SPDLED_MASK) +#define DP83848_LEDCR_SPDLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_SPDLED_MASK) >> DP83848_LEDCR_SPDLED_SHIFT) + +/* + * LNKLED (RW) + * + * Value to force on LED_LINK output + */ +#define DP83848_LEDCR_LNKLED_MASK (0x2U) +#define DP83848_LEDCR_LNKLED_SHIFT (1U) +#define DP83848_LEDCR_LNKLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_LNKLED_SHIFT) & DP83848_LEDCR_LNKLED_MASK) +#define DP83848_LEDCR_LNKLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_LNKLED_MASK) >> DP83848_LEDCR_LNKLED_SHIFT) + +/* Bitfield definition for register: PHYCR */ +/* + * MDIX_EN (RW) + * + * Auto-MDIX Enable: + * 1 = Enable Auto-neg Auto-MDIX capability. + * 0 = Disable Auto-neg Auto-MDIX capability. + * The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the BMCR register + * to be set. If Auto-Negotiation is not enabled, Auto-MDIX should be disabled as well. + */ +#define DP83848_PHYCR_MDIX_EN_MASK (0x8000U) +#define DP83848_PHYCR_MDIX_EN_SHIFT (15U) +#define DP83848_PHYCR_MDIX_EN_SET(x) (((uint16_t)(x) << DP83848_PHYCR_MDIX_EN_SHIFT) & DP83848_PHYCR_MDIX_EN_MASK) +#define DP83848_PHYCR_MDIX_EN_GET(x) (((uint16_t)(x) & DP83848_PHYCR_MDIX_EN_MASK) >> DP83848_PHYCR_MDIX_EN_SHIFT) + +/* + * FORCE_MDIX (RW) + * + * Force MDIX: + * 1 = Force MDI pairs to cross. (Receive on TPTD pair, Transmit on TPRD pair) + * 0 = Normal operation. + */ +#define DP83848_PHYCR_FORCE_MDIX_MASK (0x4000U) +#define DP83848_PHYCR_FORCE_MDIX_SHIFT (14U) +#define DP83848_PHYCR_FORCE_MDIX_SET(x) (((uint16_t)(x) << DP83848_PHYCR_FORCE_MDIX_SHIFT) & DP83848_PHYCR_FORCE_MDIX_MASK) +#define DP83848_PHYCR_FORCE_MDIX_GET(x) (((uint16_t)(x) & DP83848_PHYCR_FORCE_MDIX_MASK) >> DP83848_PHYCR_FORCE_MDIX_SHIFT) + +/* + * PAUSE_RX (RO) + * + * Pause Receive Negotiated: + * Indicates that pause receive should be enabled in the MAC. Based on ANAR[11:10] and + * ANLPAR[11:10] settings. + * This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause + * Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex + * technology. + */ +#define DP83848_PHYCR_PAUSE_RX_MASK (0x2000U) +#define DP83848_PHYCR_PAUSE_RX_SHIFT (13U) +#define DP83848_PHYCR_PAUSE_RX_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PAUSE_RX_MASK) >> DP83848_PHYCR_PAUSE_RX_SHIFT) + +/* + * PAUSE_TX (RO) + * + * Pause Transmit Negotiated: + * Indicates that pause transmit should be enabled in the MAC. Based on ANAR[11:10] and + * ANLPAR[11:10] settings. + * This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause + * Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex + * technology. + */ +#define DP83848_PHYCR_PAUSE_TX_MASK (0x1000U) +#define DP83848_PHYCR_PAUSE_TX_SHIFT (12U) +#define DP83848_PHYCR_PAUSE_TX_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PAUSE_TX_MASK) >> DP83848_PHYCR_PAUSE_TX_SHIFT) + +/* + * BIST_FE (RW) + * + * BIST Force Error: + * 1 = Force BIST Error. + * 0 = Normal operation. + * This bit forces a single error, and is self clearing. + */ +#define DP83848_PHYCR_BIST_FE_MASK (0x800U) +#define DP83848_PHYCR_BIST_FE_SHIFT (11U) +#define DP83848_PHYCR_BIST_FE_SET(x) (((uint16_t)(x) << DP83848_PHYCR_BIST_FE_SHIFT) & DP83848_PHYCR_BIST_FE_MASK) +#define DP83848_PHYCR_BIST_FE_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BIST_FE_MASK) >> DP83848_PHYCR_BIST_FE_SHIFT) + +/* + * PSR_15 (RW) + * + * BIST Sequence select: + * 1 = PSR15 selected. + * 0 = PSR9 selected. + */ +#define DP83848_PHYCR_PSR_15_MASK (0x400U) +#define DP83848_PHYCR_PSR_15_SHIFT (10U) +#define DP83848_PHYCR_PSR_15_SET(x) (((uint16_t)(x) << DP83848_PHYCR_PSR_15_SHIFT) & DP83848_PHYCR_PSR_15_MASK) +#define DP83848_PHYCR_PSR_15_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PSR_15_MASK) >> DP83848_PHYCR_PSR_15_SHIFT) + +/* + * BIST_STATUS (RO) + * + * BIST Test Status: + * 1 = BIST pass. + * 0 = BIST fail. Latched, cleared when BIST is stopped. + * For a count number of BIST errors, see the BIST Error Count in the CDCTRL1 register. + */ +#define DP83848_PHYCR_BIST_STATUS_MASK (0x200U) +#define DP83848_PHYCR_BIST_STATUS_SHIFT (9U) +#define DP83848_PHYCR_BIST_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BIST_STATUS_MASK) >> DP83848_PHYCR_BIST_STATUS_SHIFT) + +/* + * BIST_START (RW) + * + * BIST Start: + * 1 = BIST start. + * 0 = BIST stop. + */ +#define DP83848_PHYCR_BIST_START_MASK (0x100U) +#define DP83848_PHYCR_BIST_START_SHIFT (8U) +#define DP83848_PHYCR_BIST_START_SET(x) (((uint16_t)(x) << DP83848_PHYCR_BIST_START_SHIFT) & DP83848_PHYCR_BIST_START_MASK) +#define DP83848_PHYCR_BIST_START_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BIST_START_MASK) >> DP83848_PHYCR_BIST_START_SHIFT) + +/* + * BP_STRETCH (RW) + * + * Bypass LED Stretching: + * This will bypass the LED stretching and the LEDs will reflect the internal value. + * 1 = Bypass LED stretching. + * 0 = Normal operation. + */ +#define DP83848_PHYCR_BP_STRETCH_MASK (0x80U) +#define DP83848_PHYCR_BP_STRETCH_SHIFT (7U) +#define DP83848_PHYCR_BP_STRETCH_SET(x) (((uint16_t)(x) << DP83848_PHYCR_BP_STRETCH_SHIFT) & DP83848_PHYCR_BP_STRETCH_MASK) +#define DP83848_PHYCR_BP_STRETCH_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BP_STRETCH_MASK) >> DP83848_PHYCR_BP_STRETCH_SHIFT) + +/* + * LED_CNFG_0 (RW) + * + * LED Configuration + * LED_ CNFG[0] Mode Description + * 1 Mode 1 + * 0 Mode2 + * In Mode 1, LEDs are configured as follows: LED_LINK = ON for Good Link, OFF for No Link + * LED_SPEED = ON in 100Mb/s, OFF in 10Mb/s + * In Mode 2, LEDs are configured as follows: LED_LINK = ON for good Link, BLINK for Activity + * LED_SPEED = ON in 100Mb/s, OFF in 10Mb/s + */ +#define DP83848_PHYCR_LED_CNFG_0_MASK (0x20U) +#define DP83848_PHYCR_LED_CNFG_0_SHIFT (5U) +#define DP83848_PHYCR_LED_CNFG_0_SET(x) (((uint16_t)(x) << DP83848_PHYCR_LED_CNFG_0_SHIFT) & DP83848_PHYCR_LED_CNFG_0_MASK) +#define DP83848_PHYCR_LED_CNFG_0_GET(x) (((uint16_t)(x) & DP83848_PHYCR_LED_CNFG_0_MASK) >> DP83848_PHYCR_LED_CNFG_0_SHIFT) + +/* + * PHYADDR_4_0 (RW) + * + * PHY Address: PHY address for port. + */ +#define DP83848_PHYCR_PHYADDR_4_0_MASK (0x1FU) +#define DP83848_PHYCR_PHYADDR_4_0_SHIFT (0U) +#define DP83848_PHYCR_PHYADDR_4_0_SET(x) (((uint16_t)(x) << DP83848_PHYCR_PHYADDR_4_0_SHIFT) & DP83848_PHYCR_PHYADDR_4_0_MASK) +#define DP83848_PHYCR_PHYADDR_4_0_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PHYADDR_4_0_MASK) >> DP83848_PHYCR_PHYADDR_4_0_SHIFT) + +/* Bitfield definition for register: 10BTSCR */ +/* + * SQUELCH (RW) + * + * Squelch Configuration: + * Used to set the Squelch ‘ON’ threshold for the receiver. + * Default Squelch ON is 330-mV peak. + */ +#define DP83848_10BTSCR_SQUELCH_MASK (0xE00U) +#define DP83848_10BTSCR_SQUELCH_SHIFT (9U) +#define DP83848_10BTSCR_SQUELCH_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_SQUELCH_SHIFT) & DP83848_10BTSCR_SQUELCH_MASK) +#define DP83848_10BTSCR_SQUELCH_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_SQUELCH_MASK) >> DP83848_10BTSCR_SQUELCH_SHIFT) + +/* + * LOOPBACK_10_DIS (RW) + * + * In half-duplex mode, default 10BASE-T operation loops Transmit data to the Receive data + * in addition to transmitting the data on the physical medium. This is for consistency with + * earlier 10BASE2 and 10BASE5 implementations which used a shared medium. Setting + * this bit disables the loopback function. + * This bit does not affect loopback due to setting BMCR[14]. + */ +#define DP83848_10BTSCR_LOOPBACK_10_DIS_MASK (0x100U) +#define DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT (8U) +#define DP83848_10BTSCR_LOOPBACK_10_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT) & DP83848_10BTSCR_LOOPBACK_10_DIS_MASK) +#define DP83848_10BTSCR_LOOPBACK_10_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_LOOPBACK_10_DIS_MASK) >> DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT) + +/* + * LP_DIS (RW) + * + * Normal Link Pulse Disable: + * 1 = Transmission of NLPs is disabled. + * 0 = Transmission of NLPs is enabled. + */ +#define DP83848_10BTSCR_LP_DIS_MASK (0x80U) +#define DP83848_10BTSCR_LP_DIS_SHIFT (7U) +#define DP83848_10BTSCR_LP_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_LP_DIS_SHIFT) & DP83848_10BTSCR_LP_DIS_MASK) +#define DP83848_10BTSCR_LP_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_LP_DIS_MASK) >> DP83848_10BTSCR_LP_DIS_SHIFT) + +/* + * FORCE_LINK_10 (RW) + * + * Force 10Mb Good Link: + * 1 = Forced Good 10 Mb Link. + * 0 = Normal Link Status. + */ +#define DP83848_10BTSCR_FORCE_LINK_10_MASK (0x40U) +#define DP83848_10BTSCR_FORCE_LINK_10_SHIFT (6U) +#define DP83848_10BTSCR_FORCE_LINK_10_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_FORCE_LINK_10_SHIFT) & DP83848_10BTSCR_FORCE_LINK_10_MASK) +#define DP83848_10BTSCR_FORCE_LINK_10_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_FORCE_LINK_10_MASK) >> DP83848_10BTSCR_FORCE_LINK_10_SHIFT) + +/* + * POLARITY (RO) + * + * 10Mb Polarity Status: + * This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be cleared upon a + * read of 10BTSCR register, but not upon a read of the PHYSTS register. + * 1 = Inverted Polarity detected. + * 0 = Correct Polarity detected. + */ +#define DP83848_10BTSCR_POLARITY_MASK (0x10U) +#define DP83848_10BTSCR_POLARITY_SHIFT (4U) +#define DP83848_10BTSCR_POLARITY_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_POLARITY_MASK) >> DP83848_10BTSCR_POLARITY_SHIFT) + +/* + * HEARTBEAT_DIS (RW) + * + * Heartbeat Disable: This bit only has influence in half-duplex 10Mb mode. + * 1 = Heartbeat function disabled. + * 0 = Heartbeat function enabled. + * When the device is operating at 100 Mb or configured for full duplex operation, this + * bit will be ignored - the heartbeat function is disabled. + */ +#define DP83848_10BTSCR_HEARTBEAT_DIS_MASK (0x2U) +#define DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT (1U) +#define DP83848_10BTSCR_HEARTBEAT_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT) & DP83848_10BTSCR_HEARTBEAT_DIS_MASK) +#define DP83848_10BTSCR_HEARTBEAT_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_HEARTBEAT_DIS_MASK) >> DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT) + +/* + * JABBER_DIS (RW) + * + * Jabber Disable: + * Applicable only in 10BASE-T. + * 1 = Jabber function disabled. + * 0 = Jabber function enabled. + */ +#define DP83848_10BTSCR_JABBER_DIS_MASK (0x1U) +#define DP83848_10BTSCR_JABBER_DIS_SHIFT (0U) +#define DP83848_10BTSCR_JABBER_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_JABBER_DIS_SHIFT) & DP83848_10BTSCR_JABBER_DIS_MASK) +#define DP83848_10BTSCR_JABBER_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_JABBER_DIS_MASK) >> DP83848_10BTSCR_JABBER_DIS_SHIFT) + +/* Bitfield definition for register: CDCTRL1 */ +/* + * BIST_ERROR_COUNT (RO) + * + * BIST ERROR Counter: + * Counts number of errored data nibbles during Packet BIST. This value will reset when + * Packet BIST is restarted. The counter sticks when it reaches its max count. + */ +#define DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK (0xFF00U) +#define DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT (8U) +#define DP83848_CDCTRL1_BIST_ERROR_COUNT_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK) >> DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT) + +/* + * BIST_CONT_MODE (RW) + * + * Packet BIST Continuous Mode: + * Allows continuous pseudo random data transmission without any break in transmission. This + * can be used for transmit VOD testing. This is used in conjunction with the BIST controls in + * the PHYCR Register (0x19h). For 10 Mb operation, jabber function must be disabled, bit 0 of + * the 10BTSCR (0x1Ah), JABBER_DIS = 1. + */ +#define DP83848_CDCTRL1_BIST_CONT_MODE_MASK (0x20U) +#define DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT (5U) +#define DP83848_CDCTRL1_BIST_CONT_MODE_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT) & DP83848_CDCTRL1_BIST_CONT_MODE_MASK) +#define DP83848_CDCTRL1_BIST_CONT_MODE_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_BIST_CONT_MODE_MASK) >> DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT) + +/* + * CDPATTEN_10 (RW) + * + * CD Pattern Enable for 10Mb: + * 1 = Enabled. + * 0 = Disabled. + */ +#define DP83848_CDCTRL1_CDPATTEN_10_MASK (0x10U) +#define DP83848_CDCTRL1_CDPATTEN_10_SHIFT (4U) +#define DP83848_CDCTRL1_CDPATTEN_10_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_CDPATTEN_10_SHIFT) & DP83848_CDCTRL1_CDPATTEN_10_MASK) +#define DP83848_CDCTRL1_CDPATTEN_10_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_CDPATTEN_10_MASK) >> DP83848_CDCTRL1_CDPATTEN_10_SHIFT) + +/* + * 10MEG_PATT_GAP ( RW) + * + * Defines gap between data or NLP test sequences: + * 1 = 15 µs. + * 0 = 10 µs. + */ +#define DP83848_CDCTRL1_10MEG_PATT_GAP_MASK (0x4U) +#define DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT (2U) +#define DP83848_CDCTRL1_10MEG_PATT_GAP_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT) & DP83848_CDCTRL1_10MEG_PATT_GAP_MASK) +#define DP83848_CDCTRL1_10MEG_PATT_GAP_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_10MEG_PATT_GAP_MASK) >> DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT) + +/* + * CDPATTSEL_1_0 (RW) + * + * CD Pattern Select[1:0]: + * If CDPATTEN_10 = 1: + * 00 = Data, EOP0 sequence + * 01 = Data, EOP1 sequence + * 10 = NLPs + * 11 = Constant Manchester 1 s (10-MHz sine wave) for harmonic distortion testing. + */ +#define DP83848_CDCTRL1_CDPATTSEL_1_0_MASK (0x3U) +#define DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT (0U) +#define DP83848_CDCTRL1_CDPATTSEL_1_0_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT) & DP83848_CDCTRL1_CDPATTSEL_1_0_MASK) +#define DP83848_CDCTRL1_CDPATTSEL_1_0_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_CDPATTSEL_1_0_MASK) >> DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT) + +/* Bitfield definition for register: EDCR */ +/* + * ED_EN (RW) + * + * Energy Detect Enable: + * Allow Energy Detect Mode. + * When Energy Detect is enabled and Auto-Negotiation is disabled through the BMCR + * register, Auto-MDIX should be disabled through the PHYCR register. + */ +#define DP83848_EDCR_ED_EN_MASK (0x8000U) +#define DP83848_EDCR_ED_EN_SHIFT (15U) +#define DP83848_EDCR_ED_EN_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_EN_SHIFT) & DP83848_EDCR_ED_EN_MASK) +#define DP83848_EDCR_ED_EN_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_EN_MASK) >> DP83848_EDCR_ED_EN_SHIFT) + +/* + * ED_AUTO_UP (RW) + * + * Energy Detect Automatic Power Up: + * Automatically begin power-up sequence when Energy Detect Data Threshold value + * (EDCR[3:0]) is reached. Alternatively, device could be powered up manually using the + * ED_MAN bit (ECDR[12]). + */ +#define DP83848_EDCR_ED_AUTO_UP_MASK (0x4000U) +#define DP83848_EDCR_ED_AUTO_UP_SHIFT (14U) +#define DP83848_EDCR_ED_AUTO_UP_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_AUTO_UP_SHIFT) & DP83848_EDCR_ED_AUTO_UP_MASK) +#define DP83848_EDCR_ED_AUTO_UP_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_AUTO_UP_MASK) >> DP83848_EDCR_ED_AUTO_UP_SHIFT) + +/* + * ED_AUTO_DOWN (RW) + * + * Energy Detect Automatic Power Down: + * Automatically begin power-down sequence when no energy is detected. Alternatively, + * device could be powered down using the ED_MAN bit (EDCR[12]). + */ +#define DP83848_EDCR_ED_AUTO_DOWN_MASK (0x2000U) +#define DP83848_EDCR_ED_AUTO_DOWN_SHIFT (13U) +#define DP83848_EDCR_ED_AUTO_DOWN_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_AUTO_DOWN_SHIFT) & DP83848_EDCR_ED_AUTO_DOWN_MASK) +#define DP83848_EDCR_ED_AUTO_DOWN_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_AUTO_DOWN_MASK) >> DP83848_EDCR_ED_AUTO_DOWN_SHIFT) + +/* + * ED_MAN (RW) + * + * Energy Detect Manual Power Up/Down: + * Begin power-up/down sequence when this bit is asserted. When set, the Energy Detect + * algorithm will initiate a change of Energy Detect state regardless of threshold (error or + * data) and timer values. + */ +#define DP83848_EDCR_ED_MAN_MASK (0x1000U) +#define DP83848_EDCR_ED_MAN_SHIFT (12U) +#define DP83848_EDCR_ED_MAN_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_MAN_SHIFT) & DP83848_EDCR_ED_MAN_MASK) +#define DP83848_EDCR_ED_MAN_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_MAN_MASK) >> DP83848_EDCR_ED_MAN_SHIFT) + +/* + * ED_BURST_DIS (RW) + * + * Energy Detect Bust Disable: + * Disable bursting of energy detect data pulses. By default, Energy Detect (ED) transmits + * a burst of 4 ED data pulses each time the CD is powered up. When bursting is + * disabled, only a single ED data pulse will be send each time the CD is powered up. + */ +#define DP83848_EDCR_ED_BURST_DIS_MASK (0x800U) +#define DP83848_EDCR_ED_BURST_DIS_SHIFT (11U) +#define DP83848_EDCR_ED_BURST_DIS_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_BURST_DIS_SHIFT) & DP83848_EDCR_ED_BURST_DIS_MASK) +#define DP83848_EDCR_ED_BURST_DIS_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_BURST_DIS_MASK) >> DP83848_EDCR_ED_BURST_DIS_SHIFT) + +/* + * ED_PWR_STATE (RO) + * + * Energy Detect Power State: + * Indicates current Energy Detect Power state. When set, Energy Detect is in the + * powered up state. When cleared, Energy Detect is in the powered down state. This bit + * is invalid when Energy Detect is not enabled. + */ +#define DP83848_EDCR_ED_PWR_STATE_MASK (0x400U) +#define DP83848_EDCR_ED_PWR_STATE_SHIFT (10U) +#define DP83848_EDCR_ED_PWR_STATE_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_PWR_STATE_MASK) >> DP83848_EDCR_ED_PWR_STATE_SHIFT) + +/* + * ED_ERR_MET (RO) + * + * Energy Detect Error Threshold Met: + * No action is automatically taken upon receipt of error events. This bit is informational + * only and would be cleared on a read. + */ +#define DP83848_EDCR_ED_ERR_MET_MASK (0x200U) +#define DP83848_EDCR_ED_ERR_MET_SHIFT (9U) +#define DP83848_EDCR_ED_ERR_MET_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_ERR_MET_MASK) >> DP83848_EDCR_ED_ERR_MET_SHIFT) + +/* + * ED_DATA_MET (RO) + * + * Energy Detect Data Threshold Met: + * The number of data events that occurred met or surpassed the Energy Detect Data + * Threshold. This bit is cleared on a read. + */ +#define DP83848_EDCR_ED_DATA_MET_MASK (0x100U) +#define DP83848_EDCR_ED_DATA_MET_SHIFT (8U) +#define DP83848_EDCR_ED_DATA_MET_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_DATA_MET_MASK) >> DP83848_EDCR_ED_DATA_MET_SHIFT) + +/* + * ED_ERR_COUNT (RW) + * + * Energy Detect Error Threshold: + * Threshold to determine the number of energy detect error events that should cause the + * device to take action. Intended to allow averaging of noise that may be on the line. + * Counter will reset after approximately 2 seconds without any energy detect data + * events. + */ +#define DP83848_EDCR_ED_ERR_COUNT_MASK (0xF0U) +#define DP83848_EDCR_ED_ERR_COUNT_SHIFT (4U) +#define DP83848_EDCR_ED_ERR_COUNT_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_ERR_COUNT_SHIFT) & DP83848_EDCR_ED_ERR_COUNT_MASK) +#define DP83848_EDCR_ED_ERR_COUNT_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_ERR_COUNT_MASK) >> DP83848_EDCR_ED_ERR_COUNT_SHIFT) + +/* + * ED_DATA_COUNT (RW) + * + * Energy Detect Data Threshold: + * Threshold to determine the number of energy detect events that should cause the + * device to take actions. Intended to allow averaging of noise that may be on the line. + * Counter will reset after approximately 2 seconds without any energy detect data + * events. + */ +#define DP83848_EDCR_ED_DATA_COUNT_MASK (0xFU) +#define DP83848_EDCR_ED_DATA_COUNT_SHIFT (0U) +#define DP83848_EDCR_ED_DATA_COUNT_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_DATA_COUNT_SHIFT) & DP83848_EDCR_ED_DATA_COUNT_MASK) +#define DP83848_EDCR_ED_DATA_COUNT_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_DATA_COUNT_MASK) >> DP83848_EDCR_ED_DATA_COUNT_SHIFT) + + + + #endif /* HPM_DP83848_REGS_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/enet_phy/dp83867/CMakeLists.txt b/common/libraries/hpm_sdk/components/enet_phy/dp83867/CMakeLists.txt index f2848f99..2cfb65c1 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/dp83867/CMakeLists.txt +++ b/common/libraries/hpm_sdk/components/enet_phy/dp83867/CMakeLists.txt @@ -1,6 +1,9 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause +sdk_compile_definitions(-DRGMII=1) +sdk_compile_definitions(-D__USE_DP83867=1) + sdk_inc(.) +sdk_inc(../) sdk_src(hpm_dp83867.c) - diff --git a/common/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c b/common/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c index dddf00ea..484e4598 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c +++ b/common/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c @@ -1,166 +1,138 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_enet_drv.h" #include "hpm_dp83867_regs.h" #include "hpm_dp83867.h" -#include "board.h" -/*---------------------------------------------------------------------* - * Interal API - *---------------------------------------------------------------------*/ -bool dp83867_id_check(ENET_Type *ptr) +/*--------------------------------------------------------------------- + * Internal API + *--------------------------------------------------------------------- + */ +bool dp83867_check_id(ENET_Type *ptr) { uint16_t id1, id2; - id1 = enet_read_phy(ptr, PHY_ADDR, DP83867_REG_PHYID1); - id2 = enet_read_phy(ptr, PHY_ADDR, DP83867_REG_PHYID2); + id1 = enet_read_phy(ptr, PHY_ADDR, DP83867_PHYIDR1); + id2 = enet_read_phy(ptr, PHY_ADDR, DP83867_PHYIDR2); - if (DP83867_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && DP83867_PHYID2_OUI_MSB_GET(id2) == PHY_ID2) { + if (DP83867_PHYIDR1_OUI_MSB_GET(id1) == PHY_ID1 && DP83867_PHYIDR2_OUI_LSB_GET(id2) == PHY_ID2) { return true; } else { return false; } } -static void dp83867_phy_write_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data) +static void dp83867_write_phy_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data) { /* set the control register for register address */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_REGCR, DP83867_REGCR_FUNCTION_ADDR | DP83867_REGCR_DEVAD); + enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(0) | DP83867_REGCR_DEVAD_SET(0x1f)); /* write the specified register address */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_ADDAR, addr); + enet_write_phy(ptr, phy_addr, DP83867_ADDAR, addr); /* set the control register for register data */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_REGCR, DP83867_REGCR_FUNCTION_DATA | DP83867_REGCR_DEVAD); + enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(1) | DP83867_REGCR_DEVAD_SET(0x1f)); /* write the specified register data */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_ADDAR, data); + enet_write_phy(ptr, phy_addr, DP83867_ADDAR, data); } -static uint16_t dp83867_phy_read_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr) +static uint16_t dp83867_read_phy_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr) { /* set the control register for register address */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_REGCR, DP83867_REGCR_FUNCTION_ADDR | DP83867_REGCR_DEVAD); + enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(0) | DP83867_REGCR_DEVAD_SET(0x1f)); /* write the specified register address */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_ADDAR, addr); + enet_write_phy(ptr, phy_addr, DP83867_ADDAR, addr); /* set the control register for register data */ - enet_write_phy(ptr, phy_addr, DP83867_EXT_REG_REGCR, DP83867_REGCR_FUNCTION_DATA | DP83867_REGCR_DEVAD); + enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(1) | DP83867_REGCR_DEVAD_SET(0x1f)); /* read the specified register data */ - return enet_read_phy(ptr, phy_addr, DP83867_EXT_REG_ADDAR); + return enet_read_phy(ptr, phy_addr, DP83867_ADDAR); } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * API - *---------------------------------------------------------------------*/ -uint16_t DP83867_REGister_check(ENET_Type *ptr, uint32_t addr) -{ - return enet_read_phy(ptr, PHY_ADDR, addr); -} - + *--------------------------------------------------------------------- + */ void dp83867_reset(ENET_Type *ptr) { uint16_t data; /* PHY reset */ - enet_write_phy(ptr, PHY_ADDR, DP83867_REG_BMCR, DP83867_BMCR_RESET_SET(1)); + enet_write_phy(ptr, PHY_ADDR, DP83867_BMCR, DP83867_BMCR_RESET_SET(1)); /* wait until the reset is completed */ do { - data = enet_read_phy(ptr, PHY_ADDR, DP83867_REG_BMCR); + data = enet_read_phy(ptr, PHY_ADDR, DP83867_BMCR); } while (DP83867_BMCR_RESET_GET(data)); } void dp83867_basic_mode_default_config(ENET_Type *ptr, dp83867_config_t *config) { - config->loopback = 0; /* Enable PCS loopback mode */ - config->speed = 2; /* 3: reserved; 2: 1000mbps; 1: 100mbps; 0: 10mbps */ - config->auto_negotiation = 1; /* Enable Auto-Negotiation */ - config->duplex_mode = 1; /* Full duplex mode */ + config->loopback = false; /* Disable PCS loopback mode */ + #if __DISABLE_AUTO_NEGO + config->auto_negotiation = false; /* Disable Auto-Negotiation */ + config->speed = enet_phy_port_speed_100mbps; + config->duplex = enet_phy_duplex_full; + #else + config->auto_negotiation = true; /* Enable Auto-Negotiation */ + #endif } bool dp83867_basic_mode_init(ENET_Type *ptr, dp83867_config_t *config) { - uint16_t para = 0; + uint16_t data = 0; - para |= DP83867_BMCR_RESET_SET(0) /* Normal operation */ + data |= DP83867_BMCR_RESET_SET(0) /* Normal operation */ | DP83867_BMCR_LOOPBACK_SET(config->loopback) /* Configure PCS loopback mode */ | DP83867_BMCR_ANE_SET(config->auto_negotiation) /* Configure Auto-Negotiation */ | DP83867_BMCR_PWD_SET(0) /* Normal operation */ | DP83867_BMCR_ISOLATE_SET(0) /* Normal operation */ | DP83867_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ - | DP83867_BMCR_DUPLEX_SET(config->duplex_mode) /* Config duplex mode */ | DP83867_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ if (config->auto_negotiation == false) { - para |= DP83867_BMCR_SPEED0_SET(config->speed) | DP83867_BMCR_SPEED1_SET(config->speed >> 1); + data |= DP83867_BMCR_SPEED0_SET(config->speed) | DP83867_BMCR_SPEED1_SET(config->speed >> 1); /* Set port speed */ + data |= DP83867_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ } /* check the id of dp83867 */ - if (dp83867_id_check(ptr) == false) { + if (dp83867_check_id(ptr) == false) { return false; } - while (dp83867_get_phy_link_status(ptr) == 0) { - - } + enet_write_phy(ptr, PHY_ADDR, DP83867_BMCR, data); + data = enet_read_phy(ptr, PHY_ADDR, DP83867_BMCR); return true; } -void dp83867_init_auto_negotiation(void) -{ - -} - -uint16_t dp83867_get_phy_link_status(ENET_Type *ptr) -{ - return DP83867_BMSR_LINK_STATUS_GET(enet_read_phy(ptr, PHY_ADDR, DP83867_REG_BMSR)); -} - -void dp83867_set_rgmii_rx_delay(ENET_Type *ptr, uint32_t phy_addr, uint8_t delay) +void dp83867_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) { - dp83867_phy_write_ext(ptr, phy_addr, DP83867_EXT_REG_RGMIIDCTL, delay); -} - -uint16_t dp83867_get_rgmii_rx_delay(ENET_Type *ptr, uint32_t phy_addr) -{ - uint16_t temp = 0; - - temp = dp83867_phy_read_ext(ptr, phy_addr, DP83867_EXT_REG_RGMIIDCTL); - - return temp; -} - -void dp83867_set_rx_clk_delay(ENET_Type *ptr) -{ - uint16_t para = 0; - - para = dp83867_phy_read_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL); - dp83867_phy_write_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL, para | 1); -} - -void dp83867_enable_crc_check(ENET_Type *ptr) -{ - uint16_t para = 0; + uint16_t data; - para = dp83867_phy_read_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RXFCFG); - dp83867_phy_write_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RXFCFG, para | (1 << 7)); + data = enet_read_phy(ptr, PHY_ADDR, DP83867_PHYSTS); + status->enet_phy_link = DP83867_PHYSTS_LINK_STATUS_GET(data); + status->enet_phy_speed = DP83867_PHYSTS_SPEED_SELECTION_GET(data) == 0 ? enet_phy_port_speed_10mbps : DP83867_PHYSTS_SPEED_SELECTION_GET(data) == 1 ? enet_phy_port_speed_100mbps : enet_phy_port_speed_1000mbps; + status->enet_phy_duplex = DP83867_PHYSTS_DUPLEX_MODE_GET(data); } -void dp83867_enable_rmii_inf(ENET_Type *ptr) +void dp83867_set_mdi_crossover_mode(ENET_Type *ptr, enet_phy_crossover_mode_t mode) { - uint16_t para = 0; + uint16_t data; - para = dp83867_phy_read_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL); - dp83867_phy_write_ext(ptr, PHY_ADDR, DP83867_EXT_REG_RGMIICTL, para | (1 << 7)); -} + data = dp83867_read_phy_ext(ptr, PHY_ADDR, DP83867_PHYCR); + data &= ~DP83867_PHYCR_MDI_CROSSOVER_MASK; + data |= DP83867_PHYCR_MDI_CROSSOVER_SET(mode); + dp83867_write_phy_ext(ptr, PHY_ADDR, DP83867_PHYCR, data); +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h b/common/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h index 5e636595..6a8b23d4 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h +++ b/common/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h @@ -1,33 +1,37 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -#ifndef HPM_DP83867_H -#define HPM_DP83867_H +#ifndef HPM_DP83867_DRV_H +#define HPM_DP83867_DRV_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ -#include "stdint.h" - -/*---------------------------------------------------------------------* + *--------------------------------------------------------------------- + */ +#include "hpm_enet_phy.h" +#include "hpm_common.h" +#include "hpm_enet_regs.h" +/*--------------------------------------------------------------------- * Macro Const Definitions - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #define PHY_ADDR (0U) #define PHY_ID1 (0x2000U) #define PHY_ID2 (0x28U) -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Typedef Struct Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ typedef struct { bool loopback; uint8_t speed; bool auto_negotiation; - uint8_t duplex_mode; + uint8_t duplex; } dp83867_config_t; typedef enum { @@ -52,25 +56,17 @@ typedef enum { #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Exported Functions - *---------------------------------------------------------------------*/ -uint16_t dp83867_check(ENET_Type *ptr, uint32_t addr); + *--------------------------------------------------------------------- + */ void dp83867_reset(ENET_Type *ptr); void dp83867_basic_mode_default_config(ENET_Type *ptr, dp83867_config_t *config); bool dp83867_basic_mode_init(ENET_Type *ptr, dp83867_config_t *config); -void dp83867_read_status(ENET_Type *ptr); -void dp83867_control_config(ENET_Type *ptr); -void dp83867_ctl_config(ENET_Type *ptr); -void dp83867_bist_config(ENET_Type *ptr); -uint16_t dp83867_get_phy_link_status(ENET_Type *ptr); -void dp83867_set_rx_clk_delay(ENET_Type *ptr); -void dp83867_enable_crc_check(ENET_Type *ptr); -void dp83867_set_rgmii_rx_delay(ENET_Type *ptr, uint32_t phy_addr, uint8_t delay); -uint16_t dp83867_get_rgmii_rx_delay(ENET_Type *ptr, uint32_t phy_addr); -void dp83867_enable_rmii_inf(ENET_Type *ptr); +void dp83867_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); +void dp83867_set_mdi_crossover_mode(ENET_Type *ptr, enet_phy_crossover_mode_t mode); #if defined(__cplusplus) } #endif /* __cplusplus */ -#endif /* HPM_DP83867_H */ \ No newline at end of file +#endif /* HPM_DP83867_H */ diff --git a/common/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h b/common/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h index 1c228f3a..37599789 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h +++ b/common/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h @@ -1,198 +1,326 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ + #ifndef HPM_DP83867_REGS_H #define HPM_DP83867_REGS_H - /* Register Definitions */ -#define DP83867_REG_BMCR (0U) /* Basic Mode Control Register */ -#define DP83867_REG_BMSR (1U) /* Basic Mode Status Register */ -#define DP83867_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ -#define DP83867_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ -#define DP83867_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ -#define DP83867_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ -#define DP83867_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ -#define DP83867_REG_ANNPTR (7U) /* Auto-Negotiation Next Page Transmit Register */ -#define DP83867_REG_ANNPRR (8U) /* Auto-Negotiation Next Page Receive Register */ -#define DP83867_REG_GBCR (9U) /* 1000Base-T Control Register */ -#define DP83867_REG_STATUS (10U) /* Status Register */ - -#define DP83867_REG_MACR (13U) /* MMD Access Control Register */ -#define DP83867_REG_MAADR (14U) /* MMD Access Address Data Register */ -#define DP83867_REG_GBESR (15U) /* 1000Base-T Extended Status Register */ -#define DP83867_REG_PHYCR (16U) /* PHY Specific Control Register */ -#define DP83867_REG_PHYSR (17U) /* PHY Specific Status Register */ -#define DP83867_REG_INER (18U) /* Interrupt Enable Register */ -#define DP83867_REG_INSR (19U) /* Interrupt Status Register */ -#define DP83867_REG_RXERC (24U) /* Receive Error Counter */ -#define DP83867_REG_PAGSEL (31U) /* Page Select Register */ - -/* RTL MMD Register Definitions */ -#define DP83867_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ -#define DP83867_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ -#define DP83867_MMD_REG_EEECR (20U) /* EEE Capability Register */ -#define DP83867_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ -#define DP83867_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ -#define DP83867_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ - -/* DP83867 */ - -/* DP83867 Extended Registers */ -#define DP83867_EXT_REG_REGCR (0x000DU) /* Register Control Register */ -#define DP83867_EXT_REG_ADDAR (0x000EU) /* Address or Data Register */ -#define DP83867_EXT_REG_BISCR (0x0016U) /* BIST Control Register */ -#define DP83867_EXT_REG_CTRL (0x001fU) /* Control Register */ -#define DP83867_EXT_REG_RGMIICTL (0x0032U) /* RGMII Control Register */ -#define DP83867_EXT_REG_LOOPCR (0x00FEU) /* Loopback Configuration Register */ -#define DP83867_EXT_REG_RXFCFG (0x0134U) /* Recevie Configuration Register */ - -/* DP83867 extended registers */ -#define DP83867_EXT_REG_RGMIIDCTL (0x0086U) /* RGMII Delay Control */ - - -#define DP83867_REGCR_FUNCTION_ADDR (0 << 14) -#define DP83867_REGCR_FUNCTION_DATA (1 << 14) -#define DP83867_REGCR_DEVAD (0x1f) +typedef enum { + DP83867_BMCR = 0, /* 0x0: Basic Mode Control Register */ + DP83867_BMSR = 1, /* 0x1: Basic Mode Status Register */ + DP83867_PHYIDR1 = 2, /* 0x2: PHY Identifier Register #1 */ + DP83867_PHYIDR2 = 3, /* 0x3: PHY Identifier Register #2 */ + DP83867_ANAR = 4, /* 0x4: MII Interrupt Control Register */ + DP83867_ANLPAR = 5, /* 0x5: Auto-Negotiation Link Partner Ability Register */ + DP83867_ANER = 6, /* 0x6: Auto-Negotiate Expansion Register */ + DP83867_ANNPTR = 7, /* 0x7: Auto-Negotiation Next Page Transmit Register */ + DP83867_ANNPRR = 8, /* 0x8: Auto-Negotiation Next Page Receive Register */ + DP83867_CFG1 = 9, /* 0x9: Configuration Register 1 */ + DP83867_STS1 = 10, /* 0xA: Status Register 1 */ + DP83867_REGCR = 13, /* 0xD: Register Control Register */ + DP83867_ADDAR = 14, /* 0xE: Address or Data Register */ + DP83867_1KSCR = 15, /* 0xF: 1000BASE-T Status Register */ + DP83867_PHYCR = 16, /* 0x10: PHY Control Register */ + DP83867_PHYSTS = 17, /* 0x11: PHY Status Register */ + DP83867_MICR = 18, /* 0x12: MII Interrupt Control Register */ + DP83867_ISR = 19, /* 0x13: Interrupt Status Register */ + DP83867_CRG2 = 20, /* 0x14: Configuration Register 2 */ + DP83867_RECR = 21, /* 0x15: Receiver Error Counter Register */ + DP83867_STS2 = 23, /* 0x17: Status Register 2 */ + DP83867_LEDCR1 = 24, /* 0x18: LED Configuration Register 1 */ + DP83867_LEDCR2 = 25, /* 0x19: LED Configuration Register 2 */ + DP83867_LEDCR3 = 26, /* 0x1A: LED Configuration Register 3 */ + DP83867_CFG3 = 30, /* 0x1E: Configuration Register 3 */ + DP83867_CTRL = 31, /* 0x1F: Control Register */ + DP83867_RGMIIDCTL = 134, /* 0x86: RGMII Delay Control Register */ +} DP83867_REG_Type; + /* Bitfield definition for register: BMCR */ /* - * Reset (RW) + * RESET (RW/SC) * - * 1: PHY reset - * 0: Normal operation - * Register 0 (BMCR) and register 1 (BMSR) will return to default - * values after a software reset (set Bit15 to 1). - * This action may change the internal PHY state and the state of the - * physical link associated with the PHY. + * Reset: + * 1 = Initiate software Reset / Reset in Process. + * 0 = Normal operation. + * This bit, which is self-clearing, returns a value of one until the reset + * process is complete. The configuration is restrapped. */ -#define DP83867_BMCR_RESET_MASK (0x8000U) +#define DP83867_BMCR_RESET_MASK (0x8000U) #define DP83867_BMCR_RESET_SHIFT (15U) -#define DP83867_BMCR_RESET_SET(x) (((uint32_t)(x) << DP83867_BMCR_RESET_SHIFT) & DP83867_BMCR_RESET_MASK) -#define DP83867_BMCR_RESET_GET(x) (((uint32_t)(x) & DP83867_BMCR_RESET_MASK) >> DP83867_BMCR_RESET_SHIFT) +#define DP83867_BMCR_RESET_SET(x) (((uint16_t)(x) << DP83867_BMCR_RESET_SHIFT) & DP83867_BMCR_RESET_MASK) +#define DP83867_BMCR_RESET_GET(x) (((uint16_t)(x) & DP83867_BMCR_RESET_MASK) >> DP83867_BMCR_RESET_SHIFT) /* - * Loopback (RW) + * LOOPBACK (RW) * - * Loopback Mode. - * 1: Enable PCS loopback mode - * 0: Disable PCS loopback mode + * Loopback: + * 1 = Loopback enabled. + * 0 = Normal operation. + * The loopback function enables MAC transmit data to be routed to + * the MAC receive data path. + * Setting this bit may cause the descrambler to lose synchronization + * and produce a 500-µs dead time before any valid data will appear at + * the MII receive outputs. */ -#define DP83867_BMCR_LOOPBACK_MASK (0x4000U) +#define DP83867_BMCR_LOOPBACK_MASK (0x4000U) #define DP83867_BMCR_LOOPBACK_SHIFT (14U) -#define DP83867_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << DP83867_BMCR_LOOPBACK_SHIFT) & DP83867_BMCR_LOOPBACK_MASK) -#define DP83867_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & DP83867_BMCR_LOOPBACK_MASK) >> DP83867_BMCR_LOOPBACK_SHIFT) +#define DP83867_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << DP83867_BMCR_LOOPBACK_SHIFT) & DP83867_BMCR_LOOPBACK_MASK) +#define DP83867_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & DP83867_BMCR_LOOPBACK_MASK) >> DP83867_BMCR_LOOPBACK_SHIFT) /* - * Speed[0] (RW) + * SPEED0 (RW) * - * Speed Select Bit 0. - * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 - * determine device speed selection. + * Speed Select (Bits 6, 13): + * When auto-negotiation is disabled writing to this bit allows the port + * speed to be selected. + * 11 = Reserved + * 10 = 1000 Mbps + * 1 = 100 Mbps + * 0 = 10 Mbps */ -#define DP83867_BMCR_SPEED0_MASK (0x2000U) +#define DP83867_BMCR_SPEED0_MASK (0x2000U) #define DP83867_BMCR_SPEED0_SHIFT (13U) -#define DP83867_BMCR_SPEED0_SET(x) (((uint32_t)(x) << DP83867_BMCR_SPEED0_SHIFT) & DP83867_BMCR_SPEED0_MASK) -#define DP83867_BMCR_SPEED0_GET(x) (((uint32_t)(x) & DP83867_BMCR_SPEED0_MASK) >> DP83867_BMCR_SPEED0_SHIFT) +#define DP83867_BMCR_SPEED0_SET(x) (((uint16_t)(x) << DP83867_BMCR_SPEED0_SHIFT) & DP83867_BMCR_SPEED0_MASK) +#define DP83867_BMCR_SPEED0_GET(x) (((uint16_t)(x) & DP83867_BMCR_SPEED0_MASK) >> DP83867_BMCR_SPEED0_SHIFT) /* - * ANE (RW) + * ANE (STRAP, RW) * - * Auto-Negotiation Enable. - * 1: Enable Auto-Negotiation - * 0: Disable Auto-Negotiation + * Auto-Negotiation Enable: + * Strap controls initial value at reset. + * 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are + * ignored when this bit is set. + * 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port + * speed and duplex mode. */ -#define DP83867_BMCR_ANE_MASK (0x1000U) +#define DP83867_BMCR_ANE_MASK (0x1000U) #define DP83867_BMCR_ANE_SHIFT (12U) -#define DP83867_BMCR_ANE_SET(x) (((uint32_t)(x) << DP83867_BMCR_ANE_SHIFT) & DP83867_BMCR_ANE_MASK) -#define DP83867_BMCR_ANE_GET(x) (((uint32_t)(x) & DP83867_BMCR_ANE_MASK) >> DP83867_BMCR_ANE_SHIFT) +#define DP83867_BMCR_ANE_SET(x) (((uint16_t)(x) << DP83867_BMCR_ANE_SHIFT) & DP83867_BMCR_ANE_MASK) +#define DP83867_BMCR_ANE_GET(x) (((uint16_t)(x) & DP83867_BMCR_ANE_MASK) >> DP83867_BMCR_ANE_SHIFT) /* * PWD (RW) * - * Power Down. - * 1: Power down (only Management Interface and logic are active; link - * is down) - * 0: Normal operation + * Power Down: + * 1 = Power down. + * 0 = Normal operation. + * Setting this bit powers down the PHY. Only the register block is + * enabled during a power down condition. This bit is ORd with the + * input from the PWRDOWN_INT pin. When the active low + * PWRDOWN_INT pin is asserted, this bit will be set. */ -#define DP83867_BMCR_PWD_MASK (0x0800U) +#define DP83867_BMCR_PWD_MASK (0x800U) #define DP83867_BMCR_PWD_SHIFT (11U) -#define DP83867_BMCR_PWD_SET(x) (((uint32_t)(x) << DP83867_BMCR_PWD_SHIFT) & DP83867_BMCR_PWD_MASK) -#define DP83867_BMCR_PWD_GET(x) (((uint32_t)(x) & DP83867_BMCR_PWD_MASK) >> DP83867_BMCR_PWD_SHIFT) +#define DP83867_BMCR_PWD_SET(x) (((uint16_t)(x) << DP83867_BMCR_PWD_SHIFT) & DP83867_BMCR_PWD_MASK) +#define DP83867_BMCR_PWD_GET(x) (((uint16_t)(x) & DP83867_BMCR_PWD_MASK) >> DP83867_BMCR_PWD_SHIFT) /* - * Isolate (RW) + * ISOLATE (RW) * - * Isolate. - * 1: RGMII/GMII interface is isolated; the serial management interface - * (MDC, MDIO) is still active. When this bit is asserted, the - * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and - * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. - * 0: Normal operation + * Isolate: + * 1 = Isolates the Port from the MII with the exception of the serial + * management. + * 0 = Normal operation. */ -#define DP83867_BMCR_ISOLATE_MASK (0x0400U) +#define DP83867_BMCR_ISOLATE_MASK (0x400U) #define DP83867_BMCR_ISOLATE_SHIFT (10U) -#define DP83867_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << DP83867_BMCR_ISOLATE_SHIFT) & DP83867_BMCR_ISOLATE_MASK) -#define DP83867_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & DP83867_BMCR_ISOLATE_MASK) >> DP83867_BMCR_ISOLATE_SHIFT) +#define DP83867_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << DP83867_BMCR_ISOLATE_SHIFT) & DP83867_BMCR_ISOLATE_MASK) +#define DP83867_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & DP83867_BMCR_ISOLATE_MASK) >> DP83867_BMCR_ISOLATE_SHIFT) /* - * Restart_AN (RW) + * RESTART_AN (RW/SC) * - * Restart Auto-Negotiation. - * 1: Restart Auto-Negotiation - * 0: Normal operation + * Restart Auto-Negotiation: + * 1 = Restart Auto-Negotiation. Reinitiates the Auto-Negotiation + * process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is + * ignored. This bit is self-clearing and will return a value of 1 until + * Auto-Negotiation is initiated, whereupon it will self-clear. Operation of + * the Auto-Negotiation process is not affected by the management + * entity clearing this bit. + * 0 = Normal operation. */ -#define DP83867_BMCR_RESTART_AN_MASK (0x0200U) +#define DP83867_BMCR_RESTART_AN_MASK (0x200U) #define DP83867_BMCR_RESTART_AN_SHIFT (9U) -#define DP83867_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << DP83867_BMCR_RESTART_AN_SHIFT) & DP83867_BMCR_RESTART_AN_MASK) -#define DP83867_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & DP83867_BMCR_RESTART_AN_MASK) >> DP83867_BMCR_RESTART_AN_SHIFT) +#define DP83867_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << DP83867_BMCR_RESTART_AN_SHIFT) & DP83867_BMCR_RESTART_AN_MASK) +#define DP83867_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & DP83867_BMCR_RESTART_AN_MASK) >> DP83867_BMCR_RESTART_AN_SHIFT) /* - * Duplex (RW) + * DUPLEX (STRAP, RW) * - * Duplex Mode. - * 1: Full Duplex operation - * 0: Half Duplex operation - * This bit is valid only in force mode, i.e., NWay is disabled. + * Duplex Mode: + * When auto-negotiation is disabled writing to this bit allows the port + * Duplex capability to be selected. + * 1 = Full Duplex operation. + * 0 = Half Duplex operation. */ -#define DP83867_BMCR_DUPLEX_MASK (0x0100U) +#define DP83867_BMCR_DUPLEX_MASK (0x100U) #define DP83867_BMCR_DUPLEX_SHIFT (8U) -#define DP83867_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << DP83867_BMCR_DUPLEX_SHIFT) & DP83867_BMCR_DUPLEX_MASK) -#define DP83867_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & DP83867_BMCR_DUPLEX_MASK) >> DP83867_BMCR_DUPLEX_SHIFT) +#define DP83867_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << DP83867_BMCR_DUPLEX_SHIFT) & DP83867_BMCR_DUPLEX_MASK) +#define DP83867_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMCR_DUPLEX_MASK) >> DP83867_BMCR_DUPLEX_SHIFT) /* - * Collision Test (RW) + * COLLISION_TEST (RW) * - * Collision Test. - * 1: Collision test enabled - * 0: Normal operation - * When set, this bit will cause the COL signal to be asserted in response - * to the assertion of TXEN within 512-bit times. The COL signal will be - * de-asserted within 4-bit times in response to the de-assertion of - * TXEN. + * Collision Test: + * 1 = Collision test enabled. + * 0 = Normal operation. + * When set, this bit will cause the COL signal to be asserted in + * response to the assertion of TX_EN within 512-bit times. The COL + * signal will be deasserted within 4-bit times in response to the + * deassertion of TX_EN. */ -#define DP83867_BMCR_COLLISION_TEST_MASK (0x0080U) +#define DP83867_BMCR_COLLISION_TEST_MASK (0x80U) #define DP83867_BMCR_COLLISION_TEST_SHIFT (7U) -#define DP83867_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << DP83867_BMCR_COLLISION_TEST_SHIFT) & DP83867_BMCR_COLLISION_TEST_MASK) -#define DP83867_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & DP83867_BMCR_COLLISION_TEST_MASK) >> DP83867_BMCR_COLLISION_TEST_SHIFT) +#define DP83867_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << DP83867_BMCR_COLLISION_TEST_SHIFT) & DP83867_BMCR_COLLISION_TEST_MASK) +#define DP83867_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & DP83867_BMCR_COLLISION_TEST_MASK) >> DP83867_BMCR_COLLISION_TEST_SHIFT) /* - * Speed[1] (RW) + * SPEED1 (RW) * - * Speed Select Bit 1. - * Refer to bit 0.13. + * Speed Select: See description for bit 13. */ -#define DP83867_BMCR_SPEED1_MASK (0x0040U) +#define DP83867_BMCR_SPEED1_MASK (0x40U) #define DP83867_BMCR_SPEED1_SHIFT (6U) -#define DP83867_BMCR_SPEED1_SET(x) (((uint32_t)(x) << DP83867_BMCR_SPEED1_SHIFT) & DP83867_BMCR_SPEED1_MASK) -#define DP83867_BMCR_SPEED1_GET(x) (((uint32_t)(x) & DP83867_BMCR_SPEED1_MASK) >> DP83867_BMCR_SPEED1_SHIFT) +#define DP83867_BMCR_SPEED1_SET(x) (((uint16_t)(x) << DP83867_BMCR_SPEED1_SHIFT) & DP83867_BMCR_SPEED1_MASK) +#define DP83867_BMCR_SPEED1_GET(x) (((uint16_t)(x) & DP83867_BMCR_SPEED1_MASK) >> DP83867_BMCR_SPEED1_SHIFT) /* Bitfield definition for register: BMSR */ +/* + * 100BASE_T4 (RO/P) + * + * 100BASE-T4 Capable: + * 0 = Device not able to perform 100BASE-T4 mode. + */ +#define DP83867_BMSR_100BASE_T4_MASK (0x8000U) +#define DP83867_BMSR_100BASE_T4_SHIFT (15U) +#define DP83867_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_T4_MASK) >> DP83867_BMSR_100BASE_T4_SHIFT) + +/* + * 100BASE_TX_FULL_DUPLEX (RO/P) + * + * 100BASE-TX Full Duplex Capable: + * 1 = Device able to perform 100BASE-TX in full duplex mode. + */ +#define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_MASK (0x4000U) +#define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT (14U) +#define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_TX_FULL_DUPLEX_MASK) >> DP83867_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT) + +/* + * 100BASE_TX_HALF_DUPLEX (RO/P) + * + * 100BASE-TX Half Duplex Capable: + * 1 = Device able to perform 100BASE-TX in half duplex mode. + */ +#define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_MASK (0x2000U) +#define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_SHIFT (13U) +#define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_TX_HALF_DUPLEX_MASK) >> DP83867_BMSR_100BASE_TX_HALF_DUPLEX_SHIFT) + +/* + * 10BASE_TE_FULL_DUPLEX (RO/P) + * + * 10BASE-Te Full Duplex Capable: + * 1 = Device able to perform 10BASE-Te in full duplex mode. + */ +#define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_MASK (0x1000U) +#define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_SHIFT (12U) +#define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_10BASE_TE_FULL_DUPLEX_MASK) >> DP83867_BMSR_10BASE_TE_FULL_DUPLEX_SHIFT) + +/* + * 10BASE_TE_HALF_DUPLEX (RO/P) + * + * 10BASE-Te Half Duplex Capable: + * 1 = Device able to perform 10BASE-Te in half duplex mode. + */ +#define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_MASK (0x800U) +#define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_SHIFT (11U) +#define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_10BASE_TE_HALF_DUPLEX_MASK) >> DP83867_BMSR_10BASE_TE_HALF_DUPLEX_SHIFT) + +/* + * 100BASE_T2_FULL_DUPLEX (RO/P) + * + * 100BASE-T2 Full Duplex Capable: + * 0 = Device not able to perform 100BASE-T2 in full duplex mode. + */ +#define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_MASK (0x400U) +#define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_SHIFT (10U) +#define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_T2_FULL_DUPLEX_MASK) >> DP83867_BMSR_100BASE_T2_FULL_DUPLEX_SHIFT) + +/* + * 100BASE_T2_HALF_DUPLEX (RO/P) + * + * 100BASE-T2 Half Duplex Capable: + * 0 = Device not able to perform 100BASE-T2 in half duplex mode. + */ +#define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_MASK (0x200U) +#define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_SHIFT (9U) +#define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_T2_HALF_DUPLEX_MASK) >> DP83867_BMSR_100BASE_T2_HALF_DUPLEX_SHIFT) + +/* + * EXTENDED_STATUS (RO/P) + * + * 1000BASE-T Extended Status Register: + * 1 = Device supports Extended Status Register 0x0F. + */ +#define DP83867_BMSR_EXTENDED_STATUS_MASK (0x100U) +#define DP83867_BMSR_EXTENDED_STATUS_SHIFT (8U) +#define DP83867_BMSR_EXTENDED_STATUS_GET(x) (((uint16_t)(x) & DP83867_BMSR_EXTENDED_STATUS_MASK) >> DP83867_BMSR_EXTENDED_STATUS_SHIFT) + +/* + * MF_PREAMBLE_SUPPRESSION (RO/P) + * + * Preamble Suppression Capable: + * 1 = Device able to perform management transaction with preamble + * suppressed, 32-bits of preamble needed only once after reset, + * invalid opcode or invalid turnaround. + * 0 = Normal management operation. + */ +#define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_MASK (0x40U) +#define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT (6U) +#define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_MASK) >> DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT) + +/* + * AUTO_NEGOTIATION_COMPLETE (RO) + * + * Auto-Negotiation Complete: + * 1 = Auto-Negotiation process complete. + * 0 = Auto-Negotiation process not complete. + */ +#define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) +#define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) +#define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) + +/* + * REMOTE_FAULT (RO/LH) + * + * Remote Fault: + * 1 = Remote Fault condition detected (cleared on read or by reset). + * Fault criteria: Far-End Fault Indication or notification from Link + * Partner of Remote Fault. + * 0 = No remote fault condition detected. + */ +#define DP83867_BMSR_REMOTE_FAULT_MASK (0x10U) +#define DP83867_BMSR_REMOTE_FAULT_SHIFT (4U) +#define DP83867_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & DP83867_BMSR_REMOTE_FAULT_MASK) >> DP83867_BMSR_REMOTE_FAULT_SHIFT) + +/* + * AUTO_NEGOTIATION_ABILITY ( RO/P ) + * + * Auto Negotiation Ability: + * 1 = Device is able to perform Auto-Negotiation. + * 0 = Device is not able to perform Auto-Negotiation. + */ +#define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) +#define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) +#define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) /* + * LINK_STATUS ( RO/LL) + * * Link Status: * 1 = Valid link established. * 0 = Link not established. @@ -200,45 +328,2161 @@ * occurrence of a link failure condition will causes the Link Status bit * to clear. Once cleared, this bit may only be set by establishing a * good link condition and a read through the management interface. -*/ -#define DP83867_BMSR_LINK_STATUS_MASK (0x0004U) + */ +#define DP83867_BMSR_LINK_STATUS_MASK (0x4U) #define DP83867_BMSR_LINK_STATUS_SHIFT (2U) -#define DP83867_BMSR_LINK_STATUS_GET(x) (((uint32_t)(x) & DP83867_BMSR_LINK_STATUS_MASK) >> DP83867_BMSR_LINK_STATUS_SHIFT) +#define DP83867_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83867_BMSR_LINK_STATUS_MASK) >> DP83867_BMSR_LINK_STATUS_SHIFT) + +/* + * JABBER_DETECT ( RO/LH) + * + * Jabber Detect: This bit only has meaning in 10-Mbps mode. + * 1 = Jabber condition detected. + * 0 = No Jabber. + * This bit is implemented with a latching function, such that the + * occurrence of a jabber condition causes it to set until it is cleared by + * a read to this register by the management interface or by a reset. + */ +#define DP83867_BMSR_JABBER_DETECT_MASK (0x2U) +#define DP83867_BMSR_JABBER_DETECT_SHIFT (1U) +#define DP83867_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83867_BMSR_JABBER_DETECT_MASK) >> DP83867_BMSR_JABBER_DETECT_SHIFT) + +/* + * EXTENDED_CAPABILITY (RO/P) + * + * Extended Capability: + * 1 = Extended register capabilities. + * 0 = Basic register set capabilities only. + */ +#define DP83867_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) +#define DP83867_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) +#define DP83867_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & DP83867_BMSR_EXTENDED_CAPABILITY_MASK) >> DP83867_BMSR_EXTENDED_CAPABILITY_SHIFT) + +/* Bitfield definition for register: PHYIDR1 */ +/* + * OUI_MSB (RO/P) + * + * OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h,) are + * stored in bits 15 to 0 of this register. The most significant two bits of + * the OUI are ignored (the IEEE standard refers to these as bits 1 and + * 2). + */ +#define DP83867_PHYIDR1_OUI_MSB_MASK (0xFFFFU) +#define DP83867_PHYIDR1_OUI_MSB_SHIFT (0U) +#define DP83867_PHYIDR1_OUI_MSB_GET(x) (((uint16_t)(x) & DP83867_PHYIDR1_OUI_MSB_MASK) >> DP83867_PHYIDR1_OUI_MSB_SHIFT) + +/* Bitfield definition for register: PHYIDR2 */ +/* + * OUI_LSB (RO/P) + * + * OUI Least Significant Bits: + * Bits 19 to 24 of the OUI (080028h) are mapped from bits 15 to 10 of + * this register respectively. + */ +#define DP83867_PHYIDR2_OUI_LSB_MASK (0xFC00U) +#define DP83867_PHYIDR2_OUI_LSB_SHIFT (10U) +#define DP83867_PHYIDR2_OUI_LSB_GET(x) (((uint16_t)(x) & DP83867_PHYIDR2_OUI_LSB_MASK) >> DP83867_PHYIDR2_OUI_LSB_SHIFT) + +/* + * VNDR_MDL (RO/P) + * + * Vendor Model Number: + * The six bits of vendor model number are mapped from bits 9 to 4 + * (most significant bit to bit 9). + */ +#define DP83867_PHYIDR2_VNDR_MDL_MASK (0x3F0U) +#define DP83867_PHYIDR2_VNDR_MDL_SHIFT (4U) +#define DP83867_PHYIDR2_VNDR_MDL_GET(x) (((uint16_t)(x) & DP83867_PHYIDR2_VNDR_MDL_MASK) >> DP83867_PHYIDR2_VNDR_MDL_SHIFT) + +/* + * MDL_REV (RO/P) + * + * Model Revision Number: + * Four bits of the vendor model revision number are mapped from bits + * 3 to 0 (most significant bit to bit 3). This field will be incremented for + * all major device changes. + */ +#define DP83867_PHYIDR2_MDL_REV_MASK (0xFU) +#define DP83867_PHYIDR2_MDL_REV_SHIFT (0U) +#define DP83867_PHYIDR2_MDL_REV_GET(x) (((uint16_t)(x) & DP83867_PHYIDR2_MDL_REV_MASK) >> DP83867_PHYIDR2_MDL_REV_SHIFT) + +/* Bitfield definition for register: ANAR */ +/* + * NP (RW) + * + * Next Page Indication: + * 0 = Next Page Transfer not desired. + * 1 = Next Page Transfer desired. + */ +#define DP83867_ANAR_NP_MASK (0x8000U) +#define DP83867_ANAR_NP_SHIFT (15U) +#define DP83867_ANAR_NP_SET(x) (((uint16_t)(x) << DP83867_ANAR_NP_SHIFT) & DP83867_ANAR_NP_MASK) +#define DP83867_ANAR_NP_GET(x) (((uint16_t)(x) & DP83867_ANAR_NP_MASK) >> DP83867_ANAR_NP_SHIFT) + +/* + * RF (RW) + * + * Remote Fault: + * 1 = Advertises that this device has detected a Remote Fault. + * 0 = No Remote Fault detected. + */ +#define DP83867_ANAR_RF_MASK (0x2000U) +#define DP83867_ANAR_RF_SHIFT (13U) +#define DP83867_ANAR_RF_SET(x) (((uint16_t)(x) << DP83867_ANAR_RF_SHIFT) & DP83867_ANAR_RF_MASK) +#define DP83867_ANAR_RF_GET(x) (((uint16_t)(x) & DP83867_ANAR_RF_MASK) >> DP83867_ANAR_RF_SHIFT) + +/* + * ASM_DIR (RW) + * + * Asymmetric PAUSE Support for Full Duplex Links: + * The ASM_DIR bit indicates that asymmetric PAUSE is supported. + * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 + * Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution + * status is reported in PHYCR[13:12]. + * 1 = Advertise that the DTE (MAC) has implemented both the + * optional MAC control sublayer and the pause function as specified + * in clause 31 and annex 31B of 802.3u. + * 0 = No MAC based full duplex flow control. + */ +#define DP83867_ANAR_ASM_DIR_MASK (0x800U) +#define DP83867_ANAR_ASM_DIR_SHIFT (11U) +#define DP83867_ANAR_ASM_DIR_SET(x) (((uint16_t)(x) << DP83867_ANAR_ASM_DIR_SHIFT) & DP83867_ANAR_ASM_DIR_MASK) +#define DP83867_ANAR_ASM_DIR_GET(x) (((uint16_t)(x) & DP83867_ANAR_ASM_DIR_MASK) >> DP83867_ANAR_ASM_DIR_SHIFT) + +/* + * PAUSE (RW) + * + * PAUSE Support for Full Duplex Links: + * The PAUSE bit indicates that the device is capable of providing the + * symmetric PAUSE functions as defined in Annex 31B. + * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 + * Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution + * status is reported in PHYCR[13:12]. + * 1 = Advertise that the DTE (MAC) has implemented both the + * optional MAC control sublayer and the pause function as specified + * in clause 31 and annex 31B of 802.3u. + * 0 = No MAC based full duplex flow control. + */ +#define DP83867_ANAR_PAUSE_MASK (0x400U) +#define DP83867_ANAR_PAUSE_SHIFT (10U) +#define DP83867_ANAR_PAUSE_SET(x) (((uint16_t)(x) << DP83867_ANAR_PAUSE_SHIFT) & DP83867_ANAR_PAUSE_MASK) +#define DP83867_ANAR_PAUSE_GET(x) (((uint16_t)(x) & DP83867_ANAR_PAUSE_MASK) >> DP83867_ANAR_PAUSE_SHIFT) + +/* + * T4 (RO/P) + * + * 100BASE-T4 Support: + * 1 = 100BASE-T4 is supported by the local device. + * 0 = 100BASE-T4 not supported. + */ +#define DP83867_ANAR_T4_MASK (0x200U) +#define DP83867_ANAR_T4_SHIFT (9U) +#define DP83867_ANAR_T4_GET(x) (((uint16_t)(x) & DP83867_ANAR_T4_MASK) >> DP83867_ANAR_T4_SHIFT) + +/* + * TX_FD (STRAP, RW) + * + * 100BASE-TX Full Duplex Support: + * 1 = 100BASE-TX Full Duplex is supported by the local device. + * 0 = 100BASE-TX Full Duplex not supported. + */ +#define DP83867_ANAR_TX_FD_MASK (0x100U) +#define DP83867_ANAR_TX_FD_SHIFT (8U) +#define DP83867_ANAR_TX_FD_SET(x) (((uint16_t)(x) << DP83867_ANAR_TX_FD_SHIFT) & DP83867_ANAR_TX_FD_MASK) +#define DP83867_ANAR_TX_FD_GET(x) (((uint16_t)(x) & DP83867_ANAR_TX_FD_MASK) >> DP83867_ANAR_TX_FD_SHIFT) + +/* + * TX (STRAP, RW) + * + * 100BASE-TX Support: + * 1 = 100BASE-TX is supported by the local device. + * 0 = 100BASE-TX not supported. + */ +#define DP83867_ANAR_TX_MASK (0x80U) +#define DP83867_ANAR_TX_SHIFT (7U) +#define DP83867_ANAR_TX_SET(x) (((uint16_t)(x) << DP83867_ANAR_TX_SHIFT) & DP83867_ANAR_TX_MASK) +#define DP83867_ANAR_TX_GET(x) (((uint16_t)(x) & DP83867_ANAR_TX_MASK) >> DP83867_ANAR_TX_SHIFT) + +/* + * 10_FD (STRAP, RW) + * + * 10BASE-Te Full Duplex Support: + * 1 = 10BASE-Te Full Duplex is supported by the local device. + * 0 = 10BASE-Te Full Duplex not supported. + */ +#define DP83867_ANAR_10_FD_MASK (0x40U) +#define DP83867_ANAR_10_FD_SHIFT (6U) +#define DP83867_ANAR_10_FD_SET(x) (((uint16_t)(x) << DP83867_ANAR_10_FD_SHIFT) & DP83867_ANAR_10_FD_MASK) +#define DP83867_ANAR_10_FD_GET(x) (((uint16_t)(x) & DP83867_ANAR_10_FD_MASK) >> DP83867_ANAR_10_FD_SHIFT) + +/* + * 10BASETE_EN (STRAP, RW) + * + * 10BASE-Te Support: + * 1 = 10BASE-Te is supported by the local device. + * 0 = 10BASE-Te not supported. + */ +#define DP83867_ANAR_10BASETE_EN_MASK (0x20U) +#define DP83867_ANAR_10BASETE_EN_SHIFT (5U) +#define DP83867_ANAR_10BASETE_EN_SET(x) (((uint16_t)(x) << DP83867_ANAR_10BASETE_EN_SHIFT) & DP83867_ANAR_10BASETE_EN_MASK) +#define DP83867_ANAR_10BASETE_EN_GET(x) (((uint16_t)(x) & DP83867_ANAR_10BASETE_EN_MASK) >> DP83867_ANAR_10BASETE_EN_SHIFT) + +/* + * SELECTOR (RW) + * + * Protocol Selection Bits: + * These bits contain the binary encoded protocol selector supported + * by this port. <00001> indicates that this device supports IEEE + * 802.3u. + */ +#define DP83867_ANAR_SELECTOR_MASK (0x1FU) +#define DP83867_ANAR_SELECTOR_SHIFT (0U) +#define DP83867_ANAR_SELECTOR_SET(x) (((uint16_t)(x) << DP83867_ANAR_SELECTOR_SHIFT) & DP83867_ANAR_SELECTOR_MASK) +#define DP83867_ANAR_SELECTOR_GET(x) (((uint16_t)(x) & DP83867_ANAR_SELECTOR_MASK) >> DP83867_ANAR_SELECTOR_SHIFT) + +/* Bitfield definition for register: ANLPAR */ +/* + * NP (RO) + * + * Next Page Indication: + * 0 = Link Partner does not desire Next Page Transfer. + * 1 = Link Partner desires Next Page Transfer. + */ +#define DP83867_ANLPAR_NP_MASK (0x8000U) +#define DP83867_ANLPAR_NP_SHIFT (15U) +#define DP83867_ANLPAR_NP_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_NP_MASK) >> DP83867_ANLPAR_NP_SHIFT) + +/* + * ACK (RO) + * + * Acknowledge: + * 1 = Link Partner acknowledges reception of the ability data word. + * 0 = Not acknowledged. + * The Auto-Negotiation state machine will automatically control this bit + * based on the incoming FLP bursts. + */ +#define DP83867_ANLPAR_ACK_MASK (0x4000U) +#define DP83867_ANLPAR_ACK_SHIFT (14U) +#define DP83867_ANLPAR_ACK_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_ACK_MASK) >> DP83867_ANLPAR_ACK_SHIFT) + +/* + * RF (RO) + * + * Remote Fault: + * 1 = Remote Fault indicated by Link Partner. + * 0 = No Remote Fault indicated by Link Partner. + */ +#define DP83867_ANLPAR_RF_MASK (0x2000U) +#define DP83867_ANLPAR_RF_SHIFT (13U) +#define DP83867_ANLPAR_RF_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_RF_MASK) >> DP83867_ANLPAR_RF_SHIFT) + +/* + * ASM_DIR (RO) + * + * ASYMMETRIC PAUSE: + * 1 = Asymmetric pause is supported by the Link Partner. + * 0 = Asymmetric pause is not supported by the Link Partner. + */ +#define DP83867_ANLPAR_ASM_DIR_MASK (0x800U) +#define DP83867_ANLPAR_ASM_DIR_SHIFT (11U) +#define DP83867_ANLPAR_ASM_DIR_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_ASM_DIR_MASK) >> DP83867_ANLPAR_ASM_DIR_SHIFT) + +/* + * PAUSE (RO) + * + * PAUSE: + * 1 = Pause function is supported by the Link Partner. + * 0 = Pause function is not supported by the Link Partner. + */ +#define DP83867_ANLPAR_PAUSE_MASK (0x400U) +#define DP83867_ANLPAR_PAUSE_SHIFT (10U) +#define DP83867_ANLPAR_PAUSE_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_PAUSE_MASK) >> DP83867_ANLPAR_PAUSE_SHIFT) + +/* + * T4 (RO) + * + * 100BASE-T4 Support: + * 1 = 100BASE-T4 is supported by the Link Partner. + * 0 = 100BASE-T4 not supported by the Link Partner. + */ +#define DP83867_ANLPAR_T4_MASK (0x200U) +#define DP83867_ANLPAR_T4_SHIFT (9U) +#define DP83867_ANLPAR_T4_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_T4_MASK) >> DP83867_ANLPAR_T4_SHIFT) + +/* + * TX_FD (RO) + * + * 100BASE-TX Full Duplex Support: + * 1 = 100BASE-TX Full Duplex is supported by the Link Partner. + * 0 = 100BASE-TX Full Duplex not supported by the Link Partner. + */ +#define DP83867_ANLPAR_TX_FD_MASK (0x100U) +#define DP83867_ANLPAR_TX_FD_SHIFT (8U) +#define DP83867_ANLPAR_TX_FD_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_TX_FD_MASK) >> DP83867_ANLPAR_TX_FD_SHIFT) + +/* + * TX (RO) + * + * 100BASE-TX Support: + * 1 = 100BASE-TX is supported by the Link Partner. + * 0 = 100BASE-TX not supported by the Link Partner. + */ +#define DP83867_ANLPAR_TX_MASK (0x80U) +#define DP83867_ANLPAR_TX_SHIFT (7U) +#define DP83867_ANLPAR_TX_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_TX_MASK) >> DP83867_ANLPAR_TX_SHIFT) + +/* + * 10_FD (RO) + * + * 10BASE-Te Full Duplex Support: + * 1 = 10BASE-Te Full Duplex is supported by the Link Partner. + * 0 = 10BASE-Te Full Duplex not supported by the Link Partner. + */ +#define DP83867_ANLPAR_10_FD_MASK (0x40U) +#define DP83867_ANLPAR_10_FD_SHIFT (6U) +#define DP83867_ANLPAR_10_FD_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_10_FD_MASK) >> DP83867_ANLPAR_10_FD_SHIFT) + +/* + * 10 (RO) + * + * 10BASE-Te Support: + * 1 = 10BASE-Te is supported by the Link Partner. + * 0 = 10BASE-Te not supported by the Link Partner. + */ +#define DP83867_ANLPAR_10_MASK (0x20U) +#define DP83867_ANLPAR_10_SHIFT (5U) +#define DP83867_ANLPAR_10_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_10_MASK) >> DP83867_ANLPAR_10_SHIFT) + +/* + * SELECTOR (RO) + * + * Protocol Selection Bits: + * Link Partner's binary encoded protocol selector. + */ +#define DP83867_ANLPAR_SELECTOR_MASK (0x1FU) +#define DP83867_ANLPAR_SELECTOR_SHIFT (0U) +#define DP83867_ANLPAR_SELECTOR_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_SELECTOR_MASK) >> DP83867_ANLPAR_SELECTOR_SHIFT) + +/* Bitfield definition for register: ANER */ +/* + * RX_NEXT_PAGE_LOC_ABLE (RO) + * + * Receive Next Page Location Able: + * 1 = Received Next Page storage location is specified by bit 6.5. + * 0 = Received Next Page storage location is not specified by bit 6.5. + */ +#define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_MASK (0x40U) +#define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_SHIFT (6U) +#define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_MASK) >> DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_SHIFT) + +/* + * RX_NEXT_PAGE_STOR_LOC (RO) + * + * Receive Next Page Storage Location: + * 1 = Link Partner Next Pages are stored in register 8. + * 0 = Link Partner Next Pages are stored in register 5. + */ +#define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_MASK (0x20U) +#define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_SHIFT (5U) +#define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_GET(x) (((uint16_t)(x) & DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_MASK) >> DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_SHIFT) + +/* + * PDF (RO) + * + * Parallel Detection Fault: + * 1 = A fault has been detected via the Parallel Detection function. + * 0 = A fault has not been detected. + */ +#define DP83867_ANER_PDF_MASK (0x10U) +#define DP83867_ANER_PDF_SHIFT (4U) +#define DP83867_ANER_PDF_GET(x) (((uint16_t)(x) & DP83867_ANER_PDF_MASK) >> DP83867_ANER_PDF_SHIFT) + +/* + * LP_NP_ABLE (RO) + * + * Link Partner Next Page Able: + * 1 = Link Partner does support Next Page. + * 0 = Link Partner does not support Next Page. + */ +#define DP83867_ANER_LP_NP_ABLE_MASK (0x8U) +#define DP83867_ANER_LP_NP_ABLE_SHIFT (3U) +#define DP83867_ANER_LP_NP_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_LP_NP_ABLE_MASK) >> DP83867_ANER_LP_NP_ABLE_SHIFT) + +/* + * NP_ABLE (RO/P) + * + * Next Page Able: + * 1 = Indicates local device is able to send additional Next Pages. + */ +#define DP83867_ANER_NP_ABLE_MASK (0x4U) +#define DP83867_ANER_NP_ABLE_SHIFT (2U) +#define DP83867_ANER_NP_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_NP_ABLE_MASK) >> DP83867_ANER_NP_ABLE_SHIFT) + +/* + * PAGE_RX (RO/COR) + * + * Link Code Word Page Received: + * 1 = Link Code Word has been received, cleared on a read. + * 0 = Link Code Word has not been received. + */ +#define DP83867_ANER_PAGE_RX_MASK (0x2U) +#define DP83867_ANER_PAGE_RX_SHIFT (1U) +#define DP83867_ANER_PAGE_RX_GET(x) (((uint16_t)(x) & DP83867_ANER_PAGE_RX_MASK) >> DP83867_ANER_PAGE_RX_SHIFT) + +/* + * LP_AN_ABLE (RO) + * + * Link Partner Auto-Negotiation Able: + * 1 = Indicates that the Link Partner supports Auto-Negotiation. + * 0 = Indicates that the Link Partner does not support Auto- + * Negotiation. + */ +#define DP83867_ANER_LP_AN_ABLE_MASK (0x1U) +#define DP83867_ANER_LP_AN_ABLE_SHIFT (0U) +#define DP83867_ANER_LP_AN_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_LP_AN_ABLE_MASK) >> DP83867_ANER_LP_AN_ABLE_SHIFT) + +/* Bitfield definition for register: ANNPTR */ +/* + * NP (RW) + * + * Next Page Indication: + * 0 = No other Next Page Transfer desired. + * 1 = Another Next Page desired. + */ +#define DP83867_ANNPTR_NP_MASK (0x8000U) +#define DP83867_ANNPTR_NP_SHIFT (15U) +#define DP83867_ANNPTR_NP_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_NP_SHIFT) & DP83867_ANNPTR_NP_MASK) +#define DP83867_ANNPTR_NP_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_NP_MASK) >> DP83867_ANNPTR_NP_SHIFT) + +/* + * ACK (RO) + * + * Acknowledge: + * 1 = Acknowledge reception of link code word + * 0 = Do not acknowledge of link code word. + */ +#define DP83867_ANNPTR_ACK_MASK (0x4000U) +#define DP83867_ANNPTR_ACK_SHIFT (14U) +#define DP83867_ANNPTR_ACK_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_ACK_MASK) >> DP83867_ANNPTR_ACK_SHIFT) + +/* + * MP (RW) + * + * Message Page: + * 1 = Current page is a Message Page. + * 0 = Current page is an Unformatted Page. + */ +#define DP83867_ANNPTR_MP_MASK (0x2000U) +#define DP83867_ANNPTR_MP_SHIFT (13U) +#define DP83867_ANNPTR_MP_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_MP_SHIFT) & DP83867_ANNPTR_MP_MASK) +#define DP83867_ANNPTR_MP_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_MP_MASK) >> DP83867_ANNPTR_MP_SHIFT) + +/* + * ACK2 (RW) + * + * Acknowledge2: + * 1 = Will comply with message. + * 0 = Cannot comply with message. + * Acknowledge2 is used by the next page function to indicate that + * Local Device has the ability to comply with the message received. + */ +#define DP83867_ANNPTR_ACK2_MASK (0x1000U) +#define DP83867_ANNPTR_ACK2_SHIFT (12U) +#define DP83867_ANNPTR_ACK2_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_ACK2_SHIFT) & DP83867_ANNPTR_ACK2_MASK) +#define DP83867_ANNPTR_ACK2_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_ACK2_MASK) >> DP83867_ANNPTR_ACK2_SHIFT) + +/* + * TOG_TX (RO) + * + * Toggle: + * 1 = Value of toggle bit in previously transmitted Link Code Word + * was 0. + * 0 = Value of toggle bit in previously transmitted Link Code Word + * was 1. + * Toggle is used by the Arbitration function within Auto-Negotiation to + * ensure synchronization with the Link Partner during Next Page + * exchange. This bit shall always take the opposite value of the + * Toggle bit in the previously exchanged Link Code Word. + */ +#define DP83867_ANNPTR_TOG_TX_MASK (0x800U) +#define DP83867_ANNPTR_TOG_TX_SHIFT (11U) +#define DP83867_ANNPTR_TOG_TX_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_TOG_TX_MASK) >> DP83867_ANNPTR_TOG_TX_SHIFT) + +/* + * CODE (RW) + * + * Code: + * This field represents the code field of the next page transmission. If + * the MP bit is set (bit 13 of this register), then the code shall be + * interpreted as a "Message Page”, as defined in Annex 28C of IEEE + * 802.3u. Otherwise, the code shall be interpreted as an "Unformatted + * Page”, and the interpretation is application specific. + * The default value of the CODE represents a Null Page as defined in + * Annex 28C of IEEE 802.3u. + */ +#define DP83867_ANNPTR_CODE_MASK (0x7FFU) +#define DP83867_ANNPTR_CODE_SHIFT (0U) +#define DP83867_ANNPTR_CODE_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_CODE_SHIFT) & DP83867_ANNPTR_CODE_MASK) +#define DP83867_ANNPTR_CODE_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_CODE_MASK) >> DP83867_ANNPTR_CODE_SHIFT) + +/* Bitfield definition for register: ANNPRR */ +/* + * NP (RW) + * + * Next Page Indication: + * 0 = No other Next Page Transfer desired by the link partner. + * 1 = Another Next Page desired by the link partner. + */ +#define DP83867_ANNPRR_NP_MASK (0x8000U) +#define DP83867_ANNPRR_NP_SHIFT (15U) +#define DP83867_ANNPRR_NP_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_NP_SHIFT) & DP83867_ANNPRR_NP_MASK) +#define DP83867_ANNPRR_NP_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_NP_MASK) >> DP83867_ANNPRR_NP_SHIFT) + +/* + * ACK (RO) + * + * Acknowledge: + * 1 = Acknowledge reception of link code word by the link partner. + * 0 = Link partner does not acknowledge reception of link code word. + */ +#define DP83867_ANNPRR_ACK_MASK (0x4000U) +#define DP83867_ANNPRR_ACK_SHIFT (14U) +#define DP83867_ANNPRR_ACK_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_ACK_MASK) >> DP83867_ANNPRR_ACK_SHIFT) + +/* + * MP (RW) + * + * Message Page: + * 1 = Received page is a Message Page. + * 0 = Received page is an Unformatted Page. + */ +#define DP83867_ANNPRR_MP_MASK (0x2000U) +#define DP83867_ANNPRR_MP_SHIFT (13U) +#define DP83867_ANNPRR_MP_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_MP_SHIFT) & DP83867_ANNPRR_MP_MASK) +#define DP83867_ANNPRR_MP_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_MP_MASK) >> DP83867_ANNPRR_MP_SHIFT) + +/* + * ACK2 (RW) + * + * Acknowledge2: + * 1 = Link partner sets the ACK2 bit. + * 0 = Link partner coes not set the ACK2 bit. + * Acknowledge2 is used by the next page function to indicate that link + * partner has the ability to comply with the message received. + */ +#define DP83867_ANNPRR_ACK2_MASK (0x1000U) +#define DP83867_ANNPRR_ACK2_SHIFT (12U) +#define DP83867_ANNPRR_ACK2_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_ACK2_SHIFT) & DP83867_ANNPRR_ACK2_MASK) +#define DP83867_ANNPRR_ACK2_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_ACK2_MASK) >> DP83867_ANNPRR_ACK2_SHIFT) + +/* + * TOG_TX (RO) + * + * Toggle: + * 1 = Value of toggle bit in previously transmitted Link Code Word + * was 0. + * 0 = Value of toggle bit in previously transmitted Link Code Word + * was 1. + * Toggle is used by the Arbitration function within Auto-Negotiation to + * ensure synchronization with the Link Partner during Next Page + * exchange. This bit shall always take the opposite value of the + * Toggle bit in the previously exchanged Link Code Word. + */ +#define DP83867_ANNPRR_TOG_TX_MASK (0x800U) +#define DP83867_ANNPRR_TOG_TX_SHIFT (11U) +#define DP83867_ANNPRR_TOG_TX_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_TOG_TX_MASK) >> DP83867_ANNPRR_TOG_TX_SHIFT) + +/* + * CODE (RW) + * + * Code: + * This field represents the code field of the next page transmission. If + * the MP bit is set (bit 13 of this register), then the code shall be + * interpreted as a "Message Page”, as defined in Annex 28C of IEEE + * 802.3u. Otherwise, the code shall be interpreted as an "Unformatted + * Page”, and the interpretation is application specific. + * The default value of the CODE represents a Null Page as defined in + * Annex 28C of IEEE 802.3u. + */ +#define DP83867_ANNPRR_CODE_MASK (0x7FFU) +#define DP83867_ANNPRR_CODE_SHIFT (0U) +#define DP83867_ANNPRR_CODE_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_CODE_SHIFT) & DP83867_ANNPRR_CODE_MASK) +#define DP83867_ANNPRR_CODE_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_CODE_MASK) >> DP83867_ANNPRR_CODE_SHIFT) + +/* Bitfield definition for register: CFG1 */ +/* + * TEST_MODE (RW) + * + * Test Mode Select: + * 111 = Test Mode 7 - Repetitive {Pulse, 63 zeros} + * 110 = Test Mode 6 - Repetitive 0001 sequence + * 101 = Test Mode 5 - Scrambled MLT3 Idles + * 100 = Test Mode 4 - Transmit Distortion Test + * 011 = Test Mode 3 - Transmit Jitter Test (Slave Mode) + * 010 = Test Mode 2 - Transmit Jitter Test (Master Mode) + * 001 = Test Mode 1 - Transmit Waveform Test + * 000 = Normal Mode + */ +#define DP83867_CFG1_TEST_MODE_MASK (0xE000U) +#define DP83867_CFG1_TEST_MODE_SHIFT (13U) +#define DP83867_CFG1_TEST_MODE_SET(x) (((uint16_t)(x) << DP83867_CFG1_TEST_MODE_SHIFT) & DP83867_CFG1_TEST_MODE_MASK) +#define DP83867_CFG1_TEST_MODE_GET(x) (((uint16_t)(x) & DP83867_CFG1_TEST_MODE_MASK) >> DP83867_CFG1_TEST_MODE_SHIFT) + +/* + * MASTER_SLAVE_MANUAL_CONFIGURATION (RW) + * + * Enable Manual Master / Slave Configuration: + * 1 = Enable Manual Master/Slave Configuration control. + * 0 = Disable Manual Master/Slave Configuration control. + * Using the manual configuration feature may prevent the PHY from + * establishing link in 1000Base-T mode if a conflict with the link + * partner’s setting exists. + */ +#define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK (0x1000U) +#define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT (12U) +#define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SET(x) (((uint16_t)(x) << DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT) & DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK) +#define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_GET(x) (((uint16_t)(x) & DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK) >> DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT) + +/* + * MASTER_SLAVE_CONFIGURATION_VALUE (RW) + * + * Manual Master / Slave Configuration Value: + * 1 = Set PHY as MASTER when register 09h bit 12 = 1. + * 0 = Set PHY as SLAVE when register 09h bit 12 = 1. + * Using the manual configuration feature may prevent the PHY from + * establishing link in 1000Base-T mode if a conflict with the link + * partner’s setting exists. + */ +#define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK (0x800U) +#define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT (11U) +#define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SET(x) (((uint16_t)(x) << DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT) & DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK) +#define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_GET(x) (((uint16_t)(x) & DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK) >> DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT) +/* + * PORT_TYPE (RW) + * + * Advertise Device Type: Multi or single port: + * 1 = Multi-port device. + * 0 = Single-port device. + */ +#define DP83867_CFG1_PORT_TYPE_MASK (0x400U) +#define DP83867_CFG1_PORT_TYPE_SHIFT (10U) +#define DP83867_CFG1_PORT_TYPE_SET(x) (((uint16_t)(x) << DP83867_CFG1_PORT_TYPE_SHIFT) & DP83867_CFG1_PORT_TYPE_MASK) +#define DP83867_CFG1_PORT_TYPE_GET(x) (((uint16_t)(x) & DP83867_CFG1_PORT_TYPE_MASK) >> DP83867_CFG1_PORT_TYPE_SHIFT) +/* + * 1000BASE_T_FULL_DUPLEX (RW) + * + * Advertise 1000BASE-T Full Duplex Capable: + * 1 = Advertise 1000Base-T Full Duplex ability. + * 0 = Do not advertise 1000Base-T Full Duplex ability. + */ +#define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK (0x200U) +#define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT (9U) +#define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SET(x) (((uint16_t)(x) << DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT) & DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK) +#define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT) -/* Bitfield definition for register: PHYID1 */ /* - * OUI_MSB (RO) + * 1000BASE_T_HALF_DUPLEX (RW) * - * Organizationally Unique Identifier Bit 3:18. - * Always 0000000000011100. + * Advertise 1000BASE-T Half Duplex Capable: + * 1 = Advertise 1000Base-T Half Duplex ability. + * 0 = Do not advertise 1000Base-T Half Duplex ability. */ -#define DP83867_PHYID1_OUI_MSB_MASK (0xFFFFU) -#define DP83867_PHYID1_OUI_MSB_SHIFT (0U) -#define DP83867_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & DP83867_PHYID1_OUI_MSB_MASK) >> DP83867_PHYID1_OUI_MSB_SHIFT) +#define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK (0x100U) +#define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT (8U) +#define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SET(x) (((uint16_t)(x) << DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT) & DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK) +#define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT) -/* Bitfield definition for register: PHYID2 */ /* - * OUI_LSB (RO) + * TDR_AUTO_RUN (RW) * - * Organizationally Unique Identifier Bit 19:24. - * Always 110010. + * Automatic TDR on Link Down: + * 1 = Enable execution of TDR procedure after link down event. + * 0 = Disable automatic execution of TDR. */ -#define DP83867_PHYID2_OUI_MSB_MASK (0xFC00U) -#define DP83867_PHYID2_OUI_MSB_SHIFT (10U) -#define DP83867_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & DP83867_PHYID2_OUI_MSB_MASK) >> DP83867_PHYID2_OUI_MSB_SHIFT) +#define DP83867_CFG1_TDR_AUTO_RUN_MASK (0x80U) +#define DP83867_CFG1_TDR_AUTO_RUN_SHIFT (7U) +#define DP83867_CFG1_TDR_AUTO_RUN_SET(x) (((uint16_t)(x) << DP83867_CFG1_TDR_AUTO_RUN_SHIFT) & DP83867_CFG1_TDR_AUTO_RUN_MASK) +#define DP83867_CFG1_TDR_AUTO_RUN_GET(x) (((uint16_t)(x) & DP83867_CFG1_TDR_AUTO_RUN_MASK) >> DP83867_CFG1_TDR_AUTO_RUN_SHIFT) -/* Bitfield definition for register: RGMIICTL */ +/* Bitfield definition for register: STS1 */ /* - * RGMII_EN (RW) + * MASTER_SLAVE_CONFIGURATION_FAULT (RO, LH, COR) * - * RGMII Enable: - * 1 = Enable RGMII interface. - * 0 = Disable RGMII interface + * Master / Slave Manual Configuration Fault Detected: + * 1 = Manual Master/Slave Configuration fault detected. + * 0 = No Manual Master/Slave Configuration fault detected. */ -#define DP83867_RGMIICTL_RGMII_EN_MASK (0x80) -#define DP83867_RGMIICTL_RGMII_EN_SHIFT (7U) -#define DP83867_RGMIICTL_RGMII_EN_SET(x) (((uint32_t)(x) << DP83867_RGMIICTL_RGMII_EN_SHIFT) & DP83867_RGMIICTL_RGMII_EN_MASK) -#define DP83867_RGMIICTL_RGMII_EN_GET(x) (((uint32_t)(x) & DP83867_RGMIICTL_RGMII_EN_SHIFT) >> DP83867_RGMIICTL_RGMII_EN_MASK) +#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_MASK (0x8000U) +#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_SHIFT (15U) +#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_GET(x) (((uint16_t)(x) & DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_MASK) >> DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_SHIFT) + +/* + * MASTER_SLAVE_CONFIGURATION_RESOLUTION (RO) + * + * Master / Slave Configuration Results: + * 1 = Configuration resolved to MASTER. + * 0 = Configuration resolved to SLAVE. + */ +#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_MASK (0x4000U) +#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_SHIFT (14U) +#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_GET(x) (((uint16_t)(x) & DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_MASK) >> DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_SHIFT) + +/* + * LOCAL_RECEIVER_STATUS (RO) + * + * Local Receiver Status: + * 1 = Local receiver is OK. + * 0 = Local receiver is not OK. + */ +#define DP83867_STS1_LOCAL_RECEIVER_STATUS_MASK (0x2000U) +#define DP83867_STS1_LOCAL_RECEIVER_STATUS_SHIFT (13U) +#define DP83867_STS1_LOCAL_RECEIVER_STATUS_GET(x) (((uint16_t)(x) & DP83867_STS1_LOCAL_RECEIVER_STATUS_MASK) >> DP83867_STS1_LOCAL_RECEIVER_STATUS_SHIFT) + +/* + * REMOTE_RECEIVER_STATUS (RO) + * + * Remote Receiver Status: + * 1 = Remote receiver is OK. + * 0 = Remote receiver is not OK. + */ +#define DP83867_STS1_REMOTE_RECEIVER_STATUS_MASK (0x1000U) +#define DP83867_STS1_REMOTE_RECEIVER_STATUS_SHIFT (12U) +#define DP83867_STS1_REMOTE_RECEIVER_STATUS_GET(x) (((uint16_t)(x) & DP83867_STS1_REMOTE_RECEIVER_STATUS_MASK) >> DP83867_STS1_REMOTE_RECEIVER_STATUS_SHIFT) + +/* + * 1000BASE_T_FULL_DUPLEX (RO) + * + * Link Partner 1000BASE-T Full Duplex Capable: + * 1 = Link Partner capable of 1000Base-T Full Duplex. + * 0 = Link partner not capable of 1000Base-T Full Duplex. + */ +#define DP83867_STS1_1000BASE_T_FULL_DUPLEX_MASK (0x800U) +#define DP83867_STS1_1000BASE_T_FULL_DUPLEX_SHIFT (11U) +#define DP83867_STS1_1000BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_STS1_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_STS1_1000BASE_T_FULL_DUPLEX_SHIFT) + +/* + * 1000BASE_T_HALF_DUPLEX (RO) + * + * Link Partner 1000BASE-T Half Duplex Capable: + * 1 = Link Partner capable of 1000Base-T Half Duplex. + * 0 = Link partner not capable of 1000Base-T Half Duplex. + */ +#define DP83867_STS1_1000BASE_T_HALF_DUPLEX_MASK (0x400U) +#define DP83867_STS1_1000BASE_T_HALF_DUPLEX_SHIFT (10U) +#define DP83867_STS1_1000BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_STS1_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_STS1_1000BASE_T_HALF_DUPLEX_SHIFT) + +/* + * IDLE_ERROR_COUNTER (RO,COR) + * + * 1000BASE-T Idle Error Counter + */ +#define DP83867_STS1_IDLE_ERROR_COUNTER_MASK (0xFFU) +#define DP83867_STS1_IDLE_ERROR_COUNTER_SHIFT (0U) +#define DP83867_STS1_IDLE_ERROR_COUNTER_GET(x) (((uint16_t)(x) & DP83867_STS1_IDLE_ERROR_COUNTER_MASK) >> DP83867_STS1_IDLE_ERROR_COUNTER_SHIFT) + +/* Bitfield definition for register: REGCR */ +/* + * FUNCTION (RW) + * + * 00 = Address + * 01 = Data, no post increment + * 10 = Data, post increment on read and write + * 11 = Data, post increment on write only + */ +#define DP83867_REGCR_FUNCTION_MASK (0xC000U) +#define DP83867_REGCR_FUNCTION_SHIFT (14U) +#define DP83867_REGCR_FUNCTION_SET(x) (((uint16_t)(x) << DP83867_REGCR_FUNCTION_SHIFT) & DP83867_REGCR_FUNCTION_MASK) +#define DP83867_REGCR_FUNCTION_GET(x) (((uint16_t)(x) & DP83867_REGCR_FUNCTION_MASK) >> DP83867_REGCR_FUNCTION_SHIFT) + +/* + * DEVAD (RW) + * + * Device Address: In general, these bits [4:0] are the device address + * DEVAD that directs any accesses of ADDAR register (0x000E) to + * the appropriate MMD. Specifically, the DP83867 uses the vendor + * specific DEVAD [4:0] = 11111 for accesses. All accesses through + * registers REGCR and ADDAR should use this DEVAD. + * Transactions with other DEVAD are ignored. + */ +#define DP83867_REGCR_DEVAD_MASK (0x1FU) +#define DP83867_REGCR_DEVAD_SHIFT (0U) +#define DP83867_REGCR_DEVAD_SET(x) (((uint16_t)(x) << DP83867_REGCR_DEVAD_SHIFT) & DP83867_REGCR_DEVAD_MASK) +#define DP83867_REGCR_DEVAD_GET(x) (((uint16_t)(x) & DP83867_REGCR_DEVAD_MASK) >> DP83867_REGCR_DEVAD_SHIFT) + +/* Bitfield definition for register: ADDAR */ +/* + * ADDRESS_OR_DATA_REGISTER (RW) + * + * If REGCR register 15:14 = 00, holds the MMD DEVAD's address + * register, otherwise holds the MMD DEVAD's data register + */ +#define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK (0xFFFFU) +#define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT (0U) +#define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SET(x) (((uint16_t)(x) << DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT) & DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK) +#define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_GET(x) (((uint16_t)(x) & DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK) >> DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT) + +/* Bitfield definition for register: 1KSCR */ +/* + * 1000BASE_X_FULL_DUPLEX (RO/P) + * + * 1000BASE-X Full Duplex Support: + * 1 = 1000BASE-X Full Duplex is supported by the local device. + * 0 = 1000BASE-X Full Duplex is not supported by the local device. + */ +#define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_MASK (0x8000U) +#define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_SHIFT (15U) +#define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_SHIFT) + +/* + * 1000BASE_X_HALF_DUPLEX (RO/P) + * + * 1000BASE-X Half Duplex Support: + * 1 = 1000BASE-X Half Duplex is supported by the local device. + * 0 = 1000BASE-X Half Duplex is not supported by the local device. + */ +#define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_MASK (0x4000U) +#define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_SHIFT (14U) +#define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_SHIFT) + +/* + * 1000BASE_T_FULL_DUPLEX (RO/P) + * + * 1000BASE-T Full Duplex Support: + * 1 = 1000BASE-T Full Duplex is supported by the local device. + * 0 = 1000BASE-T Full Duplex is not supported by the local device. + */ +#define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_MASK (0x2000U) +#define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_SHIFT (13U) +#define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_SHIFT) + +/* + * 1000BASE_T_HALF_DUPLEX (RO/P) + * + * 1000BASE-T Half Duplex Support: + * 1 = 1000BASE-T Half Duplex is supported by the local device. + * 0 = 1000BASE-T Half Duplex is not supported by the local device. + */ +#define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_MASK (0x1000U) +#define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_SHIFT (12U) +#define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_SHIFT) + +/* Bitfield definition for register: PHYCR */ +/* + * TX_FIFO_DEPTH (RW) + * + * TX FIFO Depth: + * 11 = 8 bytes/nibbles (1000Mbps/Other Speeds) + * 10 = 6 bytes/nibbles (1000Mbps/Other Speeds) + * 01 = 4 bytes/nibbles (1000Mbps/Other Speeds) + * 00 = 3 bytes/nibbles (1000Mbps/Other Speeds) + * Note: FIFO is enabled only in the following modes: + * 1000BaseT + GMII + * 10BaseT/100BaseTX/1000BaseT + SGMII + */ +#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK (0xC000U) +#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT (14U) +#define DP83867_PHYCR_TX_FIFO_DEPTH_SET(x) (((uint16_t)(x) << DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT) & DP83867_PHYCR_TX_FIFO_DEPTH_MASK) +#define DP83867_PHYCR_TX_FIFO_DEPTH_GET(x) (((uint16_t)(x) & DP83867_PHYCR_TX_FIFO_DEPTH_MASK) >> DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT) + +/* + * RX_FIFO_DEPTH (RW) + * + * RX FIFO Depth: + * 11 = 8 bytes/nibbles (1000 Mbps/Other Speeds) + * 10 = 6 bytes/nibbles (1000 Mbps/Other Speeds) + * 01 = 4 bytes/nibbles (1000 Mbps/Other Speeds) + * 00 = 3 bytes/nibbles (1000 Mbps/Other Speeds) + * Note: FIFO is enabled only in SGMII + */ +#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK (0x3000U) +#define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT (12U) +#define DP83867_PHYCR_RX_FIFO_DEPTH_SET(x) (((uint16_t)(x) << DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) & DP83867_PHYCR_RX_FIFO_DEPTH_MASK) +#define DP83867_PHYCR_RX_FIFO_DEPTH_GET(x) (((uint16_t)(x) & DP83867_PHYCR_RX_FIFO_DEPTH_MASK) >> DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) + +/* + * SGMII_EN (RW) + * + * SGMII Enable: + * 1 = Enable SGMII + * 0 = Disable SGMII + */ +#define DP83867_PHYCR_SGMII_EN_MASK (0x800U) +#define DP83867_PHYCR_SGMII_EN_SHIFT (11U) +#define DP83867_PHYCR_SGMII_EN_SET(x) (((uint16_t)(x) << DP83867_PHYCR_SGMII_EN_SHIFT) & DP83867_PHYCR_SGMII_EN_MASK) +#define DP83867_PHYCR_SGMII_EN_GET(x) (((uint16_t)(x) & DP83867_PHYCR_SGMII_EN_MASK) >> DP83867_PHYCR_SGMII_EN_SHIFT) + +/* + * FORCE_LINK_GOOD (RW) + * + * Force Link Good: + * 1 = Force link good according to the selected speed. + * 0 = Normal operation + */ +#define DP83867_PHYCR_FORCE_LINK_GOOD_MASK (0x400U) +#define DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT (10U) +#define DP83867_PHYCR_FORCE_LINK_GOOD_SET(x) (((uint16_t)(x) << DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT) & DP83867_PHYCR_FORCE_LINK_GOOD_MASK) +#define DP83867_PHYCR_FORCE_LINK_GOOD_GET(x) (((uint16_t)(x) & DP83867_PHYCR_FORCE_LINK_GOOD_MASK) >> DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT) + +/* + * POWER_SAVE_MODE (RW) + * + * Power-Saving Modes: + * 11 = Passive Sleep mode: Power down all digital and analog + * blocks. + * 10 =Active Sleep mode: Power down all digital and analog blocks. + * Automatic power-up is performed when link partner is detected. Link + * pulses are transmitted approximately once per 1.4 Sec in this mode + * to wake up any potential link partner. + * 01 = IEEE mode: power down all digital and analog blocks. + * Note: If DISABLE_CLK_125 (bit [4]of this register) is set to zero, the + * PLL is also powered down. + * 00 = Normal mode + */ +#define DP83867_PHYCR_POWER_SAVE_MODE_MASK (0x300U) +#define DP83867_PHYCR_POWER_SAVE_MODE_SHIFT (8U) +#define DP83867_PHYCR_POWER_SAVE_MODE_SET(x) (((uint16_t)(x) << DP83867_PHYCR_POWER_SAVE_MODE_SHIFT) & DP83867_PHYCR_POWER_SAVE_MODE_MASK) +#define DP83867_PHYCR_POWER_SAVE_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYCR_POWER_SAVE_MODE_MASK) >> DP83867_PHYCR_POWER_SAVE_MODE_SHIFT) + +/* + * DEEP_POWER_DOWN_EN (RW) + * + * Deep power-down mode enable + * 1 = When power down is initiated through assertion of the external + * power-down pin or through the POWER_DOWN bit in the BMCR, + * the device enters a deep power-down mode. + * 0 = Normal operation. + */ +#define DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK (0x80U) +#define DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT (7U) +#define DP83867_PHYCR_DEEP_POWER_DOWN_EN_SET(x) (((uint16_t)(x) << DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT) & DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK) +#define DP83867_PHYCR_DEEP_POWER_DOWN_EN_GET(x) (((uint16_t)(x) & DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK) >> DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT) + +/* + * MDI_CROSSOVER (RW) + * + * MDI Crosssover Mode: + * 1x = Enable automatic crossover + * 01 = Manual MDI-X configuration + * 00 = Manual MDI configuration + */ +#define DP83867_PHYCR_MDI_CROSSOVER_MASK (0x60U) +#define DP83867_PHYCR_MDI_CROSSOVER_SHIFT (5U) +#define DP83867_PHYCR_MDI_CROSSOVER_SET(x) (((uint16_t)(x) << DP83867_PHYCR_MDI_CROSSOVER_SHIFT) & DP83867_PHYCR_MDI_CROSSOVER_MASK) +#define DP83867_PHYCR_MDI_CROSSOVER_GET(x) (((uint16_t)(x) & DP83867_PHYCR_MDI_CROSSOVER_MASK) >> DP83867_PHYCR_MDI_CROSSOVER_SHIFT) + +/* + * DISABLE_CLK_125 (RW) + * + * Disable 125MHz Clock: + * This bit may be used in conjunction with POWER_SAVE_MODE + * (bits 9:8 of this register). + * 1 = Disable CLK125. + * 0 = Enable CLK125. + */ +#define DP83867_PHYCR_DISABLE_CLK_125_MASK (0x10U) +#define DP83867_PHYCR_DISABLE_CLK_125_SHIFT (4U) +#define DP83867_PHYCR_DISABLE_CLK_125_SET(x) (((uint16_t)(x) << DP83867_PHYCR_DISABLE_CLK_125_SHIFT) & DP83867_PHYCR_DISABLE_CLK_125_MASK) +#define DP83867_PHYCR_DISABLE_CLK_125_GET(x) (((uint16_t)(x) & DP83867_PHYCR_DISABLE_CLK_125_MASK) >> DP83867_PHYCR_DISABLE_CLK_125_SHIFT) + +/* + * STANDBY_MODE (RW) + * + * Standby Mode: + * 1 = Enable standby mode. Digital and analog circuitry are powered + * up, but no link can be established. + * 0 = Normal operation. + */ +#define DP83867_PHYCR_STANDBY_MODE_MASK (0x4U) +#define DP83867_PHYCR_STANDBY_MODE_SHIFT (2U) +#define DP83867_PHYCR_STANDBY_MODE_SET(x) (((uint16_t)(x) << DP83867_PHYCR_STANDBY_MODE_SHIFT) & DP83867_PHYCR_STANDBY_MODE_MASK) +#define DP83867_PHYCR_STANDBY_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYCR_STANDBY_MODE_MASK) >> DP83867_PHYCR_STANDBY_MODE_SHIFT) + +/* + * LINE_DRIVER_INV_EN (RW) + * + * Line Driver Inversion Enable: + * 1 = Invert Line Driver Transmission. + * 0 = Normal operation. + */ +#define DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK (0x2U) +#define DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT (1U) +#define DP83867_PHYCR_LINE_DRIVER_INV_EN_SET(x) (((uint16_t)(x) << DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT) & DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK) +#define DP83867_PHYCR_LINE_DRIVER_INV_EN_GET(x) (((uint16_t)(x) & DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK) >> DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT) + +/* + * DISABLE_JABBER (RW) + * + * Disable Jabber + * 1 = Disable Jabber function. + * 0 = Enable Jabber function. + */ +#define DP83867_PHYCR_DISABLE_JABBER_MASK (0x1U) +#define DP83867_PHYCR_DISABLE_JABBER_SHIFT (0U) +#define DP83867_PHYCR_DISABLE_JABBER_SET(x) (((uint16_t)(x) << DP83867_PHYCR_DISABLE_JABBER_SHIFT) & DP83867_PHYCR_DISABLE_JABBER_MASK) +#define DP83867_PHYCR_DISABLE_JABBER_GET(x) (((uint16_t)(x) & DP83867_PHYCR_DISABLE_JABBER_MASK) >> DP83867_PHYCR_DISABLE_JABBER_SHIFT) + +/* Bitfield definition for register: PHYSTS */ +/* + * SPEED_SELECTION (RO) + * + * Speed Select Status: + * These two bits indicate the speed of operation as determined by + * Auto-Negotiation or as set by manual configuration. + * 11 = Reserved + * 10 = 1000 Mbps + * 01 = 100 Mbps + * 00 = 10 Mbps + */ +#define DP83867_PHYSTS_SPEED_SELECTION_MASK (0xC000U) +#define DP83867_PHYSTS_SPEED_SELECTION_SHIFT (14U) +#define DP83867_PHYSTS_SPEED_SELECTION_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SPEED_SELECTION_MASK) >> DP83867_PHYSTS_SPEED_SELECTION_SHIFT) + +/* + * DUPLEX_MODE (RO) + * + * Duplex Mode Status: + * 1 = Full Duplex + * 0 = Half Duplex. + */ +#define DP83867_PHYSTS_DUPLEX_MODE_MASK (0x2000U) +#define DP83867_PHYSTS_DUPLEX_MODE_SHIFT (13U) +#define DP83867_PHYSTS_DUPLEX_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_DUPLEX_MODE_MASK) >> DP83867_PHYSTS_DUPLEX_MODE_SHIFT) + +/* + * PAGE_RECEIVED ( RO, LH, COR) + * + * Page Received: + * This bit is latched high and will be cleared upon a read. + * 1 = Page received. + * 0 = No page received. + */ +#define DP83867_PHYSTS_PAGE_RECEIVED_MASK (0x1000U) +#define DP83867_PHYSTS_PAGE_RECEIVED_SHIFT (12U) +#define DP83867_PHYSTS_PAGE_RECEIVED_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_PAGE_RECEIVED_MASK) >> DP83867_PHYSTS_PAGE_RECEIVED_SHIFT) + +/* + * SPEED_DUPLEX_RESOLVED (RO) + * + * Speed Duplex Resolution Status: + * 1 = Auto-Negotiation has completed or is disabled. + * 0 = Auto-Negotiation is enabled and has not completed. + */ +#define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_MASK (0x800U) +#define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_SHIFT (11U) +#define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_MASK) >> DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_SHIFT) + +/* + * LINK_STATUS (RO) + * + * Link Status: + * 1 = Link is up. + * 0 = Link is down. + */ +#define DP83867_PHYSTS_LINK_STATUS_MASK (0x400U) +#define DP83867_PHYSTS_LINK_STATUS_SHIFT (10U) +#define DP83867_PHYSTS_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_LINK_STATUS_MASK) >> DP83867_PHYSTS_LINK_STATUS_SHIFT) + +/* + * MDI_X_MODE_CD (RO) + * + * MDI/MDIX Resolution Status for C and D Line Driver Pairs: + * 1 = Resolved as MDIX + * 0 = Resolved as MDI. + */ +#define DP83867_PHYSTS_MDI_X_MODE_CD_MASK (0x200U) +#define DP83867_PHYSTS_MDI_X_MODE_CD_SHIFT (9U) +#define DP83867_PHYSTS_MDI_X_MODE_CD_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_MDI_X_MODE_CD_MASK) >> DP83867_PHYSTS_MDI_X_MODE_CD_SHIFT) + +/* + * MDI_X_MODE_AB (RO) + * + * MDI/MDIX Resolution Status for A and B Line Driver Pairs: + * 1 = Resolved as MDIX + * 0 = Resolved as MDI. + */ +#define DP83867_PHYSTS_MDI_X_MODE_AB_MASK (0x100U) +#define DP83867_PHYSTS_MDI_X_MODE_AB_SHIFT (8U) +#define DP83867_PHYSTS_MDI_X_MODE_AB_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_MDI_X_MODE_AB_MASK) >> DP83867_PHYSTS_MDI_X_MODE_AB_SHIFT) + +/* + * SPEED_OPT_STATUS (RO) + * + * Speed Optimization Status: + * 1 = Auto-Negotiation is currently being performed with Speed + * Optimization masking 1000BaseT abilities (Valid only during Auto- + * Negotiation). + * 0 = Auto-Negotiation is currently being performed without Speed + * Optimization. + */ +#define DP83867_PHYSTS_SPEED_OPT_STATUS_MASK (0x80U) +#define DP83867_PHYSTS_SPEED_OPT_STATUS_SHIFT (7U) +#define DP83867_PHYSTS_SPEED_OPT_STATUS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SPEED_OPT_STATUS_MASK) >> DP83867_PHYSTS_SPEED_OPT_STATUS_SHIFT) + +/* + * SLEEP_MODE (RO) + * + * Sleep Mode Status: + * 1 = Device currently in sleep mode. + * 0 = Device currently in active mode. + */ +#define DP83867_PHYSTS_SLEEP_MODE_MASK (0x40U) +#define DP83867_PHYSTS_SLEEP_MODE_SHIFT (6U) +#define DP83867_PHYSTS_SLEEP_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SLEEP_MODE_MASK) >> DP83867_PHYSTS_SLEEP_MODE_SHIFT) + +/* + * WIRE_CROSS (RO) + * + * Crossed Wire Indication: + * Indicates channel polarity in 1000BASE-T linked status. Bits [5:2] + * correspond to channels [D,C,B,A], respectively. + * 1 = Channel polarity is reversed. + * 0 = Channel polarity is normal. + */ +#define DP83867_PHYSTS_WIRE_CROSS_MASK (0x3CU) +#define DP83867_PHYSTS_WIRE_CROSS_SHIFT (2U) +#define DP83867_PHYSTS_WIRE_CROSS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_WIRE_CROSS_MASK) >> DP83867_PHYSTS_WIRE_CROSS_SHIFT) + +/* + * POLARITY_STATUS (RO) + * + * 10BASE-Te Polarity Status: + * 1 = Correct Polarity detected. + * 0 = Inverted Polarity detected. + */ +#define DP83867_PHYSTS_POLARITY_STATUS_MASK (0x2U) +#define DP83867_PHYSTS_POLARITY_STATUS_SHIFT (1U) +#define DP83867_PHYSTS_POLARITY_STATUS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_POLARITY_STATUS_MASK) >> DP83867_PHYSTS_POLARITY_STATUS_SHIFT) + +/* + * JABBER_DETECT (RO) + * + * Jabber Detect: This bit only has meaning in 10 Mbps mode. + * This bit is a duplicate of the Jabber Detect bit in the BMSR register, + * except that it is not cleared upon a read of the PHYSTS register. + * 1 = Jabber condition detected. + * 0 = No Jabber. + */ +#define DP83867_PHYSTS_JABBER_DETECT_MASK (0x1U) +#define DP83867_PHYSTS_JABBER_DETECT_SHIFT (0U) +#define DP83867_PHYSTS_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_JABBER_DETECT_MASK) >> DP83867_PHYSTS_JABBER_DETECT_SHIFT) + +/* Bitfield definition for register: MICR */ +/* + * AUTONEG_ERR_INT_EN (RW) + * + * Enable Auto-Negotiation Error Interrupt: + * 1 = Enable Auto-Negotiation Error interrupt. + * 0 = Disable Auto-Negotiation Error interrupt. + */ +#define DP83867_MICR_AUTONEG_ERR_INT_EN_MASK (0x8000U) +#define DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT (15U) +#define DP83867_MICR_AUTONEG_ERR_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT) & DP83867_MICR_AUTONEG_ERR_INT_EN_MASK) +#define DP83867_MICR_AUTONEG_ERR_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_AUTONEG_ERR_INT_EN_MASK) >> DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT) + +/* + * SPEED_CHNG_INT_EN (RW) + * + * Enable Speed Change Interrupt: + * 1 = Enable Speed Change interrupt. + * 0 = Disable Speed Change interrupt. + */ +#define DP83867_MICR_SPEED_CHNG_INT_EN_MASK (0x4000U) +#define DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT (14U) +#define DP83867_MICR_SPEED_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT) & DP83867_MICR_SPEED_CHNG_INT_EN_MASK) +#define DP83867_MICR_SPEED_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_SPEED_CHNG_INT_EN_MASK) >> DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT) + +/* + * DUPLEX_MODE_CHNG_INT_EN (RW) + * + * Enable Duplex Mode Change Interrupt: + * 1 = Enable Duplex Mode Change interrupt. + * 0 = Disable Duplex Mode Change interrupt. + */ +#define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK (0x2000U) +#define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT (13U) +#define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT) & DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK) +#define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK) >> DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT) + +/* + * PAGE_RECEIVED_INT_EN (RW) + * + * Enable Page Received Interrupt: + * 1 = Enable Page Received Interrupt. + * 0 = Disable Page Received Interrupt. + */ +#define DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK (0x1000U) +#define DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT (12U) +#define DP83867_MICR_PAGE_RECEIVED_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT) & DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK) +#define DP83867_MICR_PAGE_RECEIVED_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK) >> DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT) + +/* + * AUTONEG_COMP_INT_EN (RW) + * + * Enable Auto-Negotiation Complete Interrupt: + * 1 = Enable Auto-Negotiation Complete Interrupt. + * 0 = Disable Auto-Negotiation Complete Interrupt. + */ +#define DP83867_MICR_AUTONEG_COMP_INT_EN_MASK (0x800U) +#define DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT (11U) +#define DP83867_MICR_AUTONEG_COMP_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT) & DP83867_MICR_AUTONEG_COMP_INT_EN_MASK) +#define DP83867_MICR_AUTONEG_COMP_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_AUTONEG_COMP_INT_EN_MASK) >> DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT) + +/* + * LINK_STATUS_CHNG_INT_EN (RW) + * + * Enable Link Status Change Interrupt: + * 1 = Enable Link Status Change interrupt. + * 0 = Disable Link Status Change interrupt. + */ +#define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK (0x400U) +#define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT (10U) +#define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT) & DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK) +#define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK) >> DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT) + +/* + * FALSE_CARRIER_INT_EN (RW) + * + * Enable False Carrier Interrupt: + * 1 = Enable False Carrier interrupt. + * 0 = Disable False Carrier interrupt. + */ +#define DP83867_MICR_FALSE_CARRIER_INT_EN_MASK (0x100U) +#define DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT (8U) +#define DP83867_MICR_FALSE_CARRIER_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT) & DP83867_MICR_FALSE_CARRIER_INT_EN_MASK) +#define DP83867_MICR_FALSE_CARRIER_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_FALSE_CARRIER_INT_EN_MASK) >> DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT) + +/* + * MDI_CROSSOVER_CHNG_INT_EN (RW) + * + * Enable MDI Crossover Change Interrupt: + * 1 = Enable MDI Crossover Change interrupt. + * 0 = Disable MDI Crossover Change interrupt. + */ +#define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK (0x40U) +#define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT (6U) +#define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT) & DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK) +#define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK) >> DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT) + +/* + * SPEED_OPT_EVENT_INT_EN (RW) + * + * Enable Speed Optimization Event Interrupt: + * 1 = Enable Speed Optimization Event Interrupt. + * 0 = Disable Speed Optimization Event Interrupt. + */ +#define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK (0x20U) +#define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT (5U) +#define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT) & DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK) +#define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK) >> DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT) + +/* + * SLEEP_MODE_CHNG_INT_EN (RW) + * + * Enable Sleep Mode Change Interrupt: + * 1 = Enable Sleep Mode Change Interrupt. + * 0 = Disable Sleep Mode Change Interrupt. + */ +#define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK (0x10U) +#define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT (4U) +#define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT) & DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK) +#define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK) >> DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT) + +/* + * WOL_INT_EN (RW) + * + * Enable Wake-on-LAN Interrupt: + * 1 = Enable Wake-on-LAN Interrupt. + * 0 = Disable Wake-on-LAN Interrupt. + */ +#define DP83867_MICR_WOL_INT_EN_MASK (0x8U) +#define DP83867_MICR_WOL_INT_EN_SHIFT (3U) +#define DP83867_MICR_WOL_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_WOL_INT_EN_SHIFT) & DP83867_MICR_WOL_INT_EN_MASK) +#define DP83867_MICR_WOL_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_WOL_INT_EN_MASK) >> DP83867_MICR_WOL_INT_EN_SHIFT) + +/* + * XGMII_ERR_INT_EN (RW) + * + * Enable xGMII Error Interrupt: + * 1 = Enable xGMII Error Interrupt. + * 0 = Disable xGMII Error Interrupt. + */ +#define DP83867_MICR_XGMII_ERR_INT_EN_MASK (0x4U) +#define DP83867_MICR_XGMII_ERR_INT_EN_SHIFT (2U) +#define DP83867_MICR_XGMII_ERR_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_XGMII_ERR_INT_EN_SHIFT) & DP83867_MICR_XGMII_ERR_INT_EN_MASK) +#define DP83867_MICR_XGMII_ERR_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_XGMII_ERR_INT_EN_MASK) >> DP83867_MICR_XGMII_ERR_INT_EN_SHIFT) + +/* + * POLARITY_CHNG_INT_EN (RW) + * + * Enable Polarity Change Interrupt: + * 1 = Enable Polarity Change interrupt. + * 0 = Disable Polarity Change interrupt. + */ +#define DP83867_MICR_POLARITY_CHNG_INT_EN_MASK (0x2U) +#define DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT (1U) +#define DP83867_MICR_POLARITY_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT) & DP83867_MICR_POLARITY_CHNG_INT_EN_MASK) +#define DP83867_MICR_POLARITY_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_POLARITY_CHNG_INT_EN_MASK) >> DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT) + +/* + * JABBER_INT_EN (RW) + * + * Enable Jabber Interrupt: + * 1 = Enable Jabber interrupt. + * 0 = Disable Jabber interrupt. + */ +#define DP83867_MICR_JABBER_INT_EN_MASK (0x1U) +#define DP83867_MICR_JABBER_INT_EN_SHIFT (0U) +#define DP83867_MICR_JABBER_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_JABBER_INT_EN_SHIFT) & DP83867_MICR_JABBER_INT_EN_MASK) +#define DP83867_MICR_JABBER_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_JABBER_INT_EN_MASK) >> DP83867_MICR_JABBER_INT_EN_SHIFT) + +/* Bitfield definition for register: ISR */ +/* + * AUTONEG_ERR_INT (RO, LH, COR) + * + * Auto-Negotiation Error Interrupt: + * 1 = Auto-Negotiation Error interrupt is pending and is cleared by the + * current read. + * 0 = No Auto-Negotiation Error interrupt. + */ +#define DP83867_ISR_AUTONEG_ERR_INT_MASK (0x8000U) +#define DP83867_ISR_AUTONEG_ERR_INT_SHIFT (15U) +#define DP83867_ISR_AUTONEG_ERR_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_AUTONEG_ERR_INT_MASK) >> DP83867_ISR_AUTONEG_ERR_INT_SHIFT) + +/* + * SPEED_CHNG_INT (RO, LH, COR) + * + * Speed Change Interrupt: + * 1 = Speed Change interrupt is pending and is cleared by the current + * read. + * 0 = No Speed Change interrupt. + */ +#define DP83867_ISR_SPEED_CHNG_INT_MASK (0x4000U) +#define DP83867_ISR_SPEED_CHNG_INT_SHIFT (14U) +#define DP83867_ISR_SPEED_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_SPEED_CHNG_INT_MASK) >> DP83867_ISR_SPEED_CHNG_INT_SHIFT) + +/* + * DUPLEX_MODE_CHNG_INT (RO, LH, COR) + * + * Duplex Mode Change Interrupt: + * 1 = Duplex Mode Change interrupt is pending and is cleared by the + * current read. + * 0 = No Duplex Mode Change interrupt. + */ +#define DP83867_ISR_DUPLEX_MODE_CHNG_INT_MASK (0x2000U) +#define DP83867_ISR_DUPLEX_MODE_CHNG_INT_SHIFT (13U) +#define DP83867_ISR_DUPLEX_MODE_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_DUPLEX_MODE_CHNG_INT_MASK) >> DP83867_ISR_DUPLEX_MODE_CHNG_INT_SHIFT) + +/* + * PAGE_RECEIVED_INT (RO, LH, COR) + * + * Page Received Interrupt: + * 1 = Page Received Interrupt is pending and is cleared by the + * current read. + * 0 = No Page Received Interrupt is pending. + */ +#define DP83867_ISR_PAGE_RECEIVED_INT_MASK (0x1000U) +#define DP83867_ISR_PAGE_RECEIVED_INT_SHIFT (12U) +#define DP83867_ISR_PAGE_RECEIVED_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_PAGE_RECEIVED_INT_MASK) >> DP83867_ISR_PAGE_RECEIVED_INT_SHIFT) + +/* + * AUTONEG_COMP_INT (RO, LH, COR) + * + * Auto-Negotiation Complete Interrupt: + * 1 = Auto-Negotiation Complete Interrupt is pending and is cleared + * by the current read. + * 0 = No Auto-Negotiation Complete Interrupt is pending. + */ +#define DP83867_ISR_AUTONEG_COMP_INT_MASK (0x800U) +#define DP83867_ISR_AUTONEG_COMP_INT_SHIFT (11U) +#define DP83867_ISR_AUTONEG_COMP_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_AUTONEG_COMP_INT_MASK) >> DP83867_ISR_AUTONEG_COMP_INT_SHIFT) + +/* + * LINK_STATUS_CHNG_INT (RO, LH, COR) + * + * Link Status Change Interrupt: + * 1 = Link Status Change interrupt is pending and is cleared by the + * current read. + * 0 = No Link Status Change interrupt is pending. + */ +#define DP83867_ISR_LINK_STATUS_CHNG_INT_MASK (0x400U) +#define DP83867_ISR_LINK_STATUS_CHNG_INT_SHIFT (10U) +#define DP83867_ISR_LINK_STATUS_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_LINK_STATUS_CHNG_INT_MASK) >> DP83867_ISR_LINK_STATUS_CHNG_INT_SHIFT) + +/* + * FALSE_CARRIER_INT ( RO, LH, COR) + * + * False Carrier Interrupt: + * 1 = False Carrier interrupt is pending and is cleared by the current + * read. + * 0 = No False Carrier interrupt is pending. + */ +#define DP83867_ISR_FALSE_CARRIER_INT_MASK (0x100U) +#define DP83867_ISR_FALSE_CARRIER_INT_SHIFT (8U) +#define DP83867_ISR_FALSE_CARRIER_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_FALSE_CARRIER_INT_MASK) >> DP83867_ISR_FALSE_CARRIER_INT_SHIFT) + +/* + * MDI_CROSSOVER_CHNG_INT (RO, LH, COR) + * + * MDI Crossover Change Interrupt: + * 1 = MDI Crossover Change interrupt is pending and is cleared by + * the current read. + * 0 = No MDI Crossover Change interrupt is pending. + */ +#define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_MASK (0x40U) +#define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_SHIFT (6U) +#define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_MDI_CROSSOVER_CHNG_INT_MASK) >> DP83867_ISR_MDI_CROSSOVER_CHNG_INT_SHIFT) + +/* + * SPEED_OPT_EVENT_INT (RO, LH, COR) + * + * Speed Optimization Event Interrupt: + * 1 = Speed Optimization Event Interrupt is pending and is cleared by + * the current read. + * 0 = No Speed Optimization Event Interrupt is pending. + */ +#define DP83867_ISR_SPEED_OPT_EVENT_INT_MASK (0x20U) +#define DP83867_ISR_SPEED_OPT_EVENT_INT_SHIFT (5U) +#define DP83867_ISR_SPEED_OPT_EVENT_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_SPEED_OPT_EVENT_INT_MASK) >> DP83867_ISR_SPEED_OPT_EVENT_INT_SHIFT) + +/* + * SLEEP_MODE_CHNG_INT (RO, LH, COR) + * + * Sleep Mode Change Interrupt: + * 1 = Sleep Mode Change Interrupt is pending and is cleared by the + * current read. + * 0 = No Sleep Mode Change Interrupt is pending. + */ +#define DP83867_ISR_SLEEP_MODE_CHNG_INT_MASK (0x10U) +#define DP83867_ISR_SLEEP_MODE_CHNG_INT_SHIFT (4U) +#define DP83867_ISR_SLEEP_MODE_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_SLEEP_MODE_CHNG_INT_MASK) >> DP83867_ISR_SLEEP_MODE_CHNG_INT_SHIFT) + +/* + * WOL_INT (RO, LH, COR) + * + * Wake-on-LAN Interrupt: + * 1 = Wake-on-LAN Interrupt is pending. + * 0 = No Wake-on-LAN Interrupt is pending. + */ +#define DP83867_ISR_WOL_INT_MASK (0x8U) +#define DP83867_ISR_WOL_INT_SHIFT (3U) +#define DP83867_ISR_WOL_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_WOL_INT_MASK) >> DP83867_ISR_WOL_INT_SHIFT) + +/* + * XGMII_ERR_INT (RO, LH, COR) + * + * xGMII Error Interrupt: + * 1 = xGMII Error Interrupt is pending and is cleared by the current + * read. + * 0 = No xGMII Error Interrupt is pending. + */ +#define DP83867_ISR_XGMII_ERR_INT_MASK (0x4U) +#define DP83867_ISR_XGMII_ERR_INT_SHIFT (2U) +#define DP83867_ISR_XGMII_ERR_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_XGMII_ERR_INT_MASK) >> DP83867_ISR_XGMII_ERR_INT_SHIFT) + +/* + * POLARITY_CHNG_INT (RO, LH, COR) + * + * Polarity Change Interrupt: + * 1 = Polarity Change interrupt is pending and is cleared by the + * current read. + * 0 = No Polarity Change interrupt is pending. + */ +#define DP83867_ISR_POLARITY_CHNG_INT_MASK (0x2U) +#define DP83867_ISR_POLARITY_CHNG_INT_SHIFT (1U) +#define DP83867_ISR_POLARITY_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_POLARITY_CHNG_INT_MASK) >> DP83867_ISR_POLARITY_CHNG_INT_SHIFT) + +/* + * JABBER_INT (RO, LH, COR) + * + * Jabber Interrupt: + * 1 = Jabber interrupt is pending and is cleared by the current read. + * 0 = No Jabber interrupt is pending. + */ +#define DP83867_ISR_JABBER_INT_MASK (0x1U) +#define DP83867_ISR_JABBER_INT_SHIFT (0U) +#define DP83867_ISR_JABBER_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_JABBER_INT_MASK) >> DP83867_ISR_JABBER_INT_SHIFT) + +/* Bitfield definition for register: CRG2 */ +/* + * INTERRUPT_POLARITY (RW) + * + * Configure Interrupt Polarity: + * 1 = Interrupt pin is active low. + * 0 = Interrupt pin is active high. + */ +#define DP83867_CRG2_INTERRUPT_POLARITY_MASK (0x2000U) +#define DP83867_CRG2_INTERRUPT_POLARITY_SHIFT (13U) +#define DP83867_CRG2_INTERRUPT_POLARITY_SET(x) (((uint16_t)(x) << DP83867_CRG2_INTERRUPT_POLARITY_SHIFT) & DP83867_CRG2_INTERRUPT_POLARITY_MASK) +#define DP83867_CRG2_INTERRUPT_POLARITY_GET(x) (((uint16_t)(x) & DP83867_CRG2_INTERRUPT_POLARITY_MASK) >> DP83867_CRG2_INTERRUPT_POLARITY_SHIFT) + +/* + * SPEED_OPT_ATTEMPT_CNT (RO) + * + * Speed Optimization Attempt Count: + * Selects the number of 1000BASE-T link establishment attempt + * failures prior to performing Speed Optimization. + * 11 = 8 + * 10 = 4 + * 01 = 2 + * 00 = 1 + */ +#define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_MASK (0xC00U) +#define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_SHIFT (10U) +#define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_MASK) >> DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_SHIFT) + +/* + * SPEED_OPT_EN (RW) + * + * Speed Optimization Enable: + * 1 = Enable Speed Optimization. + * 0 = Disable Speed Optimization. + */ +#define DP83867_CRG2_SPEED_OPT_EN_MASK (0x200U) +#define DP83867_CRG2_SPEED_OPT_EN_SHIFT (9U) +#define DP83867_CRG2_SPEED_OPT_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_EN_MASK) +#define DP83867_CRG2_SPEED_OPT_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_EN_MASK) >> DP83867_CRG2_SPEED_OPT_EN_SHIFT) + +/* + * SPEED_OPT_ENHANCED_EN (RW) + * + * Speed Optimization Enhanced Mode Enable: + * In enhanced mode, speed is optimized if energy is not detected in + * channels C and D. + * 1 = Enable Speed Optimization enhanced mode. + * 0 = Disable Speed Optimization enhanced mode. + */ +#define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK (0x100U) +#define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT (8U) +#define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK) +#define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK) >> DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT) + +/* + * SGMII_AUTONEG_EN (RW) + * + * SGMII Auto-Negotiation Enable: + * 1 = Enable SGMII Auto-Negotaition. + * 0 = Disable SGMII Auto-Negotaition. + */ +#define DP83867_CRG2_SGMII_AUTONEG_EN_MASK (0x80U) +#define DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT (7U) +#define DP83867_CRG2_SGMII_AUTONEG_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT) & DP83867_CRG2_SGMII_AUTONEG_EN_MASK) +#define DP83867_CRG2_SGMII_AUTONEG_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SGMII_AUTONEG_EN_MASK) >> DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT) + +/* + * SPEED_OPT_10M_EN (RW) + * + * Enable Speed Optimization to 10BASE-Te: + * 1 = Enable speed optimization to 10BASE-Te if link establishment + * fails in 1000BASE-T and 100BASE-TX . + * 0 = Disable speed optimization to 10BASE-Te. + */ +#define DP83867_CRG2_SPEED_OPT_10M_EN_MASK (0x40U) +#define DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT (6U) +#define DP83867_CRG2_SPEED_OPT_10M_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_10M_EN_MASK) +#define DP83867_CRG2_SPEED_OPT_10M_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_10M_EN_MASK) >> DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT) + +/* Bitfield definition for register: RECR */ +/* + * RXERCNT_15_0 (RO, WSC) + * + * RX_ER Counter: + * Receive error counter. This register saturates at the maximum value + * of 0xFFFF. It is cleared by dummy write to this register. + */ +#define DP83867_RECR_RXERCNT_15_0_MASK (0xFFFFU) +#define DP83867_RECR_RXERCNT_15_0_SHIFT (0U) +#define DP83867_RECR_RXERCNT_15_0_SET(x) (((uint16_t)(x) << DP83867_RECR_RXERCNT_15_0_SHIFT) & DP83867_RECR_RXERCNT_15_0_MASK) +#define DP83867_RECR_RXERCNT_15_0_GET(x) (((uint16_t)(x) & DP83867_RECR_RXERCNT_15_0_MASK) >> DP83867_RECR_RXERCNT_15_0_SHIFT) + +/* Bitfield definition for register: STS2 */ +/* + * PRBS_LOCK (RO) + * + * PRBS Lock Status: + * 1 = PRBS checker is locked to the received byte stream. + * 0 = PRBS checker is not locked. + */ +#define DP83867_STS2_PRBS_LOCK_MASK (0x800U) +#define DP83867_STS2_PRBS_LOCK_SHIFT (11U) +#define DP83867_STS2_PRBS_LOCK_GET(x) (((uint16_t)(x) & DP83867_STS2_PRBS_LOCK_MASK) >> DP83867_STS2_PRBS_LOCK_SHIFT) + +/* + * PRBS_LOCK_LOST (RO, LH, COR) + * + * PRBS Lock Lost: + * 1 = PRBS checker has lost lock. + * 0 = PRBS checker has not lost lock. + */ +#define DP83867_STS2_PRBS_LOCK_LOST_MASK (0x400U) +#define DP83867_STS2_PRBS_LOCK_LOST_SHIFT (10U) +#define DP83867_STS2_PRBS_LOCK_LOST_GET(x) (((uint16_t)(x) & DP83867_STS2_PRBS_LOCK_LOST_MASK) >> DP83867_STS2_PRBS_LOCK_LOST_SHIFT) + +/* + * PKT_GEN_BUSY (RO) + * + * Packet Generator Busy: + * 1 = Packet generation is in process. + * 0 = Packet generation is not in process. + */ +#define DP83867_STS2_PKT_GEN_BUSY_MASK (0x200U) +#define DP83867_STS2_PKT_GEN_BUSY_SHIFT (9U) +#define DP83867_STS2_PKT_GEN_BUSY_GET(x) (((uint16_t)(x) & DP83867_STS2_PKT_GEN_BUSY_MASK) >> DP83867_STS2_PKT_GEN_BUSY_SHIFT) + +/* + * SCR_MODE_MASTER_1G (RO) + * + * Gigabit Master Scramble Mode: + * 1 = 1G PCS (master) is in legacy encoding mode. + * 0 = 1G PCS (master) is in normal encoding mode.. + */ +#define DP83867_STS2_SCR_MODE_MASTER_1G_MASK (0x100U) +#define DP83867_STS2_SCR_MODE_MASTER_1G_SHIFT (8U) +#define DP83867_STS2_SCR_MODE_MASTER_1G_GET(x) (((uint16_t)(x) & DP83867_STS2_SCR_MODE_MASTER_1G_MASK) >> DP83867_STS2_SCR_MODE_MASTER_1G_SHIFT) + +/* + * SCR_MODE_SLAVE_1G (RO) + * + * Gigabit Slave Scramble Mode: + * 1 = 1G PCS (slave) is in legacy encoding mode. + * 0 = 1G PCS (slave) is in normal encoding mode.. + */ +#define DP83867_STS2_SCR_MODE_SLAVE_1G_MASK (0x80U) +#define DP83867_STS2_SCR_MODE_SLAVE_1G_SHIFT (7U) +#define DP83867_STS2_SCR_MODE_SLAVE_1G_GET(x) (((uint16_t)(x) & DP83867_STS2_SCR_MODE_SLAVE_1G_MASK) >> DP83867_STS2_SCR_MODE_SLAVE_1G_SHIFT) + +/* + * CORE_PWR_MODE (RO) + * + * Core Power Mode: + * 1 = Core is in normal power mode. + * 0 = Core is power-down mode or in sleep mode. + */ +#define DP83867_STS2_CORE_PWR_MODE_MASK (0x40U) +#define DP83867_STS2_CORE_PWR_MODE_SHIFT (6U) +#define DP83867_STS2_CORE_PWR_MODE_GET(x) (((uint16_t)(x) & DP83867_STS2_CORE_PWR_MODE_MASK) >> DP83867_STS2_CORE_PWR_MODE_SHIFT) + +/* Bitfield definition for register: LEDCR1 */ +/* + * LED_GPIO_SEL (RW) + * + * Source of the GPIO LED_3: + * 1111: Reserved + * 1110: Receive Error + * 1101: Receive Error or Transmit Error + * 1100: RESERVED + * 1011: Link established, blink for transmit or receive activity + * 1010: Full duplex + * 1001: 100/1000BT link established + * 1000: 10/100BT link established + * 0111: 10BT link established + * 0110: 100 BTX link established + * 0101: 1000BT link established + * 0100: Collision detected + * 0011: Receive activity + * 0010: Transmit activity + * 0001: Receive or Transmit activity + * 0000: Link established + */ +#define DP83867_LEDCR1_LED_GPIO_SEL_MASK (0xF000U) +#define DP83867_LEDCR1_LED_GPIO_SEL_SHIFT (12U) +#define DP83867_LEDCR1_LED_GPIO_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_GPIO_SEL_SHIFT) & DP83867_LEDCR1_LED_GPIO_SEL_MASK) +#define DP83867_LEDCR1_LED_GPIO_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_GPIO_SEL_MASK) >> DP83867_LEDCR1_LED_GPIO_SEL_SHIFT) + +/* + * LED_2_SEL (RW) + * + * Source of LED_2: + * 1111: Reserved + * 1110: Receive Error + * 1101: Receive Error or Transmit Error + * 1100: RESERVED + * 1011: Link established, blink for transmit or receive activity + * 1010: Full duplex + * 1001: 100/1000BT link established + * 1000: 10/100BT link established + * 0111: 10BT link established + * 0110: 100 BTX link established + * 0101: 1000BT link established + * 0100: Collision detected + * 0011: Receive activity + * 0010: Transmit activity + * 0001: Receive or Transmit activity + * 0000: Link established + */ +#define DP83867_LEDCR1_LED_2_SEL_MASK (0xF00U) +#define DP83867_LEDCR1_LED_2_SEL_SHIFT (8U) +#define DP83867_LEDCR1_LED_2_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_2_SEL_SHIFT) & DP83867_LEDCR1_LED_2_SEL_MASK) +#define DP83867_LEDCR1_LED_2_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_2_SEL_MASK) >> DP83867_LEDCR1_LED_2_SEL_SHIFT) + +/* + * LED_1_SEL (RW) + * + * Source of LED_1: + * 1111: Reserved + * 1110: Receive Error + * 1101: Receive Error or Transmit Error + * 1100: RESERVED + * 1011: Link established, blink for transmit or receive activity + * 1010: Full duplex + * 1001: 100/1000BT link established + * 1000: 10/100BT link established + * 0111: 10BT link established + * 0110: 100 BTX link established + * 0101: 1000BT link established + * 0100: Collision detected + * 0011: Receive activity + * 0010: Transmit activity + * 0001: Receive or Transmit activity + * 0000: Link established + */ +#define DP83867_LEDCR1_LED_1_SEL_MASK (0xF0U) +#define DP83867_LEDCR1_LED_1_SEL_SHIFT (4U) +#define DP83867_LEDCR1_LED_1_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_1_SEL_SHIFT) & DP83867_LEDCR1_LED_1_SEL_MASK) +#define DP83867_LEDCR1_LED_1_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_1_SEL_MASK) >> DP83867_LEDCR1_LED_1_SEL_SHIFT) + +/* + * LED_0_SEL (RW) + * + * Source of LED_0: + * 1111: Reserved + * 1110: Receive Error + * 1101: Receive Error or Transmit Error + * 1100: RESERVED + * 1011: Link established, blink for transmit or receive activity + * 1010: Full duplex + * 1001: 100/1000BT link established + * 1000: 10/100BT link established + * 0111: 10BT link established + * 0110: 100 BTX link established + * 0101: 1000BT link established + * 0100: Collision detected + * 0011: Receive activity + * 0010: Transmit activity + * 0001: Receive or Transmit activity + * 0000: Link established + */ +#define DP83867_LEDCR1_LED_0_SEL_MASK (0xFU) +#define DP83867_LEDCR1_LED_0_SEL_SHIFT (0U) +#define DP83867_LEDCR1_LED_0_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_0_SEL_SHIFT) & DP83867_LEDCR1_LED_0_SEL_MASK) +#define DP83867_LEDCR1_LED_0_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_0_SEL_MASK) >> DP83867_LEDCR1_LED_0_SEL_SHIFT) + +/* Bitfield definition for register: LEDCR2 */ +/* + * LED_GPIO_POLARITY (RW) + * + * GPIO LED Polarity: + * 1 = Active high + * 0 = Active low + */ +#define DP83867_LEDCR2_LED_GPIO_POLARITY_MASK (0x4000U) +#define DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT (14U) +#define DP83867_LEDCR2_LED_GPIO_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT) & DP83867_LEDCR2_LED_GPIO_POLARITY_MASK) +#define DP83867_LEDCR2_LED_GPIO_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_POLARITY_MASK) >> DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT) + +/* + * LED_GPIO_DRV_VAL (RW) + * + * GPIO LED Drive Value: + * Value to force on GPIO LED + * This bit is only valid if enabled through LED_GPIO_DRV_EN. + */ +#define DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK (0x2000U) +#define DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT (13U) +#define DP83867_LEDCR2_LED_GPIO_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK) +#define DP83867_LEDCR2_LED_GPIO_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT) + +/* + * LED_GPIO_DRV_EN (RW) + * + * GPIO LED Drive Enable: + * 1 = Force the value of the LED_GPIO_DRV_VAL bit onto the GPIO + * LED. + * 0 = Normal operation + */ +#define DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK (0x1000U) +#define DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT (12U) +#define DP83867_LEDCR2_LED_GPIO_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK) +#define DP83867_LEDCR2_LED_GPIO_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK) >> DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT) + +/* + * LED_2_POLARITY (RW) + * + * LED_2 Polarity: + * 1 = Active high + * 0 = Active low + */ +#define DP83867_LEDCR2_LED_2_POLARITY_MASK (0x400U) +#define DP83867_LEDCR2_LED_2_POLARITY_SHIFT (10U) +#define DP83867_LEDCR2_LED_2_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_2_POLARITY_SHIFT) & DP83867_LEDCR2_LED_2_POLARITY_MASK) +#define DP83867_LEDCR2_LED_2_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_2_POLARITY_MASK) >> DP83867_LEDCR2_LED_2_POLARITY_SHIFT) + +/* + * LED_2_DRV_VAL (RW) + * + * LED_2 Drive Value: + * Value to force on LED_2 + * This bit is only valid if enabled through LED_2_DRV_EN. + */ +#define DP83867_LEDCR2_LED_2_DRV_VAL_MASK (0x200U) +#define DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT (9U) +#define DP83867_LEDCR2_LED_2_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_2_DRV_VAL_MASK) +#define DP83867_LEDCR2_LED_2_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_2_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT) + +/* + * LED_2_DRV_EN (RW) + * + * LED_2 Drive Enable: + * 1 = Force the value of the LED_2_DRV_VAL bit onto LED_2. + * 0 = Normal operation + */ +#define DP83867_LEDCR2_LED_2_DRV_EN_MASK (0x100U) +#define DP83867_LEDCR2_LED_2_DRV_EN_SHIFT (8U) +#define DP83867_LEDCR2_LED_2_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_2_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_2_DRV_EN_MASK) +#define DP83867_LEDCR2_LED_2_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_2_DRV_EN_MASK) >> DP83867_LEDCR2_LED_2_DRV_EN_SHIFT) + +/* + * LED_1_POLARITY (RW) + * + * LED_1 Polarity: + * 1 = Active high + * 0 = Active low + */ +#define DP83867_LEDCR2_LED_1_POLARITY_MASK (0x40U) +#define DP83867_LEDCR2_LED_1_POLARITY_SHIFT (6U) +#define DP83867_LEDCR2_LED_1_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_1_POLARITY_SHIFT) & DP83867_LEDCR2_LED_1_POLARITY_MASK) +#define DP83867_LEDCR2_LED_1_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_1_POLARITY_MASK) >> DP83867_LEDCR2_LED_1_POLARITY_SHIFT) + +/* + * LED_1_DRV_VAL (RW) + * + * LED_1 Drive Value: + * Value to force on LED_1 + * This bit is only valid if enabled through LED_1_DRV_EN. + */ +#define DP83867_LEDCR2_LED_1_DRV_VAL_MASK (0x20U) +#define DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT (5U) +#define DP83867_LEDCR2_LED_1_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_1_DRV_VAL_MASK) +#define DP83867_LEDCR2_LED_1_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_1_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT) + +/* + * LED_1_DRV_EN (RW) + * + * LED_1 Drive Enable: + * 1 = Force the value of the LED_1_DRV_VAL bit onto LED_1. + * 0 = Normal operation + */ +#define DP83867_LEDCR2_LED_1_DRV_EN_MASK (0x10U) +#define DP83867_LEDCR2_LED_1_DRV_EN_SHIFT (4U) +#define DP83867_LEDCR2_LED_1_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_1_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_1_DRV_EN_MASK) +#define DP83867_LEDCR2_LED_1_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_1_DRV_EN_MASK) >> DP83867_LEDCR2_LED_1_DRV_EN_SHIFT) + +/* + * LED_0_POLARITY (RW) + * + * LED_0 Polarity: + * 1 = Active high + * 0 = Active low + */ +#define DP83867_LEDCR2_LED_0_POLARITY_MASK (0x4U) +#define DP83867_LEDCR2_LED_0_POLARITY_SHIFT (2U) +#define DP83867_LEDCR2_LED_0_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_0_POLARITY_SHIFT) & DP83867_LEDCR2_LED_0_POLARITY_MASK) +#define DP83867_LEDCR2_LED_0_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_0_POLARITY_MASK) >> DP83867_LEDCR2_LED_0_POLARITY_SHIFT) + +/* + * LED_0_DRV_VAL (RW) + * + * LED_0 Drive Value: + * Value to force on LED_0 + * This bit is only valid if enabled through LED_0_DRV_EN. + */ +#define DP83867_LEDCR2_LED_0_DRV_VAL_MASK (0x2U) +#define DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT (1U) +#define DP83867_LEDCR2_LED_0_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_0_DRV_VAL_MASK) +#define DP83867_LEDCR2_LED_0_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_0_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT) + +/* + * LED_0_DRV_EN (RW) + * + * LED_0 Drive Enable: + * 1 = Force the value of the LED_0_DRV_VAL bit onto LED_0. + * 0 = Normal operation + */ +#define DP83867_LEDCR2_LED_0_DRV_EN_MASK (0x1U) +#define DP83867_LEDCR2_LED_0_DRV_EN_SHIFT (0U) +#define DP83867_LEDCR2_LED_0_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_0_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_0_DRV_EN_MASK) +#define DP83867_LEDCR2_LED_0_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_0_DRV_EN_MASK) >> DP83867_LEDCR2_LED_0_DRV_EN_SHIFT) + +/* Bitfield definition for register: LEDCR3 */ +/* + * LEDS_BYPASS_STRETCHING (RW) + * + * Bypass LED Stretching: + * 1 = Bypass LED Stretching + * 0 = Normal operation + */ +#define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK (0x4U) +#define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT (2U) +#define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SET(x) (((uint16_t)(x) << DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT) & DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK) +#define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_GET(x) (((uint16_t)(x) & DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK) >> DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT) + +/* + * LEDS_BLINK_RATE (RW) + * + * LED Blink Rate: + * 11: 2 Hz (500 ms) + * 10: 5 Hz (200 ms) + * 01: 10 Hz (100 ms) + * 00 = 20 Hz (50 ms) + */ +#define DP83867_LEDCR3_LEDS_BLINK_RATE_MASK (0x3U) +#define DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT (0U) +#define DP83867_LEDCR3_LEDS_BLINK_RATE_SET(x) (((uint16_t)(x) << DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT) & DP83867_LEDCR3_LEDS_BLINK_RATE_MASK) +#define DP83867_LEDCR3_LEDS_BLINK_RATE_GET(x) (((uint16_t)(x) & DP83867_LEDCR3_LEDS_BLINK_RATE_MASK) >> DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT) + +/* Bitfield definition for register: CFG3 */ +/* + * FAST_LINK_UP_IN_PARALLEL_DETECT (RW) + * + * Fast Link-Up in Parallel Detect Mode: + * 1 = Enable Fast Link-Up time During Parallel Detection + * 0 = Normal Parallel Detection link establishment + * In Fast Auto MDI-X this bit is automatically set. + */ +#define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK (0x8000U) +#define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT (15U) +#define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT) & DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK) +#define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK) >> DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT) + +/* + * FAST_AN_ENABLE (RW) + * + * Fast Auto-Negotiation Enable: + * 1 = Enable Fast Auto-Negotiation mode – The PHY auto- + * negotiates using Timer setting according to Fast AN Sel bits + * 0 = Disable Fast Auto-Negotiation mode – The PHY auto- + * negotiates using normal Timer setting + * Adjusting these bits reduces the time it takes to Auto-negotiate + * between two PHYs. Note: When using this option care must be + * taken to maintain proper operation of the system. While shortening + * these timer intervals may not cause problems in normal operation, + * there are certain situations where this may lead to problems. + */ +#define DP83867_CFG3_FAST_AN_ENABLE_MASK (0x4000U) +#define DP83867_CFG3_FAST_AN_ENABLE_SHIFT (14U) +#define DP83867_CFG3_FAST_AN_ENABLE_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_AN_ENABLE_SHIFT) & DP83867_CFG3_FAST_AN_ENABLE_MASK) +#define DP83867_CFG3_FAST_AN_ENABLE_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_AN_ENABLE_MASK) >> DP83867_CFG3_FAST_AN_ENABLE_SHIFT) + +/* + * FAST_AN_SEL (RW) + * + * Fast Auto-Negotiation Select bits: + * Fast AN Select Break Link Timer(ms) Link Fail Inhibit TImer(ms) Auto-Neg Wait Timer(ms) + * <00> 80 50 35 + * <01> 120 75 50 + * <10> 240 150 100 + * <11> NA NA NA + * Adjusting these bits reduces the time it takes to auto-negotiate + * between two PHYs. In Fast AN mode, both PHYs should be + * configured to the same configuration. These 2 bits define the + * duration for each state of the Auto-Negotiation process according + * to the table above. The new duration time must be enabled by + * setting Fast AN En - bit 4 of this register. Note: Using this mode in + * cases where both link partners are not configured to the same + * Fast Auto-Negotiation configuration might produce scenarios with + * unexpected behavior. + */ +#define DP83867_CFG3_FAST_AN_SEL_MASK (0x3000U) +#define DP83867_CFG3_FAST_AN_SEL_SHIFT (12U) +#define DP83867_CFG3_FAST_AN_SEL_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_AN_SEL_SHIFT) & DP83867_CFG3_FAST_AN_SEL_MASK) +#define DP83867_CFG3_FAST_AN_SEL_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_AN_SEL_MASK) >> DP83867_CFG3_FAST_AN_SEL_SHIFT) + +/* + * EXTENDED_FD_ABILITY (RW) + * + * Extended Full-Duplex Ability: + * 1 = Force Full-Duplex while working with link partner in forced + * 100B-TX. When the PHY is set to Auto-Negotiation or Force 100B- + * TX and the link partner is operated in Force 100B-TX, the link is + * always Full Duplex + * 0 = Disable Extended Full Duplex Ability. Decision to work in Full + * Duplex or Half Duplex mode follows IEEE specification. + */ +#define DP83867_CFG3_EXTENDED_FD_ABILITY_MASK (0x800U) +#define DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT (11U) +#define DP83867_CFG3_EXTENDED_FD_ABILITY_SET(x) (((uint16_t)(x) << DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT) & DP83867_CFG3_EXTENDED_FD_ABILITY_MASK) +#define DP83867_CFG3_EXTENDED_FD_ABILITY_GET(x) (((uint16_t)(x) & DP83867_CFG3_EXTENDED_FD_ABILITY_MASK) >> DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT) + +/* + * ROBUST_AUTO_MDIX (RW) + * + * Robust Auto-MDIX: + * 1 =Enable Robust Auto MDI/MDIX resolution + * 0 = Normal Auto MDI/MDIX mode + * If link partners are configured to operational modes that are not + * supported by normal Auto MDI/MDIX mode (like Auto-Neg versus + * Force 100Base-TX or Force 100Base-TX versus Force 100Base- + * TX), this Robust Auto MDI/MDIX mode allows MDI/MDIX + * resolution and prevents deadlock. + */ +#define DP83867_CFG3_ROBUST_AUTO_MDIX_MASK (0x200U) +#define DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT (9U) +#define DP83867_CFG3_ROBUST_AUTO_MDIX_SET(x) (((uint16_t)(x) << DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT) & DP83867_CFG3_ROBUST_AUTO_MDIX_MASK) +#define DP83867_CFG3_ROBUST_AUTO_MDIX_GET(x) (((uint16_t)(x) & DP83867_CFG3_ROBUST_AUTO_MDIX_MASK) >> DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT) + +/* + * FAST_AUTO_MDIX (RW) + * + * Fast Auto MDI/MDIX: + * 1 = Enable Fast Auto MDI/MDIX mode + * 0 = Normal Auto MDI/MDIX mode + * If both link partners are configured to work in Force 100Base-TX + * mode (Auto-Negotiation is disabled), this mode enables Automatic + * MDI/MDIX resolution in a short time. + */ +#define DP83867_CFG3_FAST_AUTO_MDIX_MASK (0x100U) +#define DP83867_CFG3_FAST_AUTO_MDIX_SHIFT (8U) +#define DP83867_CFG3_FAST_AUTO_MDIX_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_AUTO_MDIX_SHIFT) & DP83867_CFG3_FAST_AUTO_MDIX_MASK) +#define DP83867_CFG3_FAST_AUTO_MDIX_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_AUTO_MDIX_MASK) >> DP83867_CFG3_FAST_AUTO_MDIX_SHIFT) + +/* + * INT_OE (RW) + * + * Interrupt Output Enable: + * 1 = INTN/PWDNN Pad is an Interrupt Output. + * 0 = INTN/PWDNN Pad in a Power-Down Input. + */ +#define DP83867_CFG3_INT_OE_MASK (0x80U) +#define DP83867_CFG3_INT_OE_SHIFT (7U) +#define DP83867_CFG3_INT_OE_SET(x) (((uint16_t)(x) << DP83867_CFG3_INT_OE_SHIFT) & DP83867_CFG3_INT_OE_MASK) +#define DP83867_CFG3_INT_OE_GET(x) (((uint16_t)(x) & DP83867_CFG3_INT_OE_MASK) >> DP83867_CFG3_INT_OE_SHIFT) + +/* + * FORCE_INTERRUPT (RW) + * + * Force Interrupt: + * 1 = Assert interrupt pin. + * 0 = Normal interrupt mode. + */ +#define DP83867_CFG3_FORCE_INTERRUPT_MASK (0x40U) +#define DP83867_CFG3_FORCE_INTERRUPT_SHIFT (6U) +#define DP83867_CFG3_FORCE_INTERRUPT_SET(x) (((uint16_t)(x) << DP83867_CFG3_FORCE_INTERRUPT_SHIFT) & DP83867_CFG3_FORCE_INTERRUPT_MASK) +#define DP83867_CFG3_FORCE_INTERRUPT_GET(x) (((uint16_t)(x) & DP83867_CFG3_FORCE_INTERRUPT_MASK) >> DP83867_CFG3_FORCE_INTERRUPT_SHIFT) + +/* + * TDR_FAIL (RO) + * + * TDR Failure: + * 1 = TDR failed. + * 0 = Normal TDR operation. + */ +#define DP83867_CFG3_TDR_FAIL_MASK (0x4U) +#define DP83867_CFG3_TDR_FAIL_SHIFT (2U) +#define DP83867_CFG3_TDR_FAIL_GET(x) (((uint16_t)(x) & DP83867_CFG3_TDR_FAIL_MASK) >> DP83867_CFG3_TDR_FAIL_SHIFT) + +/* + * TDR_DONE (RO) + * + * TDR Done: + * 1 = TDR has completed. + * 0 = TDR has not completed. + */ +#define DP83867_CFG3_TDR_DONE_MASK (0x2U) +#define DP83867_CFG3_TDR_DONE_SHIFT (1U) +#define DP83867_CFG3_TDR_DONE_GET(x) (((uint16_t)(x) & DP83867_CFG3_TDR_DONE_MASK) >> DP83867_CFG3_TDR_DONE_SHIFT) + +/* + * TDR_START (RW) + * + * TDR Start: + * 1 = Start TDR. + * 0 = Normal operation + */ +#define DP83867_CFG3_TDR_START_MASK (0x1U) +#define DP83867_CFG3_TDR_START_SHIFT (0U) +#define DP83867_CFG3_TDR_START_SET(x) (((uint16_t)(x) << DP83867_CFG3_TDR_START_SHIFT) & DP83867_CFG3_TDR_START_MASK) +#define DP83867_CFG3_TDR_START_GET(x) (((uint16_t)(x) & DP83867_CFG3_TDR_START_MASK) >> DP83867_CFG3_TDR_START_SHIFT) + +/* Bitfield definition for register: CTRL */ +/* + * SW_RESET (RW,SC) + * + * Software Reset: + * 1 = Perform a full reset, including registers. + * 0 = Normal operation. + */ +#define DP83867_CTRL_SW_RESET_MASK (0x8000U) +#define DP83867_CTRL_SW_RESET_SHIFT (15U) +#define DP83867_CTRL_SW_RESET_SET(x) (((uint16_t)(x) << DP83867_CTRL_SW_RESET_SHIFT) & DP83867_CTRL_SW_RESET_MASK) +#define DP83867_CTRL_SW_RESET_GET(x) (((uint16_t)(x) & DP83867_CTRL_SW_RESET_MASK) >> DP83867_CTRL_SW_RESET_SHIFT) + +/* + * SW_RESTART (RW,SC) + * + * Software Restart: + * 1 = Perform a full reset, not including registers. . + * 0 = Normal operation. + */ +#define DP83867_CTRL_SW_RESTART_MASK (0x4000U) +#define DP83867_CTRL_SW_RESTART_SHIFT (14U) +#define DP83867_CTRL_SW_RESTART_SET(x) (((uint16_t)(x) << DP83867_CTRL_SW_RESTART_SHIFT) & DP83867_CTRL_SW_RESTART_MASK) +#define DP83867_CTRL_SW_RESTART_GET(x) (((uint16_t)(x) & DP83867_CTRL_SW_RESTART_MASK) >> DP83867_CTRL_SW_RESTART_SHIFT) + +/* Bitfield definition for register: RGMIIDCTL */ +/* + * RGMII_TX_DELAY_CTRL (RW) + * + * RGMII Transmit Clock Delay: + * 1111: 4.00 ns + * 1110: 3.75 ns + * 1101: 3.50 ns + * 1100: 3.25 ns + * 1011: 3.00 ns + * 1010: 2.75 ns + * 1001: 2.50 ns + * 1000: 2.25 ns + * 0111: 2.00 ns + * 0110: 1.75 ns + * 0101: 1.50 ns + * 0100: 1.25 ns + * 0011: 1.00 ns + * 0010: 0.75 ns + * 0001: 0.50 ns + * 0000: 0.25 ns + */ +#define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK (0xF0U) +#define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT (4U) +#define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SET(x) (((uint16_t)(x) << DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT) & DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK) +#define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_GET(x) (((uint16_t)(x) & DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK) >> DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT) + +/* + * RGMII_RX_DELAY_CTRL (RW) + * + * RGMII Receive Clock Delay: + * 1111: 4.00 ns + * 1110: 3.75 ns + * 1101: 3.50 ns + * 1100: 3.25 ns + * 1011: 3.00 ns + * 1010: 2.75 ns + * 1001: 2.50 ns + * 1000: 2.25 ns + * 0111: 2.00 ns + * 0110: 1.75 ns + * 0101: 1.50 ns + * 0100: 1.25 ns + * 0011: 1.00 ns + * 0010: 0.75 ns + * 0001: 0.50 ns + * 0000: 0.25 ns + */ +#define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK (0xFU) +#define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT (0U) +#define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SET(x) (((uint16_t)(x) << DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT) & DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK) +#define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_GET(x) (((uint16_t)(x) & DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK) >> DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT) + + + + #endif /* HPM_DP83867_REGS_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h b/common/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h new file mode 100644 index 00000000..ef99f709 --- /dev/null +++ b/common/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_ENET_PHY_H +#define HPM_ENET_PHY_H +#include + +typedef enum { + enet_phy_port_speed_10mbps = 0, + enet_phy_port_speed_100mbps, + enet_phy_port_speed_1000mbps +} enet_phy_port_speed_t; + +typedef enum { + enet_phy_duplex_half = 0, + enet_phy_duplex_full +} enet_phy_duplex_mode_t; + +typedef enum { + enet_phy_mdi_crossover_manual_mdi = 0, + enet_phy_mdi_crossover_manual_mdix, + enet_phy_mdi_crossover_automatic +} enet_phy_crossover_mode_t; + +typedef struct { + uint8_t enet_phy_link; + uint8_t enet_phy_speed; + uint8_t enet_phy_duplex; +} enet_phy_status_t; + +#endif \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h b/common/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h index a35bb205..c998daef 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h +++ b/common/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h @@ -1,18 +1,20 @@ -/* - * Copyright (c) 2021 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - #ifndef HPM_ENET_PHY_COMMON_H #define HPM_ENET_PHY_COMMON_H -typedef enum { - enet_port_speed_10mbps = 0, - enet_port_speed_100msbs, - enet_port_speed_1000mbps -} enet_port_speed_t; - +#if defined(__USE_DP83867) && __USE_DP83867 + #include "hpm_dp83867.h" + #include "hpm_dp83867_regs.h" +#elif defined(__USE_RTL8211) && __USE_RTL8211 + #include "hpm_rtl8211.h" + #include "hpm_rtl8211_regs.h" +#elif defined(__USE_DP83848) && __USE_DP83848 + #include "hpm_dp83848.h" + #include "hpm_dp83848_regs.h" +#elif defined(__USE_RTL8201) && __USE_RTL8201 + #include "hpm_rtl8201.h" + #include "hpm_rtl8201_regs.h" +#else + #error no specified Ethernet PHY !!! +#endif -#endif \ No newline at end of file +#endif /* HPM_ENET_PHY_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/enet_phy/rtl8201/CMakeLists.txt b/common/libraries/hpm_sdk/components/enet_phy/rtl8201/CMakeLists.txt index 40294d1c..f989353e 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/rtl8201/CMakeLists.txt +++ b/common/libraries/hpm_sdk/components/enet_phy/rtl8201/CMakeLists.txt @@ -1,5 +1,9 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021-2022 HPMicro # SPDX-License-Identifier: BSD-3-Clause +sdk_compile_definitions(-DRGMII=0) +sdk_compile_definitions(-D__USE_RTL8201=1) + sdk_inc(.) +sdk_inc(../) sdk_src(hpm_rtl8201.c) diff --git a/common/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c b/common/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c index 02936377..30f1f811 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c +++ b/common/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c @@ -1,69 +1,73 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_enet_drv.h" #include "hpm_rtl8201_regs.h" #include "hpm_rtl8201.h" #include "board.h" -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- + * * Internal API - *---------------------------------------------------------------------*/ -static bool rtl8201_id_check(ENET_Type *ptr) + *--------------------------------------------------------------------- + */ +static bool rtl8201_check_id(ENET_Type *ptr) { uint16_t id1, id2; - id1 = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_PHYID1); - id2 = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_PHYID2); + id1 = enet_read_phy(ptr, PHY_ADDR, RTL8201_PHYID1); + id2 = enet_read_phy(ptr, PHY_ADDR, RTL8201_PHYID2); - if (RTL8201_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && RTL8201_PHYID2_OUI_MSB_GET(id2) == PHY_ID2) { + if (RTL8201_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && RTL8201_PHYID2_OUI_LSB_GET(id2) == PHY_ID2) { return true; } else { return false; } } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * API - *---------------------------------------------------------------------*/ -uint16_t rtl8201_register_check(ENET_Type *ptr, uint32_t addr) -{ - return enet_read_phy(ptr, PHY_ADDR, addr); -} - + *--------------------------------------------------------------------- + */ void rtl8201_reset(ENET_Type *ptr) { uint16_t data; /* PHY reset */ - enet_write_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR, RTL8201_BMCR_RESET_SET(1)); + enet_write_phy(ptr, PHY_ADDR, RTL8201_BMCR, RTL8201_BMCR_RESET_SET(1)); /* wait until the reset is completed */ do { - data = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR); + data = enet_read_phy(ptr, PHY_ADDR, RTL8201_BMCR); } while (RTL8201_BMCR_RESET_GET(data)); } void rtl8201_basic_mode_default_config(ENET_Type *ptr, rtl8201_config_t *config) { - config->loopback = 1; /* Enable PCS loopback mode */ - config->speed = 2; /* reserved:3/2; 100mbps: 1; 10mbps: 0 */ - config->auto_negotiation = 1; /* Enable Auto-Negotiation */ - config->duplex_mode = 1; /* Full duplex mode */ + config->loopback = 0; /* Disable PCS loopback mode */ + #if __DISABLE_AUTO_NEGO + config->auto_negotiation = false; /* Disable Auto-Negotiation */ + config->speed = enet_phy_port_speed_100mbps; + config->duplex = enet_phy_duplex_full; + #else + config->auto_negotiation = 1; /* Enable Auto-Negotiation */ + #endif + config->txc_input = true; /* Set TXC as input mode */ } bool rtl8201_basic_mode_init(ENET_Type *ptr, rtl8201_config_t *config) { - uint16_t para = 0; + uint16_t data = 0; - para |= RTL8201_BMCR_RESET_SET(0) /* Normal operation */ + data |= RTL8201_BMCR_RESET_SET(0) /* Normal operation */ | RTL8201_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ | RTL8201_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ | RTL8201_BMCR_PWD_SET(0) /* Normal operation */ @@ -72,27 +76,37 @@ bool rtl8201_basic_mode_init(ENET_Type *ptr, rtl8201_config_t *config) | RTL8201_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ if (config->auto_negotiation == 0) { - para |= RTL8201_BMCR_SPEED0_SET(config->speed) | RTL8201_BMCR_SPEED1_SET(config->speed >> 1); + data |= RTL8201_BMCR_SPEED0_SET(config->speed); /* Set port speed */ + data |= RTL8201_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ } /* check the id of rtl8201 */ - if (rtl8201_id_check(ptr) == false) { + if (rtl8201_check_id(ptr) == false) { return false; } - para = enet_read_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR) & ~RTL8201_BMCR_SPEED0_MASK; - enet_write_phy(ptr, PHY_ADDR, RTL8201_REG_BMCR, para); + enet_write_phy(ptr, PHY_ADDR, RTL8201_BMCR, data); /* select page 7 */ - enet_write_phy(ptr, PHY_ADDR, 31, 7); - para = enet_read_phy(ptr, PHY_ADDR, 16); - para |= 1 << 12; /* set txc as input mode */ - enet_write_phy(ptr, PHY_ADDR, 16, para); + enet_write_phy(ptr, PHY_ADDR, RTL8201_PAGESEL, 7); + + /* set txc direction */ + data = enet_read_phy(ptr, PHY_ADDR, RTL8201_RMSR_P7); + data &= ~RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK; + data |= RTL8201_RMSR_P7_RG_RMII_CLKDIR_SET(config->txc_input); + enet_write_phy(ptr, PHY_ADDR, RTL8201_RMSR_P7, data); return true; } - -void rtl8201_init_auto_negotiation(void) +void rtl8201_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) { -} + uint16_t data; + + data = enet_read_phy(ptr, PHY_ADDR, RTL8201_BMSR); + status->enet_phy_link = RTL8201_BMSR_LINK_STATUS_GET(data); + + data = enet_read_phy(ptr, PHY_ADDR, RTL8201_BMCR); + status->enet_phy_speed = RTL8201_BMCR_SPEED0_GET(data) == 0 ? enet_phy_port_speed_10mbps : enet_phy_port_speed_100mbps; + status->enet_phy_duplex = RTL8201_BMCR_DUPLEX_GET(data); +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h b/common/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h index 3359412f..fb7e1724 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h +++ b/common/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,42 +8,46 @@ #ifndef HPM_rtl8201_H #define HPM_rtl8201_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ -#include "stdint.h" - -/*---------------------------------------------------------------------* + *--------------------------------------------------------------------- + */ +#include "hpm_enet_phy.h" +#include "hpm_common.h" +#include "hpm_enet_regs.h" +/*--------------------------------------------------------------------- * Macro Const Definitions - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #define PHY_ADDR (2U) #define PHY_ID1 (0x001CU) #define PHY_ID2 (0x32U) -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Typedef Struct Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ typedef struct { bool loopback; uint8_t speed; bool auto_negotiation; - uint8_t duplex_mode; + uint8_t duplex; + bool txc_input; } rtl8201_config_t; #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Exported Functions - *---------------------------------------------------------------------*/ -uint16_t rtl8201_check(ENET_Type *ptr, uint32_t addr); + *--------------------------------------------------------------------- + */ void rtl8201_reset(ENET_Type *ptr); void rtl8201_basic_mode_default_config(ENET_Type *ptr, rtl8201_config_t *config); bool rtl8201_basic_mode_init(ENET_Type *ptr, rtl8201_config_t *config); -void rtl8201_read_status(ENET_Type *ptr); -void rtl8201_control_config(ENET_Type *ptr); +void rtl8201_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); #if defined(__cplusplus) } #endif /* __cplusplus */ -#endif /* HPM_rtl8201_H */ \ No newline at end of file +#endif /* HPM_rtl8201_H */ diff --git a/common/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h b/common/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h index 436ac804..12ac67ee 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h +++ b/common/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h @@ -1,195 +1,407 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2023 hpmicro * * SPDX-License-Identifier: BSD-3-Clause * */ + #ifndef HPM_RTL8201_REGS_H #define HPM_RTL8201_REGS_H - /* RTL Register Definitions */ -#define RTL8201_REG_BMCR (0U) /* Basic Mode Control Register */ -#define RTL8201_REG_BMSR (1U) /* Basic Mode Status Register */ -#define RTL8201_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ -#define RTL8201_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ -#define RTL8201_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ -#define RTL8201_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ -#define RTL8201_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ - -#define RTL8201_REG_RXERC (24U) /* Receive Error Counter */ -#define RTL8201_REG_FB_LP (28U) /* Fiber Mode and Loopback Register */ -#define RTL8201_REG_PAGSEL (31U) /* Page Select Register */ - -/* RTL MMD Register Definitions */ -#define RTL8201_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ -#define RTL8201_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ -#define RTL8201_MMD_REG_EEECR (20U) /* EEE Capability Register */ -#define RTL8201_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ -#define RTL8201_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ -#define RTL8201_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ - -/* Page 0 Registers */ -#define RTL8201_REG_MACR (13U) /* MMD Access Control Register */ -#define RTL8201_REG_MAADR (14U) /* MMD Access Address Data Register */ - -/* Bitfiled definitions of Register: MACR */ -#define RTL8201_REGCR_FUNCTION_ADDR (0 << 14) -#define RTL8201_REGCR_FUNCTION_DATA (1 << 14) -#define RTL8201_REGCR_DEVAD (0x1f) +typedef enum { + RTL8201_BMCR = 0, /* 0x0: Basic Mode Control Register */ + RTL8201_BMSR = 1, /* 0x1: (Basic Mode Status Register */ + RTL8201_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */ + RTL8201_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */ + RTL8201_RMSR_P7 = 16, /* 0x10: RMII Mode Setting Register */ + RTL8201_PAGESEL = 31, /* 0x1F: Page Select Register */ +} RTL8201_REG_Type; + /* Bitfield definition for register: BMCR */ /* - * Reset (RW) + * RESET (RW/SC) * - * 1: PHY reset - * 0: Normal operation - * Register 0 (BMCR) and register 1 (BMSR) will return to default - * values after a software reset (set Bit15 to 1). + * This bit sets the status and control registers of the PHY in the + * default state. This bit is self-clearing. + * 1: Software reset 0: Normal operation + * Register 0 and register 1 will return to default values after a + * software reset (set Bit15 to 1). * This action may change the internal PHY state and the state of the * physical link associated with the PHY. */ -#define RTL8201_BMCR_RESET_MASK (0x8000U) +#define RTL8201_BMCR_RESET_MASK (0x8000U) #define RTL8201_BMCR_RESET_SHIFT (15U) -#define RTL8201_BMCR_RESET_SET(x) (((uint32_t)(x) << RTL8201_BMCR_RESET_SHIFT) & RTL8201_BMCR_RESET_MASK) -#define RTL8201_BMCR_RESET_GET(x) (((uint32_t)(x) & RTL8201_BMCR_RESET_MASK) >> RTL8201_BMCR_RESET_SHIFT) +#define RTL8201_BMCR_RESET_SET(x) (((uint16_t)(x) << RTL8201_BMCR_RESET_SHIFT) & RTL8201_BMCR_RESET_MASK) +#define RTL8201_BMCR_RESET_GET(x) (((uint16_t)(x) & RTL8201_BMCR_RESET_MASK) >> RTL8201_BMCR_RESET_SHIFT) /* - * Loopback (RW) + * LOOPBACK (RW) * - * Loopback Mode. - * 1: Enable PCS loopback mode - * 0: Disable PCS loopback mode + * This bit enables loopback of transmit data nibbles TXD3:0 to the + * receive data path. + * 1: Enable loopback 0: Normal operation */ -#define RTL8201_BMCR_LOOPBACK_MASK (0x4000U) +#define RTL8201_BMCR_LOOPBACK_MASK (0x4000U) #define RTL8201_BMCR_LOOPBACK_SHIFT (14U) -#define RTL8201_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << RTL8201_BMCR_LOOPBACK_SHIFT) & RTL8201_BMCR_LOOPBACK_MASK) -#define RTL8201_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & RTL8201_BMCR_LOOPBACK_MASK) >> RTL8201_BMCR_LOOPBACK_SHIFT) +#define RTL8201_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << RTL8201_BMCR_LOOPBACK_SHIFT) & RTL8201_BMCR_LOOPBACK_MASK) +#define RTL8201_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & RTL8201_BMCR_LOOPBACK_MASK) >> RTL8201_BMCR_LOOPBACK_SHIFT) /* - * Speed[0] (RW) + * SPEED0 (RW) * - * Speed Select Bit 0. - * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 - * determine device speed selection. + * This bit sets the network speed. + * 1: 100Mbps 0: 10Mbps + * After completing auto negotiation, this bit will reflect the speed + * status. + * 1: 100Base-T 0: 10Base-T + * When 100Base-FX mode is enabled, this bit=1 and is read only. */ -#define RTL8201_BMCR_SPEED0_MASK (0x2000U) +#define RTL8201_BMCR_SPEED0_MASK (0x2000U) #define RTL8201_BMCR_SPEED0_SHIFT (13U) -#define RTL8201_BMCR_SPEED0_SET(x) (((uint32_t)(x) << RTL8201_BMCR_SPEED0_SHIFT) & RTL8201_BMCR_SPEED0_MASK) -#define RTL8201_BMCR_SPEED0_GET(x) (((uint32_t)(x) & RTL8201_BMCR_SPEED0_MASK) >> RTL8201_BMCR_SPEED0_SHIFT) +#define RTL8201_BMCR_SPEED0_SET(x) (((uint16_t)(x) << RTL8201_BMCR_SPEED0_SHIFT) & RTL8201_BMCR_SPEED0_MASK) +#define RTL8201_BMCR_SPEED0_GET(x) (((uint16_t)(x) & RTL8201_BMCR_SPEED0_MASK) >> RTL8201_BMCR_SPEED0_SHIFT) /* * ANE (RW) * - * Auto-Negotiation Enable. - * 1: Enable Auto-Negotiation - * 0: Disable Auto-Negotiation + * This bit enables/disables the NWay auto-negotiation function. + * 1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored + * 0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the + * link speed and the data transfer mode, respectively + * When 100Base-FX mode is enabled, this bit=0 and is read only. */ -#define RTL8201_BMCR_ANE_MASK (0x1000U) +#define RTL8201_BMCR_ANE_MASK (0x1000U) #define RTL8201_BMCR_ANE_SHIFT (12U) -#define RTL8201_BMCR_ANE_SET(x) (((uint32_t)(x) << RTL8201_BMCR_ANE_SHIFT) & RTL8201_BMCR_ANE_MASK) -#define RTL8201_BMCR_ANE_GET(x) (((uint32_t)(x) & RTL8201_BMCR_ANE_MASK) >> RTL8201_BMCR_ANE_SHIFT) +#define RTL8201_BMCR_ANE_SET(x) (((uint16_t)(x) << RTL8201_BMCR_ANE_SHIFT) & RTL8201_BMCR_ANE_MASK) +#define RTL8201_BMCR_ANE_GET(x) (((uint16_t)(x) & RTL8201_BMCR_ANE_MASK) >> RTL8201_BMCR_ANE_SHIFT) /* * PWD (RW) * - * Power Down. - * 1: Power down (only Management Interface and logic are active; link - * is down) - * 0: Normal operation + * This bit turns down the power of the PHY chip, including the + * internal crystal oscillator circuit. + * The MDC, MDIO is still alive for accessing the MAC. + * 1: Power down 0: Normal operation */ -#define RTL8201_BMCR_PWD_MASK (0x0800U) +#define RTL8201_BMCR_PWD_MASK (0x800U) #define RTL8201_BMCR_PWD_SHIFT (11U) -#define RTL8201_BMCR_PWD_SET(x) (((uint32_t)(x) << RTL8201_BMCR_PWD_SHIFT) & RTL8201_BMCR_PWD_MASK) -#define RTL8201_BMCR_PWD_GET(x) (((uint32_t)(x) & RTL8201_BMCR_PWD_MASK) >> RTL8201_BMCR_PWD_SHIFT) +#define RTL8201_BMCR_PWD_SET(x) (((uint16_t)(x) << RTL8201_BMCR_PWD_SHIFT) & RTL8201_BMCR_PWD_MASK) +#define RTL8201_BMCR_PWD_GET(x) (((uint16_t)(x) & RTL8201_BMCR_PWD_MASK) >> RTL8201_BMCR_PWD_SHIFT) /* - * Isolate (RW) + * ISOLATE (RW) * - * Isolate. - * 1: RGMII/GMII interface is isolated; the serial management interface - * (MDC, MDIO) is still active. When this bit is asserted, the - * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and - * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. + * 1: Electrically isolate the PHY from MII/GMII/RGMII/RSGMII. + * PHY is still able to respond to MDC/MDIO. * 0: Normal operation */ -#define RTL8201_BMCR_ISOLATE_MASK (0x0400U) +#define RTL8201_BMCR_ISOLATE_MASK (0x400U) #define RTL8201_BMCR_ISOLATE_SHIFT (10U) -#define RTL8201_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << RTL8201_BMCR_ISOLATE_SHIFT) & RTL8201_BMCR_ISOLATE_MASK) -#define RTL8201_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & RTL8201_BMCR_ISOLATE_MASK) >> RTL8201_BMCR_ISOLATE_SHIFT) +#define RTL8201_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << RTL8201_BMCR_ISOLATE_SHIFT) & RTL8201_BMCR_ISOLATE_MASK) +#define RTL8201_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & RTL8201_BMCR_ISOLATE_MASK) >> RTL8201_BMCR_ISOLATE_SHIFT) /* - * Restart_AN (RW) + * RESTART_AN (RW/SC) * - * Restart Auto-Negotiation. - * 1: Restart Auto-Negotiation - * 0: Normal operation + * This bit allows the NWay auto-negotiation function to be reset. + * 1: Re-start auto-negotiation 0: Normal operation */ -#define RTL8201_BMCR_RESTART_AN_MASK (0x0200U) +#define RTL8201_BMCR_RESTART_AN_MASK (0x200U) #define RTL8201_BMCR_RESTART_AN_SHIFT (9U) -#define RTL8201_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << RTL8201_BMCR_RESTART_AN_SHIFT) & RTL8201_BMCR_RESTART_AN_MASK) -#define RTL8201_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & RTL8201_BMCR_RESTART_AN_MASK) >> RTL8201_BMCR_RESTART_AN_SHIFT) +#define RTL8201_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << RTL8201_BMCR_RESTART_AN_SHIFT) & RTL8201_BMCR_RESTART_AN_MASK) +#define RTL8201_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & RTL8201_BMCR_RESTART_AN_MASK) >> RTL8201_BMCR_RESTART_AN_SHIFT) /* - * Duplex (RW) + * DUPLEX (RW) * - * Duplex Mode. - * 1: Full Duplex operation - * 0: Half Duplex operation - * This bit is valid only in force mode, i.e., NWay is disabled. + * This bit sets the duplex mode if auto-negotiation is disabled (bit + * 0:12=0). + * 1: Full duplex 0: Half duplex + * After completing auto-negotiation, this bit will reflect the duplex + * status. + * 1: Full duplex 0: Half duplex */ -#define RTL8201_BMCR_DUPLEX_MASK (0x0100U) +#define RTL8201_BMCR_DUPLEX_MASK (0x100U) #define RTL8201_BMCR_DUPLEX_SHIFT (8U) -#define RTL8201_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << RTL8201_BMCR_DUPLEX_SHIFT) & RTL8201_BMCR_DUPLEX_MASK) -#define RTL8201_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & RTL8201_BMCR_DUPLEX_MASK) >> RTL8201_BMCR_DUPLEX_SHIFT) +#define RTL8201_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << RTL8201_BMCR_DUPLEX_SHIFT) & RTL8201_BMCR_DUPLEX_MASK) +#define RTL8201_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & RTL8201_BMCR_DUPLEX_MASK) >> RTL8201_BMCR_DUPLEX_SHIFT) /* - * Collision Test (RW) + * COLLISION_TEST (RW) * * Collision Test. * 1: Collision test enabled * 0: Normal operation - * When set, this bit will cause the COL signal to be asserted in response - * to the assertion of TXEN within 512-bit times. The COL signal will be - * de-asserted within 4-bit times in response to the de-assertion of - * TXEN. + * When set, this bit will cause the COL signal to be asserted in + * response to the TXEN assertion within 512-bit times. The COL + * signal will be de-asserted within 4-bit times in response to the + * TXEN de-assertion. */ -#define RTL8201_BMCR_COLLISION_TEST_MASK (0x0080U) +#define RTL8201_BMCR_COLLISION_TEST_MASK (0x80U) #define RTL8201_BMCR_COLLISION_TEST_SHIFT (7U) -#define RTL8201_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << RTL8201_BMCR_COLLISION_TEST_SHIFT) & RTL8201_BMCR_COLLISION_TEST_MASK) -#define RTL8201_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & RTL8201_BMCR_COLLISION_TEST_MASK) >> RTL8201_BMCR_COLLISION_TEST_SHIFT) +#define RTL8201_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << RTL8201_BMCR_COLLISION_TEST_SHIFT) & RTL8201_BMCR_COLLISION_TEST_MASK) +#define RTL8201_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & RTL8201_BMCR_COLLISION_TEST_MASK) >> RTL8201_BMCR_COLLISION_TEST_SHIFT) /* - * Speed[1] (RW) + * SPEED1 (RW) * * Speed Select Bit 1. - * Refer to bit 0.13. + * Refer to bit 13. */ -#define RTL8201_BMCR_SPEED1_MASK (0x0040U) +#define RTL8201_BMCR_SPEED1_MASK (0x40U) #define RTL8201_BMCR_SPEED1_SHIFT (6U) -#define RTL8201_BMCR_SPEED1_SET(x) (((uint32_t)(x) << RTL8201_BMCR_SPEED1_SHIFT) & RTL8201_BMCR_SPEED1_MASK) -#define RTL8201_BMCR_SPEED1_GET(x) (((uint32_t)(x) & RTL8201_BMCR_SPEED1_MASK) >> RTL8201_BMCR_SPEED1_SHIFT) +#define RTL8201_BMCR_SPEED1_SET(x) (((uint16_t)(x) << RTL8201_BMCR_SPEED1_SHIFT) & RTL8201_BMCR_SPEED1_MASK) +#define RTL8201_BMCR_SPEED1_GET(x) (((uint16_t)(x) & RTL8201_BMCR_SPEED1_MASK) >> RTL8201_BMCR_SPEED1_SHIFT) + +/* Bitfield definition for register: BMSR */ +/* + * 100BASE_T4 (RO) + * + * 1: Enable 100Base-T4 support + * 0: Suppress 100Base-T4 support + */ +#define RTL8201_BMSR_100BASE_T4_MASK (0x8000U) +#define RTL8201_BMSR_100BASE_T4_SHIFT (15U) +#define RTL8201_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & RTL8201_BMSR_100BASE_T4_MASK) >> RTL8201_BMSR_100BASE_T4_SHIFT) + +/* + * 100BASE_TX_FULL (RO) + * + * 1: Enable 100Base-TX full duplex support + * 0: Suppress 100Base-TX full duplex support + */ +#define RTL8201_BMSR_100BASE_TX_FULL_MASK (0x4000U) +#define RTL8201_BMSR_100BASE_TX_FULL_SHIFT (14U) +#define RTL8201_BMSR_100BASE_TX_FULL_GET(x) (((uint16_t)(x) & RTL8201_BMSR_100BASE_TX_FULL_MASK) >> RTL8201_BMSR_100BASE_TX_FULL_SHIFT) + +/* + * 100BASE_TX_HALF (RO) + * + * 1: Enable 100Base-TX half duplex support + * 0: Suppress 100Base-TX half duplex support + */ +#define RTL8201_BMSR_100BASE_TX_HALF_MASK (0x2000U) +#define RTL8201_BMSR_100BASE_TX_HALF_SHIFT (13U) +#define RTL8201_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & RTL8201_BMSR_100BASE_TX_HALF_MASK) >> RTL8201_BMSR_100BASE_TX_HALF_SHIFT) + +/* + * 10BASE_T_FULL (RO) + * + * 1: Enable 10Base-T full duplex support + * 0: Suppress 10Base-T full duplex support + */ +#define RTL8201_BMSR_10BASE_T_FULL_MASK (0x1000U) +#define RTL8201_BMSR_10BASE_T_FULL_SHIFT (12U) +#define RTL8201_BMSR_10BASE_T_FULL_GET(x) (((uint16_t)(x) & RTL8201_BMSR_10BASE_T_FULL_MASK) >> RTL8201_BMSR_10BASE_T_FULL_SHIFT) + +/* + * 10BASE_T_HALF (RO) + * + * 1: Enable 10Base-T half duplex support + * 0: Suppress 10Base-T half duplex support + */ +#define RTL8201_BMSR_10BASE_T_HALF_MASK (0x800U) +#define RTL8201_BMSR_10BASE_T_HALF_SHIFT (11U) +#define RTL8201_BMSR_10BASE_T_HALF_GET(x) (((uint16_t)(x) & RTL8201_BMSR_10BASE_T_HALF_MASK) >> RTL8201_BMSR_10BASE_T_HALF_SHIFT) + +/* + * PREAMBLE_SUPPRESSION (RO) + * + * The RTL8201F/FL/FN will accept management frames + * with preamble suppressed. + * A minimum of 32 preamble bits are required for the first + * management interface read/write transaction after reset. + * One idle bit is required between any two management + * transactions as per IEEE 802.3u specifications. + */ +#define RTL8201_BMSR_PREAMBLE_SUPPRESSION_MASK (0x40U) +#define RTL8201_BMSR_PREAMBLE_SUPPRESSION_SHIFT (6U) +#define RTL8201_BMSR_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & RTL8201_BMSR_PREAMBLE_SUPPRESSION_MASK) >> RTL8201_BMSR_PREAMBLE_SUPPRESSION_SHIFT) + +/* + * AUTO_NEGOTIATION_COMPLETE (RO) + * + * 1: Auto-negotiation process completed + * 0: Auto-negotiation process not completed + */ +#define RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) +#define RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) +#define RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) + +/* + * REMOTE_FAULT (RC) + * + * 1: Remote fault condition detected (cleared on read) + * 0: No remote fault condition detected + * When in 100Base-FX mode, this bit means an in-band + * signal Far-End-Fault has been detected (see 8.10 Far End + * Fault Indication, page 39). + */ +#define RTL8201_BMSR_REMOTE_FAULT_MASK (0x10U) +#define RTL8201_BMSR_REMOTE_FAULT_SHIFT (4U) +#define RTL8201_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & RTL8201_BMSR_REMOTE_FAULT_MASK) >> RTL8201_BMSR_REMOTE_FAULT_SHIFT) + +/* + * AUTO_NEGOTIATION_ABILITY (RO) + * + * 1: PHY is able to perform auto-negotiation + * 0: PHY is not able to perform auto-negotiation + */ +#define RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) +#define RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) +#define RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) + +/* + * LINK_STATUS (RO) + * + * 1: Valid link established + * 0: No valid link established + * This bit indicates whether the link was lost since the last + * read. For the current link status, read this register twice. + */ +#define RTL8201_BMSR_LINK_STATUS_MASK (0x4U) +#define RTL8201_BMSR_LINK_STATUS_SHIFT (2U) +#define RTL8201_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & RTL8201_BMSR_LINK_STATUS_MASK) >> RTL8201_BMSR_LINK_STATUS_SHIFT) + +/* + * JABBER_DETECT (RO) + * + * 1: Jabber condition detected + * 0: No jabber condition detected + */ +#define RTL8201_BMSR_JABBER_DETECT_MASK (0x2U) +#define RTL8201_BMSR_JABBER_DETECT_SHIFT (1U) +#define RTL8201_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & RTL8201_BMSR_JABBER_DETECT_MASK) >> RTL8201_BMSR_JABBER_DETECT_SHIFT) + +/* + * EXTENDED_CAPABILITY (RO) + * + * 1: Extended register capable (permanently=1) + * 0: Not extended register capable + */ +#define RTL8201_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) +#define RTL8201_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) +#define RTL8201_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & RTL8201_BMSR_EXTENDED_CAPABILITY_MASK) >> RTL8201_BMSR_EXTENDED_CAPABILITY_SHIFT) /* Bitfield definition for register: PHYID1 */ /* * OUI_MSB (RO) * - * Organizationally Unique Identifier Bit 3:18. - * Always 0000000000011100. + * Composed of the 6 th to 21 st bits of the Organizationally Unique + * Identifier (OUI), respectively. */ -#define RTL8201_PHYID1_OUI_MSB_MASK (0xFFFFU) +#define RTL8201_PHYID1_OUI_MSB_MASK (0xFFFFU) #define RTL8201_PHYID1_OUI_MSB_SHIFT (0U) -#define RTL8201_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8201_PHYID1_OUI_MSB_MASK) >> RTL8201_PHYID1_OUI_MSB_SHIFT) +#define RTL8201_PHYID1_OUI_MSB_GET(x) (((uint16_t)(x) & RTL8201_PHYID1_OUI_MSB_MASK) >> RTL8201_PHYID1_OUI_MSB_SHIFT) /* Bitfield definition for register: PHYID2 */ /* * OUI_LSB (RO) * - * Organizationally Unique Identifier Bit 19:24. - * Always 110010. + * Assigned to the 0 through 5 th bits of the OUI. RO 110010 + */ +#define RTL8201_PHYID2_OUI_LSB_MASK (0xFC00U) +#define RTL8201_PHYID2_OUI_LSB_SHIFT (10U) +#define RTL8201_PHYID2_OUI_LSB_GET(x) (((uint16_t)(x) & RTL8201_PHYID2_OUI_LSB_MASK) >> RTL8201_PHYID2_OUI_LSB_SHIFT) + +/* + * MODEL_NUMBER (RO) + * + * Model Number + */ +#define RTL8201_PHYID2_MODEL_NUMBER_MASK (0x3F0U) +#define RTL8201_PHYID2_MODEL_NUMBER_SHIFT (4U) +#define RTL8201_PHYID2_MODEL_NUMBER_GET(x) (((uint16_t)(x) & RTL8201_PHYID2_MODEL_NUMBER_MASK) >> RTL8201_PHYID2_MODEL_NUMBER_SHIFT) + +/* + * REVISION_NUMBER (RO) + * + * Revision Number + */ +#define RTL8201_PHYID2_REVISION_NUMBER_MASK (0xFU) +#define RTL8201_PHYID2_REVISION_NUMBER_SHIFT (0U) +#define RTL8201_PHYID2_REVISION_NUMBER_GET(x) (((uint16_t)(x) & RTL8201_PHYID2_REVISION_NUMBER_MASK) >> RTL8201_PHYID2_REVISION_NUMBER_SHIFT) + +/* Bitfield definition for register: RMSR_P7 */ +/* + * RG_RMII_CLKDIR (RW) + * + * This Bit Sets the Type of TXC in RMII Mode. + * 0: Output + * 1: Input + */ +#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK (0x1000U) +#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT (12U) +#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT) & RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK) +#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK) >> RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT) + +/* + * RG_RMII_TX_OFFSET (RW) + * + * Adjust RMII TX Interface Timing. */ -#define RTL8201_PHYID2_OUI_MSB_MASK (0xFC00U) -#define RTL8201_PHYID2_OUI_MSB_SHIFT (10U) -#define RTL8201_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8201_PHYID2_OUI_MSB_MASK) >> RTL8201_PHYID2_OUI_MSB_SHIFT) +#define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_MASK (0xF00U) +#define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SHIFT (8U) +#define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SHIFT) & RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_MASK) +#define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_MASK) >> RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SHIFT) + +/* + * RG_RMII_RX_OFFSET (RW) + * + * Adjust RMII RX Interface Timing. + */ +#define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_MASK (0xF0U) +#define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SHIFT (4U) +#define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SHIFT) & RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_MASK) +#define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_MASK) >> RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SHIFT) + +/* + * RMII_MODE (RW) + * + * 0: MII Mode + * 1: RMII Mode + */ +#define RTL8201_RMSR_P7_RMII_MODE_MASK (0x8U) +#define RTL8201_RMSR_P7_RMII_MODE_SHIFT (3U) +#define RTL8201_RMSR_P7_RMII_MODE_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RMII_MODE_SHIFT) & RTL8201_RMSR_P7_RMII_MODE_MASK) +#define RTL8201_RMSR_P7_RMII_MODE_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RMII_MODE_MASK) >> RTL8201_RMSR_P7_RMII_MODE_SHIFT) + +/* + * RG_RMII_RXDV_SEL (RW) + * + * 0: CRS/CRS_DV pin is CRS_DV signal + * 1: CRS/CRS_DV pin is RXDV signal + */ +#define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_MASK (0x4U) +#define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SHIFT (2U) +#define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SHIFT) & RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_MASK) +#define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_MASK) >> RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SHIFT) + +/* + * RG_RMII_RXDSEL (RW) + * + * 0: RMII data only + * 1: RMII data with SSD Error + */ +#define RTL8201_RMSR_P7_RG_RMII_RXDSEL_MASK (0x2U) +#define RTL8201_RMSR_P7_RG_RMII_RXDSEL_SHIFT (1U) +#define RTL8201_RMSR_P7_RG_RMII_RXDSEL_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_RXDSEL_SHIFT) & RTL8201_RMSR_P7_RG_RMII_RXDSEL_MASK) +#define RTL8201_RMSR_P7_RG_RMII_RXDSEL_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_RXDSEL_MASK) >> RTL8201_RMSR_P7_RG_RMII_RXDSEL_SHIFT) + +/* Bitfield definition for register: PAGESEL */ +/* + * PAGE_SEL (RW) + * + * Select Page Address: 00000000~11111111. + */ +#define RTL8201_PAGESEL_PAGE_SEL_MASK (0xFFU) +#define RTL8201_PAGESEL_PAGE_SEL_SHIFT (0U) +#define RTL8201_PAGESEL_PAGE_SEL_SET(x) (((uint16_t)(x) << RTL8201_PAGESEL_PAGE_SEL_SHIFT) & RTL8201_PAGESEL_PAGE_SEL_MASK) +#define RTL8201_PAGESEL_PAGE_SEL_GET(x) (((uint16_t)(x) & RTL8201_PAGESEL_PAGE_SEL_MASK) >> RTL8201_PAGESEL_PAGE_SEL_SHIFT) + + + #endif /* HPM_RTL8201_REGS_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/enet_phy/rtl8211/CMakeLists.txt b/common/libraries/hpm_sdk/components/enet_phy/rtl8211/CMakeLists.txt index 4bb23157..917f0e96 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/rtl8211/CMakeLists.txt +++ b/common/libraries/hpm_sdk/components/enet_phy/rtl8211/CMakeLists.txt @@ -1,6 +1,9 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause +sdk_compile_definitions(-DRGMII=1) +sdk_compile_definitions(-D__USE_RTL8211=1) + sdk_inc(.) +sdk_inc(../) sdk_src(hpm_rtl8211.c) - diff --git a/common/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c b/common/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c index 09094ca2..5acc819d 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c +++ b/common/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c @@ -1,69 +1,72 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_enet_drv.h" #include "hpm_rtl8211_regs.h" #include "hpm_rtl8211.h" #include "board.h" -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- + * * Interal API - *---------------------------------------------------------------------*/ -static bool rtl8211_id_check(ENET_Type *ptr) + *--------------------------------------------------------------------- + */ +static bool rtl8211_check_id(ENET_Type *ptr) { uint16_t id1, id2; - id1 = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYID1); - id2 = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYID2); + id1 = enet_read_phy(ptr, PHY_ADDR, RTL8211_PHYID1); + id2 = enet_read_phy(ptr, PHY_ADDR, RTL8211_PHYID2); - if (RTL8211_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && RTL8211_PHYID2_OUI_MSB_GET(id2) == PHY_ID2) { + if (RTL8211_PHYID1_OUI_MSB_GET(id1) == PHY_ID1 && RTL8211_PHYID2_OUI_LSB_GET(id2) == PHY_ID2) { return true; } else { return false; } } -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * API - *---------------------------------------------------------------------*/ -uint16_t rtl8211_register_check(ENET_Type *ptr, uint32_t addr) -{ - return enet_read_phy(ptr, PHY_ADDR, addr); -} - + *--------------------------------------------------------------------- + */ void rtl8211_reset(ENET_Type *ptr) { uint16_t data; /* PHY reset */ - enet_write_phy(ptr, PHY_ADDR, RTL8211_REG_BMCR, RTL8211_BMCR_RESET_SET(1)); + enet_write_phy(ptr, PHY_ADDR, RTL8211_BMCR, RTL8211_BMCR_RESET_SET(1)); /* wait until the reset is completed */ do { - data = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_BMCR); + data = enet_read_phy(ptr, PHY_ADDR, RTL8211_BMCR); } while (RTL8211_BMCR_RESET_GET(data)); } void rtl8211_basic_mode_default_config(ENET_Type *ptr, rtl8211_config_t *config) { - config->loopback = 0; /* Enable PCS loopback mode */ - config->speed = 1; /* reserved:3/2; 100mbps: 1; 10mbps: 0 */ - config->auto_negotiation = 1; /* Enable Auto-Negotiation */ - config->duplex_mode = 1; /* Full duplex mode */ + config->loopback = 0; /* Disable PCS loopback mode */ + #if __DISABLE_AUTO_NEGO + config->auto_negotiation = false; /* Disable Auto-Negotiation */ + config->speed = enet_phy_port_speed_100mbps; + config->duplex = enet_phy_duplex_full; + #else + config->auto_negotiation = 1; /* Enable Auto-Negotiation */ + #endif } bool rtl8211_basic_mode_init(ENET_Type *ptr, rtl8211_config_t *config) { - uint16_t para = 0; + uint16_t data = 0; - para |= RTL8211_BMCR_RESET_SET(0) /* Normal operation */ + data |= RTL8211_BMCR_RESET_SET(0) /* Normal operation */ | RTL8211_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ | RTL8211_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ | RTL8211_BMCR_PWD_SET(0) /* Normal operation */ @@ -72,50 +75,27 @@ bool rtl8211_basic_mode_init(ENET_Type *ptr, rtl8211_config_t *config) | RTL8211_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ if (config->auto_negotiation == 0) { - para |= RTL8211_BMCR_SPEED0_SET(config->speed) | RTL8211_BMCR_SPEED1_SET(config->speed >> 1); + data |= RTL8211_BMCR_SPEED0_SET(config->speed) | RTL8211_BMCR_SPEED1_SET(config->speed >> 1); /* Set port speed */ + data |= RTL8211_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ } - enet_write_phy(ptr, PHY_ADDR, RTL8211_REG_BMCR, para); + enet_write_phy(ptr, PHY_ADDR, RTL8211_BMCR, data); /* check the id of rtl8211 */ - if (rtl8211_id_check(ptr) == false) { + if (rtl8211_check_id(ptr) == false) { return false; } return true; } -void rtl8211_auto_negotiation_init(void) -{ - /* TODO */ -} - - -void rtl8211_read_status(ENET_Type *ptr) -{ - uint16_t status; - - status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_BMSR); - printf("BMSR: %08x\n", status); - status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_GBSR); - printf("GBSR: %08x\n", status); - status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_GBESR); - printf("GBESR: %08x\n", status); - status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYSR); - printf("PHYSR: %08x\n", status); - status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_RXERC); - printf("RXERC: %08x\n", status); - - status = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYCR); - printf("PHYCR, %x\n", status); -} -void rtl8211_control_config(ENET_Type *ptr) +void rtl8211_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) { - uint16_t para = 0; - - para = enet_read_phy(ptr, PHY_ADDR, RTL8211_REG_PHYCR) | (1 << 10); - - enet_write_phy(ptr, PHY_ADDR, RTL8211_REG_PHYCR, para); + uint16_t data; + data = enet_read_phy(ptr, PHY_ADDR, RTL8211_PHYSR); + status->enet_phy_link = RTL8211_PHYSR_LINK_REAL_TIME_GET(data); + status->enet_phy_speed = RTL8211_PHYSR_SPEED_GET(data) == 0 ? enet_phy_port_speed_10mbps : RTL8211_PHYSR_SPEED_GET(data) == 1 ? enet_phy_port_speed_100mbps : enet_phy_port_speed_1000mbps; + status->enet_phy_duplex = RTL8211_PHYSR_DUPLEX_GET(data); } \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h b/common/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h index 5b208573..ccc4d5fc 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h +++ b/common/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,42 +8,46 @@ #ifndef HPM_RTL8211_H #define HPM_RTL8211_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ -#include "stdint.h" - -/*---------------------------------------------------------------------* + *--------------------------------------------------------------------- + */ +#include "hpm_enet_phy.h" +#include "hpm_common.h" +#include "hpm_enet_regs.h" +/*--------------------------------------------------------------------- + * * Macro Const Definitions - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #define PHY_ADDR (2U) #define PHY_ID1 (0x001CU) #define PHY_ID2 (0x32U) -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Typedef Struct Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ typedef struct { bool loopback; uint8_t speed; bool auto_negotiation; - uint8_t duplex_mode; + uint8_t duplex; } rtl8211_config_t; #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Exported Functions - *---------------------------------------------------------------------*/ -uint16_t rtl8211_check(ENET_Type *ptr, uint32_t addr); + *--------------------------------------------------------------------- + */ void rtl8211_reset(ENET_Type *ptr); void rtl8211_basic_mode_default_config(ENET_Type *ptr, rtl8211_config_t *config); bool rtl8211_basic_mode_init(ENET_Type *ptr, rtl8211_config_t *config); -void rtl8211_read_status(ENET_Type *ptr); -void rtl8211_control_config(ENET_Type *ptr); +void rtl8211_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); #if defined(__cplusplus) } #endif /* __cplusplus */ -#endif /* HPM_RTL8211_H */ \ No newline at end of file +#endif /* HPM_RTL8211_H */ diff --git a/common/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h b/common/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h index 567c76e7..1d5ad505 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h +++ b/common/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h @@ -1,48 +1,28 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021-2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ + #ifndef HPM_RTL8211_REGS_H #define HPM_RTL8211_REGS_H - /* RTL Register Definitions */ -#define RTL8211_REG_BMCR (0U) /* Basic Mode Control Register */ -#define RTL8211_REG_BMSR (1U) /* Basic Mode Status Register */ -#define RTL8211_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ -#define RTL8211_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ -#define RTL8211_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ -#define RTL8211_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ -#define RTL8211_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ -#define RTL8211_REG_ANNPTR (7U) /* Auto-Negotiation Next Page Transmit Register */ -#define RTL8211_REG_ANNPRR (8U) /* Auto-Negotiation Next Page Receive Register */ -#define RTL8211_REG_GBCR (9U) /* 1000Base-T Control Register */ -#define RTL8211_REG_GBSR (10U) /* 1000Base-T Status Register */ - -#define RTL8211_REG_MACR (13U) /* MMD Access Control Register */ -#define RTL8211_REG_MAADR (14U) /* MMD Access Address Data Register */ -#define RTL8211_REG_GBESR (15U) /* 1000Base-T Extended Status Register */ -#define RTL8211_REG_PHYCR (16U) /* PHY Specific Control Register */ -#define RTL8211_REG_PHYSR (17U) /* PHY Specific Status Register */ -#define RTL8211_REG_INER (18U) /* Interrupt Enable Register */ -#define RTL8211_REG_INSR (19U) /* Interrupt Status Register */ -#define RTL8211_REG_RXERC (24U) /* Receive Error Counter */ -#define RTL8211_REG_PAGSEL (31U) /* Page Select Register */ - -/* RTL MMD Register Definitions */ -#define RTL8211_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ -#define RTL8211_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ -#define RTL8211_MMD_REG_EEECR (20U) /* EEE Capability Register */ -#define RTL8211_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ -#define RTL8211_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ -#define RTL8211_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ +typedef enum { + RTL8211_BMCR = 0, /* 0x0: Basic Mode Control Register */ + RTL8211_BMSR = 1, /* 0x1: (Basic Mode Status Register */ + RTL8211_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */ + RTL8211_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */ + RTL8211_PHYSR = 17, /* 0x11: PHY Specific Status Register */ +} RTL8211_REG_Type; + /* Bitfield definition for register: BMCR */ /* - * Reset (RW) + * RESET (RW/SC) * + * Reset. * 1: PHY reset * 0: Normal operation * Register 0 (BMCR) and register 1 (BMSR) will return to default @@ -50,34 +30,38 @@ * This action may change the internal PHY state and the state of the * physical link associated with the PHY. */ -#define RTL8211_BMCR_RESET_MASK (0x8000U) +#define RTL8211_BMCR_RESET_MASK (0x8000U) #define RTL8211_BMCR_RESET_SHIFT (15U) -#define RTL8211_BMCR_RESET_SET(x) (((uint32_t)(x) << RTL8211_BMCR_RESET_SHIFT) & RTL8211_BMCR_RESET_MASK) -#define RTL8211_BMCR_RESET_GET(x) (((uint32_t)(x) & RTL8211_BMCR_RESET_MASK) >> RTL8211_BMCR_RESET_SHIFT) +#define RTL8211_BMCR_RESET_SET(x) (((uint16_t)(x) << RTL8211_BMCR_RESET_SHIFT) & RTL8211_BMCR_RESET_MASK) +#define RTL8211_BMCR_RESET_GET(x) (((uint16_t)(x) & RTL8211_BMCR_RESET_MASK) >> RTL8211_BMCR_RESET_SHIFT) /* - * Loopback (RW) + * LOOPBACK (RW) * * Loopback Mode. * 1: Enable PCS loopback mode * 0: Disable PCS loopback mode */ -#define RTL8211_BMCR_LOOPBACK_MASK (0x4000U) +#define RTL8211_BMCR_LOOPBACK_MASK (0x4000U) #define RTL8211_BMCR_LOOPBACK_SHIFT (14U) -#define RTL8211_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << RTL8211_BMCR_LOOPBACK_SHIFT) & RTL8211_BMCR_LOOPBACK_MASK) -#define RTL8211_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & RTL8211_BMCR_LOOPBACK_MASK) >> RTL8211_BMCR_LOOPBACK_SHIFT) +#define RTL8211_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << RTL8211_BMCR_LOOPBACK_SHIFT) & RTL8211_BMCR_LOOPBACK_MASK) +#define RTL8211_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & RTL8211_BMCR_LOOPBACK_MASK) >> RTL8211_BMCR_LOOPBACK_SHIFT) /* - * Speed[0] (RW) + * SPEED0 (RW) * - * Speed Select Bit 0. - * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 - * determine device speed selection. + * Speed Select (Bits 6, 13): + * When auto-negotiation is disabled writing to this bit allows the port + * speed to be selected. + * 11 = Reserved + * 10 = Reserved + * 1 = 100 Mbps + * 0 = 10 Mbps */ -#define RTL8211_BMCR_SPEED0_MASK (0x2000U) +#define RTL8211_BMCR_SPEED0_MASK (0x2000U) #define RTL8211_BMCR_SPEED0_SHIFT (13U) -#define RTL8211_BMCR_SPEED0_SET(x) (((uint32_t)(x) << RTL8211_BMCR_SPEED0_SHIFT) & RTL8211_BMCR_SPEED0_MASK) -#define RTL8211_BMCR_SPEED0_GET(x) (((uint32_t)(x) & RTL8211_BMCR_SPEED0_MASK) >> RTL8211_BMCR_SPEED0_SHIFT) +#define RTL8211_BMCR_SPEED0_SET(x) (((uint16_t)(x) << RTL8211_BMCR_SPEED0_SHIFT) & RTL8211_BMCR_SPEED0_MASK) +#define RTL8211_BMCR_SPEED0_GET(x) (((uint16_t)(x) & RTL8211_BMCR_SPEED0_MASK) >> RTL8211_BMCR_SPEED0_SHIFT) /* * ANE (RW) @@ -86,10 +70,10 @@ * 1: Enable Auto-Negotiation * 0: Disable Auto-Negotiation */ -#define RTL8211_BMCR_ANE_MASK (0x1000U) +#define RTL8211_BMCR_ANE_MASK (0x1000U) #define RTL8211_BMCR_ANE_SHIFT (12U) -#define RTL8211_BMCR_ANE_SET(x) (((uint32_t)(x) << RTL8211_BMCR_ANE_SHIFT) & RTL8211_BMCR_ANE_MASK) -#define RTL8211_BMCR_ANE_GET(x) (((uint32_t)(x) & RTL8211_BMCR_ANE_MASK) >> RTL8211_BMCR_ANE_SHIFT) +#define RTL8211_BMCR_ANE_SET(x) (((uint16_t)(x) << RTL8211_BMCR_ANE_SHIFT) & RTL8211_BMCR_ANE_MASK) +#define RTL8211_BMCR_ANE_GET(x) (((uint16_t)(x) & RTL8211_BMCR_ANE_MASK) >> RTL8211_BMCR_ANE_SHIFT) /* * PWD (RW) @@ -99,77 +83,244 @@ * is down) * 0: Normal operation */ -#define RTL8211_BMCR_PWD_MASK (0x0800U) +#define RTL8211_BMCR_PWD_MASK (0x800U) #define RTL8211_BMCR_PWD_SHIFT (11U) -#define RTL8211_BMCR_PWD_SET(x) (((uint32_t)(x) << RTL8211_BMCR_PWD_SHIFT) & RTL8211_BMCR_PWD_MASK) -#define RTL8211_BMCR_PWD_GET(x) (((uint32_t)(x) & RTL8211_BMCR_PWD_MASK) >> RTL8211_BMCR_PWD_SHIFT) +#define RTL8211_BMCR_PWD_SET(x) (((uint16_t)(x) << RTL8211_BMCR_PWD_SHIFT) & RTL8211_BMCR_PWD_MASK) +#define RTL8211_BMCR_PWD_GET(x) (((uint16_t)(x) & RTL8211_BMCR_PWD_MASK) >> RTL8211_BMCR_PWD_SHIFT) /* - * Isolate (RW) + * ISOLATE (RW) * * Isolate. * 1: RGMII/GMII interface is isolated; the serial management interface * (MDC, MDIO) is still active. When this bit is asserted, the - * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and - * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. + * RTL8211E-VB(VL)/RTL8211EG-VB ignores TXD[7:0], and TXCLT + * inputs, and presents a high impedance on TXC, RXC, RXCLT, + * RXD[7:0]. * 0: Normal operation */ -#define RTL8211_BMCR_ISOLATE_MASK (0x0400U) +#define RTL8211_BMCR_ISOLATE_MASK (0x400U) #define RTL8211_BMCR_ISOLATE_SHIFT (10U) -#define RTL8211_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << RTL8211_BMCR_ISOLATE_SHIFT) & RTL8211_BMCR_ISOLATE_MASK) -#define RTL8211_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & RTL8211_BMCR_ISOLATE_MASK) >> RTL8211_BMCR_ISOLATE_SHIFT) +#define RTL8211_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << RTL8211_BMCR_ISOLATE_SHIFT) & RTL8211_BMCR_ISOLATE_MASK) +#define RTL8211_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & RTL8211_BMCR_ISOLATE_MASK) >> RTL8211_BMCR_ISOLATE_SHIFT) /* - * Restart_AN (RW) + * RESTART_AN (RW/SC) * * Restart Auto-Negotiation. * 1: Restart Auto-Negotiation * 0: Normal operation */ -#define RTL8211_BMCR_RESTART_AN_MASK (0x0200U) +#define RTL8211_BMCR_RESTART_AN_MASK (0x200U) #define RTL8211_BMCR_RESTART_AN_SHIFT (9U) -#define RTL8211_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << RTL8211_BMCR_RESTART_AN_SHIFT) & RTL8211_BMCR_RESTART_AN_MASK) -#define RTL8211_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & RTL8211_BMCR_RESTART_AN_MASK) >> RTL8211_BMCR_RESTART_AN_SHIFT) +#define RTL8211_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << RTL8211_BMCR_RESTART_AN_SHIFT) & RTL8211_BMCR_RESTART_AN_MASK) +#define RTL8211_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & RTL8211_BMCR_RESTART_AN_MASK) >> RTL8211_BMCR_RESTART_AN_SHIFT) /* - * Duplex (RW) + * DUPLEX (RW) * * Duplex Mode. * 1: Full Duplex operation * 0: Half Duplex operation * This bit is valid only in force mode, i.e., NWay is disabled. */ -#define RTL8211_BMCR_DUPLEX_MASK (0x0100U) +#define RTL8211_BMCR_DUPLEX_MASK (0x100U) #define RTL8211_BMCR_DUPLEX_SHIFT (8U) -#define RTL8211_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << RTL8211_BMCR_DUPLEX_SHIFT) & RTL8211_BMCR_DUPLEX_MASK) -#define RTL8211_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & RTL8211_BMCR_DUPLEX_MASK) >> RTL8211_BMCR_DUPLEX_SHIFT) +#define RTL8211_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << RTL8211_BMCR_DUPLEX_SHIFT) & RTL8211_BMCR_DUPLEX_MASK) +#define RTL8211_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & RTL8211_BMCR_DUPLEX_MASK) >> RTL8211_BMCR_DUPLEX_SHIFT) /* - * Collision Test (RW) + * COLLISION_TEST (RW) * * Collision Test. * 1: Collision test enabled * 0: Normal operation - * When set, this bit will cause the COL signal to be asserted in response - * to the assertion of TXEN within 512-bit times. The COL signal will be - * de-asserted within 4-bit times in response to the de-assertion of - * TXEN. */ -#define RTL8211_BMCR_COLLISION_TEST_MASK (0x0080U) +#define RTL8211_BMCR_COLLISION_TEST_MASK (0x80U) #define RTL8211_BMCR_COLLISION_TEST_SHIFT (7U) -#define RTL8211_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << RTL8211_BMCR_COLLISION_TEST_SHIFT) & RTL8211_BMCR_COLLISION_TEST_MASK) -#define RTL8211_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & RTL8211_BMCR_COLLISION_TEST_MASK) >> RTL8211_BMCR_COLLISION_TEST_SHIFT) +#define RTL8211_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << RTL8211_BMCR_COLLISION_TEST_SHIFT) & RTL8211_BMCR_COLLISION_TEST_MASK) +#define RTL8211_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & RTL8211_BMCR_COLLISION_TEST_MASK) >> RTL8211_BMCR_COLLISION_TEST_SHIFT) /* - * Speed[1] (RW) + * SPEED1 (RW) * * Speed Select Bit 1. - * Refer to bit 0.13. + * Refer to bit 13. */ -#define RTL8211_BMCR_SPEED1_MASK (0x0040U) +#define RTL8211_BMCR_SPEED1_MASK (0x40U) #define RTL8211_BMCR_SPEED1_SHIFT (6U) -#define RTL8211_BMCR_SPEED1_SET(x) (((uint32_t)(x) << RTL8211_BMCR_SPEED1_SHIFT) & RTL8211_BMCR_SPEED1_MASK) -#define RTL8211_BMCR_SPEED1_GET(x) (((uint32_t)(x) & RTL8211_BMCR_SPEED1_MASK) >> RTL8211_BMCR_SPEED1_SHIFT) +#define RTL8211_BMCR_SPEED1_SET(x) (((uint16_t)(x) << RTL8211_BMCR_SPEED1_SHIFT) & RTL8211_BMCR_SPEED1_MASK) +#define RTL8211_BMCR_SPEED1_GET(x) (((uint16_t)(x) & RTL8211_BMCR_SPEED1_MASK) >> RTL8211_BMCR_SPEED1_SHIFT) + +/* Bitfield definition for register: BMSR */ +/* + * 100BASE_T4 (RO) + * + * 100Base-T4 Capability. + * The RTL8211E-VB(VL)/RTL8211EG-VB does not support + * 100Base-T4 mode. This bit should always be 0. + */ +#define RTL8211_BMSR_100BASE_T4_MASK (0x8000U) +#define RTL8211_BMSR_100BASE_T4_SHIFT (15U) +#define RTL8211_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & RTL8211_BMSR_100BASE_T4_MASK) >> RTL8211_BMSR_100BASE_T4_SHIFT) + +/* + * 100BASE_TX_FULL (RO) + * + * 100Base-TX Full Duplex Capability. + * 1: Device is able to perform 100Base-TX in full duplex mode + * 0: Device is not able to perform 100Base-TX in full duplex mode + */ +#define RTL8211_BMSR_100BASE_TX_FULL_MASK (0x4000U) +#define RTL8211_BMSR_100BASE_TX_FULL_SHIFT (14U) +#define RTL8211_BMSR_100BASE_TX_FULL_GET(x) (((uint16_t)(x) & RTL8211_BMSR_100BASE_TX_FULL_MASK) >> RTL8211_BMSR_100BASE_TX_FULL_SHIFT) + +/* + * 100BASE_TX_HALF (RO) + * + * 100Base-TX Half Duplex Capability. + * 1: Device is able to perform 100Base-TX in half duplex mode + * 0: Device is not able to perform 100Base-TX in half duplex mode + */ +#define RTL8211_BMSR_100BASE_TX_HALF_MASK (0x2000U) +#define RTL8211_BMSR_100BASE_TX_HALF_SHIFT (13U) +#define RTL8211_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & RTL8211_BMSR_100BASE_TX_HALF_MASK) >> RTL8211_BMSR_100BASE_TX_HALF_SHIFT) + +/* + * 10BASE_T_FULL (RO) + * + * 10Base-T Full Duplex Capability. + * 1: Device is able to perform 10Base-T in full duplex mode. + * 0: Device is not able to perform 10Base-T in full duplex mode. + */ +#define RTL8211_BMSR_10BASE_T_FULL_MASK (0x1000U) +#define RTL8211_BMSR_10BASE_T_FULL_SHIFT (12U) +#define RTL8211_BMSR_10BASE_T_FULL_GET(x) (((uint16_t)(x) & RTL8211_BMSR_10BASE_T_FULL_MASK) >> RTL8211_BMSR_10BASE_T_FULL_SHIFT) + +/* + * 10BASE_T_HALF (RO) + * + * 10Base-T Half Duplex Capability. + * 1: Device is able to perform 10Base-T in half duplex mode + * 0: Device is not able to perform 10Base-T in half duplex mode + */ +#define RTL8211_BMSR_10BASE_T_HALF_MASK (0x800U) +#define RTL8211_BMSR_10BASE_T_HALF_SHIFT (11U) +#define RTL8211_BMSR_10BASE_T_HALF_GET(x) (((uint16_t)(x) & RTL8211_BMSR_10BASE_T_HALF_MASK) >> RTL8211_BMSR_10BASE_T_HALF_SHIFT) + +/* + * 10BASE_T2_FULL (RO) + * + * 10Base-T2 Full Duplex Capability. + * The RTL8211E-VB(VL)/RTL8211EG-VB does not support + * 10Base-T2 mode and this bit should always be 0. + */ +#define RTL8211_BMSR_10BASE_T2_FULL_MASK (0x400U) +#define RTL8211_BMSR_10BASE_T2_FULL_SHIFT (10U) +#define RTL8211_BMSR_10BASE_T2_FULL_GET(x) (((uint16_t)(x) & RTL8211_BMSR_10BASE_T2_FULL_MASK) >> RTL8211_BMSR_10BASE_T2_FULL_SHIFT) + +/* + * 10BASE_T2_HALF (RO) + * + * 10Base-T2 Half Duplex Capability. + * The RTL8211E-VB(VL)/RTL8211EG-VB does not support + * 10Base-T2 mode. This bit should always be 0. + */ +#define RTL8211_BMSR_10BASE_T2_HALF_MASK (0x200U) +#define RTL8211_BMSR_10BASE_T2_HALF_SHIFT (9U) +#define RTL8211_BMSR_10BASE_T2_HALF_GET(x) (((uint16_t)(x) & RTL8211_BMSR_10BASE_T2_HALF_MASK) >> RTL8211_BMSR_10BASE_T2_HALF_SHIFT) + +/* + * 1000BASE_T_EXTENDED_STATUS (RO) + * + * 1000Base-T Extended Status Register. + * 1: Device supports Extended Status Register 0x0F (15) + * 0: Device does not support Extended Status Register 0x0F + * This register is read-only and is always set to 1. + */ +#define RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_MASK (0x100U) +#define RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_SHIFT (8U) +#define RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_GET(x) (((uint16_t)(x) & RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_MASK) >> RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_SHIFT) + +/* + * PREAMBLE_SUPPRESSION (RO) + * + * Preamble Suppression Capability (Permanently On). + * The RTL8211E-VB(VL)/RTL8211EG-VB always accepts + * transactions with preamble suppressed. + */ +#define RTL8211_BMSR_PREAMBLE_SUPPRESSION_MASK (0x40U) +#define RTL8211_BMSR_PREAMBLE_SUPPRESSION_SHIFT (6U) +#define RTL8211_BMSR_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & RTL8211_BMSR_PREAMBLE_SUPPRESSION_MASK) >> RTL8211_BMSR_PREAMBLE_SUPPRESSION_SHIFT) + +/* + * AUTO_NEGOTIATION_COMPLETE (RO) + * + * Auto-Negotiation Complete. + * 1: Auto-Negotiation process complete, and contents of registers + * 5, 6, 8, and 10 are valid + * 0: Auto-Negotiation process not complete + */ +#define RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) +#define RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) +#define RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) + +/* + * REMOTE_FAULT (RC) + * + * Remote Fault. + * 1: Remote fault condition detected (cleared on read or by reset). + * Indication or notification of remote fault from Link Partner + * 0: No remote fault condition detected + */ +#define RTL8211_BMSR_REMOTE_FAULT_MASK (0x10U) +#define RTL8211_BMSR_REMOTE_FAULT_SHIFT (4U) +#define RTL8211_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & RTL8211_BMSR_REMOTE_FAULT_MASK) >> RTL8211_BMSR_REMOTE_FAULT_SHIFT) + +/* + * AUTO_NEGOTIATION_ABILITY (RO) + * + * Auto Configured Link. + * 1: Device is able to perform Auto-Negotiation + * 0: Device is not able to perform Auto-Negotiation + */ +#define RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) +#define RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) +#define RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) + +/* + * LINK_STATUS (RO) + * + * Link Status. + * 1: Linked + * 0: Not Linked + * This register indicates whether the link was lost since the last read. + * For the current link status, either read this register twice or read + * register bit 17.10 Link Real Time. + */ +#define RTL8211_BMSR_LINK_STATUS_MASK (0x4U) +#define RTL8211_BMSR_LINK_STATUS_SHIFT (2U) +#define RTL8211_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & RTL8211_BMSR_LINK_STATUS_MASK) >> RTL8211_BMSR_LINK_STATUS_SHIFT) + +/* + * JABBER_DETECT (RC) + * + * Jabber Detect. + * 1: Jabber condition detected + * 0: No Jabber occurred + */ +#define RTL8211_BMSR_JABBER_DETECT_MASK (0x2U) +#define RTL8211_BMSR_JABBER_DETECT_SHIFT (1U) +#define RTL8211_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & RTL8211_BMSR_JABBER_DETECT_MASK) >> RTL8211_BMSR_JABBER_DETECT_SHIFT) + +/* + * EXTENDED_CAPABILITY (RO) + * + * 1: Extended register capabilities, always 1 + */ +#define RTL8211_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) +#define RTL8211_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) +#define RTL8211_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & RTL8211_BMSR_EXTENDED_CAPABILITY_MASK) >> RTL8211_BMSR_EXTENDED_CAPABILITY_SHIFT) /* Bitfield definition for register: PHYID1 */ /* @@ -178,9 +329,9 @@ * Organizationally Unique Identifier Bit 3:18. * Always 0000000000011100. */ -#define RTL8211_PHYID1_OUI_MSB_MASK (0xFFFFU) +#define RTL8211_PHYID1_OUI_MSB_MASK (0xFFFFU) #define RTL8211_PHYID1_OUI_MSB_SHIFT (0U) -#define RTL8211_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8211_PHYID1_OUI_MSB_MASK) >> RTL8211_PHYID1_OUI_MSB_SHIFT) +#define RTL8211_PHYID1_OUI_MSB_GET(x) (((uint16_t)(x) & RTL8211_PHYID1_OUI_MSB_MASK) >> RTL8211_PHYID1_OUI_MSB_SHIFT) /* Bitfield definition for register: PHYID2 */ /* @@ -189,8 +340,112 @@ * Organizationally Unique Identifier Bit 19:24. * Always 110010. */ -#define RTL8211_PHYID2_OUI_MSB_MASK (0xFC00U) -#define RTL8211_PHYID2_OUI_MSB_SHIFT (10U) -#define RTL8211_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8211_PHYID2_OUI_MSB_MASK) >> RTL8211_PHYID2_OUI_MSB_SHIFT) +#define RTL8211_PHYID2_OUI_LSB_MASK (0xFC00U) +#define RTL8211_PHYID2_OUI_LSB_SHIFT (10U) +#define RTL8211_PHYID2_OUI_LSB_GET(x) (((uint16_t)(x) & RTL8211_PHYID2_OUI_LSB_MASK) >> RTL8211_PHYID2_OUI_LSB_SHIFT) + +/* + * MODEL_NUMBER (RO) + * + * Manufacture’s Model Number + */ +#define RTL8211_PHYID2_MODEL_NUMBER_MASK (0x3F0U) +#define RTL8211_PHYID2_MODEL_NUMBER_SHIFT (4U) +#define RTL8211_PHYID2_MODEL_NUMBER_GET(x) (((uint16_t)(x) & RTL8211_PHYID2_MODEL_NUMBER_MASK) >> RTL8211_PHYID2_MODEL_NUMBER_SHIFT) + +/* + * REVISION_NUMBER (RO) + * + * Revision Number + */ +#define RTL8211_PHYID2_REVISION_NUMBER_MASK (0xFU) +#define RTL8211_PHYID2_REVISION_NUMBER_SHIFT (0U) +#define RTL8211_PHYID2_REVISION_NUMBER_GET(x) (((uint16_t)(x) & RTL8211_PHYID2_REVISION_NUMBER_MASK) >> RTL8211_PHYID2_REVISION_NUMBER_SHIFT) + +/* Bitfield definition for register: PHYSR */ +/* + * SPEED (RO) + * + * Link Speed. + * 11: Reserved 10: 1000Mbps + * 01: 100Mbps 00: 10Mbps + */ +#define RTL8211_PHYSR_SPEED_MASK (0xC000U) +#define RTL8211_PHYSR_SPEED_SHIFT (14U) +#define RTL8211_PHYSR_SPEED_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_SPEED_MASK) >> RTL8211_PHYSR_SPEED_SHIFT) + +/* + * DUPLEX (RO) + * + * Full/Half Duplex Mode. + * 1: Full duplex 0: Half duplex + */ +#define RTL8211_PHYSR_DUPLEX_MASK (0x2000U) +#define RTL8211_PHYSR_DUPLEX_SHIFT (13U) +#define RTL8211_PHYSR_DUPLEX_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_DUPLEX_MASK) >> RTL8211_PHYSR_DUPLEX_SHIFT) + +/* + * PAGE_RECEIVED (RC) + * + * New Page Received. + * 1: Page received 0: Page not received + */ +#define RTL8211_PHYSR_PAGE_RECEIVED_MASK (0x1000U) +#define RTL8211_PHYSR_PAGE_RECEIVED_SHIFT (12U) +#define RTL8211_PHYSR_PAGE_RECEIVED_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_PAGE_RECEIVED_MASK) >> RTL8211_PHYSR_PAGE_RECEIVED_SHIFT) + +/* + * SPEED_AND_DUPLEX_RESOLVED (RO) + * + * Speed and Duplex Mode Resolved. + * 1: Resolved 0: Not resolved + */ +#define RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_MASK (0x800U) +#define RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_SHIFT (11U) +#define RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_MASK) >> RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_SHIFT) + +/* + * LINK_REAL_TIME (RO) + * + * Real Time Link Status. + * 1: Link OK 0: Link not OK + */ +#define RTL8211_PHYSR_LINK_REAL_TIME_MASK (0x400U) +#define RTL8211_PHYSR_LINK_REAL_TIME_SHIFT (10U) +#define RTL8211_PHYSR_LINK_REAL_TIME_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_LINK_REAL_TIME_MASK) >> RTL8211_PHYSR_LINK_REAL_TIME_SHIFT) + +/* + * MDI_CROSSOVER_STATUS (RO) + * + * MDI/MDI Crossover Status. + * 1: MDI Crossover 0: MDI + */ +#define RTL8211_PHYSR_MDI_CROSSOVER_STATUS_MASK (0x40U) +#define RTL8211_PHYSR_MDI_CROSSOVER_STATUS_SHIFT (6U) +#define RTL8211_PHYSR_MDI_CROSSOVER_STATUS_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_MDI_CROSSOVER_STATUS_MASK) >> RTL8211_PHYSR_MDI_CROSSOVER_STATUS_SHIFT) + +/* + * PRE_LINKOK (RO) + * + * Reflects Local Receiver is OK. + * 0: Receiver is not OK + * 1: Receiver is OK + */ +#define RTL8211_PHYSR_PRE_LINKOK_MASK (0x2U) +#define RTL8211_PHYSR_PRE_LINKOK_SHIFT (1U) +#define RTL8211_PHYSR_PRE_LINKOK_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_PRE_LINKOK_MASK) >> RTL8211_PHYSR_PRE_LINKOK_SHIFT) + +/* + * JABBER_REAL_TIME (RO) + * + * Real Time Jabber Indication. + * 1: Jabber Indication 0: No jabber Indication + */ +#define RTL8211_PHYSR_JABBER_REAL_TIME_MASK (0x1U) +#define RTL8211_PHYSR_JABBER_REAL_TIME_SHIFT (0U) +#define RTL8211_PHYSR_JABBER_REAL_TIME_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_JABBER_REAL_TIME_MASK) >> RTL8211_PHYSR_JABBER_REAL_TIME_SHIFT) + + + #endif /* HPM_RTL8211_REGS_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/ipc_event_mgr/CMakeLists.txt b/common/libraries/hpm_sdk/components/ipc_event_mgr/CMakeLists.txt new file mode 100644 index 00000000..1fdf601d --- /dev/null +++ b/common/libraries/hpm_sdk/components/ipc_event_mgr/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2022 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +sdk_inc(.) +sdk_src(hpm_ipc_event_mgr.c) + +add_subdirectory_ifdef(CONFIG_IPC_EVENT_MGR_MBX mbx) diff --git a/common/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.c b/common/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.c new file mode 100644 index 00000000..100c1db7 --- /dev/null +++ b/common/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_ipc_event_mgr.h" +#include "hpm_ipc_event_mgr_mbx_internal.h" + +/***************************************************************************************************************** + * + * Definitions + * + *****************************************************************************************************************/ + +/***************************************************************************************************************** + * + * Prototypes + * + *****************************************************************************************************************/ + +/***************************************************************************************************************** + * + * Variables + * + *****************************************************************************************************************/ +static ipc_event_t s_ipc_event_table[ipc_event_table_len]; + +/***************************************************************************************************************** + * + * Codes + * + *****************************************************************************************************************/ +void ipc_init(void) +{ + ipc_init_internal(); +} + +void ipc_enable_event_interrupt(uint32_t priority) +{ + ipc_enable_event_interrupt_internal(priority); +} + +void ipc_disable_event_interrupt(void) +{ + ipc_disable_event_interrupt_internal(); +} + +hpm_stat_t ipc_register_event(ipc_event_type_t type, ipc_event_callback_t callback, void *callback_data) +{ + hpm_stat_t status; + + if ((type >= ipc_event_table_len) || (callback == NULL)) { + status = status_invalid_argument; + } else { + s_ipc_event_table[type].callback = callback; + s_ipc_event_table[type].callback_data = callback_data; + status = status_success; + } + + return status; +} + +hpm_stat_t ipc_tigger_event(ipc_event_type_t type, uint16_t event_data) +{ + hpm_stat_t status; + uint32_t remote_data; + + if (type >= ipc_event_table_len) { + status = status_invalid_argument; + } else { + remote_data = (((uint32_t)type) << 16) | event_data; + ipc_tigger_event_internal(remote_data); + status = status_success; + } + + return status; +} + +void ipc_event_handler(uint32_t data) +{ + uint16_t event_type; + uint16_t event_data; + + if (0U != data) { + event_type = (uint16_t)(data >> 16u); + event_data = (uint16_t)(data & 0x0000FFFFu); + + if (((ipc_event_type_t)event_type >= ipc_remote_start_event) && ((ipc_event_type_t)event_type < ipc_event_table_len)) { + if (s_ipc_event_table[(ipc_event_type_t)event_type].callback != NULL) { + s_ipc_event_table[(ipc_event_type_t)event_type].callback( + event_data, s_ipc_event_table[(ipc_event_type_t)event_type].callback_data); + } + } + } +} diff --git a/common/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.h b/common/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.h new file mode 100644 index 00000000..a4c6e4e9 --- /dev/null +++ b/common/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_IPC_EVENT_MGR_H +#define HPM_IPC_EVENT_MGR_H + +#ifdef __cplusplus + +extern "C" { +#endif + +/** + * @brief Type definition of event callback function pointer. + * + * @param [in] event data + * @param [in] callback context data + */ +typedef void (*ipc_event_callback_t)(uint16_t event_data, void *context); + +/** + * @brief Type definition of structure with event handler and data. + */ +typedef struct { + ipc_event_callback_t callback; /**< Pointer to callback function.*/ + void *callback_data; /**< Context data for callback.*/ +} ipc_event_t; + +/** + * @brief Type definition of event types. + */ +typedef enum { + ipc_remote_start_event = 1, + ipc_remote_rpmsg_event, + ipc_event_table_len +} ipc_event_type_t; + +/** + * @brief IPC Init. + */ +void ipc_init(void); + +/** + * @brief Enbale IPC event interrupt. + * + * @param [in] interrupt priority + */ +void ipc_enable_event_interrupt(uint32_t priority); + +/** + * @brief Disbale IPC event interrupt. + */ +void ipc_disable_event_interrupt(void); + +/** + * @brief Register IPC event + * + * @param [in] event type + * @param [in] event callback function + * @param [in] event callback data + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if the parameter is invalid + */ +hpm_stat_t ipc_register_event(ipc_event_type_t type, ipc_event_callback_t callback, void *callback_data); + +/** + * @brief Trigger IPC event + * + * @param [in] event type + * @param [in] event data + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t ipc_tigger_event(ipc_event_type_t type, uint16_t event_data); + +/*! + * @brief event handler + * + * This function is called when event received + * + * @param [in] event type and data. + */ +void ipc_event_handler(uint32_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_IPC_EVENT_MGR_H */ diff --git a/common/libraries/hpm_sdk/components/ipc_event_mgr/mbx/CMakeLists.txt b/common/libraries/hpm_sdk/components/ipc_event_mgr/mbx/CMakeLists.txt new file mode 100644 index 00000000..ad369535 --- /dev/null +++ b/common/libraries/hpm_sdk/components/ipc_event_mgr/mbx/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2022 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +sdk_inc(.) +sdk_src(hpm_ipc_event_mgr_mbx_internal.c) + diff --git a/common/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_config.h b/common/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_config.h new file mode 100644 index 00000000..f7111612 --- /dev/null +++ b/common/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_config.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_IPC_EVENT_MGR_MBX_CONFIG_H +#define HPM_IPC_EVENT_MGR_MBX_CONFIG_H + + +#if defined(HPM_FEATURE_MBX_SIDE_A) +#define HPM_MBX HPM_MBX0A +#define IRQn_MBX IRQn_MBX0A +#elif defined(HPM_FEATURE_MBX_SIDE_B) +#define HPM_MBX HPM_MBX0B +#define IRQn_MBX IRQn_MBX0B +#endif + + +#endif /* HPM_IPC_EVENT_MGR_MBX_CONFIG_H */ diff --git a/common/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.c b/common/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.c new file mode 100644 index 00000000..ebdb0e6c --- /dev/null +++ b/common/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_soc.h" +#include "hpm_mbx_drv.h" +#include "hpm_ipc_event_mgr.h" +#include "hpm_ipc_event_mgr_mbx_config.h" +#include "hpm_ipc_event_mgr_mbx_internal.h" + +/***************************************************************************************************************** + * + * Definitions + * + *****************************************************************************************************************/ + +/***************************************************************************************************************** + * + * Prototypes + * + *****************************************************************************************************************/ +static void mbx_isr(void); +SDK_DECLARE_EXT_ISR_M(IRQn_MBX, mbx_isr) + +/***************************************************************************************************************** + * + * Variables + * + *****************************************************************************************************************/ + +/***************************************************************************************************************** + * + * Codes + * + *****************************************************************************************************************/ +void ipc_init_internal(void) +{ + mbx_init(HPM_MBX); +} + +void ipc_enable_event_interrupt_internal(uint32_t priority) +{ + mbx_enable_intr(HPM_MBX, MBX_CR_RWMVIE_MASK); + intc_m_enable_irq_with_priority(IRQn_MBX, priority); +} + +void ipc_disable_event_interrupt_internal(void) +{ + mbx_disable_intr(HPM_MBX, MBX_CR_RWMVIE_MASK); + intc_m_disable_irq(IRQn_MBX); +} + +hpm_stat_t ipc_tigger_event_internal(uint32_t remote_data) +{ + return mbx_send_message(HPM_MBX, remote_data); +} + +/*! + * @brief ISR handler + * + * This function is called when data from MBX is received + */ +static void mbx_isr(void) +{ + uint32_t data; + hpm_stat_t state; + + state = mbx_retrieve_message(HPM_MBX, &data); + + if (state == status_success) { + ipc_event_handler(data); + } +} diff --git a/common/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.h b/common/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.h new file mode 100644 index 00000000..cb22df04 --- /dev/null +++ b/common/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_IPC_EVENT_MGR_MBX_INTERNAL_H +#define HPM_IPC_EVENT_MGR_MBX_INTERNAL_H + +#ifdef __cplusplus + +extern "C" { +#endif + +/** + * @brief Initial MBX. + */ +void ipc_init_internal(void); + +/** + * @brief Enbale MBX event interrupt + * + * @param [in] interrupt priority + */ +void ipc_enable_event_interrupt_internal(uint32_t priority); + +/** + * @brief Disbale MBX event interrupt + */ +void ipc_disable_event_interrupt_internal(void); + +/** + * @brief Trigger MBX event + * + * @param [in] remote data + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t ipc_tigger_event_internal(uint32_t remote_data); + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_IPC_EVENT_MGR_MBX_INTERNAL_H */ diff --git a/common/libraries/hpm_sdk/components/serial_nor/sfdp_def.h b/common/libraries/hpm_sdk/components/serial_nor/sfdp_def.h index f50cf48e..14cfbe9e 100644 --- a/common/libraries/hpm_sdk/components/serial_nor/sfdp_def.h +++ b/common/libraries/hpm_sdk/components/serial_nor/sfdp_def.h @@ -1,6 +1,6 @@ -// -// Created by hpm15 on 3/11/21. -// +/* */ +/* Created by hpm15 on 3/11/21. */ +/* */ #ifndef SFDP_DEF_H #define SFDP_DEF_H @@ -8,44 +8,42 @@ #include #include "hpm_common.h" -//! @brief Commands for probing the FLASH device +/* ! @brief Commands for probing the FLASH device */ #define kSerialFlash_ReadSFDP (0x5AU) #define kSerialFlash_ReadManufacturerId (0x9FU) -//!@brief SFDP related definitions +/* !@brief SFDP related definitions */ #define SFDP_SIGNATURE (0x50444653UL) /* ASCII: SFDP */ #define kSfdp_Version_Major_1_0 (1U) -#define kSfdp_Version_Minor_0 (0U) // JESD216 -#define kSfdp_Version_Minor_A (5U) // JESD216A -#define kSfdp_Version_Minor_B (6U) // JESD216B -#define kSfdp_Version_Minor_C (7U) // JESD216C -#define kSfdp_Version_Minor_D (8U) // JESD216D +#define kSfdp_Version_Minor_0 (0U) /* JESD216 */ +#define kSfdp_Version_Minor_A (5U) /* JESD216A */ +#define kSfdp_Version_Minor_B (6U) /* JESD216B */ +#define kSfdp_Version_Minor_C (7U) /* JESD216C */ +#define kSfdp_Version_Minor_D (8U) /* JESD216D */ #define kSfdp_BasicProtocolTableSize_Rev0 (36U) #define kSfdp_BasicProtocolTableSize_RevA (64U) #define kSfdp_BasicProtocolTableSize_RevB kSfdp_BasicProtocolTableSize_RevA #define kSfdp_BasicProtocolTableSize_RevC (80U) #define kSfdp_BasicProtocolTableSize_RevD kSfdp_BasicProtocolTableSize_RevC -typedef union _sfdp_header -{ +typedef union _sfdp_header { uint32_t words[2]; - struct - { + struct { uint32_t signature; uint8_t minor_rev; uint8_t major_rev; uint8_t param_hdr_num; - uint8_t sfdp_access_protocol; // Defined in JESD216C, reserved for older version + uint8_t sfdp_access_protocol; /* Defined in JESD216C, reserved for older version */ }; } sfdp_header_t; -//!@brief SFDP parameter Type ID definitions +/* !@brief SFDP parameter Type ID definitions */ #define kParameterID_BasicSpiProtocol (0xFF00U) -// New Table added in JESD216B +/* New Table added in JESD216B */ #define kParameterID_SectorMap (0xFF81U) #define kParameterID_4ByteAddressInstructionTable (0xFF84U) -// New Table added in JESD216C +/* New Table added in JESD216C */ #define kParameterID_xSpiProfile1_0 (0xFF05U) #define kParameterID_xSpiOrofile2_0 (0xFF06U) #define kParameterID_StaCtrlCfgRegMap (0xFF87U) @@ -60,16 +58,14 @@ typedef union _sfdp_header #define kCommandExtensionInverseOfCommand (1U) #define kCommandAndCommandExtension16BitWord (2U) -//!@brief Supported methods to enter 8-8-8 mode from 1-1-1 mode, More details please refer to JESD216C/D +/* !@brief Supported methods to enter 8-8-8 mode from 1-1-1 mode, More details please refer to JESD216C/D */ #define kEnterOctalMode_Option0 HPM_BITSMASK(1U, 1) #define kEnterOctalMode_Option1 HPM_BITSMASK(1U, 2) -//!@brief SFDP Parameter Header, see JESD216D doc for more details -typedef union _sfdp_parameter_header -{ +/* !@brief SFDP Parameter Header, see JESD216D doc for more details */ +typedef union _sfdp_parameter_header { uint32_t words[2]; - struct - { + struct { uint8_t parameter_id_lsb; uint8_t minor_rev; uint8_t major_rev; @@ -80,14 +76,11 @@ typedef union _sfdp_parameter_header } sfdp_parameter_header_t; -//!@brief Basic Flash Parameter Table, see JESD216D doc for more details -typedef union _jedec_flash_param_table -{ +/* !@brief Basic Flash Parameter Table, see JESD216D doc for more details */ +typedef union _jedec_flash_param_table { uint32_t words[20]; - struct - { - struct - { + struct { + struct { uint32_t erase_size : 2; uint32_t write_granularity : 1; uint32_t reserved0 : 2; @@ -100,79 +93,69 @@ typedef union _jedec_flash_param_table uint32_t supports_1_4_4_fast_read : 1; uint32_t support_1_1_4_fast_read : 1; uint32_t unused1 : 9; - } misc; // 1st word - uint32_t flash_density; // 2nd word - struct - { + } misc; /* 1st word */ + uint32_t flash_density; /* 2nd word */ + struct { uint32_t dummy_clocks_1_4_4_read : 5; uint32_t mode_clocks_1_4_4_read : 3; uint32_t inst_1_4_4_read : 8; uint32_t dummy_clocks_1_1_4_read : 5; uint32_t mode_clocks_1_1_4_read : 3; uint32_t inst_1_1_4_read : 8; - } read_1_4_info; // 3rd word - struct - { + } read_1_4_info; /* 3rd word */ + struct { uint32_t dummy_clocks_1_2_2_read : 5; uint32_t mode_clocks_1_2_2_read : 3; uint32_t inst_1_2_2_read : 8; uint32_t dummy_clocks_1_1_2_read : 5; uint32_t mode_clocks_1_1_2_read : 3; uint32_t inst_1_1_2_read : 8; - } read_1_2_info; // 4th word + } read_1_2_info; /* 4th word */ - struct - { + struct { uint32_t support_2_2_2_fast_read : 1; uint32_t reserved0 : 3; uint32_t support_4_4_4_fast_read : 1; uint32_t reserved1 : 27; - } read_22_44_check; // 5th word + } read_22_44_check; /* 5th word */ - struct - { + struct { uint32_t reserved0 : 16; uint32_t dummy_clocks_2_2_2_read : 5; uint32_t mode_clocks_2_2_2_read : 3; uint32_t inst_2_2_2_read : 8; - } read_2_2_info; // 6th word - struct - { + } read_2_2_info; /* 6th word */ + struct { uint32_t reserved0 : 16; uint32_t dummy_clocks_4_4_4_read : 5; uint32_t mode_clocks_4_4_4_read : 3; uint32_t inst_4_4_4_read : 8; - } read_4_4_info; // 7th word + } read_4_4_info; /* 7th word */ - struct - { + struct { uint8_t size; uint8_t inst; - } erase_info[4]; // 8th,9th word + } erase_info[4]; /* 8th,9th word */ - uint32_t erase_timing; // 10th word - struct - { + uint32_t erase_timing; /* 10th word */ + struct { uint32_t reserved0 : 4; uint32_t page_size : 4; uint32_t reserved1 : 24; - } chip_erase_progrm_info; // 11th word + } chip_erase_progrm_info; /* 11th word */ - struct - { + struct { uint32_t suspend_resume_spec; uint32_t suspend_resume_inst; - } suspend_resume_info; // 12th, 13th word + } suspend_resume_info; /* 12th, 13th word */ - struct - { + struct { uint32_t reserved0 : 2; uint32_t busy_status_polling : 6; uint32_t reserved1 : 24; - } busy_status_info; // 14th word + } busy_status_info; /* 14th word */ - struct - { + struct { uint32_t mode_4_4_4_disable_seq : 4; uint32_t mode_4_4_4_enable_seq : 5; uint32_t support_mode_0_4_4 : 1; @@ -181,29 +164,26 @@ typedef union _jedec_flash_param_table uint32_t quad_enable_requirement : 3; uint32_t hold_reset_disable : 1; uint32_t reserved0 : 8; - } mode_4_4_info; // 15th word + } mode_4_4_info; /* 15th word */ - struct - { + struct { uint32_t status_reg_write_enable : 7; uint32_t reserved0 : 1; uint32_t soft_reset_rescue_support : 6; uint32_t exit_4_byte_addressing : 10; uint32_t enter_4_byte_addrssing : 8; - } mode_config_info; // 16th word + } mode_config_info; /* 16th word */ - struct - { + struct { uint32_t dummy_clocks_1_8_8_read : 5; uint32_t mode_clocks_1_8_8_read : 3; uint32_t inst_1_8_8_read : 8; uint32_t dummy_clocks_1_1_8_read : 5; uint32_t mode_clocks_1_1_8_read : 3; uint32_t inst_1_1_8_read : 8; - } read_1_8_info; // 17th word + } read_1_8_info; /* 17th word */ - struct - { + struct { uint32_t reserved : 18; uint32_t output_driver_strength : 5; uint32_t jedec_spi_protocol_reset : 1; @@ -213,10 +193,9 @@ typedef union _jedec_flash_param_table uint32_t dqs_support_in_opi_str : 1; uint32_t cmd_and_extension_in_opi_ddr : 2; uint32_t byte_order_in_opi_ddr : 1; - } xpi_misc_info; // 18th word + } xpi_misc_info; /* 18th word */ - struct - { + struct { uint32_t opi_sdr_disable_seq : 4; uint32_t opi_sdr_enable_seq : 5; uint32_t support_mode_0_8_8 : 1; @@ -224,10 +203,9 @@ typedef union _jedec_flash_param_table uint32_t mode_0_8_8_entry_method : 4; uint32_t octal_enable_requirement : 3; uint32_t reserved : 9; - } mode_octal_info; // 19th word + } mode_octal_info; /* 19th word */ - struct - { + struct { uint32_t qpi_sdr_no_dqs : 4; uint32_t qpi_sdr_with_dqs : 4; uint32_t qpi_ddr_no_dqs : 4; @@ -236,19 +214,16 @@ typedef union _jedec_flash_param_table uint32_t opi_sdr_with_dqs : 4; uint32_t opi_ddr_no_dqs : 4; uint32_t opi_ddr_with_dqs : 4; - } max_speed_info_xpi; // 20th word + } max_speed_info_xpi; /* 20th word */ }; } jedec_flash_param_table_t; -//!@brief 4Byte Addressing Instruction Table, see JESD216D doc for more details -typedef union _jedec_4byte_addressing_inst_table -{ +/* !@brief 4Byte Addressing Instruction Table, see JESD216D doc for more details */ +typedef union _jedec_4byte_addressing_inst_table { uint32_t words[2]; - struct - { - struct - { + struct { + struct { uint32_t support_1_1_1_read : 1; uint32_t support_1_1_1_fast_read : 1; uint32_t support_1_1_2_fast_read : 1; @@ -272,101 +247,86 @@ typedef union _jedec_4byte_addressing_inst_table uint32_t reserved : 12; } cmd_4byte_support_info; - struct - { + struct { uint8_t erase_inst[4]; } erase_inst_info; }; } jedec_4byte_addressing_inst_table_t; -typedef union _jedec_cmd_sequence_change_to_octal_mode -{ +typedef union _jedec_cmd_sequence_change_to_octal_mode { uint32_t words[8]; - struct - { - struct - { + struct { + struct { uint32_t byte3_of_1st_command_seq : 8; uint32_t byte2_of_1st_command_seq : 8; uint32_t byte1_of_1st_command_seq : 8; uint32_t length_of_1st_command_seq : 8; - } first_command_sequence_low; // 1st command sequence + } first_command_sequence_low; /* 1st command sequence */ - struct - { + struct { uint32_t byte7_of_first_command_seq : 8; uint32_t byte6_of_first_command_seq : 8; uint32_t byte5_of_first_command_seq : 8; uint32_t byte4_of_first_command_seq : 8; - } first_command_sequence_high; // 1st command sequence + } first_command_sequence_high; /* 1st command sequence */ - struct - { + struct { uint32_t byte3_of_2nd_command_seq : 8; uint32_t byte2_of_2nd_command_seq : 8; uint32_t byte1_of_2nd_command_seq : 8; uint32_t length_of_2nd_command_seq : 8; - } second_command_sequence_low; // 2nd command sequence + } second_command_sequence_low; /* 2nd command sequence */ - struct - { + struct { uint32_t byte7_of_2nd_command_seq : 8; uint32_t byte6_of_2nd_command_seq : 8; uint32_t byte5_of_2nd_command_seq : 8; uint32_t byte4_of_2md_command_seq : 8; - } second_command_sequence_high; // 2nd command sequence + } second_command_sequence_high; /* 2nd command sequence */ - struct - { + struct { uint32_t byte3_of_3rd_command_seq : 8; uint32_t byte2_of_3rd_command_seq : 8; uint32_t byte1_of_3rd_command_seq : 8; uint32_t length_of_3rd_command_seq : 8; - } third_command_sequence_low; // 3rd command sequence + } third_command_sequence_low; /* 3rd command sequence */ - struct - { + struct { uint32_t byte7_of_3rd_command_seq : 8; uint32_t byte6_of_3rd_command_seq : 8; uint32_t byte5_of_3rd_command_seq : 8; uint32_t byte4_of_3rd_command_seq : 8; - } third_command_sequence_high; // 3rd command sequence + } third_command_sequence_high; /* 3rd command sequence */ - struct - { + struct { uint32_t byte3_of_4th_command_seq : 8; uint32_t byte2_of_4th_command_seq : 8; uint32_t byte1_of_4th_command_seq : 8; uint32_t length_of_4th_command_seq : 8; - } fourth_command_sequence_low; // 4th command sequence + } fourth_command_sequence_low; /* 4th command sequence */ - struct - { + struct { uint32_t byte7_of_4th_command_seq : 8; uint32_t byte6_of_4th_command_seq : 8; uint32_t byte5_of_4th_command_seq : 8; uint32_t byte4_of_4th_command_seq : 8; - } fourth_command_sequence_high; // 4th command sequence + } fourth_command_sequence_high; /* 4th command sequence */ }; } jedec_cmd_sequence_change_to_octal_mode_t; -typedef union _jedec_x_spi_profile1_0_table_t -{ +typedef union _jedec_x_spi_profile1_0_table_t { uint32_t words[5]; - struct - { - struct - { + struct { + struct { uint32_t fast_read_wrapped_cmd : 8; uint32_t fast_read_cmd : 8; uint32_t reserved : 16; } table1; - struct - { + struct { uint32_t write_nv_register_cmd : 8; uint32_t write_v_register_cmd : 8; uint32_t reserved : 16; @@ -377,14 +337,11 @@ typedef union _jedec_x_spi_profile1_0_table_t } jedec_x_spi_profile1_0_table_t; -typedef union _jedec_status_control_configuration_reg_map -{ +typedef union _jedec_status_control_configuration_reg_map { uint32_t words[28]; - struct - { + struct { uint32_t unused_table[2]; - struct - { + struct { uint32_t dummy_cycles_1s_1s_1s : 4; uint32_t reserved0 : 2; uint32_t dummy_cycles_8d_8d_8d : 4; @@ -400,15 +357,14 @@ typedef union _jedec_status_control_configuration_reg_map }; } jedec_status_control_configuration_reg_map_t; -typedef struct _jdec_query_table -{ - uint32_t standard_version; // JESD216 version +typedef struct _jdec_query_table { + uint32_t standard_version; /* JESD216 version */ uint32_t flash_param_tbl_size; jedec_flash_param_table_t flash_param_tbl; bool has_4b_addressing_inst_table; jedec_4byte_addressing_inst_table_t flash_4b_inst_tbl; bool has_otcal_ddr_mode_enable_sequence_table; - jedec_cmd_sequence_change_to_octal_mode_t otcal_ddr_mode_enable_sequence; // JESD216C/D + jedec_cmd_sequence_change_to_octal_mode_t otcal_ddr_mode_enable_sequence; /* JESD216C/D */ jedec_x_spi_profile1_0_table_t profile1_0_table; bool has_spi_profile1_0_table; jedec_status_control_configuration_reg_map_t sccr_map; @@ -416,7 +372,7 @@ typedef struct _jdec_query_table } jedec_info_table_t; -//!@brief Typical Serial NOR commands supported by most Serial NOR devices +/* !@brief Typical Serial NOR commands supported by most Serial NOR devices */ #define kSerialNorCmd_BasicRead_3B (0x03U) #define kSerialNorCmd_BasicRead_4B (0x13U) #define kSerialNorCmd_PageProgram_1_1_1_3B (0x02U) diff --git a/common/libraries/hpm_sdk/components/spi/hpm_spi.c b/common/libraries/hpm_sdk/components/spi/hpm_spi.c index 3b56f9c9..11699399 100644 --- a/common/libraries/hpm_sdk/components/spi/hpm_spi.c +++ b/common/libraries/hpm_sdk/components/spi/hpm_spi.c @@ -65,7 +65,9 @@ void hpm_spi_prepare_dma_tx_descriptors(spi_context_t *context, spi_control_conf | SPI_TRANSCTRL_RDTRANCNT_SET(temp32 - 1); if (i == 0) { - temp32 = temp32 + 1; /* DMA transmits one byte more than SPI at the first transmission */ + /* Set the count of data transferred by dma to be one more than that of spi */ + /* when dma transfer finished, there are data in SPI fifo, dma should not execute the dma descriptor which changes SPI CTRL register */ + temp32 = temp32 + 1; } if (i == trans_count - 1) { temp32 = temp32 - 1; @@ -212,6 +214,15 @@ static uint32_t hpm_spi_get_trans_count(spi_context_t *context, spi_control_conf return trans_count; } +/** + * spi with dma chain workflow + * + * 1. call spi_setup_dma_transfer to config SPI for first transmission + * 2. execute data transmission phase in dma chain descriptor + * 3. execute setting SPI CTRL register phase in dma chain descriptor + * 4. execute writing SPI CMD register phase in dma chain descriptor + * 5. Repeat steps 2-4 until finish the transmission + */ static hpm_stat_t spi_setup_trans_with_dma_chain(spi_context_t *context, spi_control_config_t *config) { hpm_stat_t stat = status_success; @@ -229,6 +240,7 @@ static hpm_stat_t spi_setup_trans_with_dma_chain(spi_context_t *context, spi_con /* active spi cs pin */ context->write_cs(context->cs_pin, SPI_CS_ACTIVE); + /* config SPI for first dma transmission */ stat = spi_setup_dma_transfer(spi_ptr, config, &context->cmd, @@ -275,6 +287,7 @@ static hpm_stat_t spi_setup_trans_with_dma_chain(spi_context_t *context, spi_con dma_ch_config.src_width = DMA_TRANSFER_WIDTH_WORD; dma_ch_config.dst_width = DMA_TRANSFER_WIDTH_WORD; dma_ch_config.size_in_byte = 4; + /* start data transmission phase in dma chain */ dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(dma_linked_descriptor + SPI_DMA_DESC_COUNT_PER_TRANS - 1)); stat = dma_setup_channel(dma_ptr, dma_channel, &dma_ch_config, true); diff --git a/common/libraries/hpm_sdk/components/spi/hpm_spi.h b/common/libraries/hpm_sdk/components/spi/hpm_spi.h index 6dccb7f1..d4cd78f0 100644 --- a/common/libraries/hpm_sdk/components/spi/hpm_spi.h +++ b/common/libraries/hpm_sdk/components/spi/hpm_spi.h @@ -61,6 +61,9 @@ extern "C" { /** * @brief hpm_spi setup dma transfer * + * @note if the transferred data count more than SPI_SOC_TRANSFER_COUNT_MAX, this API will using + * DMA chain descriptors to link SPI transmission. + * * @param[in] spi_context A pointer to the struct of "spi_context_t" * @param[in] spi_config A pointer to the struct of "spi_control_config_t" * @retval status_success if SPI transfers data successfully. diff --git a/common/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c b/common/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c index 26fdabfc..cf6e251c 100644 --- a/common/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c +++ b/common/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c @@ -10,10 +10,15 @@ static uint8_t g_i2c_addr; hpm_stat_t gt911_read_data(gt911_context_t *context, uint16_t addr, uint8_t *buf, uint32_t size) { + hpm_stat_t stat; uint8_t r[2]; r[0] = addr >> 8; r[1] = addr & 0xFF; - return i2c_master_address_read(context->ptr, g_i2c_addr, r, sizeof(r), buf, size); + stat = i2c_master_write(context->ptr, g_i2c_addr, r, sizeof(r)); + if (stat != status_success) { + return stat; + } + return i2c_master_read(context->ptr, g_i2c_addr, buf, size); } hpm_stat_t gt911_write_data(gt911_context_t *context, uint16_t addr, uint8_t *buf, uint32_t size) diff --git a/common/libraries/hpm_sdk/drivers/CMakeLists.txt b/common/libraries/hpm_sdk/drivers/CMakeLists.txt index 7041e36f..e85091e0 100644 --- a/common/libraries/hpm_sdk/drivers/CMakeLists.txt +++ b/common/libraries/hpm_sdk/drivers/CMakeLists.txt @@ -39,3 +39,8 @@ sdk_src_ifdef(CONFIG_HAS_HPMSDK_MCHTMR src/hpm_mchtmr_drv.c) sdk_src_ifdef(CONFIG_HAS_HPMSDK_FFA src/hpm_ffa_drv.c) sdk_src_ifdef(CONFIG_HAS_HPMSDK_TSNS src/hpm_tsns_drv.c) sdk_src_ifdef(CONFIG_HAS_HPMSDK_DAC src/hpm_dac_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_CRC src/hpm_crc_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_PLA src/hpm_pla_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_SDM src/hpm_sdm_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_LIN src/hpm_lin_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_MCAN src/hpm_mcan_drv.c) diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h index 61f5d394..f5e2a6e0 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h @@ -23,7 +23,7 @@ #define ADC12_IS_SIGNAL_TYPE_INVALID(TYPE) (TYPE > (uint32_t)adc12_sample_signal_count) /** @brief Define ADC12 validity check for the channel number */ -#define ADC12_IS_CHANNEL_INVALID(PTR, CH) (CH > ADC12_SOC_MAX_CH_NUM) +#define ADC12_IS_CHANNEL_INVALID(CH) (CH > ADC12_SOC_MAX_CH_NUM) /** @brief Define ADC12 validity check for the trigger number */ #define ADC12_IS_TRIG_CH_INVLAID(CH) (CH > ADC12_SOC_MAX_TRIG_CH_NUM) @@ -316,16 +316,25 @@ static inline uint32_t adc12_get_status_flags(ADC12_Type *ptr) } /** - * @brief Get the setting value of the WAIT_DIS bit. + * @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus + * until the ADC has completed its conversion. * * @param[in] ptr An ADC12 peripheral base address. - * @return Status that indicats whether the current setting of the WAIT_DIS bit in the BUF_RESULT register is disabled. - * @retval true It means that the WAIT_DIS bit is 1. - * @retval false It means that the WAIT_DIS bit is 0. */ -static inline bool adc12_get_wait_dis_status(ADC12_Type *ptr) +static inline void adc12_disable_busywait(ADC12_Type *ptr) { - return ADC12_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0); + ptr->BUF_CFG0 |= ADC12_BUF_CFG0_WAIT_DIS_SET(1); +} + +/** + * @brief Set value of the WAIT_DIS bit. ADC blocks access to the associated peripheral bus + * until the ADC completes the conversion. + * + * @param[in] ptr An ADC12 peripheral base address. + */ +static inline void adc12_enable_busywait(ADC12_Type *ptr) +{ + ptr->BUF_CFG0 &= ~ADC12_BUF_CFG0_WAIT_DIS_MASK; } /** diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h index 58e3ab1d..19e9eed3 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h @@ -20,7 +20,11 @@ */ /** @brief Define ADC16 validity check for the channel number */ +#if ADC16_SOC_TEMP_CH_EN #define ADC16_IS_CHANNEL_INVALID(CH) (CH > ADC16_SOC_MAX_CH_NUM && CH != ADC16_SOC_TEMP_CH_NUM) +#else +#define ADC16_IS_CHANNEL_INVALID(CH) (CH > ADC16_SOC_MAX_CH_NUM) +#endif /** @brief Define ADC16 validity check for the trigger number */ #define ADC16_IS_TRIG_CH_INVLAID(CH) (CH > ADC16_SOC_MAX_TRIG_CH_NUM) @@ -37,6 +41,14 @@ /** @brief Define ADC16 validity check for the DMA buffer length in the preemption mode */ #define ADC16_IS_PMT_DMA_BUFF_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES)) +/** @brief Define ADC16 resolutions. */ +typedef enum { + adc16_res_8_bits = 9, + adc16_res_10_bits = 11, + adc16_res_12_bits = 14, + adc16_res_16_bits = 21 +} adc16_resolution_t; + /** @brief Define ADC16 conversion modes. */ typedef enum { adc16_conv_mode_oneshot = 0, @@ -80,6 +92,7 @@ typedef enum { /** @brief ADC16 common configuration struct. */ typedef struct { + uint8_t res; uint8_t conv_mode; uint8_t wait_dis; uint32_t adc_clk_div; @@ -308,16 +321,25 @@ static inline uint32_t adc16_get_status_flags(ADC16_Type *ptr) } /** - * @brief Get the setting value of the WAIT_DIS bit. + * @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus + * until the ADC has completed its conversion. + * + * @param[in] ptr An ADC16 peripheral base address. + */ +static inline void adc16_disable_busywait(ADC16_Type *ptr) +{ + ptr->BUF_CFG0 |= ADC16_BUF_CFG0_WAIT_DIS_SET(1); +} + +/** + * @brief Set value of the WAIT_DIS bit. ADC blocks access to the associated peripheral bus + * until the ADC completes the conversion. * * @param[in] ptr An ADC16 peripheral base address. - * @return Status that indicats whether the current setting of the WAIT_DIS bit in the BUF_RESULT register is disabled. - * @retval true It means that the WAIT_DIS bit is 1. - * @retval false It means that the WAIT_DIS bit is 0. */ -static inline bool adc16_get_wait_dis_status(ADC16_Type *ptr) +static inline void adc16_enable_busywait(ADC16_Type *ptr) { - return ADC16_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0); + ptr->BUF_CFG0 &= ~ADC16_BUF_CFG0_WAIT_DIS_MASK; } /** diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h index 0dcb2ccd..7bb3ab35 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h @@ -65,6 +65,8 @@ #define CAM_COLOR_FORMAT_RGB555 (CAM_CR1_COLOR_FORMATS_SET(6)) #define CAM_COLOR_FORMAT_YCBCR422 (CAM_CR1_COLOR_FORMATS_SET(7)) #define CAM_COLOR_FORMAT_YUV444 (CAM_CR1_COLOR_FORMATS_SET(8)) +#define CAM_COLOR_FORMAT_RAW8 (CAM_CR1_COLOR_FORMATS_SET(0xf)) +#define CAM_COLOR_FORMAT_UNSUPPORTED (1) /** * @brief CAM config @@ -114,6 +116,26 @@ typedef enum { extern "C" { #endif +/** + * @brief cam get pixel format value + * + * @param format display_pixel_format_t + * @return uint32_t cam color format, like CAM_COLOR_FORMAT_RGB565 + */ +static inline uint32_t cam_get_pixel_format(display_pixel_format_t format) +{ + switch (format) { + case display_pixel_format_rgb565: + return CAM_COLOR_FORMAT_RGB565; + case display_pixel_format_ycbcr422: + return CAM_COLOR_FORMAT_YCBCR422; + case display_pixel_format_raw8: + return CAM_COLOR_FORMAT_RAW8; + default: + return CAM_COLOR_FORMAT_UNSUPPORTED; + } +} + /** * @brief CAM set high and low limits of color key * diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h index d76166a7..4c9c505e 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,7 +10,7 @@ #include "hpm_common.h" #include "hpm_can_regs.h" - +#include "hpm_soc_feature.h" /** * @brief CAN driver APIs @@ -257,7 +257,7 @@ typedef struct { } can_config_t; -#ifdef __cpluspuls +#ifdef __cplusplus extern "C" { #endif @@ -678,7 +678,11 @@ static inline uint8_t can_get_last_arbitration_lost_position(CAN_Type *base) */ static inline void can_set_transmitter_delay_compensation(CAN_Type *base, uint8_t sample_point, bool enable) { +#if defined(CAN_SOC_CANFD_TDC_REQUIRE_STUFF_EXCEPTION_WORKAROUND) && (CAN_SOC_CANFD_TDC_REQUIRE_STUFF_EXCEPTION_WORKAROUND == 1) + base->TDC = CAN_TDC_TDCEN_SET((uint8_t) enable); +#else base->TDC = CAN_TDC_SSPOFF_SET(sample_point) | CAN_TDC_TDCEN_SET((uint8_t) enable); +#endif } /** @@ -874,7 +878,7 @@ hpm_stat_t can_read_received_message(CAN_Type *base, can_receive_buf_t *message) */ -#ifdef __cpluspuls +#ifdef __cplusplus } #endif diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_common.h b/common/libraries/hpm_sdk/drivers/inc/hpm_common.h index 33d83346..78eb6615 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_common.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_common.h @@ -13,7 +13,6 @@ #include #include #include -#include "hpm_sdk_version.h" /** * @@ -108,6 +107,7 @@ enum { status_group_pllctl, status_group_pllctlv2, status_group_ffa, + status_group_mcan, status_group_middleware_start = 500, status_group_sdmmc = status_group_middleware_start, diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h new file mode 100644 index 00000000..100eeda4 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_CRC_DRV_H +#define HPM_CRC_DRV_H + +/** + * @brief CRC APIs + * @defgroup crc_interface CRC driver APIs + * @ingroup crc_interfaces + * @{ + */ + + +#include "hpm_common.h" +#include "hpm_crc_regs.h" + +/** + * @brief CRC preset definitions + */ +typedef enum crc_preset_enum { + crc_preset_none = 0, + crc_preset_crc32, /*!< Poly: 0x04C11DB7, Init: 0xFFFFFFFF, Refin: True, Refout: True, Xorout: 0xFFFFFFFF */ + crc_preset_crc32_autosar, /*!< Poly: 0xF4ACFB13, Init: 0xFFFFFFFF, Refin: True, Refout: True, Xorout: 0xFFFFFFFF */ + crc_preset_crc16_ccitt, /*!< Poly: 0x1021, Init: 0x0000, Refin: True, Refout: True, Xorout: 0x0000 */ + crc_preset_crc16_xmodem, /*!< Poly: 0x1021, Init: 0x0000, Refin: False, Refout: False, Xorout: 0x0000 */ + crc_preset_crc16_modbus, /*!< Poly: 0x8005, Init: 0xFFFF, Refin: True, Refout: True, Xorout: 0x0000 */ + crc_preset_crc16_dnp, /*!< Poly: 0x3D65, Init: 0x0000, Refin: True, Refout: True, Xorout: 0xFFFF */ + crc_preset_crc16_x25, /*!< Poly: 0x1021, Init: 0xFFFF, Refin: True, Refout: True, Xorout: 0xFFFF */ + crc_preset_crc16_usb, /*!< Poly: 0x8005, Init: 0xFFFF, Refin: True, Refout: True, Xorout: 0xFFFF */ + crc_preset_crc16_maxim, /*!< Poly: 0x8005, Init: 0x0000, Refin: True, Refout: True, Xorout: 0xFFFF */ + crc_preset_crc16_ibm, /*!< Poly: 0x8005, Init: 0x0000, Refin: True, Refout: True, Xorout: 0x0000 */ + crc_preset_crc8_maxim, /*!< Poly: 0x31, Init: 0x00, Refin: True, Refout: True, Xorout: 0x00 */ + crc_preset_crc8_rohc, /*!< Poly: 0x07, Init: 0xFF, Refin: True, Refout: True, Xorout: 0x00 */ + crc_preset_crc8_itu, /*!< Poly: 0x07, Init: 0x00, Refin: False, Refout: False, Xorout: 0x55 */ + crc_preset_crc8, /*!< Poly: 0x07, Init: 0x00, Refin: False, Refout: False, Xorout: 0x00 */ + crc_preset_crc5_usb, /*!< Poly: 0x05, Init: 0x1F, Refin: True, Refout: True, Xorout: 0x1F */ +} crc_preset_t; + +/** + * @brief CRC Refin definitions. + */ +typedef enum crc_refin_enum { + crc_refin_false = 0, /*!< Do not manipulate input data stream. */ + crc_refin_true = 1, /*!< Reflect each byte in the input stream bitwise. */ +} crc_refin_t; + +/** + * @brief CRC Refout definitions. + */ +typedef enum crc_refout_enum { + crc_refout_false = 0, /*!< Do not manipulate output data stream. */ + crc_refout_true = 1, /*!< Reflect each byte in the output stream bitwise. */ +} crc_refout_t; + +/** + * @brief crc input data stream byte order definitions. + */ +typedef enum crc_in_byte_order_enum { + crc_in_byte_order_lsb = 0, /*!< Byte order of the CRC DATA LS Byte first. */ + crc_in_byte_order_msb = 1, /*!< Byte order of the CRC DATA MS Byte first. */ +} crc_in_byte_order_t; + +#define CRC_POLY_WIDTH_4 (4U) +#define CRC_POLY_WIDTH_5 (5U) +#define CRC_POLY_WIDTH_6 (6U) +#define CRC_POLY_WIDTH_7 (7U) +#define CRC_POLY_WIDTH_8 (8U) +#define CRC_POLY_WIDTH_16 (16U) +#define CRC_POLY_WIDTH_24 (24U) +#define CRC_POLY_WIDTH_32 (32U) + +/** + * @brief Channel config + */ +typedef struct crc_channel_config { + crc_preset_t preset; /*!< Preset CRC. See "crc_preset_t". */ + uint32_t init; /*!< Initial value for CRC. */ + uint32_t poly; /*!< Poly for CRC. */ + uint32_t poly_width; /*!< CRC poly width. See "CRC_POLY_WIDTH_x". */ + crc_in_byte_order_t in_byte_order; /*!< CRC intput byte order. See "crc_in_byte_order_t". */ + crc_refout_t refout; /*!< CRC reflect output. See "crc_refout_t". */ + crc_refin_t refin; /*!< CRC reflect iutput. See "crc_refin_t". */ + uint32_t xorout; /*!< XOR mask for CRC result (for no mask, should be 0). */ +} crc_channel_config_t; + +#define CRC_REG_WRITE8(addr, data)\ +{\ + uint32_t addr32 = (uint32_t)(addr);\ + (*(volatile uint8_t *)(addr32) = (data));\ +} + +#define CRC_REG_WRITE16(addr, data)\ +{\ + uint32_t addr32 = (uint32_t)(addr);\ + (*(volatile uint16_t *)(addr32) = (data));\ +} + +#define CRC_REG_WRITE32(addr, data)\ +{\ + uint32_t addr32 = (uint32_t)(addr);\ + (*(volatile uint32_t *)(addr32) = (data));\ +} + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Reset CRC channel + * + * @param[in] ptr CRC base address + * @param[in] ch_index Index of the channel to be reset + * + */ +static inline void crc_reset(CRC_Type *ptr, uint32_t ch_index) +{ + ptr->CHN[ch_index].CLR |= CRC_CHN_CLR_CLR_MASK; +} + +/** + * @brief Get default channel config + * + * @param[in] ptr CRC base address + * @param[in] cfg Channel config + */ +void crc_get_default_channel_config(crc_channel_config_t *cfg); + +/** + * @brief Setup CRC channel + * + * @param[in] ptr CRC base address + * @param[in] ch_index Target channel index to be configured + * @param[in] cfg Channel config + * + * @return status_success if everything is okay + */ +hpm_stat_t crc_setup_channel_config(CRC_Type *ptr, uint32_t ch_index, + crc_channel_config_t *cfg); + +/** + * @brief Calculate one byte data crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] data Data that to be calculate + */ +static inline void crc_calc_byte(CRC_Type *ptr, uint32_t ch_index, uint8_t data) +{ + CRC_REG_WRITE8(&ptr->CHN[ch_index].DATA, data); +} + +/** + * @brief Calculate length bytes data block crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] pbuffer Data to be calculate buffer + * @param[in] length Number of pbuffer, unit is byte + */ +void crc_calc_block_bytes(CRC_Type *ptr, uint32_t ch_index, uint8_t *pbuffer, uint32_t length); + +/** + * @brief Calculate half-word data crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] data Data that to be calculate + */ +static inline void crc_calc_half_word(CRC_Type *ptr, uint32_t ch_index, uint16_t data) +{ + CRC_REG_WRITE16(&ptr->CHN[ch_index].DATA, data); +} + +/** + * @brief Calculate length half-words data block crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] pbuffer Data to be calculate buffer + * @param[in] length Number of pbuffer, unit is half word(2 bytes) + */ +void crc_calc_block_half_words(CRC_Type *ptr, uint32_t ch_index, uint16_t *pbuffer, uint32_t length); + +/** + * @brief Calculate word data crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] data Data that to be calculate + */ +static inline void crc_calc_word(CRC_Type *ptr, uint32_t ch_index, uint32_t data) +{ + CRC_REG_WRITE32(&ptr->CHN[ch_index].DATA, data); +} + +/** + * @brief Calculate length words data block crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] pbuffer Data to be calculate buffer + * @param[in] length Number of pbuffer, unit is word(4 bytes) + */ +void crc_calc_block_words(CRC_Type *ptr, uint32_t ch_index, uint32_t *pbuffer, uint32_t length); + +/** + * @brief Fast calculate length bytes large data block crc + * + * @param[in] ptr CRC base address + * @param[in] ch_index CRC channel index + * @param[in] pbuffer Data to be calculate buffer + * @param[in] length Number of pbuffer, unit is byte + */ +void crc_calc_large_block_fast(CRC_Type *ptr, uint32_t ch_index, uint8_t *pbuffer, uint32_t length); + +/** + * @brief Get CRC result + * + * @param[in] ptr CRC base address + * @param[in] ch_index Index of the channel to be get + * @return CRC result + */ +static inline uint32_t crc_get_result(CRC_Type *ptr, uint32_t ch_index) +{ + return ptr->CHN[ch_index].RESULT; +} +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* HPM_CRC_DRV_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_csr_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_csr_drv.h new file mode 100644 index 00000000..acec7c6d --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_csr_drv.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_CSR_DRV_H +#define HPM_CSR_DRV_H + +#include "hpm_csr_regs.h" +#include "riscv/riscv_core.h" + + +/** + * @brief CSR driver APIs + * @defgroup csr_interface CSR driver APIs + * @ingroup csr_interfaces + * @{ + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Enable access to CSR_CYCLE and CSR_MCYCLEH + * @note This Function can be called in Machine mode only + * + */ +static inline void hpm_csr_enable_access_to_csr_cycle(void) +{ + uint32_t mcounter_en = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounter_en | CSR_MCOUNTEREN_CY_MASK); +} + +/** + * @brief Disable access to CSR_CYCLE and CSR_MCYCLEH + * @note This Function can be called in Machine mode only + * + */ +static inline void hpm_csr_disable_access_to_csr_cycle(void) +{ + uint32_t mcounter_en = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounter_en & ~CSR_MCOUNTEREN_CY_MASK); +} + +/** + * @brief Get the core cycle value + * @note The CY bit in MCOUNTEREN must be enabled before using this API whendevice is : + * - in supervisor mode if the device supports M/S/U mode, or + * - in user mode if the device supports M/U mode + * + * @return CSR cycle value in 64-bit + */ +static inline uint64_t hpm_csr_get_core_cycle(void) +{ + uint64_t result; + uint32_t resultl_first = read_csr(CSR_CYCLE); + uint32_t resulth = read_csr(CSR_CYCLEH); + uint32_t resultl_second = read_csr(CSR_CYCLE); + if (resultl_first < resultl_second) { + result = ((uint64_t)resulth << 32) | resultl_first; /* if CYCLE didn't roll over, return the value directly */ + } else { + resulth = read_csr(CSR_CYCLEH); + result = ((uint64_t)resulth << 32) | resultl_second; /* if CYCLE rolled over, need to get the CYCLEH again */ + } + return result; + } + +/** + * @brief Get the core mcycle value + * @note This function can be called in machine mode only + * + * @return CSR mcycle value in 64-bit + */ +static inline uint64_t hpm_csr_get_core_mcycle(void) +{ + uint64_t result; + uint32_t resultl_first = read_csr(CSR_MCYCLE); + uint32_t resulth = read_csr(CSR_MCYCLEH); + uint32_t resultl_second = read_csr(CSR_MCYCLE); + if (resultl_first < resultl_second) { + result = ((uint64_t)resulth << 32) | resultl_first; /* if MCYCLE didn't roll over, return the value directly */ + } else { + resulth = read_csr(CSR_MCYCLEH); + result = ((uint64_t)resulth << 32) | resultl_second; /* if MCYCLE rolled over, need to get the MCYCLEH again */ + } + return result; + } + + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + + +#endif /* HPM_CSR_DRV_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_display_common.h b/common/libraries/hpm_sdk/drivers/inc/hpm_display_common.h index 44cb71e2..30317466 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_display_common.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_display_common.h @@ -51,6 +51,7 @@ typedef enum display_pixel_format { display_pixel_format_yuv422, display_pixel_format_ycbcr422, display_pixel_format_y8, + display_pixel_format_raw8, } display_pixel_format_t; /** @@ -172,6 +173,8 @@ static inline return 16; case display_pixel_format_y8: return 8; + case display_pixel_format_raw8: + return 8; default: return 0; } diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h index d4915eeb..49c89079 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h @@ -184,15 +184,15 @@ static inline void dma_disable_channel(DMA_Type *ptr, uint32_t ch_index) } /** - * @brief Check whether DMA channel is transferring + * @brief Check whether DMA channel is enable * * @param[in] ptr DMA base address * @param[in] ch_index Index of the channel * - * @return true if DMA channel is transferring + * @return true if DMA channel is enable * */ -static inline bool dma_channel_is_transferring(DMA_Type *ptr, uint32_t ch_index) +static inline bool dma_channel_is_enable(DMA_Type *ptr, uint32_t ch_index) { return (ptr->CHCTRL[ch_index].CTRL & DMA_CHCTRL_CTRL_ENABLE_MASK) ? true : false; } @@ -445,6 +445,21 @@ hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_index, */ hpm_stat_t dma_setup_handshake(DMA_Type *ptr, dma_handshake_config_t *pconfig, bool start_transfer); + +#if defined(DMA_SOC_HAS_IDLE_FLAG) && (DMA_SOC_HAS_IDLE_FLAG == 1) +/** + * @brief Check whether DMA is idle + * @param [in] ptr DMA base address + * @return true DMA is idle + * @return false DMA is busy + */ +static inline bool dma_is_idle(DMA_Type *ptr) +{ + return ((ptr->IDMISC & DMA_IDMISC_IDLE_FLAG_MASK) != 0U); +} +#endif + + #ifdef __cplusplus } #endif diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h index bfdb8fc7..3b3ed88b 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -8,9 +8,10 @@ #ifndef HPM_ENET_DRV_H #define HPM_ENET_DRV_H -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_common.h" #include "hpm_enet_regs.h" #include "hpm_soc_feature.h" @@ -23,9 +24,10 @@ * @{ */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Macro Constant Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #define ENET_HEADER (14U) /**< 6-byte Dest addr, 6-byte Src addr, 2-byte type */ #define ENET_EXTRA (2U) /**< Extra bytes in some cases */ #define ENET_VLAN_TAG (4U) /**< optional 802.1q VLAN Tag */ @@ -40,9 +42,14 @@ #define ENET_ADJ_FREQ_BASE_ADDEND (0x7fffffffUL) /**< PTP base adjustment addend */ #define ENET_ONE_SEC_IN_NANOSEC (1000000000UL) /**< one second in nanoseconds */ -/*---------------------------------------------------------------------* + +#define ENET_PPS_CMD_MASK (0x07UL) /**< Enet PPS CMD Mask */ +#define ENET_PPS_CMD_OFS_FAC (3U) /**< Enet PPS CMD OFS Factor */ +/*--------------------------------------------------------------------- * Typedef Enum Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ + /** @brief Programmable burst length selections */ typedef enum { enet_normal_int_sum_en = ENET_DMA_INTR_EN_NIE_MASK, @@ -68,13 +75,39 @@ typedef enum { /** @brief Checksum insertion control selections */ typedef enum { - enet_cic_bypass = 0, - enet_cic_insert_ipv4_header, - enet_cic_insert_tcp_udp_icmp, - enet_cic_insert_tcp_upd_icmp, -} enet_insert_t; + enet_cic_disable = 0, + enet_cic_ip = 1, + enet_cic_ip_no_pseudoheader = 2, + enet_cic_ip_pseudoheader = 3 +} enet_cic_insertion_control_t; -/** @brief PHY opeartion selections */ +/** @brief VLAN insertion control selections */ +typedef enum { + enet_vlic_disable = 0, + enet_vlic_remove_vlan_tag = 1, + enet_vlic_insert_vlan_tag = 2, + enet_vlic_replace_vlan_tag = 3 +} enet_vlan_insertion_control_t; + +/** @brief SA insertion or replacement control selections for any selective frames */ +typedef enum { + enet_saic_disable = 0, + enet_saic_insert_mac0 = 1, + enet_saic_replace_mac0 = 2, + enet_saic_insert_mac1 = 5, + enet_saic_replace_mac1 = 6 +} enet_saic_insertion_replacement_control_t; + +/** @brief SA insertion or replacement control selections for all transmit frames */ +typedef enum { + enet_sarc_disable = 0, + enet_sarc_insert_mac0 = 2, + enet_sarc_replace_mac0 = 3, + enet_sarc_insert_mac1 = 6, + enet_sarc_replace_mac1 = 7 +} enet_sarc_insertion_replacement_control_t; + +/** @brief PHY operation selections */ typedef enum { enet_phy_op_read = 0, enet_phy_op_write @@ -162,11 +195,20 @@ typedef enum { enet_ts_ss_ptp_msg_7 = 12 /* Pdelay_Req, Pdelay_Resp */ } enet_ts_ss_ptp_msg_t; +/** @brief PTP timer rollover modes */ typedef enum { enet_ts_bin_rollover_control = 0, /* timestamp rolls over after 0x7fffffff */ enet_ts_dig_rollover_control /* timestamp rolls over after 0x3b9ac9ff */ } enet_ts_rollover_control_t; +/** @brief PPS indexes */ +typedef enum { + enet_pps_0 = -1, + enet_pps_1 = 0, + enet_pps_2 = 1, + enet_pps_3 = 2 +} enet_pps_idx_t; + /** @brief PPS0 control for output frequency selections */ typedef enum { enet_pps_ctrl_pps = 0, @@ -197,9 +239,11 @@ typedef enum { enet_pps_cmd_stop_pulse_train_immediately, enet_pps_cmd_cancel_stop_pulse_train } enet_pps_cmd_t; -/*---------------------------------------------------------------------* + +/*--------------------------------------------------------------------- * Typedef Struct Declarations - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ /** @brief enet buffer config struct */ typedef struct { uint32_t buffer; @@ -207,13 +251,13 @@ typedef struct { uint16_t size; } enet_buff_config_t; - /** @brief enet mac config struct */ typedef struct { uint32_t mac_addr_high[ENET_SOC_ADDR_MAX_COUNT]; uint32_t mac_addr_low[ENET_SOC_ADDR_MAX_COUNT]; uint8_t valid_max_count; uint8_t dma_pbl; + uint8_t sarc; } enet_mac_config_t; /** @brief transmission descriptor struct */ @@ -257,7 +301,7 @@ typedef struct { uint32_t tbs1 : 13; /**< Transmit Buffer 1 Size */ uint32_t reserved: 3; /**< Reserved */ uint32_t tbs2 : 13; /**< Transmit Buffer 2 Size */ - uint32_t saic : 3; /**< SA Inertion Control */ + uint32_t saic : 3; /**< SA Insertion Control */ } tdes1_bm; }; @@ -339,7 +383,7 @@ typedef struct { union { uint32_t rdes2; struct { - uint32_t buffer1; /**< Buffer 1 Address */ + uint32_t buffer1; /**< Buffer 1 Address */ } rdes2_bm; }; @@ -355,26 +399,26 @@ typedef struct { union { uint32_t rdes4; struct { - uint32_t ip_payload_type : 3; /**< IP Payload Type */ - uint32_t ip_header_err : 1; /**< IP Header Error */ - uint32_t ip_payload_err : 1; /**< IP Payload Error */ - uint32_t ip_chksum_bypassed : 1; /**< IP Checksum Bypassed */ - uint32_t ipv4_pkt_received : 1; /**< IPv4 Packet Received */ - uint32_t ipv6_pkt_received : 1; /**< IPv6 Packet Received */ - uint32_t msg_type : 4; /**< Message Type */ - uint32_t ptp_frame_type : 1; /**< PTP Frame Type */ - uint32_t ptp_version : 1; /**< PTP Version */ - uint32_t ts_dp : 1; /**< Timestamp Dropped */ - uint32_t reserved0 : 1; /**< Reserved */ - uint32_t av_pkt_recv : 1; /**< AV Packet Received */ - uint32_t av_tagged_pkt_recv : 1; /**< AV Tagged Packet Received */ - uint32_t vlan_tag_pri_value : 3; /**< VLAN Tag Priority Value */ - uint32_t reserved1 : 3; /**< Reserved */ - uint32_t l3_fm : 1; /**< Layer 3 Filter Matched */ - uint32_t l4_fm : 1; /**< Layer 4 Filter Matched */ - uint32_t l3_l4_fnl : 2; /**< Layer 3 and Layer 4 Filter Number Matched */ - uint32_t reserved2 : 4; /**< Reserved */ - } rdes4_bm; + uint32_t ip_payload_type : 3; /**< IP Payload Type */ + uint32_t ip_header_err : 1; /**< IP Header Error */ + uint32_t ip_payload_err : 1; /**< IP Payload Error */ + uint32_t ip_chksum_bypassed : 1; /**< IP Checksum Bypassed */ + uint32_t ipv4_pkt_received : 1; /**< IPv4 Packet Received */ + uint32_t ipv6_pkt_received : 1; /**< IPv6 Packet Received */ + uint32_t msg_type : 4; /**< Message Type */ + uint32_t ptp_frame_type : 1; /**< PTP Frame Type */ + uint32_t ptp_version : 1; /**< PTP Version */ + uint32_t ts_dp : 1; /**< Timestamp Dropped */ + uint32_t reserved0 : 1; /**< Reserved */ + uint32_t av_pkt_recv : 1; /**< AV Packet Received */ + uint32_t av_tagged_pkt_recv : 1; /**< AV Tagged Packet Received */ + uint32_t vlan_tag_pri_value : 3; /**< VLAN Tag Priority Value */ + uint32_t reserved1 : 3; /**< Reserved */ + uint32_t l3_fm : 1; /**< Layer 3 Filter Matched */ + uint32_t l4_fm : 1; /**< Layer 4 Filter Matched */ + uint32_t l3_l4_fnl : 2; /**< Layer 3 and Layer 4 Filter Number Matched */ + uint32_t reserved2 : 4; /**< Reserved */ + } rdes4_bm; }; struct { @@ -405,6 +449,18 @@ typedef struct { uint32_t seg_count; } enet_rx_frame_info_t; +/** @brief enet control config struct for transmission */ +typedef struct { + bool enable_ioc; /* interrupt on completion */ + bool disable_crc; /* disable CRC */ + bool disable_pad; /* disable Pad */ + bool enable_tts; /* enable transmit timestamp */ + bool enable_crcr; /* CRC replacement control */ + uint8_t cic; /* checksum insertion control */ + uint8_t vlic; /* VLAN insertion control */ + uint8_t saic; /* SA insertion control */ +} enet_tx_control_config_t; + /** @brief enet description struct */ typedef struct { enet_tx_desc_t *tx_desc_list_head; @@ -414,6 +470,7 @@ typedef struct { enet_buff_config_t tx_buff_cfg; enet_buff_config_t rx_buff_cfg; enet_rx_frame_info_t rx_frame_info; + enet_tx_control_config_t tx_control_config; } enet_desc_t; /** @brief PTP system timestamp struct */ @@ -466,9 +523,18 @@ typedef struct { #if defined __cplusplus extern "C" { #endif /* __cplusplus */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Exported Functions - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ +/** + * @brief Get a default control config for tranmission + * + * @param[in] ptr An Ethernet peripheral base address + * @param[in] config A pointer to a control config structure for tranmission + */ +void enet_get_default_tx_control_config(ENET_Type *ptr, enet_tx_control_config_t *config); + /** * @brief Initialize controller * @@ -547,7 +613,7 @@ enet_frame_t enet_get_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, e enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info, uint32_t rx_desc_count); /** - * @brief prepare for the transmission descriptors + * @brief prepare for the transmission descriptors (It will be deprecated.) * * @param[in] ptr An Ethernet peripheral base address * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames @@ -559,6 +625,19 @@ enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_l */ uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, uint16_t frame_length, uint16_t tx_buff_size); +/** + * @brief prepare for the transmission descriptors + * + * @param[in] ptr An Ethernet peripheral base address + * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames + * @param[in] config a pointer to the control configuration for the transmission frames + * @param[in] frame_length the length of the transmission + * @param[in] tx_buff_size the size of the transmission buffer + * @retval a result of the transmission preparation. + * 1 means that the preparation is successful. + * 0 means that the preparation is unsuccessful. + */ +uint32_t enet_prepare_tx_desc(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, enet_tx_control_config_t *config, uint16_t frame_length, uint16_t tx_buff_size); /** * @brief Initialize DMA transmission descriptors in chain mode * @@ -657,20 +736,24 @@ void enet_set_snapshot_ptp_message_type(ENET_Type *ptr, enet_ts_ss_ptp_msg_t ts_ void enet_set_pps0_control_output(ENET_Type *ptr, enet_pps_ctrl_t freq); /** - * @brief Set the pps0 control config + * @brief Set a pps command for ppsx * * @param[in] ptr An Ethernet peripheral base address - * @param[in] enet_pps_ctrl_t A struct pointer indicating the specified pps command configuration + * @param[in] cmd An enum value indicating the specified pps command + * @param[in] idx An enum value indicating the index of pps instance + * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success */ -void enet_set_pps0_command_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg); +hpm_stat_t enet_set_ppsx_command(ENET_Type *ptr, enet_pps_cmd_t cmd, enet_pps_idx_t idx); /** - * @brief Set the pps0 control config + * @brief Set a pps config for ppsx * * @param[in] ptr An Ethernet peripheral base address - * @param[in] enet_pps_ctrl_t An enum value indicating the specified pps command + * @param[in] cmd An enum value indicating the specified pps config + * @param[in] idx An enum value indicating the index of pps instance + * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success */ -void enet_set_pps0_cmd(ENET_Type *ptr, enet_pps_cmd_t cmd); +hpm_stat_t enet_set_ppsx_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg, enet_pps_idx_t idx); #if defined __cplusplus } diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h index c20622b4..a0cb50e6 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h @@ -138,6 +138,9 @@ static inline void gptmr_channel_update_count(GPTMR_Type *ptr, uint8_t ch_index, uint32_t value) { + if (value > 0) { + value--; + } ptr->CHANNEL[ch_index].CNTUPTVAL = GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(value); ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTUPT_MASK; } @@ -305,6 +308,9 @@ static inline void gptmr_stop_counter(GPTMR_Type *ptr, uint8_t ch_index) */ static inline void gptmr_update_cmp(GPTMR_Type *ptr, uint8_t ch_index, uint8_t cmp_index, uint32_t cmp) { + if (cmp > 0) { + cmp--; + } ptr->CHANNEL[ch_index].CMP[cmp_index] = GPTMR_CHANNEL_CMP_CMP_SET(cmp); } @@ -317,7 +323,10 @@ static inline void gptmr_update_cmp(GPTMR_Type *ptr, uint8_t ch_index, uint8_t c */ static inline void gptmr_channel_config_update_reload(GPTMR_Type *ptr, uint8_t ch_index, uint32_t reload) { - ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(reload - 1); + if (reload > 0) { + reload--; + } + ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(reload); } /** diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h index 0e2c7412..64440b73 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h @@ -239,6 +239,19 @@ static inline uint32_t i2c_get_status(I2C_Type *ptr) return ptr->STATUS; } +/** + * @brief i2c get interrupts setting + * + * @details Get interrupt setting register value + * + * @param [in] ptr I2C base address + * @retval [out] uint32_t interrupt setting register value + */ +static inline uint32_t i2c_get_irq_setting(I2C_Type *ptr) +{ + return ptr->INTEN; +} + /** * @brief disable interrupts * @@ -362,8 +375,9 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, * @param [in] i2c_ptr I2C base address * @param [in] device_address I2C slave address * @param [in] size size of data to be sent in bytes + * @retval hpm_stat_t status_success if starting transmission without any error */ -void i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size); +hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size); /** * @brief I2C master start read data by DMA @@ -374,8 +388,9 @@ void i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address * @param [in] i2c_ptr I2C base address * @param [in] device_address I2C slave address * @param [in] size size of data to be read in bytes + * @retval hpm_stat_t status_success if starting transmission without any error */ -void i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size); +hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size); /** * @brief I2C master read data from certain slave device @@ -467,8 +482,55 @@ static inline void i2c_dma_disable(I2C_Type *ptr) * * @param [in] ptr I2C base address * @param [in] size size of data in bytes + * @retval hpm_stat_t status_success if configuring transmission without any error + */ +hpm_stat_t i2c_slave_dma_transfer(I2C_Type *ptr, const uint32_t size); + +/** + * @brief I2C write byte into FIFO + * + * @param ptr [in] ptr I2C base address + * @param data [in] byte to ne sent + */ +static inline void i2c_write_byte(I2C_Type *ptr, uint8_t data) +{ + ptr->DATA = I2C_DATA_DATA_SET(data); +} + +/** + * @brief I2C read byte into FIFO + * + * @param ptr [in] ptr I2C base address + * @return uint8_t read byte + */ +static inline uint8_t i2c_read_byte(I2C_Type *ptr) +{ + return (uint8_t)I2C_DATA_DATA_GET(ptr->DATA); +} + +/** + * @brief I2C get direction + * + * @note The same value has different meanings in master and slave modes + * + * @param ptr [in] ptr I2C base address + * @return uint8_t direction value + */ +static inline uint8_t i2c_get_direction(I2C_Type *ptr) +{ + return (uint8_t)I2C_CTRL_DIR_GET(ptr->CTRL); +} + +/** + * @brief I2C master configure transfer setting + * + * @param i2c_ptr [in] ptr I2C base address + * @param device_address [in] I2C slave address + * @param size [in] size of data to be transferred in bytes + * @param read [in] true for receive, false for transmit + * @retval hpm_stat_t status_success if configuring transmission without any error */ -void i2c_slave_dma_transfer(I2C_Type *ptr, const uint32_t size); +hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size, bool read); /** * @} diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h index 984dcf46..fc6b9436 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -428,6 +428,14 @@ static inline void i2s_stop_transfer(I2S_Type *ptr) */ hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config); +/** + * @brief I2S config tx for slave + * + * @param [in] ptr I2S base address + * @param [in] config i2s_transfer_config_t + */ +hpm_stat_t i2s_config_tx_slave(I2S_Type *ptr, i2s_transfer_config_t *config); + /** * @brief I2S config rx * @@ -438,6 +446,15 @@ hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config */ hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config); +/** + * @brief I2S config rx for slave + * + * @param [in] ptr I2S base address + * @param [in] config i2s_transfer_config_t + * @retval hpm_stat_t status_invalid_argument or status_success + */ +hpm_stat_t i2s_config_rx_slave(I2S_Type *ptr, i2s_transfer_config_t *config); + /** * @brief I2S config transfer * @@ -448,6 +465,15 @@ hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config */ hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config); +/** + * @brief I2S config transfer for slave + * + * @param [in] ptr I2S base address + * @param [in] config i2s_transfer_config_t + * @retval hpm_stat_t status_invalid_argument or status_success + */ +hpm_stat_t i2s_config_transfer_slave(I2S_Type *ptr, i2s_transfer_config_t *config); + /** * @brief I2S send data * diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_lin_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_lin_drv.h new file mode 100644 index 00000000..917f5151 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_lin_drv.h @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_LIN_DRV_H +#define HPM_LIN_DRV_H + +#include +#include "hpm_common.h" +#include "hpm_lin_regs.h" +#include "hpm_soc_feature.h" + +/** bit4 and bit5 encode data length in ID */ +#define LIN_ID_DATA_LEN_SHIFT 4U +#define LIN_ID_DATA_LEN_MASK 0x30U +#define LIN_ID_DATA_LEN_GET(x) (((uint8_t)(x) & LIN_ID_DATA_LEN_MASK) >> LIN_ID_DATA_LEN_SHIFT) + +/** + * @brief LIN driver APIs + * @defgroup lin_interface LIN driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief data length in ID bit4 and bit5 + */ +typedef enum { + id_data_length_2bytes, + id_data_length_2bytes_2, /**< both 0 and 1 represent 2 bytes */ + id_data_length_4bytes, + id_data_length_8bytes +} lin_id_data_length_t; + +/** + * @brief bus inactivity tome to go to sleep + */ +typedef enum { + bus_inactivity_time_4s, + bus_inactivity_time_6s, + bus_inactivity_time_8s, + bus_inactivity_time_10s +} lin_bus_inactivity_time_t; + +/** + * @brief wakeup repeat time + */ +typedef enum { + wakeup_repeat_time_180ms, + wakeup_repeat_time_200ms, + wakeup_repeat_time_220ms, + wakeup_repeat_time_240ms +} lin_wakeup_repeat_time_t; + +typedef struct { + uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */ + uint32_t baudrate; /**< Baudrate */ +} lin_timing_t; + +/** + * @brief LIN config + */ +typedef struct { + uint8_t id; /**< ID */ + uint8_t *data_buff; /**< data buff */ + bool data_length_from_id; /**< data length should be decoded from the identifier or not) */ + uint8_t data_length; /**< used when data_length_from_id is false */ + bool enhanced_checksum; /**< true for enhanced checksum; false for classic checksum */ + bool transmit; /**< true for transmit operation; false for receive operation */ + /* bool start; */ /**< true for start operation; false for only configuration */ +} lin_trans_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief lin get STATE register value + * + * @param [in] ptr lin base address + * @return uint8_t STATE register value + */ +static inline uint8_t lin_get_status(LIN_Type *ptr) +{ + return ptr->STATE; +} + +/** + * @brief lin reset interrupt + * + * @param ptr lin base address + */ +static inline void lin_reset_interrupt(LIN_Type *ptr) +{ + ptr->CONTROL |= LIN_CONTROL_RESET_INT_MASK; +} + +/** + * @brief lin reset error + * + * @param ptr lin base address + */ +static inline void lin_reset_error(LIN_Type *ptr) +{ + ptr->CONTROL |= LIN_CONTROL_RESET_ERROR_MASK; +} + +/** + * @brief lin wakeup + * + * @param ptr lin base address + */ +static inline void lin_wakeup(LIN_Type *ptr) +{ + ptr->CONTROL |= LIN_CONTROL_WAKEUP_REQ_MASK; +} + +/** + * @brief lin sleep + * + * @param ptr lin base address + */ +static inline void lin_sleep(LIN_Type *ptr) +{ + ptr->CONTROL |= LIN_CONTROL_SLEEP_MASK; +} + +/** + * @brief lin slave stop + * + * @param ptr lin base address + */ +static inline void lin_slave_stop(LIN_Type *ptr) +{ + ptr->CONTROL |= LIN_CONTROL_STOP_MASK; +} + +/** + * @brief lin slave ack + * + * @param ptr lin base address + */ +static inline void lin_slave_ack(LIN_Type *ptr) +{ + ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; +} + +/** + * @brief lin slave set bus inactivity time + * + * @param ptr lin base address + * @param time lin_bus_inactivity_time_t + */ +static inline void lin_slave_set_bus_inactivity_time(LIN_Type *ptr, lin_bus_inactivity_time_t time) +{ + ptr->TV |= LIN_TV_BUS_INACTIVITY_TIME_SET(time); +} + +/** + * @brief lin slave set wakeup repeat time + * + * @param ptr lin base address + * @param time lin_wakeup_repeat_time_t + */ +static inline void lin_slave_set_wakeup_repeat_time(LIN_Type *ptr, lin_wakeup_repeat_time_t time) +{ + ptr->TV |= LIN_TV_WUP_REPEAT_TIME_SET(time); +} + +/** + * @brief lin set mode + * + * @param ptr lin base address + * @param master true for master mode, false for slave mode + */ +static inline void lin_set_mode(LIN_Type *ptr, bool master) +{ + if (master) { + ptr->TV |= LIN_TV_MASTER_MODE_MASK; + } else { + ptr->TV &= ~LIN_TV_MASTER_MODE_MASK; + } +} + +/** + * @brief lin get data value in byte + * + * @param ptr lin base address + * @param index byte index + * @return uint8_t byte value + */ +static inline uint8_t lin_get_data_byte(LIN_Type *ptr, uint8_t index) +{ + return ptr->DATABYTE[index]; +} + +/** + * @brief lin write data value in byte + * + * @param ptr lin base address + * @param index byte index + * @param data byte value + */ +static inline void lin_write_data_byte(LIN_Type *ptr, uint8_t index, uint8_t data) +{ + ptr->DATABYTE[index] = data; +} + +/** + * @brief lin active status + * + * @param ptr lin base address + * @return bool true for active, false for inactive + */ +static inline bool lin_is_active(LIN_Type *ptr) +{ + return ((ptr->STATE & LIN_STATE_LIN_ACTIVE_MASK) == LIN_STATE_LIN_ACTIVE_MASK) ? true : false; +} + +/** + * @brief lin complete status + * + * @param ptr lin base address + * @return bool true for complete, false for incomplete + */ +static inline bool lin_is_complete(LIN_Type *ptr) +{ + return ((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK) ? true : false; +} + +/** + * @brief lin get ID + * + * @param ptr lin base address + * @return uint8_t ID value + */ +static inline uint8_t lin_get_id(LIN_Type *ptr) +{ + return ptr->ID; +} + +/** + * @brief lin configure timing on master mode + * + * @param ptr lin base address + * @param timing lin_timing_t + * @return hpm_stat_t + */ +hpm_stat_t lin_master_configure_timing(LIN_Type *ptr, lin_timing_t *timing); + +/** + * @brief lin config timing on slave mode + * + * @param ptr lin base address + * @param src_freq_in_hz source frequency + * @return hpm_stat_t + */ +hpm_stat_t lin_slave_configure_timing(LIN_Type *ptr, uint32_t src_freq_in_hz); + +/** + * @brief lin transfer on master mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + */ +void lin_master_transfer(LIN_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin transfer on slave mode + * + * @note call this function after lin generate data request interrupt + * + * @param ptr lin base address + * @param config lin_trans_config_t + */ +void lin_slave_transfer(LIN_Type *ptr, lin_trans_config_t *config); + +/** + * @brief get data length + * + * @note data length is determined by DATA_LEN register and ID + * + * @param ptr lin base address + * @return uint8_t data length + */ +uint8_t lin_get_data_length(LIN_Type *ptr); + +/** + * @brief lin send data on master mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_master_sent(LIN_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin receive data on master mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_master_receive(LIN_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin send data on slave mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_slave_sent(LIN_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin receive data on slave mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_slave_receive(LIN_Type *ptr, lin_trans_config_t *config); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_LIN_DRV_H */ + diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h new file mode 100644 index 00000000..de1da77b --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h @@ -0,0 +1,1577 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_MCAN_DRV_H +#define HPM_MCAN_DRV_H + +#include "hpm_common.h" +#include "hpm_mcan_regs.h" +#include "hpm_mcan_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* @brief MCAN driver APIs +* @defgroup mcan_interface MCAN driver APIs +* @ingroup mcan_interfaces +* @{ +* +*/ + + +enum { + status_mcan_filter_index_out_of_range = MAKE_STATUS(status_group_mcan, 0), + status_mcan_rxfifo_empty, + status_mcan_rxfifo_full, + status_mcan_txbuf_full, + status_mcan_txfifo_full, + status_mcan_rxfifo0_busy, + status_mcan_rxfifo1_busy, + status_mcan_txbuf_index_out_of_range, + status_mcan_rxbuf_index_out_of_range, + status_mcan_rxbuf_empty, + status_mcan_tx_evt_fifo_empty, + status_mcan_timestamp_not_exist, + status_mcan_ram_out_of_range, +}; + +/** + * @brief CAN Interrupt Mask + */ +#define MCAN_INT_ACCESS_TO_RESERVED_ADDR MCAN_IR_ARA_MASK /*!< Access to Reserved Address */ +#define MCAN_INT_PROTOCOL_ERR_IN_DATA_PHASE MCAN_IR_PED_MASK /*!< Protocol Error Happened at Data Phase */ +#define MCAN_INT_PROTOCOL_ERR_IN_ARB_PHASE MCAN_IR_PEA_MASK /*!< Protocol Error Happened at Arbitration Phase */ +#define MCAN_INT_WATCHDOG_INT MCAN_IR_WDI_MASK /*!< Watchdog interrupt */ + +#define MCAN_INT_BUS_OFF_STATUS MCAN_IR_BO_MASK /*!< Bus-off State Change */ +#define MCAN_INT_WARNING_STATUS MCAN_IR_EW_MASK /*!< Error Warning State Change */ +#define MCAN_INT_ERROR_PASSIVE MCAN_IR_EP_MASK /*!< Error Passive State Change */ +#define MCAN_INT_ERROR_LOGGING_OVERFLOW MCAN_IR_ELO_MASK /*!< Error Logging Overflow */ +#define MCAN_INT_BIT_ERROR_UNCORRECTED MCAN_IR_BEU_MASK /*!< Bit Error was not corrected */ +#define MCAN_INT_BIT_ERROR_CORRECTED MCAN_IR_BEC_MASK /*!< Bit Error was corrected */ + +#define MCAN_INT_MSG_STORE_TO_RXBUF MCAN_IR_DRX_MASK /*!< Message was stored to RX Buffer */ +#define MCAN_INT_TIMEOUT_OCCURRED MCAN_IR_TOO_MASK /*!< Timeout Interrupt */ +#define MCAN_INT_MSG_RAM_ACCESS_FAILURE MCAN_IR_MRAF_MASK /*!< Message RAM Access Failure */ +#define MCAN_INT_TIMESTAMP_WRAPAROUND MCAN_IR_TSW_MASK /*!< Timestamp Counter Wrap Around */ + +#define MCAN_INT_TX_EVT_FIFO_EVT_LOST MCAN_IR_TEFL_MASK /*!< TX Event FIFO Element Lost */ +#define MCAN_INT_TX_EVT_FIFO_FULL MCAN_IR_TEFF_MASK /*!< TX Event FIFO Full */ +#define MCAN_INT_TX_EVT_FIFO_WMK_REACHED MCAN_IR_TEFW_MASK /*!< TX Event FIFO Watermark Reached */ +#define MCAN_INT_TX_EVT_FIFO_NEW_ENTRY MCAN_IR_TEFN_MASK /*!< TX Event FIFO New Entry */ + +#define MCAN_INT_TXFIFO_EMPTY MCAN_IR_TFE_MASK /*!< TX FIFO Empty */ +#define MCAN_INT_TX_CANCEL_FINISHED MCAN_IR_TCF_MASK /*!< Transmission Cancellation Finished */ +#define MCAN_INT_TX_COMPLETED MCAN_IR_TC_MASK /*!< Transmission Completed */ +#define MCAN_INT_HIGH_PRIORITY_MSG MCAN_IR_HPM_MASK /*!< High Priority Message */ + +#define MCAN_INT_RXFIFO1_MSG_LOST MCAN_IR_RF1L_MASK /*!< RX FIFO0 Message Lost */ +#define MCAN_INT_RXFIFO1_FULL MCAN_IR_RF1F_MASK /*!< RX FIFO1 Full */ +#define MCAN_INT_RXFIFO1_WMK_REACHED MCAN_IR_RF1W_MASK /*!< RX FIFO1 Watermark Reached */ +#define MCAN_INT_RXFIFO1_NEW_MSG MCAN_IR_RF1N_MASK /*!< RX FIFO1 New Message */ + +#define MCAN_INT_RXFIFO0_MSG_LOST MCAN_IR_RF0L_MASK /*!< RX FIFO0 Message Lost */ +#define MCAN_INT_RXFIFO0_FULL MCAN_IR_RF0F_MASK /*!< RX FIFO0 Full */ +#define MCAN_INT_RXFIFO0_WMK_REACHED MCAN_IR_RF0W_MASK /*!< RX FIFO0 Watermark Reached */ +#define MCAN_INT_RXFIFI0_NEW_MSG MCAN_IR_RF0N_MASK /*!< RX FIFO0 New Message */ + +/** + * @brief MCAN Receive Event Flags + */ +#define MCAN_EVENT_RECEIVE (MCAN_INT_RXFIFI0_NEW_MSG | MCAN_INT_RXFIFO1_NEW_MSG | MCAN_INT_MSG_STORE_TO_RXBUF) + +/** + * @brief MCAN Transmit Event Flags + */ +#define MCAN_EVENT_TRANSMIT (MCAN_INT_TX_COMPLETED) +/** + * @brief MCAN Error Event Flags + */ +#define MCAN_EVENT_ERROR (MCAN_INT_BUS_OFF_STATUS | MCAN_INT_WARNING_STATUS \ + | MCAN_INT_ERROR_PASSIVE | MCAN_INT_BIT_ERROR_UNCORRECTED) + +/** + * @brief Maximum Transmission Retry Count + */ +#define MCAN_TX_RETRY_COUNT_MAX (10000000UL) +/** + * @brief Maximum Receive Wait Retry Count + */ +#define MCAN_RX_RETRY_COUNT_MAX (80000000UL) + +/*********************************************************************************************************************** + * @brief Default CAN RAM definitions + **********************************************************************************************************************/ +#define MCAN_RAM_WORD_SIZE (640U) /*!< RAM WORD Size */ +/* CAN Filter Element Size Definitions */ +#define MCAN_FILTER_ELEM_STD_ID_SIZE (4U) /*!< Standard Filter Element Size in Bytes */ +#define MCAN_FILTER_ELEM_EXT_ID_SIZE (8U) /*!< Extended Filter Element SIze in Bytes */ +#define MCAN_STD_FILTER_ELEM_SIZE_MAX (128U) /*!< Maximum Standard Filter Element Count */ +#define MCAN_EXT_FILTER_ELEM_SIZE_MAX (64U) /*!< Maximum Extended Filter Element Count */ +/* MCAN Default Field Size Definitions for CAN2.0 */ +#define MCAN_TXRX_ELEM_SIZE_CAN_MAX (4U * sizeof(uint32_t)) +#define MCAN_FILTER_SIZE_CAN_DEFAULT (32U) +#define MCAN_TXBUF_SIZE_CAN_DEFAULT (32U) +#define MCAN_RXFIFO_SIZE_CAN_DEFAULT (32U) +#define MCAN_RXBUF_SIZE_CAN_DEFAULT (16U) +/* MCAN Default Field Size Definitions for CANFD */ +#define MCAN_TXRX_ELEM_SIZE_CANFD_MAX (18U * sizeof(uint32_t)) +#define MCAN_FILTER_SIZE_CANFD_DEFAULT (16U) +#define MCAN_TXBUF_SIZE_CANFD_DEFAULT (8U) +#define MCAN_RXFIFO_SIZE_CANFD_DEFAULT (8U) +#define MCAN_RXBUF_SIZE_CANFD_DEFAULT (4U) + +#define MCAN_TXEVT_ELEM_SIZE (8U) + +/** + * @brief CAN Bit Timing Parameters + */ +typedef struct mcan_bit_timing_param_struct { + uint16_t prescaler; /*!< Data Bit Rate Prescaler */ + uint16_t num_seg1; /*!< Time segment before sample point (including prop_seg and phase_sge1 */ + uint16_t num_seg2; /*!< Time segment after sample point */ + uint8_t num_sjw; /*!< Data (Re)Synchronization Jump Width */ + bool enable_tdc; /*!< Enable TDC flag, for CANFD data bit timing only */ +} mcan_bit_timing_param_t; + +/** + * @brief CAN Bit Timing Options + */ +typedef enum mcan_bit_timing_option { + mcan_bit_timing_can2_0, /**< CAN 2.0 bit timing option */ + mcan_bit_timing_canfd_nominal, /**< CANFD nominal timing option */ + mcan_bit_timing_canfd_data, /**< CANFD data timing option */ +} mcan_bit_timing_option_t; + +/** + * @brief CAN Message Header Size + */ +#define MCAN_MESSAGE_HEADER_SIZE_IN_BYTES (8U) +#define MCAN_MESSAGE_HEADER_SIZE_IN_WORDS (2U) + +/** + * @brief CAN Transmit Message Frame + * + * @note Users need to pay attention to the CAN Identifier settings + * For standard identifier, the use_ext_id should be set to 0 and the std_id should be used + * For extended identifier, the use_ext_id should be set to 1 and the ext_id should be used + */ +typedef struct mcan_tx_message_struct { + union { + struct { + uint32_t ext_id: 29; /*!< Extended CAN Identifier */ + uint32_t rtr: 1; /*!< Remote Transmission Request */ + uint32_t use_ext_id: 1; /*!< Extended Identifier */ + uint32_t error_state_indicator: 1; /*!< Error State Indicator */ + }; + struct { + uint32_t : 18; + uint32_t std_id: 11; /*!< Standard CAN Identifier */ + uint32_t : 3; + }; + }; + struct { + uint32_t : 8; + uint32_t message_marker_h: 8; /*!< Message Marker[15:8] */ + uint32_t dlc: 4; /*!< Data Length Code */ + uint32_t bitrate_switch: 1; /*!< Bit Rate Switch */ + uint32_t canfd_frame: 1; /*!< CANFD frame */ + uint32_t timestamp_capture_enable: 1; /*!< Timestamp Capture Enable for TSU */ + uint32_t event_fifo_control: 1; /*!< Event FIFO control */ + uint32_t message_marker_l: 8; /*!< Message Marker[7:0] */ + }; + union { + uint8_t data_8[64]; /*!< Data buffer as byte array */ + uint32_t data_32[16]; /*!< Data buffer as word array */ + }; +} mcan_tx_frame_t; + +/** + * @brief CAN Receive Message Frame + * + * @note Users need to pay attention to the CAN Identifier settings + * For standard identifier, the use_ext_id should be set to 0 and the std_id should be used + * For extended identifier, the use_ext_id should be set to 1 and the ext_id should be used + */ +typedef struct mcan_rx_message_struct { + union { + struct { + uint32_t ext_id: 29; /*!< Extended CAN Identifier */ + uint32_t rtr: 1; /*!< Remote Frame Flag */ + uint32_t use_ext_id: 1; /*!< Extended Identifier */ + uint32_t error_state_indicator: 1; /*!< Error State Indicator */ + }; + struct { + uint32_t : 18; + uint32_t std_id: 11; /*!< Standard CAN Identifier */ + uint32_t : 3; + }; + }; + struct { + union { + uint16_t rx_timestamp; /*!< Received timestamp */ + struct { + uint16_t rx_timestamp_pointer: 4; /*!< Timestamp Pointer */ + uint16_t rx_timestamp_captured: 1; /*!< Timestamp Captured flag */ + uint16_t : 11; + }; + }; + }; + struct { + uint16_t dlc: 4; /*!< Data Length Code */ + uint16_t bitrate_switch: 1; /*!< Bit rate switch flag */ + uint16_t canfd_frame: 1; /*!< CANFD Frame flag */ + uint16_t : 1; + uint16_t filter_index: 7; /*!< CAN filter index */ + uint16_t accepted_non_matching_frame: 1; /*!< Accept non-matching Frame flag */ + }; + union { + uint8_t data_8[64]; /*!< Data buffer as byte array */ + uint32_t data_32[16]; /*!< Data buffer as word array */ + }; +} mcan_rx_message_t; + +/** + * @brief TX Event Fifo Element Structure + */ +typedef union mcan_tx_event_fifo_elem_struct { + struct { + /* First word */ + union { + struct { + uint32_t ext_id: 29; /*!< CAN Identifier */ + uint32_t rtr: 1; /*!< Remote Transmission Request */ + uint32_t extend_id: 1; /*!< Extended Identifier */ + uint32_t error_state_indicator: 1; /*!< Error State Indicator */ + }; + struct { + uint32_t : 18; + uint32_t std_id: 11; + uint32_t : 3; + }; + }; + + /* first 16-bit of the 2nd word */ + union { + uint16_t tx_timestamp; /*!< Tx Timestamp */ + struct { + uint16_t tx_timestamp_pointer: 4; /*!< TX timestamp pointer */ + uint16_t tx_timestamp_captured: 1; /*!< TX timestamp captured flag */ + uint16_t : 11; + }; + }; + /* high-half 16-bit of the 2nd word */ + struct { + uint16_t dlc: 4; /*!< Data length code */ + uint16_t bitrate_switch: 1; /*!< Bitrate Switch flag */ + uint16_t canfd_frame: 1; /*!< CANFD frame */ + uint16_t event_type: 2; /*!< Event type */ + uint16_t message_marker: 8; /*!< Message Marker */ + }; + }; + uint32_t words[2]; +} mcan_tx_event_fifo_elem_t; + + + +/** + * @brief CAN Identifier Types + */ +#define MCAN_CAN_ID_TYPE_STANDARD (0U) /*!< Standard Identifier */ +#define MCAN_CAN_ID_TYPE_EXTENDED (1U) /*!< Extended Identifier */ + +/** + * @brief MCAN Filter Configuration + */ +typedef union mcan_filter_config_struct { + struct { + uint16_t list_start_addr; /*!< List Start address (CAN Message Buffer Offset) */ + uint16_t list_size; /*!< Element Count */ + }; + uint32_t reg_val; /*!< Register value */ +} mcan_filter_config_t; + +/** + * @brief MCAN RXFIFO Configuration + */ +typedef union mcan_rxfifo_config_struct { + struct { + uint32_t start_addr: 16; /*!< Start address (CAN Message Buffer Offset) */ + uint32_t fifo_size: 8; /*!< FIFO element count */ + uint32_t watermark: 7; /*!< FIFO watermark */ + uint32_t operation_mode: 1; /*!< Operation mode */ + }; + uint32_t reg_val; /*!< Register value */ +} mcan_rxfifo_config_t; + +/** + * @brief MCAN RXBUF Configuration + */ +typedef struct { + uint32_t start_addr; /*!< Start address (CAN Message Buffer Offset) */ +} mcan_rxbuf_config_t; + +/** + * @brief MCAN Data Field Size Definitions + */ +#define MCAN_DATA_FIELD_SIZE_8BYTES (0U) +#define MCAN_DATA_FIELD_SIZE_12BYTES (1U) +#define MCAN_DATA_FIELD_SIZE_16BYTES (2U) +#define MCAN_DATA_FIELD_SIZE_20BYTES (3U) +#define MCAN_DATA_FIELD_SIZE_24BYTES (4U) +#define MCAN_DATA_FIELD_SIZE_32BYTES (5U) +#define MCAN_DATA_FIELD_SIZE_48BYTES (6U) +#define MCAN_DATA_FIELD_SIZE_64BYTES (7U) + +/** + * @brief MCAN FIFO Operation Mode types + */ +#define MCAN_FIFO_OPERATION_MODE_BLOCKING (0U) +#define MCAN_FIFO_OPERATION_MODE_OVERWRITE (1U) + +/** + * @brief MCAN RXBUF or RXFIFO Element Configuration + */ +typedef union mcan_rx_fifo_or_buf_elem_config_struct { + struct { + uint32_t fifo0_data_field_size: 4; /*!< FIFO0 data field size option */ + uint32_t fifo1_data_field_size: 4; /*!< FIFO1 data field size option */ + uint32_t buf_data_field_size: 4; /*!< Buffer Data field size option */ + uint32_t : 20; + }; + uint32_t reg_val; /*!< Register value */ +} mcan_rx_fifo_or_buf_elem_config_t; + +/** + * @brief MCAN TXBUF operation mode types + */ +#define MCAN_TXBUF_OPERATION_MODE_FIFO (0U) +#define MCAN_TXBUF_OPERATION_MODE_QUEUE (1U) + + +typedef union mcan_txbuf_config_struct { + struct { + uint32_t start_addr: 16; /*!< Start address (CAN Message Buffer Offset) */ + uint32_t dedicated_tx_buf_size: 6; /*!< Dedicated TX buffer size */ + uint32_t : 2; + uint32_t fifo_queue_size: 6; /*!< FIFO or Queue Size */ + uint32_t tx_fifo_queue_mode: 1; /*!< FIFO or Queue mode selection */ + uint32_t : 1; + }; + uint32_t reg_val; /*!< register value */ +} mcan_txbuf_config_t; + +typedef struct mcan_txbuf_elem_config_struct { + uint32_t data_field_size; /*!< Data Field size option */ +} mcan_txbuf_elem_config_t; + +/** + * @brief MCAN TX Event FIFO Structure + */ +typedef union { + struct { + uint16_t start_addr; /*!< Start Address(CAN Message Buffer Offset */ + uint8_t fifo_size; /*!< FIFO element count */ + uint8_t fifo_watermark; /*!< FIFO watermark */ + }; + uint32_t reg_val; /*!< register value */ +} mcan_tx_evt_fifo_config_t; + +/** + * @brief MCAN RAM Flexible Configuration + * + * @Note This Configration provides the full MCAN RAM configuration, this configuration is recommended only for + * experienced developers who is skilled at the MCAN IP + */ +typedef struct mcan_ram_flexible_config_struct { + bool enable_std_filter; /*!< Enable Standard Identifier Filter */ + bool enable_ext_filter; /*!< Enable Extended Identifier Filter */ + bool enable_rxfifo0; /*!< Enable RXFIFO */ + bool enable_rxfifo1; /*!< Enable RXFIF1 */ + bool enable_rxbuf; /*!< Enable RXBUF */ + bool enable_txbuf; /*!< Enable TXBUF */ + bool enable_tx_evt_fifo; /*!< Enable TX Event FIFO */ + + mcan_filter_config_t std_filter_config; /*!< Standard Identifier Filter Configuration */ + mcan_filter_config_t ext_filter_config; /*!< Extended Identifier Filter Configuration */ + + mcan_txbuf_config_t txbuf_config; /*!< TXBUF Configuration */ + mcan_txbuf_elem_config_t txbuf_elem_config; /*!< TXBUF Element Configuration */ + mcan_tx_evt_fifo_config_t tx_evt_fifo_config; /*!< TX Event FIFO Configuration */ + + mcan_rxfifo_config_t rxfifo0_config; /*!< RXFIFO0 Configuration */ + mcan_rxfifo_config_t rxfifo1_config; /*!< RXFIFO1 Configuration */ + mcan_rxbuf_config_t rxbuf_config; /*!< RXBUF Configuration */ + mcan_rx_fifo_or_buf_elem_config_t rx_elem_config; /*!< RX Element Configuration */ +} mcan_ram_flexible_config_t; + +/** + * @brief MCAN RAM configuration + * + * @Note: This Configuration focuses on the minimum required information for MCAN RAM configuration + * The Start address of each BUF/FIFO will be automatically calculated by the MCAN Driver API + * This RAM configuration is recommended for the most developers + */ +typedef struct mcan_ram_config_struct { + bool enable_std_filter; /*!< Enable Standard Identifier Filter */ + uint8_t std_filter_elem_count; /*!< Standard Identifier Filter Element Count */ + + bool enable_ext_filter; /*!< Enable Extended Identifier Filter */ + uint8_t ext_filter_elem_count; /*!< Extended Identifier Filter Element Count */ + + struct { + uint32_t enable: 4; /*!< Enable Flag for RXFIFO */ + uint32_t elem_count: 8; /*!< Element Count for RXFIFO */ + uint32_t watermark: 8; /*!< Watermark for RXFIFO */ + uint32_t operation_mode: 4; /*!< Operation Mode for RXFIFO */ + uint32_t data_field_size: 8; /*!< Data field size option for RXFIFO */ + } rxfifos[2]; + + bool enable_rxbuf; /*!< Enable RXBUF */ + uint8_t rxbuf_elem_count; /*!< RXBUF Element count */ + uint16_t rxbuf_data_field_size; /*!< RXBUF Data Field Size option */ + + bool enable_txbuf; /*!< Enable TXBUF */ + uint8_t txbuf_data_field_size; /*!< TXBUF Data Field Size option */ + uint8_t txbuf_dedicated_txbuf_elem_count; /*!< Dedicated TXBUF element count */ + uint8_t txbuf_fifo_or_queue_elem_count; /*!< FIFO/Queue element count */ + uint8_t txfifo_or_txqueue_mode; /*!< TXFIFO/QUEUE mode */ + + bool enable_tx_evt_fifo; /*!< Enable TX Event FIFO */ + uint8_t tx_evt_fifo_elem_count; /*!< TX Event FIFO Element count */ + uint8_t tx_evt_fifo_watermark; /*!< TX Event FIFO Watermark */ +} mcan_ram_config_t; + +/** + * @brief MCAN Accept Non-Matching Frame options + */ +#define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0 (0U) /*!< Save non-matching frame to RXFIFO0 */ +#define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO1 (1U) /*!< Save non-matching frame to RXFIFO1 */ +#define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT (2U) /*!< Reject non-matching frame */ + +/** + * @brief MCAN Global CAN configuration + */ +typedef struct mcan_global_filter_config_struct { + uint8_t accept_non_matching_std_frame_option; /*!< Accept non-matching standard frame option */ + uint8_t accept_non_matching_ext_frame_option; /*!< Accept non-matching extended frame option */ + bool reject_remote_std_frame; /*!< Reject Remote Standard Frame */ + bool reject_remote_ext_frame; /*!< Reject Remote Extended Frame */ +} mcan_global_filter_config_t; + +/** + * @brief MCAN Filter type definitions + */ +#define MCAN_FILTER_TYPE_RANGE_FILTER (0U) /*!< CAN Identifier Range filter */ +#define MCAN_FILTER_TYPE_SPECIFIED_ID_FILTER (1U) /*!< CAN Identifier ID filter */ +#define MCAN_FILTER_TYPE_CLASSIC_FILTER (2U) /*!< CAN classic filter */ +#define MCAN_FILTER_TYPE_FILTER_DISABLED (3U) /*!< CAN filter disabled */ +#define MCAN_FILTER_TYPE_DUAL_ID_EXT_FILTER_IGNORE_MASK /*!< CAN Identifier Range filter, ignoring extended ID mask */ + +/** + * @brief MCAN Filter Configuration Options + */ +#define MCAN_FILTER_ELEM_CFG_DISABLED (0) /*!< Disable Filter Element */ +#define MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH (1U) /*!< Store data into RXFIFO0 if matching */ +#define MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO1_IF_MATCH (2U) /*!< Store data into RXFIFO1 if matching */ +#define MCAN_FILTER_ELEM_CFG_REJECT_ID_IF_MATCH (3U) /*!< Reject ID if matching */ +#define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_IF_MATCH (4U) /*!< Set Priority if matching */ +/*!< Set Priority and store into RXFIFO0 if matching */ +#define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_AND_STORE_IN_FIFO0_IF_MATCH (5U) +/*!< Set Priority and store into RXFIFO1 if matching */ +#define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_AND_STORE_IN_FIFO1_IF_MATCH (6U) +#define MCAN_FILTER_ELEM_CFG_STORE_INTO_RX_BUFFER_OR_AS_DBG_MSG (7U) /*!< Store into RXBUF if matching */ + +/** + * @brief MCAN Filter Element definitions + */ +typedef struct mcan_std_id_filter_elem_struct { + uint8_t filter_type; /*!< Filter type */ + uint8_t filter_config; /*!< Filter configuration */ + uint8_t can_id_type; /*!< CAN ID type */ + uint8_t sync_message; /*!< Sync Message */ + union { + /* This definition takes effect if the filter type is range filter */ + struct { + uint32_t start_id; /*!< Start of ID range */ + uint32_t end_id; /*!< End of ID range */ + }; + /* This definition takes effect if the filter type is dual id filter */ + struct { + uint32_t id1; /*!< ID1 */ + uint32_t id2; /*!< ID2 */ + }; + /* This definition takes effect if the filter type is classic filter */ + struct { + uint32_t filter_id; /*!< Filter ID */ + uint32_t filter_mask; /*!< Filter Mask */ + }; + /* This definition takes effect if the filter configuration is "store into RX Buffer or as debug message" + * + * In this definition, only the extact ID matching mode is activated + */ + struct { + uint32_t match_id; /*!< Matching ID */ + uint32_t offset: 6; /*!< RX Buffer Index */ + uint32_t filter_event: 3; /*!< Filter event, set to 0 */ + uint32_t store_location: 2; /*!< Store location, 0 - RX buffer */ + uint32_t : 21; + }; + }; +} mcan_filter_elem_t; + +/** + * @brief MCAN Filter Element List structure + */ +typedef struct mcan_filter_elem_list_struct { + uint32_t mcan_filter_elem_count; /*!< Number of Filter element */ + const mcan_filter_elem_t *filter_elem_list; /*!< Filter element list */ +} mcan_filter_elem_list_t; + +/** + * @brief MCAN Configuration for all filters + * + * @Note The MCAN RAM related settings are excluded + */ +typedef struct mcan_all_filters_config_struct { + mcan_global_filter_config_t global_filter_config; /*!< Global Filter configuration */ + uint32_t ext_id_mask; /*!< Extended ID mask */ + mcan_filter_elem_list_t std_id_filter_list; /*!< Standard Identifier Configuration List */ + mcan_filter_elem_list_t ext_id_filter_list; /*!< Extended Identifier Configuration List */ +} mcan_all_filters_config_t; + +/** + * @brief CAN Node Mode types + */ +typedef enum mcan_node_mode_enum { + mcan_mode_normal = 0, /*!< CAN works in normal mode */ + mcan_mode_loopback_internal = 1, /*!< CAN works in internal loopback mode */ + mcan_mode_loopback_external = 2, /*!< CAN works in external loopback mode */ + mcan_mode_listen_only = 3, /*!< CAN works in listen-only mode */ +} mcan_node_mode_t; + +/** + * @brief MCAN Timestamp Value + */ +typedef struct mcan_timestamp_value_struct { + bool is_16bit; /*!< Timestamp is 16-bit */ + bool is_32bit; /*!< Timestamp is 32-bit */ + bool is_64bit; /*!< Timestamp is 64-bit */ + bool is_empty; /*!< Timestamp is empty */ + union { + uint16_t ts_16bit; /*!< 16-bit timestamp value */ + uint32_t ts_32bit; /*!< 32-bit timestamp value */ + uint64_t ts_64bit; /*!< 64-bit timestamp value */ + uint32_t words[2]; /*!< timestamp words */ + }; +} mcan_timestamp_value_t; + +/** + * @brief MCAN TSU Configuration + */ +typedef struct mcan_tsu_config_struct { + uint16_t prescaler; /*!< Prescaler for MCAN clock, Clock source: AHB clock */ + bool capture_on_sof; /*!< Capture On SOF, true - Capture on SOF, false - Capture on EOF */ + bool use_ext_timebase; /*!< Use External Timebase */ + uint16_t ext_timebase_src; /*!< External Timebase source, see the hpm_mcan_soc.h for more details */ + bool enable_tsu; /*!< Enable Timestamp Unit */ + bool enable_64bit_timestamp; /*!< Enable 64bit Timestamp */ +} mcan_tsu_config_t; + +/** + * @brief MCAN Timestamp Select + */ +#define MCAN_TIMESTAMP_SEL_MIN (0U) +#define MCAN_TIMESTAMP_SEL_VALUE_ALWAYS_ZERO (0U) /*!< Timestamp value always equal to 0 */ +#define MCAN_TIMESTAMP_SEL_VALUE_INCREMENT (1U) /*!< Timestamp value increments according to prescaler */ +#define MCAN_TIMESTAMP_SEL_EXT_TS_VAL_USED (2U) /*!< External Timestamp value used */ +#define MCAN_TIMESTAMP_SEL_MAX (MCAN_TIMESTAMP_SEL_EXT_TS_VAL_USED) + +/** + * @brief MCAN Internal timestamp configuration + */ +typedef struct mcan_internal_timestamp_config_struct { + uint8_t counter_prescaler; /*!< Timestamp Counter Prescaler, clock source: AHB clock */ + uint8_t timestamp_selection; /*!< Timestamp Select */ +} mcan_internal_timestamp_config_t; + +/** + * @brief MCAN Configuration Structure + */ +typedef struct mcan_config_struct { + union { + /* This struct takes effect if use_lowlevl_timing_setting = false */ + struct { + uint32_t baudrate; /*!< CAN 2.0 baudrate/CAN-FD Nominal Baudrate, in terms of bps */ + uint32_t baudrate_fd; /*!< CANFD data baudrate, in terms of bps */ + uint16_t can20_samplepoint_min; /*!< Value = Minimum CAN2.0 sample point * 10 */ + uint16_t can20_samplepoint_max; /*!< Value = Maximum CAN2.0 sample point * 10 */ + uint16_t canfd_samplepoint_min; /*!< Value = Minimum CANFD sample point * 10 */ + uint16_t canfd_samplepoint_max; /*!< Value = Maximum CANFD sample point * 10 */ + }; + /* This struct takes effect if use_lowlevl_timing_setting = true */ + struct { + mcan_bit_timing_param_t can_timing; /*!< CAN2.0/CANFD nominal timing setting */ + mcan_bit_timing_param_t canfd_timing; /*!< CANFD data timing setting */ + }; + }; + bool use_lowlevel_timing_setting; /*!< Use Low-level timing setting */ + mcan_node_mode_t mode; /*!< CAN node mode */ + bool enable_non_iso_mode; /*!< Enable Non-ISO FD mode */ + bool enable_transmit_pause; /*!< Enable Transmit Pause */ + bool enable_edge_filtering; /*!< Enable Edge Filtering */ + bool disable_protocol_exception_handling; /*!< Disable Protocol Exception Handling */ + bool enable_wide_message_marker; /*!< Enable Wide Message Marker */ + bool use_timestamping_unit; /*!< Use external Timestamp Unit */ + bool enable_canfd; /*!< Enable CANFD mode */ + bool enable_tdc; /*!< Enable transmitter delay compensation */ + mcan_internal_timestamp_config_t timestamp_cfg; /*!< Internal Timestamp Configuration */ + mcan_tsu_config_t tsu_config; /*!< TSU configuration */ + mcan_ram_config_t ram_config; /*!< MCAN RAM configuration */ + mcan_all_filters_config_t all_filters_config; /*!< All Filter configuration */ +} mcan_config_t; + +/** + * @brief MCAN Timeout Selection Options + */ +#define MCAN_TIMEOUT_SEL_TYPE_CONTINUOUS_OPERATION (0U) +#define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_TX_EVT_FIFO (1U) +#define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_RX_FIFO0 (2U) +#define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_RX_FIFO1 (3U) + +/** + * @brief MCAN Timeout Counter Configuration + */ +typedef struct mcan_timeout_counter_config_struct { + bool enable_timeout_counter; /*!< Enable Timeout counter */ + uint8_t timeout_selection; /*!< Timeout source selection */ + uint16_t timeout_period; /*!< Timeout period */ +} mcan_timeout_counter_config_t; + +/** + * @brief MCAN Error Count Information + */ +typedef struct mcan_error_count_struct { + uint8_t transmit_error_count; /*!< Transmit Error Count */ + uint8_t receive_error_count; /*!< Receive Error Count */ + bool receive_error_passive; /*!< The Receive Error Counter has reached the error passive level */ + uint8_t can_error_logging_count; /*!< CAN Error Logging count */ +} mcan_error_count_t; + +/** + * @brief MCAN Transmitter Delay Compensation Configuration + */ +typedef struct mcan_tdc_config_t { + uint8_t ssp_offset; /*!< SSP offset */ + uint8_t filter_window_length; /*!< Filter Window Length */ +} mcan_tdc_config_t; + + +/** + * @brief MCAN Message Storage Indicator Types + */ +#define MCAN_MESSAGE_STORAGE_INDICATOR_NO_FIFO_SELECTED (0U) +#define MCAN_MESSAGE_STORAGE_INDICATOR_FIFO_MESSAGE_LOST (1U) +#define MCAN_MESSAGE_STORAGE_INDICATOR_RXFIFO0 (2U) +#define MCAN_MESSAGE_STORAGE_INDICATOR_RXFIFO1 (3U) + +/** + * @brief MCAN High Priority Message Status Information + */ +typedef struct mcan_high_priority_message_status_struct { + uint8_t filter_list_type; /*!< Filter List Type, 0 - STD filter, 1 - EXT filter */ + uint8_t filter_index; /*!< Filter Elem List */ + uint8_t message_storage_indicator; /*!< Message Storage Indicator */ + uint8_t buffer_index; +} mcan_high_priority_message_status_t; + +/** + * @brief Enable Transmit Pause + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_transmit_pause(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_TXP_MASK; +} + +/** + * @brief Disable Transmit Pause + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_transmit_pause(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_TXP_MASK; +} + +/** + * @brief Enable Edge Filtering + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_edge_filtering(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_EFBI_MASK; +} + +/** + * @brief Disable Edge Filtering + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_edge_filtering(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_EFBI_MASK; +} + +/** + * @brief Enable Protocol Exception Handling + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_protocol_exception_handling(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_PXHD_MASK; +} + +/** + * @brief Disable Protocol Exception Handling + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_protocol_exception_handling(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_PXHD_MASK; +} + +/** + * @brief Enable Wide Message Marker + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_wide_message_marker(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_WMM_MASK; +} + +/** + * @brief Disable Wide Message Marker + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_wide_message_marker(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_WMM_MASK; +} + +/** + * @brief Enable External Timestamp Unit + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_tsu(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_UTSU_MASK; +} + +/** + * @brief Disable External Timestamp Unit + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_tsu(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_UTSU_MASK; +} + +/** + * @brief Check whether TSU is used + * @param [in] ptr MCAN base + * @retval true if TSU is used + * @retval false if TSU is not used + */ +static inline bool mcan_is_tsu_used(MCAN_Type *ptr) +{ + return ((ptr->CCCR & MCAN_CCCR_UTSU_MASK) != 0U); +} + +/** + * @brief Check whether 64-bit TSU timestamp is used + * @param [in] ptr MCAN base + * @retval true if 64-bit timestamp is used + * @retval false if 32-bit timestamp is used + */ +static inline bool mcan_is_64bit_tsu_timestamp_used(MCAN_Type *ptr) +{ + return ((ptr->TSCFG & MCAN_TSCFG_EN64_MASK) != 0U); +} + +/** + * @brief Enable Bit Rate Switch + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_bitrate_switch(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_BRSE_MASK; +} + +/** + * @brief Disable Bit Rate Switch + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_bitrate_switch(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_BRSE_MASK; +} + +/** + * @brief Enable Auto Retransmission + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_auto_retransmission(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_DAR_MASK; +} + +/** + * @brief Disable Auto Transmission + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_auto_retransmission(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_DAR_MASK; +} + +/** + * @brief Disable Bus monitoring Mode + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_bus_monitoring_mode(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_MON_MASK; +} + +/** + * @brief Enable Clock Stop Request + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_clock_stop_request(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_CSR_MASK; +} + +/** + * @brief Disable Clock Stop Request + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_clock_stop_request(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_CSR_MASK; +} + +/** + * @brief Enable Clock Stop Acknowledge + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_clock_stop_acknowledge(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_CSA_MASK; +} + +/** + * @brief Disable Clock Stop Acknowledge + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_clock_stop_acknowledge(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_CSA_MASK; +} + +/** + * @brief Disable Restricted Operation Mode + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_restricted_operation_mode(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_ASM_MASK; +} + +/** + * @brief Get Timestamp Counter Value + * @param [in] ptr MCAN base + * @return timestamp value + */ +static inline uint16_t mcan_get_timestamp_counter_value(MCAN_Type *ptr) +{ + return ptr->TSCV; +} + +/** + * @brief Get Timeout value + * @param [in] ptr MCAN base + * @return timeout value + */ +static inline uint16_t mcan_get_timeout_counter_value(MCAN_Type *ptr) +{ + return ptr->TOCV; +} + +/** + * @brief Get Error Counter Information + * @param [in] ptr MCAN base + * @param [out] err_cnt Error Count buffer + */ +static inline void mcan_get_error_counter(MCAN_Type *ptr, mcan_error_count_t *err_cnt) +{ + uint32_t ecr = ptr->ECR; + err_cnt->transmit_error_count = MCAN_ECR_TEC_GET(ecr); + err_cnt->receive_error_count = MCAN_ECR_REC_GET(ecr); + err_cnt->receive_error_passive = (MCAN_ECR_RP_GET(ecr) == 1U); + err_cnt->can_error_logging_count = MCAN_ECR_CEL_GET(ecr); +} + +/** + * @brief Get Last Error Code + * @param [in] ptr MCAN base + * @return Last Error code + */ +static inline uint8_t mcan_get_last_error_code(MCAN_Type *ptr) +{ + return MCAN_PSR_LEC_GET(ptr->PSR); +} + +/** + * @brief Get Last Data Phase Error Code + * @param [in] ptr MCAN base + * @return Last Error Code in Data phase + */ +static inline uint8_t mcan_get_last_data_error_code(MCAN_Type *ptr) +{ + return MCAN_PSR_DLEC_GET(ptr->PSR); +} + +/** + * @brief Get CAN Activity + * @param [in] ptr MCAN base + * @return CAN IP activity + */ +static inline uint8_t mcan_get_activity(MCAN_Type *ptr) +{ + return MCAN_PSR_ACT_GET(ptr->PSR); +} + +/** + * @brief Check whether the CAN node is under error passive state + * @param [in] ptr MCAN base + * @return true is CAN is under error passive state + */ +static inline bool mcan_is_in_err_passive_state(MCAN_Type *ptr) +{ + return (MCAN_PSR_EP_GET(ptr->PSR) == 1U); +} + +/** + * @brief Check whether the CAN mode is under Warning State + * @param [in] ptr MCAN base + * @return true if the CAN node is under Error Warning State + */ +static inline bool mcan_is_in_error_warning_state(MCAN_Type *ptr) +{ + return (MCAN_PSR_EW_GET(ptr->PSR) == 1U); +} + +/** + * @brief Check whether the CAN node is under Bus-off state + * @param [in] ptr MCAN base + * @return true if the CAN node is under Bus-off state + */ +static inline bool mcan_is_in_busoff_state(MCAN_Type *ptr) +{ + return (MCAN_PSR_BO_GET(ptr->PSR) == 1U); +} + +/** + * @brief Get the Last Data Phase Error + * @param [in] ptr MCAN base + * @return The last Data Phase Error + */ +static inline uint8_t mcan_get_data_phase_last_error_code(MCAN_Type *ptr) +{ + return MCAN_PSR_DLEC_GET(ptr->PSR); +} + +/** + * @brief Check Whether the Error Status Indicator Flag is set in the last received CANFD message + * @param [in] ptr MCAN base + * @return true if the Error Status Indicator Flag is set in the last received CANFD Message + */ +static inline bool mcan_is_error_state_indicator_flag_set_in_last_received_canfd_msg(MCAN_Type *ptr) +{ + return (MCAN_PSR_RESI_GET(ptr->PSR) == 1U); +} + +/** + * @brief Check whether the Bitrate Switch Flag is set in the last received CANFD message + * @param [in] ptr MCAN base + * @return true if Bit rate switch flag is set in the last received CANFD message + */ +static inline bool mcan_is_bitrate_switch_flag_set_in_last_received_canfd_msg(MCAN_Type *ptr) +{ + return (MCAN_PSR_RBRS_GET(ptr->PSR) == 1U); +} + +/** + * @brief Check whether CANFD messages were received + * @param [in] ptr MCAN base + * @return true if a CANFD message was received + */ +static inline bool mcan_is_canfd_message_received(MCAN_Type *ptr) +{ + return (MCAN_PSR_RFDF_GET(ptr->PSR) == 1U); +} + +/** + * @brief Check whether Protocol Exception Events were occurred + * @param [in] ptr MCAN base + * @return true if Protocol Exception Events were occurred + */ +static inline bool mcan_is_protocol_exception_event_occurred(MCAN_Type *ptr) +{ + return (MCAN_PSR_PXE_GET(ptr->PSR) == 1U); +} + +/** + * @brief Get the Transmitter Delay Compensation Value + * @param [in] ptr MCAN base + * @return Transmitter Delay Compensation value + */ +static inline uint8_t mcan_get_transmitter_delay_compensation_value(MCAN_Type *ptr) +{ + return MCAN_PSR_TDCV_GET(ptr->PSR); +} + +/** + * @brief Get Interrupt Flags + * @param [in] ptr MCAN base + * @return Interrupt Flags + */ +static inline uint32_t mcan_get_interrupt_flags(MCAN_Type *ptr) +{ + return ptr->IR; +} + +/** + * @brief Clear Interrupt Flags + * @param [in] ptr MCAN base + * @param [in] mask Interrupt Mask + */ +static inline void mcan_clear_interrupt_flags(MCAN_Type *ptr, uint32_t mask) +{ + ptr->IR = mask; +} + +/** + * @brief Enable Interrupts + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_enable_interrupts(MCAN_Type *ptr, uint32_t mask) +{ + ptr->ILS &= ~mask; + ptr->IE |= mask; + ptr->ILE = 1U; +} + +/** + * @brief Enable TXBUF Interrupt + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_enable_txbuf_interrupt(MCAN_Type *ptr, uint32_t mask) +{ + ptr->TXBTIE |= mask; +} + +/** + * @brief Disable TXBUF Interrupt + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_disable_txbuf_interrupt(MCAN_Type *ptr, uint32_t mask) +{ + ptr->TXBTIE &= ~mask; +} + +/** + * @brief Disable Interrupts + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_disable_interrupts(MCAN_Type *ptr, uint32_t mask) +{ + ptr->IE &= ~mask; +} + +/** + * @brief Enable TXBUF Transmission interrupt + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_enable_txbuf_transmission_interrupt(MCAN_Type *ptr, uint32_t mask) +{ + ptr->TXBTIE |= mask; +} + +/** + * @brief Disable TXBUF Transmission interrupt + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_disable_txbuf_transmission_interrupt(MCAN_Type *ptr, uint32_t mask) +{ + ptr->TXBTIE &= ~mask; +} + +/** + * @brief Enable TXBUF Cancellation Finish interrupt + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_enable_txbuf_cancel_finish_interrupt(MCAN_Type *ptr, uint32_t mask) +{ + ptr->TXBCIE |= mask; +} + +/** + * @brief Disable TXBUF Cancellation Finish interrupt + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + */ +static inline void mcan_disable_txbuf_cancel_finish_interrupt(MCAN_Type *ptr, uint32_t mask) +{ + ptr->TXBCIE &= ~mask; +} + +/** + * @brief Select Interrupt Line + * @param [in] ptr MCAN base + * @param [in] mask Interrupt mask + * @param [in] line_index Interrupt Line Index + */ +static inline void mcan_interrupt_line_select(MCAN_Type *ptr, uint32_t mask, uint8_t line_index) +{ + if (line_index == 0) { + ptr->ILS &= ~mask; + } else { + ptr->ILS |= mask; + } + ptr->ILE = (1UL << line_index); +} + +/** + * @brief Check whether a TXFIFO/TXBUF transmission request is pending + * @param [in] ptr CAN Base + * @param [in] index TXBUF/TXFIFO Index + * @return True is the specified TXFIFO/TXBUF Transmission request is pending + */ +static inline bool mcan_is_transmit_request_pending(MCAN_Type *ptr, uint32_t index) +{ + return ((ptr->TXBRP & ((1UL << index))) != 0U); +} + +/** + * @brief Check whether TXFIFO is full + * @param [in] ptr MCAN base + * @return true if TXFIFO is full + */ +static inline bool mcan_is_txfifo_full(MCAN_Type *ptr) +{ + return ((ptr->TXFQS & MCAN_TXFQS_TFQF_MASK) != 0U); +} + +/** + * @brief Get the TXFIFO Put Index + * @param [in] ptr MCAN base + * @return The TX FIFO Put Index + */ +static inline uint32_t mcan_get_txfifo_put_index(MCAN_Type *ptr) +{ + return MCAN_TXFQS_TFQPI_GET(ptr->TXFQS); +} + +/** + * @brief Request A Transmission via specified TXBUF Index + * @param [in] ptr MCAN Base + * @param [in] index TXBUF index + */ +static inline void mcan_send_add_request(MCAN_Type *ptr, uint32_t index) +{ + ptr->TXBAR = (1UL << index); +} + +/** + * @brief Check whether the Transmission completed via specified TXBUF/TXFIFO + * @param [in] ptr MCAN base + * @param [in] index TXBUF Index + * @return True is the Transmission completed via specified TXBUF + */ +static inline bool mcan_is_transmit_occurred(MCAN_Type *ptr, uint32_t index) +{ + return ((ptr->TXBTO & (1UL << index)) != 0U); +} + +/** + * @brief Check Whether there are data available in specified RXBUF + * @param [in] ptr MCAN Base + * @param [in] index RXBUF index + * @return True if there are data available + */ +static inline bool mcan_is_rxbuf_data_available(MCAN_Type *ptr, uint32_t index) +{ + bool result; + if (index < 32U) { + result = (ptr->NDAT1 & (1UL << index)) != 0U; + } else if (index < 64U) { + result = (ptr->NDAT2 & (1UL << (index - 32U))) != 0U; + } else { + result = false; + } + return result; +} + +/** + * @brief Clear RXBUF Data available Flag for specified RXBUF + * @param [in] ptr MCAN base + * @param [in] index RXBUF index + */ +static inline void mcan_clear_rxbuf_data_available_flag(MCAN_Type *ptr, uint32_t index) +{ + if (index < 32U) { + ptr->NDAT1 = (1UL << index); + } else if (index < 64U) { + ptr->NDAT2 = (1UL << (index - 32U)); + } else { + /* Do nothing */ + } +} + +/** + * @brief Check whether specified Interrupt is set + * @param [in] ptr MCAN Base + * @param [in] mask Interrupt Flags + * @retval true if corresponding bits are set + */ +static inline bool mcan_is_interrupt_flag_set(MCAN_Type *ptr, uint32_t mask) +{ + return ((ptr->IR & mask) != 0U); +} + +static inline bool mcan_is_tsu_timestamp_available(MCAN_Type *ptr, uint32_t index) +{ + bool is_available = false; + if (index < ARRAY_SIZE(ptr->TS_SEL)) { + is_available = ((ptr->TSS1 & (1UL << index)) != 0U); + } + return is_available; +} + +/** + * @brief Read 32bit Timestamp value from TSU + * @param [in] ptr MCAN Base + * @param [in] index Timestamp pointer + * @return Timestamp value + */ +uint32_t mcan_read_32bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index); + +/** + * @brief Read 64bit Timestamp value from TSU + * @param [in] ptr MCAN Base + * @param [in] index Timestamp pointer + * @return Timestamp value + */ +uint64_t mcan_read_64bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index); + +/** + * @brief Get High Priority Message Status + * @param [in] ptr MCAN base + * @param [out] status Pointer to High Priority Message Status Buffer + */ +void mcan_get_high_priority_message_status(MCAN_Type *ptr, mcan_high_priority_message_status_t *status); + +/** + * @brief Get Default CAN configuration + * @param [in] ptr MCAN base + * @param [out] config CAN configuration + */ +void mcan_get_default_config(MCAN_Type *ptr, mcan_config_t *config); + +/** + * @brief Get message Size from Data Length Code + * @param [in] dlc Data Length Code + * @return Message Size in Bytes + */ +uint8_t mcan_get_message_size_from_dlc(uint8_t dlc); + +uint8_t mcan_get_data_field_size(uint8_t data_field_size_option); + +/** + * @brief Get Default Full MCAN RAM configuration + * If the device is configured as classic CAN node, the default CAN RAM settings are as below: + * - Standard Identifier Filter Elements: 32 + * - Extended Identifier Filter Elements: 32 + * - TXBUF Elements Info: + * - Element Count:32 + * - Dedicated TXBUF element count: 16 + * - TXFIFO/QQueue element count: 16 + * - Data Field Size: 8 + * - RXFIFO0 Elements Info: + * - Element Count :32 + * - Data Field Size: 8 + * - RXFIFO1 Elements Info: + * - Element Count : 32 + * - Data Field Size: 8 + * - RXBUF Element Info: + * - Element Count: 16 + * - Data Field Size : 8 + * - TX Event FIFO Element Count: 32 + * If the device is configured as CANFD node, the default CAN RAM settings are as below: + * - Standard Identifier Filter Elements: 16 + * - Extended Identifier Filter Elements: 16 + * - TXBUF Elements Info: + * - Element Count:8 + * - Dedicated TXBUF element count: 4 + * - TXFIFO/QQueue element count: 4 + * - Data Field Size: 64 + * - RXFIFO0 Elements Info: + * - Element Count : 8 + * - Data Field Size: 64 + * - RXFIFO1 Elements Info: + * - Element Count : 8 + * - Data Field Size: 64 + * - RXBUF Element Info: + * - Element Count: 4 + * - Data Field Size : 64 + * - TX Event FIFO Element Count: 8 + * + * @param [in] ptr MCAN base + * @param [out] ram_config CAN RAM Configuration + * @param [in] enable_canfd CANFD enable flag + */ +void mcan_get_defaul_ram_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *ram_config, bool enable_canfd); + +/** + * @brief Get Default MCAN RAM configuration + * If the device is configured as classic CAN node, the default CAN RAM settings are as below: + * - Standard Identifier Filter Elements: 32 + * - Extended Identifier Filter Elements: 32 + * - TXBUF Elements Info: + * - Element Count:32 + * - Dedicated TXBUF element count: 16 + * - TXFIFO/QQueue element count: 16 + * - Data Field Size: 8 + * - RXFIFO0 Elements Info: + * - Element Count :32 + * - Data Field Size: 8 + * - RXFIFO1 Elements Info: + * - Element Count : 32 + * - Data Field Size: 8 + * - RXBUF Element Info: + * - Element Count: 16 + * - Data Field Size : 8 + * - TX Event FIFO Element Count: 32 + * If the device is configured as CANFD node, the default CAN RAM settings are as below: + * - Standard Identifier Filter Elements: 16 + * - Extended Identifier Filter Elements: 16 + * - TXBUF Elements Info: + * - Element Count:8 + * - Dedicated TXBUF element count: 4 + * - TXFIFO/QQueue element count: 4 + * - Data Field Size: 64 + * - RXFIFO0 Elements Info: + * - Element Count : 8 + * - Data Field Size: 64 + * - RXFIFO1 Elements Info: + * - Element Count : 8 + * - Data Field Size: 64 + * - RXBUF Element Info: + * - Element Count: 4 + * - Data Field Size : 64 + * - TX Event FIFO Element Count: 8 + * + * @param [in] ptr MCAN base + * @param [out] ram_config CAN RAM Configuration + * @param [in] enable_canfd CANFD enable flag + */ +void mcan_get_default_ram_config(MCAN_Type *ptr, mcan_ram_config_t *simple_config, bool enable_canfd); + +/** + * @brief Initialize CAN controller + * @param [in] ptr MCAN base + * @param [in] config CAN configuration + * @param [in] src_clk_freq CAN clock frequency + * @retval status_success if operation is successful + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_freq); + +/** + * @brief Configure MCAN RAM will Full RAM configuration + * @param [in] ptr MCAN base + * @param [in] config MCAN RAM Full Configuration + * @return status_success if no errors reported + */ +hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *config); + +/** + * @brief Configure MCAN RAM will Simplified RAM configuration + * @param [in] ptr MCAN base + * @param [in] config MCAN RAM configuration + * @return status_success if no errors reported + */ +hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config); + +/** + * @brief Configure All CAN filters + * @param [in] ptr MCAN base + * @param [in] config All CAN Filter configuration + * @return status_success if no errors reported + */ +hpm_stat_t mcan_config_all_filters(MCAN_Type *ptr, mcan_all_filters_config_t *config); + +/** + * @brief Configure Transmitter Delay Compensation + * @param [in] ptr MCAN base + * @param [in] config Transmitter Delay compensation configure + * @return status_success if no errors reported + */ +hpm_stat_t mcan_config_transmitter_delay_compensation(MCAN_Type *ptr, mcan_tdc_config_t *config); + +/** + * @brief Configure Global Filter + * @param [in] ptr MCAN base + * @param [in] filter_config Global Filter Configuration + * @return status_success if no errors reported + */ +hpm_stat_t mcan_set_global_filter_config(MCAN_Type *ptr, mcan_global_filter_config_t *filter_config); + +/** + * @brief Set CAN filter element + * @param [in] ptr MCAN base + * @param [in] filter_elem CAN filter element + * @param [in] index CAN Filter element index + * @return status_success if no errors reported + */ +hpm_stat_t mcan_set_filter_element(MCAN_Type *ptr, const mcan_filter_elem_t *filter_elem, uint32_t index); + +/** + * @brief Write Frame to CAN TX Buffer + * @param [in] ptr MCAN base + * @param [in] index TX Buffer Index + * @param [in] tx_frame TX frame + * @return status_success if no errors reported + */ +hpm_stat_t mcan_write_txbuf(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame); + +/** + * @brief Write Frame CAN to TXFIFO + * @param [in] ptr MCAN base + * @param [in] tx_frame TX frame + * @return status_success if no errors reported + */ +hpm_stat_t mcan_write_txfifo(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame); + +/** + * @brief Read message from CAN RXBUF + * @param [in] ptr MCAN base + * @param [in] index Index of RXBUF + * @param [out] rx_frame Buffer to hold RX frame + * @return status_success if no errors reported + */ +hpm_stat_t mcan_read_rxbuf(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame); + +/** + * @brief Read message from CAN RXBUF + * @param [in] ptr MCAN base + * @param [in] fifo_index RXFIFO index, 0 - RXFO0, 1 - RXFIFO1 + * @param [out] rx_frame Buffer to hold RX frame + * @return status_success if no errors reported + */ +hpm_stat_t mcan_read_rxfifo(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame); + +/** + * @brief Read TX Event from CAN TX EVENT FIFO + * @param [in] ptr MCAN base + * @param [out] tx_evt TX Event Buffer + * @retval status_success if no errors happened + * @retval status_mcan_tx_evt_fifo_empty if there are no TX events available + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t mcan_read_tx_evt_fifo(MCAN_Type *ptr, mcan_tx_event_fifo_elem_t *tx_evt); + +/** + * @brief Transmit CAN message in blocking way + * @param [in] ptr MCAN base + * @param [in] tx_frame CAN Transmit Message buffer + * @return status_success if no errors reported + */ +hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame); + +/** + * @brief Transmit CAN message via TX in blocking way + * @param [in] ptr MCAN base + * @param [in] tx_frame CAN Transmit Message buffer + * @return status_success if no errors reported + */ +hpm_stat_t mcan_transmit_via_txbuf_nonblocking(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame); + +/** + * @brief Receive CAN Frame from RXBUF in blocking way + * @param [in] ptr MCAN base + * @param [in] index RXBUF index + * @param [out] rx_frame Buffer to hold Received Frame + * @return status_success if no errors reported + */ +hpm_stat_t mcan_receive_from_buf_blocking(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame); + +/** + * @brief Receive CAN Frame from RXFIFO in blocking way + * @param [in] ptr MCAN base + * @param [in] fifo_index RXFIFO index, 0 - RXFIFO0, 1 - RXFIFO1 + * @param [out] rx_frame Buffer to hold Received Frame + * @return status_success if no errors reported + */ +hpm_stat_t mcan_receive_from_fifo_blocking(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame); + +/** + * @brief Get Timstamp from MCAN TX Event + * @param [in] ptr MCAN base + * @param [in] tx_evt TX Event Element + * @param [out] timestamp Timestamp value + * @retval status_success if no errors happened + * @retval status_invalid_argument if any parameters are invalid + * @retval status_mcan_timestamp_not_exist if no timestamp information is available + */ +hpm_stat_t mcan_get_timestamp_from_tx_event(MCAN_Type *ptr, + const mcan_tx_event_fifo_elem_t *tx_evt, + mcan_timestamp_value_t *timestamp); + +/** + * @brief Get Timstamp from MCAN RX frame + * @param [in] ptr MCAN base + * @param [in] rx_msg Received message + * @param [out] timestamp Timestamp value + * @retval status_success if no errors happened + * @retval status_invalid_argument if any parameters are invalid + * @retval status_mcan_timestamp_not_exist if no timestamp information is available + */ +hpm_stat_t mcan_get_timestamp_from_received_message(MCAN_Type *ptr, + const mcan_rx_message_t *rx_msg, + mcan_timestamp_value_t *timestamp); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* HPM_MCAN_DRV_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h new file mode 100644 index 00000000..5a6f97db --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h @@ -0,0 +1,550 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLA_DRV_H +#define HPM_PLA_DRV_H + +#include "hpm_common.h" +#include "hpm_pla_regs.h" + +/** + * @brief PLA driver APIs + * @defgroup pla_interface PLA driver APIs + * @ingroup io_interfaces + * @{ + */ + +#define PLA_AOI_16TO8_SIGNAL_NUM (16U) +#define PLA_AOI_8TO7_SIGNAL_NUM (8U) +#define PLA_CHN_CFG_ACTIVE_WORD (0xF00DU) + +#define PLA_AOI_16TO8_CONNECT_(input, value) \ + PLA_CHN_AOI_16TO8_AOI_16TO8_##input##_SET(value) +/** + * @brief Input signal configuration for synthetic aoi_16to8 + * + */ +#define PLA_AOI_16TO8_CONNECT(input_signal, operation) \ + PLA_AOI_16TO8_CONNECT_(input_signal, operation) + +/** + * @brief aoi_16to8 operation on input signals + * + */ +typedef enum pla_aoi_signal_operation_type { + pla_aoi_operation_and_0 = 0, /**< signal & 0 */ + pla_aoi_operation_and_1 = 1, /**< signal & 1 */ + pla_aoi_operation_xor_1 = 2, /**< signal xor 1 */ + pla_aoi_operation_or_1 = 3, /**< signal | 1 */ +} pla_aoi_signal_operation_type_t; + +typedef enum pla_filter_sw_inject_type { + pla_filter_sw_inject_low = 0, + pla_filter_sw_inject_height = 1, + pla_filter_sw_inject_disable = 2, +} pla_filter_sw_inject_type_t; + +/** + * @brief aoi channel index + * + */ +typedef enum pla_channel_type { + pla_chn_0 = PLA_CHN_0, /**< channel 0 */ + pla_chn_1 = PLA_CHN_1, /**< channel 1 */ + pla_chn_2 = PLA_CHN_2, /**< channel 2 */ + pla_chn_3 = PLA_CHN_3, /**< channel 3 */ + pla_chn_4 = PLA_CHN_4, /**< channel 4 */ + pla_chn_5 = PLA_CHN_5, /**< channel 5 */ + pla_chn_6 = PLA_CHN_6, /**< channel 6 */ + pla_chn_7 = PLA_CHN_7, /**< channel 7 */ +} pla_channel_type_t; + +/** + * @brief Raw input signal for aoi16to8 module + * + */ +typedef enum pla_aoi_16to8_input_signal_type { + pla_1st_filter_out_0 = 0, + pla_1st_filter_out_1 = 1, + pla_1st_filter_out_2 = 2, + pla_1st_filter_out_3 = 3, + pla_1st_filter_out_4 = 4, + pla_1st_filter_out_5 = 5, + pla_1st_filter_out_6 = 6, + pla_1st_filter_out_7 = 7, + pla_1st_filter_out_8 = 8, + pla_1st_filter_out_9 = 9, + pla_1st_filter_out_10 = 10, + pla_1st_filter_out_11 = 11, + pla_1st_filter_out_12 = 12, + pla_1st_filter_out_13 = 13, + pla_1st_filter_out_14 = 14, + pla_1st_filter_out_15 = 15, +} pla_aoi_16to8_input_signal_type_t; + +/** + * @brief aoi_16to8 channel index + * + */ +typedef enum pla_aoi_16to8_channel_type { + pla_aoi_16to8_chn_0 = PLA_CHN_AOI_16TO8_AOI_16TO8_00, /**< channel 0 */ + pla_aoi_16to8_chn_1 = PLA_CHN_AOI_16TO8_AOI_16TO8_01, /**< channel 1 */ + pla_aoi_16to8_chn_2 = PLA_CHN_AOI_16TO8_AOI_16TO8_02, /**< channel 2 */ + pla_aoi_16to8_chn_3 = PLA_CHN_AOI_16TO8_AOI_16TO8_03, /**< channel 3 */ + pla_aoi_16to8_chn_4 = PLA_CHN_AOI_16TO8_AOI_16TO8_04, /**< channel 4 */ + pla_aoi_16to8_chn_5 = PLA_CHN_AOI_16TO8_AOI_16TO8_05, /**< channel 5 */ + pla_aoi_16to8_chn_6 = PLA_CHN_AOI_16TO8_AOI_16TO8_06, /**< channel 6 */ + pla_aoi_16to8_chn_7 = PLA_CHN_AOI_16TO8_AOI_16TO8_07, /**< channel 7 */ +} pla_aoi_16to8_channel_type_t; + +/** + * @brief + * + */ +typedef struct pla_aoi_16to8_cfg_unit { + pla_aoi_16to8_input_signal_type_t signal; + pla_aoi_signal_operation_type_t op; +} pla_aoi_16to8_cfg_unit_t; + +/** + * @brief + * + */ +typedef struct pla_aoi_16to8_chn_cfg { + pla_channel_type_t chn; /**< pla channel */ + pla_aoi_16to8_channel_type_t aoi_16to8_chn; /**< aoi_16to8 channel */ + pla_aoi_16to8_cfg_unit_t input[PLA_AOI_16TO8_SIGNAL_NUM]; /**< Configuration of each aoi_16to8 input signal */ +} pla_aoi_16to8_chn_cfg_t; + +/** + * @brief + * + */ +typedef enum pla_aoi_8to7_input_signal_type { + pla_2st_filter_out_0 = 0, + pla_2st_filter_out_1 = 1, + pla_2st_filter_out_2 = 2, + pla_2st_filter_out_3 = 3, + pla_2st_filter_out_4 = 4, + pla_2st_filter_out_5 = 5, + pla_2st_filter_out_6 = 6, + pla_2st_filter_out_7 = 7, +} pla_aoi_8to7_input_signal_type_t; + +/** + * @brief + * + */ +typedef enum pla_aoi_8to7_channel_type { + pla_aoi_8to7_chn_0 = 0, /**< channel 0 */ + pla_aoi_8to7_chn_1 = 1, /**< channel 1 */ + pla_aoi_8to7_chn_2 = 2, /**< channel 2 */ + pla_aoi_8to7_chn_3 = 3, /**< channel 3 */ + pla_aoi_8to7_chn_4 = 4, /**< channel 4 */ + pla_aoi_8to7_chn_5 = 5, /**< channel 5 */ + pla_aoi_8to7_chn_6 = 6, /**< channel 6 */ +} pla_aoi_8to7_channel_type_t; + + +/** + * @brief + * + */ +typedef struct pla_aoi_8to7_cfg_unit { + pla_aoi_8to7_input_signal_type_t signal; + pla_aoi_signal_operation_type_t op; +} pla_aoi_8to7_cfg_unit_t; + +/** + * @brief + * + */ +typedef struct pla_aoi_8to7_chn_cfg { + pla_channel_type_t chn; /**< pla channel */ + pla_aoi_8to7_channel_type_t aoi_8to7_chn; /**< aoi_16to8 channel */ + pla_aoi_8to7_cfg_unit_t input[PLA_AOI_8TO7_SIGNAL_NUM]; /**< Configuration of each aoi_16to8 input signal */ +} pla_aoi_8to7_chn_cfg_t; + +/** + * @brief + * + */ +typedef union pla_filter_cfg { + struct { + uint32_t sync_edge_filter_disable:1; + uint32_t software_inject:2; + uint32_t filter_reverse:1; + uint32_t edge_dect_en:1; + uint32_t nege_edge_dect_en:1; + uint32_t pose_edge_dect_en:1; + uint32_t filter_sync_level:1; + uint32_t filter_ext_en:1; + uint32_t reserved:3; + uint32_t filter_ext_type:3; + uint32_t filter_ext_counter:16; + }; + uint32_t val; +} pla_filter_cfg_t; + +typedef union pla_ff_cfg { + struct { + uint32_t sel_cfg_ff_type:3; + uint32_t sel_clk_source:1; + uint32_t sel_adder_minus:1; + uint32_t reserved:11; + uint32_t dis_osc_loop_clamp:1; + uint32_t osc_loop_clamp_value:1; + }; + uint32_t val; +} pla_ff_cfg_t; + +typedef enum pla_ff_type { + pla_ff_type_dff = 0, + pla_ff_type_3th_filter0 = 1, + pla_ff_type_dual_edge_DFF = 2, + pla_ff_type_trigger_ff = 3, + pla_ff_type_jk_ff = 4, + pla_ff_type_latch = 5, + pla_ff_type_adder_minus = 6 +} pla_ff_type_t; + + +typedef enum pla_filter1_inchannel_type { + pla_filter1_inchn0 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_0, + pla_filter1_inchn1 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_1, + pla_filter1_inchn2 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_2, + pla_filter1_inchn3 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_3, + pla_filter1_inchn4 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_4, + pla_filter1_inchn5 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_5, + pla_filter1_inchn6 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_6, + pla_filter1_inchn7 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_7, +} pla_filter1_inchannel_type_t; + +typedef enum pla_filter1_outchannel_type { + pla_filter1_outchn0 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_0, + pla_filter1_outchn1 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_1, + pla_filter1_outchn2 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_2, + pla_filter1_outchn3 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_3, + pla_filter1_outchn4 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_4, + pla_filter1_outchn5 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_5, + pla_filter1_outchn6 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_6, + pla_filter1_outchn7 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_7, +} pla_filter1_outchannel_type_t; + + +typedef enum pla_filter2_channel_type { + pla_filter2_chn0 = PLA_CHN_FILTER_2ND_SECOND_FILTER_0, + pla_filter2_chn1 = PLA_CHN_FILTER_2ND_SECOND_FILTER_1, + pla_filter2_chn2 = PLA_CHN_FILTER_2ND_SECOND_FILTER_2, + pla_filter2_chn3 = PLA_CHN_FILTER_2ND_SECOND_FILTER_3, + pla_filter2_chn4 = PLA_CHN_FILTER_2ND_SECOND_FILTER_4, + pla_filter2_chn5 = PLA_CHN_FILTER_2ND_SECOND_FILTER_5, + pla_filter2_chn6 = PLA_CHN_FILTER_2ND_SECOND_FILTER_6, + pla_filter2_chn7 = PLA_CHN_FILTER_2ND_SECOND_FILTER_7, +} pla_filter2_channel_type_t; + +typedef enum pla_filter3_channel_type { + pla_filter3_chn0 = PLA_CHN_FILTER_3RD_THIRD_FILTER_0, + pla_filter3_chn1 = PLA_CHN_FILTER_3RD_THIRD_FILTER_1, + pla_filter3_chn2 = PLA_CHN_FILTER_3RD_THIRD_FILTER_2, + pla_filter3_chn3 = PLA_CHN_FILTER_3RD_THIRD_FILTER_3, + pla_filter3_chn4 = PLA_CHN_FILTER_3RD_THIRD_FILTER_4, + pla_filter3_chn5 = PLA_CHN_FILTER_3RD_THIRD_FILTER_5, + pla_filter3_chn6 = PLA_CHN_FILTER_3RD_THIRD_FILTER_6, +} pla_filter3_channel_type_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Configure one channel of aoi_16to8 + * + * @param pla @ref PLA_Type + * @param cfg @ref pla_aoi_16to8_cfg_t + */ +void pla_set_aoi_16to8_one_channel(PLA_Type * pla, + pla_aoi_16to8_chn_cfg_t *cfg); + +/** + * @brief Get one channel of aoi_16to8 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param aoi_16to8_chn @ref pla_aoi_16to8_channel_type_t + * @param cfg @ref pla_aoi_16to8_chn_cfg_t + */ +void pla_get_aoi_16to8_one_channel(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_16to8_channel_type_t aoi_16to8_chn, + pla_aoi_16to8_chn_cfg_t *cfg); + +/** + * @brief Set one signal of aoi_16to8 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param aoi_16to8_chn @ref pla_aoi_16to8_channel_type_t + * @param cfg @ref pla_aoi_16to8_cfg_unit_t + */ +static inline void pla_set_aoi_16to8_input_signal(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_16to8_channel_type_t aoi_16to8_chn, + pla_aoi_16to8_cfg_unit_t *cfg) +{ + pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] = pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] & + ~(((uint32_t)cfg->op) << (cfg->signal << 1)); +} + +/** + * @brief Get one signal of aoi_16to8 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param aoi_16to8_chn @ref pla_aoi_16to8_channel_type_t + * @param signal @ref pla_aoi_16to8_input_signal_type_t + * @param cfg @ref pla_aoi_16to8_cfg_unit_t + */ +static inline void pla_get_aoi_16to8_input_signal(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_16to8_channel_type_t aoi_16to8_chn, + pla_aoi_16to8_input_signal_type_t signal, + pla_aoi_16to8_cfg_unit_t *cfg) +{ + cfg->op = (pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] >> (signal << 1)) & 0x03; + cfg->signal = signal; +} + + +/** + * @brief Configure one channel of aoi_8to7 + * + * @param pla @ref PLA_Type + * @param cfg @ref pla_aoi_8to7_chn_cfg_t + */ +void pla_set_aoi_8to7_one_channel(PLA_Type *pla, + pla_aoi_8to7_chn_cfg_t *cfg); + +/** + * @brief Get one channel of aoi_8to7 + * + * @param pla @ref PLA_Type + * @param cfg @ref pla_aoi_8to7_chn_cfg_t + */ +void pla_get_aoi_8to7_one_channel(PLA_Type *pla, + pla_aoi_8to7_chn_cfg_t *cfg); + +/** + * @brief Configure one signal of aoi_8to7 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param aoi_16to8_chn @ref pla_aoi_8to7_channel_type_t + * @param cfg @ref pla_aoi_8to7_cfg_unit_t + */ +void pla_set_aoi_8to7_input_signal(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_8to7_channel_type_t aoi_8to7_chn, + pla_aoi_8to7_cfg_unit_t *cfg); + +/** + * @brief Get one signal of aoi_8to7 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param aoi_8to7_chn @ref pla_aoi_8to7_channel_type_t + * @param signal @ref pla_aoi_8to7_input_signal_type_t + * @param cfg @ref pla_aoi_8to7_cfg_unit_t + */ +void pla_get_aoi_8to7_input_signal(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_8to7_channel_type_t aoi_8to7_chn, + pla_aoi_8to7_input_signal_type_t signal, + pla_aoi_8to7_cfg_unit_t *cfg); + +/** + * @brief Configure filter1 out + * + * @param pla @ref PLA_Type + * @param filter1_out_chn @ref pla_filter1_outchannel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_set_filter1_out(PLA_Type *pla, + pla_filter1_outchannel_type_t filter1_out_chn, + pla_filter_cfg_t *cfg) +{ + pla->FILTER_1ST_PLA_OUT[filter1_out_chn] = cfg->val; +} + +/** + * @brief Get filter1 out + * + * @param pla @ref PLA_Type + * @param filter1_out_chn @ref pla_filter1_outchannel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_get_filter1_out(PLA_Type *pla, + pla_filter1_outchannel_type_t filter1_out_chn, + pla_filter_cfg_t *cfg) +{ + cfg->val = pla->FILTER_1ST_PLA_OUT[filter1_out_chn]; +} + +/** + * @brief Configure filter1 in + * + * @param pla @ref PLA_Type + * @param filter1_in_chn @ref pla_filter1_inchannel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_set_filter1_in(PLA_Type *pla, + pla_filter1_inchannel_type_t filter1_in_chn, + pla_filter_cfg_t *cfg) +{ + pla->FILTER_1ST_PLA_IN[filter1_in_chn] = cfg->val; +} + +/** + * @brief Get filter 1 + * + * @param pla @ref PLA_Type + * @param filter1_in_chn @ref pla_filter1_inchannel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_get_filter1_in(PLA_Type *pla, + pla_filter1_inchannel_type_t filter1_in_chn, + pla_filter_cfg_t *cfg) +{ + cfg->val = pla->FILTER_1ST_PLA_IN[filter1_in_chn]; +} + +/** + * @brief Configure filter 2 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param filter2_chn @ref pla_filter2_channel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_set_filter2(PLA_Type *pla, + pla_channel_type_t chn, + pla_filter2_channel_type_t filter2_chn, + pla_filter_cfg_t *cfg) +{ + pla->CHN[chn].FILTER_2ND[filter2_chn] = cfg->val; +} + +/** + * @brief Get filter2 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param filter2_chn @ref pla_filter2_channel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_get_filter2(PLA_Type *pla, + pla_channel_type_t chn, + pla_filter2_channel_type_t filter2_chn, + pla_filter_cfg_t *cfg) +{ + cfg->val = pla->CHN[chn].FILTER_2ND[filter2_chn]; +} + +/** + * @brief Configure filter3 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param filter3_chn @ref pla_filter3_channel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_set_filter3(PLA_Type *pla, + pla_channel_type_t chn, + pla_filter3_channel_type_t filter3_chn, + pla_filter_cfg_t *cfg) +{ + pla->CHN[chn].FILTER_3RD[filter3_chn] = cfg->val; +} + +/** + * @brief Get filter3 + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param filter3_chn @ref pla_filter3_channel_type_t + * @param cfg @ref pla_filter_cfg_t + */ +static inline void pla_get_filter3(PLA_Type *pla, + pla_channel_type_t chn, + pla_filter3_channel_type_t filter3_chn, + pla_filter_cfg_t *cfg) +{ + cfg->val = pla->CHN[chn].FILTER_3RD[filter3_chn]; +} + +/** + * @brief Set ff function + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param cfg @ref pla_ff_cfg_t + */ +static inline void pla_set_ff(PLA_Type *pla, + pla_channel_type_t chn, + pla_ff_cfg_t *cfg) +{ + pla->CHN[chn].CFG_FF = cfg->val; +} + +/** + * @brief Get ff function + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + * @param cfg @ref pla_ff_cfg_t + */ +static inline void pla_get_ff(PLA_Type *pla, + pla_channel_type_t chn, + pla_ff_cfg_t *cfg) +{ + cfg->val = pla->CHN[chn].CFG_FF; +} + +/** + * @brief enable pla channel + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + */ +static inline void pla_channel_enable(PLA_Type *pla, + pla_channel_type_t chn) +{ + pla->CHN_CFG_ACTIVE[chn] = PLA_CHN_CFG_ACTIVE_WORD; +} + +/** + * @brief disable pla channel + * + * @param pla @ref PLA_Type + * @param chn @ref pla_channel_type_t + */ +static inline void pla_channel_disable(PLA_Type *pla, + pla_channel_type_t chn) +{ + pla->CHN_CFG_ACTIVE[chn] = false; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_PLA_DRV_H */ + diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h index b9ec9965..deb49952 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h @@ -62,7 +62,7 @@ typedef enum pwm_register_update { } pwm_shadow_register_update_trigger_t; /** - * @brief configure the state of channel 0∼7 outputs when the forced output is in effect + * @brief configure the state of channel 0-7 outputs when the forced output is in effect * */ typedef enum pwm_fault_mode { @@ -132,11 +132,17 @@ typedef enum pwm_output_type { typedef struct pwm_cmp_config { uint32_t cmp; /**< compare value */ bool enable_ex_cmp; /**< enable extended compare value */ +#if PWM_SOC_HRPWM_SUPPORT + bool enable_hrcmp; /**< enable high precision pwm */ +#endif uint8_t mode; /**< compare work mode: pwm_cmp_mode_output_compare or pwm_cmp_mode_input_capture */ uint8_t update_trigger; /**< compare configuration update trigger */ uint8_t ex_cmp; /**< extended compare value */ uint8_t half_clock_cmp; /**< half clock compare value*/ uint8_t jitter_cmp; /**< jitter compare value */ +#if PWM_SOC_HRPWM_SUPPORT + uint8_t hrcmp; /**< high precision pwm */ +#endif } pwm_cmp_config_t; /** @@ -238,6 +244,22 @@ static inline void pwm_set_start_count(PWM_Type *pwm_x, | PWM_STA_STA_SET(start); } +#if PWM_SOC_HRPWM_SUPPORT + +/** + * @brief set hrpwm counter start value + * + * @param pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param start pwm timer counter start value + */ +static inline void pwm_set_hrpwm_start_count(PWM_Type *pwm_x, + uint32_t start) +{ + pwm_x->STA_HRPWM = PWM_STA_HRPWM_STA_SET(start); +} + +#endif + /** * @brief set the reload value * @@ -254,6 +276,26 @@ static inline void pwm_set_reload(PWM_Type *pwm_x, | PWM_RLD_RLD_SET(reload); } +#if PWM_SOC_HRPWM_SUPPORT + +/** + * @brief set the hr pwm reload value + * + * @param pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param hr_reload pwm timer counter hrpwm reload value + * @param reload pwm timer counter reload value + */ +static inline void pwm_set_hrpwm_reload(PWM_Type *pwm_x, + uint16_t hrpwm_reload, + uint32_t reload) +{ + pwm_shadow_register_unlock(pwm_x); + pwm_x->RLD_HRPWM = PWM_RLD_HRPWM_RLD_HR_SET(hrpwm_reload) + | PWM_RLD_HRPWM_RLD_SET(reload); +} + +#endif + /** * @brief clear pwm status register * @@ -270,6 +312,20 @@ static inline void pwm_clear_status(PWM_Type *pwm_x, uint32_t mask) pwm_x->SR |= mask; } +#if PWM_SOC_TIMER_RESET_SUPPORT + +/** + * @brief Reset timer and extension timer + * + * @param pwm_x PWM base address, HPM_PWMx(x=0..n) + */ +static inline void pwm_timer_reset(PWM_Type *pwm_x) +{ + pwm_x->GCR = ((pwm_x->GCR & ~(PWM_GCR_TIMERRESET_MASK)) | PWM_GCR_TIMERRESET_SET(1)); +} + +#endif + /** * @brief get pwm status register * @@ -388,23 +444,56 @@ static inline void pwm_set_load_counter_shadow_register_trigger(PWM_Type *pwm_x, } /** - * @brief configure the cmp shadow on capture mode + * @brief Configure input capture cmp to trigger shadow register updates * * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - * @param[in] edge which edge is used as shadow register hardware load event + * @param[in] is_falling_edge which edge is used as shadow register hardware load event * @arg 1- falling edge * @arg 0- rising edge */ static inline void pwm_load_cmp_shadow_on_capture(PWM_Type *pwm_x, uint8_t index, - bool edge) + bool is_falling_edge) { pwm_x->CMPCFG[index] |= PWM_CMPCFG_CMPMODE_MASK; - pwm_x->GCR = ((pwm_x->GCR & ~(PWM_GCR_HWSHDWEDG_MASK)) - | PWM_GCR_HWSHDWEDG_SET(edge)); + pwm_x->GCR = ((pwm_x->GCR & ~(PWM_GCR_CMPSHDWSEL_MASK | PWM_GCR_HWSHDWEDG_MASK)) + | PWM_GCR_CMPSHDWSEL_SET(index) + | PWM_GCR_HWSHDWEDG_SET(is_falling_edge)); +} + +#if PWM_SOC_SHADOW_TRIG_SUPPORT +/** + * @brief Set the timer shadow register to update the trigger edge + * + * @param[in] pwm_x pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] is_falling_edge which edge is used as shadow register hardware load event + * @arg 1- falling edge + * @arg 0- rising edge + */ +static inline void pwm_set_cnt_shadow_trig_edge(PWM_Type *pwm_x, + bool is_falling_edge) +{ + pwm_x->SHCR = ((pwm_x->SHCR & ~PWM_SHCR_CNT_UPDATE_EDGE_MASK) + | PWM_SHCR_CNT_UPDATE_EDGE_SET(is_falling_edge)); +} + +/** + * @brief Set the force output shadow register to update the trigger edge + * + * @param[in] pwm_x pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] is_falling_edge which edge is used as shadow register hardware load event + * @arg 1- falling edge + * @arg 0- rising edge + */ +static inline void pwm_set_force_shadow_trig_edge(PWM_Type *pwm_x, + bool is_falling_edge) +{ + pwm_x->SHCR = ((pwm_x->SHCR & ~PWM_SHCR_FORCE_UPDATE_EDGE_MASK) + | PWM_SHCR_FORCE_UPDATE_EDGE_SET(is_falling_edge)); } +#endif /** * @brief disable pwn cmp half clock * @@ -454,6 +543,23 @@ static inline void pwm_cmp_update_cmp_value(PWM_Type *pwm_x, uint8_t index, | PWM_CMP_CMP_SET(cmp) | PWM_CMP_XCMP_SET(ex_cmp); } +#if PWM_SOC_HRPWM_SUPPORT +/** + * @brief update high-precision cmp value + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) + * @param[in] cmp clock counter compare value + * @param[in] hrcmp high-precision pwm + */ +static inline void pwm_cmp_update_hrcmp_value(PWM_Type *pwm_x, uint8_t index, + uint32_t cmp, uint16_t hrcmp) +{ + pwm_x->CMP_HRPWM[index] = (pwm_x->CMP_HRPWM[index] & ~(PWM_CMP_HRPWM_CMP_MASK | PWM_CMP_HRPWM_CMP_HR_MASK)) + | PWM_CMP_HRPWM_CMP_SET(cmp) | PWM_CMP_HRPWM_CMP_HR_SET(hrcmp); +} +#endif + /** * @brief Forced update of pwm cmp register value, cmp content guaranteed accurate by user * @@ -477,12 +583,22 @@ static inline void pwm_config_cmp(PWM_Type *pwm_x, uint8_t index, pwm_cmp_config { pwm_shadow_register_unlock(pwm_x); if (config->mode == pwm_cmp_mode_output_compare) { - pwm_x->CMPCFG[index] = PWM_CMPCFG_XCNTCMPEN_SET(config->enable_ex_cmp) +#if PWM_SOC_HRPWM_SUPPORT + if (config->enable_hrcmp) { + pwm_x->CMPCFG[index] = PWM_CMPCFG_CMPSHDWUPT_SET(config->update_trigger); + pwm_x->CMP[index] = PWM_CMP_HRPWM_CMP_SET(config->cmp) + | PWM_CMP_HRPWM_CMP_HR_SET(config->hrcmp); + } else { +#endif + pwm_x->CMPCFG[index] = PWM_CMPCFG_XCNTCMPEN_SET(config->enable_ex_cmp) | PWM_CMPCFG_CMPSHDWUPT_SET(config->update_trigger); - pwm_x->CMP[index] = PWM_CMP_CMP_SET(config->cmp) + pwm_x->CMP[index] = PWM_CMP_CMP_SET(config->cmp) | PWM_CMP_XCMP_SET(config->ex_cmp) | PWM_CMP_CMPHLF_SET(config->half_clock_cmp) | PWM_CMP_CMPJIT_SET(config->jitter_cmp); +#if PWM_SOC_HRPWM_SUPPORT + } +#endif } else { pwm_x->CMPCFG[index] |= PWM_CMPCFG_CMPMODE_MASK; } @@ -790,6 +906,100 @@ hpm_stat_t pwm_update_raw_cmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, */ hpm_stat_t pwm_update_raw_cmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2); +#if PWM_SOC_HRPWM_SUPPORT +/** + * @brief Enable high-precision pwm + * + * @param[in] pwm_x @ref PWM_Type PWM base address + */ +static inline void pwm_enable_hrpwm(PWM_Type *pwm_x) +{ + pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_HR_PWM_EN_MASK)) | PWM_GCR_HR_PWM_EN_SET(1); +} + +/** + * @brief Disable high-precision pwm + * + * @param[in] pwm_x @ref PWM_Type PWM base address + */ +static inline void pwm_disable_hrpwm(PWM_Type *pwm_x) +{ + pwm_x->GCR = pwm_x->GCR & ~(PWM_GCR_HR_PWM_EN_MASK); +} + +/** + * @brief Calibrate all channels of hrpwm + * + * @param[in] pwm_x @ref PWM_Type PWM base address + */ +static inline void pwm_cal_hrpwm_start(PWM_Type *pwm_x) +{ + pwm_x->HRPWM_CFG |= PWM_HRPWM_CFG_CAL_START_MASK; +} + +/** + * @brief Calibrate specified hrpwm channels + * + * @param[in] pwm_x @ref PWM_Type PWM base address + * @param[in] chn Channel number + */ +static inline void pwm_cal_hrpwm_chn_start(PWM_Type *pwm_x, uint8_t chn) +{ + pwm_x->HRPWM_CFG |= PWM_HRPWM_CFG_CAL_START_SET(chn); +} + +/** + * @brief Wait for the completion of calibration of the specified channel of high-precision PWM, blocking + * + * @param[in] pwm_x @ref PWM_Type PWM base address + * @param[in] chn Channel number + */ +static inline void pwm_cal_hrpwm_chn_wait(PWM_Type *pwm_x, uint8_t chn) +{ + while (PWM_ANASTS_CALON_GET(pwm_x->ANASTS[chn])) { + }; +} + +/** + * @brief get calibration status + * + * @param[in] pwm_x pwm_x @ref PWM_Type PWM base address + * @param[in] chn Channel number + * @return uint32_t finished will be set zero. + */ +static inline uint32_t pwm_get_cal_hrpwm_status(PWM_Type *pwm_x, uint8_t chn) +{ + return PWM_ANASTS_CALON_GET(pwm_x->ANASTS[chn]); +} + +/** + * @brief update raw high-precision compare value for edge aligned waveform + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] cmp_index index of cmp to be adjusted (0..(PWM_SOC_PWM_MAX_COUNT-1)) + * @param[in] target_cmp target compare value + * @param[in] target_hrcmp target high-precision compare value + * @return hpm_stat_t + */ +hpm_stat_t pwm_update_raw_hrcmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, uint32_t target_cmp, + uint16_t target_hrcmp); + +/** + * @brief update raw high-precision compare value for central aligned waveform + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param[in] cmp1_index index of cmp1 to be adjusted (cmp1_index must be even number) + * @param[in] cmp2_index index of cmp2 to be adjusted (cmp2_index must be odd number) + * @param[in] target_cmp1 target compare value for cmp1 + * @param[in] target_cmp2 target compare value for cmp2 + * @param[in] target_hrcmp1 target high-precision compare value for cmp1 + * @param[in] target_hrcmp2 target high-precision compare value for cmp2 + * @return hpm_stat_t + */ +hpm_stat_t pwm_update_raw_hrcmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, + uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2, + uint16_t target_hrcmp1, uint16_t target_hrcmp2); +#endif #ifdef __cplusplus } diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h index 6401b1b9..6b52d498 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h @@ -62,6 +62,17 @@ typedef enum qei_work_mode { qei_work_mode_ud = 2, /**< Up and Down (UD) mode */ } qei_work_mode_t; +/** + * @brief speed history type + * + */ +typedef enum qei_speed_his_type { + qei_speed_his0 = QEI_SPDHIS_SPDHIS0, /**< Speed history0 */ + qei_speed_his1 = QEI_SPDHIS_SPDHIS1, /**< Speed history1 */ + qei_speed_his2 = QEI_SPDHIS_SPDHIS2, /**< Speed history2 */ + qei_speed_his3 = QEI_SPDHIS_SPDHIS3, /**< Speed history3 */ +} qei_speed_his_type_t; + #ifdef __cplusplus extern "C" { #endif @@ -393,16 +404,12 @@ static inline uint32_t qei_get_count_on_snap1_event(QEI_Type *qei_x, * @brief get speed history * * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] hist_index @ref QEI_SPDHIS_SPDHIS1 ,QEI_SPDHIS_SPDHISx(x=0...n) + * @param[in] hist_index @ref qei_speed_his_type_t * @retval speed history value - * @arg 0 - hist_index out of range * @arg counter value */ -static inline uint32_t qei_get_speed_history(QEI_Type *qei_x, uint8_t hist_index) +static inline uint32_t qei_get_speed_history(QEI_Type *qei_x, qei_speed_his_type_t hist_index) { - if (hist_index > QEI_SPDHIS_SPDHIS3) { - return 0; - } return QEI_SPDHIS_SPDHIS0_GET(qei_x->SPDHIS[hist_index]); } diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h index 61f33ae2..a959fef1 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,6 +33,7 @@ typedef struct { */ #define RTC_ALARM_TYPE_ONE_SHOT (0U) /**< The RTC alarm will be triggered only once */ #define RTC_ALARM_TYPE_PERIODIC (1U) /**< The RTC alarm will be triggered periodically */ +#define RTC_ALARM_TYPE_ABSOLUTE_TIME_ONE_SHOT (2U) /**< The RTC alarm will be triggered via the absolute time provided via period */ /** * @brief Typical RTC alarm period definitions diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_sdk_version.h b/common/libraries/hpm_sdk/drivers/inc/hpm_sdk_version.h deleted file mode 100644 index ba729f89..00000000 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_sdk_version.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SDK_VERSION_H -#define HPM_SDK_VERSION_H - -/* #undef SDK_VERSION_CODE */ -#define SDK_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) - -#define SDKVERSION 0x1000000 -#define SDK_VERSION_NUMBER 0x10000 -#define SDK_VERSION_MAJOR 1 -#define SDK_VERSION_MINOR 0 -#define SDK_PATCHLEVEL 0 -#define SDK_VERSION_STRING "1.0.0" - -#define BUILD_VERSION - - -#endif /* HPM_SDK_VERSION_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h new file mode 100644 index 00000000..1c166bb4 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h @@ -0,0 +1,468 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SDM_DRV_H +#define HPM_SDM_DRV_H + +#include "hpm_common.h" +#include "hpm_sdm_regs.h" + +/* defined channel mask macro */ +#define SAMPLING_MODE_MASK (0x7U) +#define CHN_SAMPLING_MODE_SHIFT(ch) ((ch) * 3U + SDM_CTRL_CHMD_SHIFT) +#define CHN_SAMPLING_MODE_MASK(ch) (SAMPLING_MODE_MASK << CHN_SAMPLING_MODE_SHIFT(ch)) + +#define CH0_EN_MASK (0x1U << SDM_CTRL_CH_EN_SHIFT) +#define CHN_EN_MASK(ch) (CH0_EN_MASK << (ch)) + +#define CHN_ERR_MASK(ch) (SDM_INT_EN_CH0ERR_MASK << (ch)) +#define CHN_DRY_MASK(ch) (SDM_INT_EN_CH0DRY_MASK << (ch)) + +typedef enum { + sdm_sampling_rising_clk_edge = 0, + sdm_sampling_every_clk_edge = 1, + sdm_sampling_manchester_mode = 2, + sdm_sampling_falling_clk_edge = 3, + sdm_sampling_rising_two_clk_edge = 4, + sdm_sampling_falling_two_clk_edge = 5 +} sdm_sampling_mode_t; + +typedef enum { + sdm_filter_sinc1 = 0, + sdm_filter_sinc2 = 1, + sdm_filter_sinc3 = 2, + sdm_filter_fast_sinc2 = 3 +} sdm_filter_type_t; + +typedef struct { + bool clk_signal_sync; + bool data_signal_sync; + bool interrupt_en; +} sdm_control_t; + +typedef struct { + uint8_t sampling_mode; + bool enable_err_interrupt; + bool enable_data_ready_interrupt; +} sdm_channel_common_config_t; + +typedef struct { + uint16_t high_threshold; + uint16_t zero_cross_threshold; + uint16_t low_threshold; + + bool en_zero_cross_threshold_int; + bool en_clock_invalid_int; + bool en_high_threshold_int; + bool en_low_threshold_int; + uint8_t filter_type; /**< sdm_filter_type_t */ + uint8_t oversampling_rate; /**< 1 - 32 */ + uint8_t ignore_invalid_samples; + bool enable; +} sdm_comparator_config_t; + +typedef struct { + uint8_t fifo_threshold; + bool en_fifo_threshold_int; + uint8_t manchester_threshold :8; + uint8_t wdg_threshold :8; + uint8_t en_af_int :1; + uint8_t en_data_overflow_int :1; + uint8_t en_cic_data_saturation_int :1; + uint8_t en_data_ready_int :1; + uint8_t sync_source :6; + uint8_t fifo_clean_on_sync :1; /**< fifo clean by hardware when fifo interrupt occurred */ + uint8_t wtsynaclr :1; + uint8_t wtsynmclr :1; + uint8_t wtsyncen :1; + uint8_t output_32bit :1; + uint8_t data_ready_flag_by_fifo :1; + uint8_t enable :1; + + uint8_t filter_type; /**< sdm_filter_type_t */ + bool pwm_signal_sync; + uint8_t output_offset; /**< 16bit mode need configure this */ + uint16_t oversampling_rate; /**< 1-256 */ + uint8_t ignore_invalid_samples; +} sdm_filter_config_t; + +typedef struct { + uint32_t count; + uint8_t *buff; + uint8_t data_len_in_bytes; /* 16bit-2 32bit-4 */ + bool using_fifo; +} sdm_output_config_t; + +typedef enum { + sdm_comparator_no_event = 0, + sdm_comparator_event_out_high_threshold = SDM_CH_SCST_CMPH_MASK, + sdm_comparator_event_out_low_threshold = SDM_CH_SCST_CMPL_MASK, + sdm_comparator_event_hz = SDM_CH_SCST_HZ_MASK, + sdm_comparator_event_invalid_clk = SDM_CH_SCST_MF_MASK +} sdm_comparator_event_t; + +typedef enum { + sdm_chn0_error_mask = SDM_INT_EN_CH0ERR_MASK, + sdm_chn1_error_mask = SDM_INT_EN_CH1ERR_MASK, + sdm_chn2_error_mask = SDM_INT_EN_CH2ERR_MASK, + sdm_chn3_error_mask = SDM_INT_EN_CH3ERR_MASK, + sdm_chn0_data_ready_mask = SDM_INT_EN_CH0DRY_MASK, + sdm_chn1_data_ready_mask = SDM_INT_EN_CH1DRY_MASK, + sdm_chn2_data_ready_mask = SDM_INT_EN_CH2DRY_MASK, + sdm_chn3_data_ready_mask = SDM_INT_EN_CH3DRY_MASK +} sdm_channel_int_status_mask_t; + +typedef enum { + sdm_chn0_enable_mask = 1U << SDM_CTRL_CH_EN_SHIFT, + sdm_chn1_enable_mask = 1U << (SDM_CTRL_CH_EN_SHIFT + 1U), + sdm_chn2_enable_mask = 1U << (SDM_CTRL_CH_EN_SHIFT + 2U), + sdm_chn3_enable_mask = 1U << (SDM_CTRL_CH_EN_SHIFT + 3U) +} sdm_channel_enable_mask_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief sdm enable module interrupt + * + * @param ptr SDM base address + * @param enable true for enable, false for disable + */ +static inline void sdm_enable_module_interrupt(SDM_Type *ptr, bool enable) +{ + if (enable) { + ptr->CTRL |= SDM_CTRL_IE_MASK; + } else { + ptr->CTRL &= ~SDM_CTRL_IE_MASK; + } +} + +/** + * @brief sdm enable channel + * + * @param ptr SDM base address + * @param ch_index channel index + * @param enable true for enable, false for disable + */ +static inline void sdm_enable_channel(SDM_Type *ptr, uint8_t ch_index, bool enable) +{ + if (enable) { + ptr->CTRL |= CHN_EN_MASK(ch_index); + } else { + ptr->CTRL &= ~CHN_EN_MASK(ch_index); + } +} + +/** + * @brief sdm enable channel by mask + * + * @note ch_mask supports bitwise or operation, this API could enable multiple channels at the same time + * + * @param ptr SDM base address + * @param ch_mask sdm_channel_enable_mask_t + */ +static inline void sdm_enable_channel_by_mask(SDM_Type *ptr, uint32_t ch_mask) +{ + ptr->CTRL = (ptr->CTRL & (~SDM_CTRL_CH_EN_MASK)) | ch_mask; +} + +/** + * @brief sdm set channel sampling mode + * + * @param ptr SDM base address + * @param ch_index channel index + * @param mode sdm_sampling_mode_t + */ +static inline void sdm_set_channel_sampling_mode(SDM_Type *ptr, uint8_t ch_index, sdm_sampling_mode_t mode) +{ + ptr->CTRL &= ~CHN_SAMPLING_MODE_MASK(ch_index); + ptr->CTRL |= mode << (SDM_CTRL_CHMD_SHIFT + ch_index); +} + +/** + * @brief sdm enable channel interrupt + * + * @param ptr SDM base address + * @param mask sdm_channel_int_status_mask_t, support bitwise or operation + */ +static inline void sdm_enable_channel_interrupt(SDM_Type *ptr, uint32_t mask) +{ + ptr->INT_EN |= mask; +} + +/** + * @brief sdm get status register value + * + * @param ptr SDM base address + * @return uint32_t sdm status register value + */ +static inline uint32_t sdm_get_status(SDM_Type *ptr) +{ + return ptr->STATUS; +} + +/** + * @brief get channel data ready status + * + * @param ptr SDM base address + * @param ch channel + * @return true data ready + * @return false not ready + */ +static inline bool sdm_get_channel_data_ready_status(SDM_Type *ptr, uint8_t ch) +{ + return (((ptr->STATUS) & CHN_DRY_MASK(ch)) == CHN_DRY_MASK(ch)); +} + +/** + * @brief get channel error status + * + * @param ptr SDM base address + * @param ch channel + * @return true error occur + * @return false no error + */ +static inline bool sdm_get_channel_data_error_status(SDM_Type *ptr, uint8_t ch) +{ + return (((ptr->STATUS) & CHN_ERR_MASK(ch)) == CHN_ERR_MASK(ch)); +} + +/** + * @brief sdm set channel's fifo threshold + * + * @param ptr SDM base address + * @param ch channel index + * @param threshold threshold value + */ +static inline void sdm_set_ch_fifo_threshold(SDM_Type *ptr, uint8_t ch, uint8_t threshold) +{ + ptr->CH[ch].SDFIFOCTRL = SDM_CH_SDFIFOCTRL_THRSH_SET(threshold); +} + +/** + * @brief sdm get channel fifo threshold + * + * @param ptr SDM base address + * @param ch channel index + * @return uint8_t fifo threshold value + */ +static inline uint8_t sdm_get_ch_fifo_threshold(SDM_Type *ptr, uint8_t ch) +{ + return (uint8_t)(SDM_CH_SDFIFOCTRL_THRSH_GET(ptr->CH[ch].SDFIFOCTRL)); +} + +/** + * @brief sdm get channel filter status + * + * @param ptr SDM base address + * @param ch channel index + * @return uint32_t channel filter status register value + */ +static inline uint32_t sdm_get_channel_filter_status(SDM_Type *ptr, uint8_t ch) +{ + return ptr->CH[ch].SDST; +} + +/** + * @brief sdm get channel data count in fifo + * + * @param ptr SDM base address + * @param ch channel index + * @return uint8_t data count + */ +static inline uint8_t sdm_get_channel_fifo_data_count(SDM_Type *ptr, uint8_t ch) +{ + return (uint8_t)(SDM_CH_SDST_FILL_GET(ptr->CH[ch].SDST)); +} + +/** + * @brief sdm get channel filter output data in fifo + * + * @param ptr SDM base address + * @param ch channel index + * @return int32_t data + */ +static inline int32_t sdm_get_channel_fifo_data(SDM_Type *ptr, uint8_t ch) +{ + return ptr->CH[ch].SDFIFO; +} + +/** + * @brief sdm get channel input clock cycle count + * + * @param ptr SDM base address + * @param ch channel index + * @return uint8_t clock cycle count + */ +static inline uint8_t sdm_get_channel_clock_cycle_count(SDM_Type *ptr, uint8_t ch) +{ + return (uint8_t)(SDM_CH_SDST_PERIOD_MCLK_GET(ptr->CH[ch].SDST)); +} + +/** + * @brief sdm get channel comparator data + * + * @param ptr SDM base address + * @param ch channel index + * @return uint16_t comparator data + */ +static inline uint16_t sdm_get_channel_comparator_data(SDM_Type *ptr, uint8_t ch) +{ + return (uint16_t)(ptr->CH[ch].SCAMP); +} + +/** + * @brief sdm set channel comparator high threshold + * + * @param ptr SDM base address + * @param ch channel index + * @param value high threshold value + */ +static inline void sdm_set_channel_comparator_high_threshold(SDM_Type *ptr, uint8_t ch, uint16_t value) +{ + ptr->CH[ch].SCHTL = value; +} + +/** + * @brief sdm set channel comparator zero crossing threshold + * + * @param ptr SDM base address + * @param ch channel index + * @param value zero crossing threshold value + */ +static inline void sdm_set_channel_comparator_zero_crossing_threshold(SDM_Type *ptr, uint8_t ch, uint16_t value) +{ + ptr->CH[ch].SCHTLZ = value; +} + +/** + * @brief sdm set channel comparator low threshold + * + * @param ptr SDM base address + * @param ch channel index + * @param value low threshold value + */ +static inline void sdm_set_channel_comparator_low_threshold(SDM_Type *ptr, uint8_t ch, uint16_t value) +{ + ptr->CH[ch].SCLLT = value; +} + +/** + * @brief sdm get channel comparator status register value + * + * @param ptr SDM base address + * @param ch channel index + * @return uint32_t channel comparator status register value + */ +static inline uint32_t sdm_get_channel_comparator_status(SDM_Type *ptr, uint8_t ch) +{ + return ptr->CH[ch].SCST; +} + +/** + * @brief sdm get default module control + * + * @param ptr SDM base address + * @param control sdm_control_t + */ +void sdm_get_default_module_control(SDM_Type *ptr, sdm_control_t *control); + +/** + * @brief sdm init module + * + * @param ptr SDM base address + * @param control sdm_control_t + */ +void sdm_init_module(SDM_Type *ptr, sdm_control_t *control); + +/** + * @brief sdm get channel common setting + * + * @param ptr SDM base address + * @param config sdm_channel_common_config_t + */ +void sdm_get_channel_common_setting(SDM_Type *ptr, sdm_channel_common_config_t *config); + +/** + * @brief sdm config channel's common setting + * + * @param ptr SDM base address + * @param ch_index channel index + * @param config sdm_channel_common_config_t + */ +void sdm_config_channel_common_setting(SDM_Type *ptr, uint8_t ch_index, sdm_channel_common_config_t *config); + +/** + * @brief sdm get channel default filter config + * + * @param ptr SDM base address + * @param filter_config sdm_filter_config_t + */ +void sdm_get_channel_default_filter_config(SDM_Type *ptr, sdm_filter_config_t *filter_config); + +/** + * @brief sdm config channel filter + * + * @param ptr SDM base address + * @param ch_index channel index + * @param filter_config sdm_filter_config_t + */ +void sdm_config_channel_filter(SDM_Type *ptr, uint8_t ch_index, sdm_filter_config_t *filter_config); + +/** + * @brief sdm get channel default comparator config + * + * @param ptr SDM base address + * @param cmp_config sdm_comparator_config_t + */ +void sdm_get_channel_default_comparator_config(SDM_Type *ptr, sdm_comparator_config_t *cmp_config); + +/** + * @brief sdm config channel comparator + * + * @param ptr SDM base address + * @param ch_index channel index + * @param cmp_config sdm_comparator_config_t + */ +void sdm_config_channel_comparator(SDM_Type *ptr, uint8_t ch_index, sdm_comparator_config_t *cmp_config); + +/** + * @brief sdm receive one filter data + * + * @param ptr SDM base address + * @param ch_index channel index + * @param using_fifo true for getting data from fifo, false for getting data from register + * @param data data buff + * @param data_len_in_bytes output data len in bytes + * @retval hpm_stat_t status_success only if it succeeds + */ +hpm_stat_t sdm_receive_one_filter_data(SDM_Type *ptr, uint8_t ch_index, bool using_fifo, int8_t *data, uint8_t data_len_in_bytes); + +/** + * @brief sdm receive filter data + * + * @param ptr SDM base address + * @param ch_index channel index + * @param using_fifo true for getting data from fifo, false for getting data from register + * @param data data buff + * @param count data count + * @param data_len_in_bytes output data len in bytes + * @retval hpm_stat_t status_success only if it succeeds + */ +hpm_stat_t sdm_receive_filter_data(SDM_Type *ptr, uint8_t ch_index, bool using_fifo, int8_t *data, uint32_t count, uint8_t data_len_in_bytes); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_SDM_DRV_H */ + diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h index a0edb502..b7c20a6f 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -18,6 +18,7 @@ #include "hpm_common.h" #include "hpm_sdp_regs.h" +#include "hpm_soc_feature.h" /*********************************************************************************************************************** * Definitions @@ -26,32 +27,71 @@ * @brief SDP AES key bit options */ typedef enum { - sdp_aes_keybits_128, /**< 128 bit AES key */ - sdp_aes_keybits_256, /**< 256 bit AES key */ -} sdp_aes_key_bits_t; + sdp_aes_keybits_128 = 0, /**< 128 bit AES key */ + sdp_aes_keybits_256 = 1, /**< 256 bit AES key */ +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) + sdp_sm4_keybits_128 = sdp_aes_keybits_128, /* SM4 Key bits */ +#endif +} sdp_crypto_key_bits_t; + +typedef sdp_crypto_key_bits_t sdp_aes_key_bits_t; + +typedef sdp_crypto_key_bits_t sdp_sm4_key_bits_t; + +/** + * @brief Crypto operation option + */ +typedef enum { + sdp_aes_op_encrypt, /**< AES Encrypt operation */ + sdp_aes_op_decrypt, /**< AES Decrypt operation */ +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) + sdp_sm4_op_encrypt = sdp_aes_op_encrypt, /**< SM4 Encrypt operation */ + sdp_sm4_op_decrypt = sdp_aes_op_decrypt, /**< SM4 Decrypt operation */ +#endif +} sdp_crypto_op_t; + +typedef sdp_crypto_op_t sdp_aes_op_t; + +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) + +typedef sdp_crypto_op_t sdp_sm4_op_t; + +#endif /** - * @brief AES operation option + * @brief SDP Crypto algorithms + * */ typedef enum { - sdp_aes_op_encrypt, /**< AES Encrypt operation */ - sdp_aes_op_decrypt, /**< AES Decrypt operation */ -} sdp_aes_op_t; + sdp_crypto_alg_aes, /**< AES */ +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) + sdp_crypto_alg_sm4, /**< SM4 */ +#endif +} sdp_crypto_alg_t; /** * @brief SDP HASH algorithm definitions */ typedef enum { - sdp_hash_alg_sha1, /**< SDP SHA1 */ - sdp_hash_alg_crc32, /**< SDP CRC32 */ - sdp_hash_alg_sha256, /**< SDP SHA256 */ + sdp_hash_alg_sha1 = 0, /**< SDP SHA1 */ + sdp_hash_alg_crc32 = 1, /**< SDP CRC32 */ + sdp_hash_alg_sha256 = 2, /**< SDP SHA256 */ +#if defined(SDP_HAS_SM3_SUPPORT) && (SDP_HAS_SM3_SUPPORT == 1) + sdp_hash_alg_sm3 = 8, /**< SDP SM3 */ + sdp_hash_alg_max = sdp_hash_alg_sm3, +#else sdp_hash_alg_max = sdp_hash_alg_sha256, +#endif } sdp_hash_alg_t; -#define HASH_BLOCK_SIZE (64U) /**< Hash block size in bytes */ -#define AES_BLOCK_SIZE (16U) /**< AES block size in bytes */ -#define AES_128_KEY_SIZE (0x10U) /**< AES 128-bit key size in bytes */ -#define AES_256_KEY_SIZE (0x20U) /**< AES 256-bit key size in bytes */ +#define HASH_BLOCK_SIZE (64U) /**< Hash block size in bytes */ +#define AES_BLOCK_SIZE (16U) /**< AES block size in bytes */ +#define AES_128_KEY_SIZE (0x10U) /**< AES 128-bit key size in bytes */ +#define AES_256_KEY_SIZE (0x20U) /**< AES 256-bit key size in bytes */ + +#define SM4_BLOCK_SIZE (AES_BLOCK_SIZE) /**< SM4 block size in bytes */ +#define SM4_KEY_SIZE (AES_128_KEY_SIZE) /**< SM4 Key size in bytes */ + /** * @brief Bitfield definitions for the PKT_CTRL */ @@ -68,15 +108,15 @@ typedef struct _sdp_packet_struct { struct _sdp_packet_struct *next_cmd; union { struct { - uint32_t RESERVED0 : 1; - uint32_t PKTINT : 1; /**< Packet interrupt flag */ - uint32_t DCRSEMA : 1; /**< Descrement Semaphore flag */ - uint32_t CHAIN : 1; /**< Chain Packet flag */ - uint32_t HASHINIT : 1; /**< Hash initialize flag */ - uint32_t HASHFINISH : 1; /**< Hash finish flag */ - uint32_t CIPHIV : 1; /**< Cipher IV flag */ - uint32_t RESERVED1 : 17; - uint32_t PKTTAG : 8; /**< Packet tag flag, not used */ + uint32_t RESERVED0: 1; + uint32_t PKTINT: 1; /**< Packet interrupt flag */ + uint32_t DCRSEMA: 1; /**< Descrement Semaphore flag */ + uint32_t CHAIN: 1; /**< Chain Packet flag */ + uint32_t HASHINIT: 1; /**< Hash initialize flag */ + uint32_t HASHFINISH: 1; /**< Hash finish flag */ + uint32_t CIPHIV: 1; /**< Cipher IV flag */ + uint32_t RESERVED1: 17; + uint32_t PKTTAG: 8; /**< Packet tag flag, not used */ }; uint32_t PKT_CTRL; /**< Packet control word */ } pkt_ctrl; @@ -92,13 +132,19 @@ typedef struct _sdp_packet_struct { typedef struct { uint8_t key_idx; /**< AES key index */ uint8_t key_bits; /**< AES key bits */ - uint16_t reserved; + uint16_t crypto_algo; sdp_pkt_struct_t sdp_pkt; /**< SDP packet for AES operation */ uint32_t buf0[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf0 */ uint32_t buf1[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf1 */ uint32_t buf2[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf2 */ uint32_t buf3[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf3 */ -} sdp_aes_ctx_t; +} sdp_crypto_ctx_t; + +typedef sdp_crypto_ctx_t sdp_aes_ctx_t; + +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +typedef sdp_crypto_ctx_t sdp_sm4_ctx_t; +#endif /** * @brief SDP DMA context @@ -130,7 +176,8 @@ enum { status_sdp_error_dst = MAKE_STATUS(status_group_sdp, 8), /**< Error destination address */ status_sdp_error_hash = MAKE_STATUS(status_group_sdp, 9), /**< Error Hash digest */ status_sdp_error_chain = MAKE_STATUS(status_group_sdp, 10), /**< Error packet chain */ - status_sdp_error_invalid_mac, /**< Inavlid Message Athenticaion Code (MAC) */ + status_sdp_error_invalid_mac = MAKE_STATUS(status_group_sdp, 11),/**< Inavlid Message Athenticaion Code (MAC) */ + status_sdp_invalid_alg = MAKE_STATUS(status_group_sdp, 12), /**< Invalid algorithm */ }; @@ -143,168 +190,298 @@ extern "C" /*********************************************************************************************************************** * Prototypes **********************************************************************************************************************/ - /** - * @brief Initialize the SDP controller - * @param [in] base SDP base address - * @retval API execution status. - */ - hpm_stat_t sdp_init(SDP_Type * base); - - /** - * @brief De-initialize the SDP controller - * @param [in] base SDP base address - * @retval API execution status. - */ - hpm_stat_t sdp_deinit(SDP_Type *base); - - /** - * @brief Set the AES key for the SDP AES operation - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] key AES key - * @param [in] key_bits AES key-bit option - * @param [in] key_idx AES key index - * @retval API execution status. - */ - hpm_stat_t sdp_aes_set_key(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t key_bits, - uint32_t key_idx); - - /** - * @brief Perform the basic AES ECB operation - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] op AES operation option - * @param [in] len AES data length in bytes - * @param [in] in Input buffer - * @param [out] out Output buffer - * @retval API execution status. - */ - hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, - uint8_t *out); - - /** - * @brief Perform the AES CBC operation - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] op AES operation option - * @param [in] length AES data length in bytes - * @param [in] iv Initial vector/nonce - * @param [in] input Input buffer - * @param [out] output Output buffer - * @retval API execution status. - */ - hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t length, - const uint8_t iv[16], const uint8_t *input, uint8_t *output); - - /** - * @brief Perform the AES-CTR operation - * See NIST Special Publication800-38A for more details - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] nonce_counter AES-CTR nounce/counter - * @param [in] input Input buffer - * @param [out] output Output buffer - * @param [in] length Length of data for AES-CTR operation - * @retval API execution status. - */ - hpm_stat_t sdp_aes_crypt_ctr(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_counter, uint8_t *input, - uint8_t *output, uint32_t length); - - /** - * @brief Perform the AES-CCM generate and encrypt - * See NIST Special Publication 800-38C for more details - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] input_len Input data length in bytes - * @param [in] iv Initial vector - * @param [in] iv_len Initial vector length in bytes - * @param [in] aad Additional Authentication data - * @param [in] aad_len Additional authentication data size - * @param [in] input Input data buffer - * @param [out] output Output buffer - * @param [out] tag MAC buffer - * @param [in] tag_len Tag/MAC size in bytes - * @retval API execution status. - */ - hpm_stat_t sdp_aes_ccm_generate_encrypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *iv, - uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, uint8_t *tag, uint32_t tag_len); - - /** - * @brief Perform the AES-CCM decrypt and verify - * See NIST Special Publication 800-38C for more details - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] input_len Input data length in bytes - * @param [in] iv Initial vector - * @param [in] iv_len Initial vector length in bytes - * @param [in] aad Additional Authentication data - * @param [in] aad_len Additional authentication data size - * @param [in] input Input data buffer - * @param [out] output Output buffer - * @param [in] tag MAC buffer - * @param [in] tag_len Tag/MAC size in bytes - * @retval API execution status. - */ - hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *iv, - uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, const uint8_t *tag, uint32_t tag_len); - - /** - * @brief Perform the DMA accelerated memcpy - * @param [in] base SDP base address - * @param [in] sdp_ctx SDP DMA context - * @param [out] dst Destination address for memcpy operation - * @param [in] src Source address for memcpy operation - * @param [in] length Length of the data to be copied - * @retval API execution status. - */ - hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, const void *src, uint32_t length); - - /** - * @brief Perform the DMA accelerated memset - * @param [in] base SDP base address - * @param [in] sdp_ctx SDP DMA context - * @param [out] dst SDP destination address for memset operation - * @param [in] pattern pattern for memset operation - * @param [in] length length of the memory for memset operation - * @retval API execution status. - */ - hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t pattern, uint32_t length); - - /** - * @brief Initialize the HASH engine - * @param [in] base SDP base address - * @param [in] hash_ctx HASH operation context - * @param [in] alg Hash algorithm - * @retval API execution status. status_success or status_invalid_argument - */ - hpm_stat_t sdp_hash_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); - - /** - * @brief Compute the HASH digest - * @param [in] base SDP base address - * @param [in] hash_ctx HASH operation context - * @param [in] data Data for HASH computing - * @param [in] length Data size for HASH computing - * @retval API execution status. - */ - hpm_stat_t sdp_hash_update(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); - - /** - * @brief Finish the HASH calculation and output the digest - * @param [in] base SDP base address - * @param [in] hash_ctx HASH operation context - * @param [out] digest Digest buffer - * @retval API execution status. - */ - hpm_stat_t sdp_hash_finish(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, uint8_t *digest); - - /** - * @brief Wait until the SDP operation gets done - * @retval API execution status. - */ - hpm_stat_t sdp_wait_done(SDP_Type *base); +/** + * @brief Initialize the SDP controller + * @param [in] base SDP base address + * @retval API execution status. + */ +hpm_stat_t sdp_init(SDP_Type *base); + +/** + * @brief De-initialize the SDP controller + * @param [in] base SDP base address + * @retval API execution status. + */ +hpm_stat_t sdp_deinit(SDP_Type *base); + +/** + * @brief Set the AES key for the SDP AES operation + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] key AES key + * @param [in] key_bits AES key-bit option + * @param [in] key_idx AES key index + * @retval API execution status. + */ +hpm_stat_t sdp_aes_set_key(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + const uint8_t *key, + sdp_aes_key_bits_t key_bits, + uint32_t key_idx); + +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +/** + * @brief Set the SM4 key for the SDP SM4 operation + * @param [in] base SDP base address + * @param [in] sm4_ctx AES operation context + * @param [in] key SM4 key + * @param [in] key_bits SM4 key-bit option + * @param [in] key_idx AES key index + * @retval API execution status. + */ +hpm_stat_t sdp_sm4_set_key(SDP_Type *base, + sdp_sm4_ctx_t *sm4_ctx, + const uint8_t *key, + sdp_sm4_key_bits_t key_bits, + uint32_t key_idx); +#endif + +/** + * @brief Perform the basic AES ECB operation + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] op AES operation option + * @param [in] len AES data length in bytes + * @param [in] in Input buffer + * @param [out] out Output buffer + * @retval API execution status. + */ +hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t len, + const uint8_t *in, + uint8_t *out); + +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +/** + * @brief Perform the basic SM4 ECB operation + * @param [in] base SDP base address + * @param [in] sm4_ctx SM4 operation context + * @param [in] op SM4 operation option + * @param [in] len SM4 data length in bytes + * @param [in] in Input buffer + * @param [out] out Output buffer + * @retval API execution status. + */ +#define sdp_sm4_crypt_ecb sdp_aes_crypt_ecb +#endif + +/** + * @brief Perform the AES CBC operation + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] op AES operation option + * @param [in] length AES data length in bytes + * @param [in] iv Initial vector/nonce + * @param [in] input Input buffer + * @param [out] output Output buffer + * @retval API execution status. + */ +hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + const uint8_t iv[16], + const uint8_t *input, + uint8_t *output); + +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +/** + * @brief Perform the SM4 CBC operation + * @param [in] base SM4 base address + * @param [in] sm4_ctx SM4 operation context + * @param [in] op SM4 operation option + * @param [in] length SM4 data length in bytes + * @param [in] iv Initial vector/nonce + * @param [in] input Input buffer + * @param [out] output Output buffer + * @retval API execution status. + */ +#define sdp_sm4_crypt_cbc sdp_aes_crypt_cbc +#endif + +/** + * @brief Perform the AES-CTR operation + * See NIST Special Publication800-38A for more details + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] nonce_counter AES-CTR nounce/counter + * @param [in] input Input buffer + * @param [out] output Output buffer + * @param [in] length Length of data for AES-CTR operation + * @retval API execution status. + */ +hpm_stat_t sdp_aes_crypt_ctr(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + uint8_t *nonce_counter, + uint8_t *input, + uint8_t *output, + uint32_t length); + +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +/** + * @brief Perform the SM4-CTR operation + * @param [in] base SDP base address + * @param [in] sm4_ctx SM4 operation context + * @param [in] nonce_counter SM4-CTR nounce/counter + * @param [in] input Input buffer + * @param [out] output Output buffer + * @param [in] length Length of data for SM4-CTR operation + * @retval API execution status. + */ +#define sdp_sm4_crypt_ctr sdp_aes_crypt_ctr +#endif + +/** + * @brief Perform the AES-CCM generate and encrypt + * See NIST Special Publication 800-38C for more details + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] input_len Input data length in bytes + * @param [in] iv Initial vector + * @param [in] iv_len Initial vector length in bytes + * @param [in] aad Additional Authentication data + * @param [in] aad_len Additional authentication data size + * @param [in] input Input data buffer + * @param [out] output Output buffer + * @param [out] tag MAC buffer + * @param [in] tag_len Tag/MAC size in bytes + * @retval API execution status. + */ +hpm_stat_t sdp_aes_ccm_generate_encrypt(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *iv, + uint32_t iv_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); + +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +/** + * @brief Perform the SM4-CCM generate and encrypt + * See NIST Special Publication 800-38C for more details + * @param [in] base SDP base address + * @param [in] sm4_ctx SM4 operation context + * @param [in] input_len Input data length in bytes + * @param [in] iv Initial vector + * @param [in] iv_len Initial vector length in bytes + * @param [in] aad Additional Authentication data + * @param [in] aad_len Additional authentication data size + * @param [in] input Input data buffer + * @param [out] output Output buffer + * @param [out] tag MAC buffer + * @param [in] tag_len Tag/MAC size in bytes + * @retval API execution status. + */ +#define sdp_sm4_ccm_generate_encrypt sdp_aes_ccm_generate_encrypt +#endif + +/** + * @brief Perform the AES-CCM decrypt and verify + * See NIST Special Publication 800-38C for more details + * @param [in] base SDP base address + * @param [in] aes_ctx AES operation context + * @param [in] input_len Input data length in bytes + * @param [in] iv Initial vector + * @param [in] iv_len Initial vector length in bytes + * @param [in] aad Additional Authentication data + * @param [in] aad_len Additional authentication data size + * @param [in] input Input data buffer + * @param [out] output Output buffer + * @param [in] tag MAC buffer + * @param [in] tag_len Tag/MAC size in bytes + * @retval API execution status. + */ +hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *iv, + uint32_t iv_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); + +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +/** + * @brief Perform the SM4-CCM decrypt and verify + * @param [in] base SDP base address + * @param [in] sm4_ctx SM4 operation context + * @param [in] input_len Input data length in bytes + * @param [in] iv Initial vector + * @param [in] iv_len Initial vector length in bytes + * @param [in] aad Additional Authentication data + * @param [in] aad_len Additional authentication data size + * @param [in] input Input data buffer + * @param [out] output Output buffer + * @param [in] tag MAC buffer + * @param [in] tag_len Tag/MAC size in bytes + * @retval API execution status. + */ +#define sdp_sm4_ccm_decrypt_verify sdp_aes_ccm_decrypt_verify +#endif +/** + * @brief Perform the DMA accelerated memcpy + * @param [in] base SDP base address + * @param [in] sdp_ctx SDP DMA context + * @param [out] dst Destination address for memcpy operation + * @param [in] src Source address for memcpy operation + * @param [in] length Length of the data to be copied + * @retval API execution status. + */ +hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, const void *src, uint32_t length); + +/** + * @brief Perform the DMA accelerated memset + * @param [in] base SDP base address + * @param [in] sdp_ctx SDP DMA context + * @param [out] dst SDP destination address for memset operation + * @param [in] pattern pattern for memset operation + * @param [in] length length of the memory for memset operation + * @retval API execution status. + */ +hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t pattern, uint32_t length); + +/** + * @brief Initialize the HASH engine + * @param [in] base SDP base address + * @param [in] hash_ctx HASH operation context + * @param [in] alg Hash algorithm + * @retval API execution status. status_success or status_invalid_argument + */ +hpm_stat_t sdp_hash_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); + +/** + * @brief Compute the HASH digest + * @param [in] base SDP base address + * @param [in] hash_ctx HASH operation context + * @param [in] data Data for HASH computing + * @param [in] length Data size for HASH computing + * @retval API execution status. + */ +hpm_stat_t sdp_hash_update(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); + +/** + * @brief Finish the HASH calculation and output the digest + * @param [in] base SDP base address + * @param [in] hash_ctx HASH operation context + * @param [out] digest Digest buffer + * @retval API execution status. + */ +hpm_stat_t sdp_hash_finish(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, uint8_t *digest); + +/** + * @brief Wait until the SDP operation gets done + * @retval API execution status. + */ +hpm_stat_t sdp_wait_done(SDP_Type *base); #ifdef __cplusplus } diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h index 50d69baf..ea723688 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h @@ -288,7 +288,7 @@ void spi_format_init(SPI_Type *ptr, spi_format_config_t *config); * * @param [in] ptr SPI base address * @param [in] config spi_control_config_t - * @param [in/out] cmd spi transfer command address + * @param [in,out] cmd spi transfer command address * @param [in] addr spi transfer target address * @param [in] wbuff spi sent data buff address * @param [in] wcount spi sent data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX @@ -320,6 +320,9 @@ hpm_stat_t spi_setup_dma_transfer(SPI_Type *ptr, /** * @brief spi wait for idle status * + * @note on master mode, if software controls CS signal, this function does not really reflect the SPI state. + * on slave mode, if CS signal is asserted, take it as busy; if SPI CS signal is de-asserted, take it as idle. + * * @param [in] ptr SPI base address * @retval hpm_stat_t status_success if spi in idle status */ @@ -328,6 +331,9 @@ hpm_stat_t spi_wait_for_idle_status(SPI_Type *ptr); /** * @brief spi wait for busy status * + * @note on master mode, if software controls CS signal, this function does not really reflect the SPI state. + * on slave mode, if CS signal is asserted, take it as busy; if SPI CS signal is de-asserted, take it as idle. + * * @param [in] ptr SPI base address * @retval hpm_stat_t status_success if spi in busy status */ @@ -338,7 +344,7 @@ hpm_stat_t spi_wait_for_busy_status(SPI_Type *ptr); * * This function configures SPI TX FIFO threshold. * - * @param base SPI base address. + * @param ptr SPI base address. * @param threshold The FIFO threshold value, the value should not greater than FIFO size. */ static inline void spi_set_tx_fifo_threshold(SPI_Type *ptr, uint32_t threshold) @@ -351,7 +357,7 @@ static inline void spi_set_tx_fifo_threshold(SPI_Type *ptr, uint32_t threshold) * * This function configures SPI RX FIFO threshold. * - * @param base SPI base address. + * @param ptr SPI base address. * @param threshold The FIFO threshold value, the value should not greater than FIFO size. */ static inline void spi_set_rx_fifo_threshold(SPI_Type *ptr, uint32_t threshold) @@ -515,7 +521,7 @@ hpm_stat_t spi_read_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_contro * @param [in] ptr SPI base address * @param [in] mode spi mode, use the spi_mode_selection_t * @param [in] config point to spi_control_config_t - * @param [in] cmd command data address + * @param [in] addr point to address * @retval hpm_stat_t status_success if spi transfer without any error */ hpm_stat_t spi_write_address(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint32_t *addr); @@ -553,6 +559,78 @@ static inline uint8_t spi_get_data_length_in_bytes(SPI_Type *ptr) return ((spi_get_data_length_in_bits(ptr) + 7U) / 8U); } +/** + * @brief SPI get active status. + * + * @param ptr SPI base address. + * @retval bool true for active, false for inactive + */ +static inline bool spi_is_active(SPI_Type *ptr) +{ + return ((ptr->STATUS & SPI_STATUS_SPIACTIVE_MASK) == SPI_STATUS_SPIACTIVE_MASK) ? true : false; +} + +/** + * @brief SPI enable tx dma + * + * @param ptr SPI base address + */ +static inline void spi_enable_tx_dma(SPI_Type *ptr) +{ + ptr->CTRL |= SPI_CTRL_TXDMAEN_MASK; +} + +/** + * @brief SPI disable tx dma + * + * @param ptr SPI base address + */ +static inline void spi_disable_tx_dma(SPI_Type *ptr) +{ + ptr->CTRL &= ~SPI_CTRL_TXDMAEN_MASK; +} + +/** + * @brief SPI enable rx dma + * + * @param ptr SPI base address + */ +static inline void spi_enable_rx_dma(SPI_Type *ptr) +{ + ptr->CTRL |= SPI_CTRL_RXDMAEN_MASK; +} + +/** + * @brief SPI disable rx dma + * + * @param ptr SPI base address + */ +static inline void spi_disable_rx_dma(SPI_Type *ptr) +{ + ptr->CTRL &= ~SPI_CTRL_RXDMAEN_MASK; +} + +/** + * @brief SPI slave get sent data count + * + * @param ptr SPI base address + * @retval uint32_t data count + */ +static inline uint32_t spi_slave_get_sent_data_count(SPI_Type *ptr) +{ + return SPI_SLVDATACNT_WCNT_GET(ptr->SLVDATACNT); +} + +/** + * @brief SPI slave get received data count + * + * @param ptr SPI base address + * @retval uint32_t data count + */ +static inline uint32_t spi_slave_get_received_data_count(SPI_Type *ptr) +{ + return SPI_SLVDATACNT_RCNT_GET(ptr->SLVDATACNT); +} /** * @} diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h index c1c38df2..fd4392e2 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h @@ -185,8 +185,9 @@ static inline void trgm_output_update_source(TRGM_Type *ptr, uint8_t output, uin static inline void trgm_output_config(TRGM_Type *ptr, uint8_t output, trgm_output_t *config) { ptr->TRGOCFG[output] = TRGM_TRGOCFG_TRIGOSEL_SET(config->input) - | TRGM_TRGOCFG_FEDG2PEN_SET(config->type) - | TRGM_TRGOCFG_REDG2PEN_SET(config->type); + | (config->type & TRGM_TRGOCFG_FEDG2PEN_MASK) + | (config->type & TRGM_TRGOCFG_REDG2PEN_MASK) + | TRGM_TRGOCFG_OUTINV_SET(config->invert); } /** diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h index 0ef26876..83ce0056 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021 - 2022 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,6 +9,7 @@ #define HPM_UART_DRV_H #include "hpm_common.h" #include "hpm_uart_regs.h" +#include "hpm_soc_feature.h" /** * @@ -85,6 +86,9 @@ typedef enum uart_intr_enable { uart_intr_tx_slot_avail = UART_IER_ETHEI_MASK, uart_intr_rx_line_stat = UART_IER_ELSI_MASK, uart_intr_modem_stat = UART_IER_EMSI_MASK, +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + uart_intr_rx_line_idle = UART_IER_ERXIDLE_MASK, +#endif } uart_intr_enable_t; /* @brief UART interrupt IDs */ @@ -117,20 +121,40 @@ typedef struct uart_modem_config { bool set_rts_high; /**< Set signal RTS level high flag */ } uart_modem_config_t; +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +/** + * @brief UART RX Line Idle detection conditions + */ +typedef enum hpm_uart_rxline_idle_cond { + uart_rxline_idle_cond_rxline_logic_one = 0, /**< Treat as idle if the RX Line high duration exceeds threshold */ + uart_rxline_idle_cond_state_machine_idle = 1 /**< Treat as idle if the RX state machine idle state duration exceeds threshold */ +} uart_rxline_idle_cond_t; + +typedef struct hpm_uart_rxline_idle_detect_config { + bool detect_enable; /**< RX Line Idle detection flag */ + bool detect_irq_enable; /**< Enable RX Line Idle detection interrupt */ + uart_rxline_idle_cond_t idle_cond; /**< RX Line Idle detection condition */ + uint8_t threshold; /**< UART RX Line Idle detection threshold, in terms of bits */ +} uart_rxline_idle_config_t; +#endif + /** * @brief UART config */ typedef struct hpm_uart_config { - uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */ - uint32_t baudrate; /**< Baudrate */ - uint8_t num_of_stop_bits; /**< Number of stop bits */ - uint8_t word_length; /**< Word length */ - uint8_t parity; /**< Parity */ - uint8_t tx_fifo_level; /**< TX Fifo level */ - uint8_t rx_fifo_level; /**< RX Fifo level */ - bool dma_enable; /**< DMA Enable flag */ - bool fifo_enable; /**< Fifo Enable flag */ - uart_modem_config_t modem_config; /**< Modem config */ + uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */ + uint32_t baudrate; /**< Baudrate */ + uint8_t num_of_stop_bits; /**< Number of stop bits */ + uint8_t word_length; /**< Word length */ + uint8_t parity; /**< Parity */ + uint8_t tx_fifo_level; /**< TX Fifo level */ + uint8_t rx_fifo_level; /**< RX Fifo level */ + bool dma_enable; /**< DMA Enable flag */ + bool fifo_enable; /**< Fifo Enable flag */ + uart_modem_config_t modem_config; /**< Modem config */ +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + uart_rxline_idle_config_t rxidle_config; /**< RX Idle configuration */ +#endif } uart_config_t; #ifdef __cplusplus @@ -140,7 +164,7 @@ extern "C" { /** * @brief Get fifo size * - * @param ptr UART base address + * @param [in] ptr UART base address * @retval size of Fifo */ static inline uint8_t uart_get_fifo_size(UART_Type *ptr) @@ -151,9 +175,9 @@ static inline uint8_t uart_get_fifo_size(UART_Type *ptr) /** * @brief Reset TX Fifo * - * @Note this API may modify other bit fields in FIFO control register + * @note this API may modify other bit fields in FIFO control register * - * @param ptr UART base address + * @param [in] ptr UART base address */ static inline void uart_reset_tx_fifo(UART_Type *ptr) { @@ -163,9 +187,9 @@ static inline void uart_reset_tx_fifo(UART_Type *ptr) /** * @brief Reset RX Fifo * - * @Note this API may modify other bit fields in FIFO control register + * @note this API may modify other bit fields in FIFO control register * - * @param ptr UART base address + * @param [in] ptr UART base address */ static inline void uart_reset_rx_fifo(UART_Type *ptr) { @@ -173,11 +197,11 @@ static inline void uart_reset_rx_fifo(UART_Type *ptr) } /** - * @brief Reset both TX and RX Fifo + * @brief [in] Reset both TX and RX Fifo * - * @Note this API may modify other bit fields in FIFO control register + * @note this API may modify other bit fields in FIFO control register * - * @param ptr UART base address + * @param [in] ptr UART base address */ static inline void uart_reset_all_fifo(UART_Type *ptr) { @@ -187,7 +211,7 @@ static inline void uart_reset_all_fifo(UART_Type *ptr) /** * @brief Enable modem loopback * - * @param ptr UART base address + * @param [in] ptr UART base address */ static inline void uart_modem_enable_loopback(UART_Type *ptr) { @@ -197,7 +221,7 @@ static inline void uart_modem_enable_loopback(UART_Type *ptr) /** * @brief Disable modem loopback * - * @param ptr UART base address + * @param [in] ptr UART base address */ static inline void uart_modem_disable_loopback(UART_Type *ptr) { @@ -207,7 +231,7 @@ static inline void uart_modem_disable_loopback(UART_Type *ptr) /** * @brief Disable modem auto flow control * - * @param ptr UART base address + * @param [in] ptr UART base address */ static inline void uart_modem_disable_auto_flow_control(UART_Type *ptr) @@ -218,7 +242,7 @@ static inline void uart_modem_disable_auto_flow_control(UART_Type *ptr) /** * @brief Enable modem auto flow control * - * @param ptr UART base address + * @param [in] ptr UART base address */ static inline void uart_modem_enable_auto_flow_control(UART_Type *ptr) { @@ -228,7 +252,7 @@ static inline void uart_modem_enable_auto_flow_control(UART_Type *ptr) /** * @brief Configure modem * - * @param ptr UART base address + * @param [in] ptr UART base address * @param config Pointer to modem config struct */ static inline void uart_modem_config(UART_Type *ptr, uart_modem_config_t *config) @@ -241,7 +265,7 @@ static inline void uart_modem_config(UART_Type *ptr, uart_modem_config_t *config /** * @brief Get modem status * - * @param ptr UART base address + * @param [in] ptr UART base address * @retval Current modem status */ static inline uint8_t uart_get_modem_status(UART_Type *ptr) @@ -275,20 +299,20 @@ static inline uint8_t uart_read_byte(UART_Type *ptr) /** * @brief Check modem status with given mask * - * @param ptr UART base address + * @param [in] ptr UART base address * @param mask Status mask value to be checked against * @retval true if any bit in given mask is set * @retval false if none of any bit in given mask is set */ static inline bool uart_check_modem_status(UART_Type *ptr, uart_modem_stat_t mask) { - return (ptr->MSR & mask); + return ((ptr->MSR & mask) != 0U) ? true : false; } /** * @brief Disable IRQ with mask * - * @param ptr UART base address + * @param [in] ptr UART base address * @param irq_mask IRQ mask value to be disabled */ static inline void uart_disable_irq(UART_Type *ptr, uart_intr_enable_t irq_mask) @@ -299,7 +323,7 @@ static inline void uart_disable_irq(UART_Type *ptr, uart_intr_enable_t irq_mask) /** * @brief Enable IRQ with mask * - * @param ptr UART base address + * @param [in] ptr UART base address * @param irq_mask IRQ mask value to be enabled */ static inline void uart_enable_irq(UART_Type *ptr, uart_intr_enable_t irq_mask) @@ -310,7 +334,7 @@ static inline void uart_enable_irq(UART_Type *ptr, uart_intr_enable_t irq_mask) /** * @brief Get Enabled IRQ * - * @param ptr UART base address + * @param [in] ptr UART base address * @return enabled irq */ static inline uint32_t uart_get_enabled_irq(UART_Type *ptr) @@ -321,7 +345,7 @@ static inline uint32_t uart_get_enabled_irq(UART_Type *ptr) /** * @brief Get interrupt identification * - * @param ptr UART base address + * @param [in] ptr UART base address * @retval interrupt id */ static inline uint8_t uart_get_irq_id(UART_Type *ptr) @@ -329,10 +353,58 @@ static inline uint8_t uart_get_irq_id(UART_Type *ptr) return (ptr->IIR & UART_IIR_INTRID_MASK); } +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +/** + * @brief Determine whether UART RX Line is idle + * @param [in] ptr UART base address + */ +static inline bool uart_is_rxline_idle(UART_Type *ptr) +{ + return ((ptr->IIR & UART_IIR_RXIDLE_FLAG_MASK) != 0U) ? true : false; +} + +/** + * @brief Clear UART RX Line Idle Flag + * @param [in] ptr UART base address + */ +static inline void uart_clear_rxline_idle_flag(UART_Type *ptr) +{ + ptr->IIR = UART_IIR_RXIDLE_FLAG_MASK; /* Write-1-Clear Logic */ +} + +/** + * @brief Enable UART RX Idle Line detection logic + * @param [in] ptr UART base address + */ +static inline void uart_enable_rxline_idle_detection(UART_Type *ptr) +{ + ptr->RXIDLE_CFG |= UART_RXIDLE_CFG_DETECT_EN_MASK; +} + +/** + * @brief Disable UART RX Idle Line detection logic + * + * @param [in] ptr UART base address + */ +static inline void uart_disable_rxline_idle_detection(UART_Type *ptr) +{ + ptr->RXIDLE_CFG &= ~UART_RXIDLE_CFG_DETECT_EN_MASK; +} + +/** + * @brief Configure UART RX Line detection + * @param [in] ptr UART base address + * @param [in] rxidle_config RXLine IDLE detection configuration + * @retval status_success if no error occurs + */ +hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t rxidle_config); + +#endif + /** * @brief Get status * - * @param ptr UART base address + * @param [in] ptr UART base address * @retval current status */ static inline uint8_t uart_get_status(UART_Type *ptr) @@ -343,20 +415,20 @@ static inline uint8_t uart_get_status(UART_Type *ptr) /** * @brief Check uart status according to the given status mask * - * @param ptr UART base address + * @param [in] ptr UART base address * @param mask Status mask value to be checked against * @retval true if any bit in given mask is set * @retval false if none of any bit in given mask is set */ static inline bool uart_check_status(UART_Type *ptr, uart_stat_t mask) { - return (ptr->LSR & mask); + return ((ptr->LSR & mask) != 0U) ? true : false; } /** * @brief Get default config * - * @param ptr UART base address + * @param [in] ptr UART base address * @param config Pointer to the buffer to save default values */ void uart_default_config(UART_Type *ptr, uart_config_t *config); @@ -364,7 +436,7 @@ void uart_default_config(UART_Type *ptr, uart_config_t *config); /** * @brief Initialization * - * @param ptr UART base address + * @param [in] ptr UART base address * @param config Pointer to config struct * @retval status_success only if it succeeds */ @@ -373,7 +445,7 @@ hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config); /** * @brief Send one byte after checking thresh hold status * - * @param ptr UART base address + * @param [in] ptr UART base address * @param c Byte to be sent * @retval status_success only if it succeeds */ @@ -382,7 +454,7 @@ hpm_stat_t uart_send_byte(UART_Type *ptr, uint8_t c); /** * @brief Receive one byte after checking data ready status * - * @param ptr UART base address + * @param [in] ptr UART base address * @param c Pointer to buffer to save the byte received on UART * @retval status_success only if it succeeds */ @@ -391,7 +463,7 @@ hpm_stat_t uart_receive_byte(UART_Type *ptr, uint8_t *c); /** * @brief Set uart signal output level * - * @param ptr UART base address + * @param [in] ptr UART base address * @param signal Target signal * @param level Target signal level */ @@ -402,7 +474,7 @@ void uart_set_signal_level(UART_Type *ptr, /** * @brief Flush sending buffer/fifo * - * @param ptr UART base address + * @param [in] ptr UART base address * @retval status_success only if it succeeds */ hpm_stat_t uart_flush(UART_Type *ptr); @@ -410,7 +482,7 @@ hpm_stat_t uart_flush(UART_Type *ptr); /** * @brief Receive bytes blocking * - * @param ptr UART base address + * @param [in] ptr UART base address * @param buf Pointer to the buffer to save received data * @param size_in_byte Size in byte to be sent * @retval status_success only if it succeeds @@ -420,7 +492,7 @@ hpm_stat_t uart_receive_data(UART_Type *ptr, uint8_t *buf, uint32_t size_in_byte /** * @brief Send bytes blocking * - * @param ptr UART base address + * @param [in] ptr UART base address * @param buf Pointer to the buffer to be sent * @param size_in_byte Size in byte to be sent * @retval status_success only if it succeeds diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h index 0059e337..51e81cb3 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -48,7 +48,7 @@ typedef enum interrupt_interval_enum { interrupt_interval_clock_period_multi_16k = 6, interrupt_interval_clock_period_multi_32k = 7, interrupt_interval_clock_period_multi_128k = 8, - interrupt_interval_clock_period_multi_256k = 9, + interrupt_interval_clock_period_multi_512k = 9, interrupt_interval_clock_period_multi_2m = 10, interrupt_interval_clock_period_multi_8m = 11, interrupt_interval_clock_period_multi_32m = 12, @@ -236,6 +236,26 @@ hpm_stat_t wdg_init(WDG_Type *base, wdg_control_t *wdg_ctrl); */ reset_interval_t wdg_convert_reset_interval_from_us(const uint32_t src_freq, const uint32_t reset_us); +/** + * @brief Convert the interrupt interval value based on the WDG source clock frequency and the expected interrupt interval + * in terms of microseconds + * + * @param [in] src_freq WDG source clock frequency + * @param [in] interval Expected Interrupt interval + * @retval Converted WDG interrupt interval in us + */ + uint64_t wdg_convert_interrupt_interval_to_us(const uint32_t src_freq, interrupt_interval_t interval); + +/** + * @brief Convert the Reset interval value based on the WDG source clock frequency and the expected reset interval + * in terms of microseconds + * + * @param [in] src_freq WDG source clock frequency + * @param [in] interval Expected Reset interval + * @retval Converted WDG reset interval in us + */ +uint32_t wdg_convert_reset_interval_to_us(const uint32_t src_freq, reset_interval_t interval); + /** * @brief Convert the interrupt interval value based on the WDG source clock frequency and the expected interrupt interval * in terms of microseconds @@ -253,7 +273,7 @@ interrupt_interval_t wdg_convert_interrupt_interval_from_us(const uint32_t src_f * @param [in] src_freq WDG source clock frequency * @return Converted WDG interrupt interval in terms of microseconds */ -uint32_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq); +uint64_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq); /** * @brief Get Actual WDG Reset Interval in terms of microseconds @@ -262,7 +282,7 @@ uint32_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_fre * @param [in] src_freq WDG source clock frequency * @return Converted WDG total reset interval in terms of microseconds */ -uint32_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq); +uint64_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq); #ifdef __cplusplus } diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c index 486078fd..e26e6551 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c @@ -13,7 +13,7 @@ void adc12_get_default_config(adc12_config_t *config) config->res = adc12_res_12_bits; config->conv_mode = adc12_conv_mode_oneshot; config->adc_clk_div = 1; - config->wait_dis = 0; + config->wait_dis = 1; config->sel_sync_ahb = true; config->adc_ahb_en = false; } @@ -162,7 +162,7 @@ hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config) hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config) { /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ptr, config->ch)) { + if (ADC12_IS_CHANNEL_INVALID(config->ch)) { return status_invalid_argument; } @@ -216,7 +216,7 @@ hpm_stat_t adc12_init_seq_dma(ADC12_Type *ptr, adc12_dma_config_t *dma_config) hpm_stat_t adc12_set_prd_config(ADC12_Type *ptr, adc12_prd_config_t *config) { /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ptr, config->ch)) { + if (ADC12_IS_CHANNEL_INVALID(config->ch)) { return status_invalid_argument; } @@ -264,7 +264,7 @@ hpm_stat_t adc12_set_seq_config(ADC12_Type *ptr, adc12_seq_config_t *config) /* Set sequence queue */ for (int i = 0; i < config->seq_len; i++) { /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ptr, config->queue[i].ch)) { + if (ADC12_IS_CHANNEL_INVALID(config->queue[i].ch)) { return status_invalid_argument; } @@ -287,7 +287,7 @@ hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config) temp |= ADC12_CONFIG_TRIG_LEN_SET(config->trig_len - 1); for (int i = 0; i < config->trig_len; i++) { - if (ADC12_IS_CHANNEL_INVALID(ptr, config->trig_ch)) { + if (ADC12_IS_CHANNEL_INVALID(config->trig_ch)) { return status_invalid_argument; } @@ -302,12 +302,21 @@ hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config) hpm_stat_t adc12_get_oneshot_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result) { + uint32_t bus_res; + /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ptr, ch)) { + if (ADC12_IS_CHANNEL_INVALID(ch)) { return status_invalid_argument; } - *result = ADC12_BUS_RESULT_CHAN_RESULT_GET(ptr->BUS_RESULT[ch]); + bus_res = ptr->BUS_RESULT[ch]; + *result = ADC12_BUS_RESULT_CHAN_RESULT_GET(bus_res); + + if (ADC12_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0)) { + if (!ADC12_BUS_RESULT_VALID_GET(bus_res)) { + return status_fail; + } + } return status_success; } @@ -315,7 +324,7 @@ hpm_stat_t adc12_get_oneshot_result(ADC12_Type *ptr, uint8_t ch, uint16_t *resul hpm_stat_t adc12_get_prd_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result) { /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ptr, ch)) { + if (ADC12_IS_CHANNEL_INVALID(ch)) { return status_invalid_argument; } diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c index bba6c8cf..d643f5aa 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c @@ -12,7 +12,7 @@ void adc16_get_default_config(adc16_config_t *config) { config->conv_mode = adc16_conv_mode_oneshot; config->adc_clk_div = 1; - config->wait_dis = 0; + config->wait_dis = 1; config->conv_duration = 0; config->sel_sync_ahb = true; config->port3_rela_time = false; @@ -46,7 +46,7 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); - /* Enable ADC clock */ + /* Enable ADC config clock */ ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; for (i = 0; i < ADC16_SOC_PARAMS_LEN; i++) { @@ -65,7 +65,7 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) /* Enable ahb_en */ ptr->ADC_CFG0 |= ADC16_ADC_CFG0_ADC_AHB_EN_MASK; - /* Disable ADC clock */ + /* Disable ADC config clock */ ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; /* Recover input clock divider */ @@ -109,7 +109,7 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) adc16_params[i] >>= 6; } - /* Enable ADC clock */ + /* Enable ADC config clock */ ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) @@ -136,7 +136,7 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); - /* Disable ADC clock */ + /* Disable ADC config clock */ ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; return status_success; @@ -144,17 +144,19 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config) { + uint32_t clk_div_temp; + /* Set convert clock number and clock period */ if (config->adc_clk_div > ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) { return status_invalid_argument; } /* Set ADC minimum conversion cycle and ADC clock divider */ - ptr->CONV_CFG1 = ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(21) + ptr->CONV_CFG1 = ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(config->res) | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div); /* Set ahb_en */ - /* Set convert duration */ + /* Set the duration of the conversion */ ptr->ADC_CFG0 = ADC16_ADC_CFG0_ADC_AHB_EN_SET(config->sel_sync_ahb) | ADC16_ADC_CFG0_CONVERT_DURATION_SET(config->conv_duration); @@ -164,6 +166,27 @@ hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config) ptr->BUF_CFG0 = ADC16_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); } + /* Get input clock divider */ + clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(ptr->CONV_CFG1); + + /* Set input clock divider temporarily */ + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); + + /* Enable ADC config clock */ + ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + /* Set end count */ + ptr->ADC16_CONFIG1 &= ~ADC16_ADC16_CONFIG1_COV_END_CNT_MASK; + ptr->ADC16_CONFIG1 |= ADC16_ADC16_CONFIG1_COV_END_CNT_SET(ADC16_SOC_MAX_CONV_CLK_NUM - config->res + 1); + + /* Disable ADC config clock */ + ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + /* Recover input clock divider */ + ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); + /* Do a calibration */ adc16_do_calibration(ptr); @@ -309,12 +332,12 @@ hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config) hpm_stat_t adc16_set_pmt_queue_enable(ADC16_Type *ptr, uint8_t trig_ch, bool enable) { -#if ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT == 1 /* Check the specified trigger channel */ if (ADC16_IS_TRIG_CH_INVLAID(trig_ch)) { return status_invalid_argument; } +#if ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT == 1 /* Set queue enable control */ ptr->CONFIG[trig_ch] |= ADC16_CONFIG_QUEUE_EN_SET(enable); return status_success; @@ -326,11 +349,21 @@ hpm_stat_t adc16_set_pmt_queue_enable(ADC16_Type *ptr, uint8_t trig_ch, bool ena /* one shot mode */ hpm_stat_t adc16_get_oneshot_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result) { + uint32_t bus_res; + + /* Check the specified channel number */ if (ADC16_IS_CHANNEL_INVALID(ch)) { return status_invalid_argument; } - *result = ADC16_BUS_RESULT_CHAN_RESULT_GET(ptr->BUS_RESULT[ch]); + bus_res = ptr->BUS_RESULT[ch]; + *result = ADC16_BUS_RESULT_CHAN_RESULT_GET(bus_res); + + if (ADC16_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0)) { + if (!ADC16_BUS_RESULT_VALID_GET(bus_res)) { + return status_fail; + } + } return status_success; } @@ -382,13 +415,13 @@ void adc16_disable_temp_sensor(ADC16_Type *ptr) ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); - /* Enable ADC clock */ + /* Enable ADC config clock */ ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; /* Disable the temp sensor */ ptr->ADC16_CONFIG0 &= ~ADC16_ADC16_CONFIG0_TEMPSNS_EN_MASK; - /* Disable ADC clock */ + /* Disable ADC config clock */ ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; /* Recover input clock divider */ diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c index d83d7726..3c58d8a8 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c @@ -73,6 +73,19 @@ void cam_reset(CAM_Type *ptr) hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config) { hpm_stat_t stat = status_success; + uint32_t pixel_format, width; + + pixel_format = config->color_format; + width = config->width; + + if (pixel_format == CAM_COLOR_FORMAT_RAW8) { + if ((width % 2) != 0) { + return status_invalid_argument; + } + /* use rgb565 format to receive raw8 data and adjust the width to half */ + pixel_format = CAM_COLOR_FORMAT_RGB565; + width /= 2; + } cam_reset(ptr); @@ -83,11 +96,11 @@ hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config) | CAM_CR1_COLOR_EXT_SET(config->color_ext) | CAM_CR1_PACK_DIR_SET(config->data_pack_msb) | config->data_store_mode - | config->color_format + | pixel_format | config->sensor_bitwidth; ptr->IDEAL_WN_SIZE = CAM_IDEAL_WN_SIZE_HEIGHT_SET(config->height) - | CAM_IDEAL_WN_SIZE_WIDTH_SET(config->width); + | CAM_IDEAL_WN_SIZE_WIDTH_SET(width); ptr->MAX_WN_CYCLE = CAM_MAX_WN_CYCLE_ROW_SET(1200) | CAM_MAX_WN_CYCLE_COL_SET(2090); diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_can_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_can_drv.c index 404727d3..b7a10b06 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_can_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_can_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -149,16 +149,16 @@ static uint32_t find_closest_prescaler(uint32_t num_tq_mul_prescaler, uint32_t s ++prescaler; continue; } else { - has_found = true; - break; - } - uint32_t tq = num_tq_mul_prescaler / prescaler; - if (tq * prescaler == num_tq_mul_prescaler) { - has_found = true; - break; - } else if (tq < min_tq) { - has_found = false; - break; + uint32_t tq = num_tq_mul_prescaler / prescaler; + if (tq * prescaler == num_tq_mul_prescaler) { + has_found = true; + break; + } else if (tq < min_tq) { + has_found = false; + break; + } else { + ++prescaler; + } } } @@ -683,8 +683,6 @@ hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq) base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TSSS_MASK; } - can_enable_self_ack(base, config->enable_self_ack); - /* Configure CAN filters */ if (config->filter_list_num > CAN_FILTER_NUM_MAX) { status = status_can_filter_num_invalid; @@ -712,6 +710,9 @@ hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq) can_reset(base, false); + /* Set Self-ack mode*/ + can_enable_self_ack(base, config->enable_self_ack); + /* Set CAN work mode */ can_set_node_mode(base, config->mode); diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c new file mode 100644 index 00000000..52c2c80b --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_crc_drv.h" + +void crc_get_default_channel_config(crc_channel_config_t *cfg) +{ + cfg->preset = crc_preset_crc32; + cfg->poly = 0x4C11DB7ul; + cfg->init = 0xFFFFFFFul; + cfg->in_byte_order = crc_in_byte_order_lsb; + cfg->refout = crc_refout_true; + cfg->refin = crc_refin_true; + cfg->poly_width = CRC_POLY_WIDTH_32; + cfg->xorout = 0xFFFFFFF; +} + +hpm_stat_t crc_setup_channel_config(CRC_Type *ptr, uint32_t ch_index, + crc_channel_config_t *cfg) +{ + ptr->CHN[ch_index].CLR |= CRC_CHN_CLR_CLR_MASK; + ptr->CHN[ch_index].PRE_SET = cfg->preset; + + if (!ptr->CHN[ch_index].PRE_SET) { + ptr->CHN[ch_index].POLY = cfg->poly; + ptr->CHN[ch_index].INIT_DATA = cfg->init; + ptr->CHN[ch_index].XOROUT = cfg->xorout; + ptr->CHN[ch_index].MISC_SETTING = CRC_CHN_MISC_SETTING_REV_OUT_SET(cfg->refout) | + CRC_CHN_MISC_SETTING_REV_IN_SET(cfg->refin) | + CRC_CHN_MISC_SETTING_POLY_WIDTH_SET(cfg->poly_width); + } + + ptr->CHN[ch_index].MISC_SETTING |= CRC_CHN_MISC_SETTING_BYTE_REV_SET(cfg->in_byte_order); + return status_success; +} + +void crc_calc_block_bytes(CRC_Type *ptr, uint32_t ch_index, uint8_t *pbuffer, uint32_t length) +{ + uint32_t addr = (uint32_t)&ptr->CHN[ch_index].DATA; + + for (uint32_t i = 0; i < length; i++) { + CRC_REG_WRITE8(addr, pbuffer[i]); + } +} + +void crc_calc_block_half_words(CRC_Type *ptr, uint32_t ch_index, uint16_t *pbuffer, uint32_t length) +{ + uint32_t addr = (uint32_t)&ptr->CHN[ch_index].DATA; + + for (uint32_t i = 0; i < length; i++) { + CRC_REG_WRITE16(addr, pbuffer[i]); + } +} + +void crc_calc_block_words(CRC_Type *ptr, uint32_t ch_index, uint32_t *pbuffer, uint32_t length) +{ + uint32_t addr = (uint32_t)&ptr->CHN[ch_index].DATA; + + for (uint32_t i = 0; i < length; i++) { + CRC_REG_WRITE32(addr, pbuffer[i]); + } +} + +void crc_calc_large_block_fast(CRC_Type *ptr, uint32_t ch_index, uint8_t *pbuffer, uint32_t length) +{ + if (length < 16) { + crc_calc_block_bytes(ptr, ch_index, pbuffer, length); + return; + } + + uint32_t addr = (uint32_t)&ptr->CHN[ch_index].DATA; + uint32_t start_byte_addr = (uint32_t)pbuffer; + uint32_t start_byte_len = 4ul - (start_byte_addr & 0x03ul); + uint32_t word_addr = start_byte_addr + start_byte_len; + uint32_t word_len = (length - start_byte_len) & (~0x03ul); + uint32_t end_byte_addr = word_addr + word_len; + uint32_t end_byte_len = (length - start_byte_len - word_len); + + for (uint32_t i = 0; i < start_byte_len; i++) { + CRC_REG_WRITE8(addr, *(volatile uint8_t *)(start_byte_addr + i)); + } + + for (uint32_t i = 0; i < word_len; i += 4) { + CRC_REG_WRITE32(addr, *(volatile uint32_t *)(word_addr + i)); + } + + for (uint32_t i = 0; i < end_byte_len; i++) { + CRC_REG_WRITE8(addr, *(volatile uint8_t *)(end_byte_addr + i)); + } +} + diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c index 3a36766e..ee94cdcf 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c @@ -1,19 +1,21 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * */ -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Includes - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ #include "hpm_enet_drv.h" #include "hpm_enet_soc_drv.h" -/*---------------------------------------------------------------------* +/*--------------------------------------------------------------------- * Internal API - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ static void enet_mode_init(ENET_Type *ptr, uint32_t intr) { /* receive and transmit store and forward */ @@ -92,12 +94,15 @@ static int enet_mac_init(ENET_Type *ptr, enet_mac_config_t *config, enet_inf_typ { for (int i = 0; i < config->valid_max_count; i++) { if (i == 0) { - ptr->MAC_ADDR_0_HIGH = ENET_MAC_ADDR_0_HIGH_AE_MASK; + ptr->MAC_ADDR_0_HIGH &= ~ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK; + ptr->MAC_ADDR_0_LOW &= ~ENET_MAC_ADDR_0_LOW_ADDRLO_MASK; ptr->MAC_ADDR_0_HIGH |= ENET_MAC_ADDR_0_HIGH_ADDRHI_SET(config->mac_addr_high[i]); - ptr->MAC_ADDR_0_LOW = ENET_MAC_ADDR_0_LOW_ADDRLO_SET(config->mac_addr_low[i]); + ptr->MAC_ADDR_0_LOW |= ENET_MAC_ADDR_0_LOW_ADDRLO_SET(config->mac_addr_low[i]); } else { - ptr->MAC_ADDR[i].HIGH |= ENET_MAC_ADDR_HIGH_ADDRHI_SET(config->mac_addr_high[i]); - ptr->MAC_ADDR[i].LOW |= ENET_MAC_ADDR_LOW_ADDRLO_SET(config->mac_addr_low[i]); + ptr->MAC_ADDR[i-1].HIGH &= ~ENET_MAC_ADDR_HIGH_ADDRHI_MASK; + ptr->MAC_ADDR[i-1].LOW &= ~ENET_MAC_ADDR_LOW_ADDRLO_MASK; + ptr->MAC_ADDR[i-1].HIGH |= ENET_MAC_ADDR_HIGH_AE_MASK | ENET_MAC_ADDR_HIGH_ADDRHI_SET(config->mac_addr_high[i]); + ptr->MAC_ADDR[i-1].LOW |= ENET_MAC_ADDR_LOW_ADDRLO_SET(config->mac_addr_low[i]); } } @@ -105,8 +110,8 @@ static int enet_mac_init(ENET_Type *ptr, enet_mac_config_t *config, enet_inf_typ ptr->MACFF |= ENET_MACFF_RA_SET(1); /* receive all */ /* replace the content of the mac address 0 in the sa field of all transmitted frames */ - ptr->MACCFG &= ENET_MACCFG_SARC_MASK; - ptr->MACCFG |= ENET_MACCFG_SARC_SET(0x3); + ptr->MACCFG &= ~ENET_MACCFG_SARC_MASK; + ptr->MACCFG |= ENET_MACCFG_SARC_SET(config->sarc); ptr->MACCFG |= ENET_MACCFG_PS_MASK | ENET_MACCFG_FES_MASK; @@ -126,6 +131,7 @@ static int enet_mac_init(ENET_Type *ptr, enet_mac_config_t *config, enet_inf_typ ptr->MACCFG |= ENET_MACCFG_IFG_SET(2); } + /* enable transmitter enable and receiver */ ptr->MACCFG |= ENET_MACCFG_TE_MASK | ENET_MACCFG_RE_MASK; @@ -139,7 +145,8 @@ static void enet_mask_interrupt_event(ENET_Type *ptr, uint32_t mask) } /*--------------------------------------------------------------------- * Driver API - *---------------------------------------------------------------------*/ + *--------------------------------------------------------------------- + */ void enet_dma_flush(ENET_Type *ptr) { /* flush DMA transmit FIFO */ @@ -183,6 +190,7 @@ uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr) return (uint16_t)ENET_GMII_DATA_GD_GET(ptr->GMII_DATA); } + void enet_set_line_speed(ENET_Type *ptr, enet_line_speed_t speed) { ptr->MACCFG &= ~(ENET_MACCFG_PS_MASK | ENET_MACCFG_FES_MASK); @@ -197,7 +205,7 @@ void enet_set_duplex_mode(ENET_Type *ptr, enet_duplex_mode_t mode) int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *config, enet_int_config_t *int_config) { - /* select RGMII */ + /* select an interface */ enet_intf_selection(ptr, inf_type); /* initialize DMA */ @@ -212,9 +220,10 @@ int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t * return true; } -/******************************************************************************/ -/* DMA API */ -/******************************************************************************/ +/***************************************************************************** + * DMA API + ***************************************************************************** + */ uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info) { enet_rx_desc_t *rx_desc_list_cur = *parent_rx_desc_list_cur; @@ -339,6 +348,99 @@ enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_l return frame; } +void enet_get_default_tx_control_config(ENET_Type *ptr, enet_tx_control_config_t *config) +{ + config->enable_ioc = false; + config->disable_crc = true; + config->disable_pad = false; + config->enable_tts = false; + config->enable_crcr = true; + config->cic = enet_cic_ip_pseudoheader; + config->vlic = enet_vlic_disable; + config->saic = enet_saic_disable; +} + +uint32_t enet_prepare_tx_desc(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, enet_tx_control_config_t *config, uint16_t frame_length, uint16_t tx_buff_size) +{ + uint32_t buf_count = 0, size = 0, i = 0; + enet_tx_desc_t *dma_tx_desc; + enet_tx_desc_t *tx_desc_list_cur = *parent_tx_desc_list_cur; + + if (tx_buff_size == 0) { + return ENET_ERROR; + } + /* check if the descriptor is owned by the Ethernet DMA (when set) or CPU (when reset) */ + dma_tx_desc = tx_desc_list_cur; + if (frame_length > tx_buff_size) { + buf_count = frame_length / tx_buff_size; + if (frame_length % tx_buff_size) { + buf_count++; + } + } else { + buf_count = 1; + } + + if (buf_count == 1) { + /*set the last and the first segment */ + dma_tx_desc->tdes0_bm.own = 0; + dma_tx_desc->tdes0_bm.fs = 1; + dma_tx_desc->tdes0_bm.ls = 1; + dma_tx_desc->tdes0_bm.ic = config->enable_ioc; + dma_tx_desc->tdes0_bm.dc = config->disable_crc; + dma_tx_desc->tdes0_bm.dp = config->disable_pad; + dma_tx_desc->tdes0_bm.crcr = config->enable_crcr; + dma_tx_desc->tdes0_bm.cic = config->cic; + dma_tx_desc->tdes0_bm.vlic = config->vlic; + dma_tx_desc->tdes1_bm.saic = config->saic; + /* set the frame size */ + dma_tx_desc->tdes1_bm.tbs1 = (frame_length & ENET_DMATxDesc_TBS1); + /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ + dma_tx_desc->tdes0_bm.own = 1; + ptr->DMA_TX_POLL_DEMAND = 1; + + dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); + } else { + for (i = 0; i < buf_count; i++) { + /* clear first and last segment bits */ + dma_tx_desc->tdes0_bm.fs = 0; + dma_tx_desc->tdes0_bm.ls = 0; + + if (i == 0) { + /* setting the first segment bit */ + dma_tx_desc->tdes0_bm.fs = 1; + dma_tx_desc->tdes0_bm.dc = config->disable_crc; + dma_tx_desc->tdes0_bm.dp = config->disable_pad; + dma_tx_desc->tdes0_bm.crcr = config->enable_crcr; + dma_tx_desc->tdes0_bm.cic = config->cic; + dma_tx_desc->tdes0_bm.vlic = config->vlic; + dma_tx_desc->tdes1_bm.saic = config->saic; + } + + /* set the buffer 1 size */ + dma_tx_desc->tdes1_bm.tbs1 = (tx_buff_size & ENET_DMATxDesc_TBS1); + + if (i == (buf_count - 1)) { + /* set the last segment bit */ + dma_tx_desc->tdes0_bm.ls = 1; + dma_tx_desc->tdes0_bm.ic = config->enable_ioc; + size = frame_length - (buf_count - 1) * tx_buff_size; + dma_tx_desc->tdes1_bm.tbs1 = (size & ENET_DMATxDesc_TBS1); + + /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ + dma_tx_desc->tdes0_bm.own = 1; + ptr->DMA_TX_POLL_DEMAND = 1; + } + + dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); + } + } + + tx_desc_list_cur = dma_tx_desc; + *parent_tx_desc_list_cur = tx_desc_list_cur; + + return ENET_SUCCESS; +} + uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, uint16_t frame_length, uint16_t tx_buff_size) { uint32_t buf_count = 0, size = 0, i = 0; @@ -613,34 +715,65 @@ void enet_set_pps0_control_output(ENET_Type *ptr, enet_pps_ctrl_t freq) ptr->PPS_CTRL |= ENET_PPS_CTRL_PPSCTRLCMD0_SET(freq); } -void enet_set_pps0_cmd(ENET_Type *ptr, enet_pps_cmd_t cmd) +hpm_stat_t enet_set_ppsx_command(ENET_Type *ptr, enet_pps_cmd_t cmd, enet_pps_idx_t idx) { + if (idx >= ENET_SOC_PPS_MAX_COUNT) { + return status_invalid_argument; + } + /* Wait the last command to complete */ - while (ENET_PPS_CTRL_PPSCTRLCMD0_GET(ptr->PPS_CTRL)) { + while (ptr->PPS_CTRL & (ENET_PPS_CMD_MASK << ((idx + 1) << ENET_PPS_CMD_OFS_FAC))) { } - ptr->PPS_CTRL |= ENET_PPS_CTRL_PPSCTRLCMD0_SET(cmd); + /* Set the specified pps output with a specified command */ + ptr->PPS_CTRL |= cmd << ((idx + 1) << ENET_PPS_CMD_OFS_FAC); + + return status_success; } -void enet_set_pps0_command_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg) +hpm_stat_t enet_set_ppsx_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg, enet_pps_idx_t idx) { - /* Set PPS0 interval and width */ - ptr->PPS0_INTERVAL = cmd_cfg->pps_interval - 1; - ptr->PPS0_WIDTH = cmd_cfg->pps_width - 1; + if (idx >= ENET_SOC_PPS_MAX_COUNT) { + return status_invalid_argument; + } + + /* Set the interval and width for PPSx */ + if (idx == enet_pps_0) { + ptr->PPS0_INTERVAL = cmd_cfg->pps_interval - 1; + ptr->PPS0_WIDTH = cmd_cfg->pps_width - 1; + } else { + ptr->PPS[idx].INTERVAL = cmd_cfg->pps_interval - 1; + ptr->PPS[idx].WIDTH = cmd_cfg->pps_width - 1; + } /* Set the target timestamp */ - ptr->TGTTM_SEC = cmd_cfg->target_sec; - ptr->TGTTM_NSEC = cmd_cfg->target_nsec; + if (idx == enet_pps_0) { + ptr->TGTTM_SEC = cmd_cfg->target_sec; + ptr->TGTTM_NSEC = cmd_cfg->target_nsec; + } else { + ptr->PPS[idx].TGTTM_SEC = cmd_cfg->target_sec; + ptr->PPS[idx].TGTTM_NSEC = cmd_cfg->target_nsec; + } /* Set PPS0 as the command function */ - ptr->PPS_CTRL |= ENET_PPS_CTRL_PPSEN0_MASK; + if (idx == enet_pps_0) { + ptr->PPS_CTRL |= ENET_PPS_CTRL_PPSEN0_MASK; + } + +#if ENET_SOC_PPS1_EN + if (idx == enet_pps_1) { + ptr->PPS_CTRL |= ENET_PPS_CTRL_PPSEN1_MASK; + } +#endif /* Wait the last command to complete */ - while (ENET_PPS_CTRL_PPSCTRLCMD0_GET(ptr->PPS_CTRL)) { + while (ptr->PPS_CTRL & (ENET_PPS_CMD_MASK << ((idx + 1) << ENET_PPS_CMD_OFS_FAC))) { } /* Initialize with the No Command */ - ptr->PPS_CTRL &= ~ENET_PPS_CTRL_PPSCTRLCMD0_MASK; -} + ptr->PPS_CTRL &= ~(ENET_PPS_CMD_MASK << ((idx + 1) << ENET_PPS_CMD_OFS_FAC)); + + return status_success; +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c index c4a8930a..543834c4 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c @@ -29,7 +29,9 @@ hpm_stat_t gptmr_channel_config(GPTMR_Type *ptr, bool enable) { uint32_t v = 0; - if ((config->enable_sync_follow_previous_channel && !ch_index) || (config->reload == 0)) { + uint32_t tmp_value; + + if (config->enable_sync_follow_previous_channel && !ch_index) { return status_invalid_argument; } @@ -47,9 +49,17 @@ hpm_stat_t gptmr_channel_config(GPTMR_Type *ptr, | config->synci_edge; for (uint8_t i = 0; i < GPTMR_CH_CMP_COUNT; i++) { - ptr->CHANNEL[ch_index].CMP[i] = GPTMR_CHANNEL_CMP_CMP_SET(config->cmp[i]); + tmp_value = config->cmp[i]; + if (tmp_value > 0) { + tmp_value--; + } + ptr->CHANNEL[ch_index].CMP[i] = GPTMR_CHANNEL_CMP_CMP_SET(tmp_value); + } + tmp_value = config->reload; + if (tmp_value > 0) { + tmp_value--; } - ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(config->reload - 1); + ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(tmp_value); ptr->CHANNEL[ch_index].CR = v; return status_success; } diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c index 02dc8680..d2e6e8ba 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c @@ -11,15 +11,11 @@ #define HPM_I2C_DRV_DEFAULT_TPM (0U) #endif -#ifndef HPM_I2C_DRV_DEFAULT_SCL_RATIO -#define HPM_I2C_DRV_DEFAULT_SCL_RATIO (1U) -#endif - #ifndef HPM_I2C_DRV_DEFAULT_RETRY_COUNT #define HPM_I2C_DRV_DEFAULT_RETRY_COUNT (5000U) #endif -#define period_in_ns(freq) (1000000000UL / (freq)) +#define period_in_100ps(freq) (10000000000UL / (freq)) typedef struct { uint32_t t_high; @@ -27,8 +23,7 @@ typedef struct { uint16_t t_sp; uint16_t t_sudat; uint16_t t_hddat; - uint16_t t_sclhi_min1; - uint16_t t_sclhi_min2; + uint16_t t_sclhi; uint16_t t_sclratio; } i2c_timing_t; @@ -36,6 +31,10 @@ static hpm_stat_t i2c_configure_timing(uint32_t src_clk_in_hz, i2c_mode_t i2c_mode, i2c_timing_t *timing) { + int32_t setup_time, hold_time, period; + int32_t temp1, temp2, temp3; + int32_t tpclk = period_in_100ps(src_clk_in_hz); + switch (i2c_mode) { /* * |Standard mode | Fast mode | Fast mode plus | Uint @@ -44,17 +43,30 @@ static hpm_stat_t i2c_configure_timing(uint32_t src_clk_in_hz, * t_low | 4.7 | 1.3 | 0.5 | us * */ + /* time uint: 100ps */ case i2c_mode_fast: - timing->t_high = 600; - timing->t_low = 1300; + timing->t_high = 6000; + timing->t_low = 13000; + timing->t_sclratio = 2; + setup_time = 1000; + hold_time = 3000; + period = period_in_100ps(400000); /**< baudrate 400KHz */ break; case i2c_mode_fast_plus: - timing->t_high = 260; - timing->t_low = 500; + timing->t_high = 2600; + timing->t_low = 5000; + timing->t_sclratio = 2; + setup_time = 500; + hold_time = 0; + period = period_in_100ps(1000000); /**< baudrate 1MHz */ break; case i2c_mode_normal: - timing->t_high = 4000; - timing->t_low = 4700; + timing->t_high = 40000; + timing->t_low = 47000; + timing->t_sclratio = 1; + setup_time = 2500; + hold_time = 3000; + period = period_in_100ps(100000); /**< baudrate 100KHz */ break; default: return status_i2c_not_supported; @@ -66,9 +78,9 @@ static hpm_stat_t i2c_configure_timing(uint32_t src_clk_in_hz, * ------------------+----------+-----------+----------------+------- * t_sp (min) | - | 0 - 50 | 0 - 50 | ns * - * T_SP = 50ns / (25ns * (TPM + 1)) + * T_SP = 50ns / (tpclk * (TPM + 1)) */ - timing->t_sp = 50 / period_in_ns(src_clk_in_hz) / (HPM_I2C_DRV_DEFAULT_TPM + 1); + timing->t_sp = 500 / period_in_100ps(src_clk_in_hz) / (HPM_I2C_DRV_DEFAULT_TPM + 1); /* * Setup time |Standard mode | Fast mode | Fast mode plus | Uint @@ -77,8 +89,8 @@ static hpm_stat_t i2c_configure_timing(uint32_t src_clk_in_hz, * * Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk * (TPM + 1) */ - timing->t_sudat = (250 - 2 * period_in_ns(src_clk_in_hz)) / period_in_ns(src_clk_in_hz) - 2 - timing->t_sp; - + temp1 = (setup_time - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp; + timing->t_sudat = MAX(temp1, 0); /* * Hold time |Standard mode | Fast mode | Fast mode plus | Uint * ----------------+--------------+-----------+----------------+------- @@ -86,20 +98,29 @@ static hpm_stat_t i2c_configure_timing(uint32_t src_clk_in_hz, * * Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk * (TPM + 1) */ - timing->t_hddat = (300 - 2 * period_in_ns(src_clk_in_hz)) / period_in_ns(src_clk_in_hz) - 2 - timing->t_sp; + temp1 = (hold_time - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp; + timing->t_hddat = MAX(temp1, 0); /* * SCLK High period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk * (TPM + 1) > t_high; */ - timing->t_sclhi_min1 = (timing->t_high - 2 * period_in_ns(src_clk_in_hz)) - / (HPM_I2C_DRV_DEFAULT_TPM + 1) / period_in_ns(src_clk_in_hz) - 2 - timing->t_sp; + temp1 = (timing->t_high - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp; + + /* + * SCLK High period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk * (TPM + 1) > period / (1 + ratio); + */ + temp2 = (period / (1 + timing->t_sclratio) - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp; /* * SCLK Low period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM + 1) > t_low; */ - timing->t_sclhi_min2 = ((timing->t_low - 2 * period_in_ns(src_clk_in_hz)) - / (HPM_I2C_DRV_DEFAULT_TPM + 1) / period_in_ns(src_clk_in_hz) - 2 - timing->t_sp) - / (timing->t_sclratio); + temp3 = ((timing->t_low - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp) / (timing->t_sclratio); + + timing->t_sclhi = MAX(MAX(temp1, temp2), temp3); + + /* update high_period and low_period to calculated value */ + timing->t_high = 2 * tpclk + (2 + timing->t_sp + timing->t_sclhi) * tpclk; + timing->t_low = timing->t_high * timing->t_sclratio; return status_success; } @@ -118,7 +139,6 @@ hpm_stat_t i2c_init_master(I2C_Type *ptr, uint32_t src_clk_in_hz, i2c_config_t * i2c_reset(ptr); - timing.t_sclratio = HPM_I2C_DRV_DEFAULT_SCL_RATIO; stat = i2c_configure_timing(src_clk_in_hz, config->i2c_mode, &timing); if (status_success != stat) { return stat; @@ -130,7 +150,7 @@ hpm_stat_t i2c_init_master(I2C_Type *ptr, uint32_t src_clk_in_hz, i2c_config_t * | I2C_SETUP_T_SUDAT_SET(timing.t_sudat) | I2C_SETUP_T_HDDAT_SET(timing.t_hddat) | I2C_SETUP_T_SCLRADIO_SET(timing.t_sclratio - 1) - | I2C_SETUP_T_SCLHI_SET(MAX(timing.t_sclhi_min1, timing.t_sclhi_min2)) + | I2C_SETUP_T_SCLHI_SET(timing.t_sclhi) | I2C_SETUP_ADDRESSING_SET(config->is_10bit_addressing) | I2C_SETUP_IICEN_MASK | I2C_SETUP_MASTER_MASK; @@ -149,11 +169,22 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, assert(addr_size_in_byte > 0 && addr_size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); assert(size_in_byte > 0 && size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); - ptr->CMD = I2C_CMD_RESET; + retry = 0; + while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS |= I2C_STATUS_CMPL_MASK; ptr->CMD = I2C_CMD_CLEAR_FIFO; ptr->CTRL = I2C_CTRL_PHASE_START_MASK - | I2C_CTRL_PHASE_STOP_MASK | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) @@ -178,6 +209,8 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { return status_timeout; } + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS |= I2C_STATUS_CMPL_MASK; ptr->CMD = I2C_CMD_CLEAR_FIFO; ptr->CTRL = I2C_CTRL_PHASE_START_MASK @@ -217,7 +250,6 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { return status_timeout; } - ptr->STATUS |= I2C_STATUS_CMPL_MASK; return stat; } @@ -233,7 +265,19 @@ hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address assert(size_in_byte > 0 && size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); assert(addr_size_in_byte + size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); - ptr->CMD = I2C_CMD_RESET; + retry = 0; + while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS |= I2C_STATUS_CMPL_MASK; ptr->CMD = I2C_CMD_CLEAR_FIFO; ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); @@ -282,9 +326,6 @@ hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address return status_timeout; } - ptr->STATUS |= I2C_STATUS_CMPL_MASK; - - ptr->CMD = I2C_CMD_RESET; return stat; } @@ -297,6 +338,20 @@ hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + retry = 0; + while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS |= I2C_STATUS_CMPL_MASK; + ptr->CMD = I2C_CMD_CLEAR_FIFO; ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); ptr->CTRL = I2C_CTRL_PHASE_START_MASK @@ -344,9 +399,6 @@ hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, return status_fail; } - ptr->STATUS |= I2C_STATUS_CMPL_MASK | I2C_STATUS_ADDRHIT_MASK; - - ptr->INTEN = 0; if (i2c_get_data_count(ptr)) { return status_i2c_transmit_not_completed; } @@ -363,6 +415,20 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + retry = 0; + while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS |= I2C_STATUS_CMPL_MASK; + ptr->CMD = I2C_CMD_CLEAR_FIFO; ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); ptr->CTRL = I2C_CTRL_PHASE_START_MASK @@ -401,14 +467,11 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { return status_timeout; } - ptr->STATUS |= I2C_STATUS_CMPL_MASK; - ptr->INTEN = 0; if (i2c_get_data_count(ptr)) { return status_i2c_transmit_not_completed; } - ptr->CMD = I2C_CMD_RESET; return stat; } @@ -422,7 +485,6 @@ hpm_stat_t i2c_init_slave(I2C_Type *ptr, uint32_t src_clk_in_hz, ptr->ADDR = I2C_ADDR_ADDR_SET(slave_address); - timing.t_sclratio = HPM_I2C_DRV_DEFAULT_SCL_RATIO; stat = i2c_configure_timing(src_clk_in_hz, config->i2c_mode, &timing); if (status_success != stat) { return stat; @@ -434,7 +496,7 @@ hpm_stat_t i2c_init_slave(I2C_Type *ptr, uint32_t src_clk_in_hz, | I2C_SETUP_T_SUDAT_SET(timing.t_sudat) | I2C_SETUP_T_HDDAT_SET(timing.t_hddat) | I2C_SETUP_T_SCLRADIO_SET(timing.t_sclratio - 1) - | I2C_SETUP_T_SCLHI_SET(MAX(timing.t_sclhi_min1, timing.t_sclhi_min2)) + | I2C_SETUP_T_SCLHI_SET(timing.t_sclhi) | I2C_SETUP_ADDRESSING_SET(config->is_10bit_addressing) | I2C_SETUP_IICEN_MASK; @@ -449,6 +511,20 @@ hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size) assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + retry = 0; + while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS |= I2C_STATUS_CMPL_MASK; + retry = 0; left = size; while (left) { @@ -478,8 +554,6 @@ hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size) if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { return status_timeout; } - /* clear status, CMPL must to be cleared at slave mode before next transaction */ - i2c_clear_status(ptr, ptr->STATUS); if (i2c_get_data_count(ptr) != size) { return status_i2c_transmit_not_completed; @@ -498,6 +572,20 @@ hpm_stat_t i2c_slave_read(I2C_Type *ptr, assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + retry = 0; + while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS |= I2C_STATUS_CMPL_MASK; + retry = 0; left = size; while (left) { @@ -527,8 +615,6 @@ hpm_stat_t i2c_slave_read(I2C_Type *ptr, if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { return status_timeout; } - /* clear status, CMPL must to be cleared at slave mode before next transaction */ - i2c_clear_status(ptr, ptr->STATUS); if (i2c_get_data_count(ptr) != size) { return status_i2c_transmit_not_completed; @@ -537,10 +623,24 @@ hpm_stat_t i2c_slave_read(I2C_Type *ptr, return status_success; } -void i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) +hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) { + uint32_t retry = 0; assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + i2c_ptr->STATUS |= I2C_STATUS_CMPL_MASK; + i2c_ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); i2c_ptr->CTRL = I2C_CTRL_PHASE_START_MASK | I2C_CTRL_PHASE_STOP_MASK @@ -552,12 +652,27 @@ void i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + return status_success; } -void i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) +hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) { + uint32_t retry = 0; assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + /* W1C, clear CMPL bit to avoid blocking the transmission */ + i2c_ptr->STATUS |= I2C_STATUS_CMPL_MASK; + i2c_ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); i2c_ptr->CTRL = I2C_CTRL_PHASE_START_MASK | I2C_CTRL_PHASE_STOP_MASK @@ -569,11 +684,60 @@ void i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + return status_success; } -void i2c_slave_dma_transfer(I2C_Type *i2c_ptr, uint32_t size) +hpm_stat_t i2c_slave_dma_transfer(I2C_Type *i2c_ptr, uint32_t size) { + uint32_t retry = 0; + assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + + while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + /* W1C, clear CMPL bit to avoid blocking the transmission */ + i2c_ptr->STATUS |= I2C_STATUS_CMPL_MASK; + i2c_ptr->CTRL |= I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; + + return status_success; +} + +hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size, bool read) +{ + uint32_t retry = 0; + assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + + while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + break; + } + retry++; + } + if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { + return status_timeout; + } + /* W1C, clear CMPL bit to avoid blocking the transmission */ + i2c_ptr->STATUS |= I2C_STATUS_CMPL_MASK; + i2c_ptr->CMD = I2C_CMD_CLEAR_FIFO; + i2c_ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); + i2c_ptr->CTRL = I2C_CTRL_PHASE_START_MASK + | I2C_CTRL_PHASE_STOP_MASK + | I2C_CTRL_PHASE_ADDR_MASK + | I2C_CTRL_PHASE_DATA_MASK + | I2C_CTRL_DIR_SET(read) + | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + + i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + return status_success; } diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c index 1bf65e24..3dfe9054 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -107,15 +107,27 @@ static void i2s_config_cfgr(I2S_Type *ptr, i2s_transfer_config_t *config) { i2s_gate_bclk(ptr); - ptr->CFGR = I2S_CFGR_BCLK_DIV_SET(bclk_div) - | I2S_CFGR_TDM_EN_SET(config->enable_tdm_mode) - | I2S_CFGR_CH_MAX_SET(config->channel_num_per_frame) - | I2S_CFGR_STD_SET(config->protocol) - | I2S_CFGR_DATSIZ_SET(I2S_CFGR_DATASIZ(config->audio_depth)) - | I2S_CFGR_CHSIZ_SET(I2S_CFGR_CHSIZ(config->channel_length)); + ptr->CFGR = (ptr->CFGR & ~(I2S_CFGR_BCLK_DIV_MASK | I2S_CFGR_TDM_EN_MASK | I2S_CFGR_CH_MAX_MASK | I2S_CFGR_STD_MASK | I2S_CFGR_DATSIZ_MASK | I2S_CFGR_CHSIZ_MASK)) + | I2S_CFGR_BCLK_DIV_SET(bclk_div) + | I2S_CFGR_TDM_EN_SET(config->enable_tdm_mode) + | I2S_CFGR_CH_MAX_SET(config->channel_num_per_frame) + | I2S_CFGR_STD_SET(config->protocol) + | I2S_CFGR_DATSIZ_SET(I2S_CFGR_DATASIZ(config->audio_depth)) + | I2S_CFGR_CHSIZ_SET(I2S_CFGR_CHSIZ(config->channel_length)); i2s_ungate_bclk(ptr); } +static void i2s_config_cfgr_slave(I2S_Type *ptr, + i2s_transfer_config_t *config) +{ + ptr->CFGR = (ptr->CFGR & ~(I2S_CFGR_TDM_EN_MASK | I2S_CFGR_CH_MAX_MASK | I2S_CFGR_STD_MASK | I2S_CFGR_DATSIZ_MASK | I2S_CFGR_CHSIZ_MASK)) + | I2S_CFGR_TDM_EN_SET(config->enable_tdm_mode) + | I2S_CFGR_CH_MAX_SET(config->channel_num_per_frame) + | I2S_CFGR_STD_SET(config->protocol) + | I2S_CFGR_DATSIZ_SET(I2S_CFGR_DATASIZ(config->audio_depth)) + | I2S_CFGR_CHSIZ_SET(I2S_CFGR_CHSIZ(config->channel_length)); +} + static bool i2s_calculate_bclk_divider(uint32_t mclk_in_hz, uint32_t bclk_in_hz, uint32_t *div_out) { uint32_t bclk_div; @@ -144,11 +156,8 @@ static bool i2s_calculate_bclk_divider(uint32_t mclk_in_hz, uint32_t bclk_in_hz, return true; } -hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +static hpm_stat_t _i2s_config_tx(I2S_Type *ptr, i2s_transfer_config_t *config) { - uint32_t bclk_in_hz; - uint32_t bclk_div; - /* channel_num_per_frame has to even. non TDM mode, it has be 2 */ if (!i2s_audio_depth_is_valid(config->audio_depth) || !i2s_channel_length_is_valid(config->channel_length) @@ -160,29 +169,18 @@ hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config return status_invalid_argument; } - bclk_in_hz = config->sample_rate * config->channel_length * config->channel_num_per_frame; - - if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { - return status_invalid_argument; - } - - i2s_disable(ptr); - i2s_config_cfgr(ptr, bclk_div, config); - if (config->channel_slot_mask) { ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; } ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_TX_EN_MASK)) | I2S_CTRL_TX_EN_SET(1 << config->data_line) | I2S_CTRL_I2S_EN_MASK; + return status_success; } -hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +static hpm_stat_t _i2s_config_rx(I2S_Type *ptr, i2s_transfer_config_t *config) { - uint32_t bclk_in_hz; - uint32_t bclk_div; - /* channel_num_per_frame has to even. non TDM mode, it has be 2 */ if (!i2s_audio_depth_is_valid(config->audio_depth) || !i2s_channel_length_is_valid(config->channel_length) @@ -194,28 +192,18 @@ hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config return status_invalid_argument; } - bclk_in_hz = config->sample_rate * config->channel_length * config->channel_num_per_frame; - if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { - return status_invalid_argument; - } - - i2s_disable(ptr); - i2s_config_cfgr(ptr, bclk_div, config); - if (config->channel_slot_mask) { ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; } ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_RX_EN_MASK)) | I2S_CTRL_RX_EN_SET(1 << config->data_line) | I2S_CTRL_I2S_EN_MASK; + return status_success; } -hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +static hpm_stat_t _i2s_config_transfer(I2S_Type *ptr, i2s_transfer_config_t *config) { - uint32_t bclk_in_hz; - uint32_t bclk_div; - /* channel_num_per_frame has to even. non TDM mode, it has be 2 */ if (!i2s_audio_depth_is_valid(config->audio_depth) || !i2s_channel_length_is_valid(config->channel_length) @@ -227,14 +215,6 @@ hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_ return status_invalid_argument; } - bclk_in_hz = config->sample_rate * config->channel_length * config->channel_num_per_frame; - if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { - return status_invalid_argument; - } - - i2s_disable(ptr); - i2s_config_cfgr(ptr, bclk_div, config); - if (config->channel_slot_mask) { /* Suppose RX and TX use same channel */ ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; @@ -250,9 +230,82 @@ hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_ | I2S_CTRL_RX_EN_SET(1 << config->data_line) | I2S_CTRL_TX_EN_SET(1 << config->data_line) | I2S_CTRL_I2S_EN_MASK; + return status_success; } +hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +{ + uint32_t bclk_in_hz; + uint32_t bclk_div; + + bclk_in_hz = config->sample_rate * config->channel_length * config->channel_num_per_frame; + if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { + return status_invalid_argument; + } + + i2s_disable(ptr); + i2s_config_cfgr(ptr, bclk_div, config); + + return _i2s_config_tx(ptr, config); +} + +hpm_stat_t i2s_config_tx_slave(I2S_Type *ptr, i2s_transfer_config_t *config) +{ + i2s_disable(ptr); + i2s_config_cfgr_slave(ptr, config); + + return _i2s_config_tx(ptr, config); +} + +hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +{ + uint32_t bclk_in_hz; + uint32_t bclk_div; + + bclk_in_hz = config->sample_rate * config->channel_length * config->channel_num_per_frame; + if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { + return status_invalid_argument; + } + + i2s_disable(ptr); + i2s_config_cfgr(ptr, bclk_div, config); + + return _i2s_config_rx(ptr, config); +} + +hpm_stat_t i2s_config_rx_slave(I2S_Type *ptr, i2s_transfer_config_t *config) +{ + i2s_disable(ptr); + i2s_config_cfgr_slave(ptr, config); + + return _i2s_config_rx(ptr, config); +} + +hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) +{ + uint32_t bclk_in_hz; + uint32_t bclk_div; + + bclk_in_hz = config->sample_rate * config->channel_length * config->channel_num_per_frame; + if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { + return status_invalid_argument; + } + + i2s_disable(ptr); + i2s_config_cfgr(ptr, bclk_div, config); + + return _i2s_config_transfer(ptr, config); +} + +hpm_stat_t i2s_config_transfer_slave(I2S_Type *ptr, i2s_transfer_config_t *config) +{ + i2s_disable(ptr); + i2s_config_cfgr_slave(ptr, config); + + return _i2s_config_transfer(ptr, config); +} + uint32_t i2s_send_buff(I2S_Type *ptr, uint8_t tx_line_index, uint8_t samplebits, uint8_t *src, uint32_t size) { uint32_t data; @@ -297,7 +350,7 @@ uint32_t i2s_receive_buff(I2S_Type *ptr, uint8_t rx_line_index, uint8_t samplebi uint8_t bytes = samplebits / 8U; if (!i2s_audio_depth_is_valid(samplebits)) { - return status_invalid_argument; + return 0; } if ((size % bytes) != 0) { diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c index aa601f2b..1b15b00a 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c @@ -23,6 +23,8 @@ static uint32_t lcdc_pixel_format(display_pixel_format_t format) return 7; case display_pixel_format_y8: return 0xb; + case display_pixel_format_raw8: + return 0xb; default: return 9; } diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c new file mode 100644 index 00000000..912d4e13 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c @@ -0,0 +1,357 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_lin_drv.h" + +#define HPM_LIN_DRV_RETRY_COUNT (50000U) + +hpm_stat_t lin_master_configure_timing(LIN_Type *ptr, lin_timing_t *timing) +{ + assert(timing->src_freq_in_hz >= 8000000U); + assert((timing->baudrate >= 1000U) && (timing->baudrate <= 20000U)); + + uint8_t prescaler, bt_mul; + uint16_t bt_div; + + /** set master mode */ + ptr->TV |= LIN_TV_MASTER_MODE_MASK; + ptr->TV |= LIN_TV_INITIAL_MODE_MASK; + ptr->TV &= ~LIN_TV_INITIAL_MODE_MASK; + + bt_mul = 20000U / timing->baudrate - 1U; + prescaler = log((timing->src_freq_in_hz / ((bt_mul + 1U) * timing->baudrate * 200U))) / log(2U) - 1U; + bt_div = timing->src_freq_in_hz / ((1U << (prescaler + 1U)) * (bt_mul + 1U) * timing->baudrate); + + if ((bt_div < 200) || (bt_div > 512)) { + return status_invalid_argument; + } + + /** src =20MHz baudrate = 19.2KHz */ + /** bt_div = 260, scaler = 1, bt_mul = 0 */ + ptr->BAUDRATE_CTL_LOW = bt_div & 0xFF; + ptr->BARDRATE_CTL_HIGH = LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SET(bt_div >> 8U) + | LIN_BARDRATE_CTL_HIGH_BT_MUL_SET(bt_mul) + | LIN_BARDRATE_CTL_HIGH_PRESCL_SET(prescaler); + + return status_success; +} + +hpm_stat_t lin_slave_configure_timing(LIN_Type *ptr, uint32_t src_freq_in_hz) +{ + assert(src_freq_in_hz >= 8000000U); + + uint8_t prescaler; + uint16_t bt_div; + + /** set slave mode */ + ptr->TV &= ~LIN_TV_MASTER_MODE_MASK; + ptr->TV |= LIN_TV_INITIAL_MODE_MASK; + ptr->TV &= ~LIN_TV_INITIAL_MODE_MASK; + + prescaler = log((src_freq_in_hz / (20000U * 200U))) / log(2U) - 1U; + bt_div = src_freq_in_hz / ((1U << (prescaler + 1U)) * 20000U); + + if ((bt_div < 200) || (bt_div > 512)) { + return status_invalid_argument; + } + + /** src = 20MHz, prescaler = 1, bt_div = 250 */ + ptr->BAUDRATE_CTL_LOW = bt_div & 0xFF; + ptr->BARDRATE_CTL_HIGH = LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SET(bt_div >> 8U) + | LIN_BARDRATE_CTL_HIGH_PRESCL_SET(prescaler); + + return status_success; +} + +uint8_t lin_get_data_length_from_id(uint8_t id) +{ + switch (LIN_ID_DATA_LEN_GET(id)) { + case id_data_length_2bytes: + return 2; + case id_data_length_2bytes_2: + return 2; + case id_data_length_4bytes: + return 4; + case id_data_length_8bytes: + return 8; + default: + return 8; + } +} + +uint8_t lin_get_data_length(LIN_Type *ptr) +{ + uint8_t data_length = 0; + if (((ptr->DATA_LEN) & LIN_DATA_LEN_DATA_LENGTH_MASK) == LIN_DATA_LEN_DATA_LENGTH_MASK) { + data_length = lin_get_data_length_from_id(ptr->ID); + } else { + data_length = LIN_DATA_LEN_DATA_LENGTH_GET(ptr->DATA_LEN); + } + return data_length; +} + +void lin_master_transfer(LIN_Type *ptr, lin_trans_config_t *config) +{ + uint8_t data_length; + + ptr->ID = config->id; + + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(ptr->ID); + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); + } + + /** sent or receive */ + ptr->CONTROL = 0U; + if (config->transmit) { + ptr->CONTROL = LIN_CONTROL_TRANSMIT_MASK; + } + + if (config->transmit) { + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATABYTE[i] = *((config->data_buff)++); + } + } + + /** start */ + ptr->CONTROL |= LIN_CONTROL_START_REQ_MASK; +} + +hpm_stat_t lin_master_sent(LIN_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length = 0; + + /** lin active */ + while (((ptr->STATE & LIN_STATE_LIN_ACTIVE_MASK) == LIN_STATE_LIN_ACTIVE_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + ptr->ID = config->id; + + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(ptr->ID); + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); + } + + ptr->CONTROL = LIN_CONTROL_TRANSMIT_MASK; + + /** load data into registers */ + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATABYTE[i] = *((config->data_buff)++); + } + + /** start */ + ptr->CONTROL |= LIN_CONTROL_START_REQ_MASK; + + /** lin complete */ + retry = 0; + while (!((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_timeout; + } + return status_success; +} + +hpm_stat_t lin_master_receive(LIN_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length; + + /** lin active */ + while (((ptr->STATE & LIN_STATE_LIN_ACTIVE_MASK) == LIN_STATE_LIN_ACTIVE_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + ptr->ID = config->id; + + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(ptr->ID); + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); + } + + /** receive */ + ptr->CONTROL = 0U; + /** start */ + ptr->CONTROL |= LIN_CONTROL_START_REQ_MASK; + + /** waiting for receive complete */ + retry = 0; + while (!((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_fail; + } + + /** load register data into buffer */ + for (uint8_t i = 0; i < data_length; i++) { + *((config->data_buff)++) = ptr->DATABYTE[i]; + } + + return status_success; +} + +void lin_slave_transfer(LIN_Type *ptr, lin_trans_config_t *config) +{ + uint8_t data_length; + + /** transmit or receive */ + ptr->CONTROL = LIN_CONTROL_TRANSMIT_SET(config->transmit); + + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(ptr->ID); + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); + } + + if (config->transmit) { + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATABYTE[i] = *((config->data_buff)++); + } + } + + /** data ack */ + ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; +} + +hpm_stat_t lin_slave_sent(LIN_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length; + + /** lin data_req */ + /** lin active? */ + while (((ptr->STATE & LIN_STATE_DATA_REQ_MASK) == LIN_STATE_DATA_REQ_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + /** transmit */ + ptr->CONTROL = LIN_CONTROL_TRANSMIT_MASK; + + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(ptr->ID); + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); + } + + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATABYTE[i] = *((config->data_buff)++); + } + + /** data ack */ + ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; + + /** lin complete */ + retry = 0; + while (!((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_timeout; + } + return status_success; +} + +hpm_stat_t lin_slave_receive(LIN_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length; + + /** lin data_req */ + while (((ptr->STATE & LIN_STATE_DATA_REQ_MASK) == LIN_STATE_DATA_REQ_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + /** receive */ + ptr->CONTROL = 0U; + + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(ptr->ID); + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); + } + + /** data ack */ + ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; + + /** lin complete */ + retry = 0; + while (!((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_timeout; + } + + for (uint8_t i = 0; i < data_length; i++) { + *((config->data_buff)++) = ptr->DATABYTE[i]; + } + + return status_success; +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c new file mode 100644 index 00000000..90e6d581 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c @@ -0,0 +1,1682 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_mcan_drv.h" +#include +#include + +#define MCAN_CAN_BAUDRATE_DEFAULT (500UL * 1000UL) /*!< Default CAN2.0 baudrate:500 kbps */ +#define MCAN_CANFD_BAUDRATE_DEFAULT (2UL * 1000UL * 1000UL) /*!< Default CANFD baudrate: 2 Mbps */ + +/*********************************************************************************************************************** + * + * Definitions + * + **********************************************************************************************************************/ +#define NUM_TQ_SYNC_SEG (1U) + +/** + * @brief CAN2.0 Timing related definitions + */ +#define TSEG1_MIN_FOR_CAN2_0 (2U) +#define TSEG1_MAX_FOR_CAN2_0 (256U) +#define TSEG2_MIN_FOR_CAN2_0 (2U) +#define TSEG2_MAX_FOR_CAN2_0 (128U) +#define TSJW_MIN_FOR_CAN2_0 (1U) +#define TSJW_MAX_FOR_CAN2_0 (128U) +#define PRESCALER_MIN_FOR_CAN2_0 (1U) +#define PRESCALER_MAX_FOR_CAN2_0 (512U) +#define NUM_TQ_MIN_FOR_CAN2_0 (8U) +#define NUM_TQ_MAX_FOR_CAN2_0 (TSEG1_MAX_FOR_CAN2_0 + TSEG2_MAX_FOR_CAN2_0) + +/** + * @brief CANFD Nominal Timing related definitions + */ +#define TSEG1_MIN_FOR_CANFD_NOMINAL (2U) +#define TSEG1_MAX_FOR_CANFD_NOMINAL (256U) +#define TSEG2_MIN_FOR_CANFD_NOMINAL (1U) +#define TSEG2_MAX_FOR_CANFD_NOMINAL (32U) +#define TSJW_MIN_FOR_CANFD_NOMINAL (1U) +#define TSJW_MAX_FOR_CANFD_NOMINAL (128U) +#define NUM_TQ_MIN_FOR_CANFD_NOMINAL (8U) +#define NUM_TQ_MAX_FOR_CANFD_NOMINAL (TSEG1_MAX_FOR_CANFD_NOMINAL + TSEG2_MAX_FOR_CANFD_NOMINAL) +#define PRESCALER_MIN_FOR_CANFD_NOMINAL (1U) +#define PRESCALER_MAX_FOR_CANFD_NOMINAL (512U) + +/** + * @brief CANFD Data Timing related definitions + */ +#define TSEG1_MIN_FOR_CANFD_DATA (2U) +#define TSEG1_MAX_FOR_CANFD_DATA (31U) +#define TSEG2_MIN_FOR_CANFD_DATA (0U) +#define TSEG2_MAX_FOR_CANFD_DATA (15U) +#define TSJW_MIN_FOR_CANFD_DATA (0U) +#define TSJW_MAX_FOR_CANFD_DATA (15U) +#define PRESCALER_MIN_FOR_CANFD_DATA (1U) +#define PRESCALER_MAX_FOR_CANFD_DATA (32U) + +#define NUM_TQ_MIN_FOR_CANFD_DATA (8U) +#define NUM_TQ_MAX_FOR_CANFD_DATA (TSEG1_MAX_FOR_CANFD_DATA + TSEG2_MAX_FOR_CANFD_DATA) + +#define MIN_TQ_MUL_PRESCALE (8U) +#define NUM_PRESCALE_MAX (256U) + +#define CAN_SAMPLEPOINT_MIN (750U) +#define CAN_SAMPLEPOINT_MAX (875U) + +/* Invalid start address of MCAN RAM */ +#define MCAN_RAM_ADDR_INVALID ((1UL << 16) - 1U) + +/* Maximum CAN TDC offset value */ +#define MCAN_MAX_TDC_OFFSET ((uint32_t)(MCAN_TDCR_TDCO_MASK >> MCAN_TDCR_TDCO_SHIFT)) + +/** + * @brief MCAN bit timing table + */ +typedef struct mcan_bit_timing_table_struct { + uint16_t tq_min; /*!< Minimum Tq */ + uint16_t tq_max; /*!< Maximum Tq */ + uint16_t seg1_min; /*!< Minimum TSEG1 */ + uint16_t seg1_max; /*!< Maximum TSEG1 */ + uint8_t seg2_min; /*!< Minimum TSEG2 */ + uint8_t seg2_max; /*!< Maximum TSEG2 */ + uint8_t sjw_min; /*!< Minimum SJW */ + uint8_t sjw_max; /*!< Maximum SJW */ + uint8_t min_diff_seg1_minus_seg2; /*!< Minimum value of (TSEG1 - TSEG2 ) */ + uint8_t prescaler_min; /*!< Minimum Prescaler value */ + uint16_t prescaler_max; /*!< Maximum Prescaler value */ +} mcan_bit_timing_table_t; + +/*********************************************************************************************************************** + * + * Variables + * + **********************************************************************************************************************/ +static const mcan_bit_timing_table_t k_mcan_bit_timing_tbl[3] = { + /* CAN2.0 bit timing requirement */ + { + /* TQ range */ + .tq_min = NUM_TQ_MIN_FOR_CAN2_0, .tq_max = NUM_TQ_MAX_FOR_CAN2_0, + /* SEG1 range(Including Sync_Seg + Prop_Seg + Phase_Seg1 */ + .seg1_min = TSEG1_MIN_FOR_CAN2_0, .seg1_max = TSEG1_MAX_FOR_CAN2_0, + /* SEG2 Range */ + .seg2_min = TSEG2_MIN_FOR_CAN2_0, .seg2_max = TSEG2_MAX_FOR_CAN2_0, + /* SJW range */ + .sjw_min = TSJW_MIN_FOR_CAN2_0, .sjw_max = TSJW_MAX_FOR_CAN2_0, .min_diff_seg1_minus_seg2 = 2, + /* Prescaler range */ + .prescaler_min = PRESCALER_MIN_FOR_CAN2_0, .prescaler_max = PRESCALER_MAX_FOR_CAN2_0, + }, + /* CANFD Nominal Bit timing requirement */ + { + /* TQ range */ + .tq_min = NUM_TQ_MIN_FOR_CANFD_NOMINAL, .tq_max = NUM_TQ_MAX_FOR_CANFD_NOMINAL, + /* SEG1 range(Including Sync_Seg + Prop_Seg + Phase_Seg1 */ + .seg1_min = TSEG1_MIN_FOR_CANFD_NOMINAL, .seg1_max = TSEG1_MAX_FOR_CANFD_NOMINAL, + /* SEG2 range */ + .seg2_min = TSEG2_MIN_FOR_CANFD_NOMINAL, .seg2_max = TSEG2_MAX_FOR_CANFD_NOMINAL, + /* SJW range */ + .sjw_min = TSJW_MIN_FOR_CANFD_NOMINAL, .sjw_max = TSJW_MAX_FOR_CANFD_NOMINAL, .min_diff_seg1_minus_seg2 = 2, + /* Prescaler range */ + .prescaler_min = PRESCALER_MIN_FOR_CANFD_NOMINAL, .prescaler_max = PRESCALER_MAX_FOR_CANFD_NOMINAL + }, + /* CANFD Data Bit timing requirement */ + { + /* TQ range */ + .tq_min = NUM_TQ_MIN_FOR_CANFD_DATA, .tq_max = NUM_TQ_MAX_FOR_CANFD_DATA, + /* SEG1 range(Including Sync_Seg + Prop_Seg + Phase_Seg2 */ + .seg1_min = TSEG1_MIN_FOR_CANFD_DATA, .seg1_max = TSEG1_MAX_FOR_CANFD_DATA, + /* SEG2 range */ + .seg2_min = TSEG2_MIN_FOR_CANFD_DATA, .seg2_max = TSEG2_MAX_FOR_CANFD_DATA, + /* SJW range */ + .sjw_min = TSJW_MIN_FOR_CANFD_DATA, .sjw_max = TSJW_MAX_FOR_CANFD_DATA, .min_diff_seg1_minus_seg2 = 1, + /* Prescaler range */ + .prescaler_min = PRESCALER_MIN_FOR_CANFD_DATA, .prescaler_max = PRESCALER_MAX_FOR_CANFD_DATA + }}; + +static const mcan_filter_elem_t k_default_std_id_filter = { + /* Use classic filter */ + .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, + /* Store message into RXFIFO0 if matching */ + .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, + /* For Standard Identify only */ + .can_id_type = MCAN_CAN_ID_TYPE_STANDARD, + /* Sync Message, only evaluated when "CCCR.UTSU" is set */ + .sync_message = 0U, + /* Don't care if mask is set to all 1s */ + .filter_id = 0U, + /* Accept all messages */ + .filter_mask = 0x7FFU, +}; + +static const mcan_filter_elem_t k_default_ext_id_filter = { + /* Use classic filter */ + .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, + /* Store message into RXFIFO0 if matching */ + .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, + /* For Standard Identify only */ + .can_id_type = MCAN_CAN_ID_TYPE_EXTENDED, + /* Sync Message, only evaluated when "CCCR.UTSU" is set */ + .sync_message = 0, + /* Don't care if mask is set to all 1s */ + .filter_id = 0, + /* Accept all messages */ + .filter_mask = 0x1FFFFFFFUL, +}; + +/*********************************************************************************************************************** + * + * Prototypes + * + **********************************************************************************************************************/ +/** + * @brief Set Nominal Bit timing + * + * @param [in] ptr MCAN base + * @param [in] bit_timing Bit timing parameter + */ +static void mcan_set_can_nominal_bit_timing(MCAN_Type *ptr, const mcan_bit_timing_param_t *bit_timing); + +/** + * @brief Set CANFD Data Bit timing + * + * @param [in] ptr MCAN base + * + * @param [in] bit_timing Bit timing parameter + */ +static void mcan_set_can_data_bit_timing(MCAN_Type *ptr, const mcan_bit_timing_param_t *bit_timing); + +/** + * @brief Calculate the closest prescaler + * + * @param [in] num_tq_mul_prescaler Number of TQ * Prescaler + * @param [in] start_prescaler Start of Prescaler value + * @param [in] max_tq Maximum Timing Quantum + * @param [in] min_tq Minimum Timing Quantum + * + * @return Calculated prescaler value + */ +static uint32_t mcan_calculate_closest_prescaler(uint32_t num_tq_mul_prescaler, + uint32_t start_prescaler, + uint32_t max_tq, + uint32_t min_tq); + +/** + * @brief Calculate Bit timing from baudrate + * + * @param [in] src_clk_freq CAN IP clock used for generating bit timing + * @param [in] option CAN bit timing option + * @param [in] baudrate CAN baudrate in bps + * @param [in] samplepoint_min Minimum sample point, value = actual sample point * 1000 + * @param [in] samplepoint_max Maximum sample point, value = actual sample point * 1000 + * @param [out] timing_param Calculated Bit timing parameter + * + * @retval status_success if no errors happened + * @retval status_invalid_argument if the timing parameters cannot be calculated from specified baudrate + */ +static hpm_stat_t mcan_calc_bit_timing_from_baudrate(uint32_t src_clk_freq, + mcan_bit_timing_option_t option, + uint32_t baudrate, + uint16_t samplepoint_min, + uint16_t samplepoint_max, + mcan_bit_timing_param_t *timing_param); + +/** + * @brief Set MCAN bit timing from Baudrate + * + * @param [in] ptr MCAN base + * @param [in] option MCAN bit timing option + * @param [in] src_clk_freq CAN IP clock used for generating bit timing + * @param [in] baudrate Baudrate in bps + * @param [in] samplepoint_min Minimum sample point, value = actual sample point * 1000 + * @param [in] samplepoint_max Maximum sample point, value = actual sample point * 1000 + * + * @retval status_success if no errors happened + * @retval status_invalid_argument if the timing parameters cannot be calculated from specified baudrate + */ +static hpm_stat_t mcan_set_bit_timing_from_baudrate(MCAN_Type *ptr, + mcan_bit_timing_option_t option, + uint32_t src_clk_freq, + uint32_t baudrate, + uint16_t samplepoint_min, + uint16_t samplepoint_max); + +/** + * @brief Configure MCAN TSU + * + * @param [in] ptr MCAN base + * @param [in] config TSU configuration + * @retval status_success if no errors happened + * + * @retval status_invalid_arugment if any parameters are invalid + */ +static hpm_stat_t mcan_set_tsu(MCAN_Type *ptr, mcan_tsu_config_t *config); + +/** + * @brief Configure MCAN internal timestamp + * + * @param [in] ptr MCAN base + * @param [in] config Internal Timestamp Configuratiojn + * @retval status_success if no errors happened + * + * @retval status_invalid_arugment if any parameters are invalid + */ +static hpm_stat_t mcan_set_internal_timestamp(MCAN_Type *ptr, mcan_internal_timestamp_config_t *config); +/*********************************************************************************************************************** + * + * Codes + */ +static void mcan_set_can_nominal_bit_timing(MCAN_Type *ptr, const mcan_bit_timing_param_t *bit_timing) +{ + ptr->NBTP = MCAN_NBTP_NBRP_SET(bit_timing->prescaler - 1U) | MCAN_NBTP_NTSEG1_SET(bit_timing->num_seg1 - 1U) | + MCAN_NBTP_NTSEG2_SET(bit_timing->num_seg2 - 1U) | MCAN_NBTP_NSJW_SET(bit_timing->num_sjw - 1U); +} +static void mcan_set_can_data_bit_timing(MCAN_Type *ptr, const mcan_bit_timing_param_t *bit_timing) +{ + ptr->DBTP = MCAN_DBTP_DBRP_SET(bit_timing->prescaler - 1U) | MCAN_DBTP_DTSEG1_SET(bit_timing->num_seg1 - 1U) | + MCAN_DBTP_DTSEG2_SET(bit_timing->num_seg2 - 1U) | MCAN_DBTP_DSJW_SET(bit_timing->num_sjw - 1U) | + MCAN_DBTP_TDC_SET((uint32_t) bit_timing->enable_tdc); +} + +static uint32_t mcan_calculate_closest_prescaler(uint32_t num_tq_mul_prescaler, + uint32_t start_prescaler, + uint32_t max_tq, + uint32_t min_tq) +{ + bool has_found = false; + + uint32_t prescaler = start_prescaler; + + while (!has_found) { + if ((num_tq_mul_prescaler / prescaler > max_tq) || (num_tq_mul_prescaler % prescaler != 0)) { + ++prescaler; + continue; + } else { + uint32_t tq = num_tq_mul_prescaler / prescaler; + if (tq * prescaler == num_tq_mul_prescaler) { + has_found = true; + break; + } else if (tq < min_tq) { + has_found = false; + break; + } else { + ++prescaler; + } + } + } + + return has_found ? prescaler : 0U; +} + +static hpm_stat_t mcan_calc_bit_timing_from_baudrate(uint32_t src_clk_freq, + mcan_bit_timing_option_t option, + uint32_t baudrate, + uint16_t samplepoint_min, + uint16_t samplepoint_max, + mcan_bit_timing_param_t *timing_param) +{ + hpm_stat_t status = status_invalid_argument; + do { + if ((option > mcan_bit_timing_canfd_data) || (baudrate == 0U) || + (src_clk_freq / baudrate < MIN_TQ_MUL_PRESCALE) || (timing_param == NULL)) { + break; + } + + const mcan_bit_timing_table_t *tbl = &k_mcan_bit_timing_tbl[(uint8_t) option]; + + /* According to the CAN specification 2.0, + * the Tq must be in range specified in the above CAN bit-timing table + */ + if (src_clk_freq / baudrate < tbl->tq_min) { + break; + } + + uint32_t num_tq_mul_prescaler = src_clk_freq / baudrate; + uint32_t start_prescaler = 1U; + uint32_t num_seg1, num_seg2; + bool has_found = false; + + /* Find out the minimum prescaler */ + uint32_t current_prescaler; + while (!has_found) { + current_prescaler = + mcan_calculate_closest_prescaler(num_tq_mul_prescaler, start_prescaler, tbl->tq_max, tbl->tq_min); + if ((current_prescaler < start_prescaler) || (current_prescaler > NUM_PRESCALE_MAX)) { + break; + } + uint32_t num_tq = num_tq_mul_prescaler / current_prescaler; + + num_seg2 = (num_tq - tbl->min_diff_seg1_minus_seg2) / 2U; + num_seg1 = num_tq - num_seg2; + while (num_seg2 > tbl->seg2_max) { + num_seg2--; + num_seg1++; + } + + /* Recommended sample point is 75% - 87.5% */ + while ((num_seg1 * 1000U) / num_tq < samplepoint_min) { + ++num_seg1; + --num_seg2; + } + + if ((num_seg1 * 1000U) / num_tq > samplepoint_max) { + break; + } + + if ((num_seg2 >= tbl->seg2_min) && (num_seg1 <= tbl->seg1_max)) { + has_found = true; + } else { + start_prescaler = current_prescaler + 1U; + } + } + + if (has_found) { + uint32_t num_sjw = MIN(tbl->sjw_max, num_seg2); + timing_param->num_seg1 = num_seg1 - NUM_TQ_SYNC_SEG; /* Should exclude the Sync_Reg */ + timing_param->num_seg2 = num_seg2; + timing_param->num_sjw = num_sjw; + timing_param->prescaler = current_prescaler; + status = status_success; + } + } while (false); + + return status; +} + +static hpm_stat_t mcan_set_bit_timing_from_baudrate(MCAN_Type *ptr, + mcan_bit_timing_option_t option, + uint32_t src_clk_freq, + uint32_t baudrate, + uint16_t samplepoint_min, + uint16_t samplepoint_max) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if (ptr == NULL) { + break; + } + + mcan_bit_timing_param_t timing_param = { 0 }; + status = mcan_calc_bit_timing_from_baudrate(src_clk_freq, + option, + baudrate, + samplepoint_min, + samplepoint_max, + &timing_param); + + if (status == status_success) { + if (option < mcan_bit_timing_canfd_data) { + mcan_set_can_nominal_bit_timing(ptr, &timing_param); + } else { + mcan_set_can_data_bit_timing(ptr, &timing_param); + } + status = status_success; + } + + } while (false); + + return status; +} + +void mcan_get_default_ram_config(MCAN_Type *ptr, mcan_ram_config_t *simple_config, bool enable_canfd) +{ + (void) memset(simple_config, 0, sizeof(mcan_ram_config_t)); + uint32_t start_addr = mcan_get_ram_offset(ptr); + + if (!enable_canfd) { + simple_config->enable_std_filter = true; + simple_config->std_filter_elem_count = MCAN_FILTER_SIZE_CAN_DEFAULT; + start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * MCAN_FILTER_SIZE_CAN_DEFAULT; + + simple_config->enable_ext_filter = true; + simple_config->ext_filter_elem_count = MCAN_FILTER_SIZE_CAN_DEFAULT; + start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * MCAN_FILTER_SIZE_CAN_DEFAULT; + + simple_config->enable_txbuf = true; + simple_config->txbuf_dedicated_txbuf_elem_count = MCAN_TXBUF_SIZE_CAN_DEFAULT / 2; + simple_config->txbuf_fifo_or_queue_elem_count = MCAN_TXBUF_SIZE_CAN_DEFAULT / 2; + simple_config->txfifo_or_txqueue_mode = MCAN_TXBUF_OPERATION_MODE_FIFO; + simple_config->txbuf_data_field_size = MCAN_DATA_FIELD_SIZE_8BYTES; + start_addr += MCAN_TXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + + for (uint32_t i = 0; i < ARRAY_SIZE(simple_config->rxfifos); i++) { + simple_config->rxfifos[i].enable = true; + simple_config->rxfifos[i].elem_count = MCAN_RXFIFO_SIZE_CAN_DEFAULT; + simple_config->rxfifos[i].operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; + simple_config->rxfifos[i].watermark = 1U; + simple_config->rxfifos[i].data_field_size = MCAN_DATA_FIELD_SIZE_8BYTES; + start_addr += MCAN_RXFIFO_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + } + simple_config->enable_rxbuf = true; + simple_config->rxbuf_elem_count = MCAN_RXBUF_SIZE_CAN_DEFAULT; + simple_config->rxbuf_data_field_size = MCAN_DATA_FIELD_SIZE_8BYTES; + start_addr += MCAN_RXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + } else { + simple_config->enable_std_filter = true; + simple_config->std_filter_elem_count = MCAN_FILTER_SIZE_CANFD_DEFAULT; + start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * MCAN_FILTER_SIZE_CANFD_DEFAULT; + + simple_config->enable_ext_filter = true; + simple_config->ext_filter_elem_count = MCAN_FILTER_SIZE_CANFD_DEFAULT; + start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * MCAN_FILTER_SIZE_CANFD_DEFAULT; + + simple_config->enable_txbuf = true; + simple_config->txbuf_dedicated_txbuf_elem_count = MCAN_TXBUF_SIZE_CANFD_DEFAULT / 2; + simple_config->txbuf_fifo_or_queue_elem_count = MCAN_TXBUF_SIZE_CANFD_DEFAULT / 2; + simple_config->txfifo_or_txqueue_mode = MCAN_TXBUF_OPERATION_MODE_FIFO; + simple_config->txbuf_data_field_size = MCAN_DATA_FIELD_SIZE_64BYTES; + start_addr += MCAN_TXBUF_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; + + for (uint32_t i = 0; i < ARRAY_SIZE(simple_config->rxfifos); i++) { + simple_config->rxfifos[i].enable = true; + simple_config->rxfifos[i].elem_count = MCAN_RXFIFO_SIZE_CANFD_DEFAULT; + simple_config->rxfifos[i].operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; + simple_config->rxfifos[i].watermark = 1U; + simple_config->rxfifos[i].data_field_size = MCAN_DATA_FIELD_SIZE_64BYTES; + start_addr += MCAN_RXFIFO_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; + } + simple_config->enable_rxbuf = true; + simple_config->rxbuf_elem_count = MCAN_RXBUF_SIZE_CANFD_DEFAULT; + simple_config->rxbuf_data_field_size = MCAN_DATA_FIELD_SIZE_64BYTES; + start_addr += MCAN_RXBUF_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; + } + simple_config->enable_tx_evt_fifo = true; + uint32_t tx_fifo_elem_count = + simple_config->txbuf_dedicated_txbuf_elem_count + simple_config->txbuf_fifo_or_queue_elem_count; + simple_config->tx_evt_fifo_elem_count = tx_fifo_elem_count; + simple_config->tx_evt_fifo_watermark = 1U; + + start_addr += MCAN_TXEVT_ELEM_SIZE * tx_fifo_elem_count; + + assert(start_addr <= mcan_get_ram_size(ptr)); +} + +void mcan_get_defaul_ram_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *ram_config, bool enable_canfd) +{ + (void) memset(ram_config, 0, sizeof(mcan_ram_config_t)); + uint32_t start_addr = mcan_get_ram_offset(ptr); + + if (!enable_canfd) { + ram_config->enable_std_filter = true; + ram_config->std_filter_config.list_start_addr = start_addr; + ram_config->std_filter_config.list_size = MCAN_FILTER_SIZE_CAN_DEFAULT; + start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * MCAN_FILTER_SIZE_CAN_DEFAULT; + + ram_config->enable_ext_filter = true; + ram_config->ext_filter_config.list_start_addr = start_addr; + ram_config->ext_filter_config.list_size = MCAN_FILTER_SIZE_CAN_DEFAULT; + start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * MCAN_FILTER_SIZE_CAN_DEFAULT; + + ram_config->enable_txbuf = true; + ram_config->txbuf_config.start_addr = start_addr; + ram_config->txbuf_config.dedicated_tx_buf_size = MCAN_TXBUF_SIZE_CAN_DEFAULT / 2; + ram_config->txbuf_config.fifo_queue_size = MCAN_TXBUF_SIZE_CAN_DEFAULT / 2; + ram_config->txbuf_config.tx_fifo_queue_mode = MCAN_TXBUF_OPERATION_MODE_FIFO; + ram_config->txbuf_elem_config.data_field_size = MCAN_DATA_FIELD_SIZE_8BYTES; + start_addr += MCAN_TXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + + ram_config->enable_rxfifo0 = true; + ram_config->rxfifo0_config.start_addr = start_addr; + ram_config->rxfifo0_config.fifo_size = MCAN_RXFIFO_SIZE_CAN_DEFAULT; + ram_config->rxfifo0_config.operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; + ram_config->rxfifo0_config.watermark = 1U; + start_addr += MCAN_RXFIFO_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + + ram_config->enable_rxfifo1 = true; + ram_config->rxfifo1_config.start_addr = start_addr; + ram_config->rxfifo1_config.fifo_size = MCAN_RXFIFO_SIZE_CAN_DEFAULT; + ram_config->rxfifo1_config.operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; + ram_config->rxfifo1_config.watermark = 1U; + start_addr += MCAN_RXFIFO_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + + ram_config->enable_rxbuf = true; + ram_config->rxbuf_config.start_addr = start_addr; + start_addr += MCAN_RXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + } else { + ram_config->enable_std_filter = true; + ram_config->std_filter_config.list_start_addr = start_addr; + ram_config->std_filter_config.list_size = MCAN_FILTER_SIZE_CANFD_DEFAULT; + start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * MCAN_FILTER_SIZE_CANFD_DEFAULT; + + ram_config->enable_ext_filter = true; + ram_config->ext_filter_config.list_start_addr = start_addr; + ram_config->ext_filter_config.list_size = MCAN_FILTER_SIZE_CANFD_DEFAULT; + start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * MCAN_FILTER_SIZE_CANFD_DEFAULT; + + ram_config->enable_txbuf = true; + ram_config->txbuf_config.start_addr = start_addr; + ram_config->txbuf_config.dedicated_tx_buf_size = MCAN_TXBUF_SIZE_CANFD_DEFAULT / 2; + ram_config->txbuf_config.fifo_queue_size = MCAN_TXBUF_SIZE_CANFD_DEFAULT / 2; + ram_config->txbuf_config.tx_fifo_queue_mode = MCAN_TXBUF_OPERATION_MODE_FIFO; + ram_config->txbuf_elem_config.data_field_size = MCAN_DATA_FIELD_SIZE_64BYTES; + start_addr += MCAN_TXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; + + ram_config->enable_rxfifo0 = true; + ram_config->rxfifo0_config.start_addr = start_addr; + ram_config->rxfifo0_config.fifo_size = MCAN_RXFIFO_SIZE_CANFD_DEFAULT; + ram_config->rxfifo0_config.operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; + ram_config->rxfifo0_config.watermark = 1U; + start_addr += MCAN_RXFIFO_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; + + ram_config->enable_rxfifo1 = true; + ram_config->rxfifo1_config.start_addr = start_addr; + ram_config->rxfifo1_config.fifo_size = MCAN_RXFIFO_SIZE_CANFD_DEFAULT; + ram_config->rxfifo1_config.operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; + ram_config->rxfifo1_config.watermark = 1U; + start_addr += MCAN_RXFIFO_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; + + ram_config->enable_rxbuf = true; + ram_config->rxbuf_config.start_addr = start_addr; + start_addr += MCAN_RXBUF_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; + } + ram_config->enable_tx_evt_fifo = true; + ram_config->tx_evt_fifo_config.start_addr = start_addr; + uint32_t tx_fifo_size = ram_config->txbuf_config.dedicated_tx_buf_size + ram_config->txbuf_config.fifo_queue_size; + ram_config->tx_evt_fifo_config.fifo_size = tx_fifo_size; + ram_config->tx_evt_fifo_config.fifo_watermark = 1U; + + start_addr += MCAN_TXEVT_ELEM_SIZE * tx_fifo_size; + + /* Ensure the requested MCAN RAM size is less than or equal to the total MCAN RAM size */ + assert((start_addr - mcan_get_ram_offset(ptr)) <= mcan_get_ram_size(ptr)); +} + +void mcan_get_default_config(MCAN_Type *ptr, mcan_config_t *config) +{ + (void) memset(config, 0, sizeof(mcan_config_t)); + config->baudrate = MCAN_CAN_BAUDRATE_DEFAULT; + config->baudrate_fd = MCAN_CANFD_BAUDRATE_DEFAULT; + config->can20_samplepoint_max = CAN_SAMPLEPOINT_MAX; + config->can20_samplepoint_min = CAN_SAMPLEPOINT_MIN; + config->canfd_samplepoint_max = CAN_SAMPLEPOINT_MAX; + config->canfd_samplepoint_min = CAN_SAMPLEPOINT_MIN; + + config->mode = mcan_mode_normal; + config->enable_canfd = false; + + /* Default Filter settings */ + mcan_all_filters_config_t *filters_config = &config->all_filters_config; + filters_config->global_filter_config.reject_remote_ext_frame = false; + filters_config->global_filter_config.reject_remote_std_frame = false; + filters_config->global_filter_config.accept_non_matching_std_frame_option = + MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + filters_config->global_filter_config.accept_non_matching_ext_frame_option = + MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; + filters_config->ext_id_mask = 0x1FFFFFFFUL; + filters_config->std_id_filter_list.filter_elem_list = &k_default_std_id_filter; + filters_config->std_id_filter_list.mcan_filter_elem_count = 1; + filters_config->ext_id_filter_list.filter_elem_list = &k_default_ext_id_filter; + filters_config->ext_id_filter_list.mcan_filter_elem_count = 1; + + /* Default MCAN RAM Configuration */ + mcan_ram_config_t *ram_config = &config->ram_config; + mcan_get_default_ram_config(ptr, ram_config, false); + + /* Default Internal Timestamp Configuration */ + mcan_internal_timestamp_config_t *ts_config = &config->timestamp_cfg; + ts_config->counter_prescaler = 1U; + ts_config->timestamp_selection = MCAN_TIMESTAMP_SEL_VALUE_ALWAYS_ZERO; + + /* Default TSU configuration */ + mcan_tsu_config_t *tsu_config = &config->tsu_config; + tsu_config->prescaler = 1U; + tsu_config->ext_timebase_src = MCAN_TSU_EXT_TIMEBASE_SRC_PTP; + tsu_config->use_ext_timebase = false; + tsu_config->capture_on_sof = false; + tsu_config->enable_tsu = false; +} + +static void mcan_config_rxfifo(MCAN_Type *ptr, uint32_t index, uint32_t reg_val) +{ + if (index == 0U) { + ptr->RXF0C = reg_val; + } else { + ptr->RXF1C = reg_val; + } +} + +hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + do { + uint32_t elem_bytes; + uint32_t elem_count; + uint32_t start_addr = mcan_get_ram_offset(ptr); + if (config->enable_std_filter) { + mcan_filter_config_t filter_config = { .reg_val = 0 }; + filter_config.list_size = config->std_filter_elem_count; + filter_config.list_start_addr = start_addr; + ptr->SIDFC = filter_config.reg_val; + start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * (uint32_t) config->std_filter_elem_count; + } else { + ptr->SIDFC = MCAN_RAM_ADDR_INVALID; + } + + if (config->enable_ext_filter) { + mcan_filter_config_t filter_config = { .reg_val = 0 }; + filter_config.list_size = config->ext_filter_elem_count; + filter_config.list_start_addr = start_addr; + ptr->XIDFC = filter_config.reg_val; + start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * (uint32_t) config->std_filter_elem_count; + } else { + ptr->XIDFC = MCAN_RAM_ADDR_INVALID; + } + + mcan_rx_fifo_or_buf_elem_config_t rx_fifo_buf_elem_config = { .reg_val = 0U }; + + for (uint32_t i = 0; i < ARRAY_SIZE(config->rxfifos); i++) { + if (config->rxfifos[i].enable) { + elem_bytes = + mcan_get_data_field_size(config->rxfifos[i].data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + elem_count = config->rxfifos[i].elem_count; + mcan_rxfifo_config_t rxfifo_config = { .reg_val = 0 }; + rxfifo_config.start_addr = start_addr; + rxfifo_config.watermark = 1U; + rxfifo_config.operation_mode = config->rxfifos[i].operation_mode; + rxfifo_config.fifo_size = elem_count; + mcan_config_rxfifo(ptr, i, rxfifo_config.reg_val); + + if (i == 0) { + rx_fifo_buf_elem_config.fifo0_data_field_size = config->rxfifos[i].data_field_size; + } else { + rx_fifo_buf_elem_config.fifo1_data_field_size = config->rxfifos[i].data_field_size; + } + + start_addr += elem_bytes * elem_count; + } else { + mcan_config_rxfifo(ptr, i, MCAN_RAM_ADDR_INVALID); + if (i == 0) { + rx_fifo_buf_elem_config.fifo0_data_field_size = 0; + } else { + rx_fifo_buf_elem_config.fifo1_data_field_size = 0; + } + } + } + + if (config->enable_rxbuf) { + elem_bytes = mcan_get_data_field_size(config->rxbuf_data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + elem_count = config->rxbuf_elem_count; + ptr->RXBC = start_addr; + rx_fifo_buf_elem_config.buf_data_field_size = config->rxbuf_data_field_size; + + start_addr += elem_bytes * elem_count;; + } else { + rx_fifo_buf_elem_config.buf_data_field_size = 0; + ptr->RXBC = MCAN_RAM_ADDR_INVALID; + } + ptr->RXESC = rx_fifo_buf_elem_config.reg_val; + + mcan_txbuf_config_t txbuf_config = { .reg_val = 0 }; + if (config->enable_txbuf) { + txbuf_config.start_addr = start_addr; + txbuf_config.fifo_queue_size = config->txbuf_fifo_or_queue_elem_count; + txbuf_config.dedicated_tx_buf_size = config->txbuf_dedicated_txbuf_elem_count; + txbuf_config.tx_fifo_queue_mode = config->txfifo_or_txqueue_mode; + + elem_count = config->txbuf_fifo_or_queue_elem_count + config->txbuf_dedicated_txbuf_elem_count; + elem_bytes = mcan_get_data_field_size(config->txbuf_data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + + start_addr += elem_count * elem_bytes; + ptr->TXESC = (uint32_t) config->txbuf_data_field_size; + } else { + ptr->TXESC = MCAN_RAM_ADDR_INVALID; + } + + ptr->TXBC = txbuf_config.reg_val; + + mcan_tx_evt_fifo_config_t txevt_fifo_config = { .reg_val = 0 }; + if (config->enable_tx_evt_fifo) { + elem_bytes = sizeof(mcan_tx_event_fifo_elem_t); + elem_count = config->tx_evt_fifo_elem_count; + txevt_fifo_config.start_addr = start_addr; + txevt_fifo_config.fifo_size = elem_count; + txevt_fifo_config.fifo_watermark = 1U; + ptr->TXEFC = txevt_fifo_config.reg_val; + + start_addr += elem_bytes * elem_count; + } else { + ptr->TXEFC = MCAN_RAM_ADDR_INVALID; + } + + /* Check whether the requested RAM space exceeds the valid RAM range */ + uint32_t requested_ram_size = start_addr - mcan_get_ram_offset(ptr); + if (requested_ram_size > mcan_get_ram_size(ptr)) { + status = status_mcan_ram_out_of_range; + break; + } + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + do { + if (config->enable_std_filter) { + ptr->SIDFC = config->std_filter_config.reg_val; + } else { + ptr->SIDFC = MCAN_RAM_ADDR_INVALID; + } + + if (config->enable_ext_filter) { + ptr->XIDFC = config->ext_filter_config.reg_val; + } else { + ptr->XIDFC = MCAN_RAM_ADDR_INVALID; + } + + if (config->enable_rxfifo0) { + ptr->RXF0C = config->rxfifo0_config.reg_val; + } else { + ptr->RXF0C = MCAN_RAM_ADDR_INVALID; + } + + if (config->enable_rxfifo1) { + ptr->RXF1C = config->rxfifo1_config.reg_val; + } else { + ptr->RXF1C = MCAN_RAM_ADDR_INVALID; + } + + if (config->enable_rxbuf) { + ptr->RXBC = config->rxbuf_config.start_addr; + } else { + ptr->RXBC = MCAN_RAM_ADDR_INVALID; + } + + ptr->RXESC = config->rx_elem_config.reg_val; + if (config->enable_txbuf) { + ptr->TXESC = config->txbuf_elem_config.data_field_size; + } else { + ptr->TXESC = MCAN_RAM_ADDR_INVALID; + } + + ptr->TXBC = config->txbuf_config.reg_val; + + if (config->enable_tx_evt_fifo) { + ptr->TXEFC = config->tx_evt_fifo_config.reg_val; + } else { + ptr->TXEFC = MCAN_RAM_ADDR_INVALID; + } + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_config_all_filters(MCAN_Type *ptr, mcan_all_filters_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (config == NULL)) { + break; + } + + ptr->XIDAM = config->ext_id_mask; + + ptr->GFC = MCAN_GFC_RRFE_SET(config->global_filter_config.reject_remote_ext_frame) | + MCAN_GFC_RRFS_SET(config->global_filter_config.reject_remote_std_frame) | + MCAN_GFC_ANFE_SET(config->global_filter_config.accept_non_matching_ext_frame_option) | + MCAN_GFC_ANFS_SET(config->global_filter_config.accept_non_matching_std_frame_option); + + uint32_t elem_count = 0; + const mcan_filter_elem_t *elem = NULL; + if (config->ext_id_filter_list.mcan_filter_elem_count > 0) { + elem_count = config->ext_id_filter_list.mcan_filter_elem_count; + elem = config->ext_id_filter_list.filter_elem_list; + for (uint32_t i = 0; i < elem_count; i++) { + if (elem->can_id_type != MCAN_CAN_ID_TYPE_EXTENDED) { + status = status_invalid_argument; + break; + } + status = mcan_set_filter_element(ptr, elem, i); + if (status != status_success) { + break; + } + ++elem; + } + if (status != status_success) { + break; + } + } + if (config->std_id_filter_list.mcan_filter_elem_count > 0) { + elem_count = config->std_id_filter_list.mcan_filter_elem_count; + elem = config->std_id_filter_list.filter_elem_list; + for (uint32_t i = 0; i < elem_count; i++) { + if (elem->can_id_type != MCAN_CAN_ID_TYPE_STANDARD) { + status = status_invalid_argument; + break; + } + status = mcan_set_filter_element(ptr, elem, i); + if (status != status_success) { + break; + } + ++elem; + } + if (status != status_success) { + break; + } + } + status = status_success; + + } while (false); + + return status; +} + +static hpm_stat_t mcan_set_tsu(MCAN_Type *ptr, mcan_tsu_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t tscfg = 0; + + if ((config->prescaler < 1U) || (config->prescaler > 256U) || + (config->ext_timebase_src > MCAN_TSU_EXT_TIMEBASE_SRC_MAX)) { + break; + } + + if (config->enable_tsu) { + tscfg |= MCAN_TSCFG_TSUE_MASK; + } + if (config->capture_on_sof) { + tscfg |= MCAN_TSCFG_SCP_MASK; + } + if (config->use_ext_timebase) { + tscfg |= MCAN_TSCFG_TBCS_MASK; + mcan_set_tsu_ext_timebase_src(ptr, config->ext_timebase_src); + } + if (config->enable_64bit_timestamp) { + tscfg |= MCAN_TSCFG_EN64_MASK; + } + + tscfg |= MCAN_TSCFG_TBPRE_SET(config->prescaler - 1U); + + ptr->TSCFG = tscfg; + + status = status_success; + } while (false); + + return status; +} + +static hpm_stat_t mcan_set_internal_timestamp(MCAN_Type *ptr, mcan_internal_timestamp_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((config->counter_prescaler < 1U) || (config->counter_prescaler > 16) || + (config->timestamp_selection > MCAN_TIMESTAMP_SEL_MAX)) { + break; + } + + ptr->TSCC = MCAN_TSCC_TCP_SET(config->counter_prescaler - 1U) | MCAN_TSCC_TSS_SET(config->timestamp_selection); + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_freq) +{ + hpm_stat_t status = status_invalid_argument; + do { + if ((ptr == NULL) || (config == NULL)) { + break; + } + + ptr->CCCR |= MCAN_CCCR_INIT_MASK; + while ((ptr->CCCR & MCAN_CCCR_INIT_MASK) == 0) { + + } + ptr->CCCR |= MCAN_CCCR_CCE_MASK; + + if (!config->use_lowlevel_timing_setting) { + if (config->enable_canfd) { + status = mcan_set_bit_timing_from_baudrate(ptr, + mcan_bit_timing_canfd_nominal, + src_clk_freq, + config->baudrate, + config->can20_samplepoint_min, + config->can20_samplepoint_max); + HPM_BREAK_IF(status != status_success); + status = mcan_set_bit_timing_from_baudrate(ptr, + mcan_bit_timing_canfd_data, + src_clk_freq, + config->baudrate_fd, + config->canfd_samplepoint_min, + config->canfd_samplepoint_max); + } else { + status = mcan_set_bit_timing_from_baudrate(ptr, + mcan_bit_timing_can2_0, + src_clk_freq, + config->baudrate, + config->can20_samplepoint_min, + config->can20_samplepoint_max); + } + HPM_BREAK_IF(status != status_success); + } else { + mcan_set_can_nominal_bit_timing(ptr, &config->can_timing); + if (config->enable_canfd) { + mcan_set_can_data_bit_timing(ptr, &config->canfd_timing); + } + } + + switch (config->mode) { + default: + case mcan_mode_normal: + ptr->CCCR &= ~(MCAN_CCCR_MON_MASK | MCAN_CCCR_TEST_MASK); + break; + case mcan_mode_loopback_internal: + ptr->CCCR |= MCAN_CCCR_MON_MASK | MCAN_CCCR_TEST_MASK; + ptr->TEST |= MCAN_TEST_LBCK_MASK; + break; + case mcan_mode_loopback_external: + ptr->CCCR |= MCAN_CCCR_TEST_MASK; + ptr->TEST |= MCAN_TEST_LBCK_MASK; + break; + case mcan_mode_listen_only: + ptr->CCCR |= MCAN_CCCR_MON_MASK; + break; + } + + if (config->enable_canfd) { + ptr->CCCR |= MCAN_CCCR_FDOE_MASK | MCAN_CCCR_BRSE_MASK; + } else { + ptr->CCCR &= ~(MCAN_CCCR_FDOE_MASK | MCAN_CCCR_BRSE_MASK); + } + if (config->enable_non_iso_mode) { + ptr->CCCR |= MCAN_CCCR_NISO_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_NISO_MASK; + } + + if (config->enable_transmit_pause) { + ptr->CCCR |= MCAN_CCCR_TXP_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_TXP_MASK; + } + + if (config->disable_protocol_exception_handling) { + ptr->CCCR |= MCAN_CCCR_PXHD_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_PXHD_MASK; + } + + if (config->enable_wide_message_marker) { + ptr->CCCR |= MCAN_CCCR_WMM_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_WMM_MASK; + } + + if (config->enable_edge_filtering) { + ptr->CCCR |= MCAN_CCCR_EFBI_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_EFBI_MASK; + } + + /* Configure Transmitter Delay Compensation */ + if (config->enable_tdc) { + ptr->DBTP |= MCAN_DBTP_TDC_MASK; + ptr->TDCR &= ~MCAN_TDCR_TDCO_MASK; + uint32_t data_seg1 = MCAN_DBTP_DTSEG1_GET(ptr->DBTP); + uint32_t prescaler = MCAN_DBTP_DSJW_GET(ptr->DBTP); + + uint32_t calc_val = (data_seg1 + 2U) * (prescaler + 1U); + if (calc_val < MCAN_MAX_TDC_OFFSET) { + ptr->TDCR |= MCAN_TDCR_TDCO_SET(calc_val); + } else { + ptr->TDCR |= MCAN_TDCR_TDCO_SET(MCAN_MAX_TDC_OFFSET); + } + } else { + ptr->DBTP &= ~MCAN_DBTP_TDC_MASK; + } + + /* Configure TSU */ + if (config->use_timestamping_unit) { + ptr->CCCR |= MCAN_CCCR_UTSU_MASK; + status = mcan_set_tsu(ptr, &config->tsu_config); + HPM_BREAK_IF(status != status_success); + } else { + ptr->CCCR &= ~MCAN_CCCR_UTSU_MASK; + } + + /* Configure Internal Timestamp */ + status = mcan_set_internal_timestamp(ptr, &config->timestamp_cfg); + HPM_BREAK_IF(status != status_success); + + /* Initialize CAN RAM */ + uint32_t can_ram_size = mcan_get_ram_size(ptr); + uint32_t *ram_base = (uint32_t *) mcan_get_ram_base(ptr); + for (uint32_t i = 0U; i < can_ram_size / sizeof(uint32_t); i++) { + ram_base[i] = 0UL; + } + status = mcan_config_ram(ptr, &config->ram_config); + HPM_BREAK_IF(status != status_success); + + /* Configure Filters */ + status = mcan_config_all_filters(ptr, &config->all_filters_config); + HPM_BREAK_IF(status != status_success); + + /* Clear all Interrupt Flags */ + mcan_clear_interrupt_flags(ptr, ~0UL); + + ptr->CCCR &= ~MCAN_CCCR_INIT_MASK; + while ((ptr->CCCR & MCAN_CCCR_INIT_MASK) != 0U) { + } + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_set_filter_element(MCAN_Type *ptr, const mcan_filter_elem_t *filter_elem, uint32_t index) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (filter_elem == NULL)) { + break; + } + bool is_ext_id = (filter_elem->can_id_type == MCAN_CAN_ID_TYPE_EXTENDED); + + uint32_t ram_offset; + uint32_t filter_elem_size; + uint32_t size_max; + if (is_ext_id) { + ram_offset = MCAN_XIDFC_FLESA_GET(ptr->XIDFC) << MCAN_XIDFC_FLESA_SHIFT; + filter_elem_size = MCAN_FILTER_ELEM_EXT_ID_SIZE; + size_max = MCAN_XIDFC_LSE_GET(ptr->XIDFC); + } else { + ram_offset = MCAN_SIDFC_FLSSA_GET(ptr->SIDFC) << MCAN_SIDFC_FLSSA_SHIFT; + filter_elem_size = MCAN_FILTER_ELEM_STD_ID_SIZE; + size_max = MCAN_SIDFC_LSS_GET(ptr->SIDFC); + } + + if (index >= size_max) { + status = status_mcan_filter_index_out_of_range; + break; + } + + volatile uint32_t *config_start; + config_start = (volatile uint32_t *) (mcan_get_ram_base(ptr) + ram_offset + filter_elem_size * index); + + uint32_t config_words[2] = { 0, 0 }; + if (is_ext_id) { + /* EFEC + EFID1 */ + config_words[0] = ((uint32_t) (filter_elem->filter_config) << 29) | filter_elem->id1; + + /* EFT + ESYNC + EFFID2 */ + config_words[1] = filter_elem->id2; + config_words[1] |= (filter_elem->sync_message != 0) ? (1UL << 29) : 0; + config_words[1] |= ((uint32_t) filter_elem->filter_type) << 30; + + config_start[0] = config_words[0]; + config_start[1] = config_words[1]; + } else { + config_words[0] = (filter_elem->id2 & 0x7FFUL) | ((filter_elem->id1 & 0x7FFU) << 16); + config_words[0] |= (filter_elem->sync_message != 0) ? (1UL << 15) : 0; + config_words[0] |= ((uint32_t) filter_elem->filter_config) << 27; + config_words[0] |= ((uint32_t) filter_elem->filter_type) << 30; + + config_start[0] = config_words[0]; + } + + status = status_success; + + } while (false); + + return status; +} + +static uint32_t mcan_get_rxfifo0_base(MCAN_Type *ptr) +{ + uint32_t rxfifo0_buf_offset = MCAN_RXF0C_F0SA_GET(ptr->RXF0C) << 2; + uint32_t fifo_addr_base = mcan_get_ram_base(ptr) + rxfifo0_buf_offset; + return fifo_addr_base; +} + +static uint32_t mcan_get_rxfifo1_base(MCAN_Type *ptr) +{ + uint32_t rxfifo1_buf_offset = MCAN_RXF1C_F1SA_GET(ptr->RXF1C) << 2; + uint32_t fifo_addr_base = mcan_get_ram_base(ptr) + rxfifo1_buf_offset; + return fifo_addr_base; +} + +static uint32_t mcan_get_rxbuf_elem_addr(MCAN_Type *ptr, uint32_t index) +{ + uint32_t elem_size; + uint32_t elem_size_option = MCAN_RXESC_RBDS_GET(ptr->RXESC); + if (elem_size_option < 5U) { + elem_size = 8U + 4U * elem_size_option; + } else { + elem_size = 32U + (elem_size_option - 5U) * 16U; + } + elem_size += MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + + uint32_t rxbuf_offset = MCAN_RXBC_RBSA_GET(ptr->RXBC) << MCAN_RXBC_RBSA_SHIFT; + + uint32_t rxbuf_addr_base = mcan_get_ram_base(ptr) + rxbuf_offset; + + uint32_t elem_addr = rxbuf_addr_base + elem_size * index; + + return elem_addr; +} + +static uint32_t mcan_get_txbuf_elem_addr(MCAN_Type *ptr, uint32_t index) +{ + uint32_t elem_size; + uint32_t elem_size_option = MCAN_TXESC_TBDS_GET(ptr->TXESC); + if (elem_size_option < 5U) { + elem_size = 8U + 4U * elem_size_option; + } else { + elem_size = 32U + (elem_size_option - 5U) * 16U; + } + elem_size += MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + + uint32_t txbuf_offset = MCAN_TXBC_TBSA_GET(ptr->TXBC) << MCAN_TXBC_TBSA_SHIFT; + + uint32_t txbuf_addr_base = mcan_get_ram_base(ptr) + txbuf_offset; + + uint32_t elem_addr = txbuf_addr_base + elem_size * index; + + return elem_addr; +} + +uint8_t mcan_get_message_size_from_dlc(uint8_t dlc) +{ + uint32_t msg_size; + if (dlc <= 8U) { + msg_size = dlc; + } else if (dlc <= 12U) { + msg_size = 8 + (dlc - 8) * 4; + } else { + msg_size = 32 + (dlc - 13) * 16U; + } + return msg_size; +} + +uint8_t mcan_get_data_field_size(uint8_t data_field_size_option) +{ + uint8_t size_in_bytes = 0; + + switch (data_field_size_option) { + case MCAN_DATA_FIELD_SIZE_8BYTES: + size_in_bytes = 8U; + break; + case MCAN_DATA_FIELD_SIZE_12BYTES: + size_in_bytes = 12U; + break; + case MCAN_DATA_FIELD_SIZE_16BYTES: + size_in_bytes = 16U; + break; + case MCAN_DATA_FIELD_SIZE_20BYTES: + size_in_bytes = 20U; + break; + case MCAN_DATA_FIELD_SIZE_24BYTES: + size_in_bytes = 24U; + break; + case MCAN_DATA_FIELD_SIZE_32BYTES: + size_in_bytes = 32U; + break; + case MCAN_DATA_FIELD_SIZE_48BYTES: + size_in_bytes = 48U; + break; + case MCAN_DATA_FIELD_SIZE_64BYTES: + size_in_bytes = 64U; + break; + default: + /* Invalid option */ + break; + } + return size_in_bytes; +} + +hpm_stat_t mcan_write_txbuf(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (tx_frame == NULL)) { + break; + } + + uint32_t txbuf_index_max = MCAN_TXBC_NDTB_GET(ptr->TXBC); + if (index >= txbuf_index_max) { + status = status_mcan_txbuf_index_out_of_range; + break; + } + + if (!mcan_is_transmit_request_pending(ptr, index)) { + uint32_t *msg_hdr = (uint32_t *) mcan_get_txbuf_elem_addr(ptr, index); + uint32_t *msg_data = msg_hdr + 2; + uint8_t msg_size_words = (mcan_get_message_size_from_dlc(tx_frame->dlc) + 3U) / sizeof(uint32_t); + uint32_t *tx_frame_u32 = (uint32_t *) tx_frame; + msg_hdr[0] = tx_frame_u32[0]; + msg_hdr[1] = tx_frame_u32[1]; + + for (uint32_t i = 0; i < msg_size_words; i++) { + msg_data[i] = tx_frame->data_32[i]; + } + + status = status_success; + } else { + status = status_fail; + } + } while (false); + + return status; +} + +hpm_stat_t mcan_write_txfifo(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (tx_frame == NULL)) { + break; + } + if (!mcan_is_txfifo_full(ptr)) { + uint32_t put_index = mcan_get_txfifo_put_index(ptr); + uint32_t *msg_hdr = (uint32_t *) mcan_get_txbuf_elem_addr(ptr, put_index); + uint32_t *msg_data = msg_hdr + 2; + uint8_t msg_size_words = (mcan_get_message_size_from_dlc(tx_frame->dlc) + 3U) / sizeof(uint32_t); + uint32_t *tx_frame_u32 = (uint32_t *) tx_frame; + msg_hdr[0] = tx_frame_u32[0]; + msg_hdr[1] = tx_frame_u32[1]; + + for (uint32_t i = 0; i < msg_size_words; i++) { + msg_data[i] = tx_frame->data_32[i]; + } + status = status_success; + } else { + status = status_mcan_txfifo_full; + } + } while (false); + + return status; +} + +hpm_stat_t mcan_read_rxbuf(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (rx_frame == NULL)) { + break; + } + + if (!mcan_is_rxbuf_data_available(ptr, index)) { + status = status_mcan_rxbuf_empty; + break; + } + + uint32_t *msg_hdr = (uint32_t *) mcan_get_rxbuf_elem_addr(ptr, index); + uint32_t *msg_data = msg_hdr + 2; + uint32_t *rx_frame_u32 = (uint32_t *) rx_frame; + rx_frame_u32[0] = msg_hdr[0]; + rx_frame_u32[1] = msg_hdr[1]; + uint8_t msg_size_words = (mcan_get_message_size_from_dlc(rx_frame->dlc) + 3) / 4; + for (uint32_t i = 0; i < msg_size_words; i++) { + rx_frame->data_32[i] = msg_data[i]; + } + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_read_rxfifo(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (rx_frame == NULL)) { + break; + } + + uint32_t base_addr; + uint32_t elem_index; + uint32_t elem_size; + uint32_t elem_size_option; + if (fifo_index == 0) { + uint32_t rxf0s = ptr->RXF0S; + if (MCAN_RXF0S_F0FL_GET(rxf0s) == 0) { + status = status_mcan_rxfifo_empty; + break; + } + base_addr = mcan_get_rxfifo0_base(ptr); + elem_size_option = MCAN_RXESC_F0DS_GET(ptr->RXESC); + elem_index = MCAN_RXF0S_F0GI_GET(rxf0s); + } else { + uint32_t rxf1s = ptr->RXF1S; + if (MCAN_RXF1S_F1FL_GET(rxf1s) == 0) { + status = status_mcan_rxfifo_empty; + break; + } + base_addr = mcan_get_rxfifo1_base(ptr); + elem_size_option = MCAN_RXESC_F1DS_GET(ptr->RXESC); + elem_index = MCAN_RXF1S_F1GI_GET(rxf1s); + } + + + if (elem_size_option < 5U) { + elem_size = 8U + 4U * elem_size_option; + } else { + elem_size = 32U + (elem_size_option - 5U) * 16U; + } + elem_size += MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + + uint32_t elem_addr = base_addr + elem_size * elem_index; + uint32_t *msg_hdr = (uint32_t *) elem_addr; + uint32_t *msg_data = msg_hdr + 2; + uint32_t *rx_frame_u32 = (uint32_t *) rx_frame; + rx_frame_u32[0] = msg_hdr[0]; + rx_frame_u32[1] = msg_hdr[1]; + uint8_t msg_size_words = (mcan_get_message_size_from_dlc(rx_frame->dlc) + 3) / 4; + for (uint32_t i = 0; i < msg_size_words; i++) { + rx_frame->data_32[i] = msg_data[i]; + } + + if (fifo_index == 0) { + ptr->RXF0A = MCAN_RXF0S_F0GI_GET(ptr->RXF0S); + } else { + ptr->RXF1A = MCAN_RXF1S_F1GI_GET(ptr->RXF1S); + } + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_read_tx_evt_fifo(MCAN_Type *ptr, mcan_tx_event_fifo_elem_t *tx_evt) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (tx_evt == NULL)) { + break; + } + + uint32_t txefs = ptr->TXEFS; + + if (MCAN_TXEFS_EFFL_GET(txefs) == 0U) { + status = status_mcan_tx_evt_fifo_empty; + break; + } + + uint32_t base_addr = mcan_get_ram_base(ptr) + (MCAN_TXEFC_EFSA_GET(ptr->TXEFC) << MCAN_TXEFC_EFSA_SHIFT); + uint32_t elem_size = sizeof(mcan_tx_event_fifo_elem_t); + uint32_t elem_index = MCAN_TXEFS_EFGI_GET(txefs); + + uint32_t elem_addr = base_addr + elem_size * elem_index; + uint32_t *tx_evt_buf = (uint32_t *) elem_addr; + + tx_evt->words[0] = tx_evt_buf[0]; + tx_evt->words[1] = tx_evt_buf[1]; + + ptr->TXEFA = MCAN_TXEFA_EFAI_SET(elem_index); + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_transmit_via_txbuf_nonblocking(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame) +{ + hpm_stat_t status = status_invalid_argument; + do { + if ((ptr == NULL) || (tx_frame == NULL)) { + break; + } + + status = mcan_write_txbuf(ptr, index, tx_frame); + HPM_BREAK_IF(status != status_success); + + mcan_send_add_request(ptr, index); + status = status_success; + + } while (false); + return status; +} + +hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame) +{ + hpm_stat_t status = status_invalid_argument; + do { + if ((ptr == NULL) || (tx_frame == NULL)) { + break; + } + if (mcan_is_txfifo_full(ptr)) { + status = status_mcan_txfifo_full; + break; + } + + status = mcan_write_txfifo(ptr, tx_frame); + HPM_BREAK_IF(status != status_success); + + uint32_t put_index = mcan_get_txfifo_put_index(ptr); + mcan_send_add_request(ptr, put_index); + + uint32_t retry_cnt = 0; + while (!mcan_is_transmit_occurred(ptr, put_index)) { + retry_cnt++; + if (retry_cnt >= MCAN_TX_RETRY_COUNT_MAX) { + break; + } + } + if (retry_cnt >= MCAN_TX_RETRY_COUNT_MAX) { + status = status_timeout; + } else { + status = status_success; + } + } while (false); + return status; +} + +hpm_stat_t mcan_receive_from_buf_blocking(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t retry_cnt = 0; + + while (!mcan_is_rxbuf_data_available(ptr, index)) { + retry_cnt++; + if (retry_cnt >= MCAN_RX_RETRY_COUNT_MAX) { + status = status_timeout; + break; + } + } + if (status == status_timeout) { + break; + } + + mcan_clear_rxbuf_data_available_flag(ptr, index); + status = mcan_read_rxbuf(ptr, index, rx_frame); + } while (false); + + return status; +} + +hpm_stat_t mcan_receive_from_fifo_blocking(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t retry_cnt = 0; + uint32_t interrupt_flag = (fifo_index == 0U) ? MCAN_IR_RF0N_MASK : MCAN_IR_RF1N_MASK; + + while (!mcan_is_interrupt_flag_set(ptr, interrupt_flag)) { + retry_cnt++; + if (retry_cnt >= MCAN_RX_RETRY_COUNT_MAX) { + status = status_timeout; + break; + } + } + if (status == status_timeout) { + break; + } + + mcan_clear_interrupt_flags(ptr, interrupt_flag); + status = mcan_read_rxfifo(ptr, fifo_index, rx_frame); + } while (false); + + return status; +} + +void mcan_get_high_priority_message_status(MCAN_Type *ptr, mcan_high_priority_message_status_t *status) +{ + uint32_t hpms = ptr->HPMS; + status->buffer_index = MCAN_HPMS_BIDX_GET(hpms); + status->filter_index = MCAN_HPMS_FIDX_GET(hpms); + status->filter_list_type = MCAN_HPMS_FLST_GET(hpms); + status->message_storage_indicator = MCAN_HPMS_MSI_GET(hpms); +} + +hpm_stat_t mcan_set_global_filter_config(MCAN_Type *ptr, mcan_global_filter_config_t *filter_config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (filter_config == NULL)) { + break; + } + + ptr->GFC = MCAN_GFC_ANFE_SET(filter_config->accept_non_matching_ext_frame_option) | + MCAN_GFC_ANFS_SET(filter_config->accept_non_matching_std_frame_option) | + MCAN_GFC_RRFS_SET(filter_config->reject_remote_std_frame) | + MCAN_GFC_RRFE_SET(filter_config->reject_remote_ext_frame); + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t mcan_config_transmitter_delay_compensation(MCAN_Type *ptr, mcan_tdc_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (config == NULL)) { + break; + } + + ptr->TDCR = MCAN_TDCR_TDCO_SET(config->ssp_offset) | MCAN_TDCR_TDCF_SET(config->filter_window_length); + status = status_success; + + } while (false); + return status; +} + +uint32_t mcan_read_32bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index) +{ + uint32_t ts_val = 0U; + if (index < ARRAY_SIZE(ptr->TS_SEL)) { + ts_val = ptr->TS_SEL[index]; + } + return ts_val; +} + +uint64_t mcan_read_64bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index) +{ + uint64_t ts_val = 0U; + uint32_t real_index = index & 0x7U; /* Clear bit3 according to IP design */ + if (index < ARRAY_SIZE(ptr->TS_SEL)) { + ts_val = ((uint64_t) (ptr->TS_SEL[2U * real_index + 1]) << 32U); + ts_val |= ptr->TS_SEL[2U * real_index]; + /* Workaround: dummy read to clear the corresponding bits in TSS1 if the index is equal to/greater than 8 */ + if (index >= 8U) { + (void) ptr->TS_SEL[index]; + } + } + + return ts_val; +} + +hpm_stat_t mcan_get_timestamp_from_tx_event(MCAN_Type *ptr, + const mcan_tx_event_fifo_elem_t *tx_evt, + mcan_timestamp_value_t *timestamp) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF((ptr == NULL) || (tx_evt == NULL) || (timestamp == NULL)); + + (void) memset(timestamp, 0, sizeof(mcan_timestamp_value_t)); + + bool is_tsu_used = mcan_is_tsu_used(ptr); + if (!is_tsu_used) { + timestamp->is_16bit = true; + timestamp->ts_16bit = tx_evt->tx_timestamp; + } else if (tx_evt->tx_timestamp_captured != 0U) { + bool is_64bit_ts = mcan_is_64bit_tsu_timestamp_used(ptr); + uint32_t ts_index = tx_evt->tx_timestamp_pointer; + if (!is_64bit_ts) { + timestamp->is_32bit = true; + timestamp->ts_32bit = mcan_read_32bit_tsu_timestamp(ptr, ts_index); + } else { + timestamp->is_64bit = true; + timestamp->ts_64bit = mcan_read_64bit_tsu_timestamp(ptr, ts_index); + } + status = status_success; + } else { + status = status_mcan_timestamp_not_exist; + } + + } while (false); + + return status; +} + +hpm_stat_t mcan_get_timestamp_from_received_message(MCAN_Type *ptr, + const mcan_rx_message_t *rx_msg, + mcan_timestamp_value_t *timestamp) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF((ptr == NULL) || (rx_msg == NULL) || (timestamp == NULL)); + + (void) memset(timestamp, 0, sizeof(mcan_timestamp_value_t)); + + bool is_tsu_used = mcan_is_tsu_used(ptr); + if (!is_tsu_used) { + timestamp->is_16bit = true; + timestamp->ts_16bit = rx_msg->rx_timestamp; + } else if (rx_msg->rx_timestamp_captured != 0U) { + bool is_64bit_ts = mcan_is_64bit_tsu_timestamp_used(ptr); + uint32_t ts_index = rx_msg->rx_timestamp_pointer; + if (!is_64bit_ts) { + timestamp->is_32bit = true; + timestamp->ts_32bit = mcan_read_32bit_tsu_timestamp(ptr, ts_index); + } else { + timestamp->is_64bit = true; + timestamp->ts_64bit = mcan_read_64bit_tsu_timestamp(ptr, ts_index); + } + status = status_success; + } else { + status = status_mcan_timestamp_not_exist; + } + } while (false); + + return status; +} diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c new file mode 100644 index 00000000..13896ad7 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_soc_feature.h" +#include "hpm_pla_drv.h" + +void pla_set_aoi_16to8_one_channel(PLA_Type *pla, + pla_aoi_16to8_chn_cfg_t *cfg) +{ + uint8_t i; + uint32_t value; + + value = 0; + for (i = 0; i < PLA_AOI_16TO8_SIGNAL_NUM; i++) { + value |= ((uint32_t)cfg->input[i].op) << (cfg->input[i].signal << 1); + } + pla->CHN[cfg->chn].AOI_16TO8[cfg->aoi_16to8_chn] = value; +} + +void pla_get_aoi_16to8_one_channel(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_16to8_channel_type_t aoi_16to8_chn, + pla_aoi_16to8_chn_cfg_t *cfg) +{ + uint8_t i; + + for (i = 0; i < PLA_AOI_16TO8_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] >> (i << 1)) & 0x03; + } +} + +void pla_set_aoi_8to7_one_channel(PLA_Type *pla, + pla_aoi_8to7_chn_cfg_t *cfg) +{ + uint8_t i; + uint32_t value; + + value = 0; + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + value |= ((uint32_t)cfg->input[i].op) << (cfg->input[i].signal << 1); + } + switch (cfg->aoi_8to7_chn) { + case pla_aoi_8to7_chn_0: + pla->CHN[cfg->chn].AOI_8TO7_00_01 = (pla->CHN[cfg->chn].AOI_8TO7_00_01 & 0xffff0000) | value; + break; + case pla_aoi_8to7_chn_1: + pla->CHN[cfg->chn].AOI_8TO7_00_01 = (pla->CHN[cfg->chn].AOI_8TO7_00_01 & 0x0000ffff) | (value << 16); + break; + case pla_aoi_8to7_chn_2: + pla->CHN[cfg->chn].AOI_8TO7_02_03 = (pla->CHN[cfg->chn].AOI_8TO7_02_03 & 0xffff0000) | value; + break; + case pla_aoi_8to7_chn_3: + pla->CHN[cfg->chn].AOI_8TO7_02_03 = (pla->CHN[cfg->chn].AOI_8TO7_02_03 & 0x0000ffff) | (value << 16); + break; + case pla_aoi_8to7_chn_4: + pla->CHN[cfg->chn].AOI_8TO7_04_05 = (pla->CHN[cfg->chn].AOI_8TO7_04_05 & 0xffff0000) | value; + break; + case pla_aoi_8to7_chn_5: + pla->CHN[cfg->chn].AOI_8TO7_04_05 = (pla->CHN[cfg->chn].AOI_8TO7_04_05 & 0x0000ffff) | (value << 16); + break; + case pla_aoi_8to7_chn_6: + pla->CHN[cfg->chn].AOI_8TO7_06 = value; + break; + default: + break; + } +} + +void pla_get_aoi_8to7_one_channel(PLA_Type *pla, + pla_aoi_8to7_chn_cfg_t *cfg) +{ + uint8_t i; + + switch (cfg->aoi_8to7_chn) { + case pla_aoi_8to7_chn_0: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_00_01 >> (i << 1)) & 0x03; + } + break; + case pla_aoi_8to7_chn_1: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_00_01 >> (i << 17)) & 0x03; + } + break; + case pla_aoi_8to7_chn_2: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_02_03 >> (i << 1)) & 0x03; + } + break; + case pla_aoi_8to7_chn_3: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_02_03 >> (i << 17)) & 0x03; + } + break; + case pla_aoi_8to7_chn_4: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_04_05 >> (i << 1)) & 0x03; + } + break; + case pla_aoi_8to7_chn_5: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_04_05 >> (i << 17)) & 0x03; + } + break; + case pla_aoi_8to7_chn_6: + for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { + cfg->input[i].signal = i; + cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_06 >> (i << 1)) & 0x03; + } + break; + default: + break; + } +} + +void pla_set_aoi_8to7_input_signal(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_8to7_channel_type_t aoi_8to7_chn, + pla_aoi_8to7_cfg_unit_t *cfg) +{ + uint32_t value; + + value = ((uint32_t)cfg->op) << (cfg->signal << 1); + switch (aoi_8to7_chn) { + case pla_aoi_8to7_chn_0: + pla->CHN[chn].AOI_8TO7_00_01 = (pla->CHN[chn].AOI_8TO7_00_01 & 0xffff0000) | value; + break; + case pla_aoi_8to7_chn_1: + pla->CHN[chn].AOI_8TO7_00_01 = (pla->CHN[chn].AOI_8TO7_00_01 & 0x0000ffff) | (value << 16); + break; + case pla_aoi_8to7_chn_2: + pla->CHN[chn].AOI_8TO7_02_03 = (pla->CHN[chn].AOI_8TO7_02_03 & 0xffff0000) | value; + break; + case pla_aoi_8to7_chn_3: + pla->CHN[chn].AOI_8TO7_02_03 = (pla->CHN[chn].AOI_8TO7_02_03 & 0x0000ffff) | (value << 16); + break; + case pla_aoi_8to7_chn_4: + pla->CHN[chn].AOI_8TO7_04_05 = (pla->CHN[chn].AOI_8TO7_04_05 & 0xffff0000) | value; + break; + case pla_aoi_8to7_chn_5: + pla->CHN[chn].AOI_8TO7_04_05 = (pla->CHN[chn].AOI_8TO7_04_05 & 0x0000ffff) | (value << 16); + break; + case pla_aoi_8to7_chn_6: + pla->CHN[chn].AOI_8TO7_06 = value; + break; + default: + break; + } +} + +void pla_get_aoi_8to7_input_signal(PLA_Type *pla, + pla_channel_type_t chn, + pla_aoi_8to7_channel_type_t aoi_8to7_chn, + pla_aoi_8to7_input_signal_type_t signal, + pla_aoi_8to7_cfg_unit_t *cfg) +{ + + switch (aoi_8to7_chn) { + case pla_aoi_8to7_chn_0: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_00_01 >> (signal << 1)) & 0x03; + break; + case pla_aoi_8to7_chn_1: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_00_01 >> (signal << 17)) & 0x03; + break; + case pla_aoi_8to7_chn_2: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_02_03 >> (signal << 1)) & 0x03; + break; + case pla_aoi_8to7_chn_3: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_02_03 >> (signal << 17)) & 0x03; + break; + case pla_aoi_8to7_chn_4: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_04_05 >> (signal << 1)) & 0x03; + break; + case pla_aoi_8to7_chn_5: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_04_05 >> (signal << 17)) & 0x03; + break; + case pla_aoi_8to7_chn_6: + cfg->signal = signal; + cfg->op = (pla->CHN[chn].AOI_8TO7_06 >> (signal << 1)) & 0x03; + break; + default: + break; + } +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c index f13d2d68..80676c93 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 HPMicro + * Copyright (c) 2022 - 2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -20,27 +20,27 @@ hpm_stat_t pllctlv2_init_pll_with_freq(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t freq_in_hz) { + hpm_stat_t status; if ((ptr == NULL) || (freq_in_hz < PLLCTLV2_PLL_FREQ_MIN) || (freq_in_hz > PLLCTLV2_PLL_FREQ_MAX) || (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { - return status_invalid_argument; + status = status_invalid_argument; + } else { + uint32_t mfn = freq_in_hz % PLLCTLV2_PLL_XTAL_FREQ; + uint32_t mfi = freq_in_hz / PLLCTLV2_PLL_XTAL_FREQ; + + if (PLLCTLV2_PLL_MFI_MFI_GET(ptr->PLL[pll].MFI) == mfi) { + ptr->PLL[pll].MFI = mfi - 1U; + } + + ptr->PLL[pll].MFI = mfi; + /* + * NOTE: Default MFD value is 240M + */ + ptr->PLL[pll].MFN = mfn * PLLCTLV2_PLL_MFN_FACTOR; + + status = status_success; } - - uint32_t mfn = freq_in_hz % PLLCTLV2_PLL_XTAL_FREQ; - uint32_t mfi = freq_in_hz / PLLCTLV2_PLL_XTAL_FREQ; - - if (PLLCTLV2_PLL_MFI_MFI_GET(ptr->PLL[pll].MFI) == mfi) { - ptr->PLL[pll].MFI = mfi - 1; - } - - ptr->PLL[pll].MFI = mfi; - /* - * NOTE: Default MFD value is 240M - */ - ptr->PLL[pll].MFN = mfn * PLLCTLV2_PLL_MFN_FACTOR; - - while (!pllctlv2_pll_is_stable(ptr, pll)) { - } - return status_success; + return status; } void pllctlv2_enable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t step, uint32_t stop) @@ -88,7 +88,7 @@ uint32_t pllctlv2_get_pll_postdiv_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll, ui if ((ptr != NULL) && (pll < PLLCTL_SOC_PLL_MAX_COUNT)) { uint32_t postdiv = PLLCTLV2_PLL_DIV_DIV_GET(ptr->PLL[pll].DIV[div_index]); uint32_t pll_freq = pllctlv2_get_pll_freq_in_hz(ptr, pll); - postdiv_freq = (uint32_t) (pll_freq / (1 + postdiv * 1.0 / 5)); + postdiv_freq = (uint32_t) (pll_freq / (1U + postdiv * 1.0 / 5U)); } return postdiv_freq; diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c index edf77b82..95c552aa 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c @@ -40,6 +40,10 @@ void pwm_get_default_cmp_config(PWM_Type *pwm_x, pwm_cmp_config_t *config) config->mode = pwm_cmp_mode_output_compare; config->update_trigger = pwm_shadow_register_update_on_modify; config->enable_ex_cmp = false; +#if PWM_SOC_HRPWM_SUPPORT + config->enable_hrcmp = false; + config->hrcmp = 0; +#endif config->cmp = 0; config->ex_cmp = 0; config->half_clock_cmp = 0; @@ -151,4 +155,31 @@ hpm_stat_t pwm_update_raw_cmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_inde pwm_cmp_update_cmp_value(pwm_x, cmp1_index, target_cmp1, 0); pwm_cmp_update_cmp_value(pwm_x, cmp2_index, target_cmp2, 0); return status_success; -} \ No newline at end of file +} +#if PWM_SOC_HRPWM_SUPPORT + +hpm_stat_t pwm_update_raw_hrcmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, uint32_t target_cmp, + uint16_t target_hrcmp) +{ + pwm_shadow_register_unlock(pwm_x); + pwm_cmp_update_hrcmp_value(pwm_x, cmp_index, target_cmp, target_hrcmp); + return status_success; +} + +hpm_stat_t pwm_update_raw_hrcmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, + uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2, + uint16_t target_hrcmp1, uint16_t target_hrcmp2) +{ + uint32_t reload = PWM_RLD_RLD_GET(pwm_x->RLD); + if (!target_cmp1) { + target_cmp1 = reload + 1; + } + if (!target_cmp2) { + target_cmp2 = reload + 1; + } + pwm_shadow_register_unlock(pwm_x); + pwm_cmp_update_hrcmp_value(pwm_x, cmp1_index, target_cmp1, target_hrcmp1); + pwm_cmp_update_hrcmp_value(pwm_x, cmp2_index, target_cmp2, target_hrcmp2); + return status_success; +} +#endif \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c index be1eac36..68d230c9 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,10 +9,6 @@ #include "hpm_rtc_drv.h" -#define RTC_ALARM_TYPE_ONE_SHOT (0U) -#define RTC_ALARM_TYPE_PERIODIC (1U) - - hpm_stat_t rtc_config_time(RTC_Type *base, time_t time) { base->SECOND = (uint32_t)time; @@ -29,19 +25,26 @@ hpm_stat_t rtc_config_alarm(RTC_Type *base, rtc_alarm_config_t *config) { hpm_stat_t status = status_invalid_argument; do { - if ((config == NULL) || (config->index > 1U) || (config->type > RTC_ALARM_TYPE_PERIODIC)) { + if ((config == NULL) || (config->index > 1U) || (config->type > RTC_ALARM_TYPE_ABSOLUTE_TIME_ONE_SHOT)) { break; } uint32_t alarm_inc = 0; - uint32_t current_sec = base->SECOND; - uint32_t alarm = current_sec + config->period; + uint32_t alarm; if (config->type == RTC_ALARM_TYPE_ONE_SHOT) { - alarm_inc = 0; - } else { + uint32_t current_sec = base->SECOND; + alarm = current_sec + config->period; + if (alarm < current_sec) { + break; + } + } else if (config->type == RTC_ALARM_TYPE_PERIODIC) { + uint32_t current_sec = base->SECOND; alarm_inc = config->period; - } - if (alarm < current_sec) { - break; + alarm = current_sec + config->period; + if (alarm < current_sec) { + break; + } + } else { + alarm = config->period; } if (config->index == 0U) { @@ -51,6 +54,8 @@ hpm_stat_t rtc_config_alarm(RTC_Type *base, rtc_alarm_config_t *config) base->ALARM1 = alarm; base->ALARM1_INC = alarm_inc; } + + status = status_success; } while (false); return status; diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c new file mode 100644 index 00000000..1d5a0f72 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sdm_drv.h" + +#ifndef HPM_LIN_DRV_RETRY_COUNT +#define HPM_LIN_DRV_RETRY_COUNT (5000U) +#endif + + +void sdm_get_default_module_control(SDM_Type *ptr, sdm_control_t *control) +{ + control->clk_signal_sync = true; + control->data_signal_sync = true; + control->interrupt_en = false; +} + +void sdm_init_module(SDM_Type *ptr, sdm_control_t *control) +{ + /* software reset */ + ptr->CTRL |= SDM_CTRL_SFTRST_MASK; + ptr->CTRL &= ~SDM_CTRL_SFTRST_MASK; + + ptr->CTRL |= SDM_CTRL_SYNC_MCLK_SET(control->clk_signal_sync) + | SDM_CTRL_SYNC_MDAT_SET(control->data_signal_sync) + | SDM_CTRL_IE_SET(control->interrupt_en); +} + +void sdm_get_channel_common_setting(SDM_Type *ptr, sdm_channel_common_config_t *config) +{ + config->sampling_mode = sdm_sampling_rising_clk_edge; + config->enable_err_interrupt = false; + config->enable_data_ready_interrupt = false; +} + +void sdm_config_channel_common_setting(SDM_Type *ptr, uint8_t ch_index, sdm_channel_common_config_t *config) +{ + if (config->enable_err_interrupt) { + ptr->INT_EN |= CHN_ERR_MASK(ch_index); + } + + if (config->enable_data_ready_interrupt) { + ptr->INT_EN |= CHN_DRY_MASK(ch_index); + } + + ptr->CTRL &= ~CHN_SAMPLING_MODE_MASK(ch_index); + ptr->CTRL |= config->sampling_mode << CHN_SAMPLING_MODE_SHIFT(ch_index); +} + +void sdm_get_channel_default_filter_config(SDM_Type *ptr, sdm_filter_config_t *filter_config) +{ + filter_config->fifo_threshold = 8; + filter_config->en_fifo_threshold_int = true; + filter_config->manchester_threshold = 0; + filter_config->wdg_threshold = 255; + filter_config->en_af_int = 0; + filter_config->en_data_overflow_int = 1; + filter_config->en_cic_data_saturation_int = 1; + filter_config->en_data_ready_int = 1; + filter_config->sync_source = 0; + filter_config->fifo_clean_on_sync = 0; + filter_config->wtsynaclr = 0; + filter_config->wtsynmclr = 0; + filter_config->wtsyncen = 0; + filter_config->output_32bit = 1; + filter_config->data_ready_flag_by_fifo = 1; + filter_config->enable = 1; + + filter_config->filter_type = sdm_filter_sinc1; + filter_config->pwm_signal_sync = 0; + filter_config->output_offset = 0; + filter_config->oversampling_rate = 32; /**< 1- 256 */ + filter_config->ignore_invalid_samples = 0; +} + +void sdm_get_channel_default_comparator_config(SDM_Type *ptr, sdm_comparator_config_t *cmp_config) +{ + cmp_config->high_threshold = 0xffff; + cmp_config->zero_cross_threshold = 0xffff; + cmp_config->low_threshold = 0x0; + + cmp_config->en_zero_cross_threshold_int = false; + cmp_config->en_clock_invalid_int = false; + cmp_config->en_high_threshold_int = false; + cmp_config->en_low_threshold_int = false; + cmp_config->filter_type = sdm_filter_sinc1; + cmp_config->oversampling_rate = 32; /**< 1-32, when 32, write 0 into bitfield */ + cmp_config->ignore_invalid_samples = 0; + cmp_config->enable = true; +} + +void sdm_config_channel_filter(SDM_Type *ptr, uint8_t ch_index, sdm_filter_config_t *filter_config) +{ + /* fifo setting */ + ptr->CH[ch_index].SDFIFOCTRL = SDM_CH_SDFIFOCTRL_THRSH_SET(filter_config->fifo_threshold) + | SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SET(filter_config->en_fifo_threshold_int); + + ptr->CH[ch_index].SDCTRLE = SDM_CH_SDCTRLE_SGD_ORDR_SET(filter_config->filter_type) + | SDM_CH_SDCTRLE_PWMSYNC_SET(filter_config->pwm_signal_sync) + | SDM_CH_SDCTRLE_CIC_SCL_SET(filter_config->output_offset) + | SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(filter_config->oversampling_rate - 1) + | SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET(filter_config->ignore_invalid_samples); + + ptr->CH[ch_index].SDCTRLP = SDM_CH_SDCTRLP_MANCH_THR_SET(filter_config->manchester_threshold) + | SDM_CH_SDCTRLP_WDOG_THR_SET(filter_config->wdg_threshold) + | SDM_CH_SDCTRLP_AF_IE_SET(filter_config->en_af_int) + | SDM_CH_SDCTRLP_DFFOVIE_SET(filter_config->en_data_overflow_int) + | SDM_CH_SDCTRLP_DSATIE_SET(filter_config->en_cic_data_saturation_int) + | SDM_CH_SDCTRLP_DRIE_SET(filter_config->en_data_ready_int) + | SDM_CH_SDCTRLP_SYNCSEL_SET(filter_config->sync_source) + | SDM_CH_SDCTRLP_FFSYNCCLREN_SET(filter_config->fifo_clean_on_sync) + | SDM_CH_SDCTRLP_WTSYNACLR_SET(filter_config->wtsynaclr) + | SDM_CH_SDCTRLP_WTSYNMCLR_SET(filter_config->wtsynmclr) + | SDM_CH_SDCTRLP_WTSYNCEN_SET(filter_config->wtsyncen) + | SDM_CH_SDCTRLP_D32_SET(filter_config->output_32bit) + | SDM_CH_SDCTRLP_DR_OPT_SET(filter_config->data_ready_flag_by_fifo); + + ptr->CH[ch_index].SDCTRLP |= SDM_CH_SDCTRLP_EN_SET(filter_config->enable); +} + +void sdm_config_channel_comparator(SDM_Type *ptr, uint8_t ch_index, sdm_comparator_config_t *cmp_config) +{ + ptr->CH[ch_index].SCHTL = cmp_config->high_threshold; + ptr->CH[ch_index].SCLLT = cmp_config->low_threshold; + ptr->CH[ch_index].SCHTLZ = cmp_config->zero_cross_threshold; + + ptr->CH[ch_index].SCCTRL = SDM_CH_SCCTRL_HZ_EN_SET(cmp_config->en_zero_cross_threshold_int) + | SDM_CH_SCCTRL_MF_IE_SET(cmp_config->en_clock_invalid_int) + | SDM_CH_SCCTRL_HL_IE_SET(cmp_config->en_high_threshold_int) + | SDM_CH_SCCTRL_LL_IE_SET(cmp_config->en_low_threshold_int) + | SDM_CH_SCCTRL_SGD_ORDR_SET(cmp_config->filter_type) + | SDM_CH_SCCTRL_CIC_DEC_RATIO_SET(cmp_config->oversampling_rate) + | SDM_CH_SCCTRL_IGN_INI_SAMPLES_SET(cmp_config->ignore_invalid_samples); + + ptr->CH[ch_index].SCCTRL |= SDM_CH_SCCTRL_EN_SET(cmp_config->enable); +} + +hpm_stat_t sdm_receive_one_filter_data(SDM_Type *ptr, uint8_t ch_index, bool using_fifo, int8_t *data, uint8_t data_len_in_bytes) +{ + uint32_t retry = 0; + int32_t output; + + while (!sdm_get_channel_data_ready_status(ptr, ch_index)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + if (using_fifo) { + output = ptr->CH[ch_index].SDFIFO; + } else { + output = ptr->CH[ch_index].SDATA; + } + + for (uint8_t i = 0; i < data_len_in_bytes; i++) { + *(data++) = (int8_t)(output >> (i * 8)); + } + + return status_success; +} + +hpm_stat_t sdm_receive_filter_data(SDM_Type *ptr, uint8_t ch_index, bool using_fifo, int8_t *data, uint32_t count, uint8_t data_len_in_bytes) +{ + for (uint32_t i = 0; i < count; i++) { + if (status_success != sdm_receive_one_filter_data(ptr, ch_index, using_fifo, data, data_len_in_bytes)) { + return status_fail; + } + + for (uint8_t i = 0; i < data_len_in_bytes; i++) { + data++; + } + } + return status_success; +} + diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c index 03a51850..97e102d0 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -32,14 +32,17 @@ #define AES_CTR_BLOCK_UNIT (16U) typedef enum { - sdp_state_hash_init, - sdp_state_hash_update, + sdp_state_hash_init, sdp_state_hash_update, } sdp_hash_alg_state_t; #define AES_BLOCK_SIZE (16U) #define HASH_BLOCK_SIZE (64U) #define HASH_DIGEST_SIZE_MAX (32) +#define SDP_CRYPTO_ALG_IDX_AES128 (0U) +#define SDP_CRYPTO_ALG_IDX_AES256 (1U) +#define SDP_CRYPTO_ALG_IDX_SM4 (8U) + typedef struct { union { uint32_t words[HASH_BLOCK_SIZE / sizeof(uint32_t)]; @@ -74,7 +77,8 @@ static void sdp_increment_bn(uint8_t *big_num, uint32_t bytes); static void uint32_to_be(uint8_t *dst, uint32_t len, uint32_t num); -static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, +static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t input_len, const uint8_t *iv, @@ -86,14 +90,17 @@ static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint8_t *mac, uint32_t mac_len); -static void aes_ccm_format_b0(uint8_t *block, const uint8_t *iv, uint32_t iv_len, uint32_t mac_len, uint32_t aad_len, +static void aes_ccm_format_b0(uint8_t *block, + const uint8_t *iv, + uint32_t iv_len, + uint32_t mac_len, + uint32_t aad_len, uint32_t input_len); static void aes_ccm_format_ctr0(uint8_t *ctr, const uint8_t *iv, uint8_t iv_len); static uint8_t sdp_constant_time_cmp(const void *dst, const void *src, uint32_t len); - /*********************************************************************************************************************** * Codes **********************************************************************************************************************/ @@ -135,7 +142,6 @@ hpm_stat_t sdp_init(SDP_Type *base) return status; } - hpm_stat_t sdp_deinit(SDP_Type *base) { hpm_stat_t status = status_invalid_argument; @@ -146,7 +152,10 @@ hpm_stat_t sdp_deinit(SDP_Type *base) return status; } -hpm_stat_t sdp_aes_set_key(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t key_bits, +hpm_stat_t sdp_aes_set_key(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + const uint8_t *key, + sdp_aes_key_bits_t key_bits, uint32_t key_idx) { union { @@ -158,7 +167,7 @@ hpm_stat_t sdp_aes_set_key(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, const uint8_t hpm_stat_t status = status_invalid_argument; do { - /* TODO: AES_KEY index validity check */ + aes_ctx->crypto_algo = sdp_crypto_alg_aes; if (IS_HPM_BITMASK_SET(base->SDPCR, SDP_SDPCR_CIPDIS_MASK)) { status = status_sdp_no_crypto_support; @@ -203,7 +212,32 @@ hpm_stat_t sdp_aes_set_key(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, const uint8_t return status; } -hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) +hpm_stat_t sdp_sm4_set_key(SDP_Type *base, + sdp_sm4_ctx_t *sm4_ctx, + const uint8_t *key, + sdp_sm4_key_bits_t key_bits, + uint32_t key_idx) +{ + hpm_stat_t status = status_invalid_argument; + if (key_bits != sdp_sm4_keybits_128) { + return status; + } + status = sdp_aes_set_key(base, sm4_ctx, key, (sdp_aes_key_bits_t) key_bits, key_idx); + if (status != status_success) { + return status; + } + sm4_ctx->crypto_algo = sdp_crypto_alg_sm4; + + return status; +} +#endif + +hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t len, + const uint8_t *in, uint8_t *out) { assert((base != NULL) && (aes_ctx != NULL)); @@ -211,7 +245,7 @@ hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_ hpm_stat_t status; base->SDPCR = SDP_SDPCR_CIPHEN_MASK; -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->SDPCR |= HPM_BITSMASK(1, 8); base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK; base->PKTSRC = (uint32_t) in; @@ -228,16 +262,28 @@ hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_ #endif sdp_clear_error_status(base); - if (aes_ctx->key_bits == sdp_aes_keybits_128) { - base->MODCTRL = SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) - | SDP_MODCTRL_AESDIR_SET(op); - } else { - base->MODCTRL = SDP_MODCTRL_AESALG_SET(1) - | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) - | SDP_MODCTRL_AESDIR_SET(op); + if (aes_ctx->crypto_algo == sdp_crypto_alg_aes) { + if (aes_ctx->key_bits == sdp_aes_keybits_128) { + base->MODCTRL = + SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_AES128) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | + SDP_MODCTRL_AESDIR_SET(op); + } else { + base->MODCTRL = + SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_AES256) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | + SDP_MODCTRL_AESDIR_SET(op); + } + } +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) + else if (aes_ctx->crypto_algo == sdp_crypto_alg_sm4) { + base->MODCTRL = SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_SM4) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | + SDP_MODCTRL_AESDIR_SET(op); + } +#endif + else { + return status_sdp_invalid_alg; } -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->CMDPTR = 0; #else base->CMDPTR = (uint32_t) pkt_desc; @@ -249,8 +295,13 @@ hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_ return status; } -hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t length, - const uint8_t iv[16], const uint8_t *input, uint8_t *output) +hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + const uint8_t iv[16], + const uint8_t *input, + uint8_t *output) { assert((base != NULL) && (aes_ctx != NULL)); assert((op <= sdp_aes_op_decrypt) && (input != NULL) && (output != NULL)); @@ -258,7 +309,7 @@ hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_ hpm_stat_t status; base->SDPCR = SDP_SDPCR_CIPHEN_MASK; -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->SDPCR |= HPM_BITSMASK(1, 8); base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK | SDP_PKT_CTRL_CIPHIV_MASK; base->PKTSRC = (uint32_t) input; @@ -275,15 +326,25 @@ hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_ sdp_clear_error_status(base); - if (aes_ctx->key_bits == sdp_aes_keybits_128) { - base->MODCTRL = SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) - | SDP_MODCTRL_AESDIR_SET(op) - | SDP_MODCTRL_AESMOD_SET(1); - } else { - base->MODCTRL = SDP_MODCTRL_AESALG_SET(1) - | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) - | SDP_MODCTRL_AESDIR_SET(op) - | SDP_MODCTRL_AESMOD_SET(1); + if (aes_ctx->crypto_algo == sdp_crypto_alg_aes) { + if (aes_ctx->key_bits == sdp_aes_keybits_128) { + base->MODCTRL = + SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_AES128) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | + SDP_MODCTRL_AESDIR_SET(op) | SDP_MODCTRL_AESMOD_SET(1); + } else { + base->MODCTRL = + SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_AES256) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | + SDP_MODCTRL_AESDIR_SET(op) | SDP_MODCTRL_AESMOD_SET(1); + } + } +#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) + else if (aes_ctx->crypto_algo == sdp_crypto_alg_sm4) { + base->MODCTRL = SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_SM4) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | + SDP_MODCTRL_AESDIR_SET(op) | SDP_MODCTRL_AESMOD_SET(1); + } +#endif + else { + return status_sdp_invalid_alg; } /* Set IV, copy the IV to the context first in case the IV address is not 32-bit aligned */ @@ -293,7 +354,7 @@ hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, sdp_aes_op_ base->CIPHIV[i] = iv_32[i]; } (void) memset(iv_32, 0, sizeof(iv_32)); -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->CMDPTR = 0; #else base->CMDPTR = (uint32_t) pkt_desc; @@ -318,17 +379,21 @@ static void sdp_increment_bn(uint8_t *big_num, uint32_t bytes) } } -hpm_stat_t sdp_aes_crypt_ctr(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_counter, uint8_t *input, - uint8_t *output, uint32_t length) +hpm_stat_t sdp_aes_crypt_ctr(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + uint8_t *nonce_counter, + uint8_t *input, + uint8_t *output, + uint32_t length) { hpm_stat_t status = status_invalid_argument; do { HPM_BREAK_IF( - (base == NULL) || (aes_ctx == NULL) || (nonce_counter == NULL) || (input == NULL) || (output == NULL)); + (base == NULL) || (aes_ctx == NULL) || (nonce_counter == NULL) || (input == NULL) || (output == NULL)); uint32_t calc_len; - uint8_t *cipher_nonce = (uint8_t *)&aes_ctx->buf3; + uint8_t *cipher_nonce = (uint8_t *) &aes_ctx->buf3; while (length > 0) { calc_len = (length < 16U) ? length : 16U; status = sdp_aes_crypt_ecb(base, aes_ctx, sdp_aes_op_encrypt, 16, nonce_counter, cipher_nonce); @@ -376,7 +441,11 @@ static void uint32_to_be(uint8_t *dst, uint32_t len, uint32_t num) * byte (16-q...15) input length * */ -static void aes_ccm_format_b0(uint8_t *block, const uint8_t *iv, uint32_t iv_len, uint32_t mac_len, uint32_t aad_len, +static void aes_ccm_format_b0(uint8_t *block, + const uint8_t *iv, + uint32_t iv_len, + uint32_t mac_len, + uint32_t aad_len, uint32_t input_len) { uint8_t q = 15U - iv_len; @@ -411,8 +480,8 @@ static void aes_ccm_format_ctr0(uint8_t *ctr, const uint8_t *iv, uint8_t iv_len) (void) memcpy(ctr + 1U, iv, iv_len); } - -static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, +static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t input_len, const uint8_t *iv, @@ -544,15 +613,32 @@ static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, return status; } -hpm_stat_t sdp_aes_ccm_generate_encrypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *iv, - uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, uint8_t *tag, uint32_t tag_len) +hpm_stat_t sdp_aes_ccm_generate_encrypt(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *iv, + uint32_t iv_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len) { - return aes_ccm_auth_crypt(base, aes_ctx, sdp_aes_op_encrypt, input_len, iv, iv_len, aad, aad_len, input, output, - tag, tag_len); + return aes_ccm_auth_crypt(base, + aes_ctx, + sdp_aes_op_encrypt, + input_len, + iv, + iv_len, + aad, + aad_len, + input, + output, + tag, + tag_len); } - static uint8_t sdp_constant_time_cmp(const void *dst, const void *src, uint32_t len) { uint8_t result = 0U; @@ -569,9 +655,17 @@ static uint8_t sdp_constant_time_cmp(const void *dst, const void *src, uint32_t return result; } -hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *iv, - uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, const uint8_t *tag, uint32_t tag_len) +hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, + sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *iv, + uint32_t iv_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len) { hpm_stat_t status; @@ -579,8 +673,18 @@ hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, sdp_aes_ctx_t *aes_ctx, ui uint32_t calc_mac[4]; - status = aes_ccm_auth_crypt(base, aes_ctx, sdp_aes_op_decrypt, input_len, iv, iv_len, aad, aad_len, input, - output, (uint8_t *) &calc_mac, tag_len); + status = aes_ccm_auth_crypt(base, + aes_ctx, + sdp_aes_op_decrypt, + input_len, + iv, + iv_len, + aad, + aad_len, + input, + output, + (uint8_t *) &calc_mac, + tag_len); HPM_BREAK_IF(status != status_success); if (sdp_constant_time_cmp(calc_mac, tag, tag_len) != 0U) { status = status_sdp_error_invalid_mac; @@ -625,7 +729,6 @@ static void sdp_hash_internal_engine_init(SDP_Type *base, sdp_hash_ctx_t *hash_c ctx_internal->hash_finish = false; } - static hpm_stat_t sdp_hash_internal_update(SDP_Type *base, sdp_hash_ctx_t *ctx, const uint8_t *msg, uint32_t msg_size) { sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &ctx->internal; @@ -643,7 +746,7 @@ static hpm_stat_t sdp_hash_internal_update(SDP_Type *base, sdp_hash_ctx_t *ctx, } base->SDPCR = SDP_SDPCR_HASHEN_MASK; -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->SDPCR |= HPM_BITSMASK(1, 8); base->NPKTPTR = 0UL; base->PKTCTL = pkt_ctrl; @@ -662,7 +765,7 @@ static hpm_stat_t sdp_hash_internal_update(SDP_Type *base, sdp_hash_ctx_t *ctx, sdp_clear_error_status(base); base->MODCTRL = SDP_MODCTRL_HASALG_SET(ctx_internal->alg); -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->CMDPTR = 0; #else base->CMDPTR = (uint32_t) pkt_desc; @@ -782,6 +885,9 @@ hpm_stat_t sdp_hash_finish(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, uint8_t *di } break; case sdp_hash_alg_sha256: +#if defined(SDP_HAS_SM3_SUPPORT) && (SDP_HAS_SM3_SUPPORT == 1) + case sdp_hash_alg_sm3: +#endif copy_bytes = SHA256_DIGEST_SIZE_IN_BYTES; digest_words = copy_bytes / sizeof(uint32_t); for (uint32_t i = 0; i < digest_words; i++) { @@ -808,7 +914,7 @@ hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *dma_ctx, void *dst, const v } base->SDPCR = SDP_SDPCR_MCPEN_MASK; -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->SDPCR |= HPM_BITSMASK(1, 8); base->NPKTPTR = 0; base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK | SDP_PKTCTL_PKTTAG_SET(1); @@ -827,7 +933,7 @@ hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *dma_ctx, void *dst, const v sdp_clear_error_status(base); base->MODCTRL = 0; -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->CMDPTR = 0; #else base->CMDPTR = (uint32_t) pkt_desc; @@ -843,11 +949,11 @@ hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t { hpm_stat_t status; - uint32_t pattern_32 = - (pattern) | ((uint32_t) pattern << 8) | ((uint32_t) pattern << 16) | ((uint32_t) pattern << 24); + uint32_t + pattern_32 = (pattern) | ((uint32_t) pattern << 8) | ((uint32_t) pattern << 16) | ((uint32_t) pattern << 24); base->SDPCR = SDP_SDPCR_CONFEN_MASK; - #if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->SDPCR |= HPM_BITSMASK(1, 8); base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK; base->PKTSRC = (uint32_t) pattern_32; @@ -864,7 +970,7 @@ hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t sdp_clear_error_status(base); base->MODCTRL = 0; -#if SDP_REGISTER_DESCRIPTOR_COUNT +#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT base->CMDPTR = 0; #else base->CMDPTR = (uint32_t) pkt_desc; diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c index e2a13dfb..3ccb8c5f 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c @@ -255,16 +255,11 @@ hpm_stat_t spi_write_read_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t static hpm_stat_t spi_no_data(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config) { - hpm_stat_t stat; if (mode == spi_master_mode) { if (config->master_config.cmd_enable == false && config->master_config.addr_enable == false) { return status_invalid_argument; } - } else { - HPM_CHECK_RET(spi_wait_for_busy_status(ptr)); - HPM_CHECK_RET(spi_wait_for_idle_status(ptr)); } - return status_success; } @@ -441,11 +436,6 @@ hpm_stat_t spi_transfer(SPI_Type *ptr, /* read command on slave mode */ stat = spi_read_command(ptr, mode, config, cmd); - if (stat != status_success) { - return stat; - } - - stat = spi_wait_for_idle_status(ptr); return stat; } @@ -458,11 +448,6 @@ hpm_stat_t spi_setup_dma_transfer(SPI_Type *ptr, hpm_stat_t stat = status_fail; uint8_t mode; - stat = spi_wait_for_idle_status(ptr); - if (stat != status_success) { - return stat; - } - stat = spi_control_init(ptr, config, wcount, rcount); if (stat != status_success) { return stat; diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c index 24e73aa6..43b9d411 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c @@ -33,6 +33,12 @@ void uart_default_config(UART_Type *ptr, uart_config_t *config) config->modem_config.auto_flow_ctrl_en = false; config->modem_config.loop_back_en = false; config->modem_config.set_rts_high = false; +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + config->rxidle_config.detect_enable = false; + config->rxidle_config.detect_irq_enable = false; + config->rxidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one; + config->rxidle_config.threshold = 10; /* 10-bit for typical UART configuration (8-N-1) */ +#endif } static bool uart_calculate_baudrate(uint32_t freq, uint32_t baudrate, uint16_t *div_out, uint8_t *osc_out) @@ -158,7 +164,12 @@ hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config) } uart_modem_config(ptr, &config->modem_config); + +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + return uart_init_rxline_idle_detection(ptr, config->rxidle_config); +#else return status_success; +#endif } hpm_stat_t uart_set_baudrate(UART_Type *ptr, uint32_t baudrate, uint32_t src_clock_hz) @@ -266,3 +277,21 @@ hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *source, uint32_t size_in_byte } return status_success; } + + +#if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) +hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t rxidle_config) +{ + ptr->RXIDLE_CFG = UART_RXIDLE_CFG_DETECT_EN_SET(rxidle_config.detect_enable) + | UART_RXIDLE_CFG_THR_SET(rxidle_config.threshold) + | UART_RXIDLE_CFG_DETECT_COND_SET(rxidle_config.idle_cond); + + if (rxidle_config.detect_irq_enable) { + uart_enable_irq(ptr, uart_intr_rx_line_idle); + } else { + uart_disable_irq(ptr, uart_intr_rx_line_idle); + } + + return status_success; +} +#endif diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c index affd4711..111b77ea 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,7 +10,6 @@ #define TICKS_1M (1024UL * TICKS_1K) #define TICKS_1G (1024UL * TICKS_1M) #define ONE_SECOND_TICKS_IN_NS (1000UL * 1000UL * 1000UL) -#define DIFF_MAX (64U) typedef struct { uint32_t top; @@ -22,39 +21,38 @@ typedef struct { interrupt_interval_t interval; } interrupt_interval_map_t; - static const reset_interval_map_t k_reset_interval_map[reset_interval_out_of_range + 1U] = { - { 128UL, reset_interval_clock_period_mult_128 }, - { 256UL, reset_interval_clock_period_mult_256 }, - { 512UL, reset_interval_clock_period_mult_512 }, - { 1UL * TICKS_1K, reset_interval_clock_period_mult_1k }, - { 2UL * TICKS_1K, reset_interval_clock_period_mult_2k }, - { 4UL * TICKS_1K, reset_interval_clock_period_mult_4k }, - { 8UL * TICKS_1K, reset_interval_clock_period_mult_8k }, - { 16UL * TICKS_1K, reset_interval_clock_period_mult_16k }, - { 0xFFFFFFFFUL, reset_interval_out_of_range }, - }; + {128UL, reset_interval_clock_period_mult_128}, + {256UL, reset_interval_clock_period_mult_256}, + {512UL, reset_interval_clock_period_mult_512}, + {1UL * TICKS_1K, reset_interval_clock_period_mult_1k}, + {2UL * TICKS_1K, reset_interval_clock_period_mult_2k}, + {4UL * TICKS_1K, reset_interval_clock_period_mult_4k}, + {8UL * TICKS_1K, reset_interval_clock_period_mult_8k}, + {16UL * TICKS_1K, reset_interval_clock_period_mult_16k}, + {0xFFFFFFFFUL, reset_interval_out_of_range}, +}; static const interrupt_interval_map_t k_interrupt_interval_map[interrupt_interval_out_of_range + 1U] = { - { 64UL, interrupt_interval_clock_period_multi_64 }, - { 256UL, interrupt_interval_clock_period_multi_256 }, - { 1UL * TICKS_1K, interrupt_interval_clock_period_multi_1k }, - { 2UL * TICKS_1K, interrupt_interval_clock_period_multi_2k }, - { 4UL * TICKS_1K, interrupt_interval_clock_period_multi_4k }, - { 8UL * TICKS_1K, interrupt_interval_clock_period_multi_8k }, - { 16UL * TICKS_1K, interrupt_interval_clock_period_multi_16k }, - { 32UL * TICKS_1K, interrupt_interval_clock_period_multi_32k }, - { 128UL * TICKS_1K, interrupt_interval_clock_period_multi_128k }, - { 256UL * TICKS_1K, interrupt_interval_clock_period_multi_256k }, - { 2UL * TICKS_1M, interrupt_interval_clock_period_multi_2m }, - { 8UL * TICKS_1M, interrupt_interval_clock_period_multi_8m }, - { 32UL * TICKS_1M, interrupt_interval_clock_period_multi_32m }, - { 128UL * TICKS_1M, interrupt_interval_clock_period_multi_128m }, - { 512UL * TICKS_1M, interrupt_interval_clock_period_multi_512m }, - { 2UL * TICKS_1G, interrupt_interval_clock_period_multi_2g }, - { 0xFFFFFFFFUL, interrupt_interval_out_of_range } - - }; + {64UL, interrupt_interval_clock_period_multi_64}, + {256UL, interrupt_interval_clock_period_multi_256}, + {1UL * TICKS_1K, interrupt_interval_clock_period_multi_1k}, + {2UL * TICKS_1K, interrupt_interval_clock_period_multi_2k}, + {4UL * TICKS_1K, interrupt_interval_clock_period_multi_4k}, + {8UL * TICKS_1K, interrupt_interval_clock_period_multi_8k}, + {16UL * TICKS_1K, interrupt_interval_clock_period_multi_16k}, + {32UL * TICKS_1K, interrupt_interval_clock_period_multi_32k}, + {128UL * TICKS_1K, interrupt_interval_clock_period_multi_128k}, + {512UL * TICKS_1K, interrupt_interval_clock_period_multi_512k}, + {2UL * TICKS_1M, interrupt_interval_clock_period_multi_2m}, + {8UL * TICKS_1M, interrupt_interval_clock_period_multi_8m}, + {32UL * TICKS_1M, interrupt_interval_clock_period_multi_32m}, + {128UL * TICKS_1M, interrupt_interval_clock_period_multi_128m}, + {512UL * TICKS_1M, interrupt_interval_clock_period_multi_512m}, + {2UL * TICKS_1G, interrupt_interval_clock_period_multi_2g}, + {0xFFFFFFFFUL, interrupt_interval_out_of_range} + +}; /* See hpm_wdg_drv.h for more details */ hpm_stat_t wdg_init(WDG_Type *base, wdg_control_t *wdg_ctrl) @@ -64,8 +62,8 @@ hpm_stat_t wdg_init(WDG_Type *base, wdg_control_t *wdg_ctrl) HPM_BREAK_IF((base == NULL) || (wdg_ctrl == NULL)); HPM_BREAK_IF((wdg_ctrl->reset_interval > reset_interval_max) || - (wdg_ctrl->interrupt_interval > interrupt_interval_max) || - (wdg_ctrl->clksrc > wdg_clksrc_pclk)); + (wdg_ctrl->interrupt_interval > interrupt_interval_max) || + (wdg_ctrl->clksrc > wdg_clksrc_pclk)); uint32_t rst_time = (uint32_t) wdg_ctrl->reset_interval; uint32_t int_time = (uint32_t) wdg_ctrl->interrupt_interval; @@ -124,10 +122,9 @@ interrupt_interval_t wdg_convert_interrupt_interval_from_us(const uint32_t src_f src_clk_one_tick_in_ns = 1U; } - int32_t interrupt_interval_ticks = ((int64_t) interval_us * 1000L) / src_clk_one_tick_in_ns; - + uint32_t interrupt_interval_ticks = ((uint64_t) interval_us * 1000L) / src_clk_one_tick_in_ns; for (uint32_t i = 0; i < ARRAY_SIZE(k_interrupt_interval_map); i++) { - if (abs(interrupt_interval_ticks - (int32_t) k_interrupt_interval_map[i].top) <= DIFF_MAX) { + if (interrupt_interval_ticks <= k_interrupt_interval_map[i].top) { interrupt_interval = k_interrupt_interval_map[i].interval; break; } @@ -136,15 +133,29 @@ interrupt_interval_t wdg_convert_interrupt_interval_from_us(const uint32_t src_f return interrupt_interval; } +uint64_t wdg_convert_interrupt_interval_to_us(const uint32_t src_freq, interrupt_interval_t interval) +{ + uint64_t time_in_us = 0; + if ((src_freq != 0) && (interval < interrupt_interval_out_of_range)) { + uint32_t interrupt_interval_in_reg = (uint32_t) interval; + + double tick_in_ns = 1.0 * ONE_SECOND_TICKS_IN_NS / src_freq; + uint64_t + total_interval_in_ns = (uint64_t)(tick_in_ns * k_interrupt_interval_map[interrupt_interval_in_reg].top); + + time_in_us = total_interval_in_ns / 1000UL; + } -uint32_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq) + return time_in_us; +} + +uint32_t wdg_convert_reset_interval_to_us(const uint32_t src_freq, reset_interval_t interval) { uint32_t time_in_us = 0; - if ((base != NULL) && (src_freq != 0)) { - uint32_t interrupt_interval_in_reg = WDG_CTRL_INTTIME_GET(base->CTRL); - - double tick_in_ns = 1.0 * TICKS_1G / src_freq; - uint64_t total_interval_in_ns = (uint64_t)(tick_in_ns * k_interrupt_interval_map[interrupt_interval_in_reg].top); + if ((src_freq != 0) && (interval < reset_interval_out_of_range)) { + uint32_t reset_interval_in_reg = (uint32_t) interval; + double tick_in_ns = 1.0 * ONE_SECOND_TICKS_IN_NS / src_freq; + uint64_t total_interval_in_ns = (uint64_t)(tick_in_ns * k_reset_interval_map[reset_interval_in_reg].top); time_in_us = (uint32_t)(total_interval_in_ns / 1000UL); } @@ -152,15 +163,26 @@ uint32_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_fre return time_in_us; } -uint32_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq) +uint64_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq) { - uint32_t time_in_us = 0; + uint64_t time_in_us = 0; if ((base != NULL) && (src_freq != 0)) { - uint32_t reset_interval_in_reg = WDG_CTRL_RSTTIME_GET(base->CTRL); - double tick_in_ns = 1.0 * TICKS_1G / src_freq; - uint64_t total_interval_in_ns = (uint64_t)(tick_in_ns * k_reset_interval_map[reset_interval_in_reg].top); + interrupt_interval_t interval = (interrupt_interval_t) WDG_CTRL_INTTIME_GET(base->CTRL); + + time_in_us = wdg_convert_interrupt_interval_to_us(src_freq, interval); + } - time_in_us = (uint32_t)(total_interval_in_ns / 1000UL) + wdg_get_interrupt_interval_in_us(base, src_freq); + return time_in_us; +} + +uint64_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq) +{ + uint64_t time_in_us = 0; + if ((base != NULL) && (src_freq != 0)) { + reset_interval_t reset_interval = (reset_interval_t) WDG_CTRL_RSTTIME_GET(base->CTRL); + interrupt_interval_t interrupt_interval = (interrupt_interval_t) WDG_CTRL_INTTIME_GET(base->CTRL); + time_in_us = wdg_convert_reset_interval_to_us(src_freq, reset_interval) + + wdg_convert_interrupt_interval_to_us(src_freq, interrupt_interval); } return time_in_us; diff --git a/common/libraries/hpm_sdk/index.md b/common/libraries/hpm_sdk/index.md deleted file mode 100644 index 5d9467a9..00000000 --- a/common/libraries/hpm_sdk/index.md +++ /dev/null @@ -1,15 +0,0 @@ -hpm sdk -=================================== -:::{eval-rst} -.. toctree:: - :maxdepth: 1 - :caption: Contents - :name: HPM README Document - - CHANGELOG - README - boards/index - samples/index - doc/src/sdk_doc/README - -::: \ No newline at end of file diff --git a/common/libraries/hpm_sdk/index_zh.md b/common/libraries/hpm_sdk/index_zh.md deleted file mode 100644 index c9dad497..00000000 --- a/common/libraries/hpm_sdk/index_zh.md +++ /dev/null @@ -1,15 +0,0 @@ -hpm sdk -=================================== - -:::{eval-rst} -.. toctree:: - :maxdepth: 1 - :caption: 目录 - :name: HPM README Document - - CHANGELOG - README_zh - boards/index_zh - samples/index_zh - doc/src/sdk_doc/README_zh -::: \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/CMakeLists.txt b/common/libraries/hpm_sdk/soc/CMakeLists.txt index 09b36269..1c02dd68 100644 --- a/common/libraries/hpm_sdk/soc/CMakeLists.txt +++ b/common/libraries/hpm_sdk/soc/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause sdk_inc(${HPM_SOC}) diff --git a/common/libraries/hpm_sdk/soc/HPM6280/CMakeLists.txt b/common/libraries/hpm_sdk/soc/HPM6280/CMakeLists.txt new file mode 100644 index 00000000..f67d6468 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/CMakeLists.txt @@ -0,0 +1,63 @@ +# Copyright (c) 2021-2022 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +sdk_inc(toolchains) + +if(NOT DEFINED USE_CUSTOM_STARTUP) + sdk_gcc_src(toolchains/gcc/start.S) + sdk_ses_src(toolchains/segger/startup.s) +endif() + +sdk_src( + toolchains/reset.c + toolchains/trap.c + system.c +) + +sdk_gcc_src(toolchains/gcc/initfini.c) + +# soc drivers +sdk_src ( + hpm_sysctl_drv.c + hpm_l1c_drv.c + hpm_clock_drv.c + hpm_otp_drv.c +) + +if(${INCLUDE_BOOTHEADER}) + sdk_inc(boot) + sdk_src(boot/hpm_bootheader.c) +endif() + +sdk_nds_compile_options(-mcpu=d45) + +set(SOC_LINKER_SCRIPT "" PARENT_SCOPE) +if(NOT DEFINED USE_CUSTOM_LINKER) + if(${LINK_TO_FLASH}) + if(${INCLUDE_BOOTHEADER}) + if(${FLASH_XIP}) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/flash_xip.ld PARENT_SCOPE) + else() + if(${FLASH_SDRAM_XIP}) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/flash_sdram_xip.ld PARENT_SCOPE) + endif() + endif() + else() + if(${FLASH_UF2}) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/flash_uf2.ld PARENT_SCOPE) + else() + if(${FLASH_SDRAM_UF2}) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/flash_sdram_uf2.ld PARENT_SCOPE) + else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/flash.ld PARENT_SCOPE) + endif() + endif() + endif() + else() + if(BUILD_FOR_SECONDARY_CORE) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/ram_core1.ld PARENT_SCOPE) + else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/ram.ld PARENT_SCOPE) + endif() + endif() +endif() diff --git a/common/libraries/hpm_sdk/soc/HPM6280/HPM6280_svd.xml b/common/libraries/hpm_sdk/soc/HPM6280/HPM6280_svd.xml new file mode 100644 index 00000000..2eb2ba7b --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/HPM6280_svd.xml @@ -0,0 +1,134439 @@ + + + HPMICRO + HPM6280 + HPM6200 + 1.0 + HPM6200 device + + /* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + + + other + r0p0 + little + false + true + true + 7 + false + + 8 + 32 + + 32 + 0x0 + 0xFFFFFFFF + + + FGPIO + FGPIO + GPIO + 0xc0000 + + 0x0 + 0x800 + registers + + + + DI_GPIOA_VALUE + GPIO input value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOA_SET + GPIO input set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOA_CLEAR + GPIO input clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOA_TOGGLE + GPIO input toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOB_VALUE + GPIOB input + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOB_SET + GPIO input set + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOB_CLEAR + GPIO input clear + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOB_TOGGLE + GPIO input toggle + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOC_VALUE + GPIOC input + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOC_SET + GPIO input set + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOC_CLEAR + GPIO input clear + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOC_TOGGLE + GPIO input toggle + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOD_VALUE + GPIOD input + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOD_SET + GPIO input set + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOD_CLEAR + GPIO input clear + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOD_TOGGLE + GPIO input toggle + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOE_VALUE + GPIOE input + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOE_SET + GPIO input set + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOE_CLEAR + GPIO input clear + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOE_TOGGLE + GPIO input toggle + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOF_VALUE + GPIOF input + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOF_SET + GPIO input set + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOF_CLEAR + GPIO input clear + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOF_TOGGLE + GPIO input toggle + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOX_VALUE + GPIOX input + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOX_SET + GPIO input set + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOX_CLEAR + GPIO input clear + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOX_TOGGLE + GPIO input toggle + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOY_VALUE + GPIOY input + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOY_SET + GPIO input set + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOY_CLEAR + GPIO input clear + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOY_TOGGLE + GPIO input toggle + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOZ_VALUE + GPIOZ input + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOZ_SET + GPIO input set + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOZ_CLEAR + GPIO input clear + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DI_GPIOZ_TOGGLE + GPIO input toggle + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-write + + + + + DO_GPIOA_VALUE + GPIO output value + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOA_SET + GPIO output set + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOA_CLEAR + GPIO output clear + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOA_TOGGLE + GPIO output toggle + 0x10c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOB_VALUE + GPIOB output + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOB_SET + GPIO output set + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOB_CLEAR + GPIO output clear + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOB_TOGGLE + GPIO output toggle + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOC_VALUE + GPIOC output + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOC_SET + GPIO output set + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOC_CLEAR + GPIO output clear + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOC_TOGGLE + GPIO output toggle + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOD_VALUE + GPIOD output + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOD_SET + GPIO output set + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOD_CLEAR + GPIO output clear + 0x138 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOD_TOGGLE + GPIO output toggle + 0x13c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOE_VALUE + GPIOE output + 0x140 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOE_SET + GPIO output set + 0x144 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOE_CLEAR + GPIO output clear + 0x148 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOE_TOGGLE + GPIO output toggle + 0x14c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOF_VALUE + GPIOF output + 0x150 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOF_SET + GPIO output set + 0x154 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOF_CLEAR + GPIO output clear + 0x158 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOF_TOGGLE + GPIO output toggle + 0x15c + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOX_VALUE + GPIOX output + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOX_SET + GPIO output set + 0x1d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOX_CLEAR + GPIO output clear + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOX_TOGGLE + GPIO output toggle + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOY_VALUE + GPIOY output + 0x1e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOY_SET + GPIO output set + 0x1e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOY_CLEAR + GPIO output clear + 0x1e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOY_TOGGLE + GPIO output toggle + 0x1ec + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOZ_VALUE + GPIOZ output + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOZ_SET + GPIO output set + 0x1f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOZ_CLEAR + GPIO output clear + 0x1f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + DO_GPIOZ_TOGGLE + GPIO output toggle + 0x1fc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + OE_GPIOA_VALUE + GPIO direction value + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOA_SET + GPIO direction set + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOA_CLEAR + GPIO direction clear + 0x208 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOA_TOGGLE + GPIO direction toggle + 0x20c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOB_VALUE + GPIOB direction + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOB_SET + GPIO direction set + 0x214 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOB_CLEAR + GPIO direction clear + 0x218 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOB_TOGGLE + GPIO direction toggle + 0x21c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOC_VALUE + GPIOC direction + 0x220 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOC_SET + GPIO direction set + 0x224 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOC_CLEAR + GPIO direction clear + 0x228 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOC_TOGGLE + GPIO direction toggle + 0x22c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOD_VALUE + GPIOD direction + 0x230 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOD_SET + GPIO direction set + 0x234 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOD_CLEAR + GPIO direction clear + 0x238 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOD_TOGGLE + GPIO direction toggle + 0x23c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOE_VALUE + GPIOE direction + 0x240 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOE_SET + GPIO direction set + 0x244 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOE_CLEAR + GPIO direction clear + 0x248 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOE_TOGGLE + GPIO direction toggle + 0x24c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOF_VALUE + GPIOF direction + 0x250 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOF_SET + GPIO direction set + 0x254 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOF_CLEAR + GPIO direction clear + 0x258 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOF_TOGGLE + GPIO direction toggle + 0x25c + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOX_VALUE + GPIOX direction + 0x2d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOX_SET + GPIO direction set + 0x2d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOX_CLEAR + GPIO direction clear + 0x2d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOX_TOGGLE + GPIO direction toggle + 0x2dc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOY_VALUE + GPIOY direction + 0x2e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOY_SET + GPIO direction set + 0x2e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOY_CLEAR + GPIO direction clear + 0x2e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOY_TOGGLE + GPIO direction toggle + 0x2ec + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOZ_VALUE + GPIOZ direction + 0x2f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOZ_SET + GPIO direction set + 0x2f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOZ_CLEAR + GPIO direction clear + 0x2f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + OE_GPIOZ_TOGGLE + GPIO direction toggle + 0x2fc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + IF_GPIOA_VALUE + GPIO interrupt flag value + 0x300 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + IF_GPIOA_SET + GPIO interrupt flag set + 0x304 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOA_CLEAR + GPIO interrupt flag clear + 0x308 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOA_TOGGLE + GPIO interrupt flag toggle + 0x30c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOB_VALUE + GPIOB interrupt flag + 0x310 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + IF_GPIOB_SET + GPIO interrupt flag set + 0x314 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOB_CLEAR + GPIO interrupt flag clear + 0x318 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOB_TOGGLE + GPIO interrupt flag toggle + 0x31c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOC_VALUE + GPIOC interrupt flag + 0x320 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + IF_GPIOC_SET + GPIO interrupt flag set + 0x324 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOC_CLEAR + GPIO interrupt flag clear + 0x328 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOC_TOGGLE + GPIO interrupt flag toggle + 0x32c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOD_VALUE + GPIOD interrupt flag + 0x330 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + IF_GPIOD_SET + GPIO interrupt flag set + 0x334 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOD_CLEAR + GPIO interrupt flag clear + 0x338 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOD_TOGGLE + GPIO interrupt flag toggle + 0x33c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOE_VALUE + GPIOE interrupt flag + 0x340 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + IF_GPIOE_SET + GPIO interrupt flag set + 0x344 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOE_CLEAR + GPIO interrupt flag clear + 0x348 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOE_TOGGLE + GPIO interrupt flag toggle + 0x34c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOF_VALUE + GPIOF interrupt flag + 0x350 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + IF_GPIOF_SET + GPIO interrupt flag set + 0x354 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOF_CLEAR + GPIO interrupt flag clear + 0x358 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOF_TOGGLE + GPIO interrupt flag toggle + 0x35c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOX_VALUE + GPIOX interrupt flag + 0x3d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + IF_GPIOX_SET + GPIO interrupt flag set + 0x3d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOX_CLEAR + GPIO interrupt flag clear + 0x3d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOX_TOGGLE + GPIO interrupt flag toggle + 0x3dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOY_VALUE + GPIOY interrupt flag + 0x3e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + IF_GPIOY_SET + GPIO interrupt flag set + 0x3e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOY_CLEAR + GPIO interrupt flag clear + 0x3e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOY_TOGGLE + GPIO interrupt flag toggle + 0x3ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOZ_VALUE + GPIOZ interrupt flag + 0x3f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + IF_GPIOZ_SET + GPIO interrupt flag set + 0x3f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOZ_CLEAR + GPIO interrupt flag clear + 0x3f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IF_GPIOZ_TOGGLE + GPIO interrupt flag toggle + 0x3fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + read-write + + + + + IE_GPIOA_VALUE + GPIO interrupt enable value + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOA_SET + GPIO interrupt enable set + 0x404 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOA_CLEAR + GPIO interrupt enable clear + 0x408 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOA_TOGGLE + GPIO interrupt enable toggle + 0x40c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOB_VALUE + GPIOB interrupt enable + 0x410 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOB_SET + GPIO interrupt enable set + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOB_CLEAR + GPIO interrupt enable clear + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOB_TOGGLE + GPIO interrupt enable toggle + 0x41c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOC_VALUE + GPIOC interrupt enable + 0x420 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOC_SET + GPIO interrupt enable set + 0x424 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOC_CLEAR + GPIO interrupt enable clear + 0x428 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOC_TOGGLE + GPIO interrupt enable toggle + 0x42c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOD_VALUE + GPIOD interrupt enable + 0x430 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOD_SET + GPIO interrupt enable set + 0x434 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOD_CLEAR + GPIO interrupt enable clear + 0x438 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOD_TOGGLE + GPIO interrupt enable toggle + 0x43c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOE_VALUE + GPIOE interrupt enable + 0x440 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOE_SET + GPIO interrupt enable set + 0x444 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOE_CLEAR + GPIO interrupt enable clear + 0x448 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOE_TOGGLE + GPIO interrupt enable toggle + 0x44c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOF_VALUE + GPIOF interrupt enable + 0x450 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOF_SET + GPIO interrupt enable set + 0x454 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOF_CLEAR + GPIO interrupt enable clear + 0x458 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOF_TOGGLE + GPIO interrupt enable toggle + 0x45c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOX_VALUE + GPIOX interrupt enable + 0x4d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOX_SET + GPIO interrupt enable set + 0x4d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOX_CLEAR + GPIO interrupt enable clear + 0x4d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOX_TOGGLE + GPIO interrupt enable toggle + 0x4dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOY_VALUE + GPIOY interrupt enable + 0x4e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOY_SET + GPIO interrupt enable set + 0x4e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOY_CLEAR + GPIO interrupt enable clear + 0x4e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOY_TOGGLE + GPIO interrupt enable toggle + 0x4ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOZ_VALUE + GPIOZ interrupt enable + 0x4f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOZ_SET + GPIO interrupt enable set + 0x4f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOZ_CLEAR + GPIO interrupt enable clear + 0x4f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + IE_GPIOZ_TOGGLE + GPIO interrupt enable toggle + 0x4fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + PL_GPIOA_VALUE + GPIO interrupt polarity value + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOA_SET + GPIO interrupt polarity set + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOA_CLEAR + GPIO interrupt polarity clear + 0x508 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOA_TOGGLE + GPIO interrupt polarity toggle + 0x50c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOB_VALUE + GPIOB interrupt polarity + 0x510 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOB_SET + GPIO interrupt polarity set + 0x514 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOB_CLEAR + GPIO interrupt polarity clear + 0x518 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOB_TOGGLE + GPIO interrupt polarity toggle + 0x51c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOC_VALUE + GPIOC interrupt polarity + 0x520 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOC_SET + GPIO interrupt polarity set + 0x524 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOC_CLEAR + GPIO interrupt polarity clear + 0x528 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOC_TOGGLE + GPIO interrupt polarity toggle + 0x52c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOD_VALUE + GPIOD interrupt polarity + 0x530 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOD_SET + GPIO interrupt polarity set + 0x534 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOD_CLEAR + GPIO interrupt polarity clear + 0x538 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOD_TOGGLE + GPIO interrupt polarity toggle + 0x53c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOE_VALUE + GPIOE interrupt polarity + 0x540 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOE_SET + GPIO interrupt polarity set + 0x544 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOE_CLEAR + GPIO interrupt polarity clear + 0x548 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOE_TOGGLE + GPIO interrupt polarity toggle + 0x54c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOF_VALUE + GPIOF interrupt polarity + 0x550 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOF_SET + GPIO interrupt polarity set + 0x554 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOF_CLEAR + GPIO interrupt polarity clear + 0x558 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOF_TOGGLE + GPIO interrupt polarity toggle + 0x55c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOX_VALUE + GPIOX interrupt polarity + 0x5d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOX_SET + GPIO interrupt polarity set + 0x5d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOX_CLEAR + GPIO interrupt polarity clear + 0x5d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOX_TOGGLE + GPIO interrupt polarity toggle + 0x5dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOY_VALUE + GPIOY interrupt polarity + 0x5e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOY_SET + GPIO interrupt polarity set + 0x5e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOY_CLEAR + GPIO interrupt polarity clear + 0x5e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOY_TOGGLE + GPIO interrupt polarity toggle + 0x5ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOZ_VALUE + GPIOZ interrupt polarity + 0x5f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOZ_SET + GPIO interrupt polarity set + 0x5f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOZ_CLEAR + GPIO interrupt polarity clear + 0x5f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + PL_GPIOZ_TOGGLE + GPIO interrupt polarity toggle + 0x5fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + TP_GPIOA_VALUE + GPIO interrupt type value + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOA_SET + GPIO interrupt type set + 0x604 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOA_CLEAR + GPIO interrupt type clear + 0x608 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOA_TOGGLE + GPIO interrupt type toggle + 0x60c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOB_VALUE + GPIOB interrupt type + 0x610 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOB_SET + GPIO interrupt type set + 0x614 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOB_CLEAR + GPIO interrupt type clear + 0x618 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOB_TOGGLE + GPIO interrupt type toggle + 0x61c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOC_VALUE + GPIOC interrupt type + 0x620 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOC_SET + GPIO interrupt type set + 0x624 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOC_CLEAR + GPIO interrupt type clear + 0x628 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOC_TOGGLE + GPIO interrupt type toggle + 0x62c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOD_VALUE + GPIOD interrupt type + 0x630 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOD_SET + GPIO interrupt type set + 0x634 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOD_CLEAR + GPIO interrupt type clear + 0x638 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOD_TOGGLE + GPIO interrupt type toggle + 0x63c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOE_VALUE + GPIOE interrupt type + 0x640 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOE_SET + GPIO interrupt type set + 0x644 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOE_CLEAR + GPIO interrupt type clear + 0x648 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOE_TOGGLE + GPIO interrupt type toggle + 0x64c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOF_VALUE + GPIOF interrupt type + 0x650 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOF_SET + GPIO interrupt type set + 0x654 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOF_CLEAR + GPIO interrupt type clear + 0x658 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOF_TOGGLE + GPIO interrupt type toggle + 0x65c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOX_VALUE + GPIOX interrupt type + 0x6d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOX_SET + GPIO interrupt type set + 0x6d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOX_CLEAR + GPIO interrupt type clear + 0x6d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOX_TOGGLE + GPIO interrupt type toggle + 0x6dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOY_VALUE + GPIOY interrupt type + 0x6e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOY_SET + GPIO interrupt type set + 0x6e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOY_CLEAR + GPIO interrupt type clear + 0x6e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOY_TOGGLE + GPIO interrupt type toggle + 0x6ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOZ_VALUE + GPIOZ interrupt type + 0x6f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOZ_SET + GPIO interrupt type set + 0x6f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOZ_CLEAR + GPIO interrupt type clear + 0x6f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TP_GPIOZ_TOGGLE + GPIO interrupt type toggle + 0x6fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + AS_GPIOA_VALUE + GPIO interrupt asynchronous value + 0x700 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOA_SET + GPIO interrupt asynchronous set + 0x704 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOA_CLEAR + GPIO interrupt asynchronous clear + 0x708 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOA_TOGGLE + GPIO interrupt asynchronous toggle + 0x70c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOB_VALUE + GPIOB interrupt asynchronous + 0x710 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOB_SET + GPIO interrupt asynchronous set + 0x714 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOB_CLEAR + GPIO interrupt asynchronous clear + 0x718 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOB_TOGGLE + GPIO interrupt asynchronous toggle + 0x71c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOC_VALUE + GPIOC interrupt asynchronous + 0x720 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOC_SET + GPIO interrupt asynchronous set + 0x724 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOC_CLEAR + GPIO interrupt asynchronous clear + 0x728 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOC_TOGGLE + GPIO interrupt asynchronous toggle + 0x72c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOD_VALUE + GPIOD interrupt asynchronous + 0x730 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOD_SET + GPIO interrupt asynchronous set + 0x734 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOD_CLEAR + GPIO interrupt asynchronous clear + 0x738 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOD_TOGGLE + GPIO interrupt asynchronous toggle + 0x73c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOE_VALUE + GPIOE interrupt asynchronous + 0x740 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOE_SET + GPIO interrupt asynchronous set + 0x744 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOE_CLEAR + GPIO interrupt asynchronous clear + 0x748 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOE_TOGGLE + GPIO interrupt asynchronous toggle + 0x74c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOF_VALUE + GPIOF interrupt asynchronous + 0x750 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOF_SET + GPIO interrupt asynchronous set + 0x754 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOF_CLEAR + GPIO interrupt asynchronous clear + 0x758 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOF_TOGGLE + GPIO interrupt asynchronous toggle + 0x75c + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOX_VALUE + GPIOX interrupt asynchronous + 0x7d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOX_SET + GPIO interrupt asynchronous set + 0x7d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOX_CLEAR + GPIO interrupt asynchronous clear + 0x7d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOX_TOGGLE + GPIO interrupt asynchronous toggle + 0x7dc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOY_VALUE + GPIOY interrupt asynchronous + 0x7e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOY_SET + GPIO interrupt asynchronous set + 0x7e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOY_CLEAR + GPIO interrupt asynchronous clear + 0x7e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOY_TOGGLE + GPIO interrupt asynchronous toggle + 0x7ec + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOZ_VALUE + GPIOZ interrupt asynchronous + 0x7f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOZ_SET + GPIO interrupt asynchronous set + 0x7f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOZ_CLEAR + GPIO interrupt asynchronous clear + 0x7f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + AS_GPIOZ_TOGGLE + GPIO interrupt asynchronous toggle + 0x7fc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + + + GPIO0 + GPIO0 + GPIO + 0xf0000000 + + + GPIO1 + GPIO1 + GPIO + 0xf0004000 + + + PGPIO + PGPIO + GPIO + 0xf40dc000 + + + BGPIO + BGPIO + GPIO + 0xf5014000 + + + PLIC + PLIC + PLIC + 0xe4000000 + + 0x0 + 0x202000 + registers + + + + FEATURE + Feature enable register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + VECTORED + Vector mode enable +0: Disabled +1: Enabled + 1 + 1 + read-write + + + PREEMPT + Preemptive priority interrupt enable +0: Disabled +1: Enabled + 0 + 1 + read-write + + + + + PRIORITY_PRIORITY1 + Source priority + 0x4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY2 + Source priority + 0x8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY3 + Source priority + 0xc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY4 + Source priority + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY5 + Source priority + 0x14 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY6 + Source priority + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY7 + Source priority + 0x1c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY8 + Source priority + 0x20 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY9 + Source priority + 0x24 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY10 + Source priority + 0x28 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY11 + Source priority + 0x2c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY12 + Source priority + 0x30 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY13 + Source priority + 0x34 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY14 + Source priority + 0x38 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY15 + Source priority + 0x3c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY16 + Source priority + 0x40 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY17 + Source priority + 0x44 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY18 + Source priority + 0x48 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY19 + Source priority + 0x4c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY20 + Source priority + 0x50 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY21 + Source priority + 0x54 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY22 + Source priority + 0x58 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY23 + Source priority + 0x5c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY24 + Source priority + 0x60 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY25 + Source priority + 0x64 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY26 + Source priority + 0x68 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY27 + Source priority + 0x6c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY28 + Source priority + 0x70 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY29 + Source priority + 0x74 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY30 + Source priority + 0x78 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY31 + Source priority + 0x7c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY32 + Source priority + 0x80 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY33 + Source priority + 0x84 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY34 + Source priority + 0x88 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY35 + Source priority + 0x8c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY36 + Source priority + 0x90 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY37 + Source priority + 0x94 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY38 + Source priority + 0x98 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY39 + Source priority + 0x9c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY40 + Source priority + 0xa0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY41 + Source priority + 0xa4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY42 + Source priority + 0xa8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY43 + Source priority + 0xac + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY44 + Source priority + 0xb0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY45 + Source priority + 0xb4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY46 + Source priority + 0xb8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY47 + Source priority + 0xbc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY48 + Source priority + 0xc0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY49 + Source priority + 0xc4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY50 + Source priority + 0xc8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY51 + Source priority + 0xcc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY52 + Source priority + 0xd0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY53 + Source priority + 0xd4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY54 + Source priority + 0xd8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY55 + Source priority + 0xdc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY56 + Source priority + 0xe0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY57 + Source priority + 0xe4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY58 + Source priority + 0xe8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY59 + Source priority + 0xec + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY60 + Source priority + 0xf0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY61 + Source priority + 0xf4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY62 + Source priority + 0xf8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY63 + Source priority + 0xfc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY64 + Source priority + 0x100 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY65 + Source priority + 0x104 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY66 + Source priority + 0x108 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY67 + Source priority + 0x10c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY68 + Source priority + 0x110 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY69 + Source priority + 0x114 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY70 + Source priority + 0x118 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY71 + Source priority + 0x11c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY72 + Source priority + 0x120 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY73 + Source priority + 0x124 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY74 + Source priority + 0x128 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY75 + Source priority + 0x12c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY76 + Source priority + 0x130 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY77 + Source priority + 0x134 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY78 + Source priority + 0x138 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY79 + Source priority + 0x13c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY80 + Source priority + 0x140 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY81 + Source priority + 0x144 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY82 + Source priority + 0x148 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY83 + Source priority + 0x14c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY84 + Source priority + 0x150 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY85 + Source priority + 0x154 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY86 + Source priority + 0x158 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY87 + Source priority + 0x15c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY88 + Source priority + 0x160 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY89 + Source priority + 0x164 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY90 + Source priority + 0x168 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY91 + Source priority + 0x16c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY92 + Source priority + 0x170 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY93 + Source priority + 0x174 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY94 + Source priority + 0x178 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY95 + Source priority + 0x17c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY96 + Source priority + 0x180 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY97 + Source priority + 0x184 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY98 + Source priority + 0x188 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY99 + Source priority + 0x18c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY100 + Source priority + 0x190 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY101 + Source priority + 0x194 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY102 + Source priority + 0x198 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY103 + Source priority + 0x19c + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY104 + Source priority + 0x1a0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY105 + Source priority + 0x1a4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY106 + Source priority + 0x1a8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY107 + Source priority + 0x1ac + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY108 + Source priority + 0x1b0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY109 + Source priority + 0x1b4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY110 + Source priority + 0x1b8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY111 + Source priority + 0x1bc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY112 + Source priority + 0x1c0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY113 + Source priority + 0x1c4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY114 + Source priority + 0x1c8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY115 + Source priority + 0x1cc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY116 + Source priority + 0x1d0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY117 + Source priority + 0x1d4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY118 + Source priority + 0x1d8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY119 + Source priority + 0x1dc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY120 + Source priority + 0x1e0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY121 + Source priority + 0x1e4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY122 + Source priority + 0x1e8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY123 + Source priority + 0x1ec + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY124 + Source priority + 0x1f0 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY125 + Source priority + 0x1f4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY126 + Source priority + 0x1f8 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PRIORITY_PRIORITY127 + Source priority + 0x1fc + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + PENDING_PENDING0 + Pending status + 0x1000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + PENDING_PENDING1 + Pending status + 0x1004 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + PENDING_PENDING2 + Pending status + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + PENDING_PENDING3 + Pending status + 0x100c + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TRIGGER_TRIGGER0 + Trigger type + 0x1080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + TRIGGER_TRIGGER1 + Trigger type + 0x1084 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + TRIGGER_TRIGGER2 + Trigger type + 0x1088 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + TRIGGER_TRIGGER3 + Trigger type + 0x108c + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + NUMBER + Number of supported interrupt sources and targets + 0x1100 + 32 + 0xFFFFFFFF + + + NUM_TARGET + The number of supported targets + 16 + 16 + read-only + + + NUM_INTERRUPT + The number of supported interrupt sources + 0 + 16 + read-only + + + + + INFO + Version and the maximum priority + 0x1104 + 32 + 0xFFFFFFFF + + + MAX_PRIORITY + The maximum priority supported + 16 + 16 + read-only + + + VERSION + The version of the PLIC design + 0 + 16 + read-only + + + + + TARGETINT_TARGET0_INTEN_INTEN0 + machine interrupt enable + 0x2000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET0_INTEN_INTEN1 + machine interrupt enable + 0x2004 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET0_INTEN_INTEN2 + machine interrupt enable + 0x2008 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET0_INTEN_INTEN3 + machine interrupt enable + 0x200c + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET1_INTEN_INTEN0 + supervisor interrupt enable + 0x2080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET1_INTEN_INTEN1 + supervisor interrupt enable + 0x2084 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET1_INTEN_INTEN2 + supervisor interrupt enable + 0x2088 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETINT_TARGET1_INTEN_INTEN3 + supervisor interrupt enable + 0x208c + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + TARGETCONFIG_TARGET0_THRESHOLD + Target0 priority threshold + 0x200000 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + TARGETCONFIG_TARGET0_CLAIM + Target claim and complete + 0x200004 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + TARGETCONFIG_TARGET0_PPS + Preempted priority stack + 0x200400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + TARGETCONFIG_TARGET1_THRESHOLD + Target1 priority threshold + 0x201000 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + TARGETCONFIG_TARGET1_CLAIM + Target claim and complete + 0x201004 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + TARGETCONFIG_TARGET1_PPS + Preempted priority stack + 0x201400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + + + MCHTMR + MCHTMR + MCHTMR + 0xe6000000 + + 0x0 + 0x10 + registers + + + + MTIME + Machine Time + 0x0 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIME + Machine time + 0 + 64 + read-write + + + + + MTIMECMP + Machine Time Compare + 0x8 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIMECMP + Machine time compare + 0 + 64 + read-write + + + + + + + PLICSW + PLICSW + PLIC_SW + 0xe6400000 + + 0x1000 + 0x1ff008 + registers + + + + PENDING + Pending status + 0x1000 + 32 + 0x00000000 + 0x00000002 + + + INTERRUPT + writing 1 to trigger software interrupt + 1 + 1 + read-write + + + + + INTEN + Interrupt enable + 0x2000 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT + enable software interrupt + 0 + 1 + read-write + + + + + CLAIM + Claim and complete. + 0x200004 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 1 + read-write + + + + + + + GPIOM + GPIOM + GPIOM + 0xf0008000 + + 0x0 + 0x800 + registers + + + + ASSIGN_GPIOA_PIN_PIN00 + GPIO mananger + 0x0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN01 + GPIO mananger + 0x4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN02 + GPIO mananger + 0x8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN03 + GPIO mananger + 0xc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN04 + GPIO mananger + 0x10 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN05 + GPIO mananger + 0x14 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN06 + GPIO mananger + 0x18 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN07 + GPIO mananger + 0x1c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN08 + GPIO mananger + 0x20 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN09 + GPIO mananger + 0x24 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN10 + GPIO mananger + 0x28 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN11 + GPIO mananger + 0x2c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN12 + GPIO mananger + 0x30 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN13 + GPIO mananger + 0x34 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN14 + GPIO mananger + 0x38 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN15 + GPIO mananger + 0x3c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN16 + GPIO mananger + 0x40 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN17 + GPIO mananger + 0x44 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN18 + GPIO mananger + 0x48 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN19 + GPIO mananger + 0x4c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN20 + GPIO mananger + 0x50 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN21 + GPIO mananger + 0x54 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN22 + GPIO mananger + 0x58 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN23 + GPIO mananger + 0x5c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN24 + GPIO mananger + 0x60 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN25 + GPIO mananger + 0x64 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN26 + GPIO mananger + 0x68 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN27 + GPIO mananger + 0x6c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN28 + GPIO mananger + 0x70 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN29 + GPIO mananger + 0x74 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN30 + GPIO mananger + 0x78 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOA_PIN_PIN31 + GPIO mananger + 0x7c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN00 + GPIO mananger + 0x80 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN01 + GPIO mananger + 0x84 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN02 + GPIO mananger + 0x88 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN03 + GPIO mananger + 0x8c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN04 + GPIO mananger + 0x90 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN05 + GPIO mananger + 0x94 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN06 + GPIO mananger + 0x98 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN07 + GPIO mananger + 0x9c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN08 + GPIO mananger + 0xa0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN09 + GPIO mananger + 0xa4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN10 + GPIO mananger + 0xa8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN11 + GPIO mananger + 0xac + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN12 + GPIO mananger + 0xb0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN13 + GPIO mananger + 0xb4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN14 + GPIO mananger + 0xb8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN15 + GPIO mananger + 0xbc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN16 + GPIO mananger + 0xc0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN17 + GPIO mananger + 0xc4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN18 + GPIO mananger + 0xc8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN19 + GPIO mananger + 0xcc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN20 + GPIO mananger + 0xd0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN21 + GPIO mananger + 0xd4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN22 + GPIO mananger + 0xd8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN23 + GPIO mananger + 0xdc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN24 + GPIO mananger + 0xe0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN25 + GPIO mananger + 0xe4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN26 + GPIO mananger + 0xe8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN27 + GPIO mananger + 0xec + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN28 + GPIO mananger + 0xf0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN29 + GPIO mananger + 0xf4 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN30 + GPIO mananger + 0xf8 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOB_PIN_PIN31 + GPIO mananger + 0xfc + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN00 + GPIO mananger + 0x100 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN01 + GPIO mananger + 0x104 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN02 + GPIO mananger + 0x108 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN03 + GPIO mananger + 0x10c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN04 + GPIO mananger + 0x110 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN05 + GPIO mananger + 0x114 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN06 + GPIO mananger + 0x118 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN07 + GPIO mananger + 0x11c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN08 + GPIO mananger + 0x120 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN09 + GPIO mananger + 0x124 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN10 + GPIO mananger + 0x128 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN11 + GPIO mananger + 0x12c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN12 + GPIO mananger + 0x130 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN13 + GPIO mananger + 0x134 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN14 + GPIO mananger + 0x138 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN15 + GPIO mananger + 0x13c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN16 + GPIO mananger + 0x140 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN17 + GPIO mananger + 0x144 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN18 + GPIO mananger + 0x148 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN19 + GPIO mananger + 0x14c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN20 + GPIO mananger + 0x150 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN21 + GPIO mananger + 0x154 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN22 + GPIO mananger + 0x158 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN23 + GPIO mananger + 0x15c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN24 + GPIO mananger + 0x160 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN25 + GPIO mananger + 0x164 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN26 + GPIO mananger + 0x168 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOC_PIN_PIN27 + GPIO mananger + 0x16c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN00 + GPIO mananger + 0x680 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN01 + GPIO mananger + 0x684 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN02 + GPIO mananger + 0x688 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN03 + GPIO mananger + 0x68c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN04 + GPIO mananger + 0x690 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN05 + GPIO mananger + 0x694 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN06 + GPIO mananger + 0x698 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOX_PIN_PIN07 + GPIO mananger + 0x69c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN00 + GPIO mananger + 0x700 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN01 + GPIO mananger + 0x704 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN02 + GPIO mananger + 0x708 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN03 + GPIO mananger + 0x70c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN04 + GPIO mananger + 0x710 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN05 + GPIO mananger + 0x714 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN06 + GPIO mananger + 0x718 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOY_PIN_PIN07 + GPIO mananger + 0x71c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN00 + GPIO mananger + 0x780 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN01 + GPIO mananger + 0x784 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN02 + GPIO mananger + 0x788 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN03 + GPIO mananger + 0x78c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN04 + GPIO mananger + 0x790 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN05 + GPIO mananger + 0x794 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN06 + GPIO mananger + 0x798 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + ASSIGN_GPIOZ_PIN_PIN07 + GPIO mananger + 0x79c + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio +bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +1: soc gpio1; +2: cpu0 fastgpio +3: cpu1 fast gpio + 0 + 2 + read-write + + + + + + + ADC0 + ADC0 + ADC16 + 0xf0010000 + + 0x0 + 0x1464 + registers + + + + CONFIG_TRG0A + No description avaiable + 0x0 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG0B + No description avaiable + 0x4 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG0C + No description avaiable + 0x8 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG1A + No description avaiable + 0xc + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG1B + No description avaiable + 0x10 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG1C + No description avaiable + 0x14 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG2A + No description avaiable + 0x18 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG2B + No description avaiable + 0x1c + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG2C + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG3A + No description avaiable + 0x24 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG3B + No description avaiable + 0x28 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + CONFIG_TRG3C + No description avaiable + 0x2c + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + TRG_DMA_ADDR + No description avaiable + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 + read-write + + + + + BUS_RESULT_CHN0 + No description avaiable + 0x400 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN1 + No description avaiable + 0x404 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN2 + No description avaiable + 0x408 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN3 + No description avaiable + 0x40c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN4 + No description avaiable + 0x410 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN5 + No description avaiable + 0x414 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN6 + No description avaiable + 0x418 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN7 + No description avaiable + 0x41c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN8 + No description avaiable + 0x420 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN9 + No description avaiable + 0x424 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN10 + No description avaiable + 0x428 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN11 + No description avaiable + 0x42c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN12 + No description avaiable + 0x430 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN13 + No description avaiable + 0x434 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN14 + No description avaiable + 0x438 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUS_RESULT_CHN15 + No description avaiable + 0x43c + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + BUF_CFG0 + No description avaiable + 0x500 + 32 + 0x00000000 + 0x00000001 + + + WAIT_DIS + set to disable read waiting, get result immediately but maybe not current conversion result. + 0 + 1 + read-write + + + + + SEQ_CFG0 + No description avaiable + 0x800 + 32 + 0x00000000 + 0x80000F1F + + + CYCLE + current dma write cycle bit + 31 + 1 + read-only + + + SEQ_LEN + sequence queue length, 0 for one, 0xF for 16 + 8 + 4 + read-write + + + RESTART_EN + if set together with cont_en, HW will continue process the whole queue after trigger once. +If cont_en is 0, this bit is not used + 4 + 1 + read-write + + + CONT_EN + if set, HW will continue process the queue till end(seq_len) after trigger once + 3 + 1 + read-write + + + SW_TRIG + SW trigger, pulse signal, cleared by HW one cycle later + 2 + 1 + write-only + + + SW_TRIG_EN + set to enable SW trigger + 1 + 1 + read-write + + + HW_TRIG_EN + set to enable external HW trigger, only trigger on posedge + 0 + 1 + read-write + + + + + SEQ_DMA_ADDR + No description avaiable + 0x804 + 32 + 0x00000000 + 0xFFFFFFFC + + + TAR_ADDR + dma target address, should be 4-byte aligned + 2 + 30 + read-write + + + + + SEQ_WR_ADDR + No description avaiable + 0x808 + 32 + 0x00000000 + 0x00FFFFFF + + + SEQ_WR_POINTER + HW update this field after each dma write, it indicate the next dma write pointer. +dma write address is (tar_addr+seq_wr_pointer)*4 + 0 + 24 + read-only + + + + + SEQ_DMA_CFG + No description avaiable + 0x80c + 32 + 0x00000000 + 0x0FFF3FFF + + + STOP_POS + if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet + 16 + 12 + read-write + + + DMA_RST + set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. +SW should clear all cycle bit in buffer to 0 before clear dma_rst + 13 + 1 + read-write + + + STOP_EN + set to stop dma if reach the stop_pos + 12 + 1 + read-write + + + BUF_LEN + dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 +0 for 4byte; +0xFFF for 16kbyte. + 0 + 12 + read-write + + + + + SEQ_QUE_CFG0 + No description avaiable + 0x810 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG1 + No description avaiable + 0x814 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG2 + No description avaiable + 0x818 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG3 + No description avaiable + 0x81c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG4 + No description avaiable + 0x820 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG5 + No description avaiable + 0x824 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG6 + No description avaiable + 0x828 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG7 + No description avaiable + 0x82c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG8 + No description avaiable + 0x830 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG9 + No description avaiable + 0x834 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG10 + No description avaiable + 0x838 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG11 + No description avaiable + 0x83c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG12 + No description avaiable + 0x840 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG13 + No description avaiable + 0x844 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG14 + No description avaiable + 0x848 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + SEQ_QUE_CFG15 + No description avaiable + 0x84c + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + PRD_CFG_CHN0_PRD_CFG + No description avaiable + 0xc00 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN0_PRD_THSHD_CFG + No description avaiable + 0xc04 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN0_PRD_RESULT + No description avaiable + 0xc08 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN1_PRD_CFG + No description avaiable + 0xc10 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN1_PRD_THSHD_CFG + No description avaiable + 0xc14 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN1_PRD_RESULT + No description avaiable + 0xc18 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN2_PRD_CFG + No description avaiable + 0xc20 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN2_PRD_THSHD_CFG + No description avaiable + 0xc24 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN2_PRD_RESULT + No description avaiable + 0xc28 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN3_PRD_CFG + No description avaiable + 0xc30 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN3_PRD_THSHD_CFG + No description avaiable + 0xc34 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN3_PRD_RESULT + No description avaiable + 0xc38 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN4_PRD_CFG + No description avaiable + 0xc40 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN4_PRD_THSHD_CFG + No description avaiable + 0xc44 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN4_PRD_RESULT + No description avaiable + 0xc48 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN5_PRD_CFG + No description avaiable + 0xc50 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN5_PRD_THSHD_CFG + No description avaiable + 0xc54 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN5_PRD_RESULT + No description avaiable + 0xc58 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN6_PRD_CFG + No description avaiable + 0xc60 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN6_PRD_THSHD_CFG + No description avaiable + 0xc64 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN6_PRD_RESULT + No description avaiable + 0xc68 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN7_PRD_CFG + No description avaiable + 0xc70 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN7_PRD_THSHD_CFG + No description avaiable + 0xc74 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN7_PRD_RESULT + No description avaiable + 0xc78 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN8_PRD_CFG + No description avaiable + 0xc80 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN8_PRD_THSHD_CFG + No description avaiable + 0xc84 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN8_PRD_RESULT + No description avaiable + 0xc88 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN9_PRD_CFG + No description avaiable + 0xc90 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN9_PRD_THSHD_CFG + No description avaiable + 0xc94 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN9_PRD_RESULT + No description avaiable + 0xc98 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN10_PRD_CFG + No description avaiable + 0xca0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN10_PRD_THSHD_CFG + No description avaiable + 0xca4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN10_PRD_RESULT + No description avaiable + 0xca8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN11_PRD_CFG + No description avaiable + 0xcb0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN11_PRD_THSHD_CFG + No description avaiable + 0xcb4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN11_PRD_RESULT + No description avaiable + 0xcb8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN12_PRD_CFG + No description avaiable + 0xcc0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN12_PRD_THSHD_CFG + No description avaiable + 0xcc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN12_PRD_RESULT + No description avaiable + 0xcc8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN13_PRD_CFG + No description avaiable + 0xcd0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN13_PRD_THSHD_CFG + No description avaiable + 0xcd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN13_PRD_RESULT + No description avaiable + 0xcd8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN14_PRD_CFG + No description avaiable + 0xce0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN14_PRD_THSHD_CFG + No description avaiable + 0xce4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN14_PRD_RESULT + No description avaiable + 0xce8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + PRD_CFG_CHN15_PRD_CFG + No description avaiable + 0xcf0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + PRD_CFG_CHN15_PRD_THSHD_CFG + No description avaiable + 0xcf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + PRD_CFG_CHN15_PRD_RESULT + No description avaiable + 0xcf8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + SAMPLE_CFG_CHN0 + No description avaiable + 0x1000 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN1 + No description avaiable + 0x1004 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN2 + No description avaiable + 0x1008 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN3 + No description avaiable + 0x100c + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN4 + No description avaiable + 0x1010 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN5 + No description avaiable + 0x1014 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN6 + No description avaiable + 0x1018 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN7 + No description avaiable + 0x101c + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN8 + No description avaiable + 0x1020 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN9 + No description avaiable + 0x1024 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN10 + No description avaiable + 0x1028 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN11 + No description avaiable + 0x102c + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN12 + No description avaiable + 0x1030 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN13 + No description avaiable + 0x1034 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN14 + No description avaiable + 0x1038 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + SAMPLE_CFG_CHN15 + No description avaiable + 0x103c + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + CONV_CFG1 + No description avaiable + 0x1104 + 32 + 0x00000000 + 0x000001FF + + + CONVERT_CLOCK_NUMBER + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 22 adc clock cycles(based on clock after divider); +user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. +Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz). + 4 + 5 + read-write + + + CLOCK_DIVIDER + clock_period, N half clock cycle per half adc cycle +0 for same adc_clk and bus_clk, +1 for 1:2, +2 for 1:3, +... +15 for 1:16 +Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + 0 + 4 + read-write + + + + + ADC_CFG0 + No description avaiable + 0x1108 + 32 + 0x00000000 + 0xAFFFF001 + + + SEL_SYNC_AHB + set to 1 will enable sync AHB bus, to get better bus performance. +Adc_clk must to be set to same as bus clock at this mode + 31 + 1 + read-write + + + ADC_AHB_EN + set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + 29 + 1 + read-write + + + CONVERT_DURATION + for trigger queue, from trg_sample_req to trg_convert_req + 12 + 16 + read-write + + + PORT3_REALTIME + set to enable trg queue stop other queues + 0 + 1 + read-write + + + + + INT_STS + No description avaiable + 0x1110 + 32 + 0x00000000 + 0xFFE03FFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + write-only + + + TRIG_SW_CFLCT + No description avaiable + 30 + 1 + write-only + + + TRIG_HW_CFLCT + No description avaiable + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + write-only + + + SEQ_SW_CFLCT + sequence queue conflict interrup, set if HW or SW trigger received during conversion + 27 + 1 + write-only + + + SEQ_HW_CFLCT + No description avaiable + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + write-only + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + write-only + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + write-only + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 14 + write-only + + + + + INT_EN + No description avaiable + 0x1114 + 32 + 0x00000000 + 0xFFE03FFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + write-only + + + TRIG_SW_CFLCT + No description avaiable + 30 + 1 + write-only + + + TRIG_HW_CFLCT + No description avaiable + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + write-only + + + SEQ_SW_CFLCT + sequence queue conflict interrup, set if HW or SW trigger received during conversion + 27 + 1 + write-only + + + SEQ_HW_CFLCT + No description avaiable + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + write-only + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + write-only + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + write-only + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 14 + write-only + + + + + ANA_CTRL0 + No description avaiable + 0x1200 + 32 + 0x00000000 + 0x00001004 + + + ADC_CLK_ON + set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. +MUST set clock_period to 0 or 1 for adc16 reg access + 12 + 1 + read-write + + + STARTCAL + set to start the offset calibration cycle (Active H). user need to clear it after setting it. + 2 + 1 + read-write + + + + + ANA_STATUS + No description avaiable + 0x1210 + 32 + 0x00000000 + 0x00000080 + + + CALON + Indicates if the ADC is in calibration mode (Active H). + 7 + 1 + read-write + + + + + ADC16_PARAMS_ADC16_PARA00 + No description avaiable + 0x1400 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA01 + No description avaiable + 0x1402 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA02 + No description avaiable + 0x1404 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA03 + No description avaiable + 0x1406 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA04 + No description avaiable + 0x1408 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA05 + No description avaiable + 0x140a + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA06 + No description avaiable + 0x140c + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA07 + No description avaiable + 0x140e + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA08 + No description avaiable + 0x1410 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA09 + No description avaiable + 0x1412 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA10 + No description avaiable + 0x1414 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA11 + No description avaiable + 0x1416 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA12 + No description avaiable + 0x1418 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA13 + No description avaiable + 0x141a + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA14 + No description avaiable + 0x141c + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA15 + No description avaiable + 0x141e + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA16 + No description avaiable + 0x1420 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA17 + No description avaiable + 0x1422 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA18 + No description avaiable + 0x1424 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA19 + No description avaiable + 0x1426 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA20 + No description avaiable + 0x1428 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA21 + No description avaiable + 0x142a + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA22 + No description avaiable + 0x142c + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA23 + No description avaiable + 0x142e + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA24 + No description avaiable + 0x1430 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA25 + No description avaiable + 0x1432 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA26 + No description avaiable + 0x1434 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA27 + No description avaiable + 0x1436 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA28 + No description avaiable + 0x1438 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA29 + No description avaiable + 0x143a + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA30 + No description avaiable + 0x143c + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA31 + No description avaiable + 0x143e + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA32 + No description avaiable + 0x1440 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_PARAMS_ADC16_PARA33 + No description avaiable + 0x1442 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + ADC16_CONFIG0 + No description avaiable + 0x1444 + 32 + 0x00000000 + 0x03F07FFF + + + TEMPSNS_EN + set to enable temp senser + 25 + 1 + read-write + + + REG_EN + set to enable regulator + 24 + 1 + read-write + + + BANDGAP_EN + set to enable bandgap. user should set reg_en and bandgap_en before use adc16. + 23 + 1 + read-write + + + CAL_AVG_CFG + for average the calibration result. +0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; +4- 16 loops; 5-32 loops; others reserved + 20 + 3 + read-write + + + PREEMPT_EN + set to enable preemption feature + 14 + 1 + read-write + + + CONV_PARAM + convertion parameter + 0 + 14 + read-write + + + + + ADC16_CONFIG1 + No description avaiable + 0x1460 + 32 + 0x00000000 + 0x00001F00 + + + COV_END_CNT + used for faster conversion, user can change it to get higher convert speed(but less accuracy). +should set to (21-convert_clock_number+1). + 8 + 5 + read-write + + + + + + + ADC1 + ADC1 + ADC16 + 0xf0014000 + + + ADC2 + ADC2 + ADC16 + 0xf0018000 + + + SDM + SDM + SDM + 0xf001c000 + + 0x0 + 0x110 + registers + + + + CTRL + SDM control register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFE + + + SFTRST + software reset the module if asserted to be1’b1. + 31 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 5 + read-write + + + CHMD + Channel Rcv mode +Bits[2:0] for Ch0. +Bits[5:3] for Ch1 +Bits[8:6] for Ch2 +Bits[11:9] for Ch3 +3'b000: Capture at posedge of MCLK +3'b001: Capture at both posedge and negedge of MCLK +3'b010: Manchestor Mode +3'b011: Capture at negedge of MCLK +3'b100: Capture at every other posedge of MCLK +3'b101: Capture at every other negedge of MCLK +Others: Undefined + 14 + 12 + read-write + + + SYNC_MCLK + Asserted to double sync the mclk input pin before its usage inside the module + 10 + 4 + read-write + + + SYNC_MDAT + Asserted to double sync the mdat input pin before its usage inside the module + 6 + 4 + read-write + + + CH_EN + Channel Enable + 2 + 4 + read-write + + + IE + Interrupt Enable + 1 + 1 + read-write + + + + + INT_EN + Interrupt enable register. + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 8 + 24 + read-write + + + CH3DRY + Ch3 Data Ready interrupt enable. + 7 + 1 + read-write + + + CH2DRY + Ch2 Data Ready interrupt enable + 6 + 1 + read-write + + + CH1DRY + Ch1 Data Ready interrupt enable + 5 + 1 + read-write + + + CH0DRY + Ch0 Data Ready interrupt enable + 4 + 1 + read-write + + + CH3ERR + Ch3 Error interrupt enable. + 3 + 1 + read-write + + + CH2ERR + Ch2 Error interrupt enable + 2 + 1 + read-write + + + CH1ERR + Ch1 Error interrupt enable + 1 + 1 + read-write + + + CH0ERR + Ch0 Error interrupt enable + 0 + 1 + read-write + + + + + STATUS + Status Registers + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 8 + 24 + read-only + + + CH3DRY + Ch3 Data Ready. +De-assert this bit by reading the data (or data fifo) registers. + 7 + 1 + read-only + + + CH2DRY + Ch2 Data Ready + 6 + 1 + read-only + + + CH1DRY + Ch1 Data Ready + 5 + 1 + read-only + + + CH0DRY + Ch0 Data Ready + 4 + 1 + read-only + + + CH3ERR + Ch3 Error. +ORed together by channel related error signals and corresponding error interrupt enable signals. +De-assert this bit by write-1-clear the corresponding error status bits in the channel status registers. + 3 + 1 + read-only + + + CH2ERR + Ch2 Error + 2 + 1 + read-only + + + CH1ERR + Ch1 Error + 1 + 1 + read-only + + + CH0ERR + Ch0 Error + 0 + 1 + read-only + + + + + CH_0_SDFIFOCTRL + Data FIFO Path Control Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 9 + 23 + read-write + + + THRSH + FIFO threshold (0,..,16) (fillings > threshold, then gen int) + 4 + 5 + read-write + + + RESERVED + No description avaiable + 3 + 1 + read-write + + + D_RDY_INT_EN + FIFO data ready interrupt enable + 2 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 2 + read-write + + + + + CH_0_SDCTRLP + Data Path Control Primary Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + MANCH_THR + Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] + 25 + 7 + read-write + + + WDOG_THR + Watch dog threshold for channel failure of CLK halting + 17 + 8 + read-write + + + AF_IE + Acknowledge feedback interrupt enable + 16 + 1 + read-write + + + DFFOVIE + Ch Data FIFO overflow interrupt enable + 15 + 1 + read-write + + + DSATIE + Ch CIC Data Saturation Interrupt Enable + 14 + 1 + read-write + + + DRIE + Ch Data Ready Interrupt Enable + 13 + 1 + read-write + + + SYNCSEL + Select the PWM SYNC Source + 7 + 6 + read-write + + + FFSYNCCLREN + Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 + 6 + 1 + read-write + + + WTSYNACLR + 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen +0: WTSYNFLG should be cleared manually by WTSYNMCLR + 5 + 1 + read-write + + + WTSYNMCLR + 1: Manually clear WTSYNFLG. Auto-clear. + 4 + 1 + read-write + + + WTSYNCEN + 1: Start to store data only after PWM SYNC event +0: Start to store data whenever enabled + 3 + 1 + read-write + + + D32 + 1:32 bit data +0:16 bit data + 2 + 1 + read-write + + + DR_OPT + 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold +0: Use Data Reg Ready as data ready + 1 + 1 + read-write + + + EN + Data Path Enable + 0 + 1 + read-write + + + + + CH_0_SDCTRLE + Data Path Control Extra Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 19 + 13 + read-write + + + SGD_ORDR + CIC order +0: SYNC1 +1: SYNC2 +2: SYNC3 +3: FAST_SYNC + 17 + 2 + read-write + + + PWMSYNC + Asserted to double sync the PWM trigger signal + 16 + 1 + read-write + + + RESERVED + No description avaiable + 15 + 1 + read-write + + + CIC_SCL + CIC shift control + 11 + 4 + read-write + + + CIC_DEC_RATIO + CIC decimation ratio. 0 means div-by-256 + 3 + 8 + read-write + + + IGN_INI_SAMPLES + NotZero: Don't store the first samples that are not accurate +Zero: Store all samples + 0 + 3 + read-write + + + + + CH_0_SDST + Data Path Status + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 31 + 1 + read-only + + + PERIOD_MCLK + maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. + 23 + 8 + read-only + + + RESERVED + No description avaiable + 10 + 13 + read-only + + + FIFO_DR + FIFO data ready + 9 + 1 + write-only + + + AF + Achnowledge flag + 8 + 1 + write-only + + + DOV_ERR + Data FIFO Overflow Error. Error flag. + 7 + 1 + write-only + + + DSAT_ERR + CIC out Data saturation err. Error flag. + 6 + 1 + write-only + + + WTSYNFLG + Wait-for-sync event found + 5 + 1 + read-only + + + FILL + Data FIFO Fillings + 0 + 5 + read-only + + + + + CH_0_SDATA + Data + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Data + 0 + 32 + read-only + + + + + CH_0_SDFIFO + FIFO Data + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + FIFO Data + 0 + 32 + read-only + + + + + CH_0_SCAMP + instant Amplitude Results + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-only + + + VAL + instant Amplitude Results + 0 + 16 + read-only + + + + + CH_0_SCHTL + Amplitude Threshold for High Limit + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + VAL + Amplitude Threshold for High Limit + 0 + 16 + read-write + + + + + CH_0_SCHTLZ + Amplitude Threshold for zero crossing + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + VAL + Amplitude Threshold for zero crossing + 0 + 16 + read-write + + + + + CH_0_SCLLT + Amplitude Threshold for low limit + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + VAL + Amplitude Threshold for low limit + 0 + 16 + read-write + + + + + CH_0_SCCTRL + Amplitude Path Control + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 24 + 8 + read-write + + + HZ_EN + Zero Crossing Enable + 23 + 1 + read-write + + + MF_IE + Module failure Interrupt enable + 22 + 1 + read-write + + + HL_IE + HLT Interrupt Enable + 21 + 1 + read-write + + + LL_IE + LLT interrupt Enable + 20 + 1 + read-write + + + SGD_ORDR + CIC order +0: SYNC1 +1: SYNC2 +2: SYNC3 +3: FAST_SYNC + 18 + 2 + read-write + + + RESERVED + No description avaiable + 9 + 9 + read-write + + + CIC_DEC_RATIO + CIC decimation ratio. 0 means div-by-32 + 4 + 5 + read-write + + + IGN_INI_SAMPLES + NotZero: Ignore the first samples that are not accurate +Zero: Use all samples + 1 + 3 + read-write + + + EN + Amplitude Path Enable + 0 + 1 + read-write + + + + + CH_0_SCST + Amplitude Path Status + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 4 + 28 + read-only + + + HZ + Amplitude rising above HZ event found. + 3 + 1 + write-only + + + MF + power modulator Failure found. MCLK not found. Error flag. + 2 + 1 + write-only + + + CMPH + HLT out of range. Error flag. + 1 + 1 + write-only + + + CMPL + LLT out of range. Error flag. + 0 + 1 + write-only + + + + + CH_1_SDFIFOCTRL + Data FIFO Path Control Register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 9 + 23 + read-write + + + THRSH + FIFO threshold (0,..,16) (fillings > threshold, then gen int) + 4 + 5 + read-write + + + RESERVED + No description avaiable + 3 + 1 + read-write + + + D_RDY_INT_EN + FIFO data ready interrupt enable + 2 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 2 + read-write + + + + + CH_1_SDCTRLP + Data Path Control Primary Register + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + MANCH_THR + Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] + 25 + 7 + read-write + + + WDOG_THR + Watch dog threshold for channel failure of CLK halting + 17 + 8 + read-write + + + AF_IE + Acknowledge feedback interrupt enable + 16 + 1 + read-write + + + DFFOVIE + Ch Data FIFO overflow interrupt enable + 15 + 1 + read-write + + + DSATIE + Ch CIC Data Saturation Interrupt Enable + 14 + 1 + read-write + + + DRIE + Ch Data Ready Interrupt Enable + 13 + 1 + read-write + + + SYNCSEL + Select the PWM SYNC Source + 7 + 6 + read-write + + + FFSYNCCLREN + Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 + 6 + 1 + read-write + + + WTSYNACLR + 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen +0: WTSYNFLG should be cleared manually by WTSYNMCLR + 5 + 1 + read-write + + + WTSYNMCLR + 1: Manually clear WTSYNFLG. Auto-clear. + 4 + 1 + read-write + + + WTSYNCEN + 1: Start to store data only after PWM SYNC event +0: Start to store data whenever enabled + 3 + 1 + read-write + + + D32 + 1:32 bit data +0:16 bit data + 2 + 1 + read-write + + + DR_OPT + 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold +0: Use Data Reg Ready as data ready + 1 + 1 + read-write + + + EN + Data Path Enable + 0 + 1 + read-write + + + + + CH_1_SDCTRLE + Data Path Control Extra Register + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 19 + 13 + read-write + + + SGD_ORDR + CIC order +0: SYNC1 +1: SYNC2 +2: SYNC3 +3: FAST_SYNC + 17 + 2 + read-write + + + PWMSYNC + Asserted to double sync the PWM trigger signal + 16 + 1 + read-write + + + RESERVED + No description avaiable + 15 + 1 + read-write + + + CIC_SCL + CIC shift control + 11 + 4 + read-write + + + CIC_DEC_RATIO + CIC decimation ratio. 0 means div-by-256 + 3 + 8 + read-write + + + IGN_INI_SAMPLES + NotZero: Don't store the first samples that are not accurate +Zero: Store all samples + 0 + 3 + read-write + + + + + CH_1_SDST + Data Path Status + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 31 + 1 + read-only + + + PERIOD_MCLK + maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. + 23 + 8 + read-only + + + RESERVED + No description avaiable + 10 + 13 + read-only + + + FIFO_DR + FIFO data ready + 9 + 1 + write-only + + + AF + Achnowledge flag + 8 + 1 + write-only + + + DOV_ERR + Data FIFO Overflow Error. Error flag. + 7 + 1 + write-only + + + DSAT_ERR + CIC out Data saturation err. Error flag. + 6 + 1 + write-only + + + WTSYNFLG + Wait-for-sync event found + 5 + 1 + read-only + + + FILL + Data FIFO Fillings + 0 + 5 + read-only + + + + + CH_1_SDATA + Data + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Data + 0 + 32 + read-only + + + + + CH_1_SDFIFO + FIFO Data + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + FIFO Data + 0 + 32 + read-only + + + + + CH_1_SCAMP + instant Amplitude Results + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-only + + + VAL + instant Amplitude Results + 0 + 16 + read-only + + + + + CH_1_SCHTL + Amplitude Threshold for High Limit + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + VAL + Amplitude Threshold for High Limit + 0 + 16 + read-write + + + + + CH_1_SCHTLZ + Amplitude Threshold for zero crossing + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + VAL + Amplitude Threshold for zero crossing + 0 + 16 + read-write + + + + + CH_1_SCLLT + Amplitude Threshold for low limit + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + VAL + Amplitude Threshold for low limit + 0 + 16 + read-write + + + + + CH_1_SCCTRL + Amplitude Path Control + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 24 + 8 + read-write + + + HZ_EN + Zero Crossing Enable + 23 + 1 + read-write + + + MF_IE + Module failure Interrupt enable + 22 + 1 + read-write + + + HL_IE + HLT Interrupt Enable + 21 + 1 + read-write + + + LL_IE + LLT interrupt Enable + 20 + 1 + read-write + + + SGD_ORDR + CIC order +0: SYNC1 +1: SYNC2 +2: SYNC3 +3: FAST_SYNC + 18 + 2 + read-write + + + RESERVED + No description avaiable + 9 + 9 + read-write + + + CIC_DEC_RATIO + CIC decimation ratio. 0 means div-by-32 + 4 + 5 + read-write + + + IGN_INI_SAMPLES + NotZero: Ignore the first samples that are not accurate +Zero: Use all samples + 1 + 3 + read-write + + + EN + Amplitude Path Enable + 0 + 1 + read-write + + + + + CH_1_SCST + Amplitude Path Status + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 4 + 28 + read-only + + + HZ + Amplitude rising above HZ event found. + 3 + 1 + write-only + + + MF + power modulator Failure found. MCLK not found. Error flag. + 2 + 1 + write-only + + + CMPH + HLT out of range. Error flag. + 1 + 1 + write-only + + + CMPL + LLT out of range. Error flag. + 0 + 1 + write-only + + + + + CH_2_SDFIFOCTRL + Data FIFO Path Control Register + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 9 + 23 + read-write + + + THRSH + FIFO threshold (0,..,16) (fillings > threshold, then gen int) + 4 + 5 + read-write + + + RESERVED + No description avaiable + 3 + 1 + read-write + + + D_RDY_INT_EN + FIFO data ready interrupt enable + 2 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 2 + read-write + + + + + CH_2_SDCTRLP + Data Path Control Primary Register + 0x94 + 32 + 0x00000000 + 0xFFFFFFFF + + + MANCH_THR + Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] + 25 + 7 + read-write + + + WDOG_THR + Watch dog threshold for channel failure of CLK halting + 17 + 8 + read-write + + + AF_IE + Acknowledge feedback interrupt enable + 16 + 1 + read-write + + + DFFOVIE + Ch Data FIFO overflow interrupt enable + 15 + 1 + read-write + + + DSATIE + Ch CIC Data Saturation Interrupt Enable + 14 + 1 + read-write + + + DRIE + Ch Data Ready Interrupt Enable + 13 + 1 + read-write + + + SYNCSEL + Select the PWM SYNC Source + 7 + 6 + read-write + + + FFSYNCCLREN + Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 + 6 + 1 + read-write + + + WTSYNACLR + 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen +0: WTSYNFLG should be cleared manually by WTSYNMCLR + 5 + 1 + read-write + + + WTSYNMCLR + 1: Manually clear WTSYNFLG. Auto-clear. + 4 + 1 + read-write + + + WTSYNCEN + 1: Start to store data only after PWM SYNC event +0: Start to store data whenever enabled + 3 + 1 + read-write + + + D32 + 1:32 bit data +0:16 bit data + 2 + 1 + read-write + + + DR_OPT + 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold +0: Use Data Reg Ready as data ready + 1 + 1 + read-write + + + EN + Data Path Enable + 0 + 1 + read-write + + + + + CH_2_SDCTRLE + Data Path Control Extra Register + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 19 + 13 + read-write + + + SGD_ORDR + CIC order +0: SYNC1 +1: SYNC2 +2: SYNC3 +3: FAST_SYNC + 17 + 2 + read-write + + + PWMSYNC + Asserted to double sync the PWM trigger signal + 16 + 1 + read-write + + + RESERVED + No description avaiable + 15 + 1 + read-write + + + CIC_SCL + CIC shift control + 11 + 4 + read-write + + + CIC_DEC_RATIO + CIC decimation ratio. 0 means div-by-256 + 3 + 8 + read-write + + + IGN_INI_SAMPLES + NotZero: Don't store the first samples that are not accurate +Zero: Store all samples + 0 + 3 + read-write + + + + + CH_2_SDST + Data Path Status + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 31 + 1 + read-only + + + PERIOD_MCLK + maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. + 23 + 8 + read-only + + + RESERVED + No description avaiable + 10 + 13 + read-only + + + FIFO_DR + FIFO data ready + 9 + 1 + write-only + + + AF + Achnowledge flag + 8 + 1 + write-only + + + DOV_ERR + Data FIFO Overflow Error. Error flag. + 7 + 1 + write-only + + + DSAT_ERR + CIC out Data saturation err. Error flag. + 6 + 1 + write-only + + + WTSYNFLG + Wait-for-sync event found + 5 + 1 + read-only + + + FILL + Data FIFO Fillings + 0 + 5 + read-only + + + + + CH_2_SDATA + Data + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Data + 0 + 32 + read-only + + + + + CH_2_SDFIFO + FIFO Data + 0xa4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + FIFO Data + 0 + 32 + read-only + + + + + CH_2_SCAMP + instant Amplitude Results + 0xa8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-only + + + VAL + instant Amplitude Results + 0 + 16 + read-only + + + + + CH_2_SCHTL + Amplitude Threshold for High Limit + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + VAL + Amplitude Threshold for High Limit + 0 + 16 + read-write + + + + + CH_2_SCHTLZ + Amplitude Threshold for zero crossing + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + VAL + Amplitude Threshold for zero crossing + 0 + 16 + read-write + + + + + CH_2_SCLLT + Amplitude Threshold for low limit + 0xb4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + VAL + Amplitude Threshold for low limit + 0 + 16 + read-write + + + + + CH_2_SCCTRL + Amplitude Path Control + 0xb8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 24 + 8 + read-write + + + HZ_EN + Zero Crossing Enable + 23 + 1 + read-write + + + MF_IE + Module failure Interrupt enable + 22 + 1 + read-write + + + HL_IE + HLT Interrupt Enable + 21 + 1 + read-write + + + LL_IE + LLT interrupt Enable + 20 + 1 + read-write + + + SGD_ORDR + CIC order +0: SYNC1 +1: SYNC2 +2: SYNC3 +3: FAST_SYNC + 18 + 2 + read-write + + + RESERVED + No description avaiable + 9 + 9 + read-write + + + CIC_DEC_RATIO + CIC decimation ratio. 0 means div-by-32 + 4 + 5 + read-write + + + IGN_INI_SAMPLES + NotZero: Ignore the first samples that are not accurate +Zero: Use all samples + 1 + 3 + read-write + + + EN + Amplitude Path Enable + 0 + 1 + read-write + + + + + CH_2_SCST + Amplitude Path Status + 0xbc + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 4 + 28 + read-only + + + HZ + Amplitude rising above HZ event found. + 3 + 1 + write-only + + + MF + power modulator Failure found. MCLK not found. Error flag. + 2 + 1 + write-only + + + CMPH + HLT out of range. Error flag. + 1 + 1 + write-only + + + CMPL + LLT out of range. Error flag. + 0 + 1 + write-only + + + + + CH_3_SDFIFOCTRL + Data FIFO Path Control Register + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 9 + 23 + read-write + + + THRSH + FIFO threshold (0,..,16) (fillings > threshold, then gen int) + 4 + 5 + read-write + + + RESERVED + No description avaiable + 3 + 1 + read-write + + + D_RDY_INT_EN + FIFO data ready interrupt enable + 2 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 2 + read-write + + + + + CH_3_SDCTRLP + Data Path Control Primary Register + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + MANCH_THR + Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] + 25 + 7 + read-write + + + WDOG_THR + Watch dog threshold for channel failure of CLK halting + 17 + 8 + read-write + + + AF_IE + Acknowledge feedback interrupt enable + 16 + 1 + read-write + + + DFFOVIE + Ch Data FIFO overflow interrupt enable + 15 + 1 + read-write + + + DSATIE + Ch CIC Data Saturation Interrupt Enable + 14 + 1 + read-write + + + DRIE + Ch Data Ready Interrupt Enable + 13 + 1 + read-write + + + SYNCSEL + Select the PWM SYNC Source + 7 + 6 + read-write + + + FFSYNCCLREN + Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 + 6 + 1 + read-write + + + WTSYNACLR + 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen +0: WTSYNFLG should be cleared manually by WTSYNMCLR + 5 + 1 + read-write + + + WTSYNMCLR + 1: Manually clear WTSYNFLG. Auto-clear. + 4 + 1 + read-write + + + WTSYNCEN + 1: Start to store data only after PWM SYNC event +0: Start to store data whenever enabled + 3 + 1 + read-write + + + D32 + 1:32 bit data +0:16 bit data + 2 + 1 + read-write + + + DR_OPT + 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold +0: Use Data Reg Ready as data ready + 1 + 1 + read-write + + + EN + Data Path Enable + 0 + 1 + read-write + + + + + CH_3_SDCTRLE + Data Path Control Extra Register + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 19 + 13 + read-write + + + SGD_ORDR + CIC order +0: SYNC1 +1: SYNC2 +2: SYNC3 +3: FAST_SYNC + 17 + 2 + read-write + + + PWMSYNC + Asserted to double sync the PWM trigger signal + 16 + 1 + read-write + + + RESERVED + No description avaiable + 15 + 1 + read-write + + + CIC_SCL + CIC shift control + 11 + 4 + read-write + + + CIC_DEC_RATIO + CIC decimation ratio. 0 means div-by-256 + 3 + 8 + read-write + + + IGN_INI_SAMPLES + NotZero: Don't store the first samples that are not accurate +Zero: Store all samples + 0 + 3 + read-write + + + + + CH_3_SDST + Data Path Status + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 31 + 1 + read-only + + + PERIOD_MCLK + maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. + 23 + 8 + read-only + + + RESERVED + No description avaiable + 10 + 13 + read-only + + + FIFO_DR + FIFO data ready + 9 + 1 + write-only + + + AF + Achnowledge flag + 8 + 1 + write-only + + + DOV_ERR + Data FIFO Overflow Error. Error flag. + 7 + 1 + write-only + + + DSAT_ERR + CIC out Data saturation err. Error flag. + 6 + 1 + write-only + + + WTSYNFLG + Wait-for-sync event found + 5 + 1 + read-only + + + FILL + Data FIFO Fillings + 0 + 5 + read-only + + + + + CH_3_SDATA + Data + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + Data + 0 + 32 + read-only + + + + + CH_3_SDFIFO + FIFO Data + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + FIFO Data + 0 + 32 + read-only + + + + + CH_3_SCAMP + instant Amplitude Results + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-only + + + VAL + instant Amplitude Results + 0 + 16 + read-only + + + + + CH_3_SCHTL + Amplitude Threshold for High Limit + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + VAL + Amplitude Threshold for High Limit + 0 + 16 + read-write + + + + + CH_3_SCHTLZ + Amplitude Threshold for zero crossing + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + VAL + Amplitude Threshold for zero crossing + 0 + 16 + read-write + + + + + CH_3_SCLLT + Amplitude Threshold for low limit + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + VAL + Amplitude Threshold for low limit + 0 + 16 + read-write + + + + + CH_3_SCCTRL + Amplitude Path Control + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 24 + 8 + read-write + + + HZ_EN + Zero Crossing Enable + 23 + 1 + read-write + + + MF_IE + Module failure Interrupt enable + 22 + 1 + read-write + + + HL_IE + HLT Interrupt Enable + 21 + 1 + read-write + + + LL_IE + LLT interrupt Enable + 20 + 1 + read-write + + + SGD_ORDR + CIC order +0: SYNC1 +1: SYNC2 +2: SYNC3 +3: FAST_SYNC + 18 + 2 + read-write + + + RESERVED + No description avaiable + 9 + 9 + read-write + + + CIC_DEC_RATIO + CIC decimation ratio. 0 means div-by-32 + 4 + 5 + read-write + + + IGN_INI_SAMPLES + NotZero: Ignore the first samples that are not accurate +Zero: Use all samples + 1 + 3 + read-write + + + EN + Amplitude Path Enable + 0 + 1 + read-write + + + + + CH_3_SCST + Amplitude Path Status + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 4 + 28 + read-only + + + HZ + Amplitude rising above HZ event found. + 3 + 1 + write-only + + + MF + power modulator Failure found. MCLK not found. Error flag. + 2 + 1 + write-only + + + CMPH + HLT out of range. Error flag. + 1 + 1 + write-only + + + CMPL + LLT out of range. Error flag. + 0 + 1 + write-only + + + + + + + ACMP + ACMP + ACMP + 0xf0020000 + + 0x0 + 0x80 + registers + + + + CHANNEL_CHN0_CFG + Configure Register + 0x0 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + CHANNEL_CHN0_DACCFG + DAC configure register + 0x4 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + CHANNEL_CHN0_SR + Status register + 0x10 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + CHANNEL_CHN0_IRQEN + Interrupt request enable register + 0x14 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN0_DMAEN + DMA request enable register + 0x18 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN1_CFG + Configure Register + 0x20 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + CHANNEL_CHN1_DACCFG + DAC configure register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + CHANNEL_CHN1_SR + Status register + 0x30 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + CHANNEL_CHN1_IRQEN + Interrupt request enable register + 0x34 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN1_DMAEN + DMA request enable register + 0x38 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN2_CFG + Configure Register + 0x40 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + CHANNEL_CHN2_DACCFG + DAC configure register + 0x44 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + CHANNEL_CHN2_SR + Status register + 0x50 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + CHANNEL_CHN2_IRQEN + Interrupt request enable register + 0x54 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN2_DMAEN + DMA request enable register + 0x58 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN3_CFG + Configure Register + 0x60 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + CHANNEL_CHN3_DACCFG + DAC configure register + 0x64 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + CHANNEL_CHN3_SR + Status register + 0x70 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + CHANNEL_CHN3_IRQEN + Interrupt request enable register + 0x74 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + CHANNEL_CHN3_DMAEN + DMA request enable register + 0x78 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + + + DAC0 + DAC0 + DAC + 0xf0024000 + + 0x0 + 0x4c + registers + + + + CFG0 + No description avaiable + 0x0 + 32 + 0x00000000 + 0x0FFF03FF + + + SW_DAC_DATA + dac data used in direct mode(dac_mode==2'b10) + 16 + 12 + write-only + + + DMA_AHB_EN + set to enable internal DMA, it will read one burst if enough space in FIFO. +Should only be used in buffer mode. + 9 + 1 + write-only + + + SYNC_MODE + 1: sync dac clock and ahb clock. + all HW trigger signals are pulse in sync mode, can get faster response; +0: async dac clock and ahb_clock + all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + 8 + 1 + write-only + + + TRIG_MODE + 0: single mode, one trigger pulse will send one 12bit data to DAC analog; +1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + 7 + 1 + write-only + + + HW_TRIG_EN + set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + 6 + 1 + write-only + + + DAC_MODE + 00: direct mode, DAC output the fixed configured data(from sw_dac_data) +01: step mode, DAC output from start_point to end point, with configured step, can step up or step down +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; + 4 + 2 + write-only + + + BUF_DATA_MODE + data structure for buffer mode, +0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. +1: each 32-bit data contains 1 point, b11:0 for first + 3 + 1 + write-only + + + HBURST_CFG + DAC support following fixed burst only +000-SINGLE; 011-INCR4; 101: INCR8 +others are reserved + 0 + 3 + write-only + + + + + CFG1 + No description avaiable + 0x4 + 32 + 0x00010000 + 0x0007FFFF + + + ANA_CLK_EN + set to enable analog clock(divided by ana_div_cfg) + 18 + 1 + read-write + + + ANA_DIV_CFG + clock divider config for ana_clk to dac analog; +00: div2 +01: div4 +10: div6 +11: div8 + 16 + 2 + read-write + + + DIV_CFG + how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. +Used for step mode and buffer mode, if set to continual trigger mode + 0 + 16 + read-write + + + + + CFG2 + No description avaiable + 0x8 + 32 + 0x00000000 + 0x000000FF + + + DMA_RST1 + set to reset dma read pointer to buf1_start_addr; +if set both dma_rst0&dma_rst1, will set to buf0_start_addr +user can set fifo_clr bit when use dma_rst* + 7 + 1 + write-only + + + DMA_RST0 + set to reset dma read pointer to buf0_start_addr + 6 + 1 + write-only + + + FIFO_CLR + set to clear FIFO content(set both read/write pointer to 0) + 5 + 1 + write-only + + + BUF_SW_TRIG + software trigger for buffer mode, +W1C in single mode. +RW in continual mode + 4 + 1 + read-write + + + STEP_SW_TRIG3 + No description avaiable + 3 + 1 + read-write + + + STEP_SW_TRIG2 + No description avaiable + 2 + 1 + read-write + + + STEP_SW_TRIG1 + No description avaiable + 1 + 1 + read-write + + + STEP_SW_TRIG0 + software trigger0 for step mode, +W1C in single mode. +RW in continual mode + 0 + 1 + read-write + + + + + STEP_CFG_STEP0 + No description avaiable + 0x10 + 32 + 0x00000000 + 0x3FFFFFFF + + + ROUND_MODE + 0: stop at end point; +1: reload start point, step again + 29 + 1 + read-write + + + UP_DOWN + 0 for up, 1 for down + 28 + 1 + read-write + + + END_POINT + No description avaiable + 16 + 12 + read-write + + + STEP_NUM + output data change step_num each DAC clock cycle. +Ex: if step_num=3, output data sequence is 0,3,6,9 +NOTE: user should make sure end_point can be reached if step_num is not 1 +if step_num is 0, output data will always at start point + 12 + 4 + read-write + + + START_POINT + No description avaiable + 0 + 12 + read-write + + + + + STEP_CFG_STEP1 + No description avaiable + 0x14 + 32 + 0x00000000 + 0x3FFFFFFF + + + ROUND_MODE + 0: stop at end point; +1: reload start point, step again + 29 + 1 + read-write + + + UP_DOWN + 0 for up, 1 for down + 28 + 1 + read-write + + + END_POINT + No description avaiable + 16 + 12 + read-write + + + STEP_NUM + output data change step_num each DAC clock cycle. +Ex: if step_num=3, output data sequence is 0,3,6,9 +NOTE: user should make sure end_point can be reached if step_num is not 1 +if step_num is 0, output data will always at start point + 12 + 4 + read-write + + + START_POINT + No description avaiable + 0 + 12 + read-write + + + + + STEP_CFG_STEP2 + No description avaiable + 0x18 + 32 + 0x00000000 + 0x3FFFFFFF + + + ROUND_MODE + 0: stop at end point; +1: reload start point, step again + 29 + 1 + read-write + + + UP_DOWN + 0 for up, 1 for down + 28 + 1 + read-write + + + END_POINT + No description avaiable + 16 + 12 + read-write + + + STEP_NUM + output data change step_num each DAC clock cycle. +Ex: if step_num=3, output data sequence is 0,3,6,9 +NOTE: user should make sure end_point can be reached if step_num is not 1 +if step_num is 0, output data will always at start point + 12 + 4 + read-write + + + START_POINT + No description avaiable + 0 + 12 + read-write + + + + + STEP_CFG_STEP3 + No description avaiable + 0x1c + 32 + 0x00000000 + 0x3FFFFFFF + + + ROUND_MODE + 0: stop at end point; +1: reload start point, step again + 29 + 1 + read-write + + + UP_DOWN + 0 for up, 1 for down + 28 + 1 + read-write + + + END_POINT + No description avaiable + 16 + 12 + read-write + + + STEP_NUM + output data change step_num each DAC clock cycle. +Ex: if step_num=3, output data sequence is 0,3,6,9 +NOTE: user should make sure end_point can be reached if step_num is not 1 +if step_num is 0, output data will always at start point + 12 + 4 + read-write + + + START_POINT + No description avaiable + 0 + 12 + read-write + + + + + BUF_ADDR_BUF0 + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFFFFFFFD + + + BUF_START_ADDR + buffer start address, should be 4-byte aligned +AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. + 2 + 30 + read-write + + + BUF_STOP + set to stop read point at end of bufffer0 + 0 + 1 + read-write + + + + + BUF_ADDR_BUF1 + No description avaiable + 0x24 + 32 + 0x00000000 + 0xFFFFFFFD + + + BUF_START_ADDR + buffer start address, should be 4-byte aligned +AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. + 2 + 30 + read-write + + + BUF_STOP + set to stop read point at end of bufffer0 + 0 + 1 + read-write + + + + + BUF_LENGTH + No description avaiable + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + BUF1_LEN + buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer + 16 + 16 + read-write + + + BUF0_LEN + No description avaiable + 0 + 16 + read-write + + + + + IRQ_STS + No description avaiable + 0x30 + 32 + 0x00000000 + 0x0000001F + + + STEP_CMPT + No description avaiable + 4 + 1 + write-only + + + AHB_ERROR + set if hresp==2'b01(ERROR) + 3 + 1 + write-only + + + FIFO_EMPTY + No description avaiable + 2 + 1 + write-only + + + BUF1_CMPT + No description avaiable + 1 + 1 + write-only + + + BUF0_CMPT + No description avaiable + 0 + 1 + write-only + + + + + IRQ_EN + No description avaiable + 0x34 + 32 + 0x00000000 + 0x0000001F + + + STEP_CMPT + No description avaiable + 4 + 1 + read-write + + + AHB_ERROR + No description avaiable + 3 + 1 + read-write + + + FIFO_EMPTY + No description avaiable + 2 + 1 + read-write + + + BUF1_CMPT + No description avaiable + 1 + 1 + read-write + + + BUF0_CMPT + No description avaiable + 0 + 1 + read-write + + + + + DMA_EN + No description avaiable + 0x38 + 32 + 0x00000000 + 0x00000013 + + + STEP_CMPT + No description avaiable + 4 + 1 + read-write + + + BUF1_CMPT + No description avaiable + 1 + 1 + read-write + + + BUF0_CMPT + No description avaiable + 0 + 1 + read-write + + + + + ANA_CFG0 + No description avaiable + 0x40 + 32 + 0x00000030 + 0x000001FF + + + DAC12BIT_LP_MODE + No description avaiable + 8 + 1 + read-write + + + DAC_CONFIG + No description avaiable + 4 + 4 + read-write + + + CALI_DELTA_V_CFG + No description avaiable + 2 + 2 + read-write + + + BYPASS_CALI_GM + No description avaiable + 1 + 1 + read-write + + + DAC12BIT_EN + No description avaiable + 0 + 1 + read-write + + + + + CFG0_BAK + No description avaiable + 0x44 + 32 + 0x00000000 + 0x0FFF03FF + + + SW_DAC_DATA + dac data used in direct mode(dac_mode==2'b10) + 16 + 12 + read-write + + + DMA_AHB_EN + set to enable internal DMA, it will read one burst if enough space in FIFO. +Should only be used in buffer mode. + 9 + 1 + read-write + + + SYNC_MODE + 1: sync dac clock and ahb clock. + all HW trigger signals are pulse in sync mode, can get faster response; +0: async dac clock and ahb_clock + all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + 8 + 1 + read-write + + + TRIG_MODE + 0: single mode, one trigger pulse will send one 12bit data to DAC analog; +1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + 7 + 1 + read-write + + + HW_TRIG_EN + set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + 6 + 1 + read-write + + + DAC_MODE + 00: direct mode, DAC output the fixed configured data(from sw_dac_data) +01: step mode, DAC output from start_point to end point, with configured step, can step up or step down +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; + 4 + 2 + read-write + + + BUF_DATA_MODE + data structure for buffer mode, +0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. +1: each 32-bit data contains 1 point, b11:0 for first + 3 + 1 + read-write + + + HBURST_CFG + DAC support following fixed burst only +000-SINGLE; 011-INCR4; 101: INCR8 +others are reserved + 0 + 3 + read-write + + + + + STATUS0 + No description avaiable + 0x48 + 32 + 0x00000000 + 0x00FFFF80 + + + CUR_BUF_OFFSET + No description avaiable + 8 + 16 + read-write + + + CUR_BUF_INDEX + No description avaiable + 7 + 1 + read-write + + + + + + + DAC1 + DAC1 + DAC + 0xf0028000 + + + SPI0 + SPI0 + SPI + 0xf0030000 + + 0x0 + 0x80 + registers + + + + TRANSFMT + Transfer Format Register + 0x10 + 32 + 0x00020780 + 0xFFFF1F9F + + + RESERVED + No description avaiable + 18 + 14 + read-write + + + ADDRLEN + Address length in bytes +0x0: 1 byte +0x1: 2 bytes +0x2: 3 bytes +0x3: 4 bytes + 16 + 2 + read-write + + + DATALEN + The length of each data unit in bits +The actual bit number of a data unit is (DataLen + 1) + 8 + 5 + read-write + + + DATAMERGE + Enable Data Merge mode, which does automatic data split on write and data coalescing on read. +This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. +When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. + 7 + 1 + read-write + + + MOSIBIDIR + Bi-directional MOSI in regular (single) mode +0x0: MOSI is uni-directional signal in regular mode. +0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two + 4 + 1 + read-write + + + LSB + Transfer data with the least significant bit first +0x0: Most significant bit first +0x1: Least significant bit first + 3 + 1 + read-write + + + SLVMODE + SPI Master/Slave mode selection +0x0: Master mode +0x1: Slave mode + 2 + 1 + read-write + + + CPOL + SPI Clock Polarity +0x0: SCLK is LOW in the idle states +0x1: SCLK is HIGH in the idle states + 1 + 1 + read-write + + + CPHA + SPI Clock Phase +0x0: Sampling data at odd SCLK edges +0x1: Sampling data at even SCLK edges + 0 + 1 + read-write + + + + + DIRECTIO + Direct IO Control Register + 0x14 + 32 + 0x00003100 + 0x013F3F3F + + + DIRECTIOEN + Enable Direct IO +0x0: Disable +0x1: Enable + 24 + 1 + read-write + + + HOLD_OE + Output enable for the SPI Flash hold signal + 21 + 1 + read-write + + + WP_OE + Output enable for the SPI Flash write protect signal + 20 + 1 + read-write + + + MISO_OE + Output enable fo the SPI MISO signal + 19 + 1 + read-write + + + MOSI_OE + Output enable for the SPI MOSI signal + 18 + 1 + read-write + + + SCLK_OE + Output enable for the SPI SCLK signal + 17 + 1 + read-write + + + CS_OE + Output enable for SPI CS (chip select) signal + 16 + 1 + read-write + + + HOLD_O + Output value for the SPI Flash hold signal + 13 + 1 + read-write + + + WP_O + Output value for the SPI Flash write protect signal + 12 + 1 + read-write + + + MISO_O + Output value for the SPI MISO signal + 11 + 1 + read-write + + + MOSI_O + Output value for the SPI MOSI signal + 10 + 1 + read-write + + + SCLK_O + Output value for the SPI SCLK signal + 9 + 1 + read-write + + + CS_O + Output value for the SPI CS (chip select) signal + 8 + 1 + read-write + + + HOLD_I + Status of the SPI Flash hold signal + 5 + 1 + read-only + + + WP_I + Status of the SPI Flash write protect signal + 4 + 1 + read-only + + + MISO_I + Status of the SPI MISO signal + 3 + 1 + read-only + + + MOSI_I + Status of the SPI MOSI signal + 2 + 1 + read-only + + + SCLK_I + Status of the SPI SCLK signal + 1 + 1 + read-only + + + CS_I + Status of the SPI CS (chip select) signal + 0 + 1 + read-only + + + + + TRANSCTRL + Transfer Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLVDATAONLY + Data-only mode (slave mode only) +0x0: Disable the data-only mode +0x1: Enable the data-only mode +Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. + 31 + 1 + read-write + + + CMDEN + SPI command phase enable (Master mode only) +0x0: Disable the command phase +0x1: Enable the command phase + 30 + 1 + read-write + + + ADDREN + SPI address phase enable (Master mode only) +0x0: Disable the address phase +0x1: Enable the address phase + 29 + 1 + read-write + + + ADDRFMT + SPI address phase format (Master mode only) +0x0: Address phase is the regular (single) mode +0x1: The format of the address phase is the same as the data phase (DualQuad). + 28 + 1 + read-write + + + TRANSMODE + Transfer mode +The transfer sequence could be +0x0: Write and read at the same time +0x1: Write only +0x2: Read only +0x3: Write, Read +0x4: Read, Write +0x5: Write, Dummy, Read +0x6: Read, Dummy, Write +0x7: None Data (must enable CmdEn or AddrEn in master mode) +0x8: Dummy, Write +0x9: Dummy, Read +0xa~0xf: Reserved + 24 + 4 + read-write + + + DUALQUAD + SPI data phase format +0x0: Regular (Single) mode +0x1: Dual I/O mode +0x2: Quad I/O mode +0x3: Reserved + 22 + 2 + read-write + + + TOKENEN + Token transfer enable (Master mode only) +Append an one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. +0x0: Disable the one-byte special token +0x1: Enable the one-byte special token + 21 + 1 + read-write + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 12 + 9 + read-write + + + TOKENVALUE + Token value (Master mode only) +The value of the one-byte special token following the address phase for SPI read transfers. +0x0: token value = 0x00 +0x1: token value = 0x69 + 11 + 1 + read-write + + + DUMMYCNT + Dummy data count. The actual dummy count is (DummyCnt +1). +The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) +The Data pins are put into the high impedance during the dummy data phase. +DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. + 9 + 2 + read-write + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 9 + read-write + + + + + CMD + Command Register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + CMD + SPI Command + 0 + 8 + read-write + + + + + ADDR + Address Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + SPI Address +(Master mode only) + 0 + 32 + read-write + + + + + DATA + Data Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Data to transmit or the received data +For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. +If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. + 0 + 32 + read-write + + + + + CTRL + Control Register + 0x30 + 32 + 0x00000000 + 0x00FFFF1F + + + TXTHRES + Transmit (TX) FIFO Threshold +The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. + 16 + 8 + read-write + + + RXTHRES + Receive (RX) FIFO Threshold +The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. + 8 + 8 + read-write + + + TXDMAEN + TX DMA enable + 4 + 1 + read-write + + + RXDMAEN + RX DMA enable + 3 + 1 + read-write + + + TXFIFORST + Transmit FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 2 + 1 + read-write + + + RXFIFORST + Receive FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 1 + 1 + read-write + + + SPIRST + SPI reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 0 + 1 + read-write + + + + + STATUS + Status Register + 0x34 + 32 + 0x00000000 + 0x33FFFF01 + + + TXNUM_7_6 + Number of valid entries in the Transmit FIFO + 28 + 2 + read-only + + + RXNUM_7_6 + Number of valid entries in the Receive FIFO + 24 + 2 + read-only + + + TXFULL + Transmit FIFO Full flag + 23 + 1 + read-only + + + TXEMPTY + Transmit FIFO Empty flag + 22 + 1 + read-only + + + TXNUM_5_0 + Number of valid entries in the Transmit FIFO + 16 + 6 + read-only + + + RXFULL + Receive FIFO Full flag + 15 + 1 + read-only + + + RXEMPTY + Receive FIFO Empty flag + 14 + 1 + read-only + + + RXNUM_5_0 + Number of valid entries in the Receive FIFO + 8 + 6 + read-only + + + SPIACTIVE + SPI register programming is in progress. +In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. +In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. +Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. +Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. + 0 + 1 + read-only + + + + + INTREN + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000003F + + + SLVCMDEN + Enable the Slave Command Interrupt. +Control whether interrupts are triggered whenever slave commands are received. +(Slave mode only) + 5 + 1 + read-write + + + ENDINTEN + Enable the End of SPI Transfer interrupt. +Control whether interrupts are triggered when SPI transfers end. +(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) + 4 + 1 + read-write + + + TXFIFOINTEN + Enable the SPI Transmit FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. + 3 + 1 + read-write + + + RXFIFOINTEN + Enable the SPI Receive FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. + 2 + 1 + read-write + + + TXFIFOURINTEN + Enable the SPI Transmit FIFO Underrun interrupt. +Control whether interrupts are triggered when the Transmit FIFO run out of data. +(Slave mode only) + 1 + 1 + read-write + + + RXFIFOORINTEN + Enable the SPI Receive FIFO Overrun interrupt. +Control whether interrupts are triggered when the Receive FIFO overflows. +(Slave mode only) + 0 + 1 + read-write + + + + + INTRST + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000003F + + + SLVCMDINT + Slave Command Interrupt. +This bit is set when Slave Command interrupts occur. +(Slave mode only) + 5 + 1 + write-only + + + ENDINT + End of SPI Transfer interrupt. +This bit is set when End of SPI Transfer interrupts occur. + 4 + 1 + write-only + + + TXFIFOINT + TX FIFO Threshold interrupt. +This bit is set when TX FIFO Threshold interrupts occur. + 3 + 1 + write-only + + + RXFIFOINT + RX FIFO Threshold interrupt. +This bit is set when RX FIFO Threshold interrupts occur. + 2 + 1 + write-only + + + TXFIFOURINT + TX FIFO Underrun interrupt. +This bit is set when TX FIFO Underrun interrupts occur. +(Slave mode only) + 1 + 1 + write-only + + + RXFIFOORINT + RX FIFO Overrun interrupt. +This bit is set when RX FIFO Overrun interrupts occur. +(Slave mode only) + 0 + 1 + write-only + + + + + TIMING + Interface Timing Register + 0x40 + 32 + 0x00000000 + 0x00003FFF + + + CS2SCLK + The minimum time between the edges of SPI CS and the edges of SCLK. +SCLK_period * (CS2SCLK + 1) / 2 + 12 + 2 + read-write + + + CSHT + The minimum time that SPI CS should stay HIGH. +SCLK_period * (CSHT + 1) / 2 + 8 + 4 + read-write + + + SCLK_DIV + The clock frequency ratio between the clock source and SPI interface SCLK. +SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) +The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. + 0 + 8 + read-write + + + + + SLVST + Slave Status Register + 0x60 + 32 + 0x00000000 + 0x0007FFFF + + + UNDERRUN + Data underrun occurs in the last transaction + 18 + 1 + write-only + + + OVERRUN + Data overrun occurs in the last transaction + 17 + 1 + read-write + + + READY + Set this bit to indicate that the ATCSPI200 is ready for data transaction. +When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. + 16 + 1 + read-write + + + USR_STATUS + User defined status flags + 0 + 16 + read-write + + + + + SLVDATACNT + Slave Data Count Register + 0x64 + 32 + 0x00000000 + 0x03FF03FF + + + WCNT + Slave transmitted data count + 16 + 10 + read-only + + + RCNT + Slave received data count + 0 + 10 + read-only + + + + + CONFIG + Configuration Register + 0x7c + 32 + 0x00004311 + 0x00004BFF + + + SLAVE + Support for SPI Slave mode + 14 + 1 + read-only + + + DIRECTIO + Support for Direct SPI IO + 11 + 1 + read-only + + + QUADSPI + Support for Quad I/O SPI + 9 + 1 + read-only + + + DUALSPI + Support for Dual I/O SPI + 8 + 1 + read-only + + + TXFIFOSIZE + Depth of TX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 4 + 4 + read-only + + + RXFIFOSIZE + Depth of RX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 0 + 4 + read-only + + + + + + + SPI1 + SPI1 + SPI + 0xf0034000 + + + SPI2 + SPI2 + SPI + 0xf0038000 + + + SPI3 + SPI3 + SPI + 0xf003c000 + + + UART0 + UART0 + UART + 0xf0040000 + + 0x0 + 0x40 + registers + + + + RXIDLE_CFG + Receive Idle Configuration Register + 0x4 + 32 + 0x00000000 + 0x000003FF + + + DETECT_COND + IDLE Detection Condition +0 - Treat as idle if RX pin is logic one +1 - Treat as idle if UART state machine state is idle + 9 + 1 + read-write + + + DETECT_EN + UART Idle Detect Enable +0 - Disable +1 - Enable + 8 + 1 + read-write + + + THR + Threshold for UART Receive Idle detection (in terms of bits) + 0 + 8 + read-write + + + + + CFG + Configuration Register + 0x10 + 32 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 2 + 30 + read-write + + + FIFOSIZE + The depth of RXFIFO and TXFIFO +0: 16-byte FIFO +1: 32-byte FIFO +2: 64-byte FIFO +3: 128-byte FIFO + 0 + 2 + read-only + + + + + OSCR + Over Sample Control Register + 0x14 + 32 + 0x00000010 + 0x0000001F + + + OSC + Over-sample control +The value must be an even number; any odd value +writes to this field will be converted to an even value. +OSC=0: The over-sample ratio is 32 +OSC<=8: The over-sample ratio is 8 +8 < OSC< 32: The over sample ratio is OSC + 0 + 5 + read-write + + + + + RBR + Receiver Buffer Register (when DLAB = 0) + 0x20 + 32 + 0x00000000 + 0x000000FF + + + RBR + Receive data read port + 0 + 8 + read-only + + + + + THR + Transmitter Holding Register (when DLAB = 0) + 0x20 + 32 + 0x00000000 + 0x000000FF + + + THR + Transmit data write port + 0 + 8 + write-only + + + + + DLL + Divisor Latch LSB (when DLAB = 1) + 0x20 + 32 + 0x00000001 + 0x000000FF + + + DLL + Least significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IER + Interrupt Enable Register (when DLAB = 0) + 0x24 + 32 + 0x00000000 + 0x8000000F + + + ERXIDLE + Enable Receive Idle interrupt +0 - Disable Idle interrupt +1 - Enable Idle interrupt + 31 + 1 + read-write + + + EMSI + Enable modem status interrupt +The interrupt asserts when the status of one of the +following occurs: +The status of modem_rin, modem_dcdn, +modem_dsrn or modem_ctsn (If the auto-cts mode is +disabled) has been changed. +If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), +modem_ctsn would be used to control the transmitter. + 3 + 1 + read-write + + + ELSI + Enable receiver line status interrupt + 2 + 1 + read-write + + + ETHEI + Enable transmitter holding register interrupt + 1 + 1 + read-write + + + ERBI + Enable received data available interrupt and the +character timeout interrupt +0: Disable +1: Enable + 0 + 1 + read-write + + + + + DLM + Divisor Latch MSB (when DLAB = 1) + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DLM + Most significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IIR + Interrupt Identification Register + 0x28 + 32 + 0x00000001 + 0x800000CF + + + RXIDLE_FLAG + UART IDLE Flag +0 - UART is busy +1 - UART is idle + 31 + 1 + read-write + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID + 0 + 4 + read-only + + + + + FCR + FIFO Control Register + 0x28 + 32 + 0x00000000 + 0x000000FF + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + write-only + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + write-only + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + write-only + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + write-only + + + + + LCR + Line Control Register + 0x2c + 32 + 0x00000000 + 0x000000FF + + + DLAB + Divisor latch access bit + 7 + 1 + read-write + + + BC + Break control + 6 + 1 + read-write + + + SPS + Stick parity +1: Parity bit is constant 0 or 1, depending on bit4 (EPS). +0: Disable the sticky bit parity. + 5 + 1 + read-write + + + EPS + Even parity select +1: Even parity (an even number of logic-1 is in the data +and parity bits) +0: Old parity. + 4 + 1 + read-write + + + PEN + Parity enable +When this bit is set, a parity bit is generated in +transmitted data before the first STOP bit and the parity +bit would be checked for the received data. + 3 + 1 + read-write + + + STB + Number of STOP bits +0: 1 bits +1: The number of STOP bit is based on the WLS setting +When WLS = 0, STOP bit is 1.5 bits +When WLS = 1, 2, 3, STOP bit is 2 bits + 2 + 1 + read-write + + + WLS + Word length setting +0: 5 bits +1: 6 bits +2: 7 bits +3: 8 bits + 0 + 2 + read-write + + + + + MCR + Modem Control Register ( + 0x30 + 32 + 0x00000000 + 0x00000032 + + + AFE + Auto flow control enable +0: Disable +1: The auto-CTS and auto-RTS setting is based on the +RTS bit setting: +When RTS = 0, auto-CTS only +When RTS = 1, auto-CTS and auto-RTS + 5 + 1 + read-write + + + LOOP + Enable loopback mode +0: Disable +1: Enable + 4 + 1 + read-write + + + RTS + Request to send +This bit controls the modem_rtsn output. +0: The modem_rtsn output signal will be driven HIGH +1: The modem_rtsn output signal will be driven LOW + 1 + 1 + read-write + + + + + LSR + Line Status Register + 0x34 + 32 + 0x00000000 + 0x000000FF + + + ERRF + Error in RXFIFO +In the FIFO mode, this bit is set when there is at least +one parity error, framing error, or line break +associated with data in the RXFIFO. It is cleared when +this register is read and there is no more error for the +rest of data in the RXFIFO. + 7 + 1 + read-only + + + TEMT + Transmitter empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) and the Transmitter Shift Register (TSR) are +both empty. Otherwise, it is zero. + 6 + 1 + read-only + + + THRE + Transmitter Holding Register empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) is empty. Otherwise, it is zero. +If the THRE interrupt is enabled, an interrupt is +triggered when THRE becomes 1. + 5 + 1 + read-only + + + LBREAK + Line break +This bit is set when the uart_sin input signal was held +LOWfor longer than the time for a full-word +transmission. A full-word transmission is the +transmission of the START, data, parity, and STOP +bits. It is cleared when this register is read. +In the FIFO mode, this bit indicates the line break for +the received data at the top of the RXFIFO. + 4 + 1 + read-only + + + FE + Framing error +This bit is set when the received STOP bit is not +HIGH. It is cleared when this register is read. +In the FIFO mode, this bit indicates the framing error +for the received data at the top of the RXFIFO. + 3 + 1 + read-only + + + PE + Parity error +This bit is set when the received parity does not match +with the parity selected in the LCR[5:4]. It is cleared +when this register is read. +In the FIFO mode, this bit indicates the parity error +for the received data at the top of the RXFIFO. + 2 + 1 + read-only + + + OE + Overrun error +This bit indicates that data in the Receiver Buffer +Register (RBR) is overrun. + 1 + 1 + read-only + + + DR + Data ready. +This bit is set when there are incoming received data +in the Receiver Buffer Register (RBR). It is cleared +when all of the received data are read. + 0 + 1 + read-only + + + + + MSR + Modem Status Register + 0x38 + 32 + 0x00000000 + 0x00000011 + + + CTS + Clear to send +0: The modem_ctsn input signal is HIGH. +1: The modem_ctsn input signal is LOW. + 4 + 1 + read-only + + + DCTS + Delta clear to send +This bit is set when the state of the modem_ctsn input +signal has been changed since the last time this +register is read. + 0 + 1 + read-only + + + + + + + UART1 + UART1 + UART + 0xf0044000 + + + UART2 + UART2 + UART + 0xf0048000 + + + UART3 + UART3 + UART + 0xf004c000 + + + UART4 + UART4 + UART + 0xf0050000 + + + UART5 + UART5 + UART + 0xf0054000 + + + UART6 + UART6 + UART + 0xf0058000 + + + UART7 + UART7 + UART + 0xf005c000 + + + PUART + PUART + UART + 0xf40e4000 + + + MCAN0 + MCAN0 + MCAN + 0xf0080000 + + 0x0 + 0x2a00 + registers + + + + ENDN + endian register + 0x4 + 32 + 0x87654321 + 0xFFFFFFFF + + + EVT + Endianness Test Value +The endianness test value is 0x87654321. + 0 + 32 + read-only + + + + + DBTP + data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set + 0xc + 32 + 0x00000A33 + 0x009F1FFF + + + TDC + transmitter delay compensation enable +0= Transmitter Delay Compensation disabled +1= Transmitter Delay Compensation enabled + 23 + 1 + read-write + + + DBRP + Data Bit Rate Prescaler +The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 16 + 5 + read-write + + + DTSEG1 + Data time segment before sample point +Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 8 + 5 + read-write + + + DTSEG2 + Data time segment after sample point +Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 4 + 4 + read-write + + + DSJW + Data (Re)Synchronization Jump Width +Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 0 + 4 + read-write + + + + + TEST + test register + 0x10 + 32 + 0x00000000 + 0x003F3FF0 + + + SVAL + Started Valid +0= Value of TXBNS not valid +1= Value of TXBNS valid + 21 + 1 + read-only + + + TXBNS + Tx Buffer Number Started +Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. + 16 + 5 + read-only + + + PVAL + Prepared Valid +0= Value of TXBNP not valid +1= Value of TXBNP valid + 13 + 1 + read-only + + + TXBNP + Tx Buffer Number Prepared +Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. + 8 + 5 + read-only + + + RX + Receive Pin +Monitors the actual value of pin m_can_rx +0= The CAN bus is dominant (m_can_rx = ‘0’) +1= The CAN bus is recessive (m_can_rx = ‘1’) + 7 + 1 + read-only + + + TX + Control of Transmit Pin +00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time +01 Sample Point can be monitored at pin m_can_tx +10 Dominant (‘0’) level at pin m_can_tx +11 Recessive (‘1’) at pin m_can_tx + 5 + 2 + read-write + + + LBCK + Loop Back Mode +0= Reset value, Loop Back Mode is disabled +1= Loop Back Mode is enabled + 4 + 1 + read-write + + + + + RWD + ram watchdog + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + WDV + Watchdog Value +Actual Message RAM Watchdog Counter Value. + 8 + 8 + read-only + + + WDC + Watchdog Configuration +Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. + 0 + 8 + read-write + + + + + CCCR + CC control register + 0x18 + 32 + 0x00000001 + 0x0000FFFF + + + NISO + Non ISO Operation +If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD +Specification V1.0. +0= CAN FD frame format according to ISO 11898-1:2015 +1= CAN FD frame format according to Bosch CAN FD Specification V1.0 +Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. + 15 + 1 + read-write + + + TXP + Transmit Pause +If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after +itself has successfully transmitted a frame (see Section 3.5). +0= Transmit pause disabled +1= Transmit pause enabled + 14 + 1 + read-write + + + EFBI + Edge Filtering during Bus Integration +0= Edge filtering disabled +1= Two consecutive dominant tq required to detect an edge for hard synchronization + 13 + 1 + read-write + + + PXHD + Protocol Exception Handling Disable +0= Protocol exception handling enabled +1= Protocol exception handling disabled +Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. + 12 + 1 + read-write + + + WMM + Wide Message Marker +Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. +0= 8-bit Message Marker used +1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO + 11 + 1 + read-write + + + UTSU + Use Timestamping Unit +When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. +0= Internal time stamping +1= External time stamping by TSU +Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. +In this case bit UTSU is fixed to zero by synthesis. + 10 + 1 + read-write + + + BRSE + Bit Rate Switch Enable +0= Bit rate switching for transmissions disabled +1= Bit rate switching for transmissions enabled +Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. + 9 + 1 + read-write + + + FDOE + FD Operation Enable +0= FD operation disabled +1= FD operation enabled + 8 + 1 + read-write + + + TEST + Test Mode Enable +0= Normal operation, register TEST holds reset values +1= Test Mode, write access to register TEST enabled + 7 + 1 + read-write + + + DAR + Disable Automatic Retransmission +0= Automatic retransmission of messages not transmitted successfully enabled +1= Automatic retransmission disabled + 6 + 1 + read-write + + + MON + Bus Monitoring Mode +Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. +0= Bus Monitoring Mode is disabled +1= Bus Monitoring Mode is enabled + 5 + 1 + read-write + + + CSR + Clock Stop Request +0= No clock stop is requested +1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. + 4 + 1 + read-write + + + CSA + Clock Stop Acknowledge +0= No clock stop acknowledged +1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk + 3 + 1 + read-only + + + ASM + Restricted Operation Mode +Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. +0= Normal CAN operation +1= Restricted Operation Mode active + 2 + 1 + read-write + + + CCE + Configuration Change Enable +0= The CPU has no write access to the protected configuration registers +1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) + 1 + 1 + read-write + + + INIT + Initialization +0= Normal Operation +1= Initialization is started + 0 + 1 + read-write + + + + + NBTP + nominal bit timing and prescaler register + 0x1c + 32 + 0x06000A03 + 0xFFFFFF7F + + + NSJW + Nominal (Re)Synchronization Jump Width +Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 25 + 7 + read-write + + + NBRP + Nominal Bit Rate Prescaler +The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + 16 + 9 + read-write + + + NTSEG1 + Nominal Time segment before sample point +Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 8 + 8 + read-write + + + NTSEG2 + Nominal Time segment after sample point +Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 0 + 7 + read-write + + + + + TSCC + timestamp counter configuration + 0x20 + 32 + 0x00000000 + 0x000F0003 + + + TCP + Timestamp Counter Prescaler +Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 16 + 4 + read-write + + + TSS + timestamp Select +00= Timestamp counter value always 0x0000 +01= Timestamp counter value incremented according to TCP +10= External timestamp counter value used +11= Same as “00” + 0 + 2 + read-write + + + + + TSCV + timestamp counter value + 0x24 + 32 + 0x00000000 + 0x0000FFFF + + + TSC + Timestamp Counter +The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. + 0 + 16 + read-only + + + + + TOCC + timeout counter configuration + 0x28 + 32 + 0xFFFF0000 + 0xFFFF0007 + + + TOP + Timeout Period +Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + 16 + 16 + read-write + + + TOS + Timeout Select +When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. +00= Continuous operation +01= Timeout controlled by Tx Event FIFO +10= Timeout controlled by Rx FIFO 0 +11= Timeout controlled by Rx FIFO 1 + 1 + 2 + read-write + + + RP + Enable Timeout Counter +0= Timeout Counter disabled +1= Timeout Counter enabled + 0 + 1 + read-write + + + + + TOCV + timeout counter value + 0x2c + 32 + 0x0000FFFF + 0x0000FFFF + + + TOC + Timeout Counter +The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. +Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. + 0 + 16 + read-only + + + + + ECR + error counter register + 0x40 + 32 + 0x00000000 + 0x00FFFFFF + + + CEL + CAN Error Logging +The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. +The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. +Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. + 16 + 8 + read-only + + + RP + Receive Error Passive +0= The Receive Error Counter is below the error passive level of 128 +1= The Receive Error Counter has reached the error passive level of 128 + 15 + 1 + read-only + + + REC + Receive Error Counter +Actual state of the Receive Error Counter, values between 0 and 127 + 8 + 7 + read-only + + + TEC + Transmit Error Counter +Actual state of the Transmit Error Counter, values between 0 and 255 +Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. + 0 + 8 + read-only + + + + + PSR + protocol status register + 0x44 + 32 + 0x00000707 + 0x007F7FFF + + + TDCV + Transmitter Delay Compensation Value +Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + 16 + 7 + read-only + + + PXE + Protocol Exception Event +0= No protocol exception event occurred since last read access +1= Protocol exception event occurred +Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. + 14 + 1 + read-only + + + RFDF + Received a CAN FD Message +This bit is set independent of acceptance filtering. +0= Since this bit was reset by the CPU, no CAN FD message has been received +1= Message in CAN FD format with FDF flag set has been received +Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. + 13 + 1 + read-only + + + RBRS + BRS flag of last received CAN FD Message +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its BRS flag set +1= Last received CAN FD message had its BRS flag set +Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. + 12 + 1 + read-only + + + RESI + ESI flag of last received CAN FD Message +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its ESI flag set +1= Last received CAN FD message had its ESI flag set +Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. + 11 + 1 + read-only + + + DLEC + Data Phase Last Error Code +Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with +its BRS flag set has been transferred (reception or transmission) without error. +Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. + 8 + 3 + read-only + + + BO + Bus_Off Status +0= The M_CAN is not Bus_Off +1= The M_CAN is in Bus_Off state + 7 + 1 + read-only + + + EW + Warning Status +0= Both error counters are below the Error_Warning limit of 96 +1= At least one of error counter has reached the Error_Warning limit of 96 + 6 + 1 + read-only + + + EP + Error Passive +0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected +1= The M_CAN is in the Error_Passive state + 5 + 1 + read-only + + + ACT + Activity +Monitors the module’s CAN communication state. +00= Synchronizing - node is synchronizing on CAN communication +01= Idle - node is neither receiver nor transmitter +10= Receiver - node is operating as receiver +11= Transmitter - node is operating as transmitter +Note: ACT is set to “00” by a Protocol Exception Event. + 3 + 2 + read-only + + + LEC + Last Error Code +The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. +0= No Error: No error occurred since LEC has been reset by successful reception or transmission. +1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. +2= Form Error: A fixed format part of a received frame has the wrong format. +3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. +4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), +the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus +value was dominant. +5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at +dominant or continuously disturbed). +6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. +7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. +Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. +Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. +Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. + 0 + 3 + read-only + + + + + TDCR + transmitter delay compensation + 0x48 + 32 + 0x00000000 + 0x00007F7F + + + TDCO + Transmitter Delay Compensation SSP Offset +Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. + 8 + 7 + read-write + + + TDCF + Transmitter Delay Compensation Filter Window Length +Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. + 0 + 7 + read-write + + + + + IR + interrupt register + 0x50 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARA + Access to Reserved Address +0= No access to reserved address occurred +1= Access to reserved address occurred + 29 + 1 + read-write + + + PED + Protocol Error in Data Phase (Data Bit Time is used) +0= No protocol error in data phase +1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) + 28 + 1 + read-write + + + PEA + Protocol Error in Arbitration Phase (Nominal Bit Time is used) +0= No protocol error in arbitration phase +1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) + 27 + 1 + read-write + + + WDI + Watchdog Interrupt +0= No Message RAM Watchdog event occurred +1= Message RAM Watchdog event due to missing READY + 26 + 1 + read-write + + + BO + Bus_Off Status +0= Bus_Off status unchanged +1= Bus_Off status changed + 25 + 1 + read-write + + + EW + Warning Status +0= Error_Warning status unchanged +1= Error_Warning status changed + 24 + 1 + read-write + + + EP + Error Passive +0= Error_Passive status unchanged +1= Error_Passive status changed + 23 + 1 + read-write + + + ELO + Error Logging Overflow +0= CAN Error Logging Counter did not overflow +1= Overflow of CAN Error Logging Counter occurred + 22 + 1 + read-write + + + BEU + Bit Error Uncorrected +Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. +0= No bit error detected when reading from Message RAM +1= Bit error detected, uncorrected (e.g. parity logic) + 21 + 1 + read-write + + + BEC + Bit Error Corrected +Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. +0= No bit error detected when reading from Message RAM +1= Bit error detected and corrected (e.g. ECC) + 20 + 1 + read-write + + + DRX + Message stored to Dedicated Rx Buffer +The flag is set whenever a received message has been stored into a dedicated Rx Buffer. +0= No Rx Buffer updated +1= At least one received message stored into an Rx Buffer + 19 + 1 + read-write + + + TOO + Timeout Occurred +0= No timeout +1= Timeout reached + 18 + 1 + read-write + + + MRAF + Message RAM Access Failure +The flag is set, when the Rx Handler +.has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message +storage is aborted and the Rx Handler starts processing of the following message. +.was not able to write a message to the Message RAM. In this case message storage is aborted. +In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. +The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the +M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. +0= No Message RAM access failure occurred +1= Message RAM access failure occurred + 17 + 1 + read-write + + + TSW + Timestamp Wraparound +0= No timestamp counter wrap-around +1= Timestamp counter wrapped around + 16 + 1 + read-write + + + TEFL + Tx Event FIFO Element Lost +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero + 15 + 1 + read-write + + + TEFF + Tx Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + 14 + 1 + read-write + + + TEFW + Tx Event FIFO Watermark Reached +0= Tx Event FIFO fill level below watermark +1= Tx Event FIFO fill level reached watermark + 13 + 1 + read-write + + + TEFN + Tx Event FIFO New Entry +0= Tx Event FIFO unchanged +1= Tx Handler wrote Tx Event FIFO element + 12 + 1 + read-write + + + TFE + Tx FIFO Empty +0= Tx FIFO non-empty +1= Tx FIFO empty + 11 + 1 + read-write + + + TCF + Transmission Cancellation Finished +0= No transmission cancellation finished +1= Transmission cancellation finished + 10 + 1 + read-write + + + TC + Transmission Completed +0= No transmission completed +1= Transmission completed + 9 + 1 + read-write + + + HPM + High Priority Message +0= No high priority message received +1= High priority message received + 8 + 1 + read-write + + + RF1L + Rx FIFO 1 Message Lost +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 7 + 1 + read-write + + + RF1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + 6 + 1 + read-write + + + RF1W + Rx FIFO 1 Watermark Reached +0= Rx FIFO 1 fill level below watermark +1= Rx FIFO 1 fill level reached watermark + 5 + 1 + read-write + + + RF1N + Rx FIFO 1 New Message +0= No new message written to Rx FIFO 1 +1= New message written to Rx FIFO 1 + 4 + 1 + read-write + + + RF0L + Rx FIFO 0 Message Lost +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + 3 + 1 + read-write + + + RF0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + 2 + 1 + read-write + + + RF0W + Rx FIFO 0 Watermark Reached +0= Rx FIFO 0 fill level below watermark +1= Rx FIFO 0 fill level reached watermark + 1 + 1 + read-write + + + RF0N + Rx FIFO 0 New Message +0= No new message written to Rx FIFO 0 +1= New message written to Rx FIFO 0 + 0 + 1 + read-write + + + + + IE + interrupt enable + 0x54 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARAE + Access to Reserved Address Enable + 29 + 1 + read-write + + + PEDE + Protocol Error in Data Phase Enable + 28 + 1 + read-write + + + PEAE + Protocol Error in Arbitration Phase Enable + 27 + 1 + read-write + + + WDIE + Watchdog Interrupt Enable + 26 + 1 + read-write + + + BOE + Bus_Off Status Interrupt Enable + 25 + 1 + read-write + + + EWE + Warning Status Interrupt Enable + 24 + 1 + read-write + + + EPE + Error Passive Interrupt Enable + 23 + 1 + read-write + + + ELOE + Error Logging Overflow Interrupt Enable + 22 + 1 + read-write + + + BEUE + Bit Error Uncorrected Interrupt Enable + 21 + 1 + read-write + + + BECE + Bit Error Corrected Interrupt Enable + 20 + 1 + read-write + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + 19 + 1 + read-write + + + TOOE + Timeout Occurred Interrupt Enable + 18 + 1 + read-write + + + MRAFE + Message RAM Access Failure Interrupt Enable + 17 + 1 + read-write + + + TSWE + Timestamp Wraparound Interrupt Enable + 16 + 1 + read-write + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable + 15 + 1 + read-write + + + TEFFE + Tx Event FIFO Full Interrupt Enable + 14 + 1 + read-write + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + 13 + 1 + read-write + + + TEFNE + Tx Event FIFO New Entry Interrupt Enable + 12 + 1 + read-write + + + TFEE + Tx FIFO Empty Interrupt Enable + 11 + 1 + read-write + + + TCFE + Transmission Cancellation Finished Interrupt Enable + 10 + 1 + read-write + + + TCE + Transmission Completed Interrupt Enable + 9 + 1 + read-write + + + HPME + High Priority Message Interrupt Enable + 8 + 1 + read-write + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + 7 + 1 + read-write + + + RF1FE + Rx FIFO 1 Full Interrupt Enable + 6 + 1 + read-write + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + 5 + 1 + read-write + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + 4 + 1 + read-write + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + 3 + 1 + read-write + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + 2 + 1 + read-write + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + 1 + 1 + read-write + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + 0 + 1 + read-write + + + + + ILS + interrupt line select + 0x58 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARAL + Access to Reserved Address Line + 29 + 1 + read-write + + + PEDL + Protocol Error in Data Phase Line + 28 + 1 + read-write + + + PEAL + Protocol Error in Arbitration Phase Line + 27 + 1 + read-write + + + WDIL + Watchdog Interrupt Line + 26 + 1 + read-write + + + BOL + Bus_Off Status Interrupt Line + 25 + 1 + read-write + + + EWL + Warning Status Interrupt Line + 24 + 1 + read-write + + + EPL + Error Passive Interrupt Line + 23 + 1 + read-write + + + ELOL + Error Logging Overflow Interrupt Line + 22 + 1 + read-write + + + BEUL + Bit Error Uncorrected Interrupt Line + 21 + 1 + read-write + + + BECL + Bit Error Corrected Interrupt Line + 20 + 1 + read-write + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Line + 19 + 1 + read-write + + + TOOL + Timeout Occurred Interrupt Line + 18 + 1 + read-write + + + MRAFL + Message RAM Access Failure Interrupt Line + 17 + 1 + read-write + + + TSWL + Timestamp Wraparound Interrupt Line + 16 + 1 + read-write + + + TEFLL + Tx Event FIFO Event Lost Interrupt Line + 15 + 1 + read-write + + + TEFFL + Tx Event FIFO Full Interrupt Line + 14 + 1 + read-write + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Line + 13 + 1 + read-write + + + TEFNL + Tx Event FIFO New Entry Interrupt Line + 12 + 1 + read-write + + + TFEL + Tx FIFO Empty Interrupt Line + 11 + 1 + read-write + + + TCFL + Transmission Cancellation Finished Interrupt Line + 10 + 1 + read-write + + + TCL + Transmission Completed Interrupt Line + 9 + 1 + read-write + + + HPML + High Priority Message Interrupt Line + 8 + 1 + read-write + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Line + 7 + 1 + read-write + + + RF1FL + Rx FIFO 1 Full Interrupt Line + 6 + 1 + read-write + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Line + 5 + 1 + read-write + + + RF1NL + Rx FIFO 1 New Message Interrupt Line + 4 + 1 + read-write + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Line + 3 + 1 + read-write + + + RF0FL + Rx FIFO 0 Full Interrupt Line + 2 + 1 + read-write + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Line + 1 + 1 + read-write + + + RF0NL + Rx FIFO 0 New Message Interrupt Line + 0 + 1 + read-write + + + + + ILE + interrupt line enable + 0x5c + 32 + 0x00000000 + 0x00000003 + + + EINT1 + Enable Interrupt Line 1 +0= Interrupt line m_can_int1 disabled +1= Interrupt line m_can_int1 enabled + 1 + 1 + read-write + + + EINT0 + Enable Interrupt Line 0 +0= Interrupt line m_can_int0 disabled +1= Interrupt line m_can_int0 enabled + 0 + 1 + read-write + + + + + GFC + global filter configuration + 0x80 + 32 + 0x00000000 + 0x0000003F + + + ANFS + Accept Non-matching Frames Standard +Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + 4 + 2 + read-write + + + ANFE + Accept Non-matching Frames Extended +Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + 2 + 2 + read-write + + + RRFS + Reject Remote Frames Standard +0= Filter remote frames with 11-bit standard IDs +1= Reject all remote frames with 11-bit standard IDs + 1 + 1 + read-write + + + RRFE + Reject Remote Frames Extended +0= Filter remote frames with 29-bit extended IDs +1= Reject all remote frames with 29-bit extended IDs + 0 + 1 + read-write + + + + + SIDFC + standard ID filter configuration + 0x84 + 32 + 0x00000000 + 0x00FFFFFC + + + LSS + List Size Standard +0= No standard Message ID filter +1-128= Number of standard Message ID filter elements +>128= Values greater than 128 are interpreted as 128 + 16 + 8 + read-write + + + FLSSA + Filter List Standard Start Address +Start address of standard Message ID filter list (32-bit word address) + 2 + 14 + read-write + + + + + XIDFC + extended ID filter configuration + 0x88 + 32 + 0x00000000 + 0x007FFFFC + + + LSE + List Size Extended +0= No extended Message ID filter +1-64= Number of extended Message ID filter elements +>64= Values greater than 64 are interpreted as 64 + 16 + 7 + read-write + + + FLESA + Filter List Extended Start Address +Start address of extended Message ID filter list (32-bit word address). + 2 + 14 + read-write + + + + + XIDAM + extended id and mask + 0x90 + 32 + 0x1FFFFFFF + 0x1FFFFFFF + + + EIDM + Extended ID Mask +For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. + 0 + 29 + read-write + + + + + HPMS + high priority message status + 0x94 + 32 + 0x00000000 + 0x0000FFFF + + + FLST + Filter List +Indicates the filter list of the matching filter element. +0= Standard Filter List +1= Extended Filter List + 15 + 1 + read-only + + + FIDX + Filter Index +Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. + 8 + 7 + read-only + + + MSI + Message Storage Indicator +00= No FIFO selected +01= FIFO message lost +10= Message stored in FIFO 0 +11= Message stored in FIFO 1 + 6 + 2 + read-only + + + BIDX + Buffer Index +Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. + 0 + 6 + read-only + + + + + NDAT1 + new data1 + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + ND1 + New Data[31:0] +The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + 0 + 32 + read-write + + + + + NDAT2 + new data2 + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + ND2 + New Data[63:32] +The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + 0 + 32 + read-write + + + + + RXF0C + rx fifo 0 configuration + 0xa0 + 32 + 0x00000000 + 0xFF7FFFFC + + + F0OM + FIFO 0 Operation Mode +FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 0 blocking mode +1= FIFO 0 overwrite mode + 31 + 1 + read-write + + + F0WM + Rx FIFO 0 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) +>64= Watermark interrupt disabled + 24 + 7 + read-write + + + F0S + Rx FIFO 0 Size +0= No Rx FIFO 0 +1-64= Number of Rx FIFO 0 elements +>64= Values greater than 64 are interpreted as 64 +The Rx FIFO 0 elements are indexed from 0 to F0S-1 + 16 + 7 + read-write + + + F0SA + Rx FIFO 0 Start Address +Start address of Rx FIFO 0 in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + RXF0S + rx fifo 0 status + 0xa4 + 32 + 0x00000000 + 0x033F3F7F + + + RF0L + Rx FIFO 0 Message Lost +This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero +Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. + 25 + 1 + read-only + + + F0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + 24 + 1 + read-only + + + F0PI + Rx FIFO 0 Put Index +Rx FIFO 0 write index pointer, range 0 to 63. + 16 + 6 + read-only + + + F0GI + Rx FIFO 0 Get Index +Rx FIFO 0 read index pointer, range 0 to 63. + 8 + 6 + read-only + + + F0FL + Rx FIFO 0 Fill Level +Number of elements stored in Rx FIFO 0, range 0 to 64. + 0 + 7 + read-only + + + + + RXF0A + rx fifo0 acknowledge + 0xa8 + 32 + 0x00000000 + 0x0000003F + + + F0AI + Rx FIFO 0 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + 0 + 6 + read-write + + + + + RXBC + rx buffer configuration + 0xac + 32 + 0x00000000 + 0x0000FFFC + + + RBSA + Rx Buffer Start Address +Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. + 2 + 14 + read-write + + + + + RXF1C + rx fifo1 configuration + 0xb0 + 32 + 0x00000000 + 0xFF7FFFFC + + + F1OM + FIFO 1 Operation Mode +FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 1 blocking mode +1= FIFO 1 overwrite mode + 31 + 1 + read-write + + + F1WM + Rx FIFO 1 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) +>64= Watermark interrupt disabled + 24 + 7 + read-write + + + F1S + Rx FIFO 1 Size +0= No Rx FIFO 1 +1-64= Number of Rx FIFO 1 elements +>64= Values greater than 64 are interpreted as 64 +The Rx FIFO 1 elements are indexed from 0 to F1S - 1 + 16 + 7 + read-write + + + F1SA + Rx FIFO 1 Start Address +Start address of Rx FIFO 1 in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + RXF1S + rx fifo1 status + 0xb4 + 32 + 0x00000000 + 0xC33F3F7F + + + DMS + Debug Message Status +00= Idle state, wait for reception of debug messages, DMA request is cleared +01= Debug message A received +10= Debug messages A, B received +11= Debug messages A, B, C received, DMA request is set + 30 + 2 + read-only + + + RF1L + Rx FIFO 1 Message Lost +This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero +Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. + 25 + 1 + read-only + + + F1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + 24 + 1 + read-only + + + F1PI + Rx FIFO 1 Put Index +Rx FIFO 1 write index pointer, range 0 to 63. + 16 + 6 + read-only + + + F1GI + Rx FIFO 1 Get Index +Rx FIFO 1 read index pointer, range 0 to 63. + 8 + 6 + read-only + + + F1FL + Rx FIFO 1 Fill Level +Number of elements stored in Rx FIFO 1, range 0 to 64. + 0 + 7 + read-only + + + + + RXF1A + rx fifo 1 acknowledge + 0xb8 + 32 + 0x00000000 + 0x0000003F + + + F1AI + Rx FIFO 1 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + 0 + 6 + read-write + + + + + RXESC + rx buffer/fifo element size configuration + 0xbc + 32 + 0x00000000 + 0x00000777 + + + RBDS + Rx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + 8 + 3 + read-write + + + F1DS + Rx FIFO 1 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + 4 + 3 + read-write + + + F0DS + Rx FIFO 0 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field +Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. + 0 + 3 + read-write + + + + + TXBC + tx buffer configuration + 0xc0 + 32 + 0x00000000 + 0x7F3FFFFC + + + TFQM + Tx FIFO/Queue Mode +0= Tx FIFO operation +1= Tx Queue operation + 30 + 1 + read-write + + + TFQS + Transmit FIFO/Queue Size +0= No Tx FIFO/Queue +1-32= Number of Tx Buffers used for Tx FIFO/Queue +>32= Values greater than 32 are interpreted as 32 + 24 + 6 + read-write + + + NDTB + Number of Dedicated Transmit Buffers +0= No Dedicated Tx Buffers +1-32= Number of Dedicated Tx Buffers +>32= Values greater than 32 are interpreted as 32 + 16 + 6 + read-write + + + TBSA + Tx Buffers Start Address +Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). +Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. + 2 + 14 + read-write + + + + + TXFQS + tx fifo/queue status + 0xc4 + 32 + 0x00000000 + 0x003F1F3F + + + TFQF + Tx FIFO/Queue Full +0= Tx FIFO/Queue not full +1= Tx FIFO/Queue full + 21 + 1 + read-only + + + TFQPI + Tx FIFO/Queue Put Index +Tx FIFO/Queue write index pointer, range 0 to 31. + 16 + 5 + read-only + + + TFGI + Tx FIFO Get Index +Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured +(TXBC.TFQM = ‘1’). + 8 + 5 + read-only + + + TFFL + Tx FIFO Free Level +Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) +Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with +the first dedicated Tx Buffers. +Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. + 0 + 6 + read-only + + + + + TXESC + tx buffer element size configuration + 0xc8 + 32 + 0x00000000 + 0x00000007 + + + TBDS + Tx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field +Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). + 0 + 3 + read-write + + + + + TXBRP + tx buffer request pending + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + TRP + Transmission Request Pending +Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register +TXBCR. +TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the +highest priority (Tx Buffer with lowest Message ID). +A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. +After a cancellation has been requested, a finished cancellation is signalled via TXBCF +? after successful transmission together with the corresponding TXBTO bit +? when the transmission has not yet been started at the point of cancellation +? when the transmission has been aborted due to lost arbitration +? when an error occurred during frame transmission +In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. +0= No transmission request pending +1= Transmission request pending +Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. + 0 + 32 + read-only + + + + + TXBAR + tx buffer add request + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AR + Add Request +Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx +Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. +When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. +0= No transmission request added +1= Transmission requested added +Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. + 0 + 32 + read-write + + + + + TXBCR + tx buffer cancellation request + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR + Cancellation Request +Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. +0= No cancellation pending +1= Cancellation pending + 0 + 32 + read-write + + + + + TXBTO + tx buffer transmission occurred + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TO + Transmission Occurred +Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. +0= No transmission occurred +1= Transmission occurred + 0 + 32 + read-only + + + + + TXBCF + tx buffer cancellation finished + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + CF + Cancellation Finished +Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. +0= No transmit buffer cancellation +1= Transmit buffer cancellation finished + 0 + 32 + read-only + + + + + TXBTIE + tx buffer transmission interrupt enable + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmission Interrupt Enable +Each Tx Buffer has its own Transmission Interrupt Enable bit. +0= Transmission interrupt disabled +1= Transmission interrupt enable + 0 + 32 + read-write + + + + + TXBCIE + tx buffer cancellation finished interrupt enable + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CFIE + Cancellation Finished Interrupt Enable +Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. +0= Cancellation finished interrupt disabled +1= Cancellation finished interrupt enabled + 0 + 32 + read-write + + + + + TXEFC + tx event fifo configuration + 0xf0 + 32 + 0x00000000 + 0x3F3FFFFC + + + EFWM + Event FIFO Watermark +0= Watermark interrupt disabled +1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) +>32= Watermark interrupt disabled + 24 + 6 + read-write + + + EFS + Event FIFO Size +0= Tx Event FIFO disabled +1-32= Number of Tx Event FIFO elements +>32= Values greater than 32 are interpreted as 32 +The Tx Event FIFO elements are indexed from 0 to EFS - 1 + 16 + 6 + read-write + + + EFSA + Event FIFO Start Address +Start address of Tx Event FIFO in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + TXEFS + tx event fifo status + 0xf4 + 32 + 0x00000000 + 0x031F1F3F + + + TEFL + Tx Event FIFO Element Lost +This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + 25 + 1 + read-only + + + EFF + Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + 24 + 1 + read-only + + + EFPI + Event FIFO Put Index +Tx Event FIFO write index pointer, range 0 to 31. + 16 + 5 + read-only + + + EFGI + Event FIFO Get Index +Tx Event FIFO read index pointer, range 0 to 31. + 8 + 5 + read-only + + + EFFL + Event FIFO Fill Level +Number of elements stored in Tx Event FIFO, range 0 to 32. + 0 + 6 + read-only + + + + + TXEFA + tx event fifo acknowledge + 0xf8 + 32 + 0x00000000 + 0x0000001F + + + EFAI + Event FIFO Acknowledge Index +After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get +Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. + 0 + 5 + read-write + + + + + TS_SEL_TS_SEL0 + timestamp 0-15 + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL1 + timestamp 1 + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL2 + timestamp 2 + 0x208 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL3 + timestamp 3 + 0x20c + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL4 + timestamp 4 + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL5 + timestamp 5 + 0x214 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL6 + timestamp 6 + 0x218 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL7 + timestamp 7 + 0x21c + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL8 + timestamp 8 + 0x220 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL9 + timestamp 9 + 0x224 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL10 + timestamp 10 + 0x228 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL11 + timestamp 11 + 0x22c + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL12 + timestamp 12 + 0x230 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL13 + timestamp 13 + 0x234 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL14 + timestamp 14 + 0x238 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + TS_SEL_TS_SEL15 + timestamp 15 + 0x23c + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + CREL + core release register + 0x240 + 32 + 0x00000000 + 0xFFFFFFFF + + + REL + Core Release +One digit, BCD-coded + 28 + 4 + read-only + + + STEP + Step of Core Release +One digit, BCD-coded. + 24 + 4 + read-only + + + SUBSTEP + Sub-step of Core Release +One digit, BCD-coded + 20 + 4 + read-only + + + YEAR + Timestamp Year +One digit, BCD-coded. This field is set by generic parameter on +synthesis. + 16 + 4 + read-only + + + MON + Timestamp Month +Two digits, BCD-coded. This field is set by generic parameter +on synthesis. + 8 + 8 + read-only + + + DAY + Timestamp Day +Two digits, BCD-coded. This field is set by generic parameter +on synthesis. + 0 + 8 + read-only + + + + + TSCFG + timestamp configuration + 0x244 + 32 + 0x00000000 + 0x0000FF0F + + + TBPRE + Timebase Prescaler +0x00 to 0xFF +The value by which the oscillator frequency is divided for +generating the timebase counter clock. Valid values for the +Timebase Prescaler are 0 to 255. The actual interpretation by +the hardware of this value is such that one more than the value +programmed here is used. Affects only the TSU internal +timebase. When the internal timebase is excluded by synthesis, +TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not +used. + 8 + 8 + read-write + + + EN64 + set to use 64bit timestamp. +when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. +TSP can be used to select different one + 3 + 1 + read-write + + + SCP + Select Capturing Position +0: Capture Timestamp at EOF +1: Capture Timestamp at SOF + 2 + 1 + read-write + + + TBCS + Timebase Counter Select +When the internal timebase is excluded by synthesis, TBCS is +fixed to ‘1’. +0: Timestamp value captured from internal timebase counter, + ATB.TB[31:0] is the internal timbase counter +1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] + 1 + 1 + read-write + + + TSUE + Timestamp Unit Enable +0: TSU disabled +1: TSU enabled + 0 + 1 + read-write + + + + + TSS1 + timestamp status1 + 0x248 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSL + Timestamp Lost +Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. +Reading a Timestamp register resets the related bit. + 16 + 16 + read-only + + + TSN + Timestamp New +Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related +Timestamp register. Reading a Timestamp register resets the related bit. + 0 + 16 + read-only + + + + + TSS2 + timestamp status2 + 0x24c + 32 + 0x00000000 + 0x0000000F + + + TSP + Timestamp Pointer +The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 +depending on number_ts_g), it is incremented to 0. +Value also signalled on output m_can_tsp[3:0]. + 0 + 4 + read-only + + + + + ATB + actual timebase + 0x250 + 32 + 0x00000000 + 0xFFFFFFFF + + + TB + timebase for timestamp generation 31-0 + 0 + 32 + read-only + + + + + ATBH + actual timebase high + 0x254 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBH + timebase for timestamp generation 63-32 + 0 + 32 + read-only + + + + + GLB_CTL + global control + 0x400 + 32 + 0x00000000 + 0xE0000007 + + + M_CAN_STBY + m_can standby control + 31 + 1 + read-write + + + STBY_CLR_EN + m_can standby clear control +0:controlled by software by standby bit[bit31] +1:auto clear standby by hardware when rx data is 0 + 30 + 1 + read-write + + + STBY_POL + standby polarity selection + 29 + 1 + read-write + + + TSU_TBIN_SEL + No description avaiable + 0 + 3 + read-write + + + + + GLB_STATUS + global status + 0x404 + 32 + 0x00000000 + 0x0000000C + + + M_CAN_INT1 + m_can interrupt status1 + 3 + 1 + read-only + + + M_CAN_INT0 + m_can interrupt status0 + 2 + 1 + read-only + + + + + MESSAGE_BUFF_0 + message buff + 0x2000 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_1 + message buff + 0x2004 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_2 + message buff + 0x2008 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_3 + message buff + 0x200c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_4 + message buff + 0x2010 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_5 + message buff + 0x2014 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_6 + message buff + 0x2018 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + 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MESSAGE_BUFF_65 + message buff + 0x2104 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_66 + message buff + 0x2108 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_67 + message buff + 0x210c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_68 + message buff + 0x2110 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_69 + message buff + 0x2114 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_70 + message buff + 0x2118 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_71 + message buff + 0x211c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_72 + message buff + 0x2120 + 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MESSAGE_BUFF_591 + message buff + 0x293c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_592 + message buff + 0x2940 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_593 + message buff + 0x2944 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_594 + message buff + 0x2948 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_595 + message buff + 0x294c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_596 + message buff + 0x2950 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_597 + message buff + 0x2954 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_598 + message buff + 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MESSAGE_BUFF_627 + message buff + 0x29cc + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_628 + message buff + 0x29d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_629 + message buff + 0x29d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_630 + message buff + 0x29d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_631 + message buff + 0x29dc + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_632 + message buff + 0x29e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_633 + message buff + 0x29e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_634 + message buff + 0x29e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_635 + message buff + 0x29ec + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_636 + message buff + 0x29f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_637 + message buff + 0x29f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_638 + message buff + 0x29f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + MESSAGE_BUFF_639 + message buff + 0x29fc + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + m_can message buffer + 0 + 32 + read-write + + + + + + + MCAN1 + MCAN1 + MCAN + 0xf0084000 + + + MCAN2 + MCAN2 + MCAN + 0xf0088000 + + + MCAN3 + MCAN3 + MCAN + 0xf008c000 + + + WDG0 + WDG0 + WDOG + 0xf0090000 + + 0x0 + 0x20 + registers + + + + CTRL + Control Register + 0x10 + 32 + 0x00000000 + 0x000007FF + + + RSTTIME + The time interval of the reset stage: +0: Clock period x 2^7 +1: Clock period x 2^8 +2: Clock period x 2^9 +3: Clock period x 2^10 +4: Clock period x 2^11 +5: Clock period x 2^12 +6: Clock period x 2^13 +7: Clock period x 2^14 + 8 + 3 + read-write + + + INTTIME + The timer interval of the interrupt stage: +0: Clock period x 2^6 +1: Clock period x 2^8 +2: Clock period x 2^10 +3: Clock period x 2^11 +4: Clock period x 2^12 +5: Clock period x 2^13 +6: Clock period x 2^14 +7: Clock period x 2^15 +8: Clock period x 2^17 +9: Clock period x 2^19 +10: Clock period x 2^21 +11: Clock period x 2^23 +12: Clock period x 2^25 +13: Clock period x 2^27 +14: Clock period x 2^29 +15: Clock period x 2^31 + 4 + 4 + read-write + + + RSTEN + Enable or disable the watchdog reset +0: Disable +1: Enable + 3 + 1 + read-write + + + INTEN + Enable or disable the watchdog interrupt +0: Disable +1: Enable + 2 + 1 + read-write + + + CLKSEL + Clock source of timer: +0: EXTCLK +1: PCLK + 1 + 1 + read-write + + + EN + Enable or disable the watchdog timer +0: Disable +1: Enable + 0 + 1 + read-write + + + + + RESTART + Restart Register + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + RESTART + Write the magic number +ATCWDT200_RESTART_NUM to restart the +watchdog timer. + 0 + 16 + write-only + + + + + WREN + Write Protection Register + 0x18 + 32 + 0x00000000 + 0x0000FFFF + + + WEN + Write the magic code to disable the write +protection of the Control Register and the +Restart Register. + 0 + 16 + write-only + + + + + ST + Status Register + 0x1c + 32 + 0x00000000 + 0x00000001 + + + INTEXPIRED + The status of the watchdog interrupt timer +0: timer is not expired yet +1: timer is expired + 0 + 1 + write-only + + + + + + + WDG1 + WDG1 + WDOG + 0xf0094000 + + + PWDG + PWDG + WDOG + 0xf40e8000 + + + MBX0A + MBX0A + MBX + 0xf00a0000 + + 0x0 + 0x30 + registers + + + + CR + Command Registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXRESET + Reset TX Fifo and word. + 31 + 1 + read-write + + + RESERVED + Reserved + 16 + 15 + read-only + + + BARCTL + Bus Acccess Response Control, when bit 15:14= +00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. + 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. +10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. +11: reserved. + 14 + 2 + read-write + + + RESERVED + Reserved + 9 + 5 + read-only + + + BEIE + Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. +1, enable the bus access error interrupt. +0, disable the bus access error interrupt. + 8 + 1 + read-write + + + TFMAIE + TX FIFO message available interrupt enable. +1, enable the TX FIFO massage available interrupt. +0, disable the TX FIFO message available interrupt. + 7 + 1 + read-write + + + TFMEIE + TX FIFO message empty interrupt enable. +1, enable the TX FIFO massage empty interrupt. +0, disable the TX FIFO message empty interrupt. + 6 + 1 + read-write + + + RFMAIE + RX FIFO message available interrupt enable. +1, enable the RX FIFO massage available interrupt. +0, disable the RX FIFO message available interrupt. + 5 + 1 + read-write + + + RFMFIE + RX fifo message full interrupt enable. +1, enable the RX fifo message full interrupt. +0, disable the RX fifo message full interrupt. + 4 + 1 + read-write + + + RESERVED + Reserved + 2 + 2 + read-only + + + TWMEIE + TX word message empty interrupt enable. +1, enable the TX word massage empty interrupt. +0, disable the TX word message empty interrupt. + 1 + 1 + read-write + + + RWMVIE + RX word message valid interrupt enable. +1, enable the RX word massage valid interrupt. +0, disable the RX word message valid interrupt. + 0 + 1 + read-write + + + + + SR + Status Registers + 0x4 + 32 + 0x000000E2 + 0xFFFF3FFF + + + RESERVED + Not used + 24 + 8 + read-only + + + RFVC + RX FIFO valid message count + 20 + 4 + read-only + + + TFEC + TX FIFO empty message word count + 16 + 4 + read-only + + + ERRRE + bus Error for read when rx word message are still invalid, this bit is W1C bit. +1, read from word message when the word message are still invalid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 13 + 1 + write-only + + + EWTRF + bus Error for write when tx word message are still valid, this bit is W1C bit. +1, write to word message when the word message are still valid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 12 + 1 + write-only + + + ERRFE + bus Error for read when rx fifo empty, this bit is W1C bit. +1, read from a empty rx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 11 + 1 + write-only + + + EWTFF + bus Error for write when tx fifo full, this bit is W1C bit. +1, write to a fulled tx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 10 + 1 + write-only + + + EAIVA + bus Error for Accessing Invalid Address; this bit is W1C bit. +1, read and write to invalid address in the bus of this block, will set this bit. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 9 + 1 + write-only + + + EW2RO + bus Error for Write to Read Only address; this bit is W1C bit. +1, write to read only address happened in the bus of this block. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 8 + 1 + write-only + + + TFMA + TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. +1, TXFIFO message buffer has slot available +0, no slot available (fifo full) + 7 + 1 + read-write + + + TFME + TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. +1, no any message data in TXFIFO from other core. +0, there are some data in the 4x32 TX FIFO from other core yet. + 6 + 1 + read-write + + + RFMA + RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, no any data in the 4x32 TXFIFO message buffer. +0, there are some data in the the 4x32 TXFIFO message buffer already. + 5 + 1 + read-only + + + RFMF + RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written 4x32 message in the RXFIFO. +0, no 4x32 RX FIFO message from other core yet. + 4 + 1 + read-only + + + RESERVED + Not used + 2 + 2 + read-only + + + TWME + TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, means this core had write word message to TXREG. +0, means no valid word message in the TXREG yet. + 1 + 1 + read-only + + + RWMV + RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written word message in the RXREG. +0, no valid word message yet in the RXREG. + 0 + 1 + read-only + + + + + TXREG + Transmit word message to other core. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXREG + Transmit word message to other core. + 0 + 32 + write-only + + + + + RXREG + Receive word message from other core. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RXREG + Receive word message from other core. + 0 + 32 + read-only + + + + + TXWRD_TXFIFO0 + TXFIFO for sending message to other core + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFIFO + TXFIFO for sending message to other core, FIFO size, 4x32 +can write one of the word address to push data to the FIFO; +can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. + 0 + 32 + write-only + + + + + RXWRD_RXFIFO0 + RXFIFO for receiving message from other core + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFIFO + RXFIFO for receiving message from other core, FIFO size, 4x32 +can read one of the word address to pop data to the FIFO; +can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. + 0 + 32 + read-only + + + + + + + MBX0B + MBX0B + MBX + 0xf00a4000 + + + MBX1A + MBX1A + MBX + 0xf00a8000 + + + MBX1B + MBX1B + MBX + 0xf00ac000 + + + PTPC + PTPC + PTPC + 0xf00b0000 + + 0x0 + 0x200c + registers + + + + PTPC_0_CTRL0 + Control Register 0 + 0x0 + 32 + 0x00000000 + 0x000003FF + + + SUBSEC_DIGITAL_ROLLOVER + Format for ns counter rollover, +1-digital, overflow time 1000000000/0x3B9ACA00 +0-binary, overflow time 0x7FFFFFFF + 9 + 1 + read-write + + + CAPT_SNAP_KEEP + set will keep capture snap till software read capt_snapl. +If this bit is set, software should read capt_snaph first to avoid wrong result. +If this bit is cleared, capture result will be updated at each capture event + 8 + 1 + read-write + + + CAPT_SNAP_POS_EN + set will use posege of input capture signal to latch timestamp value + 7 + 1 + read-write + + + CAPT_SNAP_NEG_EN + No description avaiable + 6 + 1 + read-write + + + RESERVED + No description avaiable + 5 + 1 + read-write + + + COMP_EN + set to enable compare, will be cleared by HW when compare event triggered + 4 + 1 + read-write + + + UPDATE_TIMER + update timer with +/- ts_updt, pulse, clear after set + 3 + 1 + write-only + + + INIT_TIMER + initial timer with ts_updt, pulse, clear after set + 2 + 1 + write-only + + + FINE_COARSE_SEL + 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow +1: coarse update, ns counter add ss_incr[7:0] each clk + 1 + 1 + read-write + + + TIMER_ENABLE + No description avaiable + 0 + 1 + read-write + + + + + PTPC_0_CTRL1 + Control Register 1 + 0x4 + 32 + 0x00000000 + 0x000000FF + + + SS_INCR + constant value used to add ns counter; +such as for 50MHz timer clock, set it to 8'd20 + 0 + 8 + read-write + + + + + PTPC_0_TIMEH + timestamp high + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_HIGH + No description avaiable + 0 + 32 + read-only + + + + + PTPC_0_TIMEL + timestamp low + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_LOW + No description avaiable + 0 + 32 + read-only + + + + + PTPC_0_TS_UPDTH + timestamp update high + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_UPDATE + together with ts_updtl, used to initial or update timestamp + 0 + 32 + read-write + + + + + PTPC_0_TS_UPDTL + timestamp update low + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADD_SUB + 1 for sub; 0 for add, used only at update + 31 + 1 + read-write + + + NS_UPDATE + No description avaiable + 0 + 31 + read-write + + + + + PTPC_0_ADDEND + No description avaiable + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDEND + used in fine update mode only + 0 + 32 + read-write + + + + + PTPC_0_TARH + No description avaiable + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_HIGH + used for generate compare signal if enabled + 0 + 32 + read-write + + + + + PTPC_0_TARL + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_LOW + No description avaiable + 0 + 32 + read-write + + + + + PTPC_0_PPS_CTRL + No description avaiable + 0x2c + 32 + 0x00000000 + 0x0000000F + + + PPS_CTRL + No description avaiable + 0 + 4 + read-write + + + + + PTPC_0_CAPT_SNAPH + No description avaiable + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_HIGH + take snapshot for input capture signal, at pos or neg or both; +the result can be kept or updated at each event according to cfg0.bit8 + 0 + 32 + read-only + + + + + PTPC_0_CAPT_SNAPL + No description avaiable + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_LOW + No description avaiable + 0 + 32 + read-write + + + + + PTPC_1_CTRL0 + Control Register 0 + 0x1000 + 32 + 0x00000000 + 0x000003FF + + + SUBSEC_DIGITAL_ROLLOVER + Format for ns counter rollover, +1-digital, overflow time 1000000000/0x3B9ACA00 +0-binary, overflow time 0x7FFFFFFF + 9 + 1 + read-write + + + CAPT_SNAP_KEEP + set will keep capture snap till software read capt_snapl. +If this bit is set, software should read capt_snaph first to avoid wrong result. +If this bit is cleared, capture result will be updated at each capture event + 8 + 1 + read-write + + + CAPT_SNAP_POS_EN + set will use posege of input capture signal to latch timestamp value + 7 + 1 + read-write + + + CAPT_SNAP_NEG_EN + No description avaiable + 6 + 1 + read-write + + + RESERVED + No description avaiable + 5 + 1 + read-write + + + COMP_EN + set to enable compare, will be cleared by HW when compare event triggered + 4 + 1 + read-write + + + UPDATE_TIMER + update timer with +/- ts_updt, pulse, clear after set + 3 + 1 + write-only + + + INIT_TIMER + initial timer with ts_updt, pulse, clear after set + 2 + 1 + write-only + + + FINE_COARSE_SEL + 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow +1: coarse update, ns counter add ss_incr[7:0] each clk + 1 + 1 + read-write + + + TIMER_ENABLE + No description avaiable + 0 + 1 + read-write + + + + + PTPC_1_CTRL1 + Control Register 1 + 0x1004 + 32 + 0x00000000 + 0x000000FF + + + SS_INCR + constant value used to add ns counter; +such as for 50MHz timer clock, set it to 8'd20 + 0 + 8 + read-write + + + + + PTPC_1_TIMEH + timestamp high + 0x1008 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_HIGH + No description avaiable + 0 + 32 + read-only + + + + + PTPC_1_TIMEL + timestamp low + 0x100c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_LOW + No description avaiable + 0 + 32 + read-only + + + + + PTPC_1_TS_UPDTH + timestamp update high + 0x1010 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_UPDATE + together with ts_updtl, used to initial or update timestamp + 0 + 32 + read-write + + + + + PTPC_1_TS_UPDTL + timestamp update low + 0x1014 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADD_SUB + 1 for sub; 0 for add, used only at update + 31 + 1 + read-write + + + NS_UPDATE + No description avaiable + 0 + 31 + read-write + + + + + PTPC_1_ADDEND + No description avaiable + 0x1018 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDEND + used in fine update mode only + 0 + 32 + read-write + + + + + PTPC_1_TARH + No description avaiable + 0x101c + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_HIGH + used for generate compare signal if enabled + 0 + 32 + read-write + + + + + PTPC_1_TARL + No description avaiable + 0x1020 + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_LOW + No description avaiable + 0 + 32 + read-write + + + + + PTPC_1_PPS_CTRL + No description avaiable + 0x102c + 32 + 0x00000000 + 0x0000000F + + + PPS_CTRL + No description avaiable + 0 + 4 + read-write + + + + + PTPC_1_CAPT_SNAPH + No description avaiable + 0x1030 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_HIGH + take snapshot for input capture signal, at pos or neg or both; +the result can be kept or updated at each event according to cfg0.bit8 + 0 + 32 + read-only + + + + + PTPC_1_CAPT_SNAPL + No description avaiable + 0x1034 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_LOW + No description avaiable + 0 + 32 + read-write + + + + + TIME_SEL + No description avaiable + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + CAN3_TIME_SEL + No description avaiable + 3 + 1 + read-write + + + CAN2_TIME_SEL + No description avaiable + 2 + 1 + read-write + + + CAN1_TIME_SEL + No description avaiable + 1 + 1 + read-write + + + CAN0_TIME_SEL + set to use ptpc1 for canx +clr to use ptpc0 for canx + 0 + 1 + read-write + + + + + INT_STS + No description avaiable + 0x2004 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description avaiable + 18 + 1 + write-only + + + CAPTURE_INT_STS1 + No description avaiable + 17 + 1 + write-only + + + PPS_INT_STS1 + No description avaiable + 16 + 1 + write-only + + + COMP_INT_STS0 + No description avaiable + 2 + 1 + write-only + + + CAPTURE_INT_STS0 + No description avaiable + 1 + 1 + write-only + + + PPS_INT_STS0 + No description avaiable + 0 + 1 + write-only + + + + + INT_EN + No description avaiable + 0x2008 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description avaiable + 18 + 1 + read-write + + + CAPTURE_INT_STS1 + No description avaiable + 17 + 1 + read-write + + + PPS_INT_STS1 + No description avaiable + 16 + 1 + read-write + + + COMP_INT_STS0 + No description avaiable + 2 + 1 + read-write + + + CAPTURE_INT_STS0 + No description avaiable + 1 + 1 + read-write + + + PPS_INT_STS0 + No description avaiable + 0 + 1 + read-write + + + + + + + CRC + CRC + CRC + 0xf00b8000 + + 0x0 + 0x200 + registers + + + + CHN_0_PRE_SET + 0 pre set for crc setting + 0x0 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + CHN_0_CLR + chn0 clear crc result and setting + 0x4 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + CHN_0_POLY + chn0 poly + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + CHN_0_INIT_DATA + chn0 init_data + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + CHN_0_XOROUT + chn0 xorout + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + CHN_0_MISC_SETTING + chn0 misc_setting + 0x14 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + CHN_0_DATA + chn0 data + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + CHN_0_RESULT + chn0 result + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + CHN_1_PRE_SET + 1 pre set for crc setting + 0x40 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + CHN_1_CLR + chn1 clear crc result and setting + 0x44 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + CHN_1_POLY + chn1 poly + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + CHN_1_INIT_DATA + chn1 init_data + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + CHN_1_XOROUT + chn1 xorout + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + CHN_1_MISC_SETTING + chn1 misc_setting + 0x54 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + CHN_1_DATA + chn1 data + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + CHN_1_RESULT + chn1 result + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + CHN_2_PRE_SET + 2 pre set for crc setting + 0x80 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + CHN_2_CLR + chn2 clear crc result and setting + 0x84 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + CHN_2_POLY + chn2 poly + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + CHN_2_INIT_DATA + chn2 init_data + 0x8c + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + CHN_2_XOROUT + chn2 xorout + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + CHN_2_MISC_SETTING + chn2 misc_setting + 0x94 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + CHN_2_DATA + chn2 data + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + CHN_2_RESULT + chn2 result + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + CHN_3_PRE_SET + 3 pre set for crc setting + 0xc0 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + CHN_3_CLR + chn3 clear crc result and setting + 0xc4 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + CHN_3_POLY + chn3 poly + 0xc8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + CHN_3_INIT_DATA + chn3 init_data + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + CHN_3_XOROUT + chn3 xorout + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + CHN_3_MISC_SETTING + chn3 misc_setting + 0xd4 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + CHN_3_DATA + chn3 data + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + CHN_3_RESULT + chn3 result + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + CHN_4_PRE_SET + 4 pre set for crc setting + 0x100 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + CHN_4_CLR + chn4 clear crc result and setting + 0x104 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + CHN_4_POLY + chn4 poly + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + CHN_4_INIT_DATA + chn4 init_data + 0x10c + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + CHN_4_XOROUT + chn4 xorout + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + CHN_4_MISC_SETTING + chn4 misc_setting + 0x114 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + CHN_4_DATA + chn4 data + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + CHN_4_RESULT + chn4 result + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + CHN_5_PRE_SET + 5 pre set for crc setting + 0x140 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + CHN_5_CLR + chn5 clear crc result and setting + 0x144 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + CHN_5_POLY + chn5 poly + 0x148 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + CHN_5_INIT_DATA + chn5 init_data + 0x14c + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + CHN_5_XOROUT + chn5 xorout + 0x150 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + CHN_5_MISC_SETTING + chn5 misc_setting + 0x154 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + CHN_5_DATA + chn5 data + 0x158 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + CHN_5_RESULT + chn5 result + 0x15c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + CHN_6_PRE_SET + 6 pre set for crc setting + 0x180 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + CHN_6_CLR + chn6 clear crc result and setting + 0x184 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + CHN_6_POLY + chn6 poly + 0x188 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + CHN_6_INIT_DATA + chn6 init_data + 0x18c + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + CHN_6_XOROUT + chn6 xorout + 0x190 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + CHN_6_MISC_SETTING + chn6 misc_setting + 0x194 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + CHN_6_DATA + chn6 data + 0x198 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + CHN_6_RESULT + chn6 result + 0x19c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + CHN_7_PRE_SET + 7 pre set for crc setting + 0x1c0 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + CHN_7_CLR + chn7 clear crc result and setting + 0x1c4 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + CHN_7_POLY + chn7 poly + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + CHN_7_INIT_DATA + chn7 init_data + 0x1cc + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + CHN_7_XOROUT + chn7 xorout + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + CHN_7_MISC_SETTING + chn7 misc_setting + 0x1d4 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + CHN_7_DATA + chn7 data + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + CHN_7_RESULT + chn7 result + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + + + DMAMUX + DMAMUX + DMAMUX + 0xf00c0000 + + 0x0 + 0x40 + registers + + + + MUXCFG_HDMA_MUX0 + HDMA MUX0 Configuration + 0x0 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX1 + HDMA MUX1 Configuration + 0x4 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX2 + HDMA MUX2 Configuration + 0x8 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX3 + HDMA MUX3 Configuration + 0xc + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX4 + HDMA MUX4 Configuration + 0x10 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX5 + HDMA MUX5 Configuration + 0x14 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX6 + HDMA MUX6 Configuration + 0x18 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_HDMA_MUX7 + HDMA MUX7 Configuration + 0x1c + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX0 + XDMA MUX0 Configuration + 0x20 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX1 + XDMA MUX1 Configuration + 0x24 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX2 + XDMA MUX2 Configuration + 0x28 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX3 + XDMA MUX3 Configuration + 0x2c + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX4 + XDMA MUX4 Configuration + 0x30 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX5 + XDMA MUX5 Configuration + 0x34 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX6 + XDMA MUX6 Configuration + 0x38 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + MUXCFG_XDMA_MUX7 + XDMA MUX7 Configuration + 0x3c + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + + + HDMA + HDMA + DMA + 0xf00c4000 + + 0x0 + 0x140 + registers + + + + IDMISC + ID Misc + 0x4 + 32 + 0x00000000 + 0x00008000 + + + IDLE_FLAG + DMA Idle Flag +0 - DMA is busy +1 - DMA is dile + 15 + 1 + read-only + + + + + DMACFG + DMAC Configuration Register + 0x10 + 32 + 0x00000000 + 0xC3FFFFFF + + + CHAINXFR + Chain transfer +0x0: Chain transfer is not configured +0x1: Chain transfer is configured + 31 + 1 + read-only + + + REQSYNC + DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. +0x0: Request synchronization is not configured +0x1: Request synchronization is configured + 30 + 1 + read-only + + + DATAWIDTH + AXI bus data width +0x0: 32 bits +0x1: 64 bits +0x2: 128 bits +0x3: 256 bits + 24 + 2 + read-only + + + ADDRWIDTH + AXI bus address width +0x18: 24 bits +0x19: 25 bits +... +0x40: 64 bits +Others: Invalid + 17 + 7 + read-only + + + CORENUM + DMA core number +0x0: 1 core +0x1: 2 cores + 16 + 1 + read-only + + + BUSNUM + AXI bus interface number +0x0: 1 AXI bus +0x1: 2 AXI busses + 15 + 1 + read-only + + + REQNUM + Request/acknowledge pair number +0x0: 0 pair +0x1: 1 pair +0x2: 2 pairs +... +0x10: 16 pairs + 10 + 5 + read-only + + + FIFODEPTH + FIFO depth +0x4: 4 entries +0x8: 8 entries +0x10: 16 entries +0x20: 32 entries +Others: Invalid + 4 + 6 + read-only + + + CHANNELNUM + Channel number +0x1: 1 channel +0x2: 2 channels +... +0x8: 8 channels +Others: Invalid + 0 + 4 + read-only + + + + + DMACTRL + DMAC Control Register + 0x20 + 32 + 0x00000000 + 0x00000001 + + + RESET + Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. +Note: The software reset may cause the in-completion of AXI transaction. + 0 + 1 + write-only + + + + + CHABORT + Channel Abort Register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHABORT + Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + 0 + 32 + write-only + + + + + INTSTATUS + Interrupt Status Register + 0x30 + 32 + 0x00000000 + 0x00FFFFFF + + + TC + The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. +0x0: Channel n has no terminal count status +0x1: Channel n has terminal count status + 16 + 8 + write-only + + + ABORT + The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. +0x0: Channel n has no abort status +0x1: Channel n has abort status + 8 + 8 + write-only + + + ERROR + The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: +- Bus error +- Unaligned address +- Unaligned transfer width +- Reserved configuration +0x0: Channel n has no error status +0x1: Channel n has error status + 0 + 8 + write-only + + + + + CHEN + Channel Enable Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHEN + Alias of the Enable field of all ChnCtrl registers + 0 + 32 + read-only + + + + + CHCTRL_CH0_CTRL + Channel n Control Register + 0x40 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH0_TRANSIZE + Channel n Transfer Size Register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH0_SRCADDR + Channel n Source Address Low Part Register + 0x48 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH0_SRCADDRH + Channel n Source Address High Part Register + 0x4c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH0_DSTADDR + Channel n Destination Address Low Part Register + 0x50 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH0_DSTADDRH + Channel n Destination Address High Part Register + 0x54 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH0_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x58 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH0_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH1_CTRL + Channel n Control Register + 0x60 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH1_TRANSIZE + Channel n Transfer Size Register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH1_SRCADDR + Channel n Source Address Low Part Register + 0x68 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH1_SRCADDRH + Channel n Source Address High Part Register + 0x6c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH1_DSTADDR + Channel n Destination Address Low Part Register + 0x70 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH1_DSTADDRH + Channel n Destination Address High Part Register + 0x74 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH1_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x78 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH1_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH2_CTRL + Channel n Control Register + 0x80 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH2_TRANSIZE + Channel n Transfer Size Register + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH2_SRCADDR + Channel n Source Address Low Part Register + 0x88 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH2_SRCADDRH + Channel n Source Address High Part Register + 0x8c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH2_DSTADDR + Channel n Destination Address Low Part Register + 0x90 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH2_DSTADDRH + Channel n Destination Address High Part Register + 0x94 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH2_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x98 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH2_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH3_CTRL + Channel n Control Register + 0xa0 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH3_TRANSIZE + Channel n Transfer Size Register + 0xa4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH3_SRCADDR + Channel n Source Address Low Part Register + 0xa8 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH3_SRCADDRH + Channel n Source Address High Part Register + 0xac + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH3_DSTADDR + Channel n Destination Address Low Part Register + 0xb0 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH3_DSTADDRH + Channel n Destination Address High Part Register + 0xb4 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH3_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0xb8 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH3_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0xbc + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH4_CTRL + Channel n Control Register + 0xc0 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH4_TRANSIZE + Channel n Transfer Size Register + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH4_SRCADDR + Channel n Source Address Low Part Register + 0xc8 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH4_SRCADDRH + Channel n Source Address High Part Register + 0xcc + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH4_DSTADDR + Channel n Destination Address Low Part Register + 0xd0 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH4_DSTADDRH + Channel n Destination Address High Part Register + 0xd4 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH4_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0xd8 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH4_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH5_CTRL + Channel n Control Register + 0xe0 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH5_TRANSIZE + Channel n Transfer Size Register + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH5_SRCADDR + Channel n Source Address Low Part Register + 0xe8 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH5_SRCADDRH + Channel n Source Address High Part Register + 0xec + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH5_DSTADDR + Channel n Destination Address Low Part Register + 0xf0 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH5_DSTADDRH + Channel n Destination Address High Part Register + 0xf4 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH5_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0xf8 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH5_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH6_CTRL + Channel n Control Register + 0x100 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH6_TRANSIZE + Channel n Transfer Size Register + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH6_SRCADDR + Channel n Source Address Low Part Register + 0x108 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH6_SRCADDRH + Channel n Source Address High Part Register + 0x10c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH6_DSTADDR + Channel n Destination Address Low Part Register + 0x110 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH6_DSTADDRH + Channel n Destination Address High Part Register + 0x114 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH6_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x118 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH6_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH7_CTRL + Channel n Control Register + 0x120 + 32 + 0x00000000 + 0xEFFFFFFF + + + SRCBUSINFIDX + Bus interface index that source data is read from +0x0: Data is read from bus interface 0 +0x1: Data is read from bus interface + 31 + 1 + read-write + + + DSTBUSINFIDX + Bus interface index that destination data is written to +0x0: Data is written to bus interface 0 +0x1: Data is written to bus interface 1 + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 8 + 4 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 4 + 4 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + CHCTRL_CH7_TRANSIZE + Channel n Transfer Size Register + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 32 + read-write + + + + + CHCTRL_CH7_SRCADDR + Channel n Source Address Low Part Register + 0x128 + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH7_SRCADDRH + Channel n Source Address High Part Register + 0x12c + 32 + 0x00000001 + 0xFFFFFFFF + + + SRCADDRH + High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH7_DSTADDR + Channel n Destination Address Low Part Register + 0x130 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + CHCTRL_CH7_DSTADDRH + Channel n Destination Address High Part Register + 0x134 + 32 + 0x00000001 + 0xFFFFFFFF + + + DSTADDRH + High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + CHCTRL_CH7_LLPOINTER + Channel n Linked List Pointer Low Part Register + 0x138 + 32 + 0x00000000 + 0xFFFFFFF9 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + LLDBUSINFIDX + Bus interface index that the next descriptor is read from +0x0: The next descriptor is read from bus interface 0 + 0 + 1 + read-write + + + + + CHCTRL_CH7_LLPOINTERH + Channel n Linked List Pointer High Part Register + 0x13c + 32 + 0x00000000 + 0xFFFFFFFF + + + LLPOINTERH + High part of the pointer to the next descriptor. +This register exists only when the address bus width is wider than 32 bits. + 0 + 32 + read-write + + + + + + + XDMA + XDMA + DMA + 0xf3048000 + + + RNG + RNG + RNG + 0xf00c8000 + + 0x0 + 0x40 + registers + + + + CMD + Command Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + Not used + 7 + 25 + read-write + + + SFTRST + Soft Reset, Perform a software reset of the RNG This bit is self-clearing. +0 Do not perform a software reset. +1 Software reset + 6 + 1 + read-write + + + CLRERR + Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. +0 Do not clear the errors and the interrupt. +1 Clear the errors and the interrupt. + 5 + 1 + read-write + + + CLRINT + Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. +0 Do not clear the interrupt. +1 Clear the interrupt + 4 + 1 + read-write + + + RESERVED + Not used + 2 + 2 + read-only + + + GENSD + Generate Seed, when both ST and GS triggered, ST first and GS next. + 1 + 1 + read-write + + + SLFCHK + Self Test, when both ST and GS triggered, ST first and GS next. + 0 + 1 + read-write + + + + + CTRL + Control Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + Not used + 7 + 25 + read-only + + + MIRQERR + Mask Interrupt Request for Error + 6 + 1 + read-write + + + MIRQDN + Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: +• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). +• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. + 5 + 1 + read-write + + + AUTRSD + Auto Reseed + 4 + 1 + read-write + + + RESERVED + Not used + 2 + 2 + read-only + + + FUFMOD + FIFO underflow response mode +00 Return all zeros and set the ESR[FUFE]. +01 Return all zeros and set the ESR[FUFE]. +10 Generate the bus transfer error +11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). + 0 + 2 + read-write + + + + + STA + Status Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + Not used + 24 + 8 + read-only + + + SCPF + Self Check Pass Fail + 21 + 3 + read-only + + + RESERVED + Not used + 17 + 4 + read-only + + + FUNCERR + Error was detected, check ESR register for details + 16 + 1 + read-only + + + FSIZE + Fifo Size, it is 5 in this design. + 12 + 4 + read-only + + + FRNNU + Fifo Level, Indicates the number of random words currently in the output FIFO + 8 + 4 + read-only + + + RESERVED + Not used + 7 + 1 + read-only + + + NSDDN + New seed done. + 6 + 1 + read-only + + + FSDDN + 1st Seed done +When "1", Indicates that the RNG generated the first seed. + 5 + 1 + read-only + + + SCDN + Self Check Done +Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is +initiated by setting the CMD[ST]. +0 Self test not completed +1 Completed a self test since the last reset. + 4 + 1 + read-only + + + RSDREQ + Reseed needed +Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or +automatically if the CTRL[ARS] is set. + 3 + 1 + read-only + + + IDLE + Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. + 2 + 1 + read-only + + + BUSY + when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. + 1 + 1 + read-only + + + RESERVED + Not used + 0 + 1 + read-only + + + + + ERR + Error Registers + 0xc + 32 + 0x00000000 + 0xFFFFFF3F + + + RESERVED + OSC1 Satistics test pass failed. +Indicates the pass or fail status of the various statistics tests on the last seed generated. +0 Pass +1 Fail + 24 + 8 + read-only + + + RESERVED + OSC0 Satistics test pass failed. +Indicates the pass or fail status of the various statistics tests on the last seed generated. +0 Pass +1 Fail + 16 + 8 + read-only + + + RESERVED + Not used + 8 + 8 + read-only + + + FUFE + FIFO access error(underflow) + 5 + 1 + read-only + + + RESERVED + Statistical test error +Indicates whether the statistical tests for the last generated seed was failed or not. This bit is sticky and is +cleared by a hardware or software reset or by writing 1 to the CMD[CE]. +0 No fail for the statistical tests. +1 Failed the statistical tests during the initialization + 4 + 1 + read-only + + + SCKERR + Self-test error +Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a +hardware reset or by writing 1 to the CMD[CE] + 3 + 1 + read-only + + + RESERVED + Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a +software or hardware reset. + 2 + 1 + read-only + + + RESERVED + Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a +software or hardware reset. + 1 + 1 + read-only + + + RESERVED + Linear feedback shift register (LFSR) error +When this bit is set, the interrupt generated was caused by a failure of one of the LFSRs in any of the RNG LFSR ciruit. + 0 + 1 + read-only + + + + + FO2B + FIFO out to bus/cpu + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2B + SW read the FIFO output. + 0 + 32 + read-only + + + + + R2SK_FO2S0 + FIFO out to SDP as AES engine key + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S1 + FIFO out to SDP as AES engine key + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S2 + FIFO out to SDP as AES engine key + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S3 + FIFO out to SDP as AES engine key + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S4 + FIFO out to SDP as AES engine key + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S5 + FIFO out to SDP as AES engine key + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S6 + FIFO out to SDP as AES engine key + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + R2SK_FO2S7 + FIFO out to SDP as AES engine key + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + + + KEYM + KEYM + KEYM + 0xf00cc000 + + 0x0 + 0x50 + registers + + + + SOFTMKEY_SFK0 + software set symmetric key + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK1 + software set symmetric key + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK2 + software set symmetric key + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK3 + software set symmetric key + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK4 + software set symmetric key + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK5 + software set symmetric key + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK6 + software set symmetric key + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTMKEY_SFK7 + software set symmetric key + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK0 + system asymmetric key + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK1 + system asymmetric key + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK2 + system asymmetric key + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK3 + system asymmetric key + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK4 + system asymmetric key + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK5 + system asymmetric key + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK6 + system asymmetric key + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SOFTPKEY_SPK7 + system asymmetric key + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SEC_KEY_CTL + secure key generation + 0x40 + 32 + 0x00000000 + 0x80011117 + + + LOCK_SEC_CTL + block secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use origin value in software symmetric key +1: use scramble version of software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use alnertave scramble of fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + secure symmtric key synthesize setting, key is a XOR of followings +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + NSC_KEY_CTL + non-secure key generation + 0x44 + 32 + 0x00000000 + 0x80011117 + + + LOCK_NSC_CTL + block non-secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use origin value in fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + non-secure symmtric key synthesize setting, key is a XOR of followings +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + RNG + Random number interface behavior + 0x48 + 32 + 0x00000000 + 0x00010001 + + + BLOCK_RNG_XOR + block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset +0: RNG_XOR can be changed by software +1: RNG_XOR ignore software change from software + 16 + 1 + read-write + + + RNG_XOR + control how SFK is accepted from random number generator +0: SFK value replaced by random number input +1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG + 0 + 1 + read-write + + + + + READ_CONTROL + key read out control + 0x4c + 32 + 0x00000000 + 0x00010001 + + + BLOCK_PK_READ + asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 16 + 1 + read-write + + + BLOCK_SMK_READ + symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 0 + 1 + read-write + + + + + + + PWM0 + PWM0 + PWM + 0xf0200000 + + 0x0 + 0x42c + registers + + + + UNLK + Shadow registers unlock register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHUNLK + write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, +otherwise the shadow registers can not be written. + 0 + 32 + read-write + + + + + STA + Counter start register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + XSTA + pwm timer counter extended start point, should back to this value after reach xrld + 28 + 4 + read-write + + + STA + pwm timer counter start value + sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk + 4 + 24 + read-write + + + RESERVED + reserved + 0 + 4 + read-write + + + + + STA_HRPWM + Counter start register + 0x4 + 32 + 0x00000000 + 0xFFFFFF00 + + + STA + No description avaiable + 8 + 24 + read-write + + + + + RLD + Counter reload register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + XRLD + timeout counter extended reload point, counter will reload to xsta after reach this point + 28 + 4 + read-write + + + RLD + pwm timer counter reload value + 4 + 24 + read-write + + + RESERVED + reserved + 0 + 4 + read-write + + + + + RLD_HRPWM + Counter reload register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RLD + No description avaiable + 8 + 24 + read-write + + + RLD_HR + pwm timer counter reload value at high resolution, only exist if hwpwm is enabled. + 0 + 8 + read-write + + + + + CMP_0 + Comparator register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_1 + Comparator register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_2 + Comparator register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_3 + Comparator register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_4 + Comparator register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_5 + Comparator register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_6 + Comparator register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_7 + Comparator register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_8 + Comparator register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_9 + Comparator register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_10 + Comparator register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_11 + Comparator register + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_12 + Comparator register + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_13 + Comparator register + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_14 + Comparator register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_15 + Comparator register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_16 + Comparator register + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_17 + Comparator register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_18 + Comparator register + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_19 + Comparator register + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_20 + Comparator register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_21 + Comparator register + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_22 + Comparator register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_23 + Comparator register + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + CMP_HRPWM_0 + Comparator register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_1 + Comparator register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_2 + Comparator register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_3 + Comparator register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_4 + Comparator register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_5 + Comparator register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_6 + Comparator register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_7 + Comparator register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_8 + Comparator register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_9 + Comparator register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_10 + Comparator register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_11 + Comparator register + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_12 + Comparator register + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_13 + Comparator register + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_14 + Comparator register + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_15 + Comparator register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_16 + Comparator register + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_17 + Comparator register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_18 + Comparator register + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_19 + Comparator register + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_20 + Comparator register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_21 + Comparator register + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_22 + Comparator register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + CMP_HRPWM_23 + Comparator register + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + No description avaiable + 8 + 24 + read-write + + + CMP_HR + high resolution compare value + 0 + 8 + read-write + + + + + FRCMD + Force output mode register + 0x78 + 32 + 0x00000000 + 0x0000FFFF + + + FRCMD + 2bit for each PWM output channel (0-7); +00: force output 0 +01: force output 1 +10: output highz +11: no force + 0 + 16 + read-write + + + + + SHLK + Shadow registers lock register + 0x7c + 32 + 0x00000000 + 0x80000000 + + + SHLK + write 1 to lock all shawdow register, wirte access is not permitted + 31 + 1 + read-write + + + + + CHCFG_0 + Output channel configure register + 0x80 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_1 + Output channel configure register + 0x84 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_2 + Output channel configure register + 0x88 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_3 + Output channel configure register + 0x8c + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_4 + Output channel configure register + 0x90 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_5 + Output channel configure register + 0x94 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_6 + Output channel configure register + 0x98 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_7 + Output channel configure register + 0x9c + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_8 + Output channel configure register + 0xa0 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_9 + Output channel configure register + 0xa4 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_10 + Output channel configure register + 0xa8 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_11 + Output channel configure register + 0xac + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_12 + Output channel configure register + 0xb0 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_13 + Output channel configure register + 0xb4 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_14 + Output channel configure register + 0xb8 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_15 + Output channel configure register + 0xbc + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_16 + Output channel configure register + 0xc0 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_17 + Output channel configure register + 0xc4 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_18 + Output channel configure register + 0xc8 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_19 + Output channel configure register + 0xcc + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_20 + Output channel configure register + 0xd0 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_21 + Output channel configure register + 0xd4 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_22 + Output channel configure register + 0xd8 + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + CHCFG_23 + Output channel configure register + 0xdc + 32 + 0x00000000 + 0xFFFF0003 + + + RESERVED + read as 0 + 29 + 3 + read-write + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + RESERVED + read as 0 + 21 + 3 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + RESERVED + read as 0 + 0 + 1 + read-write + + + + + GCR + Global control register + 0xf0 + 32 + 0x00000000 + 0xFDFFFFFF + + + FAULTI3EN + 1- enable the internal fault input 3 + 31 + 1 + read-write + + + FAULTI2EN + 1- enable the internal fault input 2 + 30 + 1 + read-write + + + FAULTI1EN + 1- enable the internal fault input 1 + 29 + 1 + read-write + + + FAULTI0EN + 1- enable the internal fault input 0 + 28 + 1 + read-write + + + DEBUGFAULT + 1- enable debug mode output protection + 27 + 1 + read-write + + + FRCPOL + polarity of input pwm_force, +1- active low +0- active high + 26 + 1 + read-write + + + HWSHDWEDG + When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. +This bit assign its which edge is used as compare shadow register hardware load event. +1- Falling edge +0- Rising edge + 24 + 1 + read-write + + + CMPSHDWSEL + This bitfield select one of the comparators as hardware event time to load comparator shadow registers + 19 + 5 + read-write + + + FAULTRECEDG + When hardware load is selected as output fault recover trigger and the selected channel is capture mode. +This bit assign its effective edge of fault recover trigger. +1- Falling edge +0- Rising edge + 18 + 1 + read-write + + + FAULTRECHWSEL + Selec one of the 24 comparators as fault output recover trigger. + 13 + 5 + read-write + + + FAULTE1EN + 1- enable the external fault input 1 + 12 + 1 + read-write + + + FAULTE0EN + 1- enable the external fault input 0 + 11 + 1 + read-write + + + FAULTEXPOL + external fault polarity +1-active low +0-active high + 9 + 2 + read-write + + + RLDSYNCEN + 1- pwm timer counter reset to reload value (rld) by synci is enabled + 8 + 1 + read-write + + + CEN + 1- enable the pwm timer counter +0- stop the pwm timer counter + 7 + 1 + read-write + + + FAULTCLR + 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. +User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. + 6 + 1 + read-write + + + XRLDSYNCEN + 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled + 5 + 1 + read-write + + + HR_PWM_EN + set to enable high resolution pwm, trig_cmp, start/reload register will have different definition. + 4 + 1 + read-write + + + TIMERRESET + set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear + 3 + 1 + read-write + + + FRCTIME + This bit field select the force effective time +00: force immediately +01: force at main counter reload time +10: force at FRCSYNCI +11: no force + 1 + 2 + write-only + + + SWFRC + 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect + 0 + 1 + read-write + + + + + SHCR + Shadow register control register + 0xf4 + 32 + 0x00000000 + 0x0000FFFF + + + CNT_UPDATE_RELOAD + set to update counter working register at reload point, clear to use cnt_update_time as old version. + 15 + 1 + read-write + + + CNT_UPDATE_EDGE + 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for counter shadow registers + 14 + 1 + read-write + + + FORCE_UPDATE_EDGE + 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for FRCMD shadow registers + 13 + 1 + read-write + + + FRCSHDWSEL + This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers + 8 + 5 + read-write + + + CNTSHDWSEL + This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) + 3 + 5 + read-write + + + CNTSHDWUPT + This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 1 + 2 + read-write + + + SHLKEN + 1- enable shadow registers lock feature, +0- disable shadow registers lock, shlk bit will always be 0 + 0 + 1 + read-write + + + + + CAPPOS_0 + Capture rising edge register + 0x100 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_1 + Capture rising edge register + 0x104 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_2 + Capture rising edge register + 0x108 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_3 + Capture rising edge register + 0x10c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_4 + Capture rising edge register + 0x110 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_5 + Capture rising edge register + 0x114 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_6 + Capture rising edge register + 0x118 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_7 + Capture rising edge register + 0x11c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_8 + Capture rising edge register + 0x120 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_9 + Capture rising edge register + 0x124 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_10 + Capture rising edge register + 0x128 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_11 + Capture rising edge register + 0x12c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_12 + Capture rising edge register + 0x130 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_13 + Capture rising edge register + 0x134 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_14 + Capture rising edge register + 0x138 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_15 + Capture rising edge register + 0x13c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_16 + Capture rising edge register + 0x140 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_17 + Capture rising edge register + 0x144 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_18 + Capture rising edge register + 0x148 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_19 + Capture rising edge register + 0x14c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_20 + Capture rising edge register + 0x150 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_21 + Capture rising edge register + 0x154 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_22 + Capture rising edge register + 0x158 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CAPPOS_23 + Capture rising edge register + 0x15c + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + CNT + Counter + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + RESERVED + read-only as 0 + 0 + 4 + read-only + + + + + CAPNEG_0 + Capture falling edge register + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_1 + Capture falling edge register + 0x184 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_2 + Capture falling edge register + 0x188 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_3 + Capture falling edge register + 0x18c + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_4 + Capture falling edge register + 0x190 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_5 + Capture falling edge register + 0x194 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_6 + Capture falling edge register + 0x198 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_7 + Capture falling edge register + 0x19c + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_8 + Capture falling edge register + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_9 + Capture falling edge register + 0x1a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_10 + Capture falling edge register + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_11 + Capture falling edge register + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_12 + Capture falling edge register + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_13 + Capture falling edge register + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_14 + Capture falling edge register + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_15 + Capture falling edge register + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_16 + Capture falling edge register + 0x1c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_17 + Capture falling edge register + 0x1c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_18 + Capture falling edge register + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_19 + Capture falling edge register + 0x1cc + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_20 + Capture falling edge register + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_21 + Capture falling edge register + 0x1d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_22 + Capture falling edge register + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPNEG_23 + Capture falling edge register + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CNTCOPY + Counter copy + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + RESERVED + read-only as 0 + 0 + 4 + read-only + + + + + PWMCFG_0 + PWM channel configure register + 0x200 + 32 + 0x00000000 + 0x3FFFFFFF + + + HR_UPDATE_MODE + 0: update the hr value for the first edge at reload point; +1: update the hr value for the first edge at the last edge; +all others will be updated at previous edge +for pair mode, only pwm_cfg 0/2/4/6 are used + 29 + 1 + read-write + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_1 + PWM channel configure register + 0x204 + 32 + 0x00000000 + 0x3FFFFFFF + + + HR_UPDATE_MODE + 0: update the hr value for the first edge at reload point; +1: update the hr value for the first edge at the last edge; +all others will be updated at previous edge +for pair mode, only pwm_cfg 0/2/4/6 are used + 29 + 1 + read-write + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_2 + PWM channel configure register + 0x208 + 32 + 0x00000000 + 0x3FFFFFFF + + + HR_UPDATE_MODE + 0: update the hr value for the first edge at reload point; +1: update the hr value for the first edge at the last edge; +all others will be updated at previous edge +for pair mode, only pwm_cfg 0/2/4/6 are used + 29 + 1 + read-write + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_3 + PWM channel configure register + 0x20c + 32 + 0x00000000 + 0x3FFFFFFF + + + HR_UPDATE_MODE + 0: update the hr value for the first edge at reload point; +1: update the hr value for the first edge at the last edge; +all others will be updated at previous edge +for pair mode, only pwm_cfg 0/2/4/6 are used + 29 + 1 + read-write + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_4 + PWM channel configure register + 0x210 + 32 + 0x00000000 + 0x3FFFFFFF + + + HR_UPDATE_MODE + 0: update the hr value for the first edge at reload point; +1: update the hr value for the first edge at the last edge; +all others will be updated at previous edge +for pair mode, only pwm_cfg 0/2/4/6 are used + 29 + 1 + read-write + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_5 + PWM channel configure register + 0x214 + 32 + 0x00000000 + 0x3FFFFFFF + + + HR_UPDATE_MODE + 0: update the hr value for the first edge at reload point; +1: update the hr value for the first edge at the last edge; +all others will be updated at previous edge +for pair mode, only pwm_cfg 0/2/4/6 are used + 29 + 1 + read-write + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_6 + PWM channel configure register + 0x218 + 32 + 0x00000000 + 0x3FFFFFFF + + + HR_UPDATE_MODE + 0: update the hr value for the first edge at reload point; +1: update the hr value for the first edge at the last edge; +all others will be updated at previous edge +for pair mode, only pwm_cfg 0/2/4/6 are used + 29 + 1 + read-write + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + PWMCFG_7 + PWM channel configure register + 0x21c + 32 + 0x00000000 + 0x3FFFFFFF + + + HR_UPDATE_MODE + 0: update the hr value for the first edge at reload point; +1: update the hr value for the first edge at the last edge; +all others will be updated at previous edge +for pair mode, only pwm_cfg 0/2/4/6 are used + 29 + 1 + read-write + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + SR + Status register + 0x220 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTF + fault condition flag + 27 + 1 + write-only + + + XRLDF + extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert + 26 + 1 + write-only + + + HALFRLDF + half reload flag, this flag set when cnt count to rld/2 + 25 + 1 + write-only + + + RLDF + reload flag, this flag set when cnt count to rld value or when SYNCI assert + 24 + 1 + write-only + + + CMPFX + comparator output compare or input capture flag + 0 + 24 + write-only + + + + + IRQEN + Interrupt request enable register + 0x224 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTIRQE + fault condition interrupt enable + 27 + 1 + read-write + + + XRLDIRQE + extended reload flag interrupt enable + 26 + 1 + read-write + + + HALFRLDIRQE + half reload flag interrupt enable + 25 + 1 + read-write + + + RLDIRQE + reload flag interrupt enable + 24 + 1 + read-write + + + CMPIRQEX + comparator output compare or input capture flag interrupt enable + 0 + 24 + read-write + + + + + DMAEN + DMA request enable register + 0x22c + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTEN + fault condition DMA request enable + 27 + 1 + read-write + + + XRLDEN + extended reload flag DMA request enable + 26 + 1 + read-write + + + HALFRLDEN + half reload flag DMA request enable + 25 + 1 + read-write + + + RLDEN + reload flag DMA request enable + 24 + 1 + read-write + + + CMPENX + comparator output compare or input capture flag DMA request enable + 0 + 24 + read-write + + + + + CMPCFG_CMPCFG0 + Comparator configure register + 0x230 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_1 + Comparator configure register + 0x234 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_2 + Comparator configure register + 0x238 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_3 + Comparator configure register + 0x23c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_4 + Comparator configure register + 0x240 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_5 + Comparator configure register + 0x244 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_6 + Comparator configure register + 0x248 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_7 + Comparator configure register + 0x24c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_8 + Comparator configure register + 0x250 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_9 + Comparator configure register + 0x254 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_10 + Comparator configure register + 0x258 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_11 + Comparator configure register + 0x25c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_12 + Comparator configure register + 0x260 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_13 + Comparator configure register + 0x264 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_14 + Comparator configure register + 0x268 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_15 + Comparator configure register + 0x26c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_16 + Comparator configure register + 0x270 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_17 + Comparator configure register + 0x274 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_18 + Comparator configure register + 0x278 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_19 + Comparator configure register + 0x27c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_20 + Comparator configure register + 0x280 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_21 + Comparator configure register + 0x284 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_22 + Comparator configure register + 0x288 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + CMPCFG_23 + Comparator configure register + 0x28c + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + RESERVED + No description avaiable + 0 + 1 + read-only + + + + + ANASTS_0 + analog status register + 0x400 + 32 + 0x00000000 + 0x80000000 + + + CALON + calibration status. +will be set by hardware after setting cal_start. +cleared after calibration finished + 31 + 1 + read-only + + + + + ANASTS_1 + analog status register + 0x404 + 32 + 0x00000000 + 0x80000000 + + + CALON + calibration status. +will be set by hardware after setting cal_start. +cleared after calibration finished + 31 + 1 + read-only + + + + + ANASTS_2 + analog status register + 0x408 + 32 + 0x00000000 + 0x80000000 + + + CALON + calibration status. +will be set by hardware after setting cal_start. +cleared after calibration finished + 31 + 1 + read-only + + + + + ANASTS_3 + analog status register + 0x40c + 32 + 0x00000000 + 0x80000000 + + + CALON + calibration status. +will be set by hardware after setting cal_start. +cleared after calibration finished + 31 + 1 + read-only + + + + + ANASTS_4 + analog status register + 0x410 + 32 + 0x00000000 + 0x80000000 + + + CALON + calibration status. +will be set by hardware after setting cal_start. +cleared after calibration finished + 31 + 1 + read-only + + + + + ANASTS_5 + analog status register + 0x414 + 32 + 0x00000000 + 0x80000000 + + + CALON + calibration status. +will be set by hardware after setting cal_start. +cleared after calibration finished + 31 + 1 + read-only + + + + + ANASTS_6 + analog status register + 0x418 + 32 + 0x00000000 + 0x80000000 + + + CALON + calibration status. +will be set by hardware after setting cal_start. +cleared after calibration finished + 31 + 1 + read-only + + + + + ANASTS_7 + analog status register + 0x41c + 32 + 0x00000000 + 0x80000000 + + + CALON + calibration status. +will be set by hardware after setting cal_start. +cleared after calibration finished + 31 + 1 + read-only + + + + + HRPWM_CFG + hrpwm config register + 0x420 + 32 + 0x00000000 + 0x000000FF + + + CAL_START + calibration start. +software setting this bit to start calibration process. +each bit for one channel. + 0 + 8 + write-only + + + + + + + PWM1 + PWM1 + PWM + 0xf0210000 + + + PWM2 + PWM2 + PWM + 0xf0220000 + + + PWM3 + PWM3 + PWM + 0xf0230000 + + + HALL0 + HALL0 + HALL + 0xf0204000 + + 0x0 + 0x88 + registers + + + + CR + Control Register + 0x0 + 32 + 0x00000000 + 0x8001083F + + + READ + 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + RESERVED + reserved + 16 + 1 + read-write + + + SNAPEN + 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert + 11 + 1 + read-write + + + RESERVED + reserved + 5 + 1 + read-write + + + RSTCNT + set to reset all counter and related snapshots + 4 + 1 + read-write + + + RESERVED + reserved + 2 + 2 + read-write + + + RESERVED + reserved + 0 + 2 + read-write + + + + + PHCFG + Phase configure register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DLYSEL + This bit select delay start time: +1- start counting delay after pre-trigger +0- start counting delay after u,v,w toggle + 31 + 1 + read-write + + + RESERVED + reserved + 24 + 7 + read-write + + + DLYCNT + delay clock cycles number + 0 + 24 + read-write + + + + + WDGCFG + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDGTO + watch dog timeout value + 0 + 31 + read-write + + + + + UVWCFG + U,V,W configure register + 0xc + 32 + 0x00000000 + 0x07FFFFFF + + + RESERVED + reserved + 24 + 3 + read-write + + + PRECNT + the clock cycle number which the pre flag will set before the next uvw transition + 0 + 24 + read-write + + + + + TRGOEN + Trigger output enable register + 0x10 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- enable trigger output when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- enable trigger output when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- enable trigger output when phdly flag set + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UFEN + 1- enable trigger output when u flag set + 23 + 1 + read-write + + + VFEN + 1- enable trigger output when v flag set + 22 + 1 + read-write + + + WFEN + 1- enable trigger output when w flag set + 21 + 1 + read-write + + + + + READEN + Read event enable register + 0x14 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- load counters to their read registers when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- load counters to their read registers when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- load counters to their read registers when phdly flag set + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UFEN + 1- load counters to their read registers when u flag set + 23 + 1 + read-write + + + VFEN + 1- load counters to their read registers when v flag set + 22 + 1 + read-write + + + WFEN + 1- load counters to their read registers when w flag set + 21 + 1 + read-write + + + + + DMAEN + DMA enable register + 0x24 + 32 + 0x00000000 + 0xFFE00000 + + + WDGEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + PHUPTEN + 1- generate dma request when phupt flag set + 30 + 1 + read-write + + + PHPREEN + 1- generate dma request when phpre flag set + 29 + 1 + read-write + + + PHDLYEN + 1- generate dma request when phdly flag set + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UFEN + 1- generate dma request when u flag set + 23 + 1 + read-write + + + VFEN + 1- generate dma request when v flag set + 22 + 1 + read-write + + + WFEN + 1- generate dma request when w flag set + 21 + 1 + read-write + + + + + SR + Status register + 0x28 + 32 + 0x00000000 + 0xFFE00000 + + + WDGF + watchdog count timeout flag + 31 + 1 + read-write + + + PHUPTF + phase update flag, will set when any of u, v, w signal toggle + 30 + 1 + read-write + + + PHPREF + phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle + 29 + 1 + read-write + + + PHDLYF + phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UF + u flag, will set when u signal toggle + 23 + 1 + read-write + + + VF + v flag, will set when v signal toggle + 22 + 1 + read-write + + + WF + w flag, will set when w signal toggle + 21 + 1 + read-write + + + + + IRQEN + Interrupt request enable register + 0x2c + 32 + 0x00000000 + 0xFFE00000 + + + WDGIE + 1- generate interrupt request when wdg flag set + 31 + 1 + read-write + + + PHUPTIE + 1- generate interrupt request when phupt flag set + 30 + 1 + read-write + + + PHPREIE + 1- generate interrupt request when phpre flag set + 29 + 1 + read-write + + + PHDLYIE + 1- generate interrupt request when phdly flag set + 28 + 1 + read-write + + + RESERVED + No description avaiable + 27 + 1 + read-write + + + RESERVED + No description avaiable + 26 + 1 + read-write + + + RESERVED + No description avaiable + 25 + 1 + read-write + + + RESERVED + No description avaiable + 24 + 1 + read-write + + + UFIE + 1- generate interrupt request when u flag set + 23 + 1 + read-write + + + VFIE + 1- generate interrupt request when v flag set + 22 + 1 + read-write + + + WFIE + 1- generate interrupt request when w flag set + 21 + 1 + read-write + + + + + COUNT_CURRENT_W + W counter + 0x30 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + COUNT_CURRENT_V + V counter + 0x34 + 32 + 0x00000000 + 0xCFFFFFFF + + + RESERVED + reserved + 31 + 1 + read-only + + + RESERVED + reserved + 30 + 1 + read-only + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + COUNT_CURRENT_U + U counter + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + COUNT_CURRENT_TMR + Timer counter + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_READ_W + W read register + 0x40 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + COUNT_READ_V + V read register + 0x44 + 32 + 0x00000000 + 0xCFFFFFFF + + + RESERVED + reserved + 31 + 1 + read-only + + + RESERVED + reserved + 30 + 1 + read-only + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + COUNT_READ_U + U read register + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + COUNT_READ_TMR + Timer read register + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_SNAP0_W + W snap register 0 + 0x50 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP0_V + V snap register 0 + 0x54 + 32 + 0x00000000 + 0xCFFFFFFF + + + RESERVED + reserved + 31 + 1 + read-only + + + RESERVED + reserved + 30 + 1 + read-only + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP0_U + Usnap register 0 + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP0_TMR + Timer snap register 0 + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_SNAP1_W + W snap register 1 + 0x60 + 32 + 0x00000000 + 0x0FFFFFFF + + + WCNT + wcnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP1_V + V snap register 1 + 0x64 + 32 + 0x00000000 + 0xCFFFFFFF + + + RESERVED + reserved + 31 + 1 + read-only + + + RESERVED + reserved + 30 + 1 + read-only + + + VCNT + vcnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP1_U + U snap register 1 + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + USTAT + this bit indicate U state + 30 + 1 + read-only + + + VSTAT + this bit indicate V state + 29 + 1 + read-only + + + WSTAT + this bit indicate W state + 28 + 1 + read-only + + + UCNT + ucnt counter + 0 + 28 + read-only + + + + + COUNT_SNAP1_TMR + Timer snap register 1 + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMER + 32 bit free run timer + 0 + 32 + read-only + + + + + HIS_U_HIS0 + history register 0 + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS0 + copy of ucnt when u signal transition from 0 to 1 + 0 + 32 + read-only + + + + + HIS_U_HIS1 + history register 1 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS1 + copy of ucnt when u signal transition from 1 to 0 + 0 + 32 + read-only + + + + + HIS_V_HIS0 + V histroy register 0 + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS0 + copy of ucnt when u signal transition from 0 to 1 + 0 + 32 + read-only + + + + + HIS_V_HIS1 + V histroy register 1 + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS1 + copy of ucnt when u signal transition from 1 to 0 + 0 + 32 + read-only + + + + + HIS_W_HIS0 + W histroy register 0 + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS0 + copy of ucnt when u signal transition from 0 to 1 + 0 + 32 + read-only + + + + + HIS_W_HIS1 + W histroy register 1 + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + UHIS1 + copy of ucnt when u signal transition from 1 to 0 + 0 + 32 + read-only + + + + + + + HALL1 + HALL1 + HALL + 0xf0214000 + + + HALL2 + HALL2 + HALL + 0xf0224000 + + + HALL3 + HALL3 + HALL + 0xf0234000 + + + QEI0 + QEI0 + QEI + 0xf0208000 + + 0x0 + 0x80 + registers + + + + CR + Control register + 0x0 + 32 + 0x00000000 + 0x80077F3F + + + READ + 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + HRSTSPD + 1- reset spdcnt when H assert + 18 + 1 + read-write + + + HRSTPH + 1- reset phcnt when H assert + 17 + 1 + read-write + + + HRSTZ + 1- reset zcnt when H assert + 16 + 1 + read-write + + + PAUSESPD + 1- pause spdcnt when PAUSE assert + 14 + 1 + read-write + + + PAUSEPH + 1- pause phcnt when PAUSE assert + 13 + 1 + read-write + + + PAUSEZ + 1- pause zcnt when PAUSE assert + 12 + 1 + read-write + + + HRDIR1 + 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) + 11 + 1 + read-write + + + HRDIR0 + 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) + 10 + 1 + read-write + + + HFDIR1 + 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) + 9 + 1 + read-write + + + HFDIR0 + 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) + 8 + 1 + read-write + + + SNAPEN + 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert + 5 + 1 + read-write + + + RSTCNT + 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx + 4 + 1 + read-write + + + RESERVED + 00-x1, phase_cnt will increase at each A posedge +01-x2, phase_cnt will increase at each A/B posedge +10-x4, phase_cnt will increase at each edge(A/B, pos/neg) + 2 + 2 + read-write + + + ENCTYP + 00-abz; 01-pd; 10-ud; 11-reserved + 0 + 2 + read-write + + + + + PHCFG + Phase configure register + 0x4 + 32 + 0x00000000 + 0x007FFFFF + + + ZCNTCFG + 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 +0- zcnt will increment or decrement when Z input assert + 22 + 1 + read-write + + + PHCALIZ + 1- phcnt will set to phidx when Z input assert + 21 + 1 + read-write + + + PHMAX + maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + 0 + 21 + read-write + + + + + WDGCFG + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDGTO + watch dog timeout value + 0 + 31 + read-write + + + + + PHIDX + Phase index register + 0xc + 32 + 0x00000000 + 0x001FFFFF + + + PHIDX + phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 + 0 + 21 + read-write + + + + + TRGOEN + Tigger output enable register + 0x10 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- enable trigger output when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- enable trigger output when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- enable trigger output when zphf flag set + 28 + 1 + read-write + + + + + READEN + Read event enable register + 0x14 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- load counters to their read registers when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- load counters to their read registers when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- load counters to their read registers when zphf flag set + 28 + 1 + read-write + + + + + ZCMP + Z comparator + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCMP + zcnt postion compare value + 0 + 32 + read-write + + + + + PHCMP + Phase comparator + 0x1c + 32 + 0x00000000 + 0xE01FFFFF + + + ZCMPDIS + 1- postion compare not include zcnt + 31 + 1 + read-write + + + DIRCMPDIS + 1- postion compare not include rotation direction + 30 + 1 + read-write + + + DIRCMP + 0- position compare need positive rotation +1- position compare need negative rotation + 29 + 1 + read-write + + + PHCMP + phcnt position compare value + 0 + 21 + read-write + + + + + SPDCMP + Speed comparator + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDCMP + spdcnt position compare value + 0 + 32 + read-write + + + + + DMAEN + DMA request enable register + 0x24 + 32 + 0x00000000 + 0xF0000000 + + + WDGFEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- generate dma request when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- generate dma request when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- generate dma request when zphf flag set + 28 + 1 + read-write + + + + + SR + Status register + 0x28 + 32 + 0x00000000 + 0xF0000000 + + + WDGF + watchdog flag + 31 + 1 + read-write + + + HOMEF + home flag + 30 + 1 + read-write + + + POSCMPF + postion compare match flag + 29 + 1 + read-write + + + ZPHF + z input flag + 28 + 1 + read-write + + + + + IRQEN + Interrupt request register + 0x2c + 32 + 0x00000000 + 0xF0000000 + + + WDGIE + 1- generate interrupt when wdg flag set + 31 + 1 + read-write + + + HOMEIE + 1- generate interrupt when homef flag set + 30 + 1 + read-write + + + POSCMPIE + 1- generate interrupt when poscmpf flag set + 29 + 1 + read-write + + + ZPHIE + 1- generate interrupt when zphf flag set + 28 + 1 + read-write + + + + + COUNT_CURRENT_Z + Z counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + COUNT_CURRENT_PH + Phase counter + 0x34 + 32 + 0x00000000 + 0x461FFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + COUNT_CURRENT_SPD + Speed counter + 0x38 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + COUNT_CURRENT_TMR + Timer counter + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_READ_Z + Z counter + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + COUNT_READ_PH + Phase counter + 0x44 + 32 + 0x00000000 + 0x461FFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + COUNT_READ_SPD + Speed counter + 0x48 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + COUNT_READ_TMR + Timer counter + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_SNAP0_Z + Z snap register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + COUNT_SNAP0_PH + Phase snap register + 0x54 + 32 + 0x00000000 + 0x461FFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + COUNT_SNAP0_SPD + Speed snap register + 0x58 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + COUNT_SNAP0_TMR + Timer snap register + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + COUNT_SNAP1_Z + Z snap register 1 + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + COUNT_SNAP1_PH + Phase snap register 1 + 0x64 + 32 + 0x00000000 + 0x461FFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + COUNT_SNAP1_SPD + Speed snap register 1 + 0x68 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + COUNT_SNAP1_TMR + Timer snap register 1 + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + SPDHIS_SPDHIS0 + Speed history + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + SPDHIS_SPDHIS1 + Speed history 1 + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + SPDHIS_SPDHIS2 + Speed history 2 + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + SPDHIS_SPDHIS3 + Speed history 3 + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDHIS0 + copy of spdcnt, load from spdcnt after any transition from a = low, b = low + 0 + 32 + read-only + + + + + + + QEI1 + QEI1 + QEI + 0xf0218000 + + + QEI2 + QEI2 + QEI + 0xf0228000 + + + QEI3 + QEI3 + QEI + 0xf0238000 + + + TRGM0 + TRGM0 + TRGM + 0xf020c000 + + 0x0 + 0x404 + registers + + + + FILTCFG_PWM_IN0 + Filter configure register + 0x0 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN1 + Filter configure register + 0x4 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN2 + Filter configure register + 0x8 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN3 + Filter configure register + 0xc + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN4 + Filter configure register + 0x10 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN5 + Filter configure register + 0x14 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN6 + Filter configure register + 0x18 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_PWM_IN7 + Filter configure register + 0x1c + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN0 + Filter configure register + 0x20 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN1 + Filter configure register + 0x24 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN2 + Filter configure register + 0x28 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN3 + Filter configure register + 0x2c + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN4 + Filter configure register + 0x30 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN5 + Filter configure register + 0x34 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN6 + Filter configure register + 0x38 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN7 + Filter configure register + 0x3c + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN8 + Filter configure register + 0x40 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN9 + Filter configure register + 0x44 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN10 + Filter configure register + 0x48 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + FILTCFG_TRGM_IN11 + Filter configure register + 0x4c + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + TRGOCFG_TRGM_OUT0 + Trigger manager output configure register + 0x100 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUT1 + Trigger manager output configure register + 0x104 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUT2 + Trigger manager output configure register + 0x108 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUT3 + Trigger manager output configure register + 0x10c + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUT4 + Trigger manager output configure register + 0x110 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUT5 + Trigger manager output configure register + 0x114 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUT6 + Trigger manager output configure register + 0x118 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUT7 + Trigger manager output configure register + 0x11c + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUT8 + Trigger manager output configure register + 0x120 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUT9 + Trigger manager output configure register + 0x124 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUT10 + Trigger manager output configure register + 0x128 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUT11 + Trigger manager output configure register + 0x12c + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUTX0 + Trigger manager output configure register + 0x130 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_TRGM_OUTX1 + Trigger manager output configure register + 0x134 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_SYNCI + Trigger manager output configure register + 0x138 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_FRCI + Trigger manager output configure register + 0x13c + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_FRCSYNCI + Trigger manager output configure register + 0x140 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_SHRLDSYNCI + Trigger manager output configure register + 0x144 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_FAULTI0 + Trigger manager output configure register + 0x148 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_FAULTI1 + Trigger manager output configure register + 0x14c + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_FAULTI2 + Trigger manager output configure register + 0x150 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_FAULTI3 + Trigger manager output configure register + 0x154 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_IN8 + Trigger manager output configure register + 0x158 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_IN9 + Trigger manager output configure register + 0x15c + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_IN10 + Trigger manager output configure register + 0x160 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_IN11 + Trigger manager output configure register + 0x164 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_IN12 + Trigger manager output configure register + 0x168 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_IN13 + Trigger manager output configure register + 0x16c + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_IN14 + Trigger manager output configure register + 0x170 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PWM_IN15 + Trigger manager output configure register + 0x174 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PLA_IN0 + Trigger manager output configure register + 0x178 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PLA_IN1 + Trigger manager output configure register + 0x17c + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PLA_IN2 + Trigger manager output configure register + 0x180 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PLA_IN3 + Trigger manager output configure register + 0x184 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PLA_IN4 + Trigger manager output configure register + 0x188 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PLA_IN5 + Trigger manager output configure register + 0x18c + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PLA_IN6 + Trigger manager output configure register + 0x190 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_PLA_IN7 + Trigger manager output configure register + 0x194 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_QEI_A + Trigger manager output configure register + 0x198 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_QEI_B + Trigger manager output configure register + 0x19c + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_QEI_Z + Trigger manager output configure register + 0x1a0 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_QEI_H + Trigger manager output configure register + 0x1a4 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_QEI_PAUSE + Trigger manager output configure register + 0x1a8 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_QEI_SNAPI + Trigger manager output configure register + 0x1ac + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_HALL_U + Trigger manager output configure register + 0x1b0 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_HALL_V + Trigger manager output configure register + 0x1b4 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_HALL_W + Trigger manager output configure register + 0x1b8 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_HALL_SNAPI + Trigger manager output configure register + 0x1bc + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_ADC0_STRGI + Trigger manager output configure register + 0x1c0 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_ADC1_STRGI + Trigger manager output configure register + 0x1c4 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_ADC2_STRGI + Trigger manager output configure register + 0x1c8 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_ADCX_PTRGI0A + Trigger manager output configure register + 0x1d0 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_ADCX_PTRGI0B + Trigger manager output configure register + 0x1d4 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_ADCX_PTRGI0C + Trigger manager output configure register + 0x1d8 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_GPTMRA_SYNCI + Trigger manager output configure register + 0x1dc + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_GPTMRA_IN2 + Trigger manager output configure register + 0x1e0 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_GPTMRA_IN3 + Trigger manager output configure register + 0x1e4 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_DAC_BUF_TRIG + Trigger manager output configure register + 0x1e8 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_DAC0_STEP_TRIG + Trigger manager output configure register + 0x1ec + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_DAC1_STEP_TRIG + Trigger manager output configure register + 0x1f0 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_CMPX_WIN + Trigger manager output configure register + 0x1f4 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_CAN_PTPC0_CAP + Trigger manager output configure register + 0x1f8 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_CAN_PTPC1_CAP + Trigger manager output configure register + 0x1fc + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_SDFM_EVT0 + Trigger manager output configure register + 0x200 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_SDFM_EVT1 + Trigger manager output configure register + 0x204 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_SDFM_EVT2 + Trigger manager output configure register + 0x208 + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + TRGOCFG_SDFM_EVT3 + Trigger manager output configure register + 0x20c + 32 + 0x00000000 + 0x000003FF + + + OUTINV + 1- Invert the output + 9 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 8 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 7 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + DMACFG_0 + DMA request configure register + 0x300 + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + DMACFG_1 + DMA request configure register + 0x304 + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + DMACFG_2 + DMA request configure register + 0x308 + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + DMACFG_3 + DMA request configure register + 0x30c + 32 + 0x00000000 + 0x0000001F + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 5 + read-write + + + + + GCR + General Control Register + 0x400 + 32 + 0x00000000 + 0x00000FFF + + + TRGOPEN + The bitfield enable the TRGM outputs. + 0 + 12 + read-write + + + + + + + TRGM1 + TRGM1 + TRGM + 0xf021c000 + + + TRGM2 + TRGM2 + TRGM + 0xf022c000 + + + TRGM3 + TRGM3 + TRGM + 0xf023c000 + + + PLA0 + PLA0 + PLA + 0xf020e000 + + 0x0 + 0x420 + registers + + + + CHN_0_AOI_16TO8_AOI_16TO8_00 + CHN0 AOI_16to8 AND logic cfg + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_0_AOI_16TO8_AOI_16TO8_01 + CHN0 AOI_16to8 AND logic cfg + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_0_AOI_16TO8_AOI_16TO8_02 + CHN0 AOI_16to8 AND logic cfg + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_0_AOI_16TO8_AOI_16TO8_03 + CHN0 AOI_16to8 AND logic cfg + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_0_AOI_16TO8_AOI_16TO8_04 + CHN0 AOI_16to8 AND logic cfg + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_0_AOI_16TO8_AOI_16TO8_05 + CHN0 AOI_16to8 AND logic cfg + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_0_AOI_16TO8_AOI_16TO8_06 + CHN0 AOI_16to8 AND logic cfg + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_0_AOI_16TO8_AOI_16TO8_07 + CHN0 AOI_16to8 AND logic cfg + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_0_AOI_8TO7_00_01 + CHN0 AOI_16to8_00_01 OR logic cfg + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_01_7 + select value for AOI_8to7_01_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_01_6 + select value for AOI_8to7_01_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_01_5 + select value for AOI_8to7_01_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_01_4 + select value for AOI_8to7_01_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_01_3 + select value for AOI_8to7_01_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_01_2 + select value for AOI_8to7_01_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_01_1 + select value for AOI_8to7_01_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_01_0 + select value for AOI_8to7_01_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_00_7 + select value for AOI_8to7_00_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_00_6 + select value for AOI_8to7_00_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_00_5 + select value for AOI_8to7_00_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_00_4 + select value for AOI_8to7_00_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_00_3 + select value for AOI_8to7_00_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_00_2 + select value for AOI_8to7_00_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_00_1 + select value for AOI_8to7_00_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_00_0 + select value for AOI_8to7_00_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_0_AOI_8TO7_02_03 + CHN0 AOI_16to8_02_03 OR logic cfg + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_03_7 + select value for AOI_8to7_03_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_03_6 + select value for AOI_8to7_03_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_03_5 + select value for AOI_8to7_03_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_03_4 + select value for AOI_8to7_03_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_03_3 + select value for AOI_8to7_03_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_03_2 + select value for AOI_8to7_03_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_03_1 + select value for AOI_8to7_03_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_03_0 + select value for AOI_8to7_03_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_02_7 + select value for AOI_8to7_02_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_02_6 + select value for AOI_8to7_02_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_02_5 + select value for AOI_8to7_02_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_02_4 + select value for AOI_8to7_02_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_02_3 + select value for AOI_8to7_02_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_02_2 + select value for AOI_8to7_02_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_02_1 + select value for AOI_8to7_02_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_02_0 + select value for AOI_8to7_02_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_0_AOI_8TO7_04_05 + CHN0 AOI_16to8_04_05 OR logic cfg + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_05_7 + select value for AOI_8to7_05_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_05_6 + select value for AOI_8to7_05_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_05_5 + select value for AOI_8to7_05_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_05_4 + select value for AOI_8to7_05_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_05_3 + select value for AOI_8to7_05_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_05_2 + select value for AOI_8to7_05_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_05_1 + select value for AOI_8to7_05_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_05_0 + select value for AOI_8to7_05_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_04_7 + select value for AOI_8to7_04_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_04_6 + select value for AOI_8to7_04_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_04_5 + select value for AOI_8to7_04_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_04_4 + select value for AOI_8to7_04_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_04_3 + select value for AOI_8to7_04_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_04_2 + select value for AOI_8to7_04_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_04_1 + select value for AOI_8to7_04_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_04_0 + select value for AOI_8to7_04_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_0_AOI_8TO7_06 + CHN0 AOI_16to8_06 OR logic cfg + 0x2c + 32 + 0x00000000 + 0x0000FFFF + + + AOI_8TO7_06_7 + select value for AOI_8to7_06_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_06_6 + select value for AOI_8to7_06_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_06_5 + select value for AOI_8to7_06_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_06_4 + select value for AOI_8to7_06_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_06_3 + select value for AOI_8to7_06_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_06_2 + select value for AOI_8to7_06_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_06_1 + select value for AOI_8to7_06_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_06_0 + select value for AOI_8to7_06_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_0_FILTER_2ND_SECOND_FILTER_0 + CHN0 SECOND_FILTER cfg + 0x30 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_2ND_SECOND_FILTER_1 + CHN0 SECOND_FILTER cfg + 0x34 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_2ND_SECOND_FILTER_2 + CHN0 SECOND_FILTER cfg + 0x38 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_2ND_SECOND_FILTER_3 + CHN0 SECOND_FILTER cfg + 0x3c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_2ND_SECOND_FILTER_4 + CHN0 SECOND_FILTER cfg + 0x40 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_2ND_SECOND_FILTER_5 + CHN0 SECOND_FILTER cfg + 0x44 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_2ND_SECOND_FILTER_6 + CHN0 SECOND_FILTER cfg + 0x48 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_2ND_SECOND_FILTER_7 + CHN0 SECOND_FILTER cfg + 0x4c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_3RD_THIRD_FILTER_0 + CHN0 THIRD_FILTER cfg + 0x50 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_3RD_THIRD_FILTER_1 + CHN0 THIRD_FILTER cfg + 0x54 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_3RD_THIRD_FILTER_2 + CHN0 THIRD_FILTER cfg + 0x58 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_3RD_THIRD_FILTER_3 + CHN0 THIRD_FILTER cfg + 0x5c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_3RD_THIRD_FILTER_4 + CHN0 THIRD_FILTER cfg + 0x60 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_3RD_THIRD_FILTER_5 + CHN0 THIRD_FILTER cfg + 0x64 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_FILTER_3RD_THIRD_FILTER_6 + CHN0 THIRD_FILTER cfg + 0x68 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_0_CFG_FF + CHN0 cfg ff + 0x6c + 32 + 0x00000000 + 0x0003001F + + + OSC_LOOP_CLAMP_VALUE + osc loop clamp value when osc ring active. +0: clamp 0. +1: clamp 1. + 17 + 1 + read-write + + + DIS_OSC_LOOP_CLAMP + disable osc loop clamp. +0: enable osc loop clamp when osc ring active. +1: disable or clean current osc loop clamp. + 16 + 1 + read-write + + + SEL_ADDER_MINUS + 0: select adder when cfg_adder_minus active. +1: select minus when cfg_adder_minus active. + 4 + 1 + read-write + + + SEL_CLK_SOURCE + cfg_ff clock source. +0: system clock. +1: use 3rd_filter_2 as clock. + 3 + 1 + read-write + + + SEL_CFG_FF_TYPE + cfg_ff type. +0: DFF. +1: 3rd_filter_0. +2: dual-edge DFF. +3: Trigger FF. +4: JK FF. +5. latch. +6: full adder/minus. + 0 + 3 + read-write + + + + + CHN_1_AOI_16TO8_AOI_16TO8_00 + CHN1 AOI_16to8 AND logic cfg + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_1_AOI_16TO8_AOI_16TO8_01 + CHN1 AOI_16to8 AND logic cfg + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_1_AOI_16TO8_AOI_16TO8_02 + CHN1 AOI_16to8 AND logic cfg + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_1_AOI_16TO8_AOI_16TO8_03 + CHN1 AOI_16to8 AND logic cfg + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_1_AOI_16TO8_AOI_16TO8_04 + CHN1 AOI_16to8 AND logic cfg + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_1_AOI_16TO8_AOI_16TO8_05 + CHN1 AOI_16to8 AND logic cfg + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_1_AOI_16TO8_AOI_16TO8_06 + CHN1 AOI_16to8 AND logic cfg + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_1_AOI_16TO8_AOI_16TO8_07 + CHN1 AOI_16to8 AND logic cfg + 0x8c + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_1_AOI_8TO7_00_01 + CHN1 AOI_16to8_00_01 OR logic cfg + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_01_7 + select value for AOI_8to7_01_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_01_6 + select value for AOI_8to7_01_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_01_5 + select value for AOI_8to7_01_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_01_4 + select value for AOI_8to7_01_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_01_3 + select value for AOI_8to7_01_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_01_2 + select value for AOI_8to7_01_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_01_1 + select value for AOI_8to7_01_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_01_0 + select value for AOI_8to7_01_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_00_7 + select value for AOI_8to7_00_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_00_6 + select value for AOI_8to7_00_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_00_5 + select value for AOI_8to7_00_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_00_4 + select value for AOI_8to7_00_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_00_3 + select value for AOI_8to7_00_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_00_2 + select value for AOI_8to7_00_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_00_1 + select value for AOI_8to7_00_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_00_0 + select value for AOI_8to7_00_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_1_AOI_8TO7_02_03 + CHN1 AOI_16to8_02_03 OR logic cfg + 0x94 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_03_7 + select value for AOI_8to7_03_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_03_6 + select value for AOI_8to7_03_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_03_5 + select value for AOI_8to7_03_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_03_4 + select value for AOI_8to7_03_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_03_3 + select value for AOI_8to7_03_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_03_2 + select value for AOI_8to7_03_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_03_1 + select value for AOI_8to7_03_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_03_0 + select value for AOI_8to7_03_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_02_7 + select value for AOI_8to7_02_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_02_6 + select value for AOI_8to7_02_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_02_5 + select value for AOI_8to7_02_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_02_4 + select value for AOI_8to7_02_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_02_3 + select value for AOI_8to7_02_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_02_2 + select value for AOI_8to7_02_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_02_1 + select value for AOI_8to7_02_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_02_0 + select value for AOI_8to7_02_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_1_AOI_8TO7_04_05 + CHN1 AOI_16to8_04_05 OR logic cfg + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_05_7 + select value for AOI_8to7_05_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_05_6 + select value for AOI_8to7_05_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_05_5 + select value for AOI_8to7_05_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_05_4 + select value for AOI_8to7_05_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_05_3 + select value for AOI_8to7_05_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_05_2 + select value for AOI_8to7_05_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_05_1 + select value for AOI_8to7_05_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_05_0 + select value for AOI_8to7_05_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_04_7 + select value for AOI_8to7_04_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_04_6 + select value for AOI_8to7_04_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_04_5 + select value for AOI_8to7_04_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_04_4 + select value for AOI_8to7_04_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_04_3 + select value for AOI_8to7_04_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_04_2 + select value for AOI_8to7_04_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_04_1 + select value for AOI_8to7_04_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_04_0 + select value for AOI_8to7_04_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_1_AOI_8TO7_06 + CHN1 AOI_16to8_06 OR logic cfg + 0x9c + 32 + 0x00000000 + 0x0000FFFF + + + AOI_8TO7_06_7 + select value for AOI_8to7_06_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_06_6 + select value for AOI_8to7_06_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_06_5 + select value for AOI_8to7_06_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_06_4 + select value for AOI_8to7_06_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_06_3 + select value for AOI_8to7_06_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_06_2 + select value for AOI_8to7_06_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_06_1 + select value for AOI_8to7_06_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_06_0 + select value for AOI_8to7_06_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_1_FILTER_2ND_SECOND_FILTER_0 + CHN1 SECOND_FILTER cfg + 0xa0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_2ND_SECOND_FILTER_1 + CHN1 SECOND_FILTER cfg + 0xa4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_2ND_SECOND_FILTER_2 + CHN1 SECOND_FILTER cfg + 0xa8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_2ND_SECOND_FILTER_3 + CHN1 SECOND_FILTER cfg + 0xac + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_2ND_SECOND_FILTER_4 + CHN1 SECOND_FILTER cfg + 0xb0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_2ND_SECOND_FILTER_5 + CHN1 SECOND_FILTER cfg + 0xb4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_2ND_SECOND_FILTER_6 + CHN1 SECOND_FILTER cfg + 0xb8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_2ND_SECOND_FILTER_7 + CHN1 SECOND_FILTER cfg + 0xbc + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_3RD_THIRD_FILTER_0 + CHN1 THIRD_FILTER cfg + 0xc0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_3RD_THIRD_FILTER_1 + CHN1 THIRD_FILTER cfg + 0xc4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_3RD_THIRD_FILTER_2 + CHN1 THIRD_FILTER cfg + 0xc8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_3RD_THIRD_FILTER_3 + CHN1 THIRD_FILTER cfg + 0xcc + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_3RD_THIRD_FILTER_4 + CHN1 THIRD_FILTER cfg + 0xd0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_3RD_THIRD_FILTER_5 + CHN1 THIRD_FILTER cfg + 0xd4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_FILTER_3RD_THIRD_FILTER_6 + CHN1 THIRD_FILTER cfg + 0xd8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_1_CFG_FF + CHN1 cfg ff + 0xdc + 32 + 0x00000000 + 0x0003001F + + + OSC_LOOP_CLAMP_VALUE + osc loop clamp value when osc ring active. +0: clamp 0. +1: clamp 1. + 17 + 1 + read-write + + + DIS_OSC_LOOP_CLAMP + disable osc loop clamp. +0: enable osc loop clamp when osc ring active. +1: disable or clean current osc loop clamp. + 16 + 1 + read-write + + + SEL_ADDER_MINUS + 0: select adder when cfg_adder_minus active. +1: select minus when cfg_adder_minus active. + 4 + 1 + read-write + + + SEL_CLK_SOURCE + cfg_ff clock source. +0: system clock. +1: use 3rd_filter_2 as clock. + 3 + 1 + read-write + + + SEL_CFG_FF_TYPE + cfg_ff type. +0: DFF. +1: 3rd_filter_0. +2: dual-edge DFF. +3: Trigger FF. +4: JK FF. +5. latch. +6: full adder/minus. + 0 + 3 + read-write + + + + + CHN_2_AOI_16TO8_AOI_16TO8_00 + CHN2 AOI_16to8 AND logic cfg + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_2_AOI_16TO8_AOI_16TO8_01 + CHN2 AOI_16to8 AND logic cfg + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_2_AOI_16TO8_AOI_16TO8_02 + CHN2 AOI_16to8 AND logic cfg + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_2_AOI_16TO8_AOI_16TO8_03 + CHN2 AOI_16to8 AND logic cfg + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_2_AOI_16TO8_AOI_16TO8_04 + CHN2 AOI_16to8 AND logic cfg + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_2_AOI_16TO8_AOI_16TO8_05 + CHN2 AOI_16to8 AND logic cfg + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_2_AOI_16TO8_AOI_16TO8_06 + CHN2 AOI_16to8 AND logic cfg + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_2_AOI_16TO8_AOI_16TO8_07 + CHN2 AOI_16to8 AND logic cfg + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_2_AOI_8TO7_00_01 + CHN2 AOI_16to8_00_01 OR logic cfg + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_01_7 + select value for AOI_8to7_01_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_01_6 + select value for AOI_8to7_01_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_01_5 + select value for AOI_8to7_01_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_01_4 + select value for AOI_8to7_01_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_01_3 + select value for AOI_8to7_01_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_01_2 + select value for AOI_8to7_01_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_01_1 + select value for AOI_8to7_01_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_01_0 + select value for AOI_8to7_01_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_00_7 + select value for AOI_8to7_00_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_00_6 + select value for AOI_8to7_00_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_00_5 + select value for AOI_8to7_00_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_00_4 + select value for AOI_8to7_00_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_00_3 + select value for AOI_8to7_00_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_00_2 + select value for AOI_8to7_00_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_00_1 + select value for AOI_8to7_00_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_00_0 + select value for AOI_8to7_00_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_2_AOI_8TO7_02_03 + CHN2 AOI_16to8_02_03 OR logic cfg + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_03_7 + select value for AOI_8to7_03_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_03_6 + select value for AOI_8to7_03_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_03_5 + select value for AOI_8to7_03_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_03_4 + select value for AOI_8to7_03_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_03_3 + select value for AOI_8to7_03_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_03_2 + select value for AOI_8to7_03_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_03_1 + select value for AOI_8to7_03_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_03_0 + select value for AOI_8to7_03_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_02_7 + select value for AOI_8to7_02_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_02_6 + select value for AOI_8to7_02_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_02_5 + select value for AOI_8to7_02_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_02_4 + select value for AOI_8to7_02_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_02_3 + select value for AOI_8to7_02_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_02_2 + select value for AOI_8to7_02_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_02_1 + select value for AOI_8to7_02_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_02_0 + select value for AOI_8to7_02_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_2_AOI_8TO7_04_05 + CHN2 AOI_16to8_04_05 OR logic cfg + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_05_7 + select value for AOI_8to7_05_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_05_6 + select value for AOI_8to7_05_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_05_5 + select value for AOI_8to7_05_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_05_4 + select value for AOI_8to7_05_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_05_3 + select value for AOI_8to7_05_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_05_2 + select value for AOI_8to7_05_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_05_1 + select value for AOI_8to7_05_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_05_0 + select value for AOI_8to7_05_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_04_7 + select value for AOI_8to7_04_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_04_6 + select value for AOI_8to7_04_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_04_5 + select value for AOI_8to7_04_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_04_4 + select value for AOI_8to7_04_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_04_3 + select value for AOI_8to7_04_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_04_2 + select value for AOI_8to7_04_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_04_1 + select value for AOI_8to7_04_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_04_0 + select value for AOI_8to7_04_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_2_AOI_8TO7_06 + CHN2 AOI_16to8_06 OR logic cfg + 0x10c + 32 + 0x00000000 + 0x0000FFFF + + + AOI_8TO7_06_7 + select value for AOI_8to7_06_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_06_6 + select value for AOI_8to7_06_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_06_5 + select value for AOI_8to7_06_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_06_4 + select value for AOI_8to7_06_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_06_3 + select value for AOI_8to7_06_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_06_2 + select value for AOI_8to7_06_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_06_1 + select value for AOI_8to7_06_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_06_0 + select value for AOI_8to7_06_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_2_FILTER_2ND_SECOND_FILTER_0 + CHN2 SECOND_FILTER cfg + 0x110 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_2ND_SECOND_FILTER_1 + CHN2 SECOND_FILTER cfg + 0x114 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_2ND_SECOND_FILTER_2 + CHN2 SECOND_FILTER cfg + 0x118 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_2ND_SECOND_FILTER_3 + CHN2 SECOND_FILTER cfg + 0x11c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_2ND_SECOND_FILTER_4 + CHN2 SECOND_FILTER cfg + 0x120 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_2ND_SECOND_FILTER_5 + CHN2 SECOND_FILTER cfg + 0x124 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_2ND_SECOND_FILTER_6 + CHN2 SECOND_FILTER cfg + 0x128 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_2ND_SECOND_FILTER_7 + CHN2 SECOND_FILTER cfg + 0x12c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_3RD_THIRD_FILTER_0 + CHN2 THIRD_FILTER cfg + 0x130 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_3RD_THIRD_FILTER_1 + CHN2 THIRD_FILTER cfg + 0x134 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_3RD_THIRD_FILTER_2 + CHN2 THIRD_FILTER cfg + 0x138 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_3RD_THIRD_FILTER_3 + CHN2 THIRD_FILTER cfg + 0x13c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_3RD_THIRD_FILTER_4 + CHN2 THIRD_FILTER cfg + 0x140 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_3RD_THIRD_FILTER_5 + CHN2 THIRD_FILTER cfg + 0x144 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_FILTER_3RD_THIRD_FILTER_6 + CHN2 THIRD_FILTER cfg + 0x148 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_2_CFG_FF + CHN2 cfg ff + 0x14c + 32 + 0x00000000 + 0x0003001F + + + OSC_LOOP_CLAMP_VALUE + osc loop clamp value when osc ring active. +0: clamp 0. +1: clamp 1. + 17 + 1 + read-write + + + DIS_OSC_LOOP_CLAMP + disable osc loop clamp. +0: enable osc loop clamp when osc ring active. +1: disable or clean current osc loop clamp. + 16 + 1 + read-write + + + SEL_ADDER_MINUS + 0: select adder when cfg_adder_minus active. +1: select minus when cfg_adder_minus active. + 4 + 1 + read-write + + + SEL_CLK_SOURCE + cfg_ff clock source. +0: system clock. +1: use 3rd_filter_2 as clock. + 3 + 1 + read-write + + + SEL_CFG_FF_TYPE + cfg_ff type. +0: DFF. +1: 3rd_filter_0. +2: dual-edge DFF. +3: Trigger FF. +4: JK FF. +5. latch. +6: full adder/minus. + 0 + 3 + read-write + + + + + CHN_3_AOI_16TO8_AOI_16TO8_00 + CHN3 AOI_16to8 AND logic cfg + 0x150 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_3_AOI_16TO8_AOI_16TO8_01 + CHN3 AOI_16to8 AND logic cfg + 0x154 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_3_AOI_16TO8_AOI_16TO8_02 + CHN3 AOI_16to8 AND logic cfg + 0x158 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_3_AOI_16TO8_AOI_16TO8_03 + CHN3 AOI_16to8 AND logic cfg + 0x15c + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_3_AOI_16TO8_AOI_16TO8_04 + CHN3 AOI_16to8 AND logic cfg + 0x160 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_3_AOI_16TO8_AOI_16TO8_05 + CHN3 AOI_16to8 AND logic cfg + 0x164 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_3_AOI_16TO8_AOI_16TO8_06 + CHN3 AOI_16to8 AND logic cfg + 0x168 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_3_AOI_16TO8_AOI_16TO8_07 + CHN3 AOI_16to8 AND logic cfg + 0x16c + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_3_AOI_8TO7_00_01 + CHN3 AOI_16to8_00_01 OR logic cfg + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_01_7 + select value for AOI_8to7_01_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_01_6 + select value for AOI_8to7_01_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_01_5 + select value for AOI_8to7_01_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_01_4 + select value for AOI_8to7_01_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_01_3 + select value for AOI_8to7_01_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_01_2 + select value for AOI_8to7_01_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_01_1 + select value for AOI_8to7_01_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_01_0 + select value for AOI_8to7_01_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_00_7 + select value for AOI_8to7_00_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_00_6 + select value for AOI_8to7_00_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_00_5 + select value for AOI_8to7_00_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_00_4 + select value for AOI_8to7_00_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_00_3 + select value for AOI_8to7_00_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_00_2 + select value for AOI_8to7_00_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_00_1 + select value for AOI_8to7_00_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_00_0 + select value for AOI_8to7_00_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_3_AOI_8TO7_02_03 + CHN3 AOI_16to8_02_03 OR logic cfg + 0x174 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_03_7 + select value for AOI_8to7_03_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_03_6 + select value for AOI_8to7_03_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_03_5 + select value for AOI_8to7_03_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_03_4 + select value for AOI_8to7_03_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_03_3 + select value for AOI_8to7_03_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_03_2 + select value for AOI_8to7_03_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_03_1 + select value for AOI_8to7_03_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_03_0 + select value for AOI_8to7_03_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_02_7 + select value for AOI_8to7_02_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_02_6 + select value for AOI_8to7_02_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_02_5 + select value for AOI_8to7_02_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_02_4 + select value for AOI_8to7_02_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_02_3 + select value for AOI_8to7_02_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_02_2 + select value for AOI_8to7_02_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_02_1 + select value for AOI_8to7_02_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_02_0 + select value for AOI_8to7_02_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_3_AOI_8TO7_04_05 + CHN3 AOI_16to8_04_05 OR logic cfg + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_05_7 + select value for AOI_8to7_05_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_05_6 + select value for AOI_8to7_05_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_05_5 + select value for AOI_8to7_05_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_05_4 + select value for AOI_8to7_05_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_05_3 + select value for AOI_8to7_05_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_05_2 + select value for AOI_8to7_05_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_05_1 + select value for AOI_8to7_05_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_05_0 + select value for AOI_8to7_05_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_04_7 + select value for AOI_8to7_04_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_04_6 + select value for AOI_8to7_04_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_04_5 + select value for AOI_8to7_04_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_04_4 + select value for AOI_8to7_04_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_04_3 + select value for AOI_8to7_04_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_04_2 + select value for AOI_8to7_04_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_04_1 + select value for AOI_8to7_04_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_04_0 + select value for AOI_8to7_04_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_3_AOI_8TO7_06 + CHN3 AOI_16to8_06 OR logic cfg + 0x17c + 32 + 0x00000000 + 0x0000FFFF + + + AOI_8TO7_06_7 + select value for AOI_8to7_06_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_06_6 + select value for AOI_8to7_06_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_06_5 + select value for AOI_8to7_06_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_06_4 + select value for AOI_8to7_06_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_06_3 + select value for AOI_8to7_06_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_06_2 + select value for AOI_8to7_06_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_06_1 + select value for AOI_8to7_06_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_06_0 + select value for AOI_8to7_06_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_3_FILTER_2ND_SECOND_FILTER_0 + CHN3 SECOND_FILTER cfg + 0x180 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_2ND_SECOND_FILTER_1 + CHN3 SECOND_FILTER cfg + 0x184 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_2ND_SECOND_FILTER_2 + CHN3 SECOND_FILTER cfg + 0x188 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_2ND_SECOND_FILTER_3 + CHN3 SECOND_FILTER cfg + 0x18c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_2ND_SECOND_FILTER_4 + CHN3 SECOND_FILTER cfg + 0x190 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_2ND_SECOND_FILTER_5 + CHN3 SECOND_FILTER cfg + 0x194 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_2ND_SECOND_FILTER_6 + CHN3 SECOND_FILTER cfg + 0x198 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_2ND_SECOND_FILTER_7 + CHN3 SECOND_FILTER cfg + 0x19c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_3RD_THIRD_FILTER_0 + CHN3 THIRD_FILTER cfg + 0x1a0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_3RD_THIRD_FILTER_1 + CHN3 THIRD_FILTER cfg + 0x1a4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_3RD_THIRD_FILTER_2 + CHN3 THIRD_FILTER cfg + 0x1a8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_3RD_THIRD_FILTER_3 + CHN3 THIRD_FILTER cfg + 0x1ac + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_3RD_THIRD_FILTER_4 + CHN3 THIRD_FILTER cfg + 0x1b0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_3RD_THIRD_FILTER_5 + CHN3 THIRD_FILTER cfg + 0x1b4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_FILTER_3RD_THIRD_FILTER_6 + CHN3 THIRD_FILTER cfg + 0x1b8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_3_CFG_FF + CHN3 cfg ff + 0x1bc + 32 + 0x00000000 + 0x0003001F + + + OSC_LOOP_CLAMP_VALUE + osc loop clamp value when osc ring active. +0: clamp 0. +1: clamp 1. + 17 + 1 + read-write + + + DIS_OSC_LOOP_CLAMP + disable osc loop clamp. +0: enable osc loop clamp when osc ring active. +1: disable or clean current osc loop clamp. + 16 + 1 + read-write + + + SEL_ADDER_MINUS + 0: select adder when cfg_adder_minus active. +1: select minus when cfg_adder_minus active. + 4 + 1 + read-write + + + SEL_CLK_SOURCE + cfg_ff clock source. +0: system clock. +1: use 3rd_filter_2 as clock. + 3 + 1 + read-write + + + SEL_CFG_FF_TYPE + cfg_ff type. +0: DFF. +1: 3rd_filter_0. +2: dual-edge DFF. +3: Trigger FF. +4: JK FF. +5. latch. +6: full adder/minus. + 0 + 3 + read-write + + + + + CHN_4_AOI_16TO8_AOI_16TO8_00 + CHN4 AOI_16to8 AND logic cfg + 0x1c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_4_AOI_16TO8_AOI_16TO8_01 + CHN4 AOI_16to8 AND logic cfg + 0x1c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_4_AOI_16TO8_AOI_16TO8_02 + CHN4 AOI_16to8 AND logic cfg + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_4_AOI_16TO8_AOI_16TO8_03 + CHN4 AOI_16to8 AND logic cfg + 0x1cc + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_4_AOI_16TO8_AOI_16TO8_04 + CHN4 AOI_16to8 AND logic cfg + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_4_AOI_16TO8_AOI_16TO8_05 + CHN4 AOI_16to8 AND logic cfg + 0x1d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_4_AOI_16TO8_AOI_16TO8_06 + CHN4 AOI_16to8 AND logic cfg + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_4_AOI_16TO8_AOI_16TO8_07 + CHN4 AOI_16to8 AND logic cfg + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_4_AOI_8TO7_00_01 + CHN4 AOI_16to8_00_01 OR logic cfg + 0x1e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_01_7 + select value for AOI_8to7_01_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_01_6 + select value for AOI_8to7_01_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_01_5 + select value for AOI_8to7_01_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_01_4 + select value for AOI_8to7_01_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_01_3 + select value for AOI_8to7_01_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_01_2 + select value for AOI_8to7_01_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_01_1 + select value for AOI_8to7_01_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_01_0 + select value for AOI_8to7_01_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_00_7 + select value for AOI_8to7_00_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_00_6 + select value for AOI_8to7_00_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_00_5 + select value for AOI_8to7_00_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_00_4 + select value for AOI_8to7_00_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_00_3 + select value for AOI_8to7_00_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_00_2 + select value for AOI_8to7_00_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_00_1 + select value for AOI_8to7_00_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_00_0 + select value for AOI_8to7_00_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_4_AOI_8TO7_02_03 + CHN4 AOI_16to8_02_03 OR logic cfg + 0x1e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_03_7 + select value for AOI_8to7_03_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_03_6 + select value for AOI_8to7_03_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_03_5 + select value for AOI_8to7_03_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_03_4 + select value for AOI_8to7_03_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_03_3 + select value for AOI_8to7_03_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_03_2 + select value for AOI_8to7_03_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_03_1 + select value for AOI_8to7_03_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_03_0 + select value for AOI_8to7_03_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_02_7 + select value for AOI_8to7_02_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_02_6 + select value for AOI_8to7_02_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_02_5 + select value for AOI_8to7_02_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_02_4 + select value for AOI_8to7_02_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_02_3 + select value for AOI_8to7_02_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_02_2 + select value for AOI_8to7_02_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_02_1 + select value for AOI_8to7_02_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_02_0 + select value for AOI_8to7_02_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_4_AOI_8TO7_04_05 + CHN4 AOI_16to8_04_05 OR logic cfg + 0x1e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_05_7 + select value for AOI_8to7_05_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_05_6 + select value for AOI_8to7_05_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_05_5 + select value for AOI_8to7_05_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_05_4 + select value for AOI_8to7_05_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_05_3 + select value for AOI_8to7_05_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_05_2 + select value for AOI_8to7_05_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_05_1 + select value for AOI_8to7_05_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_05_0 + select value for AOI_8to7_05_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_04_7 + select value for AOI_8to7_04_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_04_6 + select value for AOI_8to7_04_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_04_5 + select value for AOI_8to7_04_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_04_4 + select value for AOI_8to7_04_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_04_3 + select value for AOI_8to7_04_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_04_2 + select value for AOI_8to7_04_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_04_1 + select value for AOI_8to7_04_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_04_0 + select value for AOI_8to7_04_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_4_AOI_8TO7_06 + CHN4 AOI_16to8_06 OR logic cfg + 0x1ec + 32 + 0x00000000 + 0x0000FFFF + + + AOI_8TO7_06_7 + select value for AOI_8to7_06_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_06_6 + select value for AOI_8to7_06_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_06_5 + select value for AOI_8to7_06_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_06_4 + select value for AOI_8to7_06_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_06_3 + select value for AOI_8to7_06_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_06_2 + select value for AOI_8to7_06_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_06_1 + select value for AOI_8to7_06_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_06_0 + select value for AOI_8to7_06_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_4_FILTER_2ND_SECOND_FILTER_0 + CHN4 SECOND_FILTER cfg + 0x1f0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_2ND_SECOND_FILTER_1 + CHN4 SECOND_FILTER cfg + 0x1f4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_2ND_SECOND_FILTER_2 + CHN4 SECOND_FILTER cfg + 0x1f8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_2ND_SECOND_FILTER_3 + CHN4 SECOND_FILTER cfg + 0x1fc + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_2ND_SECOND_FILTER_4 + CHN4 SECOND_FILTER cfg + 0x200 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_2ND_SECOND_FILTER_5 + CHN4 SECOND_FILTER cfg + 0x204 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_2ND_SECOND_FILTER_6 + CHN4 SECOND_FILTER cfg + 0x208 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_2ND_SECOND_FILTER_7 + CHN4 SECOND_FILTER cfg + 0x20c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_3RD_THIRD_FILTER_0 + CHN4 THIRD_FILTER cfg + 0x210 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_3RD_THIRD_FILTER_1 + CHN4 THIRD_FILTER cfg + 0x214 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_3RD_THIRD_FILTER_2 + CHN4 THIRD_FILTER cfg + 0x218 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_3RD_THIRD_FILTER_3 + CHN4 THIRD_FILTER cfg + 0x21c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_3RD_THIRD_FILTER_4 + CHN4 THIRD_FILTER cfg + 0x220 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_3RD_THIRD_FILTER_5 + CHN4 THIRD_FILTER cfg + 0x224 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_FILTER_3RD_THIRD_FILTER_6 + CHN4 THIRD_FILTER cfg + 0x228 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_4_CFG_FF + CHN4 cfg ff + 0x22c + 32 + 0x00000000 + 0x0003001F + + + OSC_LOOP_CLAMP_VALUE + osc loop clamp value when osc ring active. +0: clamp 0. +1: clamp 1. + 17 + 1 + read-write + + + DIS_OSC_LOOP_CLAMP + disable osc loop clamp. +0: enable osc loop clamp when osc ring active. +1: disable or clean current osc loop clamp. + 16 + 1 + read-write + + + SEL_ADDER_MINUS + 0: select adder when cfg_adder_minus active. +1: select minus when cfg_adder_minus active. + 4 + 1 + read-write + + + SEL_CLK_SOURCE + cfg_ff clock source. +0: system clock. +1: use 3rd_filter_2 as clock. + 3 + 1 + read-write + + + SEL_CFG_FF_TYPE + cfg_ff type. +0: DFF. +1: 3rd_filter_0. +2: dual-edge DFF. +3: Trigger FF. +4: JK FF. +5. latch. +6: full adder/minus. + 0 + 3 + read-write + + + + + CHN_5_AOI_16TO8_AOI_16TO8_00 + CHN5 AOI_16to8 AND logic cfg + 0x230 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_5_AOI_16TO8_AOI_16TO8_01 + CHN5 AOI_16to8 AND logic cfg + 0x234 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_5_AOI_16TO8_AOI_16TO8_02 + CHN5 AOI_16to8 AND logic cfg + 0x238 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_5_AOI_16TO8_AOI_16TO8_03 + CHN5 AOI_16to8 AND logic cfg + 0x23c + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_5_AOI_16TO8_AOI_16TO8_04 + CHN5 AOI_16to8 AND logic cfg + 0x240 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_5_AOI_16TO8_AOI_16TO8_05 + CHN5 AOI_16to8 AND logic cfg + 0x244 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_5_AOI_16TO8_AOI_16TO8_06 + CHN5 AOI_16to8 AND logic cfg + 0x248 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_5_AOI_16TO8_AOI_16TO8_07 + CHN5 AOI_16to8 AND logic cfg + 0x24c + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_5_AOI_8TO7_00_01 + CHN5 AOI_16to8_00_01 OR logic cfg + 0x250 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_01_7 + select value for AOI_8to7_01_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_01_6 + select value for AOI_8to7_01_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_01_5 + select value for AOI_8to7_01_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_01_4 + select value for AOI_8to7_01_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_01_3 + select value for AOI_8to7_01_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_01_2 + select value for AOI_8to7_01_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_01_1 + select value for AOI_8to7_01_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_01_0 + select value for AOI_8to7_01_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_00_7 + select value for AOI_8to7_00_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_00_6 + select value for AOI_8to7_00_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_00_5 + select value for AOI_8to7_00_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_00_4 + select value for AOI_8to7_00_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_00_3 + select value for AOI_8to7_00_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_00_2 + select value for AOI_8to7_00_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_00_1 + select value for AOI_8to7_00_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_00_0 + select value for AOI_8to7_00_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_5_AOI_8TO7_02_03 + CHN5 AOI_16to8_02_03 OR logic cfg + 0x254 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_03_7 + select value for AOI_8to7_03_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_03_6 + select value for AOI_8to7_03_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_03_5 + select value for AOI_8to7_03_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_03_4 + select value for AOI_8to7_03_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_03_3 + select value for AOI_8to7_03_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_03_2 + select value for AOI_8to7_03_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_03_1 + select value for AOI_8to7_03_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_03_0 + select value for AOI_8to7_03_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_02_7 + select value for AOI_8to7_02_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_02_6 + select value for AOI_8to7_02_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_02_5 + select value for AOI_8to7_02_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_02_4 + select value for AOI_8to7_02_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_02_3 + select value for AOI_8to7_02_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_02_2 + select value for AOI_8to7_02_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_02_1 + select value for AOI_8to7_02_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_02_0 + select value for AOI_8to7_02_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_5_AOI_8TO7_04_05 + CHN5 AOI_16to8_04_05 OR logic cfg + 0x258 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_05_7 + select value for AOI_8to7_05_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_05_6 + select value for AOI_8to7_05_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_05_5 + select value for AOI_8to7_05_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_05_4 + select value for AOI_8to7_05_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_05_3 + select value for AOI_8to7_05_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_05_2 + select value for AOI_8to7_05_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_05_1 + select value for AOI_8to7_05_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_05_0 + select value for AOI_8to7_05_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_04_7 + select value for AOI_8to7_04_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_04_6 + select value for AOI_8to7_04_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_04_5 + select value for AOI_8to7_04_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_04_4 + select value for AOI_8to7_04_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_04_3 + select value for AOI_8to7_04_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_04_2 + select value for AOI_8to7_04_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_04_1 + select value for AOI_8to7_04_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_04_0 + select value for AOI_8to7_04_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_5_AOI_8TO7_06 + CHN5 AOI_16to8_06 OR logic cfg + 0x25c + 32 + 0x00000000 + 0x0000FFFF + + + AOI_8TO7_06_7 + select value for AOI_8to7_06_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_06_6 + select value for AOI_8to7_06_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_06_5 + select value for AOI_8to7_06_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_06_4 + select value for AOI_8to7_06_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_06_3 + select value for AOI_8to7_06_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_06_2 + select value for AOI_8to7_06_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_06_1 + select value for AOI_8to7_06_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_06_0 + select value for AOI_8to7_06_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_5_FILTER_2ND_SECOND_FILTER_0 + CHN5 SECOND_FILTER cfg + 0x260 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_2ND_SECOND_FILTER_1 + CHN5 SECOND_FILTER cfg + 0x264 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_2ND_SECOND_FILTER_2 + CHN5 SECOND_FILTER cfg + 0x268 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_2ND_SECOND_FILTER_3 + CHN5 SECOND_FILTER cfg + 0x26c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_2ND_SECOND_FILTER_4 + CHN5 SECOND_FILTER cfg + 0x270 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_2ND_SECOND_FILTER_5 + CHN5 SECOND_FILTER cfg + 0x274 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_2ND_SECOND_FILTER_6 + CHN5 SECOND_FILTER cfg + 0x278 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_2ND_SECOND_FILTER_7 + CHN5 SECOND_FILTER cfg + 0x27c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_3RD_THIRD_FILTER_0 + CHN5 THIRD_FILTER cfg + 0x280 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_3RD_THIRD_FILTER_1 + CHN5 THIRD_FILTER cfg + 0x284 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_3RD_THIRD_FILTER_2 + CHN5 THIRD_FILTER cfg + 0x288 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_3RD_THIRD_FILTER_3 + CHN5 THIRD_FILTER cfg + 0x28c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_3RD_THIRD_FILTER_4 + CHN5 THIRD_FILTER cfg + 0x290 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_3RD_THIRD_FILTER_5 + CHN5 THIRD_FILTER cfg + 0x294 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_FILTER_3RD_THIRD_FILTER_6 + CHN5 THIRD_FILTER cfg + 0x298 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_5_CFG_FF + CHN5 cfg ff + 0x29c + 32 + 0x00000000 + 0x0003001F + + + OSC_LOOP_CLAMP_VALUE + osc loop clamp value when osc ring active. +0: clamp 0. +1: clamp 1. + 17 + 1 + read-write + + + DIS_OSC_LOOP_CLAMP + disable osc loop clamp. +0: enable osc loop clamp when osc ring active. +1: disable or clean current osc loop clamp. + 16 + 1 + read-write + + + SEL_ADDER_MINUS + 0: select adder when cfg_adder_minus active. +1: select minus when cfg_adder_minus active. + 4 + 1 + read-write + + + SEL_CLK_SOURCE + cfg_ff clock source. +0: system clock. +1: use 3rd_filter_2 as clock. + 3 + 1 + read-write + + + SEL_CFG_FF_TYPE + cfg_ff type. +0: DFF. +1: 3rd_filter_0. +2: dual-edge DFF. +3: Trigger FF. +4: JK FF. +5. latch. +6: full adder/minus. + 0 + 3 + read-write + + + + + CHN_6_AOI_16TO8_AOI_16TO8_00 + CHN6 AOI_16to8 AND logic cfg + 0x2a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_6_AOI_16TO8_AOI_16TO8_01 + CHN6 AOI_16to8 AND logic cfg + 0x2a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_6_AOI_16TO8_AOI_16TO8_02 + CHN6 AOI_16to8 AND logic cfg + 0x2a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_6_AOI_16TO8_AOI_16TO8_03 + CHN6 AOI_16to8 AND logic cfg + 0x2ac + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_6_AOI_16TO8_AOI_16TO8_04 + CHN6 AOI_16to8 AND logic cfg + 0x2b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_6_AOI_16TO8_AOI_16TO8_05 + CHN6 AOI_16to8 AND logic cfg + 0x2b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_6_AOI_16TO8_AOI_16TO8_06 + CHN6 AOI_16to8 AND logic cfg + 0x2b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_6_AOI_16TO8_AOI_16TO8_07 + CHN6 AOI_16to8 AND logic cfg + 0x2bc + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_6_AOI_8TO7_00_01 + CHN6 AOI_16to8_00_01 OR logic cfg + 0x2c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_01_7 + select value for AOI_8to7_01_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_01_6 + select value for AOI_8to7_01_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_01_5 + select value for AOI_8to7_01_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_01_4 + select value for AOI_8to7_01_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_01_3 + select value for AOI_8to7_01_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_01_2 + select value for AOI_8to7_01_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_01_1 + select value for AOI_8to7_01_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_01_0 + select value for AOI_8to7_01_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_00_7 + select value for AOI_8to7_00_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_00_6 + select value for AOI_8to7_00_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_00_5 + select value for AOI_8to7_00_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_00_4 + select value for AOI_8to7_00_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_00_3 + select value for AOI_8to7_00_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_00_2 + select value for AOI_8to7_00_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_00_1 + select value for AOI_8to7_00_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_00_0 + select value for AOI_8to7_00_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_6_AOI_8TO7_02_03 + CHN6 AOI_16to8_02_03 OR logic cfg + 0x2c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_03_7 + select value for AOI_8to7_03_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_03_6 + select value for AOI_8to7_03_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_03_5 + select value for AOI_8to7_03_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_03_4 + select value for AOI_8to7_03_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_03_3 + select value for AOI_8to7_03_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_03_2 + select value for AOI_8to7_03_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_03_1 + select value for AOI_8to7_03_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_03_0 + select value for AOI_8to7_03_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_02_7 + select value for AOI_8to7_02_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_02_6 + select value for AOI_8to7_02_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_02_5 + select value for AOI_8to7_02_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_02_4 + select value for AOI_8to7_02_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_02_3 + select value for AOI_8to7_02_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_02_2 + select value for AOI_8to7_02_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_02_1 + select value for AOI_8to7_02_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_02_0 + select value for AOI_8to7_02_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_6_AOI_8TO7_04_05 + CHN6 AOI_16to8_04_05 OR logic cfg + 0x2c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_05_7 + select value for AOI_8to7_05_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_05_6 + select value for AOI_8to7_05_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_05_5 + select value for AOI_8to7_05_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_05_4 + select value for AOI_8to7_05_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_05_3 + select value for AOI_8to7_05_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_05_2 + select value for AOI_8to7_05_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_05_1 + select value for AOI_8to7_05_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_05_0 + select value for AOI_8to7_05_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_04_7 + select value for AOI_8to7_04_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_04_6 + select value for AOI_8to7_04_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_04_5 + select value for AOI_8to7_04_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_04_4 + select value for AOI_8to7_04_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_04_3 + select value for AOI_8to7_04_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_04_2 + select value for AOI_8to7_04_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_04_1 + select value for AOI_8to7_04_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_04_0 + select value for AOI_8to7_04_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_6_AOI_8TO7_06 + CHN6 AOI_16to8_06 OR logic cfg + 0x2cc + 32 + 0x00000000 + 0x0000FFFF + + + AOI_8TO7_06_7 + select value for AOI_8to7_06_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_06_6 + select value for AOI_8to7_06_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_06_5 + select value for AOI_8to7_06_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_06_4 + select value for AOI_8to7_06_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_06_3 + select value for AOI_8to7_06_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_06_2 + select value for AOI_8to7_06_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_06_1 + select value for AOI_8to7_06_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_06_0 + select value for AOI_8to7_06_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_6_FILTER_2ND_SECOND_FILTER_0 + CHN6 SECOND_FILTER cfg + 0x2d0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_2ND_SECOND_FILTER_1 + CHN6 SECOND_FILTER cfg + 0x2d4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_2ND_SECOND_FILTER_2 + CHN6 SECOND_FILTER cfg + 0x2d8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_2ND_SECOND_FILTER_3 + CHN6 SECOND_FILTER cfg + 0x2dc + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_2ND_SECOND_FILTER_4 + CHN6 SECOND_FILTER cfg + 0x2e0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_2ND_SECOND_FILTER_5 + CHN6 SECOND_FILTER cfg + 0x2e4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_2ND_SECOND_FILTER_6 + CHN6 SECOND_FILTER cfg + 0x2e8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_2ND_SECOND_FILTER_7 + CHN6 SECOND_FILTER cfg + 0x2ec + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_3RD_THIRD_FILTER_0 + CHN6 THIRD_FILTER cfg + 0x2f0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_3RD_THIRD_FILTER_1 + CHN6 THIRD_FILTER cfg + 0x2f4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_3RD_THIRD_FILTER_2 + CHN6 THIRD_FILTER cfg + 0x2f8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_3RD_THIRD_FILTER_3 + CHN6 THIRD_FILTER cfg + 0x2fc + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_3RD_THIRD_FILTER_4 + CHN6 THIRD_FILTER cfg + 0x300 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_3RD_THIRD_FILTER_5 + CHN6 THIRD_FILTER cfg + 0x304 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_FILTER_3RD_THIRD_FILTER_6 + CHN6 THIRD_FILTER cfg + 0x308 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_6_CFG_FF + CHN6 cfg ff + 0x30c + 32 + 0x00000000 + 0x0003001F + + + OSC_LOOP_CLAMP_VALUE + osc loop clamp value when osc ring active. +0: clamp 0. +1: clamp 1. + 17 + 1 + read-write + + + DIS_OSC_LOOP_CLAMP + disable osc loop clamp. +0: enable osc loop clamp when osc ring active. +1: disable or clean current osc loop clamp. + 16 + 1 + read-write + + + SEL_ADDER_MINUS + 0: select adder when cfg_adder_minus active. +1: select minus when cfg_adder_minus active. + 4 + 1 + read-write + + + SEL_CLK_SOURCE + cfg_ff clock source. +0: system clock. +1: use 3rd_filter_2 as clock. + 3 + 1 + read-write + + + SEL_CFG_FF_TYPE + cfg_ff type. +0: DFF. +1: 3rd_filter_0. +2: dual-edge DFF. +3: Trigger FF. +4: JK FF. +5. latch. +6: full adder/minus. + 0 + 3 + read-write + + + + + CHN_7_AOI_16TO8_AOI_16TO8_00 + CHN7 AOI_16to8 AND logic cfg + 0x310 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_7_AOI_16TO8_AOI_16TO8_01 + CHN7 AOI_16to8 AND logic cfg + 0x314 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_7_AOI_16TO8_AOI_16TO8_02 + CHN7 AOI_16to8 AND logic cfg + 0x318 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_7_AOI_16TO8_AOI_16TO8_03 + CHN7 AOI_16to8 AND logic cfg + 0x31c + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_7_AOI_16TO8_AOI_16TO8_04 + CHN7 AOI_16to8 AND logic cfg + 0x320 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_7_AOI_16TO8_AOI_16TO8_05 + CHN7 AOI_16to8 AND logic cfg + 0x324 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_7_AOI_16TO8_AOI_16TO8_06 + CHN7 AOI_16to8 AND logic cfg + 0x328 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_7_AOI_16TO8_AOI_16TO8_07 + CHN7 AOI_16to8 AND logic cfg + 0x32c + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_16TO8_15 + select value for AOI_16to8_15. +0: 0. +1: 1st_filter_out[15]. +2: ~1st_filter_out[15]. +3: 1 + 30 + 2 + read-write + + + AOI_16TO8_14 + select value for AOI_16to8_14. +0: 0. +1: 1st_filter_out[14]. +2: ~1st_filter_out[14]. +3: 1 + 28 + 2 + read-write + + + AOI_16TO8_13 + select value for AOI_16to8_13. +0: 0. +1: 1st_filter_out[13]. +2: ~1st_filter_out[13]. +3: 1 + 26 + 2 + read-write + + + AOI_16TO8_12 + select value for AOI_16to8_12. +0: 0. +1: 1st_filter_out[12]. +2: ~1st_filter_out[12]. +3: 1 + 24 + 2 + read-write + + + AOI_16TO8_11 + select value for AOI_16to8_11. +0: 0. +1: 1st_filter_out[11]. +2: ~1st_filter_out[11]. +3: 1 + 22 + 2 + read-write + + + AOI_16TO8_10 + select value for AOI_16to8_10. +0: 0. +1: 1st_filter_out[10]. +2: ~1st_filter_out[10]. +3: 1 + 20 + 2 + read-write + + + AOI_16TO8_9 + select value for AOI_16to8_9. +0: 0. +1: 1st_filter_out[9]. +2: ~1st_filter_out[9]. +3: 1 + 18 + 2 + read-write + + + AOI_16TO8_8 + select value for AOI_16to8_8. +0: 0. +1: 1st_filter_out[8]. +2: ~1st_filter_out[8]. +3: 1 + 16 + 2 + read-write + + + AOI_16TO8_7 + select value for AOI_16to8_7. +0: 0. +1: 1st_filter_out[7]. +2: ~1st_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_16TO8_6 + select value for AOI_16to8_6. +0: 0. +1: 1st_filter_out[6]. +2: ~1st_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_16TO8_5 + select value for AOI_16to8_5. +0: 0. +1: 1st_filter_out[5]. +2: ~1st_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_16TO8_4 + select value for AOI_16to8_4. +0: 0. +1: 1st_filter_out[4]. +2: ~1st_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_16TO8_3 + select value for AOI_16to8_3. +0: 0. +1: 1st_filter_out[3]. +2: ~1st_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_16TO8_2 + select value for AOI_16to8_2. +0: 0. +1: 1st_filter_out[2]. +2: ~1st_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_16TO8_1 + select value for AOI_16to8_1. +0: 0. +1: 1st_filter_out[1]. +2: ~1st_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_16TO8_0 + select value for AOI_16to8_0. +0: 0. +1: 1st_filter_out[0]. +2: ~1st_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_7_AOI_8TO7_00_01 + CHN7 AOI_16to8_00_01 OR logic cfg + 0x330 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_01_7 + select value for AOI_8to7_01_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_01_6 + select value for AOI_8to7_01_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_01_5 + select value for AOI_8to7_01_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_01_4 + select value for AOI_8to7_01_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_01_3 + select value for AOI_8to7_01_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_01_2 + select value for AOI_8to7_01_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_01_1 + select value for AOI_8to7_01_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_01_0 + select value for AOI_8to7_01_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_00_7 + select value for AOI_8to7_00_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_00_6 + select value for AOI_8to7_00_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_00_5 + select value for AOI_8to7_00_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_00_4 + select value for AOI_8to7_00_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_00_3 + select value for AOI_8to7_00_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_00_2 + select value for AOI_8to7_00_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_00_1 + select value for AOI_8to7_00_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_00_0 + select value for AOI_8to7_00_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_7_AOI_8TO7_02_03 + CHN7 AOI_16to8_02_03 OR logic cfg + 0x334 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_03_7 + select value for AOI_8to7_03_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_03_6 + select value for AOI_8to7_03_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_03_5 + select value for AOI_8to7_03_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_03_4 + select value for AOI_8to7_03_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_03_3 + select value for AOI_8to7_03_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_03_2 + select value for AOI_8to7_03_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_03_1 + select value for AOI_8to7_03_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_03_0 + select value for AOI_8to7_03_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_02_7 + select value for AOI_8to7_02_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_02_6 + select value for AOI_8to7_02_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_02_5 + select value for AOI_8to7_02_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_02_4 + select value for AOI_8to7_02_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_02_3 + select value for AOI_8to7_02_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_02_2 + select value for AOI_8to7_02_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_02_1 + select value for AOI_8to7_02_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_02_0 + select value for AOI_8to7_02_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_7_AOI_8TO7_04_05 + CHN7 AOI_16to8_04_05 OR logic cfg + 0x338 + 32 + 0x00000000 + 0xFFFFFFFF + + + AOI_8TO7_05_7 + select value for AOI_8to7_05_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 30 + 2 + read-write + + + AOI_8TO7_05_6 + select value for AOI_8to7_05_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 28 + 2 + read-write + + + AOI_8TO7_05_5 + select value for AOI_8to7_05_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 26 + 2 + read-write + + + AOI_8TO7_05_4 + select value for AOI_8to7_05_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 24 + 2 + read-write + + + AOI_8TO7_05_3 + select value for AOI_8to7_05_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 22 + 2 + read-write + + + AOI_8TO7_05_2 + select value for AOI_8to7_05_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 20 + 2 + read-write + + + AOI_8TO7_05_1 + select value for AOI_8to7_05_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 18 + 2 + read-write + + + AOI_8TO7_05_0 + select value for AOI_8to7_05_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 16 + 2 + read-write + + + AOI_8TO7_04_7 + select value for AOI_8to7_04_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_04_6 + select value for AOI_8to7_04_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_04_5 + select value for AOI_8to7_04_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_04_4 + select value for AOI_8to7_04_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_04_3 + select value for AOI_8to7_04_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_04_2 + select value for AOI_8to7_04_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_04_1 + select value for AOI_8to7_04_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_04_0 + select value for AOI_8to7_04_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_7_AOI_8TO7_06 + CHN7 AOI_16to8_06 OR logic cfg + 0x33c + 32 + 0x00000000 + 0x0000FFFF + + + AOI_8TO7_06_7 + select value for AOI_8to7_06_7. +0: 0. +1: 2nd_filter_out[7]. +2: ~2nd_filter_out[7]. +3: 1 + 14 + 2 + read-write + + + AOI_8TO7_06_6 + select value for AOI_8to7_06_6. +0: 0. +1: 2nd_filter_out[6]. +2: ~2nd_filter_out[6]. +3: 1 + 12 + 2 + read-write + + + AOI_8TO7_06_5 + select value for AOI_8to7_06_5. +0: 0. +1: 2nd_filter_out[5]. +2: ~2nd_filter_out[5]. +3: 1 + 10 + 2 + read-write + + + AOI_8TO7_06_4 + select value for AOI_8to7_06_4. +0: 0. +1: 2nd_filter_out[4]. +2: ~2nd_filter_out[4]. +3: 1 + 8 + 2 + read-write + + + AOI_8TO7_06_3 + select value for AOI_8to7_06_3. +0: 0. +1: 2nd_filter_out[3]. +2: ~2nd_filter_out[3]. +3: 1 + 6 + 2 + read-write + + + AOI_8TO7_06_2 + select value for AOI_8to7_06_2. +0: 0. +1: 2nd_filter_out[2]. +2: ~2nd_filter_out[2]. +3: 1 + 4 + 2 + read-write + + + AOI_8TO7_06_1 + select value for AOI_8to7_06_1. +0: 0. +1: 2nd_filter_out[1]. +2: ~2nd_filter_out[1]. +3: 1 + 2 + 2 + read-write + + + AOI_8TO7_06_0 + select value for AOI_8to7_06_0. +0: 0. +1: 2nd_filter_out[0]. +2: ~2nd_filter_out[0]. +3: 1 + 0 + 2 + read-write + + + + + CHN_7_FILTER_2ND_SECOND_FILTER_0 + CHN7 SECOND_FILTER cfg + 0x340 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_2ND_SECOND_FILTER_1 + CHN7 SECOND_FILTER cfg + 0x344 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_2ND_SECOND_FILTER_2 + CHN7 SECOND_FILTER cfg + 0x348 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_2ND_SECOND_FILTER_3 + CHN7 SECOND_FILTER cfg + 0x34c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_2ND_SECOND_FILTER_4 + CHN7 SECOND_FILTER cfg + 0x350 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_2ND_SECOND_FILTER_5 + CHN7 SECOND_FILTER cfg + 0x354 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_2ND_SECOND_FILTER_6 + CHN7 SECOND_FILTER cfg + 0x358 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_2ND_SECOND_FILTER_7 + CHN7 SECOND_FILTER cfg + 0x35c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_3RD_THIRD_FILTER_0 + CHN7 THIRD_FILTER cfg + 0x360 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_3RD_THIRD_FILTER_1 + CHN7 THIRD_FILTER cfg + 0x364 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_3RD_THIRD_FILTER_2 + CHN7 THIRD_FILTER cfg + 0x368 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_3RD_THIRD_FILTER_3 + CHN7 THIRD_FILTER cfg + 0x36c + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_3RD_THIRD_FILTER_4 + CHN7 THIRD_FILTER cfg + 0x370 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_3RD_THIRD_FILTER_5 + CHN7 THIRD_FILTER cfg + 0x374 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_FILTER_3RD_THIRD_FILTER_6 + CHN7 THIRD_FILTER cfg + 0x378 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_7_CFG_FF + CHN7 cfg ff + 0x37c + 32 + 0x00000000 + 0x0003001F + + + OSC_LOOP_CLAMP_VALUE + osc loop clamp value when osc ring active. +0: clamp 0. +1: clamp 1. + 17 + 1 + read-write + + + DIS_OSC_LOOP_CLAMP + disable osc loop clamp. +0: enable osc loop clamp when osc ring active. +1: disable or clean current osc loop clamp. + 16 + 1 + read-write + + + SEL_ADDER_MINUS + 0: select adder when cfg_adder_minus active. +1: select minus when cfg_adder_minus active. + 4 + 1 + read-write + + + SEL_CLK_SOURCE + cfg_ff clock source. +0: system clock. +1: use 3rd_filter_2 as clock. + 3 + 1 + read-write + + + SEL_CFG_FF_TYPE + cfg_ff type. +0: DFF. +1: 3rd_filter_0. +2: dual-edge DFF. +3: Trigger FF. +4: JK FF. +5. latch. +6: full adder/minus. + 0 + 3 + read-write + + + + + FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_0 + FRIST_FILTER_PLA_IN setting + 0x3c0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_1 + FRIST_FILTER_PLA_IN setting + 0x3c4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_2 + FRIST_FILTER_PLA_IN setting + 0x3c8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_3 + FRIST_FILTER_PLA_IN setting + 0x3cc + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_4 + FRIST_FILTER_PLA_IN setting + 0x3d0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_5 + FRIST_FILTER_PLA_IN setting + 0x3d4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_6 + FRIST_FILTER_PLA_IN setting + 0x3d8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_7 + FRIST_FILTER_PLA_IN setting + 0x3dc + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_IN_0 + FRIST_FILTER_PLA_OUT setting + 0x3e0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_0 + FRIST_FILTER_PLA_OUT setting + 0x3e0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_1 + FRIST_FILTER_PLA_OUT setting + 0x3e4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_2 + FRIST_FILTER_PLA_OUT setting + 0x3e8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_3 + FRIST_FILTER_PLA_OUT setting + 0x3ec + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_4 + FRIST_FILTER_PLA_OUT setting + 0x3f0 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_5 + FRIST_FILTER_PLA_OUT setting + 0x3f4 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_6 + FRIST_FILTER_PLA_OUT setting + 0x3f8 + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_7 + FRIST_FILTER_PLA_OUT setting + 0x3fc + 32 + 0x00000000 + 0xFFFF71FF + + + FILTER_EXT_COUNTER + filter_ext counter value, cycles for filter or extent by system clock。 +0：0*apb_clk_period +1：1*apb_clk_period +2: 2*apb_clk_period +… +65535: 65535*apb_clk_period + 16 + 16 + read-write + + + FILTER_EXT_TYPE + filter extend type. +0-3：nothing to do. +4： input high level extend. +5： input low level extend. +6： output extend. +7： input pulse extend. + 12 + 3 + read-write + + + FILTER_EXT_ENABLE + filter extend enable. +0. bypass filter extend. all setting in bit31:12 are inactive +1. enable filter extend, all setting in bit31:12 are active. + 8 + 1 + read-write + + + FILTER_SYNC_LEVEL + synchroniser level. +0: 2 level sync. +1: 3 level sync + 7 + 1 + read-write + + + POSE_EDGE_DECT_ENABLE + pose edge detector enable. +0: disable. +1: enable. + 6 + 1 + read-write + + + NEGE_EDGE_DECT_ENABLE + nege edge detector enable. +0: disable. +1: enable. + 5 + 1 + read-write + + + EDGE_DECT_ENABLE + edge detector enable. +0: disable. bit6/bit5 setting inactive. +1: enable. bit6/bit5 setting active. + 4 + 1 + read-write + + + FILTER_REVERSE + reverse sync and edge detector filter's output. +0: not reverse. +1: reverse. + 3 + 1 + read-write + + + SOFTWARE_INJECT + software inject value for sync and edge detector filter. +0: inject low level. +1: inject high level. +2: not inject. +3. inject high level. + 1 + 2 + read-write + + + SYNC_EDGE_FILTER_ENABLE + sync and edge detector filter. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + CHN_CFG_ACTIVE_CFG_ACTIVE_CHN0 + CHN cfg active + 0x400 + 32 + 0x00000000 + 0x0000FFFF + + + CFG_ACTIVE + write 0xF00D to enable all setting. Otherwire, all setting inactive. + 0 + 16 + read-write + + + + + CHN_CFG_ACTIVE_CFG_ACTIVE_CHN1 + CHN cfg active + 0x404 + 32 + 0x00000000 + 0x0000FFFF + + + CFG_ACTIVE + write 0xF00D to enable all setting. Otherwire, all setting inactive. + 0 + 16 + read-write + + + + + CHN_CFG_ACTIVE_CFG_ACTIVE_CHN2 + CHN cfg active + 0x408 + 32 + 0x00000000 + 0x0000FFFF + + + CFG_ACTIVE + write 0xF00D to enable all setting. Otherwire, all setting inactive. + 0 + 16 + read-write + + + + + CHN_CFG_ACTIVE_CFG_ACTIVE_CHN3 + CHN cfg active + 0x40c + 32 + 0x00000000 + 0x0000FFFF + + + CFG_ACTIVE + write 0xF00D to enable all setting. Otherwire, all setting inactive. + 0 + 16 + read-write + + + + + CHN_CFG_ACTIVE_CFG_ACTIVE_CHN4 + CHN cfg active + 0x410 + 32 + 0x00000000 + 0x0000FFFF + + + CFG_ACTIVE + write 0xF00D to enable all setting. Otherwire, all setting inactive. + 0 + 16 + read-write + + + + + CHN_CFG_ACTIVE_CFG_ACTIVE_CHN5 + CHN cfg active + 0x414 + 32 + 0x00000000 + 0x0000FFFF + + + CFG_ACTIVE + write 0xF00D to enable all setting. Otherwire, all setting inactive. + 0 + 16 + read-write + + + + + CHN_CFG_ACTIVE_CFG_ACTIVE_CHN6 + CHN cfg active + 0x418 + 32 + 0x00000000 + 0x0000FFFF + + + CFG_ACTIVE + write 0xF00D to enable all setting. Otherwire, all setting inactive. + 0 + 16 + read-write + + + + + CHN_CFG_ACTIVE_CFG_ACTIVE_CHN7 + CHN cfg active + 0x41c + 32 + 0x00000000 + 0x0000FFFF + + + CFG_ACTIVE + write 0xF00D to enable all setting. Otherwire, all setting inactive. + 0 + 16 + read-write + + + + + + + PLA1 + PLA1 + PLA + 0xf021e000 + + + SYNT + SYNT + SYNT + 0xf0240000 + + 0x0 + 0x30 + registers + + + + GCR + Global control register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + CRST + 1- Reset counter + 1 + 1 + read-write + + + CEN + 1- Enable counter + 0 + 1 + read-write + + + + + RLD + Counter reload register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RLD + counter reload value + 0 + 32 + read-write + + + + + CNT + Counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT + counter + 0 + 32 + read-only + + + + + CMP_0 + Comparator + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + CMP_1 + Comparator + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + CMP_2 + Comparator + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + CMP_3 + Comparator + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + + + USB0 + USB0 + USB + 0xf2020000 + + 0x0 + 0x228 + registers + + + + GPTIMER0LD + General Purpose Timer #0 Load Register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller Register + 0x84 + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in n_GPTIMER0LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software; +In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the +counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + GPTIMER1LD + General Purpose Timer #1 Load Register + 0x88 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller Register + 0x8c + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and +automatically reload the counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + SBUSCFG + System Bus Config Register + 0x90 + 32 + 0x00000000 + 0x00000007 + + + AHBBRST + AHBBRST +AHB master interface Burst configuration +These bits control AHB master transfer type sequence (or priority). +NOTE: This register overrides n_BURSTSIZE register when its value is not zero. +000 - Incremental burst of unspecified length only +001 - INCR4 burst, then single transfer +010 - INCR8 burst, INCR4 burst, then single transfer +011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer +100 - Reserved, don't use +101 - INCR4 burst, then incremental burst of unspecified length +110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length +111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0 + 3 + read-write + + + + + USBCMD + USB Command Register + 0x140 + 32 + 0x00080000 + 0x00FFEB7F + + + ITC + ITC +Interrupt Threshold Control -Read/Write. +The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are +shown below. +Value Maximum Interrupt Interval +00000000 - Immediate (no threshold) +00000001 - 1 micro-frame +00000010 - 2 micro-frames +00000100 - 4 micro-frames +00001000 - 8 micro-frames +00010000 - 16 micro-frames +00100000 - 32 micro-frames +01000000 - 64 micro-frames + 16 + 8 + read-write + + + FS_2 + FS_2 +Frame List Size - (Read/Write or Read Only). [host mode only] +This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. +This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. +NOTE: This field is made up from USBCMD bits 15, 3 and 2. +Value Meaning +0b000 - 1024 elements (4096 bytes) Default value +0b001 - 512 elements (2048 bytes) +0b010 - 256 elements (1024 bytes) +0b011 - 128 elements (512 bytes) +0b100 - 64 elements (256 bytes) +0b101 - 32 elements (128 bytes) +0b110 - 16 elements (64 bytes) +0b111 - 8 elements (32 bytes) + 15 + 1 + read-write + + + ATDTW + ATDTW +Add dTD TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's +linked list. This bit is set and cleared by software. +This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD +to a primed endpoint may go unrecognized. + 14 + 1 + read-write + + + SUTW + SUTW +Setup TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. +If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. +This bit would also be cleared by hardware when a hazard detected. + 13 + 1 + read-write + + + ASPE + ASPE +Asynchronous Schedule Park Mode Enable - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. +NOTE: ASPE bit reset value: '0b' for OTG controller . + 11 + 1 + read-write + + + ASP + ASP +Asynchronous Schedule Park Mode Count - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. +It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. +Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. +This field is set to 3h in all controller core. + 8 + 2 + read-write + + + IAA + IAA +Interrupt on Async Advance Doorbell - Read/Write. +This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. +When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. +The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. +This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + 6 + 1 + read-write + + + ASE + ASE +Asynchronous Schedule Enable - Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Asynchronous Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Asynchronous Schedule. +1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 5 + 1 + read-write + + + PSE + PSE +Periodic Schedule Enable- Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Periodic Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Periodic Schedule +1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + 4 + 1 + read-write + + + FS_1 + FS_1 +See description at bit 15 + 2 + 2 + read-write + + + RST + RST +Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. +Host operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. +Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. +Attempting to reset an actively running host controller will result in undefined behavior. +Device operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + 1 + 1 + read-write + + + RS + RS +Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. +Host operation mode: +When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. +Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). +Device operation mode: +Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. +This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + 0 + 1 + read-write + + + + + USBSTS + USB Status Register + 0x144 + 32 + 0x00000000 + 0x030DF1FF + + + TI1 + TI1 +General Purpose Timer Interrupt 1(GPTINT1)--R/WC. +This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this +bit will clear it. + 25 + 1 + read-write + + + TI0 + TI0 +General Purpose Timer Interrupt 0(GPTINT0)--R/WC. +This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this +bit clears it. + 24 + 1 + read-write + + + UPI + USB Host Periodic Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. +This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero. + 19 + 1 + read-write + + + UAI + USB Host Asynchronous Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. +This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero + 18 + 1 + read-write + + + NAKI + NAKI +NAK Interrupt Bit--RO. +This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and +corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware +when all Enabled TX/RX Endpoint NAK bits are cleared. + 16 + 1 + read-only + + + AS + AS +Asynchronous Schedule Status - Read Only. +This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. +When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 15 + 1 + read-only + + + PS + PS +Periodic Schedule Status - Read Only. +This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 14 + 1 + read-only + + + RCL + RCL +Reclamation - Read Only. +This is a read-only status bit used to detect an empty asynchronous schedule. +Only used in the host operation mode. + 13 + 1 + read-only + + + HCH + HCH +HCHaIted - Read Only. +This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). +Only used in the host operation mode. +Default value is '0b' for OTG core . +This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE +register. +NOTE: HCH bit reset value: '0b' for OTG controller core . + 12 + 1 + read-only + + + SLI + SLI +DCSuspend - R/WC. +When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. +Only used in device operation mode. + 8 + 1 + read-write + + + SRI + SRI +SOF Received - R/WC. +When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. +Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. +Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. +In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. +Software writes a 1 to this bit to clear it. + 7 + 1 + read-write + + + URI + URI +USB Reset Received - R/WC. +When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. +Software can write a 1 to this bit to clear the USB Reset Received status bit. +Only used in device operation mode. + 6 + 1 + read-write + + + AAI + AAI +Interrupt on Async Advance - R/WC. +System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. +Only used in host operation mode. + 5 + 1 + read-write + + + SEI + System Error – RWC. Default = 0b. +In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + 4 + 1 + read-write + + + FRI + FRI +Frame List Rollover - R/WC. +The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to +zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the +frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the +Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host +Controller sets this bit to a one every time FHINDEX [12] toggles. +Only used in host operation mode. + 3 + 1 + read-write + + + PCI + PCI +Port Change Detect - R/WC. +The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. +The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + 2 + 1 + read-write + + + UEI + UEI +USB Error Interrupt (USBERRINT) - R/WC. +When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + 1 + 1 + read-write + + + UI + UI +USB Interrupt (USBINT) - R/WC. +This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB +transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. +This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when +the actual number of bytes received was less than the expected number of bytes. + 0 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + 0x00000000 + 0x030D01FF + + + TIE1 + TIE1 +General Purpose Timer #1 Interrupt Enable +When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + 25 + 1 + read-write + + + TIE0 + TIE0 +General Purpose Timer #0 Interrupt Enable +When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + 24 + 1 + read-write + + + UPIE + UPIE +USB Host Periodic Interrupt Enable +When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 19 + 1 + read-write + + + UAIE + UAIE +USB Host Asynchronous Interrupt Enable +When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 18 + 1 + read-write + + + NAKE + NAKE +NAK Interrupt Enable +When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + 16 + 1 + read-only + + + SLE + SLE +Sleep Interrupt Enable +When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 8 + 1 + read-write + + + SRE + SRE +SOF Received Interrupt Enable +When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + 7 + 1 + read-write + + + URE + URE +USB Reset Interrupt Enable +When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 6 + 1 + read-write + + + AAE + AAE +Async Advance Interrupt Enable +When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 5 + 1 + read-write + + + SEE + SEE +System Error Interrupt Enable +When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 4 + 1 + read-write + + + FRE + FRE +Frame List Rollover Interrupt Enable +When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 3 + 1 + read-write + + + PCE + PCE +Port Change Detect Interrupt Enable +When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + 2 + 1 + read-write + + + UEE + UEE +USB Error Interrupt Enable +When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + 1 + 1 + read-write + + + UE + UE +USB Interrupt Enable +When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + 0 + 1 + read-write + + + + + FRINDEX + USB Frame Index Register + 0x14c + 32 + 0x00000000 + 0x00003FFF + + + FRINDEX + FRINDEX +Frame Index. +The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. +The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. +USBCMD [Frame List Size] Number Elements N +In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. +In either mode bits 2:0 indicate the current microframe. +The bit field values description below is represented as (Frame List Size) Number Elements N. +00000000000000 - (1024) 12 +00000000000001 - (512) 11 +00000000000010 - (256) 10 +00000000000011 - (128) 9 +00000000000100 - (64) 8 +00000000000101 - (32) 7 +00000000000110 - (16) 6 +00000000000111 - (8) 5 + 0 + 14 + read-write + + + + + DEVICEADDR + Device Address Register + 0x154 + 32 + 0x00000000 + 0xFF000000 + + + USBADR + USBADR +Device Address. +These bits correspond to the USB device address + 25 + 7 + read-write + + + USBADRA + USBADRA +Device Address Advance. Default=0. +When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. +After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. +Hardware will automatically clear this bit on the following conditions: +1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). +2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). +3) Device Reset occurs (USBADR is reset to 0). +NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. +If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + 24 + 1 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address Register + 0x154 + 32 + 0x00000000 + 0xFFFFF000 + + + BASEADR + BASEADR +Base Address (Low). +These bits correspond to memory address signals [31:12], respectively. +Only used by the host controller. + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address Register + 0x158 + 32 + 0x00000000 + 0xFFFFFFE0 + + + ASYBASE + ASYBASE +Link Pointer Low (LPL). +These bits correspond to memory address signals [31:5], respectively. This field may only reference a +Queue Head (QH). +Only used by the host controller. + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address Register + 0x158 + 32 + 0x00000000 + 0xFFFFF800 + + + EPBASE + EPBASE +Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size Register + 0x160 + 32 + 0x00000000 + 0x0000FFFF + + + TXPBURST + TXPBURST +Programmable TX Burst Size. +Default value is determined by TXBURST bits in n_HWTXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from system +memory to the USB bus. + 8 + 8 + read-write + + + RXPBURST + RXPBURST +Programmable RX Burst Size. +Default value is determined by TXBURST bits in n_HWRXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from the +USB bus to system memory. + 0 + 8 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning Register + 0x164 + 32 + 0x00000000 + 0x003F1F7F + + + TXFIFOTHRES + TXFIFOTHRES +FIFO Burst Threshold. (Read/Write) +This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. +The minimum value is 2 and this value should be a low as possible to maximize USB performance. +A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. +This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + 16 + 6 + read-write + + + TXSCHHEALTH + TXSCHHEALTH +Scheduler Health Counter. (Read/Write To Clear) +Table continues on the next page +This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. + 8 + 5 + read-write + + + TXSCHOH + TXSCHOH +Scheduler Overhead. (Read/Write) [Default = 0] +This register adds an additional fixed offset to the schedule time estimator described above as Tff. +As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. +Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. +The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. +The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. +Default value is '08h' for OTG controller core . + 0 + 7 + read-write + + + + + ENDPTNAK + Endpoint NAK Register + 0x178 + 32 + 0x00000000 + 0x00FF00FF + + + EPTN + EPTN +TX Endpoint NAK - R/WC. +Each TX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received IN token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 8 + read-write + + + EPRN + EPRN +RX Endpoint NAK - R/WC. +Each RX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 8 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable Register + 0x17c + 32 + 0x00000000 + 0x00FF00FF + + + EPTNE + EPTNE +TX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the +corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 8 + read-write + + + EPRNE + EPRNE +RX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the +corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 8 + read-write + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + 0x00000000 + 0x3DFF1FFF + + + STS + STS +Serial Transceiver Select +1 Serial Interface Engine is selected +0 Parallel Interface signals is selected +Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. +When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + 29 + 1 + read-write + + + PTW + PTW +Parallel Transceiver Width +This bit has no effect if serial interface engine is used. +0 - Select the 8-bit UTMI interface [60MHz] +1 - Select the 16-bit UTMI interface [30MHz] + 28 + 1 + read-write + + + PSPD + PSPD +Port Speed - Read Only. +This register field indicates the speed at which the port is operating. +00 - Full Speed +01 - Low Speed +10 - High Speed +11 - Undefined + 26 + 2 + read-only + + + PFSC + PFSC +Port Force Full Speed Connect - Read/Write. Default = 0b. +When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp +sequence that allows the port to identify itself as High Speed. +0 - Normal operation +1 - Forced to full speed + 24 + 1 + read-write + + + PHCD + PHCD +PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. +When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY +clock. +NOTE: The PHY clock cannot be disabled if it is being used as the system clock. +In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD +Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend +will be cleared automatically when the host initials resume. Before forcing a resume from the device, the +device controller driver must clear this bit. +In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put +into suspend mode or when no downstream device is connected. Low power suspend is completely +under the control of software. +0 - Enable PHY clock +1 - Disable PHY clock + 23 + 1 + read-write + + + WKOC + WKOC +Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. +Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. +This field is zero if Port Power(PORTSC1) is zero. + 22 + 1 + read-write + + + WKDC + WKDC +Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables +the port to be sensitive to device disconnects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 21 + 1 + read-write + + + WKCN + WKCN +Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. +Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 20 + 1 + read-write + + + PTC + PTC +Port Test Control - Read/Write. Default = 0000b. +Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. +The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. +NOTE: Low speed operations are not supported as a peripheral device. +Any other value than zero indicates that the port is operating in test mode. +Value Specific Test +0000 - TEST_MODE_DISABLE +0001 - J_STATE +0010 - K_STATE +0011 - SE0 (host) / NAK (device) +0100 - Packet +0101 - FORCE_ENABLE_HS +0110 - FORCE_ENABLE_FS +0111 - FORCE_ENABLE_LS +1000-1111 - Reserved + 16 + 4 + read-write + + + PP + PP +Port Power (PP)-Read/Write or Read Only. +The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: +PPC +PP Operation +0 +1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. +1 +1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. +When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). +This feature is implemented in all controller cores (PPC = 1). + 12 + 1 + read-write + + + LS + LS +Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal +lines. +In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because +the port controller state machine and the port routing manage the connection of LS and FS. +In device mode, the use of linestate by the device controller driver is not necessary. +The encoding of the bits are: +Bits [11:10] Meaning +00 - SE0 +01 - K-state +10 - J-state +11 - Undefined + 10 + 2 + read-only + + + HSP + HSP +High-Speed Port - Read Only. Default = 0b. +When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the +host/device connected to the port is not in a high-speed mode. +NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + 9 + 1 + read-only + + + PR + PR +Port Reset - Read/Write or Read Only. Default = 0b. +In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. +When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. +In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + 8 + 1 + read-write + + + SUSP + SUSP +Suspend - Read/Write or Read Only. Default = 0b. +1=Port in suspend state. 0=Port not in suspend state. +In Host Mode: Read/Write. +Port Enabled Bit and Suspend bit of this register define the port states as follows: +Bits [Port Enabled, Suspend] Port State +0x Disable +10 Enable +11 Suspend +When in suspend state, downstream propagation of data is blocked on this port, except for port reset. +The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. +The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. +If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: Read Only. +In device mode this bit is a read only status bit. + 7 + 1 + read-write + + + FPR + FPR +Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. +In Host Mode: +Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. +This bit will automatically change to zero after the resume sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. +Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. +The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. +Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. +This field is zero if Port Power(PORTSC1) is zero in host mode. +This bit is not-EHCI compatible. +In Device mode: +After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. +The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +The bit will be cleared when the device returns to normal operation. + Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + 6 + 1 + read-write + + + OCC + OCC +Over-current Change-R/WC. Default=0. +This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + 5 + 1 + read-write + + + OCA + OCA +Over-current Active-Read Only. Default 0. +This bit will automatically transition from one to zero when the over current condition is removed. +0 - This port does not have an over-current condition. +1 - This port currently has an over-current condition + 4 + 1 + read-only + + + PEC + PEC +Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. +In Host Mode: +For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). +Software clears this by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero. +In Device mode: +The device port is always enabled, so this bit is always '0b'. + 3 + 1 + read-write + + + PE + PE +Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. +In Host Mode: +Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. +Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. +Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. +When the port is disabled, (0b) downstream propagation of data is blocked except for reset. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +The device port is always enabled, so this bit is always '1b'. + 2 + 1 + read-write + + + CSC + CSC +Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. +In Host Mode: +Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. +For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +This bit is undefined in device controller mode. + 1 + 1 + read-write + + + CCS + CCS +Current Connect Status-Read Only. +In Host Mode: +1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended. + 0 + 1 + read-write + + + + + OTGSC + On-The-Go Status & control Register + 0x1a4 + 32 + 0x00000000 + 0x07070723 + + + ASVIE + ASVIE +A Session Valid Interrupt Enable - Read/Write. + 26 + 1 + read-write + + + AVVIE + AVVIE +A VBus Valid Interrupt Enable - Read/Write. +Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + IDIE + IDIE +USB ID Interrupt Enable - Read/Write. +Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + ASVIS + ASVIS +A Session Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the A session valid threshold. +Software must write a one to clear this bit. + 18 + 1 + read-write + + + AVVIS + AVVIS +A VBus Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. +Software must write a one to clear this bit. + 17 + 1 + read-write + + + IDIS + IDIS +USB ID Interrupt Status - Read/Write. +This bit is set when a change on the ID input has been detected. +Software must write a one to clear this bit. + 16 + 1 + read-write + + + ASV + ASV +A Session Valid - Read Only. +Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + AVV + AVV +A VBus Valid - Read Only. +Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ID + ID +USB ID - Read Only. +0 = A device, 1 = B device + 8 + 1 + read-only + + + IDPU + IDPU +ID Pullup - Read/Write +This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input +will not be sampled. + 5 + 1 + read-write + + + VC + VC +VBUS Charge - Read/Write. +Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + 1 + 1 + read-write + + + VD + VD +VBUS_Discharge - Read/Write. +Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + + + USBMODE + USB Device Mode Register + 0x1a8 + 32 + 0x00000000 + 0x0000001F + + + SDIS + SDIS +Stream Disable Mode. (0 - Inactive [default]; 1 - Active) +Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. +This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. +Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. +Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. +NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for +the scheduler when using this feature. +NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + 4 + 1 + read-write + + + SLOM + SLOM +Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . +0 - Setup Lockouts On (default); +1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + 3 + 1 + read-write + + + ES + ES +Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the +host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected +by the value of this bit because they are based upon the 32-bit word. +Bit Meaning +0 - Little Endian [Default] +1 - Big Endian + 2 + 1 + read-write + + + CM + CM +Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only +implementations. For those designs that contain both host & device capability, the controller defaults to +an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ +device controllers, this register can only be written once after reset. If it is necessary to switch modes, +software must reset the controller by writing to the RESET bit in the USBCMD register before +reprogramming this register. +For OTG controller core, reset value is '00b'. +00 - Idle [Default for combination host/device] +01 - Reserved +10 - Device Controller [Default for device only controller] +11 - Host Controller [Default for host only controller] + 0 + 2 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status Register + 0x1ac + 32 + 0x00000000 + 0x000000FF + + + ENDPTSETUPSTAT + ENDPTSETUPSTAT +Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. +Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. +The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. +This register is only used in device mode. + 0 + 8 + read-write + + + + + ENDPTPRIME + Endpoint Prime Register + 0x1b0 + 32 + 0x00000000 + 0x00FF00FF + + + PETB + PETB +Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a +buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. +Software should write a one to the corresponding bit when posting a new transfer descriptor to an +endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor +from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated +endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PETB[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write + + + PERB + PERB +Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. +Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. +Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. +Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PERB[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-write + + + + + ENDPTFLUSH + Endpoint Flush Register + 0x1b4 + 32 + 0x00000000 + 0x00FF00FF + + + FETB + FETB +Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. +If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FETB[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write + + + FERB + FERB +Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FERB[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-write + + + + + ENDPTSTAT + Endpoint Status Register + 0x1b8 + 32 + 0x00000000 + 0x00FF00FF + + + ETBR + ETBR +Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. +This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. +There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. +This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. +Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. +ETBR[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-only + + + ERBR + ERBR +Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective +endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a +corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the +ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB +traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the +USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations +when a dTD is retired, and the dQH is updated. +ERBR[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete Register + 0x1bc + 32 + 0x00000000 + 0x00FF00FF + + + ETCE + ETCE +Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. +If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. +ETCE[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write + + + ERCE + ERCE +Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred +and software should read the corresponding endpoint queue to determine the transfer status. If the +corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the +USBINT . Writing one clears the corresponding bit in this register. +ERCE[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-write + + + + + ENDPTCTRL_ENDPTCTRL0 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1c0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL1 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1c4 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL2 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1c8 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL3 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1cc + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL4 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1d0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL5 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1d4 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL6 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1d8 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL7 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1dc + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + OTG_CTRL0 + No description avaiable + 0x200 + 32 + 0x00000000 + 0x020B3F90 + + + OTG_WKDPDMCHG_EN + No description avaiable + 25 + 1 + read-write + + + AUTORESUME_EN + No description avaiable + 19 + 1 + read-write + + + OTG_VBUS_WAKEUP_EN + No description avaiable + 17 + 1 + read-write + + + OTG_ID_WAKEUP_EN + No description avaiable + 16 + 1 + read-write + + + OTG_VBUS_SOURCE_SEL + No description avaiable + 13 + 1 + read-write + + + OTG_UTMI_SUSPENDM_SW + default 0 for naneng usbphy + 12 + 1 + read-write + + + OTG_UTMI_RESET_SW + default 1 for naneng usbphy + 11 + 1 + read-write + + + OTG_WAKEUP_INT_ENABLE + No description avaiable + 10 + 1 + read-write + + + OTG_POWER_MASK + No description avaiable + 9 + 1 + read-write + + + OTG_OVER_CUR_POL + No description avaiable + 8 + 1 + read-write + + + OTG_OVER_CUR_DIS + No description avaiable + 7 + 1 + read-write + + + SER_MODE_SUSPEND_EN + for naneng usbphy, only switch to serial mode when suspend + 4 + 1 + read-write + + + + + PHY_CTRL0 + No description avaiable + 0x210 + 32 + 0x00000000 + 0x02007007 + + + GPIO_ID_SEL_N + No description avaiable + 25 + 1 + read-write + + + ID_DIG_OVERRIDE + No description avaiable + 14 + 1 + read-write + + + SESS_VALID_OVERRIDE + No description avaiable + 13 + 1 + read-write + + + VBUS_VALID_OVERRIDE + No description avaiable + 12 + 1 + read-write + + + ID_DIG_OVERRIDE_EN + No description avaiable + 2 + 1 + read-write + + + SESS_VALID_OVERRIDE_EN + No description avaiable + 1 + 1 + read-write + + + VBUS_VALID_OVERRIDE_EN + No description avaiable + 0 + 1 + read-write + + + + + PHY_CTRL1 + No description avaiable + 0x214 + 32 + 0x00000000 + 0x00100002 + + + UTMI_CFG_RST_N + No description avaiable + 20 + 1 + read-write + + + UTMI_OTG_SUSPENDM + OTG suspend, not utmi_suspendm + 1 + 1 + read-write + + + + + TOP_STATUS + No description avaiable + 0x220 + 32 + 0x00000000 + 0x80000000 + + + WAKEUP_INT_STATUS + No description avaiable + 31 + 1 + read-write + + + + + PHY_STATUS + No description avaiable + 0x224 + 32 + 0x00000000 + 0x800000F5 + + + UTMI_CLK_VALID + No description avaiable + 31 + 1 + read-write + + + LINE_STATE + No description avaiable + 6 + 2 + read-write + + + HOST_DISCONNECT + No description avaiable + 5 + 1 + read-write + + + ID_DIG + No description avaiable + 4 + 1 + read-write + + + UTMI_SESS_VALID + No description avaiable + 2 + 1 + read-write + + + VBUS_VALID + No description avaiable + 0 + 1 + read-write + + + + + + + GPTMR0 + GPTMR0 + TMR + 0xf3000000 + + 0x0 + 0x20c + registers + + + + CHANNEL_CH0_CR + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFC7FFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + RESERVED + not exist + 18 + 13 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + CHANNEL_CH0_CMP_CMP0 + Comparator register 0 + 0x4 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH0_CMP_CMP1 + Comparator register 1 + 0x8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH0_RLD + Reload register + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CHANNEL_CH0_CNTUPTVAL + Counter update value register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CHANNEL_CH0_CAPPOS + Capture rising edge register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CHANNEL_CH0_CAPNEG + Capture falling edge register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CHANNEL_CH0_CAPPRD + PWM period measure register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH0_CAPDTY + PWM duty cycle measure register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH0_CNT + Counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + CHANNEL_CH1_CR + Control Register + 0x40 + 32 + 0x00000000 + 0xFFFC7FFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + RESERVED + not exist + 18 + 13 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + CHANNEL_CH1_CMP_CMP0 + Comparator register 0 + 0x44 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH1_CMP_CMP1 + Comparator register 1 + 0x48 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH1_RLD + Reload register + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CHANNEL_CH1_CNTUPTVAL + Counter update value register + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CHANNEL_CH1_CAPPOS + Capture rising edge register + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CHANNEL_CH1_CAPNEG + Capture falling edge register + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CHANNEL_CH1_CAPPRD + PWM period measure register + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH1_CAPDTY + PWM duty cycle measure register + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH1_CNT + Counter + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + CHANNEL_CH2_CR + Control Register + 0x80 + 32 + 0x00000000 + 0xFFFC7FFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + RESERVED + not exist + 18 + 13 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + CHANNEL_CH2_CMP_CMP0 + Comparator register 0 + 0x84 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH2_CMP_CMP1 + Comparator register 1 + 0x88 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH2_RLD + Reload register + 0x8c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CHANNEL_CH2_CNTUPTVAL + Counter update value register + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CHANNEL_CH2_CAPPOS + Capture rising edge register + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CHANNEL_CH2_CAPNEG + Capture falling edge register + 0xa4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CHANNEL_CH2_CAPPRD + PWM period measure register + 0xa8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH2_CAPDTY + PWM duty cycle measure register + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH2_CNT + Counter + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + CHANNEL_CH3_CR + Control Register + 0xc0 + 32 + 0x00000000 + 0xFFFC7FFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + RESERVED + not exist + 18 + 13 + read-write + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + CHANNEL_CH3_CMP_CMP0 + Comparator register 0 + 0xc4 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH3_CMP_CMP1 + Comparator register 1 + 0xc8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + CHANNEL_CH3_RLD + Reload register + 0xcc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CHANNEL_CH3_CNTUPTVAL + Counter update value register + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CHANNEL_CH3_CAPPOS + Capture rising edge register + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CHANNEL_CH3_CAPNEG + Capture falling edge register + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CHANNEL_CH3_CAPPRD + PWM period measure register + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH3_CAPDTY + PWM duty cycle measure register + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH3_CNT + Counter + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + SR + Status register + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + CH3CMP1F + channel 3 compare value 1 match flag + 15 + 1 + write-only + + + CH3CMP0F + channel 3 compare value 1 match flag + 14 + 1 + write-only + + + CH3CAPF + channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 13 + 1 + write-only + + + CH3RLDF + channel 3 counter reload flag + 12 + 1 + write-only + + + CH2CMP1F + channel 2 compare value 1 match flag + 11 + 1 + write-only + + + CH2CMP0F + channel 2 compare value 1 match flag + 10 + 1 + write-only + + + CH2CAPF + channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 9 + 1 + write-only + + + CH2RLDF + channel 2 counter reload flag + 8 + 1 + write-only + + + CH1CMP1F + channel 1 compare value 1 match flag + 7 + 1 + write-only + + + CH1CMP0F + channel 1 compare value 1 match flag + 6 + 1 + write-only + + + CH1CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 5 + 1 + write-only + + + CH1RLDF + channel 1 counter reload flag + 4 + 1 + write-only + + + CH0CMP1F + channel 1 compare value 1 match flag + 3 + 1 + write-only + + + CH0CMP0F + channel 1 compare value 1 match flag + 2 + 1 + write-only + + + CH0CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 1 + 1 + write-only + + + CH0RLDF + channel 1 counter reload flag + 0 + 1 + write-only + + + + + IRQEN + Interrupt request enable register + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 + read-write + + + CH3CMP1EN + 1- generate interrupt request when ch3cmp1f flag is set + 15 + 1 + read-write + + + CH3CMP0EN + 1- generate interrupt request when ch3cmp0f flag is set + 14 + 1 + read-write + + + CH3CAPEN + 1- generate interrupt request when ch3capf flag is set + 13 + 1 + read-write + + + CH3RLDEN + 1- generate interrupt request when ch3rldf flag is set + 12 + 1 + read-write + + + CH2CMP1EN + 1- generate interrupt request when ch2cmp1f flag is set + 11 + 1 + read-write + + + CH2CMP0EN + 1- generate interrupt request when ch2cmp0f flag is set + 10 + 1 + read-write + + + CH2CAPEN + 1- generate interrupt request when ch2capf flag is set + 9 + 1 + read-write + + + CH2RLDEN + 1- generate interrupt request when ch2rldf flag is set + 8 + 1 + read-write + + + CH1CMP1EN + 1- generate interrupt request when ch1cmp1f flag is set + 7 + 1 + read-write + + + CH1CMP0EN + 1- generate interrupt request when ch1cmp0f flag is set + 6 + 1 + read-write + + + CH1CAPEN + 1- generate interrupt request when ch1capf flag is set + 5 + 1 + read-write + + + CH1RLDEN + 1- generate interrupt request when ch1rldf flag is set + 4 + 1 + read-write + + + CH0CMP1EN + 1- generate interrupt request when ch0cmp1f flag is set + 3 + 1 + read-write + + + CH0CMP0EN + 1- generate interrupt request when ch0cmp0f flag is set + 2 + 1 + read-write + + + CH0CAPEN + 1- generate interrupt request when ch0capf flag is set + 1 + 1 + read-write + + + CH0RLDEN + 1- generate interrupt request when ch0rldf flag is set + 0 + 1 + read-write + + + + + GCR + Global control register + 0x208 + 32 + 0x00000000 + 0x0000000F + + + SWSYNCT + set this bitfield to trigger software coutner sync event + 0 + 4 + read-write + + + + + + + GPTMR1 + GPTMR1 + TMR + 0xf3004000 + + + GPTMR2 + GPTMR2 + TMR + 0xf3008000 + + + GPTMR3 + GPTMR3 + TMR + 0xf300c000 + + + PTMR + PTMR + TMR + 0xf40e0000 + + + I2C0 + I2C0 + I2C + 0xf3020000 + + 0x0 + 0x34 + registers + + + + CFG + Configuration Register + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 2 + 30 + read-write + + + FIFOSIZE + FIFO Size: +0: 2 bytes +1: 4 bytes +2: 8 bytes +3: 16 bytes + 0 + 2 + read-only + + + + + INTEN + Interrupt Enable Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 10 + 22 + read-write + + + CMPL + Set to enable the Completion Interrupt. +Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. +Slave: interrupts when a transaction addressing the controller is completed. + 9 + 1 + read-write + + + BYTERECV + Set to enable the Byte Receive Interrupt. +Interrupts when a byte of data is received +Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. + 8 + 1 + read-write + + + BYTETRANS + Set to enable the Byte Transmit Interrupt. +Interrupts when a byte of data is transmitted. + 7 + 1 + read-write + + + START + Set to enable the START Condition Interrupt. +Interrupts when a START condition/repeated START condition is detected. + 6 + 1 + read-write + + + STOP + Set to enable the STOP Condition Interrupt +Interrupts when a STOP condition is detected. + 5 + 1 + read-write + + + ARBLOSE + Set to enable the Arbitration Lose Interrupt. +Master: interrupts when the controller loses the bus arbitration +Slave: not available in this mode. + 4 + 1 + read-write + + + ADDRHIT + Set to enable the Address Hit Interrupt. +Master: interrupts when the addressed slave returned an ACK. +Slave: interrupts when the controller is addressed. + 3 + 1 + read-write + + + FIFOHALF + Set to enable the FIFO Half Interrupt. +Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. +Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. +This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. + 2 + 1 + read-write + + + FIFOFULL + Set to enable the FIFO Full Interrupt. +Interrupts when the FIFO is full. + 1 + 1 + read-write + + + FIFOEMPTY + Set to enabled the FIFO Empty Interrupt +Interrupts when the FIFO is empty. + 0 + 1 + read-write + + + + + STATUS + Status Register + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 15 + 17 + read-write + + + LINESDA + Indicates the current status of the SDA line on the bus +1: high +0: low + 14 + 1 + read-only + + + LINESCL + Indicates the current status of the SCL line on the bus +1: high +0: low + 13 + 1 + read-only + + + GENCALL + Indicates that the address of the current transaction is a general call address: +1: General call +0: Not general call + 12 + 1 + read-only + + + BUSBUSY + Indicates that the bus is busy +The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus +1: Busy +0: Not busy + 11 + 1 + read-only + + + ACK + Indicates the type of the last received/transmitted acknowledgement bit: +1: ACK +0: NACK + 10 + 1 + read-only + + + CMPL + Transaction Completion +Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration +Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. + 9 + 1 + write-only + + + BYTERECV + Indicates that a byte of data has been received. + 8 + 1 + write-only + + + BYTETRANS + Indicates that a byte of data has been transmitted. + 7 + 1 + write-only + + + START + Indicates that a START Condition or a repeated START condition has been transmitted/received. + 6 + 1 + write-only + + + STOP + Indicates that a STOP Condition has been transmitted/received. + 5 + 1 + write-only + + + ARBLOSE + Indicates that the controller has lost the bus arbitration. + 4 + 1 + write-only + + + ADDRHIT + Master: indicates that a slave has responded to the transaction. +Slave: indicates that a transaction is targeting the controller (including the General Call). + 3 + 1 + write-only + + + FIFOHALF + Transmitter: Indicates that the FIFO is half-empty. + 2 + 1 + read-only + + + FIFOFULL + Indicates that the FIFO is full. + 1 + 1 + read-only + + + FIFOEMPTY + Indicates that the FIFO is empty. + 0 + 1 + read-only + + + + + ADDR + Address Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 10 + 22 + read-write + + + ADDR + The slave address. +For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid + 0 + 10 + read-write + + + + + DATA + Data Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 8 + 24 + read-write + + + DATA + Write this register to put one byte of data to the FIFO. +Read this register to get one byte of data from the FIFO. + 0 + 8 + read-write + + + + + CTRL + Control Register + 0x24 + 32 + 0x00001E00 + 0x000F9FFF + + + RESERVED + No description avaiable + 15 + 5 + read-write + + + PHASE_START + Enable this bit to send a START condition at the beginning of transaction. +Master mode only. + 12 + 1 + read-write + + + PHASE_ADDR + Enable this bit to send the address after START condition. +Master mode only. + 11 + 1 + read-write + + + PHASE_DATA + Enable this bit to send the data after Address phase. +Master mode only. + 10 + 1 + read-write + + + PHASE_STOP + Enable this bit to send a STOP condition at the end of a transaction. +Master mode only. + 9 + 1 + read-write + + + DIR + Transaction direction +Master: Set this bit to determine the direction for the next transaction. +0: Transmitter +1: Receiver +Slave: The direction of the last received transaction. +0: Receiver +1: Transmitter + 8 + 1 + read-write + + + DATACNT + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 0 + 8 + read-write + + + + + CMD + Command Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 3 + 29 + read-write + + + CMD + Write this register with the following values to perform the corresponding actions: +0x0: no action +0x1: issue a data transaction (Master only) +0x2: respond with an ACK to the received byte +0x3: respond with a NACK to the received byte +0x4: clear the FIFO +0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) +When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. +Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. + 0 + 3 + read-write + + + + + SETUP + Setup Register + 0x2c + 32 + 0x05252100 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 29 + 3 + read-write + + + T_SUDAT + T_SUDAT defines the data setup time before releasing the SCL. +Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) +tpclk = PCLK period +TPM = The multiplier value in Timing Parameter Multiplier Register + 24 + 5 + read-write + + + T_SP + T_SP defines the pulse width of spikes that must be suppressed by the input filter. +Pulse width = T_SP * tpclk* (TPM+1) + 21 + 3 + read-write + + + T_HDDAT + T_HDDAT defines the data hold time after SCL goes LOW +Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) + 16 + 5 + read-write + + + RESERVED + No description avaiable + 14 + 2 + read-write + + + T_SCLRADIO + The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. +SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) +1: ratio = 2 +0: ratio = 1 +This field is only valid when the controller is in the master mode. + 13 + 1 + read-write + + + T_SCLHI + The HIGH period of generated SCL clock is defined by T_SCLHi. +SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) +The T_SCLHi value must be greater than T_SP and T_HDDAT values. +This field is only valid when the controller is in the master mode. + 4 + 9 + read-write + + + DMAEN + Enable the direct memory access mode data transfer. +1: Enable +0: Disable + 3 + 1 + read-write + + + MASTER + Configure this device as a master or a slave. +1: Master mode +0: Slave mode + 2 + 1 + read-write + + + ADDRESSING + I2C addressing mode: +1: 10-bit addressing mode +0: 7-bit addressing mode + 1 + 1 + read-write + + + IICEN + Enable the I2C controller. +1: Enable +0: Disable + 0 + 1 + read-write + + + + + TPM + I2C Timing Paramater Multiplier + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 5 + 27 + read-write + + + TPM + A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). + 0 + 5 + read-write + + + + + + + I2C1 + I2C1 + I2C + 0xf3024000 + + + I2C2 + I2C2 + I2C + 0xf3028000 + + + I2C3 + I2C3 + I2C + 0xf302c000 + + + LIN0 + LIN0 + LIN + 0xf3030000 + + 0x0 + 0x40 + registers + + + + DATABYTE_DATA_BYTE0 + data byte + 0x0 + 32 + 0x00000000 + 0x000000FF + + + DATA_BYTE + data byte + 0 + 8 + read-write + + + + + DATABYTE_DATA_BYTE1 + data byte + 0x4 + 32 + 0x00000000 + 0x000000FF + + + DATA_BYTE + data byte + 0 + 8 + read-write + + + + + DATABYTE_DATA_BYTE2 + data byte + 0x8 + 32 + 0x00000000 + 0x000000FF + + + DATA_BYTE + data byte + 0 + 8 + read-write + + + + + DATABYTE_DATA_BYTE3 + data byte + 0xc + 32 + 0x00000000 + 0x000000FF + + + DATA_BYTE + data byte + 0 + 8 + read-write + + + + + DATABYTE_DATA_BYTE4 + data byte + 0x10 + 32 + 0x00000000 + 0x000000FF + + + DATA_BYTE + data byte + 0 + 8 + read-write + + + + + DATABYTE_DATA_BYTE5 + data byte + 0x14 + 32 + 0x00000000 + 0x000000FF + + + DATA_BYTE + data byte + 0 + 8 + read-write + + + + + DATABYTE_DATA_BYTE6 + data byte + 0x18 + 32 + 0x00000000 + 0x000000FF + + + DATA_BYTE + data byte + 0 + 8 + read-write + + + + + DATABYTE_DATA_BYTE7 + data byte + 0x1c + 32 + 0x00000000 + 0x000000FF + + + DATA_BYTE + data byte + 0 + 8 + read-write + + + + + CONTROL + control register + 0x20 + 32 + 0x00000000 + 0x000000FF + + + STOP + slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID + 7 + 1 + write-only + + + SLEEP + The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core. + 6 + 1 + read-write + + + TRANSMIT + 1: transmit operation 0: receive operation + 5 + 1 + read-write + + + DATA_ACK + slave only. Write 1 after handling a data request interrupt + 4 + 1 + read-write + + + RESET_INT + write 1 to reset the int bit in the status register and the interrupt request output of LIN + 3 + 1 + write-only + + + RESET_ERROR + assert 1 to reset the error bits in status register and error register. A read access to this bit delivers always the value 0 + 2 + 1 + write-only + + + WAKEUP_REQ + wakeup request. Assert to terminate the Sleep mode of the LIN bus. The bit will be reset by core + 1 + 1 + read-write + + + START_REQ + master only. Set by host controller of a LIN master to start the LIN transmission. The core will reset the bit after the transmission is finished or an error is occurred + 0 + 1 + read-write + + + + + STATE + state register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + LIN_ACTIVE + The bit indicates whether the LIN bus is active or not + 7 + 1 + read-only + + + BUS_IDLE_TV + slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s + 6 + 1 + read-only + + + ABORTED + slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error. + 5 + 1 + read-only + + + DATA_REQ + slave only. Sets after receiving the identifier and requests an interrupt to the host controller. + 4 + 1 + read-only + + + INT + set when request an interrupt. Reset by reset_int + 3 + 1 + read-only + + + ERROR + set when detecte an error, clear by reset_error + 2 + 1 + read-only + + + WAKEUP + set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1 + 1 + 1 + read-only + + + COMPLETE + set after a transmission has been successful finished and it will reset at the start of a transmission. + 0 + 1 + read-only + + + + + ERROR + error register + 0x28 + 32 + 0x00000000 + 0x0000000F + + + PARITY_ERROR + slave only. identifier parity error + 3 + 1 + read-only + + + TIMEOUT + timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms + 2 + 1 + read-only + + + CHK_ERROR + checksum error + 1 + 1 + read-only + + + BIT_ERROR + bit error + 0 + 1 + read-only + + + + + DATA_LEN + data lenth register + 0x2c + 32 + 0x00000000 + 0x0000008F + + + ENH_CHECK + 1:enhence check mode + 7 + 1 + read-write + + + DATA_LENGTH + data length + 0 + 4 + read-write + + + + + BAUDRATE_CTL_LOW + baudrate control low register + 0x30 + 32 + 0x00000000 + 0x000000FF + + + BT_DIV_LOW + bit div register 7:0 + 0 + 8 + read-write + + + + + BARDRATE_CTL_HIGH + baudrate control high register + 0x34 + 32 + 0x00000000 + 0x000000FF + + + PRESCL + prescl register + 6 + 2 + read-write + + + BT_MUL + bt_mul register + 1 + 5 + read-write + + + BT_DIV_HIGH + bit div register 8 + 0 + 1 + read-write + + + + + ID + id register + 0x38 + 32 + 0x00000000 + 0x0000003F + + + ID + id register + 0 + 6 + read-write + + + + + TV + timeout control register + 0x3c + 32 + 0x00000040 + 0x000000CF + + + INITIAL_MODE + initial_mode + 7 + 1 + read-write + + + MASTER_MODE + master_mode + 6 + 1 + read-write + + + BUS_INACTIVITY_TIME + slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s + 2 + 2 + read-write + + + WUP_REPEAT_TIME + slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms + 0 + 2 + read-write + + + + + + + LIN1 + LIN1 + LIN + 0xf3034000 + + + LIN2 + LIN2 + LIN + 0xf3038000 + + + LIN3 + LIN3 + LIN + 0xf303c000 + + + SDP + SDP + SDP + 0xf304c000 + + 0x0 + 0x60 + registers + + + + SDPCR + SDP control register + 0x0 + 32 + 0x30000000 + 0xFFFE0101 + + + SFTRST + soft reset. +Write 1 then 0, to reset the SDP block. + 31 + 1 + read-write + + + CLKGAT + Clock Gate for the SDP main logic. +Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. + 30 + 1 + read-write + + + CIPDIS + Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. +1, Cipher is disabled in this chip. +0, Cipher is enabled in this chip. + 29 + 1 + read-only + + + HASDIS + HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. +1, HASH is disabled in this chip. +0, HASH is enabled in this chip. + 28 + 1 + read-only + + + RESERVED + Not used + 24 + 4 + read-only + + + CIPHEN + Cipher Enablement, controlled by SW. +1, Cipher is Enabled. +0, Cipher is Disabled. + 23 + 1 + read-write + + + HASHEN + HASH Enablement, controlled by SW. +1, HASH is Enabled. +0, HASH is Disabled. + 22 + 1 + read-write + + + MCPEN + Memory Copy Enablement, controlled by SW. +1, Memory copy is Enabled. +0, Memory copy is Disabled. + 21 + 1 + read-write + + + CONFEN + Constant Fill to memory, controlled by SW. +1, Constant fill is Enabled. +0, Constant fill is Disabled. + 20 + 1 + read-write + + + DCRPDI + Decryption Disable bit, Write to 1 to disable the decryption. + 19 + 1 + read-write + + + RESERVED + Reserved + 18 + 1 + read-write + + + TSTPKT0IRQ + Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. + 17 + 1 + read-write + + + RDSCEN + when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) +when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) + 8 + 1 + read-write + + + INTEN + Interrupt Enablement, controlled by SW. +1, SDP interrupt is enabled. +0, SDP interrupt is disabled. + 0 + 1 + read-write + + + + + MODCTRL + Mod control register. + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AESALG + AES algorithem selection. +0x0 = AES 128; +0x1 = AES 256; +0x8 = SM4； +Others, reserved. + 28 + 4 + read-write + + + AESMOD + AES mode selection. +0x0 = ECB; +0x1 = CBC; +Others, reserved. + 24 + 4 + read-write + + + AESKS + AES Key Selection. +These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: +0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. +0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +.... +0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. +0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. +0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. +0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. +0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. +0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. +0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. +0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. +0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. +0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. +0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. +0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. +0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. +Other values, reserved. + 18 + 6 + read-write + + + RESERVED + Not used + 17 + 1 + read-only + + + AESDIR + AES direction +1x1, AES Decryption +1x0, AES Encryption. + 16 + 1 + read-write + + + HASALG + HASH Algorithem selection. +0x0 SHA1 — +0x1 CRC32 — +0x2 SHA256 — + 12 + 4 + read-write + + + CRCEN + CRC enable. +1x1, CRC is enabled. +1x0, CRC is disabled. + 11 + 1 + read-write + + + HASCHK + HASH Check Enable Bit. +1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; +1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. +For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. + 10 + 1 + read-write + + + HASOUT + When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. +0 INPUT HASH +1 OUTPUT HASH + 9 + 1 + read-write + + + RESERVED + Not used + 8 + 1 + read-only + + + RESERVED + Not used + 6 + 2 + read-only + + + DINSWP + Decide whether the SDP byteswaps the input data (big-endian data); +When all bits are set, the data is assumed to be in the big-endian format + 4 + 2 + read-write + + + DOUTSWP + Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format + 2 + 2 + read-write + + + KEYSWP + Decide whether the SDP byteswaps the Key (big-endian data). +When all bits are set, the data is assumed to be in the big-endian format + 0 + 2 + read-write + + + + + PKTCNT + packet counter registers. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + Not used + 31 + 1 + read-write + + + RESERVED + Not used + 30 + 1 + read-write + + + RESERVED + Not used + 24 + 6 + read-only + + + CNTVAL + This read-only field shows the current (instantaneous) value of the packet counter + 16 + 8 + read-only + + + RESERVED + Not used + 8 + 8 + read-only + + + CNTINCR + The value written to this field is added to the spacket count. + 0 + 8 + read-write + + + + + STA + Status Registers + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TAG + packet tag. + 24 + 8 + read-only + + + IRQ + interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. + 23 + 1 + write-only + + + RESERVED + Not used + 21 + 2 + read-only + + + CHN1PKT0 + the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. + 20 + 1 + write-only + + + AESBSY + AES Busy + 19 + 1 + read-only + + + HASBSY + Hashing Busy + 18 + 1 + read-only + + + PKTCNT0 + Packet Counter registers reachs to ZERO now. + 17 + 1 + write-only + + + PKTDON + Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. + 16 + 1 + write-only + + + RESERVED + Not used + 6 + 10 + read-only + + + ERRSET + Working mode setup error. + 5 + 1 + write-only + + + ERRPKT + Packet head access error, or status update error. + 4 + 1 + write-only + + + ERRSRC + Source Buffer Access Error + 3 + 1 + write-only + + + ERRDST + Destination Buffer Error + 2 + 1 + write-only + + + ERRHAS + Hashing Check Error + 1 + 1 + write-only + + + ERRCHAIN + buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. + 0 + 1 + write-only + + + + + KEYADDR + Key Address + 0x10 + 32 + 0x00000040 + 0xFFFFFFFF + + + RESERVED + Not used + 24 + 8 + read-only + + + INDEX + To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. +Key index pointer. The valid indices are 0-[number_keys]. +In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. + 16 + 8 + read-write + + + RESERVED + Not used + 2 + 14 + read-only + + + SUBWRD + Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field +increments; To write a key, the software must first write the desired key index/subword to this register. + 0 + 2 + read-write + + + + + KEYDAT + Key Data + 0x14 + 32 + 0x00000030 + 0xFFFFFFFF + + + KEYDAT + This register provides the write access to the key/key subword specified by the key index register. +Writing this location updates the selected subword for the key located at the index +specified by the key index register. The write also triggers the SUBWORD field of the +KEY register to increment to the next higher word in the key + 0 + 32 + read-write + + + + + CIPHIV_CIPHIV0 + Cipher Initializtion Vector 0 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + CIPHIV_CIPHIV1 + Cipher Initializtion Vector 1 + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + CIPHIV_CIPHIV2 + Cipher Initializtion Vector 2 + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + CIPHIV_CIPHIV3 + Cipher Initializtion Vector 3 + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + HASWRD_HASWRD0 + Hash Data Word 0 + 0x28 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD1 + Hash Data Word 1 + 0x2c + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD2 + Hash Data Word 2 + 0x30 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD3 + Hash Data Word 3 + 0x34 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD4 + Hash Data Word 4 + 0x38 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD5 + Hash Data Word 5 + 0x3c + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD6 + Hash Data Word 6 + 0x40 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + HASWRD_HASWRD7 + Hash Data Word 7 + 0x44 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + CMDPTR + Command Pointer + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMDPTR + current command addresses the register points to the multiword +descriptor that is to be executed (or is currently being executed) + 0 + 32 + read-write + + + + + NPKTPTR + Next Packet Address Pointer + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + NPKTPTR + Next Packet Address Pointer + 0 + 32 + read-write + + + + + PKTCTL + Packet Control Registers + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTTAG + packet tag + 24 + 8 + read-write + + + RESERVED + Not used + 7 + 17 + read-write + + + CIPHIV + Load Initial Vector for the AES in this packet. + 6 + 1 + read-write + + + HASFNL + Hash Termination packet + 5 + 1 + read-write + + + HASINI + Hash Initialization packat + 4 + 1 + read-write + + + CHAIN + whether the next command pointer register must be loaded into the channel's current descriptor +pointer. + 3 + 1 + read-write + + + DCRSEMA + whether the channel's semaphore must be decremented at the end of the current operation. +When the semaphore reaches a value of zero, no more operations are issued from the channel. + 2 + 1 + read-write + + + PKTINT + Reflects whether the channel must issue an interrupt upon the completion of the packet + 1 + 1 + read-write + + + RESERVED + Not used + 0 + 1 + read-write + + + + + PKTSRC + Packet Memory Source Address + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTSRC + Packet Memory Source Address + 0 + 32 + read-write + + + + + PKTDST + Packet Memory Destination Address + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTDST + Packet Memory Destination Address + 0 + 32 + read-write + + + + + PKTBUF + Packet buffer size. + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTBUF + No description avaiable + 0 + 32 + read-write + + + + + + + SYSCTL + SYSCTL + SYSCTL + 0xf4000000 + + 0x0 + 0x3000 + registers + + + + RESOURCE_CPU0 + Resource control register for cpu0_core + 0x0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CPX0 + Resource control register for cpu0_subsys + 0x4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CPU1 + Resource control register for cpu1_core + 0x20 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CPX1 + Resource control register for cpu1_subsys + 0x24 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_POW_CPU0 + Resource control register for pow_cpu0 + 0x54 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_POW_CPU1 + Resource control register for pow_cpu1 + 0x58 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RST_SOC + Resource control register for rst_soc + 0x5c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RST_CPU0 + Resource control register for rst_cpu0 + 0x60 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RST_CPU1 + Resource control register for rst_cpu1 + 0x64 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_XTAL + Resource control register for xtal + 0x80 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL0 + Resource control register for pll0 + 0x84 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK0_PLL0 + Resource control register for clk0_pll0 + 0x88 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK1_PLL0 + Resource control register for clk1_pll0 + 0x8c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK2_PLL0 + Resource control register for clk2_pll0 + 0x90 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL1 + Resource control register for pll1 + 0x94 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK0_PLL1 + Resource control register for clk0_pll1 + 0x98 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK1_PLL1 + Resource control register for clk1_pll1 + 0x9c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL2 + Resource control register for pll2 + 0xa0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK0_PLL2 + Resource control register for clk0_pll2 + 0xa4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_CLK1_PLL2 + Resource control register for clk1_pll2 + 0xa8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL0_REF + Resource control register for pll0 ref clock + 0xac + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL1_REF + Resource control register for pll1 ref clock + 0xb0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_SRC_PLL2_REF + Resource control register for pll2 ref clock + 0xb4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CPU0 + Resource control register for clk_top_cpu0 + 0x100 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_MCT0 + Resource control register for clk_top_mct0 + 0x104 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_MCT1 + Resource control register for clk_top_mct1 + 0x108 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_XPI0 + Resource control register for clk_top_xpi0 + 0x10c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_TMR0 + Resource control register for clk_top_tmr0 + 0x110 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_TMR1 + Resource control register for clk_top_tmr1 + 0x114 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_TMR2 + Resource control register for clk_top_tmr2 + 0x118 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_TMR3 + Resource control register for clk_top_tmr3 + 0x11c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT0 + Resource control register for clk_top_urt0 + 0x120 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT1 + Resource control register for clk_top_urt1 + 0x124 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT2 + Resource control register for clk_top_urt2 + 0x128 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT3 + Resource control register for clk_top_urt3 + 0x12c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT4 + Resource control register for clk_top_urt4 + 0x130 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT5 + Resource control register for clk_top_urt5 + 0x134 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT6 + Resource control register for clk_top_urt6 + 0x138 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_URT7 + Resource control register for clk_top_urt7 + 0x13c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2C0 + Resource control register for clk_top_i2c0 + 0x140 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2C1 + Resource control register for clk_top_i2c1 + 0x144 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2C2 + Resource control register for clk_top_i2c2 + 0x148 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_I2C3 + Resource control register for clk_top_i2c3 + 0x14c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SPI0 + Resource control register for clk_top_spi0 + 0x150 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SPI1 + Resource control register for clk_top_spi1 + 0x154 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SPI2 + Resource control register for clk_top_spi2 + 0x158 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_SPI3 + Resource control register for clk_top_spi3 + 0x15c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CAN0 + Resource control register for clk_top_can0 + 0x160 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CAN1 + Resource control register for clk_top_can1 + 0x164 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CAN2 + Resource control register for clk_top_can2 + 0x168 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_CAN3 + Resource control register for clk_top_can3 + 0x16c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_PTPC + Resource control register for clk_top_ptpc + 0x170 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ANA0 + Resource control register for clk_top_ana0 + 0x174 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ANA1 + Resource control register for clk_top_ana1 + 0x178 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ANA2 + Resource control register for clk_top_ana2 + 0x17c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ANA3 + Resource control register for clk_top_ana3 + 0x180 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ANA4 + Resource control register for clk_top_ana4 + 0x184 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_REF0 + Resource control register for clk_top_ref0 + 0x188 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_REF1 + Resource control register for clk_top_ref1 + 0x18c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_LIN0 + Resource control register for clk_top_lin0 + 0x190 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_LIN1 + Resource control register for clk_top_lin1 + 0x194 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_LIN2 + Resource control register for clk_top_lin2 + 0x198 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_LIN3 + Resource control register for clk_top_lin3 + 0x19c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ADC0 + Resource control register for clk_top_adc0 + 0x200 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ADC1 + Resource control register for clk_top_adc1 + 0x204 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_ADC2 + Resource control register for clk_top_adc2 + 0x208 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_DAC0 + Resource control register for clk_top_dac0 + 0x20c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CLK_TOP_DAC1 + Resource control register for clk_top_dac1 + 0x210 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_AHBP + Resource control register for ahbapb_bus + 0x400 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_AXIS + Resource control register for soc_bus + 0x404 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_AXIC + Resource control register for conn_bus + 0x408 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_LMM0 + Resource control register for lmm0 + 0x40c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MCT0 + Resource control register for mchtmr0 + 0x410 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_LMM1 + Resource control register for lmm1 + 0x414 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MCT1 + Resource control register for mchtmr1 + 0x418 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ROM0 + Resource control register for rom + 0x41c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RAM0 + Resource control register for axi_sram + 0x420 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2C0 + Resource control register for i2c0 + 0x424 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2C1 + Resource control register for i2c1 + 0x428 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2C2 + Resource control register for i2c2 + 0x42c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_I2C3 + Resource control register for i2c3 + 0x430 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_TMR0 + Resource control register for tmr0 + 0x434 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_TMR1 + Resource control register for tmr1 + 0x438 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_TMR2 + Resource control register for tmr2 + 0x43c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_TMR3 + Resource control register for tmr3 + 0x440 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_GPIO + Resource control register for gpio + 0x444 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ADC0 + Resource control register for adc0 + 0x448 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ADC1 + Resource control register for adc1 + 0x44c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ADC2 + Resource control register for adc2 + 0x450 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_DAC0 + Resource control register for dac0 + 0x454 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_DAC1 + Resource control register for dac1 + 0x458 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_ACMP + Resource control register for acmp + 0x45c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SPI0 + Resource control register for spi0 + 0x460 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SPI1 + Resource control register for spi1 + 0x464 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SPI2 + Resource control register for spi2 + 0x468 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SPI3 + Resource control register for spi3 + 0x46c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SDM0 + Resource control register for sdm + 0x470 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT0 + Resource control register for uart0 + 0x474 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT1 + Resource control register for uart1 + 0x478 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT2 + Resource control register for uart2 + 0x47c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT3 + Resource control register for uart3 + 0x480 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT4 + Resource control register for uart4 + 0x484 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT5 + Resource control register for uart5 + 0x488 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT6 + Resource control register for uart6 + 0x48c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_URT7 + Resource control register for uart7 + 0x490 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_LIN0 + Resource control register for lin0 + 0x494 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_LIN1 + Resource control register for lin1 + 0x498 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_LIN2 + Resource control register for lin2 + 0x49c + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_LIN3 + Resource control register for lin3 + 0x4a0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_PTPC + Resource control register for ptpc + 0x4a4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CAN0 + Resource control register for can0 + 0x4a8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CAN1 + Resource control register for can1 + 0x4ac + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CAN2 + Resource control register for can2 + 0x4b0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CAN3 + Resource control register for can3 + 0x4b4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_WDG0 + Resource control register for wdg0 + 0x4b8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_WDG1 + Resource control register for wdg1 + 0x4bc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MBX0 + Resource control register for mbx0 + 0x4c0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MBX1 + Resource control register for mbx1 + 0x4c4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_CRC0 + Resource control register for crc + 0x4c8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MOT0 + Resource control register for mot0 + 0x4cc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MOT1 + Resource control register for mot1 + 0x4d0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MOT2 + Resource control register for mot2 + 0x4d4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MOT3 + Resource control register for mot3 + 0x4d8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_MSYN + Resource control register for msyn + 0x4dc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_XPI0 + Resource control register for xpi0 + 0x4e0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_HDMA + Resource control register for hdma + 0x4e4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_XDMA + Resource control register for xdma + 0x4e8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_KMAN + Resource control register for keym + 0x4ec + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_SDP0 + Resource control register for sdp + 0x4f0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_RNG0 + Resource control register for rng + 0x4f4 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_TSNS + Resource control register for tsns + 0x4f8 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_USB0 + Resource control register for usb + 0x4fc + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_REF0 + Resource control register for ref0 + 0x500 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + RESOURCE_REF1 + Resource control register for ref1 + 0x504 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + GROUP0_LINK0_VALUE + Group setting + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_LINK0_SET + Group setting + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + GROUP0_LINK0_CLEAR + Group setting + 0x808 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + GROUP0_LINK0_TOGGLE + Group setting + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + GROUP0_LINK1_VALUE + Group setting + 0x810 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_LINK1_SET + Group setting + 0x814 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + GROUP0_LINK1_CLEAR + Group setting + 0x818 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + GROUP0_LINK1_TOGGLE + Group setting + 0x81c + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + GROUP0_LINK2_VALUE + Group setting + 0x820 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP0_LINK2_SET + Group setting + 0x824 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + GROUP0_LINK2_CLEAR + Group setting + 0x828 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + GROUP0_LINK2_TOGGLE + Group setting + 0x82c + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + GROUP1_LINK0_VALUE + Group setting + 0x840 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_LINK0_SET + Group setting + 0x844 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + GROUP1_LINK0_CLEAR + Group setting + 0x848 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + GROUP1_LINK0_TOGGLE + Group setting + 0x84c + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + GROUP1_LINK1_VALUE + Group setting + 0x850 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_LINK1_SET + Group setting + 0x854 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + GROUP1_LINK1_CLEAR + Group setting + 0x858 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + GROUP1_LINK1_TOGGLE + Group setting + 0x85c + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + GROUP1_LINK2_VALUE + Group setting + 0x860 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + GROUP1_LINK2_SET + Group setting + 0x864 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + GROUP1_LINK2_CLEAR + Group setting + 0x868 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + GROUP1_LINK2_TOGGLE + Group setting + 0x86c + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + AFFILIATE_CPU0_VALUE + Affiliate of Group + 0x900 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +bit0: cpu0 depends on group0 +bit1: cpu0 depends on group1 +bit2: cpu0 depends on group2 +bit3: cpu0 depends on group3 + 0 + 4 + read-write + + + + + AFFILIATE_CPU0_SET + Affiliate of Group + 0x904 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0，each bit represents a group +0: no effect +1: the group is assigned to CPU0 + 0 + 4 + read-write + + + + + AFFILIATE_CPU0_CLEAR + Affiliate of Group + 0x908 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: the group is not assigned to CPU0 + 0 + 4 + read-write + + + + + AFFILIATE_CPU0_TOGGLE + Affiliate of Group + 0x90c + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: toggle the result that whether the group is assigned to CPU0 before + 0 + 4 + read-write + + + + + AFFILIATE_CPU1_VALUE + Affiliate of Group + 0x910 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +bit0: cpu0 depends on group0 +bit1: cpu0 depends on group1 +bit2: cpu0 depends on group2 +bit3: cpu0 depends on group3 + 0 + 4 + read-write + + + + + AFFILIATE_CPU1_SET + Affiliate of Group + 0x914 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0，each bit represents a group +0: no effect +1: the group is assigned to CPU0 + 0 + 4 + read-write + + + + + AFFILIATE_CPU1_CLEAR + Affiliate of Group + 0x918 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: the group is not assigned to CPU0 + 0 + 4 + read-write + + + + + AFFILIATE_CPU1_TOGGLE + Affiliate of Group + 0x91c + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: toggle the result that whether the group is assigned to CPU0 before + 0 + 4 + read-write + + + + + RETENTION_CPU0_VALUE + Retention Contol + 0x920 + 32 + 0x00000000 + 0x000003FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +bit00: soc_mem is kept on while cpu0 stop +bit01: soc_ctx is kept on while cpu0 stop +bit02: cpu0_mem is kept on while cpu0 stop +bit03: cpu0_ctx is kept on while cpu0 stop +bit04: cpu1_mem is kept on while cpu0 stop +bit05: cpu1_ctx is kept on while cpu0 stop +bit06: xtal_hold is kept on while cpu0 stop +bit07: pll0_hold is kept on while cpu0 stop +bit08: pll1_hold is kept on while cpu0 stop +bit09: pll2_hold is kept on while cpu0 stop + 0 + 10 + read-write + + + + + RETENTION_CPU0_SET + Retention Contol + 0x924 + 32 + 0x00000000 + 0x000003FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: keep + 0 + 10 + read-write + + + + + RETENTION_CPU0_CLEAR + Retention Contol + 0x928 + 32 + 0x00000000 + 0x000003FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: no keep + 0 + 10 + read-write + + + + + RETENTION_CPU0_TOGGLE + Retention Contol + 0x92c + 32 + 0x00000000 + 0x000003FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: toggle the result that whether the resource is kept on while CPU0 stop before + 0 + 10 + read-write + + + + + RETENTION_CPU1_VALUE + Retention Contol + 0x930 + 32 + 0x00000000 + 0x000003FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +bit00: soc_mem is kept on while cpu0 stop +bit01: soc_ctx is kept on while cpu0 stop +bit02: cpu0_mem is kept on while cpu0 stop +bit03: cpu0_ctx is kept on while cpu0 stop +bit04: cpu1_mem is kept on while cpu0 stop +bit05: cpu1_ctx is kept on while cpu0 stop +bit06: xtal_hold is kept on while cpu0 stop +bit07: pll0_hold is kept on while cpu0 stop +bit08: pll1_hold is kept on while cpu0 stop +bit09: pll2_hold is kept on while cpu0 stop + 0 + 10 + read-write + + + + + RETENTION_CPU1_SET + Retention Contol + 0x934 + 32 + 0x00000000 + 0x000003FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: keep + 0 + 10 + read-write + + + + + RETENTION_CPU1_CLEAR + Retention Contol + 0x938 + 32 + 0x00000000 + 0x000003FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: no keep + 0 + 10 + read-write + + + + + RETENTION_CPU1_TOGGLE + Retention Contol + 0x93c + 32 + 0x00000000 + 0x000003FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: toggle the result that whether the resource is kept on while CPU0 stop before + 0 + 10 + read-write + + + + + POWER_CPU0_STATUS + Power Setting + 0x1000 + 32 + 0x80000000 + 0xC0001100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + POWER_CPU0_LF_WAIT + Power Setting + 0x1004 + 32 + 0x00000255 + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + POWER_CPU0_OFF_WAIT + Power Setting + 0x100c + 32 + 0x00000015 + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + POWER_CPU1_STATUS + Power Setting + 0x1010 + 32 + 0x80000000 + 0xC0001100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + POWER_CPU1_LF_WAIT + Power Setting + 0x1014 + 32 + 0x00000255 + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + POWER_CPU1_OFF_WAIT + Power Setting + 0x101c + 32 + 0x00000015 + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + RESET_SOC_CONTROL + Reset Setting + 0x1400 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly + 0 + 1 + read-write + + + + + RESET_SOC_CONFIG + Reset Setting + 0x1404 + 32 + 0x00643203 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + RESET_SOC_COUNTER + Reset Setting + 0x140c + 32 + 0x00000003 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + RESET_CPU0_CONTROL + Reset Setting + 0x1410 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly + 0 + 1 + read-write + + + + + RESET_CPU0_CONFIG + Reset Setting + 0x1414 + 32 + 0x00643203 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + RESET_CPU0_COUNTER + Reset Setting + 0x141c + 32 + 0x00000003 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + RESET_CPU1_CONTROL + Reset Setting + 0x1420 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly + 0 + 1 + read-write + + + + + RESET_CPU1_CONFIG + Reset Setting + 0x1424 + 32 + 0x00643203 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + RESET_CPU1_COUNTER + Reset Setting + 0x142c + 32 + 0x00000003 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + CLOCK_CPU_CLK_TOP_CPU0 + Clock setting + 0x1800 + 32 + 0x00000000 + 0xD0FF07FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + SUB1_DIV + ahb bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 20 + 4 + read-write + + + SUB0_DIV + axi bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 16 + 4 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_MCT0 + Clock setting + 0x1804 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_MCT1 + Clock setting + 0x1808 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_XPI0 + Clock setting + 0x180c + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_TMR0 + Clock setting + 0x1810 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_TMR1 + Clock setting + 0x1814 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_TMR2 + Clock setting + 0x1818 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_TMR3 + Clock setting + 0x181c + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT0 + Clock setting + 0x1820 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT1 + Clock setting + 0x1824 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT2 + Clock setting + 0x1828 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT3 + Clock setting + 0x182c + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT4 + Clock setting + 0x1830 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT5 + Clock setting + 0x1834 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT6 + Clock setting + 0x1838 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_URT7 + Clock setting + 0x183c + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_I2C0 + Clock setting + 0x1840 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_I2C1 + Clock setting + 0x1844 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_I2C2 + Clock setting + 0x1848 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_I2C3 + Clock setting + 0x184c + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SPI0 + Clock setting + 0x1850 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SPI1 + Clock setting + 0x1854 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SPI2 + Clock setting + 0x1858 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_SPI3 + Clock setting + 0x185c + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CAN0 + Clock setting + 0x1860 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CAN1 + Clock setting + 0x1864 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CAN2 + Clock setting + 0x1868 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_CAN3 + Clock setting + 0x186c + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_PTPC + Clock setting + 0x1870 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ANA0 + Clock setting + 0x1874 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ANA1 + Clock setting + 0x1878 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ANA2 + Clock setting + 0x187c + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ANA3 + Clock setting + 0x1880 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_ANA4 + Clock setting + 0x1884 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_REF0 + Clock setting + 0x1888 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_REF1 + Clock setting + 0x188c + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_LIN0 + Clock setting + 0x1890 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_LIN1 + Clock setting + 0x1894 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_LIN2 + Clock setting + 0x1898 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + CLOCK_CLK_TOP_LIN3 + Clock setting + 0x189c + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + ADCCLK_CLK_TOP_ADC0 + Clock setting + 0x1c00 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + ADCCLK_CLK_TOP_ADC1 + Clock setting + 0x1c04 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + ADCCLK_CLK_TOP_ADC2 + Clock setting + 0x1c08 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + DACCLK_CLK_TOP_DAC0 + Clock setting + 0x1c0c + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + DACCLK_CLK_TOP_DAC1 + Clock setting + 0x1c10 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 + read-write + + + + + GLOBAL00 + Clock senario + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + MUX + global clock override request +bit0: override to preset0 +bit1: override to preset1 +bit2: override to preset2 +bit3: override to preset3 + 0 + 4 + read-write + + + + + MONITOR_SLICE0_CONTROL + Clock measure and monitor control + 0x2400 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0: clk_32k + 1: clk_irc24m + 2: clk_xtal_24m + 3: clk_usb0_phy + 8: clk0_osc0 + 9: clk0_pll0 + 10: clk1_pll0 + 11: clk2_pll0 + 12: clk0_pll1 + 13: clk1_pll1 + 14: clk0_pll2 + 15: clk1_pll2 +128: clk_top_cpu0 +129: clk_top_mct0 +130: clk_top_mct1 +131: clk_top_xpi0 +132: clk_top_tmr0 +133: clk_top_tmr1 +134: clk_top_tmr2 +135: clk_top_tmr3 +136: clk_top_urt0 +137: clk_top_urt1 +138: clk_top_urt2 +139: clk_top_urt3 +140: clk_top_urt4 +141: clk_top_urt5 +142: clk_top_urt6 +143: clk_top_urt7 +144: clk_top_i2c0 +145: clk_top_i2c1 +146: clk_top_i2c2 +147: clk_top_i2c3 +148: clk_top_spi0 +149: clk_top_spi1 +150: clk_top_spi2 +151: clk_top_spi3 +152: clk_top_can0 +153: clk_top_can1 +154: clk_top_can2 +155: clk_top_can3 +156: clk_top_ptpc +157: clk_top_ana0 +158: clk_top_ana1 +159: clk_top_ana2 +160: clk_top_ana3 +161: clk_top_ana4 +162: clk_top_ref0 +163: clk_top_ref1 +164: clk_top_lin0 +165: clk_top_lin1 +166: clk_top_lin2 +167: clk_top_lin3 + 0 + 8 + read-write + + + + + MONITOR_SLICE0_CURRENT + Clock measure result + 0x2404 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + MONITOR_SLICE0_LOW_LIMIT + Clock lower limit + 0x2408 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE0_HIGH_LIMIT + Clock upper limit + 0x240c + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE1_CONTROL + Clock measure and monitor control + 0x2420 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0: clk_32k + 1: clk_irc24m + 2: clk_xtal_24m + 3: clk_usb0_phy + 8: clk0_osc0 + 9: clk0_pll0 + 10: clk1_pll0 + 11: clk2_pll0 + 12: clk0_pll1 + 13: clk1_pll1 + 14: clk0_pll2 + 15: clk1_pll2 +128: clk_top_cpu0 +129: clk_top_mct0 +130: clk_top_mct1 +131: clk_top_xpi0 +132: clk_top_tmr0 +133: clk_top_tmr1 +134: clk_top_tmr2 +135: clk_top_tmr3 +136: clk_top_urt0 +137: clk_top_urt1 +138: clk_top_urt2 +139: clk_top_urt3 +140: clk_top_urt4 +141: clk_top_urt5 +142: clk_top_urt6 +143: clk_top_urt7 +144: clk_top_i2c0 +145: clk_top_i2c1 +146: clk_top_i2c2 +147: clk_top_i2c3 +148: clk_top_spi0 +149: clk_top_spi1 +150: clk_top_spi2 +151: clk_top_spi3 +152: clk_top_can0 +153: clk_top_can1 +154: clk_top_can2 +155: clk_top_can3 +156: clk_top_ptpc +157: clk_top_ana0 +158: clk_top_ana1 +159: clk_top_ana2 +160: clk_top_ana3 +161: clk_top_ana4 +162: clk_top_ref0 +163: clk_top_ref1 +164: clk_top_lin0 +165: clk_top_lin1 +166: clk_top_lin2 +167: clk_top_lin3 + 0 + 8 + read-write + + + + + MONITOR_SLICE1_CURRENT + Clock measure result + 0x2424 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + MONITOR_SLICE1_LOW_LIMIT + Clock lower limit + 0x2428 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE1_HIGH_LIMIT + Clock upper limit + 0x242c + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE2_CONTROL + Clock measure and monitor control + 0x2440 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0: clk_32k + 1: clk_irc24m + 2: clk_xtal_24m + 3: clk_usb0_phy + 8: clk0_osc0 + 9: clk0_pll0 + 10: clk1_pll0 + 11: clk2_pll0 + 12: clk0_pll1 + 13: clk1_pll1 + 14: clk0_pll2 + 15: clk1_pll2 +128: clk_top_cpu0 +129: clk_top_mct0 +130: clk_top_mct1 +131: clk_top_xpi0 +132: clk_top_tmr0 +133: clk_top_tmr1 +134: clk_top_tmr2 +135: clk_top_tmr3 +136: clk_top_urt0 +137: clk_top_urt1 +138: clk_top_urt2 +139: clk_top_urt3 +140: clk_top_urt4 +141: clk_top_urt5 +142: clk_top_urt6 +143: clk_top_urt7 +144: clk_top_i2c0 +145: clk_top_i2c1 +146: clk_top_i2c2 +147: clk_top_i2c3 +148: clk_top_spi0 +149: clk_top_spi1 +150: clk_top_spi2 +151: clk_top_spi3 +152: clk_top_can0 +153: clk_top_can1 +154: clk_top_can2 +155: clk_top_can3 +156: clk_top_ptpc +157: clk_top_ana0 +158: clk_top_ana1 +159: clk_top_ana2 +160: clk_top_ana3 +161: clk_top_ana4 +162: clk_top_ref0 +163: clk_top_ref1 +164: clk_top_lin0 +165: clk_top_lin1 +166: clk_top_lin2 +167: clk_top_lin3 + 0 + 8 + read-write + + + + + MONITOR_SLICE2_CURRENT + Clock measure result + 0x2444 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + MONITOR_SLICE2_LOW_LIMIT + Clock lower limit + 0x2448 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE2_HIGH_LIMIT + Clock upper limit + 0x244c + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE3_CONTROL + Clock measure and monitor control + 0x2460 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0: clk_32k + 1: clk_irc24m + 2: clk_xtal_24m + 3: clk_usb0_phy + 8: clk0_osc0 + 9: clk0_pll0 + 10: clk1_pll0 + 11: clk2_pll0 + 12: clk0_pll1 + 13: clk1_pll1 + 14: clk0_pll2 + 15: clk1_pll2 +128: clk_top_cpu0 +129: clk_top_mct0 +130: clk_top_mct1 +131: clk_top_xpi0 +132: clk_top_tmr0 +133: clk_top_tmr1 +134: clk_top_tmr2 +135: clk_top_tmr3 +136: clk_top_urt0 +137: clk_top_urt1 +138: clk_top_urt2 +139: clk_top_urt3 +140: clk_top_urt4 +141: clk_top_urt5 +142: clk_top_urt6 +143: clk_top_urt7 +144: clk_top_i2c0 +145: clk_top_i2c1 +146: clk_top_i2c2 +147: clk_top_i2c3 +148: clk_top_spi0 +149: clk_top_spi1 +150: clk_top_spi2 +151: clk_top_spi3 +152: clk_top_can0 +153: clk_top_can1 +154: clk_top_can2 +155: clk_top_can3 +156: clk_top_ptpc +157: clk_top_ana0 +158: clk_top_ana1 +159: clk_top_ana2 +160: clk_top_ana3 +161: clk_top_ana4 +162: clk_top_ref0 +163: clk_top_ref1 +164: clk_top_lin0 +165: clk_top_lin1 +166: clk_top_lin2 +167: clk_top_lin3 + 0 + 8 + read-write + + + + + MONITOR_SLICE3_CURRENT + Clock measure result + 0x2464 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + MONITOR_SLICE3_LOW_LIMIT + Clock lower limit + 0x2468 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + MONITOR_SLICE3_HIGH_LIMIT + Clock upper limit + 0x246c + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + CPU_CPU0_LP + CPU0 LP control + 0x2800 + 32 + 0x00001000 + 0xFF013703 + + + WAKE_CNT + CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + 24 + 8 + read-write + + + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 + 1 + read-write + + + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 + 1 + read-only + + + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 + 1 + read-only + + + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wake up happened + 10 + 1 + read-write + + + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 + 1 + read-write + + + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 reset not happened +1: CPU0 reset happened + 8 + 1 + read-write + + + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved + 0 + 2 + read-write + + + + + CPU_CPU0_LOCK + CPU0 Lock GPR + 0x2804 + 32 + 0x00000002 + 0x0000FFFE + + + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 + read-write + + + LOCK + Lock bit for CPU_LOCK + 1 + 1 + read-write + + + + + CPU_CPU0_GPR_GPR0 + CPU0 GPR0 + 0x2808 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR1 + CPU0 GPR1 + 0x280c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR2 + CPU0 GPR2 + 0x2810 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR3 + CPU0 GPR3 + 0x2814 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR4 + CPU0 GPR4 + 0x2818 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR5 + CPU0 GPR5 + 0x281c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR6 + CPU0 GPR6 + 0x2820 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR7 + CPU0 GPR7 + 0x2824 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR8 + CPU0 GPR8 + 0x2828 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR9 + CPU0 GPR9 + 0x282c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR10 + CPU0 GPR10 + 0x2830 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR11 + CPU0 GPR11 + 0x2834 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR12 + CPU0 GPR12 + 0x2838 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_GPR_GPR13 + CPU0 GPR13 + 0x283c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU0_WAKEUP_STATUS_STATUS0 + CPU0 wakeup IRQ status + 0x2840 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_WAKEUP_STATUS_STATUS1 + CPU0 wakeup IRQ status + 0x2844 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_WAKEUP_STATUS_STATUS2 + CPU0 wakeup IRQ status + 0x2848 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_WAKEUP_STATUS_STATUS3 + CPU0 wakeup IRQ status + 0x284c + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU0_WAKEUP_ENABLE_ENABLE0 + CPU0 wakeup IRQ enable + 0x2880 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_WAKEUP_ENABLE_ENABLE1 + CPU0 wakeup IRQ enable + 0x2884 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_WAKEUP_ENABLE_ENABLE2 + CPU0 wakeup IRQ enable + 0x2888 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU0_WAKEUP_ENABLE_ENABLE3 + CPU0 wakeup IRQ enable + 0x288c + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU1_LP + CPU1 LP control + 0x2c00 + 32 + 0x00001000 + 0xFF013703 + + + WAKE_CNT + CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + 24 + 8 + read-write + + + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 + 1 + read-write + + + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 + 1 + read-only + + + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 + 1 + read-only + + + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wake up happened + 10 + 1 + read-write + + + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 + 1 + read-write + + + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 reset not happened +1: CPU0 reset happened + 8 + 1 + read-write + + + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved + 0 + 2 + read-write + + + + + CPU_CPU1_LOCK + CPU1 Lock GPR + 0x2c04 + 32 + 0x00000002 + 0x0000FFFE + + + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 + read-write + + + LOCK + Lock bit for CPU_LOCK + 1 + 1 + read-write + + + + + CPU_CPU1_GPR_GPR0 + CPU1 GPR0 + 0x2c08 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR1 + CPU1 GPR1 + 0x2c0c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR2 + CPU1 GPR2 + 0x2c10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR3 + CPU1 GPR3 + 0x2c14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR4 + CPU1 GPR4 + 0x2c18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR5 + CPU1 GPR5 + 0x2c1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR6 + CPU1 GPR6 + 0x2c20 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR7 + CPU1 GPR7 + 0x2c24 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR8 + CPU1 GPR8 + 0x2c28 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR9 + CPU1 GPR9 + 0x2c2c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR10 + CPU1 GPR10 + 0x2c30 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR11 + CPU1 GPR11 + 0x2c34 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR12 + CPU1 GPR12 + 0x2c38 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_GPR_GPR13 + CPU1 GPR13 + 0x2c3c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + CPU_CPU1_WAKEUP_STATUS_STATUS0 + CPU1 wakeup IRQ status + 0x2c40 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU1_WAKEUP_STATUS_STATUS1 + CPU1 wakeup IRQ status + 0x2c44 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU1_WAKEUP_STATUS_STATUS2 + CPU1 wakeup IRQ status + 0x2c48 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU1_WAKEUP_STATUS_STATUS3 + CPU1 wakeup IRQ status + 0x2c4c + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + CPU_CPU1_WAKEUP_ENABLE_ENABLE0 + CPU1 wakeup IRQ enable + 0x2c80 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU1_WAKEUP_ENABLE_ENABLE1 + CPU1 wakeup IRQ enable + 0x2c84 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU1_WAKEUP_ENABLE_ENABLE2 + CPU1 wakeup IRQ enable + 0x2c88 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + CPU_CPU1_WAKEUP_ENABLE_ENABLE3 + CPU1 wakeup IRQ enable + 0x2c8c + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + + + IOC + IOC + IOC + 0xf4040000 + + 0x0 + 0xf40 + registers + + + + PAD_PA00_FUNC_CTL + ALT SELECT + 0x0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA00_PAD_CTL + PAD SETTINGS + 0x4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA01_FUNC_CTL + ALT SELECT + 0x8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA01_PAD_CTL + PAD SETTINGS + 0xc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA02_FUNC_CTL + ALT SELECT + 0x10 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA02_PAD_CTL + PAD SETTINGS + 0x14 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA03_FUNC_CTL + ALT SELECT + 0x18 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA03_PAD_CTL + PAD SETTINGS + 0x1c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA04_FUNC_CTL + ALT SELECT + 0x20 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA04_PAD_CTL + PAD SETTINGS + 0x24 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA05_FUNC_CTL + ALT SELECT + 0x28 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA05_PAD_CTL + PAD SETTINGS + 0x2c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA06_FUNC_CTL + ALT SELECT + 0x30 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA06_PAD_CTL + PAD SETTINGS + 0x34 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA07_FUNC_CTL + ALT SELECT + 0x38 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA07_PAD_CTL + PAD SETTINGS + 0x3c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA08_FUNC_CTL + ALT SELECT + 0x40 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA08_PAD_CTL + PAD SETTINGS + 0x44 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA09_FUNC_CTL + ALT SELECT + 0x48 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA09_PAD_CTL + PAD SETTINGS + 0x4c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA10_FUNC_CTL + ALT SELECT + 0x50 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA10_PAD_CTL + PAD SETTINGS + 0x54 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA11_FUNC_CTL + ALT SELECT + 0x58 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA11_PAD_CTL + PAD SETTINGS + 0x5c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA12_FUNC_CTL + ALT SELECT + 0x60 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA12_PAD_CTL + PAD SETTINGS + 0x64 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA13_FUNC_CTL + ALT SELECT + 0x68 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA13_PAD_CTL + PAD SETTINGS + 0x6c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA14_FUNC_CTL + ALT SELECT + 0x70 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA14_PAD_CTL + PAD SETTINGS + 0x74 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA15_FUNC_CTL + ALT SELECT + 0x78 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA15_PAD_CTL + PAD SETTINGS + 0x7c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA16_FUNC_CTL + ALT SELECT + 0x80 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA16_PAD_CTL + PAD SETTINGS + 0x84 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA17_FUNC_CTL + ALT SELECT + 0x88 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA17_PAD_CTL + PAD SETTINGS + 0x8c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA18_FUNC_CTL + ALT SELECT + 0x90 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA18_PAD_CTL + PAD SETTINGS + 0x94 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA19_FUNC_CTL + ALT SELECT + 0x98 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA19_PAD_CTL + PAD SETTINGS + 0x9c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA20_FUNC_CTL + ALT SELECT + 0xa0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA20_PAD_CTL + PAD SETTINGS + 0xa4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA21_FUNC_CTL + ALT SELECT + 0xa8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA21_PAD_CTL + PAD SETTINGS + 0xac + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA22_FUNC_CTL + ALT SELECT + 0xb0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA22_PAD_CTL + PAD SETTINGS + 0xb4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA23_FUNC_CTL + ALT SELECT + 0xb8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA23_PAD_CTL + PAD SETTINGS + 0xbc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA24_FUNC_CTL + ALT SELECT + 0xc0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA24_PAD_CTL + PAD SETTINGS + 0xc4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA25_FUNC_CTL + ALT SELECT + 0xc8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA25_PAD_CTL + PAD SETTINGS + 0xcc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA26_FUNC_CTL + ALT SELECT + 0xd0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA26_PAD_CTL + PAD SETTINGS + 0xd4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA27_FUNC_CTL + ALT SELECT + 0xd8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA27_PAD_CTL + PAD SETTINGS + 0xdc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA28_FUNC_CTL + ALT SELECT + 0xe0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA28_PAD_CTL + PAD SETTINGS + 0xe4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA29_FUNC_CTL + ALT SELECT + 0xe8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA29_PAD_CTL + PAD SETTINGS + 0xec + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA30_FUNC_CTL + ALT SELECT + 0xf0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA30_PAD_CTL + PAD SETTINGS + 0xf4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PA31_FUNC_CTL + ALT SELECT + 0xf8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PA31_PAD_CTL + PAD SETTINGS + 0xfc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB00_FUNC_CTL + ALT SELECT + 0x100 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB00_PAD_CTL + PAD SETTINGS + 0x104 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB01_FUNC_CTL + ALT SELECT + 0x108 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB01_PAD_CTL + PAD SETTINGS + 0x10c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB02_FUNC_CTL + ALT SELECT + 0x110 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB02_PAD_CTL + PAD SETTINGS + 0x114 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB03_FUNC_CTL + ALT SELECT + 0x118 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB03_PAD_CTL + PAD SETTINGS + 0x11c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB04_FUNC_CTL + ALT SELECT + 0x120 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB04_PAD_CTL + PAD SETTINGS + 0x124 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB05_FUNC_CTL + ALT SELECT + 0x128 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB05_PAD_CTL + PAD SETTINGS + 0x12c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB06_FUNC_CTL + ALT SELECT + 0x130 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB06_PAD_CTL + PAD SETTINGS + 0x134 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB07_FUNC_CTL + ALT SELECT + 0x138 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB07_PAD_CTL + PAD SETTINGS + 0x13c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB08_FUNC_CTL + ALT SELECT + 0x140 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB08_PAD_CTL + PAD SETTINGS + 0x144 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB09_FUNC_CTL + ALT SELECT + 0x148 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB09_PAD_CTL + PAD SETTINGS + 0x14c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB10_FUNC_CTL + ALT SELECT + 0x150 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB10_PAD_CTL + PAD SETTINGS + 0x154 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB11_FUNC_CTL + ALT SELECT + 0x158 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB11_PAD_CTL + PAD SETTINGS + 0x15c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB12_FUNC_CTL + ALT SELECT + 0x160 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB12_PAD_CTL + PAD SETTINGS + 0x164 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB13_FUNC_CTL + ALT SELECT + 0x168 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB13_PAD_CTL + PAD SETTINGS + 0x16c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB14_FUNC_CTL + ALT SELECT + 0x170 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB14_PAD_CTL + PAD SETTINGS + 0x174 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB15_FUNC_CTL + ALT SELECT + 0x178 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB15_PAD_CTL + PAD SETTINGS + 0x17c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB16_FUNC_CTL + ALT SELECT + 0x180 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB16_PAD_CTL + PAD SETTINGS + 0x184 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB17_FUNC_CTL + ALT SELECT + 0x188 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB17_PAD_CTL + PAD SETTINGS + 0x18c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB18_FUNC_CTL + ALT SELECT + 0x190 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB18_PAD_CTL + PAD SETTINGS + 0x194 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB19_FUNC_CTL + ALT SELECT + 0x198 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB19_PAD_CTL + PAD SETTINGS + 0x19c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB20_FUNC_CTL + ALT SELECT + 0x1a0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB20_PAD_CTL + PAD SETTINGS + 0x1a4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB21_FUNC_CTL + ALT SELECT + 0x1a8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB21_PAD_CTL + PAD SETTINGS + 0x1ac + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB22_FUNC_CTL + ALT SELECT + 0x1b0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB22_PAD_CTL + PAD SETTINGS + 0x1b4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB23_FUNC_CTL + ALT SELECT + 0x1b8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB23_PAD_CTL + PAD SETTINGS + 0x1bc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB24_FUNC_CTL + ALT SELECT + 0x1c0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB24_PAD_CTL + PAD SETTINGS + 0x1c4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB25_FUNC_CTL + ALT SELECT + 0x1c8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB25_PAD_CTL + PAD SETTINGS + 0x1cc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB26_FUNC_CTL + ALT SELECT + 0x1d0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB26_PAD_CTL + PAD SETTINGS + 0x1d4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB27_FUNC_CTL + ALT SELECT + 0x1d8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB27_PAD_CTL + PAD SETTINGS + 0x1dc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB28_FUNC_CTL + ALT SELECT + 0x1e0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB28_PAD_CTL + PAD SETTINGS + 0x1e4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB29_FUNC_CTL + ALT SELECT + 0x1e8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB29_PAD_CTL + PAD SETTINGS + 0x1ec + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB30_FUNC_CTL + ALT SELECT + 0x1f0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB30_PAD_CTL + PAD SETTINGS + 0x1f4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PB31_FUNC_CTL + ALT SELECT + 0x1f8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PB31_PAD_CTL + PAD SETTINGS + 0x1fc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC00_FUNC_CTL + ALT SELECT + 0x200 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC00_PAD_CTL + PAD SETTINGS + 0x204 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC01_FUNC_CTL + ALT SELECT + 0x208 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC01_PAD_CTL + PAD SETTINGS + 0x20c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC02_FUNC_CTL + ALT SELECT + 0x210 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC02_PAD_CTL + PAD SETTINGS + 0x214 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC03_FUNC_CTL + ALT SELECT + 0x218 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC03_PAD_CTL + PAD SETTINGS + 0x21c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC04_FUNC_CTL + ALT SELECT + 0x220 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC04_PAD_CTL + PAD SETTINGS + 0x224 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC05_FUNC_CTL + ALT SELECT + 0x228 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC05_PAD_CTL + PAD SETTINGS + 0x22c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC06_FUNC_CTL + ALT SELECT + 0x230 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC06_PAD_CTL + PAD SETTINGS + 0x234 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC07_FUNC_CTL + ALT SELECT + 0x238 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC07_PAD_CTL + PAD SETTINGS + 0x23c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC08_FUNC_CTL + ALT SELECT + 0x240 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC08_PAD_CTL + PAD SETTINGS + 0x244 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC09_FUNC_CTL + ALT SELECT + 0x248 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC09_PAD_CTL + PAD SETTINGS + 0x24c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC10_FUNC_CTL + ALT SELECT + 0x250 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC10_PAD_CTL + PAD SETTINGS + 0x254 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC11_FUNC_CTL + ALT SELECT + 0x258 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC11_PAD_CTL + PAD SETTINGS + 0x25c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC12_FUNC_CTL + ALT SELECT + 0x260 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC12_PAD_CTL + PAD SETTINGS + 0x264 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC13_FUNC_CTL + ALT SELECT + 0x268 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC13_PAD_CTL + PAD SETTINGS + 0x26c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC14_FUNC_CTL + ALT SELECT + 0x270 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC14_PAD_CTL + PAD SETTINGS + 0x274 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC15_FUNC_CTL + ALT SELECT + 0x278 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC15_PAD_CTL + PAD SETTINGS + 0x27c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC16_FUNC_CTL + ALT SELECT + 0x280 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC16_PAD_CTL + PAD SETTINGS + 0x284 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC17_FUNC_CTL + ALT SELECT + 0x288 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC17_PAD_CTL + PAD SETTINGS + 0x28c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC18_FUNC_CTL + ALT SELECT + 0x290 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC18_PAD_CTL + PAD SETTINGS + 0x294 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC19_FUNC_CTL + ALT SELECT + 0x298 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC19_PAD_CTL + PAD SETTINGS + 0x29c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC20_FUNC_CTL + ALT SELECT + 0x2a0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC20_PAD_CTL + PAD SETTINGS + 0x2a4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC21_FUNC_CTL + ALT SELECT + 0x2a8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC21_PAD_CTL + PAD SETTINGS + 0x2ac + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC22_FUNC_CTL + ALT SELECT + 0x2b0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC22_PAD_CTL + PAD SETTINGS + 0x2b4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC23_FUNC_CTL + ALT SELECT + 0x2b8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC23_PAD_CTL + PAD SETTINGS + 0x2bc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC24_FUNC_CTL + ALT SELECT + 0x2c0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC24_PAD_CTL + PAD SETTINGS + 0x2c4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC25_FUNC_CTL + ALT SELECT + 0x2c8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC25_PAD_CTL + PAD SETTINGS + 0x2cc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC26_FUNC_CTL + ALT SELECT + 0x2d0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC26_PAD_CTL + PAD SETTINGS + 0x2d4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PC27_FUNC_CTL + ALT SELECT + 0x2d8 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PC27_PAD_CTL + PAD SETTINGS + 0x2dc + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX00_FUNC_CTL + ALT SELECT + 0xd00 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX00_PAD_CTL + PAD SETTINGS + 0xd04 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX01_FUNC_CTL + ALT SELECT + 0xd08 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX01_PAD_CTL + PAD SETTINGS + 0xd0c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX02_FUNC_CTL + ALT SELECT + 0xd10 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX02_PAD_CTL + PAD SETTINGS + 0xd14 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX03_FUNC_CTL + ALT SELECT + 0xd18 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX03_PAD_CTL + PAD SETTINGS + 0xd1c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX04_FUNC_CTL + ALT SELECT + 0xd20 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX04_PAD_CTL + PAD SETTINGS + 0xd24 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX05_FUNC_CTL + ALT SELECT + 0xd28 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX05_PAD_CTL + PAD SETTINGS + 0xd2c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX06_FUNC_CTL + ALT SELECT + 0xd30 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX06_PAD_CTL + PAD SETTINGS + 0xd34 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PX07_FUNC_CTL + ALT SELECT + 0xd38 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PX07_PAD_CTL + PAD SETTINGS + 0xd3c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY00_FUNC_CTL + ALT SELECT + 0xe00 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY00_PAD_CTL + PAD SETTINGS + 0xe04 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY01_FUNC_CTL + ALT SELECT + 0xe08 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY01_PAD_CTL + PAD SETTINGS + 0xe0c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY02_FUNC_CTL + ALT SELECT + 0xe10 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY02_PAD_CTL + PAD SETTINGS + 0xe14 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY03_FUNC_CTL + ALT SELECT + 0xe18 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY03_PAD_CTL + PAD SETTINGS + 0xe1c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY04_FUNC_CTL + ALT SELECT + 0xe20 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY04_PAD_CTL + PAD SETTINGS + 0xe24 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY05_FUNC_CTL + ALT SELECT + 0xe28 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY05_PAD_CTL + PAD SETTINGS + 0xe2c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY06_FUNC_CTL + ALT SELECT + 0xe30 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY06_PAD_CTL + PAD SETTINGS + 0xe34 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PY07_FUNC_CTL + ALT SELECT + 0xe38 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PY07_PAD_CTL + PAD SETTINGS + 0xe3c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ00_FUNC_CTL + ALT SELECT + 0xf00 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ00_PAD_CTL + PAD SETTINGS + 0xf04 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ01_FUNC_CTL + ALT SELECT + 0xf08 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ01_PAD_CTL + PAD SETTINGS + 0xf0c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ02_FUNC_CTL + ALT SELECT + 0xf10 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ02_PAD_CTL + PAD SETTINGS + 0xf14 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ03_FUNC_CTL + ALT SELECT + 0xf18 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ03_PAD_CTL + PAD SETTINGS + 0xf1c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ04_FUNC_CTL + ALT SELECT + 0xf20 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ04_PAD_CTL + PAD SETTINGS + 0xf24 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ05_FUNC_CTL + ALT SELECT + 0xf28 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ05_PAD_CTL + PAD SETTINGS + 0xf2c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ06_FUNC_CTL + ALT SELECT + 0xf30 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ06_PAD_CTL + PAD SETTINGS + 0xf34 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + PAD_PZ07_FUNC_CTL + ALT SELECT + 0xf38 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +… +31:ALT31 + 0 + 5 + read-write + + + + + PAD_PZ07_PAD_CTL + PAD SETTINGS + 0xf3c + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + + + PIOC + PIOC + IOC + 0xf40d8000 + + + BIOC + BIOC + IOC + 0xf5010000 + + + OTPSHW + OTPSHW + OTP + 0xf4080000 + + 0x0 + 0xc08 + registers + + + + SHADOW_SHADOW000 + Fuse shadow registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW001 + Fuse shadow registers + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW002 + Fuse shadow registers + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW003 + Fuse shadow registers + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW004 + Fuse shadow registers + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW005 + Fuse shadow registers + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW006 + Fuse shadow registers + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW007 + Fuse shadow registers + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW008 + Fuse shadow registers + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW009 + Fuse shadow registers + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW010 + Fuse shadow registers + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW011 + Fuse shadow registers + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW012 + Fuse shadow registers + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW013 + Fuse shadow registers + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW014 + Fuse shadow registers + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW015 + Fuse shadow registers + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW016 + Fuse shadow registers + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW017 + Fuse shadow registers + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW018 + Fuse shadow registers + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW019 + Fuse shadow registers + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW020 + Fuse shadow registers + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW021 + Fuse shadow registers + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW022 + Fuse shadow registers + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW023 + Fuse shadow registers + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW024 + Fuse shadow registers + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW025 + Fuse shadow registers + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW026 + Fuse shadow registers + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW027 + Fuse shadow registers + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW028 + Fuse shadow registers + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW029 + Fuse shadow registers + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW030 + Fuse shadow registers + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW031 + Fuse shadow registers + 0x7c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW032 + Fuse shadow registers + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW033 + Fuse shadow registers + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW034 + Fuse shadow registers + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW035 + Fuse shadow registers + 0x8c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW036 + Fuse shadow registers + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW037 + Fuse shadow registers + 0x94 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW038 + Fuse shadow registers + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW039 + Fuse shadow registers + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW040 + Fuse shadow registers + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW041 + Fuse shadow registers + 0xa4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW042 + Fuse shadow registers + 0xa8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW043 + Fuse shadow registers + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW044 + Fuse shadow registers + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW045 + Fuse shadow registers + 0xb4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW046 + Fuse shadow registers + 0xb8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW047 + Fuse shadow registers + 0xbc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW048 + Fuse shadow registers + 0xc0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW049 + Fuse shadow registers + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW050 + Fuse shadow registers + 0xc8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW051 + Fuse shadow registers + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW052 + Fuse shadow registers + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW053 + Fuse shadow registers + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW054 + Fuse shadow registers + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW055 + Fuse shadow registers + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW056 + Fuse shadow registers + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW057 + Fuse shadow registers + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW058 + Fuse shadow registers + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW059 + Fuse shadow registers + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW060 + Fuse shadow registers + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW061 + Fuse shadow registers + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW062 + Fuse shadow registers + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW063 + Fuse shadow registers + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW064 + Fuse shadow registers + 0x100 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW065 + Fuse shadow registers + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW066 + Fuse shadow registers + 0x108 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW067 + Fuse shadow registers + 0x10c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW068 + Fuse shadow registers + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW069 + Fuse shadow registers + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW070 + Fuse shadow registers + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW071 + Fuse shadow registers + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW072 + Fuse shadow registers + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW073 + Fuse shadow registers + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW074 + Fuse shadow registers + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW075 + Fuse shadow registers + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW076 + Fuse shadow registers + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW077 + Fuse shadow registers + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW078 + Fuse shadow registers + 0x138 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW079 + Fuse shadow registers + 0x13c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW080 + Fuse shadow registers + 0x140 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW081 + Fuse shadow registers + 0x144 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW082 + Fuse shadow registers + 0x148 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW083 + Fuse shadow registers + 0x14c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW084 + Fuse shadow registers + 0x150 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW085 + Fuse shadow registers + 0x154 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW086 + Fuse shadow registers + 0x158 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW087 + Fuse shadow registers + 0x15c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW088 + Fuse shadow registers + 0x160 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW089 + Fuse shadow registers + 0x164 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW090 + Fuse shadow registers + 0x168 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW091 + Fuse shadow registers + 0x16c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW092 + Fuse shadow registers + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW093 + Fuse shadow registers + 0x174 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW094 + Fuse shadow registers + 0x178 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW095 + Fuse shadow registers + 0x17c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW096 + Fuse shadow registers + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW097 + Fuse shadow registers + 0x184 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW098 + Fuse shadow registers + 0x188 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW099 + Fuse shadow registers + 0x18c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW100 + Fuse shadow registers + 0x190 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW101 + Fuse shadow registers + 0x194 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW102 + Fuse shadow registers + 0x198 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW103 + Fuse shadow registers + 0x19c + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW104 + Fuse shadow registers + 0x1a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW105 + Fuse shadow registers + 0x1a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW106 + Fuse shadow registers + 0x1a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW107 + Fuse shadow registers + 0x1ac + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW108 + Fuse shadow registers + 0x1b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW109 + Fuse shadow registers + 0x1b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW110 + Fuse shadow registers + 0x1b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW111 + Fuse shadow registers + 0x1bc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW112 + Fuse shadow registers + 0x1c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW113 + Fuse shadow registers + 0x1c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW114 + Fuse shadow registers + 0x1c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW115 + Fuse shadow registers + 0x1cc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW116 + Fuse shadow registers + 0x1d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW117 + Fuse shadow registers + 0x1d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW118 + Fuse shadow registers + 0x1d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW119 + Fuse shadow registers + 0x1dc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW120 + Fuse shadow registers + 0x1e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW121 + Fuse shadow registers + 0x1e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW122 + Fuse shadow registers + 0x1e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW123 + Fuse shadow registers + 0x1ec + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW124 + Fuse shadow registers + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW125 + Fuse shadow registers + 0x1f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW126 + Fuse shadow registers + 0x1f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_SHADOW127 + Fuse shadow registers + 0x1fc + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK00 + Fuse shadow lock + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK01 + Fuse shadow lock + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK02 + Fuse shadow lock + 0x208 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK03 + Fuse shadow lock + 0x20c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK04 + Fuse shadow lock + 0x210 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK05 + Fuse shadow lock + 0x214 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK06 + Fuse shadow lock + 0x218 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + SHADOW_LOCK_LOCK07 + Fuse shadow lock + 0x21c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_FUSE000 + Fuse Array + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE001 + Fuse Array + 0x404 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE002 + Fuse Array + 0x408 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE003 + Fuse Array + 0x40c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE004 + Fuse Array + 0x410 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE005 + Fuse Array + 0x414 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE006 + Fuse Array + 0x418 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE007 + Fuse Array + 0x41c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE008 + Fuse Array + 0x420 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE009 + Fuse Array + 0x424 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE010 + Fuse Array + 0x428 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE011 + Fuse Array + 0x42c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE012 + Fuse Array + 0x430 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE013 + Fuse Array + 0x434 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE014 + Fuse Array + 0x438 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE015 + Fuse Array + 0x43c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE016 + Fuse Array + 0x440 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE017 + Fuse Array + 0x444 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE018 + Fuse Array + 0x448 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE019 + Fuse Array + 0x44c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE020 + Fuse Array + 0x450 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE021 + Fuse Array + 0x454 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE022 + Fuse Array + 0x458 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE023 + Fuse Array + 0x45c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE024 + Fuse Array + 0x460 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE025 + Fuse Array + 0x464 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE026 + Fuse Array + 0x468 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE027 + Fuse Array + 0x46c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE028 + Fuse Array + 0x470 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE029 + Fuse Array + 0x474 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE030 + Fuse Array + 0x478 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE031 + Fuse Array + 0x47c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE032 + Fuse Array + 0x480 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE033 + Fuse Array + 0x484 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE034 + Fuse Array + 0x488 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE035 + Fuse Array + 0x48c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE036 + Fuse Array + 0x490 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE037 + Fuse Array + 0x494 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE038 + Fuse Array + 0x498 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE039 + Fuse Array + 0x49c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE040 + Fuse Array + 0x4a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE041 + Fuse Array + 0x4a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE042 + Fuse Array + 0x4a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE043 + Fuse Array + 0x4ac + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE044 + Fuse Array + 0x4b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE045 + Fuse Array + 0x4b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE046 + Fuse Array + 0x4b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE047 + Fuse Array + 0x4bc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE048 + Fuse Array + 0x4c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE049 + Fuse Array + 0x4c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE050 + Fuse Array + 0x4c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE051 + Fuse Array + 0x4cc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE052 + Fuse Array + 0x4d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE053 + Fuse Array + 0x4d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE054 + Fuse Array + 0x4d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE055 + Fuse Array + 0x4dc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE056 + Fuse Array + 0x4e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE057 + Fuse Array + 0x4e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE058 + Fuse Array + 0x4e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE059 + Fuse Array + 0x4ec + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE060 + Fuse Array + 0x4f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE061 + Fuse Array + 0x4f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE062 + Fuse Array + 0x4f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE063 + Fuse Array + 0x4fc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE064 + Fuse Array + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE065 + Fuse Array + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE066 + Fuse Array + 0x508 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE067 + Fuse Array + 0x50c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE068 + Fuse Array + 0x510 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE069 + Fuse Array + 0x514 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE070 + Fuse Array + 0x518 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE071 + Fuse Array + 0x51c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE072 + Fuse Array + 0x520 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE073 + Fuse Array + 0x524 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE074 + Fuse Array + 0x528 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE075 + Fuse Array + 0x52c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE076 + Fuse Array + 0x530 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE077 + Fuse Array + 0x534 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE078 + Fuse Array + 0x538 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE079 + Fuse Array + 0x53c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE080 + Fuse Array + 0x540 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE081 + Fuse Array + 0x544 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE082 + Fuse Array + 0x548 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE083 + Fuse Array + 0x54c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE084 + Fuse Array + 0x550 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE085 + Fuse Array + 0x554 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE086 + Fuse Array + 0x558 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE087 + Fuse Array + 0x55c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE088 + Fuse Array + 0x560 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE089 + Fuse Array + 0x564 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE090 + Fuse Array + 0x568 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE091 + Fuse Array + 0x56c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE092 + Fuse Array + 0x570 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE093 + Fuse Array + 0x574 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE094 + Fuse Array + 0x578 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE095 + Fuse Array + 0x57c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE096 + Fuse Array + 0x580 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE097 + Fuse Array + 0x584 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE098 + Fuse Array + 0x588 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE099 + Fuse Array + 0x58c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE100 + Fuse Array + 0x590 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE101 + Fuse Array + 0x594 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE102 + Fuse Array + 0x598 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE103 + Fuse Array + 0x59c + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE104 + Fuse Array + 0x5a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE105 + Fuse Array + 0x5a4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE106 + Fuse Array + 0x5a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE107 + Fuse Array + 0x5ac + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE108 + Fuse Array + 0x5b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE109 + Fuse Array + 0x5b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE110 + Fuse Array + 0x5b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE111 + Fuse Array + 0x5bc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE112 + Fuse Array + 0x5c0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE113 + Fuse Array + 0x5c4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE114 + Fuse Array + 0x5c8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE115 + Fuse Array + 0x5cc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE116 + Fuse Array + 0x5d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE117 + Fuse Array + 0x5d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE118 + Fuse Array + 0x5d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE119 + Fuse Array + 0x5dc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE120 + Fuse Array + 0x5e0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE121 + Fuse Array + 0x5e4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE122 + Fuse Array + 0x5e8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE123 + Fuse Array + 0x5ec + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE124 + Fuse Array + 0x5f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE125 + Fuse Array + 0x5f4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE126 + Fuse Array + 0x5f8 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_FUSE127 + Fuse Array + 0x5fc + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK00 + Fuse lock + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK01 + Fuse lock + 0x604 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK02 + Fuse lock + 0x608 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK03 + Fuse lock + 0x60c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK04 + Fuse lock + 0x610 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK05 + Fuse lock + 0x614 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK06 + Fuse lock + 0x618 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + FUSE_LOCK_LOCK07 + Fuse lock + 0x61c + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + UNLOCK + UNLOCK + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + UNLOCK + unlock word for fuse array operation +write "OPEN" to unlock fuse array, write any other value will lock write to fuse. +Please make sure 24M crystal is running and 2.5V LDO working properly + 0 + 32 + read-write + + + + + DATA + DATA + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data register for non-blocking access +this register hold dat read from fuse array or data to by programmed to fuse array + 0 + 32 + read-write + + + + + ADDR + ADDR + 0x808 + 32 + 0x00000000 + 0x0000007F + + + ADDR + word address to be read or write + 0 + 7 + read-write + + + + + CMD + CMD + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + command to access fure array +"BLOW" will update fuse word at ADDR to value hold in DATA +"READ" will fetch fuse value in at ADDR to DATA register + 0 + 32 + read-write + + + + + LOAD_REQ + LOAD Request + 0xa00 + 32 + 0x00000007 + 0x0000000F + + + REQUEST + reload request for 4 regions +bit0: region0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + LOAD_COMP + LOAD complete + 0xa04 + 32 + 0x00000007 + 0x0000000F + + + COMPLETE + reload complete sign for 4 regions +bit0: region 0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + REGION_LOAD_REGION0 + LOAD region + 0xa20 + 32 + 0x00000800 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + REGION_LOAD_REGION1 + LOAD region + 0xa24 + 32 + 0x00001008 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + REGION_LOAD_REGION2 + LOAD region + 0xa28 + 32 + 0x00000010 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + REGION_LOAD_REGION3 + LOAD region + 0xa2c + 32 + 0x00000000 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + INT_FLAG + interrupt flag + 0xc00 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write flag, write 1 to clear +0: fuse is not written or writing +1: value in DATA register is programmed into fuse + 2 + 1 + read-write + + + READ + fuse read flag, write 1 to clear +0: fuse is not read or reading +1: fuse value is put in DATA register + 1 + 1 + read-write + + + LOAD + fuse load flag, write 1 to clear +0: fuse is not loaded or loading +1: fuse loaded + 0 + 1 + read-write + + + + + INT_EN + interrupt enable + 0xc04 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write interrupt enable +0: fuse write interrupt is not enable +1: fuse write interrupt is enable + 2 + 1 + read-write + + + READ + fuse read interrupt enable +0: fuse read interrupt is not enable +1: fuse read interrupt is enable + 1 + 1 + read-write + + + LOAD + fuse load interrupt enable +0: fuse load interrupt is not enable +1: fuse load interrupt is enable + 0 + 1 + read-write + + + + + + + OTP + OTP + OTP + 0xf40c8000 + + + PPOR + PPOR + PPOR + 0xf40c0000 + + 0x0 + 0x20 + registers + + + + RESET_FLAG + flag indicate reset source + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + reset reason of last hard reset, write 1 to clear each bit +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + write-only + + + + + RESET_STATUS + reset source status + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + current status of reset sources +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_HOLD + reset hold attribute + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_ENABLE + reset source enable + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + enable of reset sources +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_HOT + reset type triggered by reset + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TYPE + reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + RESET_COLD + reset type attribute + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected +0: brownout +1: temperature(not available) +2: resetpin(not available) +4: debug reset +5: jtag reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2 +19: watch dog 3 +20: pmic watch dog +31: software + 0 + 32 + read-write + + + + + SOFTWARE_RESET + Software reset counter + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + 0 + 32 + read-write + + + + + + + PCFG + PCFG + PMU + 0xf40c4000 + + 0x0 + 0x70 + registers + + + + BANDGAP + BANGGAP control + 0x0 + 32 + 0x00101010 + 0x831F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + LOWPOWER_MODE + Banggap work in low power mode, banggap function limited +0: banggap works in normal mode +1: banggap works in low power mode + 25 + 1 + read-write + + + POWER_SAVE + Banggap work in power save mode, banggap function normally +0: banggap works in high performance mode +1: banggap works in power saving mode + 24 + 1 + read-write + + + VBG_1P0_TRIM + Banggap 1.0V output trim value + 16 + 5 + read-write + + + VBG_P65_TRIM + Banggap 1.0V output trim value + 8 + 5 + read-write + + + VBG_P50_TRIM + Banggap 1.0V output trim value + 0 + 5 + read-write + + + + + LDO1P1 + 1V LDO config + 0x4 + 32 + 0x0001044C + 0x00010FFF + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. +700: 700mV +720: 720mV +. . . +1320:1320mV + 0 + 12 + read-write + + + + + LDO2P5 + 2.5V LDO config + 0x8 + 32 + 0x000009C4 + 0x10010FFF + + + READY + Ready flag, will set 1ms after enabled or voltage change +0: LDO is not ready for use +1: LDO is ready + 28 + 1 + read-only + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. +2125: 2125mV +2150: 2150mV +. . . +2900:2900mV + 0 + 12 + read-write + + + + + DCDC_MODE + DCDC mode select + 0x10 + 32 + 0x0001047E + 0x10070FFF + + + READY + Ready flag +0: DCDC is applying new change +1: DCDC is ready + 28 + 1 + read-only + + + MODE + DCDC work mode +XX0: trun off +001: basic mode +011: generic mode +101: automatic mode +111: expert mode + 16 + 3 + read-write + + + VOLT + DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_LPMODE + DCDC low power mode + 0x14 + 32 + 0x00000384 + 0x00000FFF + + + STBY_VOLT + DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_PROT + DCDC protection + 0x18 + 32 + 0x00000010 + 0x11818191 + + + ILIMIT_LP + over current setting for low power mode +0:250mA +1:200mA + 28 + 1 + read-write + + + OVERLOAD_LP + over current in low power mode +0: current is below setting +1: overcurrent happened in low power mode + 24 + 1 + read-write + + + DISABLE_POWER_LOSS + disable power loss protection +0: power loss protection enabled, DCDC shuts down when power loss +1: power loss protection disabled, DCDC try working after power voltage drop + 23 + 1 + read-write + + + POWER_LOSS_FLAG + power loss +0: input power is good +1: input power is too low + 16 + 1 + read-only + + + DISABLE_OVERVOLTAGE + ouput over voltage protection +0: protection enabled, DCDC will shut down is output voltage is unexpected high +1: protection disabled, DCDC continue to adjust output voltage + 15 + 1 + read-write + + + OVERVOLT_FLAG + output over voltage flag +0: output is normal +1: output is unexpected high + 8 + 1 + read-only + + + DISABLE_SHORT + disable output short circuit protection +0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected +1: short circuit protection disabled + 7 + 1 + read-write + + + SHORT_CURRENT + short circuit current setting +0: 2.0A, +1: 1.3A + 4 + 1 + read-write + + + SHORT_FLAG + short circuit flag +0: current is within limit +1: short circuits detected + 0 + 1 + read-only + + + + + DCDC_CURRENT + DCDC current estimation + 0x1c + 32 + 0x00000000 + 0x0000811F + + + ESTI_EN + enable current measure + 15 + 1 + read-write + + + VALID + Current level valid +0: data is invalid +1: data is valid + 8 + 1 + read-only + + + LEVEL + DCDC current level, current level is num * 50mA + 0 + 5 + read-only + + + + + DCDC_ADVMODE + DCDC advance setting + 0x20 + 32 + 0x03120040 + 0x073F007F + + + EN_RCSCALE + Enable RC scale + 24 + 3 + read-write + + + DC_C + Loop C number + 20 + 2 + read-write + + + DC_R + Loop R number + 16 + 4 + read-write + + + EN_FF_DET + enable feed forward detect +0: feed forward detect is disabled +1: feed forward detect is enabled + 6 + 1 + read-write + + + EN_FF_LOOP + enable feed forward loop +0: feed forward loop is disabled +1: feed forward loop is enabled + 5 + 1 + read-write + + + EN_AUTOLP + enable auto enter low power mode +0: do not enter low power mode +1: enter low power mode if current is detected low + 4 + 1 + read-write + + + EN_DCM_EXIT + avoid over voltage +0: stay in DCM mode when voltage excess +1: change to CCM mode when voltage excess + 3 + 1 + read-write + + + EN_SKIP + enable skip on narrow pulse +0: do not skip narrow pulse +1: skip narrow pulse + 2 + 1 + read-write + + + EN_IDLE + enable skip when voltage is higher than threshold +0: do not skip +1: skip if voltage is excess + 1 + 1 + read-write + + + EN_DCM + DCM mode +0: CCM mode +1: DCM mode + 0 + 1 + read-write + + + + + DCDC_ADVPARAM + DCDC advance parameter + 0x24 + 32 + 0x00006E1C + 0x00007F7F + + + MIN_DUT + minimum duty cycle + 8 + 7 + read-write + + + MAX_DUT + maximum duty cycle + 0 + 7 + read-write + + + + + DCDC_MISC + DCDC misc parameter + 0x28 + 32 + 0x00070100 + 0x13170317 + + + EN_HYST + hysteres enable + 28 + 1 + read-write + + + HYST_SIGN + hysteres sign + 25 + 1 + read-write + + + HYST_THRS + hysteres threshold + 24 + 1 + read-write + + + RC_SCALE + Loop RC scale threshold + 20 + 1 + read-write + + + DC_FF + Loop feed forward number + 16 + 3 + read-write + + + OL_THRE + overload for threshold for lod power mode + 8 + 2 + read-write + + + OL_HYST + current hysteres range +0: 12.5mV +1: 25mV + 4 + 1 + read-write + + + DELAY + enable delay +0: delay disabled, +1: delay enabled + 2 + 1 + read-write + + + CLK_SEL + clock selection +0: select DCDC internal oscillator +1: select RC24M oscillator + 1 + 1 + read-write + + + EN_STEP + enable stepping in voltage change +0: stepping disabled, +1: steping enabled + 0 + 1 + read-write + + + + + DCDC_DEBUG + DCDC Debug + 0x2c + 32 + 0x00005DBF + 0x000FFFFF + + + UPDATE_TIME + DCDC voltage change time in 24M clock cycles, default value is 1mS + 0 + 20 + read-write + + + + + DCDC_START_TIME + DCDC ramp time + 0x30 + 32 + 0x0001193F + 0x000FFFFF + + + START_TIME + Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + 0 + 20 + read-write + + + + + DCDC_RESUME_TIME + DCDC resume time + 0x34 + 32 + 0x00008C9F + 0x000FFFFF + + + RESUME_TIME + Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + 0 + 20 + read-write + + + + + POWER_TRAP + SOC power trap + 0x40 + 32 + 0x00000000 + 0x80010001 + + + TRIGGERED + Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. +0: low power trap is not triggered +1: low power trap triggered + 31 + 1 + read-write + + + RETENTION + DCDC enter standby mode, which will reduce voltage for memory content retention +0: Shutdown DCDC +1: reduce DCDC voltage + 16 + 1 + read-write + + + TRAP + Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered +0: trap not enabled, pmic side low power function disabled +1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + 0 + 1 + read-write + + + + + WAKE_CAUSE + Wake up source + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAUSE + wake up cause, each bit represents one wake up source, write 1 to clear the register bit +0: wake up source is not active during last wakeup +1: wake up source is active furing last wakeup +bit 0: pmic_enable +bit 1: debug wakeup +bit 4: fuse interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit11: Security monitor interrupt +bit12: Security in PMIC event +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit18: BATT Button interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + WAKE_MASK + Wake up mask + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + MASK + mask for wake up sources, each bit represents one wakeup source +0: allow source to wake up system +1: disallow source to wakeup system +bit 0: pmic_enable +bit 1: debug wakeup +bit 4: fuse interrupt +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit11: Security monitor interrupt +bit12: Security in PMIC event +bit16: Security violation in BATT +bit17: GPIO in BATT interrupt +bit18: BATT Button interrupt +bit19: RTC alarm interrupt + 0 + 32 + read-write + + + + + SCG_CTRL + Clock gate control in PMIC + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + SCG + control whether clock being gated during PMIC low power flow, 2 bits for each peripheral +00,01: reserved +10: clock is always off +11: clock is always on +bit0-1: fuse +bit6-7:gpio +bit8-9:ioc +bit10-11: timer +bit12-13:wdog +bit14-15:uart +bit16-17:debug + 0 + 32 + read-write + + + + + DEBUG_STOP + Debug stop config + 0x50 + 32 + 0x00000001 + 0x00000003 + + + CPU1 + Stop peripheral when CPU1 enter debug mode +0: peripheral keep running when CPU1 in debug mode +1: peripheral enter debug mode when CPU1 enter debug + 1 + 1 + read-write + + + CPU0 + Stop peripheral when CPU0 enter debug mode +0: peripheral keep running when CPU0 in debug mode +1: peripheral enter debug mode when CPU0 enter debug + 0 + 1 + read-write + + + + + RC24M + RC 24M config + 0x60 + 32 + 0x00000310 + 0x8000071F + + + RC_TRIMMED + RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: RC is not trimmed +1: RC is trimmed + 31 + 1 + read-write + + + TRIM_C + Coarse trim for RC24M, bigger value means faster + 8 + 3 + read-write + + + TRIM_F + Fine trim for RC24M, bigger value means faster + 0 + 5 + read-write + + + + + RC24M_TRACK + RC 24M track mode + 0x64 + 32 + 0x00000000 + 0x00010011 + + + SEL24M + Select track reference +0: select 32K as reference +1: select 24M XTAL as reference + 16 + 1 + read-write + + + RETURN + Retrun default value when XTAL loss +0: remain last tracking value +1: switch to default value + 4 + 1 + read-write + + + TRACK + track mode +0: RC24M free running +1: track RC24M to external XTAL + 0 + 1 + read-write + + + + + TRACK_TARGET + RC 24M track target + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRE_DIV + Divider for reference source + 16 + 16 + read-write + + + TARGET + Target frequency multiplier of divided source + 0 + 16 + read-write + + + + + STATUS + RC 24M track status + 0x6c + 32 + 0x00000000 + 0x0011871F + + + SEL32K + track is using XTAL32K +0: track is not using XTAL32K +1: track is using XTAL32K + 20 + 1 + read-only + + + SEL24M + track is using XTAL24M +0: track is not using XTAL24M +1: track is using XTAL24M + 16 + 1 + read-only + + + EN_TRIM + default value takes effect +0: default value is invalid +1: default value is valid + 15 + 1 + read-only + + + TRIM_C + default coarse trim value + 8 + 3 + read-only + + + TRIM_F + default fine trim value + 0 + 5 + read-only + + + + + + + PSEC + PSEC + PSEC + 0xf40cc000 + + 0x0 + 0x18 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x000300F0 + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + PMIC_FAIL + PMIC secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 7 + 1 + read-write + + + PMIC_NSC + PMIC secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 6 + 1 + read-write + + + PMIC_SEC + PMIC secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 5 + 1 + read-write + + + PMIC_INS + PMIC secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 4 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF000C + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + PMIC_ESC_NSC + PMIC is escalating non-secure event + 3 + 1 + read-only + + + PMIC_ESC_SEC + PMIC is escalting secure event + 2 + 1 + read-only + + + + + LIFECYCLE + Lifecycle + 0x14 + 32 + 0x00000000 + 0x000000FF + + + LIFECYCLE + lifecycle status, +bit7: lifecycle_debate, +bit6: lifecycle_scribe, +bit5: lifecycle_no_ret, +bit4: lifecycle_return, +bit3: lifecycle_secure, +bit2: lifecycle_nonsec, +bit1: lifecycle_create, +bit0: lifecycle_unknow + 0 + 8 + read-only + + + + + + + PMON + PMON + PMON + 0xf40d0000 + + 0x0 + 0x48 + registers + + + + MONITOR_GLITCH0_CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_GLITCH0_STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + MONITOR_GLITCH1_CONTROL + Glitch and clock monitor control + 0x8 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_GLITCH1_STATUS + Glitch and clock monitor status + 0xc + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + MONITOR_CLOCK0_CONTROL + Glitch and clock monitor control + 0x10 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_CLOCK0_STATUS + Glitch and clock monitor status + 0x14 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + MONITOR_CLOCK1_CONTROL + Glitch and clock monitor control + 0x18 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_CLOCK1_STATUS + Glitch and clock monitor status + 0x1c + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + IRQ_FLAG + No description avaiable + 0x40 + 32 + 0x00000000 + 0x0000000F + + + FLAG + interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag +0: no monitor interrupt +1: monitor interrupt happened + 0 + 4 + read-write + + + + + IRQ_ENABLE + No description avaiable + 0x44 + 32 + 0x00000000 + 0x0000000F + + + ENABLE + interrupt enable, each bit represents for one monitor +0: monitor interrupt disabled +1: monitor interrupt enabled + 0 + 4 + read-write + + + + + + + PGPR + PGPR + PGPR + 0xf40d4000 + + 0x0 + 0x40 + registers + + + + PMIC_GPR00 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR01 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR02 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR03 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR04 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR05 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR06 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR07 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR08 + Generic control + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR09 + Generic control + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR10 + Generic control + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR11 + Generic control + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR12 + Generic control + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR13 + Generic control + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR14 + Generic control + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR15 + Generic control + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + PLLCTLV2 + PLLCTLV2 + PLLCTLV2 + 0xf4100000 + + 0x0 + 0x200 + registers + + + + XTAL + OSC configuration + 0x0 + 32 + 0x0001FFFF + 0xB00FFFFF + + + BUSY + Busy flag +0: Oscillator is working or shutdown +1: Oscillator is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + RAMP_TIME + Rampup time of XTAL oscillator in cycles of RC24M clock +0: 0 cycle +1: 1 cycle +2: 2 cycle +1048575: 1048575 cycles + 0 + 20 + read-write + + + + + PLL_PLL0_MFI + PLL0 multiple register + 0x80 + 32 + 0x00000010 + 0xB000007F + + + BUSY + Busy flag +0: PLL is stable or shutdown +1: PLL is changing status + 31 + 1 + read-only + + + RESPONSE + PLL status +0: PLL is not stable +1: PLL is stable for use + 29 + 1 + read-only + + + ENABLE + PLL enable status +0: PLL is off +1: PLL is on + 28 + 1 + read-only + + + MFI + loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) +0-15: invalid +16: divide by 16 +17: divide by17 +. . . +42: divide by 42 +43~:invalid + 0 + 7 + read-write + + + + + PLL_PLL0_MFN + PLL0 fraction numerator register + 0x84 + 32 + 0x09896800 + 0x3FFFFFFF + + + MFN + Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + 0 + 30 + read-write + + + + + PLL_PLL0_MFD + PLL0 fraction demoninator register + 0x88 + 32 + 0x0E4E1C00 + 0x3FFFFFFF + + + MFD + Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + 0 + 30 + read-write + + + + + PLL_PLL0_SS_STEP + PLL0 spread spectrum step register + 0x8c + 32 + 0x00000000 + 0x3FFFFFFF + + + STEP + Step of spread spectrum modulator. +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + PLL_PLL0_SS_STOP + PLL0 spread spectrum stop register + 0x90 + 32 + 0x00000000 + 0x3FFFFFFF + + + STOP + Stop point of spread spectrum modulator +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + PLL_PLL0_CONFIG + PLL0 confguration register + 0x94 + 32 + 0x00000000 + 0x00000101 + + + SPREAD + Enable spread spectrum function. This field supports changing during PLL running. + 8 + 1 + read-write + + + REFSEL + Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. +0: XTAL24M +1: IRC24M + 0 + 1 + read-write + + + + + PLL_PLL0_LOCKTIME + PLL0 lock time register + 0x98 + 32 + 0x000009C4 + 0x0000FFFF + + + LOCKTIME + Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + 0 + 16 + read-write + + + + + PLL_PLL0_STEPTIME + PLL0 step time register + 0x9c + 32 + 0x000009C4 + 0x0000FFFF + + + STEPTIME + Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + 0 + 16 + read-write + + + + + PLL_PLL0_ADVANCED + PLL0 advance configuration register + 0xa0 + 32 + 0x00000000 + 0x11000000 + + + SLOW + Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. +0: fast lock enabled, lock time is 100us +1: fast lock disabled, lock time is 400us + 28 + 1 + read-write + + + DITHER + Enable dither function + 24 + 1 + read-write + + + + + PLL_PLL0_DIV_DIV0 + PLL0 divider output 0 configuration register + 0xc0 + 32 + 0x00000000 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL0_DIV_DIV1 + PLL0 divider output 1 configuration register + 0xc4 + 32 + 0x00000000 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL0_DIV_DIV2 + PLL0 divider output 2 configuration register + 0xc8 + 32 + 0x00000000 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL1_MFI + PLL1 multiple register + 0x100 + 32 + 0x00000018 + 0xB000007F + + + BUSY + Busy flag +0: PLL is stable or shutdown +1: PLL is changing status + 31 + 1 + read-only + + + RESPONSE + PLL status +0: PLL is not stable +1: PLL is stable for use + 29 + 1 + read-only + + + ENABLE + PLL enable status +0: PLL is off +1: PLL is on + 28 + 1 + read-only + + + MFI + loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) +0-15: invalid +16: divide by 16 +17: divide by17 +. . . +42: divide by 42 +43~:invalid + 0 + 7 + read-write + + + + + PLL_PLL1_MFN + PLL1 fraction numerator register + 0x104 + 32 + 0x00000000 + 0x3FFFFFFF + + + MFN + Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + 0 + 30 + read-write + + + + + PLL_PLL1_MFD + PLL1 fraction demoninator register + 0x108 + 32 + 0x0E4E1C00 + 0x3FFFFFFF + + + MFD + Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + 0 + 30 + read-write + + + + + PLL_PLL1_SS_STEP + PLL1 spread spectrum step register + 0x10c + 32 + 0x00000000 + 0x3FFFFFFF + + + STEP + Step of spread spectrum modulator. +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + PLL_PLL1_SS_STOP + PLL1 spread spectrum stop register + 0x110 + 32 + 0x00000000 + 0x3FFFFFFF + + + STOP + Stop point of spread spectrum modulator +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + PLL_PLL1_CONFIG + PLL1 confguration register + 0x114 + 32 + 0x00000000 + 0x00000101 + + + SPREAD + Enable spread spectrum function. This field supports changing during PLL running. + 8 + 1 + read-write + + + REFSEL + Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. +0: XTAL24M +1: IRC24M + 0 + 1 + read-write + + + + + PLL_PLL1_LOCKTIME + PLL1 lock time register + 0x118 + 32 + 0x000009C4 + 0x0000FFFF + + + LOCKTIME + Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + 0 + 16 + read-write + + + + + PLL_PLL1_STEPTIME + PLL1 step time register + 0x11c + 32 + 0x000009C4 + 0x0000FFFF + + + STEPTIME + Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + 0 + 16 + read-write + + + + + PLL_PLL1_ADVANCED + PLL1 advance configuration register + 0x120 + 32 + 0x000009C4 + 0x11000000 + + + SLOW + Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. +0: fast lock enabled, lock time is 100us +1: fast lock disabled, lock time is 400us + 28 + 1 + read-write + + + DITHER + Enable dither function + 24 + 1 + read-write + + + + + PLL_PLL1_DIV_DIV0 + PLL1 divider output 0 configuration register + 0x140 + 32 + 0x00000001 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL1_DIV_DIV1 + PLL1 divider output 1 configuration register + 0x144 + 32 + 0x00000004 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL2_MFI + PLL2 multiple register + 0x180 + 32 + 0x0000001E + 0xB000007F + + + BUSY + Busy flag +0: PLL is stable or shutdown +1: PLL is changing status + 31 + 1 + read-only + + + RESPONSE + PLL status +0: PLL is not stable +1: PLL is stable for use + 29 + 1 + read-only + + + ENABLE + PLL enable status +0: PLL is off +1: PLL is on + 28 + 1 + read-only + + + MFI + loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) +0-15: invalid +16: divide by 16 +17: divide by17 +. . . +42: divide by 42 +43~:invalid + 0 + 7 + read-write + + + + + PLL_PLL2_MFN + PLL2 fraction numerator register + 0x184 + 32 + 0x00182B80 + 0x3FFFFFFF + + + MFN + Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + 0 + 30 + read-write + + + + + PLL_PLL2_MFD + PLL2 fraction demoninator register + 0x188 + 32 + 0x0E4E1C00 + 0x3FFFFFFF + + + MFD + Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + 0 + 30 + read-write + + + + + PLL_PLL2_SS_STEP + PLL2 spread spectrum step register + 0x18c + 32 + 0x00000000 + 0x3FFFFFFF + + + STEP + Step of spread spectrum modulator. +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + PLL_PLL2_SS_STOP + PLL2 spread spectrum stop register + 0x190 + 32 + 0x00000000 + 0x3FFFFFFF + + + STOP + Stop point of spread spectrum modulator +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + PLL_PLL2_CONFIG + PLL2 confguration register + 0x194 + 32 + 0x00000000 + 0x00000101 + + + SPREAD + Enable spread spectrum function. This field supports changing during PLL running. + 8 + 1 + read-write + + + REFSEL + Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. +0: XTAL24M +1: IRC24M + 0 + 1 + read-write + + + + + PLL_PLL2_LOCKTIME + PLL2 lock time register + 0x198 + 32 + 0x000009C4 + 0x0000FFFF + + + LOCKTIME + Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + 0 + 16 + read-write + + + + + PLL_PLL2_STEPTIME + PLL2 step time register + 0x19c + 32 + 0x000009C4 + 0x0000FFFF + + + STEPTIME + Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + 0 + 16 + read-write + + + + + PLL_PLL2_ADVANCED + PLL2 advance configuration register + 0x1a0 + 32 + 0x000009C4 + 0x11000000 + + + SLOW + Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. +0: fast lock enabled, lock time is 100us +1: fast lock disabled, lock time is 400us + 28 + 1 + read-write + + + DITHER + Enable dither function + 24 + 1 + read-write + + + + + PLL_PLL2_DIV_DIV0 + PLL2 divider output 0 configuration register + 0x1c0 + 32 + 0x00000002 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + PLL_PLL2_DIV_DIV1 + PLL2 divider output 1 configuration register + 0x1c4 + 32 + 0x00000003 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + + + TSNS + TSNS + TSNS + 0xf4104000 + + 0x0 + 0x3c + registers + + + + T + Temperature + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Signed number of temperature in 256 x celsius degree + 0 + 32 + read-only + + + + + TMAX + Maximum Temperature + 0x4 + 32 + 0xFF800000 + 0xFFFFFFFF + + + T + maximum temperature ever found + 0 + 32 + read-only + + + + + TMIN + Minimum Temperature + 0x8 + 32 + 0x007FFFFF + 0xFFFFFFFF + + + T + minimum temperature ever found + 0 + 32 + read-only + + + + + AGE + Sample age + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + AGE + age of T register in 24MHz clock cycles + 0 + 32 + read-only + + + + + STATUS + Status + 0x10 + 32 + 0x00000000 + 0x80000001 + + + VALID + indicate value in T is valid or not +0: not valid +1:valid + 31 + 1 + read-only + + + TRIGGER + Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode + 0 + 1 + write-only + + + + + CONFIG + Configuration + 0x14 + 32 + 0x00600300 + 0xC3FF0713 + + + IRQ_EN + Enable interrupt + 31 + 1 + read-write + + + RST_EN + Enable reset + 30 + 1 + read-write + + + COMPARE_MIN_EN + Enable compare for minimum temperature + 25 + 1 + read-write + + + COMPARE_MAX_EN + Enable compare for maximum temperature + 24 + 1 + read-write + + + SPEED + cycles of a progressive step in 24M clock, valide from 24-255, default 96 +24: 24 cycle for a step +25: 25 cycle for a step +26: 26 cycle for a step +... +255: 255 cycle for a step + 16 + 8 + read-write + + + AVERAGE + Average time, default in 3 +0: measure and return +1: twice and average +2: 4 times and average +. . . +7: 128 times and average + 8 + 3 + read-write + + + CONTINUOUS + continuous mode that keep sampling temperature peridically +0: trigger mode +1: continuous mode + 4 + 1 + read-write + + + ASYNC + Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value +0: active mode +1: Async mode + 1 + 1 + read-write + + + ENABLE + Enable temperature +0: disable, temperature sensor is shut down +1: enable. Temperature sensor enabled + 0 + 1 + read-write + + + + + VALIDITY + Sample validity + 0x18 + 32 + 0x016E3600 + 0xFFFFFFFF + + + VALIDITY + time for temperature values to expire in 24M clock cycles + 0 + 32 + read-write + + + + + FLAG + Temperature flag + 0x1c + 32 + 0x00000000 + 0x00330001 + + + RECORD_MIN_CLR + Clear minimum recorder of temerature, write 1 to clear + 21 + 1 + read-write + + + RECORD_MAX_CLR + Clear maximum recorder of temerature, write 1 to clear + 20 + 1 + read-write + + + UNDER_TEMP + Clear under temperature status, write 1 to clear + 17 + 1 + read-write + + + OVER_TEMP + Clear over temperature status, write 1 to clear + 16 + 1 + read-write + + + IRQ + IRQ flag, write 1 to clear + 0 + 1 + read-write + + + + + UPPER_LIM_IRQ + Maximum temperature to interrupt + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_IRQ + Minimum temperature to interrupt + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + UPPER_LIM_RST + Maximum temperature to reset + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_RST + Minimum temperature to reset + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + ASYNC + Configuration in asynchronous mode + 0x30 + 32 + 0x00000000 + 0x010107FF + + + ASYNC_TYPE + Compare hotter than or colder than in asynchoronous mode +0: hotter than +1: colder than + 24 + 1 + read-write + + + POLARITY + Polarity of internal comparator + 16 + 1 + read-write + + + VALUE + Value of async mode to compare + 0 + 11 + read-write + + + + + ADVAN + Advance configuration + 0x38 + 32 + 0x00000000 + 0x03010003 + + + ASYNC_IRQ + interrupt status of asynchronous mode + 25 + 1 + read-only + + + ACTIVE_IRQ + interrupt status of active mode + 24 + 1 + read-only + + + SAMPLING + temperature sampling is working + 16 + 1 + read-only + + + NEG_ONLY + use negative compare polarity only + 1 + 1 + read-write + + + POS_ONLY + use positive compare polarity only + 0 + 1 + read-write + + + + + + + BPOR + BPOR + BPOR + 0xf5004000 + + 0x0 + 0x14 + registers + + + + POR_CAUSE + Power on cause + 0x0 + 32 + 0x00000000 + 0x0000001F + + + CAUSE + Power on cause, each bit represnts one cause, write 1 to clear each bit +bit0: wakeup button +bit1: security violation +bit2: RTC alarm 0 +bit3: RTC alarm 1 +bit4: GPIO + 0 + 5 + read-write + + + + + POR_SELECT + Power on select + 0x4 + 32 + 0x00000000 + 0x0000001F + + + SELECT + Power on cause select, each bit represnts one cause, value 1 enables corresponding cause +bit0: wakeup button +bit1: security violation +bit2: RTC alarm 0 +bit3: RTC alarm 1 +bit4: GPIO + 0 + 5 + read-write + + + + + POR_CONFIG + Power on reset config + 0x8 + 32 + 0x00000000 + 0x00000001 + + + RETENTION + retention battery domain setting +0: battery reset on reset pin reset happen +1: battery domain retention when reset pin reset happen + 0 + 1 + read-write + + + + + POR_CONTROL + Power down control + 0xc + 32 + 0x00000000 + 0x0000FFFF + + + COUNTER + Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 + 0 + 16 + read-write + + + + + + + BCFG + BCFG + TRIM + 0xf5008000 + + 0x0 + 0x14 + registers + + + + VBG_CFG + Bandgap config + 0x0 + 32 + 0x00000000 + 0x831F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + LP_MODE + Bandgap works in low power mode +0: not in low power mode +1: bandgap work in low power mode + 25 + 1 + read-write + + + POWER_SAVE + Bandgap works in power save mode +0: not in power save mode +1: bandgap work in power save mode + 24 + 1 + read-write + + + VBG_1P0 + Bandgap 1.0V output trim + 16 + 5 + read-write + + + VBG_P65 + Bandgap 0.65V output trim + 8 + 5 + read-write + + + VBG_P50 + Bandgap 0.50V output trim + 0 + 5 + read-write + + + + + IRC32K_CFG + On-chip 32k oscillator config + 0x8 + 32 + 0x00000000 + 0x80C001FF + + + IRC_TRIMMED + IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: irc is not trimmed +1: irc is trimmed + 31 + 1 + read-write + + + CAPEX7_TRIM + IRC32K bit 7 + 23 + 1 + read-write + + + CAPEX6_TRIM + IRC32K bit 6 + 22 + 1 + read-write + + + CAP_TRIM + capacitor trim bits + 0 + 9 + read-write + + + + + XTAL32K_CFG + XTAL 32K config + 0xc + 32 + 0x00000000 + 0x00001313 + + + HYST_EN + crystal 32k hysteres enable + 12 + 1 + read-write + + + GMSEL + crystal 32k gm selection + 8 + 2 + read-write + + + CFG + crystal 32k config + 4 + 1 + read-write + + + AMP + crystal 32k amplifier + 0 + 2 + read-write + + + + + CLK_CFG + Clock config + 0x10 + 32 + 0x00000000 + 0x10010010 + + + XTAL_SEL + crystal selected + 28 + 1 + read-only + + + KEEP_IRC + force irc32k run + 16 + 1 + read-write + + + FORCE_XTAL + force switch to crystal + 4 + 1 + read-write + + + + + + + BUTN + BUTN + BUTN + 0xf500c000 + + 0x0 + 0xc + registers + + + + BTN_STATUS + Button status + 0x0 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click status, write 1 to clear flag +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press status, write 1 to clear flag +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + BTN_IRQ_MASK + Button interrupt mask + 0x4 + 32 + 0x00000000 + 0x77770FFF + + + XWCLICK + wake button click status when power button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 28 + 3 + read-write + + + WCLICK + wake button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 24 + 3 + read-write + + + XPCLICK + power button click status when wake button held interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 20 + 3 + read-write + + + PCLICK + power button click interrupt enable +bit0: clicked +bit1: double clicked +bit2: tripple clicked + 16 + 3 + read-write + + + DBTN + Dual button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 8 + 4 + read-write + + + WBTN + Wake button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 4 + 4 + read-write + + + PBTN + Power button press interrupt enable +bit0: button pressed +bit1: button confirmd +bit2: button long pressed +bit3: button long long pressed + 0 + 4 + read-write + + + + + LED_INTENSE + Debounce setting + 0x8 + 32 + 0x00000000 + 0x000F000F + + + RLED + Rbutton brightness 0 + 16 + 4 + read-write + + + PLED + Pbutton brightness 0 + 0 + 4 + read-write + + + + + + + BGPR + BGPR + BGPR + 0xf5018000 + + 0x0 + 0x20 + registers + + + + BATT_GPR0 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR1 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR2 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR3 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR4 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR5 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR6 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + BATT_GPR7 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + BSEC + BSEC + BSEC + 0xf5040000 + + 0x0 + 0x18 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x0003000F + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + BATT_FAIL + BATT secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 3 + 1 + read-write + + + BATT_NSC + BATT secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 2 + 1 + read-write + + + BATT_SEC + BATT secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 1 + 1 + read-write + + + BATT_INS + BATT secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 0 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF0003 + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + BATT_ESC_NSC + BATT is escalating non-secure event + 1 + 1 + read-only + + + BATT_ESC_SEC + BATT is escalting ssecure event + 0 + 1 + read-only + + + + + + + RTC + RTC + RTC + 0xf5044000 + + 0x0 + 0x2c + registers + + + + SECOND + Second counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SECOND + second counter + 0 + 32 + read-write + + + + + SUBSEC + Sub-second counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + SUBSEC + sub second counter + 0 + 32 + read-only + + + + + SEC_SNAP + Second counter snap shot + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_SNAP + second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + SUB_SNAP + Sub-second counter snap shot + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + SUB_SNAP + sub second snap shot, write to take snap shot + 0 + 32 + read-write + + + + + ALARM0 + RTC alarm0 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM0_INC + Alarm0 incremental + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM1 + RTC alarm1 + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ALARM + Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC + 0 + 32 + read-write + + + + + ALARM1_INC + Alarm1 incremental + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + INCREASE + adder when ARLAM0 happen, helps to create periodical alarm + 0 + 32 + read-write + + + + + ALARM_FLAG + RTC alarm flag + 0x20 + 32 + 0x00000000 + 0x00000003 + + + ALARM1 + alarm1 happen + 1 + 1 + read-write + + + ALARM0 + alarm0 happen + 0 + 1 + read-write + + + + + ALARM_EN + RTC alarm enable + 0x24 + 32 + 0x00000000 + 0x00000003 + + + ENABLE1 + alarm1 mask +0: alarm1 disabled +1: alarm1 enabled + 1 + 1 + read-write + + + ENABLE0 + alarm0 mask +0: alarm0 disabled +1: alarm0 enabled + 0 + 1 + read-write + + + + + + + BKEY + BKEY + BKEY + 0xf5048000 + + 0x0 + 0x4c + registers + + + + KEY_0_DATA_0 + Key data + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_1 + Key data + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_2 + Key data + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_3 + Key data + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_4 + Key data + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_5 + Key data + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_6 + Key data + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_0_DATA_7 + Key data + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_0 + Key data + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_1 + Key data + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_2 + Key data + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_3 + Key data + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_4 + Key data + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_5 + Key data + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_6 + Key data + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + KEY_1_DATA_7 + Key data + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + security key data + 0 + 32 + read-write + + + + + ECC_KEY0 + Key ECC and access control + 0x40 + 32 + 0x00000000 + 0xC000FFFF + + + WLOCK + write lock to key0 +0: write enable +1: write ignored + 31 + 1 + read-write + + + RLOCK + read lock to key0 +0: key read enable +1: key always read as 0 + 30 + 1 + read-write + + + ECC + Parity check bits for key0 + 0 + 16 + read-write + + + + + ECC_KEY1 + Key 1 ECC and access control + 0x44 + 32 + 0x00000000 + 0xC000FFFF + + + WLOCK + write lock to key0 +0: write enable +1: write ignored + 31 + 1 + read-write + + + RLOCK + read lock to key0 +0: key read enable +1: key always read as 0 + 30 + 1 + read-write + + + ECC + Parity check bits for key0 + 0 + 16 + read-write + + + + + SELECT + Key selection + 0x48 + 32 + 0x00000000 + 0x00000001 + + + SELECT + select key, key0 treated as secure key, in non-scure mode, only key1 can be selected +0: select key0 in secure mode, key1 in non-secure mode +1: select key1 in secure or nonsecure mode + 0 + 1 + read-write + + + + + + + BMON + BMON + BMON + 0xf504c000 + + 0x0 + 0x24 + registers + + + + MONITOR_GLITCH0_CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_GLITCH0_STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + MONITOR_CLOCK0_CONTROL + Glitch and clock monitor control + 0x10 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + MONITOR_CLOCK0_STATUS + Glitch and clock monitor status + 0x14 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + + TAMP + TAMP + TAMP + 0xf5050000 + + 0x0 + 0x88 + registers + + + + TAMP_TAMP0_CONTROL + Tamper n control + 0x0 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP0_POLY + Tamper n Polynomial of LFSR + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP0_LFSR + Tamper n LFSR shift register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_TAMP1_CONTROL + Tamper1 control + 0x10 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP1_POLY + Tamper1 Polynomial of LFSR + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP1_LFSR + Tamper1 LFSR shift register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_TAMP2_CONTROL + Tamper2 control + 0x20 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP2_POLY + Tamper2 Polynomial of LFSR + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP2_LFSR + Tamper2 LFSR shift register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_TAMP3_CONTROL + Tamper3 control + 0x30 + 32 + 0x00000000 + 0x801F03F7 + + + LOCK + lock tamper setting +0: tamper setting can be changed +1: tamper setting will last to next battery domain power cycle + 31 + 1 + read-write + + + BYPASS + bypass tamper violation filter +0: filter applied +1: filter not used + 20 + 1 + read-write + + + FILTER + filter length +0: 1 cycle +1: 2 cycle +15: 65526 cycle + 16 + 4 + read-write + + + VALUE + pin value for passive tamper + 8 + 2 + read-write + + + SPEED + tamper speed selection, (2^SPEED) changes per second +0: 1 shift per second +1: 2 shifts per second +. . . +15: 32768 shifts per second + 4 + 4 + read-write + + + RECOVER + tamper will recover itself if tamper LFSR goes wrong +0: tamper will not recover +1: tamper will recover + 2 + 1 + read-write + + + ACTIVE + select active or passive tamper +0: passive tamper +1: active tamper + 1 + 1 + read-write + + + ENABLE + enable tamper +0: tamper disableed +1: tamper enabled + 0 + 1 + read-write + + + + + TAMP_TAMP3_POLY + Tamper3 Polynomial of LFSR + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" + 0 + 32 + read-write + + + + + TAMP_TAMP3_LFSR + Tamper3 LFSR shift register + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + LFSR + LFSR for active tamper, write only register, always read 0 + 0 + 32 + write-only + + + + + TAMP_FLAG + Tamper flag + 0x80 + 32 + 0x00000000 + 0x00000FFF + + + FLAG + tamper flag, each bit represents one tamper pin, write 1 to clear the flag +Note, clear can only be cleared when tamper disapeared + 0 + 12 + read-write + + + + + IRQ_EN + Tamper interrupt enable + 0x84 + 32 + 0x00000000 + 0x80000FFF + + + LOCK + lock bit for IRQ enable +0: enable bits can be changed +1: enable bits hold until next battery domain power cycle + 31 + 1 + read-write + + + IRQ_EN + interrupt enable, each bit represents one tamper pin +0: interrupt disabled +1: interrupt enabled + 0 + 12 + read-write + + + + + + + MONO + MONO + MONO + 0xf5054000 + + 0x0 + 0x8 + registers + + + + MONOL + Low part of monotonic counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + low part of monotonica counter, write to this counter will cause counter increase by 1 + 0 + 32 + read-write + + + + + MONOH + High part of monotonic counter + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + EPOCH + Fuse value for high part of monotonica + 16 + 16 + read-write + + + COUNTER + high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow + 0 + 16 + read-write + + + + + + + \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6280/SConscript b/common/libraries/hpm_sdk/soc/HPM6280/SConscript new file mode 100644 index 00000000..5717c3e6 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/SConscript @@ -0,0 +1,25 @@ +import os +import sys +Import('rtconfig') +from building import * + +#get current directory +cwd = GetCurrentDir() + +# Update include path +path = [ cwd, cwd + '/boot' ] + +# The set of source files associated with this SConscript file. +src = Split(''' + system.c + hpm_l1c_drv.c + hpm_sysctl_drv.c + hpm_clock_drv.c + hpm_otp_drv.c + boot/hpm_bootheader.c +''') + + +group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) + +Return ('group') diff --git a/common/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.c b/common/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.c new file mode 100644 index 00000000..30c2edc2 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_bootheader.h" + +/* symbol exported from startup.S */ +extern uint32_t _start[]; + +/* following symbols exported from linker script */ +extern uint32_t __app_load_addr__[]; +extern uint32_t __app_offset__[]; +extern uint32_t __fw_size__[]; + +#define FW_SIZE (32768) +__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { + (uint32_t)__app_offset__, /* offset */ + (uint32_t)__fw_size__, /* size */ + 0, /* flags */ + 0, /* reserved0 */ + (uint32_t) &__app_load_addr__, /* load_addr */ + 0, /* reserved1 */ + (uint32_t) _start, /* entry_point */ + 0, /* reserved2 */ + {0}, /* hash */ + {0}, /* iv */ +}; + +__attribute__ ((section(".boot_header"))) const boot_header_t header = { + HPM_BOOTHEADER_TAG, /* tag */ + 0x10, /* version*/ + sizeof(header) + sizeof(fw_info), + 0, /* flags */ + 0, /* sw_version */ + 0, /* fuse_version */ + 1, /* fw_count */ + 0, + 0, /* sig_block_offset */ +}; diff --git a/common/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.h b/common/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.h new file mode 100644 index 00000000..c2bf30d0 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/boot/hpm_bootheader.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BOOT_HEADER_H +#define HPM_BOOT_HEADER_H + +#include "hpm_common.h" + +#define HPM_BOOTHEADER_TAG (0xBFU) +#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) + +#ifndef HPM_BOOT_FW_COUNT +#define HPM_BOOT_FW_COUNT 1 +#endif + +#if HPM_BOOT_FW_COUNT < 1 +#error "HPM_BOOT_FW_COUNT can't be less than 1" +#endif + +typedef struct { + uint32_t offset; /* 0x0: offset to boot_header start */ + uint32_t size; /* 0x4: size in bytes */ + uint32_t flags; /* 0x8: [3:0] fw type: */ + /* 0 - executable */ + /* 1 - cmd container */ + /* [11:8] - hash type */ + /* 0 - none */ + /* 1 - sha256 */ + /* 2 - sm3 */ + uint32_t reserved0; /* 0xC */ + uint32_t load_addr; /* 0x10: load address */ + uint32_t reserved1; /* 0x14 */ + uint32_t entry_point; /* 0x18: application entry */ + uint32_t reserved2; /* 0x1C */ + uint8_t hash[64]; /* 0x20: hash value */ + uint8_t iv[32]; /* 0x60: initial vector */ +} fw_info_table_t; + +typedef struct { + uint8_t tag; /* 0x0: must be '0xbf' */ + uint8_t version; /* 0x1: header version */ + uint16_t length; /* 0x2: header length, max 8KB */ + uint32_t flags; /* 0x4: [3:0] SRK set */ + /* [7:4] SRK index */ + /* [15:8] SRK_REVOKE_MASK */ + /* [19:16] Signature Type */ + /* 1: ECDSA */ + /* 2: SM2 */ + uint16_t sw_version; /* 0x8: software version */ + uint8_t fuse_version; /* 0xA: fuse version */ + uint8_t fw_count; /* 0xB: number of fw */ + uint16_t dc_block_offset; /* 0xC: device config block offset*/ + uint16_t sig_block_offset; /* 0xE: signature block offset */ + /* + * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] + * uint32_t dc_info[]; [> <] + */ +} boot_header_t; + +#endif /* HPM_BOOT_HEADER_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_batt_iomux.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_batt_iomux.h new file mode 100644 index 00000000..adc26294 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_batt_iomux.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BATT_IOMUX_H +#define HPM_BATT_IOMUX_H + +/* IOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_BATT_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ00_FUNC_CTL_BATT_TAMPER_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_SOC_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_BATT_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ01_FUNC_CTL_BATT_TAMPER_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_SOC_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_BATT_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ02_FUNC_CTL_BATT_TAMPER_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_BATT_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ03_FUNC_CTL_BATT_TAMPER_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ03_FUNC_CTL_SOC_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_BATT_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ04_FUNC_CTL_BATT_TAMPER_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ04_FUNC_CTL_SOC_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_BATT_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PZ05_FUNC_CTL_BATT_TAMPER_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_SOC_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_BATT_TAMPER_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_SOC_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_BATT_TAMPER_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_SOC_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_BATT_IOMUX_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_drv.h new file mode 100644 index 00000000..00dfb6fc --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_drv.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BCFG_DRV_H +#define HPM_BCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_bcfg_regs.h" + +/** + * + * @brief BCFG driver APIs + * @defgroup bcfg_interface BCFG driver APIs + * @ingroup io_interfaces + * @{ + */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief enable VBAT LP mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_enable_lp_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG |= BCFG_VBG_CFG_LP_MODE_MASK; +} + +/** + * @brief disable VBAT LP mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_disable_lp_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG &= ~BCFG_VBG_CFG_LP_MODE_MASK; +} + +/** + * @brief enable power save mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_enable_power_save_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG |= BCFG_VBG_CFG_POWER_SAVE_MASK; +} + +/** + * @brief disable power save mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_disable_power_save_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG &= ~BCFG_VBG_CFG_POWER_SAVE_MASK; +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BCFG_DRV_H */ + diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_regs.h new file mode 100644 index 00000000..b1933ddb --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_bcfg_regs.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BCFG_H +#define HPM_BCFG_H + +typedef struct { + __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */ + __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ + __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */ + __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */ + __RW uint32_t CLK_CFG; /* 0x10: Clock config */ +} BCFG_Type; + + +/* Bitfield definition for register: VBG_CFG */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL) +#define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U) +#define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) +#define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) + +/* + * LP_MODE (RW) + * + * Bandgap works in low power mode + * 0: not in low power mode + * 1: bandgap work in low power mode + */ +#define BCFG_VBG_CFG_LP_MODE_MASK (0x2000000UL) +#define BCFG_VBG_CFG_LP_MODE_SHIFT (25U) +#define BCFG_VBG_CFG_LP_MODE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_LP_MODE_SHIFT) & BCFG_VBG_CFG_LP_MODE_MASK) +#define BCFG_VBG_CFG_LP_MODE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_LP_MODE_MASK) >> BCFG_VBG_CFG_LP_MODE_SHIFT) + +/* + * POWER_SAVE (RW) + * + * Bandgap works in power save mode + * 0: not in power save mode + * 1: bandgap work in power save mode + */ +#define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL) +#define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U) +#define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK) +#define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT) + +/* + * VBG_1P0 (RW) + * + * Bandgap 1.0V output trim + */ +#define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL) +#define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U) +#define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK) +#define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT) + +/* + * VBG_P65 (RW) + * + * Bandgap 0.65V output trim + */ +#define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U) +#define BCFG_VBG_CFG_VBG_P65_SHIFT (8U) +#define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK) +#define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT) + +/* + * VBG_P50 (RW) + * + * Bandgap 0.50V output trim + */ +#define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU) +#define BCFG_VBG_CFG_VBG_P50_SHIFT (0U) +#define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK) +#define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT) + +/* Bitfield definition for register: IRC32K_CFG */ +/* + * IRC_TRIMMED (RW) + * + * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: irc is not trimmed + * 1: irc is trimmed + */ +#define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) + +/* + * CAPEX7_TRIM (RW) + * + * IRC32K bit 7 + */ +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) + +/* + * CAPEX6_TRIM (RW) + * + * IRC32K bit 6 + */ +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) + +/* + * CAP_TRIM (RW) + * + * capacitor trim bits + */ +#define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU) +#define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U) +#define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) + +/* Bitfield definition for register: XTAL32K_CFG */ +/* + * HYST_EN (RW) + * + * crystal 32k hysteres enable + */ +#define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U) +#define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U) +#define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK) +#define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT) + +/* + * GMSEL (RW) + * + * crystal 32k gm selection + */ +#define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U) +#define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U) +#define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK) +#define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT) + +/* + * CFG (RW) + * + * crystal 32k config + */ +#define BCFG_XTAL32K_CFG_CFG_MASK (0x10U) +#define BCFG_XTAL32K_CFG_CFG_SHIFT (4U) +#define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK) +#define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT) + +/* + * AMP (RW) + * + * crystal 32k amplifier + */ +#define BCFG_XTAL32K_CFG_AMP_MASK (0x3U) +#define BCFG_XTAL32K_CFG_AMP_SHIFT (0U) +#define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK) +#define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT) + +/* Bitfield definition for register: CLK_CFG */ +/* + * XTAL_SEL (RO) + * + * crystal selected + */ +#define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL) +#define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U) +#define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT) + +/* + * KEEP_IRC (RW) + * + * force irc32k run + */ +#define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL) +#define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U) +#define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK) +#define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT) + +/* + * FORCE_XTAL (RW) + * + * force switch to crystal + */ +#define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U) +#define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U) +#define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK) +#define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT) + + + + +#endif /* HPM_BCFG_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_bgpr_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h similarity index 99% rename from common/libraries/hpm_sdk/soc/ip/hpm_bgpr_regs.h rename to common/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h index 857e27be..b5b4531e 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_bgpr_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_bpor_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_drv.h similarity index 100% rename from common/libraries/hpm_sdk/drivers/inc/hpm_bpor_drv.h rename to common/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_drv.h diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_bpor_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_regs.h similarity index 98% rename from common/libraries/hpm_sdk/soc/ip/hpm_bpor_regs.h rename to common/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_regs.h index ae6c4f05..539c5840 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_bpor_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_bpor_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c b/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c new file mode 100644 index 00000000..e4e9ee44 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c @@ -0,0 +1,498 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_soc.h" +#include "hpm_common.h" +#include "hpm_pllctlv2_drv.h" +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/* Clock preset values */ +#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) +#define FREQ_PRESET1_PLL0_CLK0 (400000000UL) +#define FREQ_PRESET1_PLL0_CLK1 (333333333UL) +#define FREQ_PRESET1_PLL1_CLK2 (250000000UL) +#define FREQ_PRESET1_PLL1_CLK0 (480000000UL) +#define FREQ_PRESET1_PLL1_CLK1 (320000000UL) +#define FREQ_PRESET1_PLL2_CLK0 (5160960000UL) +#define FREQ_PRESET1_PLL2_CLK1 (4515840000UL) +#define FREQ_32KHz (32768UL) +#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) +#define DAC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->DACCLK) +#define WDG_INSTANCE_NUM (2U) +#define BUS_FREQ_MAX (200000000UL) +#define FREQ_1MHz (1000000UL) + +/* Clock On/Off definitions */ +#define CLOCK_ON (true) +#define CLOCK_OFF (false) + + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ + + + +/** + * @brief Get Clock frequency for IP in common group + */ +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); + +/** + * @brief Get Clock frequency for ADC + */ +static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance); + +/** + * @brief Get Clock frequency for DAC + */ +static uint32_t get_frequency_for_dac(uint32_t instance); + +/** + * @brief Get Clock frequency for WDG + */ +static uint32_t get_frequency_for_wdg(uint32_t instance); + +/** + * @brief Turn on/off the IP clock + */ +static void switch_ip_clock(clock_name_t clock_name, bool on); + +static uint32_t get_frequency_for_cpu(void); +static uint32_t get_frequency_for_axi(void); +static uint32_t get_frequency_for_ahb(void); + +/*********************************************************************************************************************** + * Variables + **********************************************************************************************************************/ +static const clock_node_t s_adc_clk_mux_node[] = { + clock_node_ana0, clock_node_ahb, +}; + +static const clock_node_t s_dac_clk_mux_node[] = { + clock_node_ana3, clock_node_ahb +}; + +static WDG_Type *const s_wdgs[] = { HPM_WDG0, HPM_WDG1 }; + +uint32_t hpm_core_clock; + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +uint32_t clock_get_frequency(clock_name_t clock_name) +{ + uint32_t clk_freq; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); + break; + case CLK_SRC_GROUP_ADC: + clk_freq = get_frequency_for_adc(CLK_SRC_GROUP_ADC, node_or_instance); + break; + case CLK_SRC_GROUP_DAC: + clk_freq = get_frequency_for_dac(node_or_instance); + break; + case CLK_SRC_GROUP_WDG: + clk_freq = get_frequency_for_wdg(node_or_instance); + break; + case CLK_SRC_GROUP_PMIC: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case CLK_SRC_GROUP_CPU0: + clk_freq = get_frequency_for_cpu(); + break; + case CLK_SRC_GROUP_AHB: + clk_freq = get_frequency_for_ahb(); + break; + case CLK_SRC_GROUP_AXI: + clk_freq = get_frequency_for_axi(); + break; + case CLK_SRC_GROUP_SRC: + clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); + break; + default: + clk_freq = 0UL; + break; + } + return clk_freq; +} + +uint32_t get_frequency_for_source(clock_source_t source) +{ + uint32_t clk_freq; + switch (source) { + case clock_source_osc0_clk0: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case clock_source_pll0_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); + break; + case clock_source_pll0_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 1U); + break; + case clock_source_pll0_clk2: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 2U); + break; + case clock_source_pll1_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); + break; + case clock_source_pll1_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); + break; + case clock_source_pll2_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 0U); + break; + case clock_source_pll2_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 1U); + break; + default: + clk_freq = 0UL; + break; + } + + return clk_freq; +} + +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) +{ + uint32_t clk_freq = 0UL; + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); + + if (node_or_instance < clock_node_end) { + uint32_t clk_node = (uint32_t) node_or_instance; + + uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); + clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); + clk_freq = get_frequency_for_source(clk_mux) / clk_div; + } + return clk_freq; +} + +static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance) +{ + uint32_t clk_freq = 0UL; + bool is_mux_valid = false; + clock_node_t node = clock_node_end; + uint32_t adc_index = instance; + + (void) clk_src_type; + + if (adc_index < ADC_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[adc_index]); + if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { + node = s_adc_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + + if (is_mux_valid) { + if (node != clock_node_ahb) { + node += instance; + clk_freq = get_frequency_for_ip_in_common_group(node); + } else { + clk_freq = get_frequency_for_ahb(); + } + } + return clk_freq; +} + +static uint32_t get_frequency_for_dac(uint32_t instance) +{ + uint32_t clk_freq = 0UL; + bool is_mux_valid = false; + clock_node_t node = clock_node_end; + if (instance < DAC_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[instance]); + if (mux_in_reg < ARRAY_SIZE(s_dac_clk_mux_node)) { + node = s_dac_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + + if (is_mux_valid) { + if (node == clock_node_ahb) { + clk_freq = get_frequency_for_ahb(); + } else { + node += instance; + clk_freq = get_frequency_for_ip_in_common_group(node); + } + } + + return clk_freq; +} + +static uint32_t get_frequency_for_wdg(uint32_t instance) +{ + uint32_t freq_in_hz; + /* EXT clock is chosen */ + if (WDG_CTRL_CLKSEL_GET(s_wdgs[instance]->CTRL) == 0) { + freq_in_hz = get_frequency_for_cpu(); + } + /* PCLK is chosen */ + else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + +static uint32_t get_frequency_for_cpu(void) +{ + uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); + uint32_t div = SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_source(mux) / div); +} + +static uint32_t get_frequency_for_axi(void) +{ + uint32_t div = SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_cpu() / div); +} + +static uint32_t get_frequency_for_ahb(void) +{ + uint32_t div = SYSCTL_CLOCK_CPU_SUB1_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_cpu() / div); +} + +clk_src_t clock_get_source(clock_name_t clock_name) +{ + uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; + uint8_t clk_src_index = 0xFU; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_ADC: + if (node_or_instance < ADC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_ADC; + clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_WDG; + clk_src_index = (WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL) == 0); + } + break; + case CLK_SRC_GROUP_PMIC: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = clock_source_osc0_clk0; + break; + case CLK_SRC_GROUP_CPU0: + case CLK_SRC_GROUP_AHB: + case CLK_SRC_GROUP_AXI: + clk_src_group = CLK_SRC_GROUP_CPU0; + clk_src_index = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + case CLK_SRC_GROUP_SRC: + clk_src_index = (clk_src_t) node_or_instance; + break; + default: + clk_src_group = CLK_SRC_GROUP_INVALID; + break; + } + + clk_src_t clk_src; + if (clk_src_group != CLK_SRC_GROUP_INVALID) { + clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); + } else { + clk_src = clk_src_invalid; + } + + return clk_src; +} + +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src <= clk_adc_src_ahb0) || (src >= clk_adc_src_ana2)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->ADCCLK[node_or_instance] = + (HPM_SYSCTL->ADCCLK[node_or_instance] & SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_DAC) || (node_or_instance >= DAC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src < clk_dac_src_ana3) || (src > clk_dac_src_ahb0)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->DACCLK[node_or_instance] = + (HPM_SYSCTL->DACCLK[node_or_instance] & SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) +{ + hpm_stat_t status = status_success; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + if ((div < 1U) || (div > 256U)) { + status = status_clk_div_invalid; + } else { + sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, (clock_source_t) src, div); + } + break; + case CLK_SRC_GROUP_ADC: + status = status_clk_operation_unsupported; + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + if (src == clk_wdg_src_ahb0) { + s_wdgs[node_or_instance]->CTRL &= ~WDG_CTRL_CLKSEL_MASK; + } else if (src == clk_wdg_src_osc32k) { + s_wdgs[node_or_instance]->CTRL |= WDG_CTRL_CLKSEL_MASK; + } else { + status = status_clk_src_invalid; + } + } + break; + case CLK_SRC_GROUP_PMIC: + status = status_clk_fixed; + break; + case CLK_SRC_GROUP_AHB: + status = status_clk_shared_cpu0; + break; + case CLK_SRC_GROUP_AXI: + status = status_clk_shared_cpu0; + break; + case CLK_SRC_GROUP_CPU0: + if (node_or_instance == clock_node_cpu0) { + /* Note: the AXI and AHB BUS share the same CPU clock, once the CPU clock frequency + * changes, the AXI and AHB clock changes accordingly, here the driver ensures the + * AXI and AHB bus clock frequency is in valid range. + */ + uint32_t expected_freq = get_frequency_for_source((clock_source_t) src) / div; + uint32_t axi_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; + uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, (clock_source_t) src, div, axi_sub_div, ahb_sub_div); + } else { + status = status_clk_shared_cpu0; + } + break; + case CLK_SRC_GROUP_SRC: + status = status_clk_operation_unsupported; + break; + default: + status = status_clk_src_invalid; + break; + } + + return status; +} + +void switch_ip_clock(clock_name_t clock_name, bool on) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + uint32_t mode = on ? 1UL : 2UL; + HPM_SYSCTL->RESOURCE[resource] = + (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); + } +} + +void clock_enable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_ON); +} + +void clock_disable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_OFF); +} + +void clock_add_to_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); + } else if (resource == RESOURCE_SHARED_PTPC) { + sysctl_enable_group_resource(HPM_SYSCTL, group, sysctl_resource_ptpc, true); + } +} + +void clock_remove_from_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); + } else if (resource == RESOURCE_SHARED_PTPC) { + sysctl_enable_group_resource(HPM_SYSCTL, group, sysctl_resource_ptpc, false); + } +} + +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu < 2U) { + HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); + } +} + +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu < 2U) { + HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); + } +} + +void clock_cpu_delay_us(uint32_t us) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; + while (hpm_csr_get_core_cycle() < expected_ticks) { + } +} + +void clock_cpu_delay_ms(uint32_t ms) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t) ticks_per_us * 1000UL * ms; + while (hpm_csr_get_core_cycle() < expected_ticks) { + } +} + +void clock_update_core_clock(void) +{ + uint32_t hart_id = read_csr(CSR_MHARTID); + clock_name_t cpu_clk_name = (hart_id == 1U) ? clock_cpu1 : clock_cpu0; + hpm_core_clock = clock_get_frequency(cpu_clk_name); +} diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h new file mode 100644 index 00000000..dbfcc718 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_CLOCK_DRV_H +#define HPM_CLOCK_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_drv.h" +#include "hpm_csr_drv.h" + + +/** + * @brief Error codes for clock driver + */ +enum { + status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), + status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), + status_clk_invalid = MAKE_STATUS(status_group_clk, 2), + status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), + status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), + status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), + status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), + status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), + status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), + status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), + status_clk_fixed = MAKE_STATUS(status_group_clk, 10), + +}; + + + +/** + * @brief Clock source group definitions + */ +#define CLK_SRC_GROUP_COMMON (0U) +#define CLK_SRC_GROUP_ADC (1U) +#define CLK_SRC_GROUP_WDG (3U) +#define CLK_SRC_GROUP_PMIC (4U) +#define CLK_SRC_GROUP_AHB (5U) +#define CLK_SRC_GROUP_AXI (6U) +#define CLK_SRC_GROUP_DAC (7U) +#define CLK_SRC_GROUP_CPU0 (9U) +#define CLK_SRC_GROUP_SRC (10U) +#define CLK_SRC_GROUP_INVALID (15U) + +#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) +#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) +#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) + +/** + * @brief Clock source definitions + */ +typedef enum _clock_sources { + clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), + clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), + clk_src_pll0_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), + clk_src_pll0_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), + clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), + clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), + clk_src_pll2_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), + clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), + clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), + + clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 2), + clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 3), + + clk_dac_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), + clk_dac_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), + + clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), + clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), + + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), +} clk_src_t; + + +#define RESOURCE_INVALID (0xFFFFU) +#define RESOURCE_SHARED_PTPC (0xFFFEU) +#define RESOURCE_SHARED_CPU0 (0xFFFDU) + +/* Clock NAME related Macros */ +#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)(node))) +#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) +#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) +#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) + +/** + * @brief Peripheral Clock Type Description + */ +typedef enum _clock_name { + clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_CPU0, clock_node_cpu0), + clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), + clock_cpu1 = MAKE_CLOCK_NAME(sysctl_resource_cpu1, CLK_SRC_GROUP_CPU0, clock_node_cpu1), + clock_mchtmr1 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr1, CLK_SRC_GROUP_COMMON, clock_node_mchtmr1), + clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), + clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), + clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), + clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), + clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), + clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), + clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), + clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), + clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), + clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), + clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), + clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), + clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), + clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), + clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), + clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), + clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), + clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), + clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), + clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), + clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), + clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), + clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), + clock_can2 = MAKE_CLOCK_NAME(sysctl_resource_can2, CLK_SRC_GROUP_COMMON, clock_node_can2), + clock_can3 = MAKE_CLOCK_NAME(sysctl_resource_can3, CLK_SRC_GROUP_COMMON, clock_node_can3), + clock_lin0 = MAKE_CLOCK_NAME(sysctl_resource_lin0, CLK_SRC_GROUP_COMMON, clock_node_lin0), + clock_lin1 = MAKE_CLOCK_NAME(sysctl_resource_lin1, CLK_SRC_GROUP_COMMON, clock_node_lin1), + clock_lin2 = MAKE_CLOCK_NAME(sysctl_resource_lin2, CLK_SRC_GROUP_COMMON, clock_node_lin2), + clock_lin3 = MAKE_CLOCK_NAME(sysctl_resource_lin3, CLK_SRC_GROUP_COMMON, clock_node_lin3), + + clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AHB, clock_node_ahb), + clock_axi = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AXI, clock_node_axi), + clock_axic = MAKE_CLOCK_NAME(sysctl_resource_axic, CLK_SRC_GROUP_AXI, clock_node_axi), + clock_axis = MAKE_CLOCK_NAME(sysctl_resource_axis, CLK_SRC_GROUP_AXI, clock_node_axi), + clock_ahbp = MAKE_CLOCK_NAME(sysctl_resource_ahbp, CLK_SRC_GROUP_AHB, clock_node_ahb), + + clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_COMMON, clock_node_ptpc), + clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), + clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), + clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI, 0), + clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI, 1), + clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXI, 2), + clock_ram0 = MAKE_CLOCK_NAME(sysctl_resource_ram0, CLK_SRC_GROUP_AXI, 3), + clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AXI, 4), + clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 0), + clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 1), + clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 2), + clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_dma0, CLK_SRC_GROUP_AHB, 3), + clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AHB, 4), + clock_mot0 = MAKE_CLOCK_NAME(sysctl_resource_mot0, CLK_SRC_GROUP_AHB, 5), + clock_mot1 = MAKE_CLOCK_NAME(sysctl_resource_mot1, CLK_SRC_GROUP_AHB, 6), + clock_mot2 = MAKE_CLOCK_NAME(sysctl_resource_mot2, CLK_SRC_GROUP_AHB, 7), + clock_mot3 = MAKE_CLOCK_NAME(sysctl_resource_mot3, CLK_SRC_GROUP_AHB, 8), + clock_crc0 = MAKE_CLOCK_NAME(sysctl_resource_crc0, CLK_SRC_GROUP_AHB, 9), + clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 10), + clock_msyn = MAKE_CLOCK_NAME(sysctl_resource_msyn, CLK_SRC_GROUP_AHB, 11), + clock_sdm0 = MAKE_CLOCK_NAME(sysctl_resource_sdm0, CLK_SRC_GROUP_AHB, 13), + clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), + clock_lmm1 = MAKE_CLOCK_NAME(sysctl_resource_lmm1, CLK_SRC_GROUP_CPU0, 1), + clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_CPU0, 2), + + + /* For ADC, there are 2-stage clock source and divider configurations */ + clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), + clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), + clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), + clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), + clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), + clock_adc2 = MAKE_CLOCK_NAME(sysctl_resource_adc2, CLK_SRC_GROUP_ADC, 2), + + /* For DAC, there are 2-stage clock source and divider configurations */ + clock_ana3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana3), + clock_ana4 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana4), + clock_dac0 = MAKE_CLOCK_NAME(sysctl_resource_dac0, CLK_SRC_GROUP_DAC, 0), + clock_dac1 = MAKE_CLOCK_NAME(sysctl_resource_dac1, CLK_SRC_GROUP_DAC, 1), + + /* Clock sources */ + clk_osc0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 0), + clk_pll0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 1), + clk_pll0clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 2), + clk_pll0clk2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 3), + clk_pll1clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 4), + clk_pll1clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 5), + clk_pll2clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 6), + clk_pll2clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 7), +} clock_name_t; + +extern uint32_t hpm_core_clock; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get specified IP frequency + * @param[in] clock_name IP clock name + * + * @return IP clock frequency in Hz + */ +uint32_t clock_get_frequency(clock_name_t clock_name); + +/** + * @brief Get Clock frequency for selected clock source + * @param [in] source clock source + * @return clock frequency for selected clock source + */ +uint32_t get_frequency_for_source(clock_source_t source); + +/** + * @brief Get the IP clock source + * Note: This API return the direct clock source + * @param [in] clock_name clock name + * @return IP clock source + */ +clk_src_t clock_get_source(clock_name_t clock_name); + +/** + * @brief Set ADC clock source + * @param[in] clock_name ADC clock name + * @param[in] src ADC clock source + * + * @return #status_success Setting ADC clock source is successful + * #status_clk_invalid Invalid ADC clock + * #status_clk_src_invalid Invalid ADC clock source + */ +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set DAC clock source + * @param[in] clock_name DAC clock name + * @param[in] src DAC clock source + * + * @return #status_success Setting DAC clock source is successful + * #status_clk_invalid Invalid DAC clock + * #status_clk_src_invalid Invalid DAC clock source + */ +hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set the IP clock source and divider + * @param[in] clock_name clock name + * @param[in] src clock source + * @param[in] div clock divider, valid range (1 - 256) + * + * @return #status_success Setting Clock source and divider is successful. + * #status_clk_src_invalid clock source is invalid. + * #status_clk_fixed clock source and divider is a fixed value + * #status_clk_shared_ahb Clock is shared with the AHB clock + * #status_clk_shared_axi0 Clock is shared with the AXI0 clock + * #status_clk_shared_axi1 CLock is shared with the AXI1 clock + * #status_clk_shared_axi2 Clock is shared with the AXI2 clock + * #status_clk_shared_cpu0 Clock is shared with the CPU0 clock + * #status_clk_shared_cpu1 Clock is shared with the CPU1 clock + */ +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); + +/** + * @brief Enable IP clock + * @param[in] clock_name IP clock name + */ +void clock_enable(clock_name_t clock_name); + +/** + * @brief Disable IP clock + * @param[in] clock_name IP clock name + */ +void clock_disable(clock_name_t clock_name); + +/** + * @brief Add IP to specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_add_to_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Remove IP from specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_remove_from_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Delay specified microseconds + * + * @param [in] us expected delay interval in microseconds + */ +void clock_cpu_delay_us(uint32_t us); + +/** + * @brief Delay specified milliseconds + * + * @param [in] ms expected delay interval in milliseconds + */ +void clock_cpu_delay_ms(uint32_t ms); + +/** + * @brief Update the Core clock frequency + */ +void clock_update_core_clock(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_CLOCK_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_csr_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_csr_regs.h new file mode 100644 index 00000000..88d1c2a5 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_csr_regs.h @@ -0,0 +1,6512 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CSR_H +#define HPM_CSR_H + +/* STANDARD CRS address definition */ +#define CSR_USTATUS (0x0) +#define CSR_UIE (0x4) +#define CSR_UTVEC (0x5) +#define CSR_USCRATCH (0x40) +#define CSR_UEPC (0x41) +#define CSR_UCAUSE (0x42) +#define CSR_UTVAL (0x43) +#define CSR_UIP (0x44) +#define CSR_SSTATUS (0x100) +#define CSR_SEDELEG (0x102) +#define CSR_SIDELEG (0x103) +#define CSR_SIE (0x104) +#define CSR_STVEC (0x105) +#define CSR_SSCRATCH (0x140) +#define CSR_SEPC (0x141) +#define CSR_SCAUSE (0x142) +#define CSR_STVAL (0x143) +#define CSR_SIP (0x144) +#define CSR_SATP (0x180) +#define CSR_MSTATUS (0x300) +#define CSR_MISA (0x301) +#define CSR_MEDELEG (0x302) +#define CSR_MIDELEG (0x303) +#define CSR_MIE (0x304) +#define CSR_MTVEC (0x305) +#define CSR_MCOUNTEREN (0x306) +#define CSR_MHPMEVENT3 (0x323) +#define CSR_MHPMEVENT4 (0x324) +#define CSR_MHPMEVENT5 (0x325) +#define CSR_MHPMEVENT6 (0x326) +#define CSR_MSCRATCH (0x340) +#define CSR_MEPC (0x341) +#define CSR_MCAUSE (0x342) +#define CSR_MTVAL (0x343) +#define CSR_MIP (0x344) +#define CSR_PMPCFG0 (0x3A0) +#define CSR_PMPCFG1 (0x3A1) +#define CSR_PMPCFG2 (0x3A2) +#define CSR_PMPCFG3 (0x3A3) +#define CSR_PMPADDR0 (0x3B0) +#define CSR_PMPADDR1 (0x3B1) +#define CSR_PMPADDR2 (0x3B2) +#define CSR_PMPADDR3 (0x3B3) +#define CSR_PMPADDR4 (0x3B4) +#define CSR_PMPADDR5 (0x3B5) +#define CSR_PMPADDR6 (0x3B6) +#define CSR_PMPADDR7 (0x3B7) +#define CSR_PMPADDR8 (0x3B8) +#define CSR_PMPADDR9 (0x3B9) +#define CSR_PMPADDR10 (0x3BA) +#define CSR_PMPADDR11 (0x3BB) +#define CSR_PMPADDR12 (0x3BC) +#define CSR_PMPADDR13 (0x3BD) +#define CSR_PMPADDR14 (0x3BE) +#define CSR_PMPADDR15 (0x3BF) +#define CSR_TSELECT (0x7A0) +#define CSR_TDATA1 (0x7A1) +#define CSR_MCONTROL (0x7A1) +#define CSR_ICOUNT (0x7A1) +#define CSR_ITRIGGER (0x7A1) +#define CSR_ETRIGGER (0x7A1) +#define CSR_TDATA2 (0x7A2) +#define CSR_TDATA3 (0x7A3) +#define CSR_TEXTRA (0x7A3) +#define CSR_TINFO (0x7A4) +#define CSR_TCONTROL (0x7A5) +#define CSR_MCONTEXT (0x7A8) +#define CSR_SCONTEXT (0x7AA) +#define CSR_DCSR (0x7B0) +#define CSR_DPC (0x7B1) +#define CSR_DSCRATCH0 (0x7B2) +#define CSR_DSCRATCH1 (0x7B3) +#define CSR_MCYCLE (0xB00) +#define CSR_MINSTRET (0xB02) +#define CSR_MHPMCOUNTER3 (0xB03) +#define CSR_MHPMCOUNTER4 (0xB04) +#define CSR_MHPMCOUNTER5 (0xB05) +#define CSR_MHPMCOUNTER6 (0xB06) +#define CSR_MCYCLEH (0xB80) +#define CSR_MINSTRETH (0xB82) +#define CSR_MHPMCOUNTER3H (0xB83) +#define CSR_MHPMCOUNTER4H (0xB84) +#define CSR_MHPMCOUNTER5H (0xB85) +#define CSR_MHPMCOUNTER6H (0xB86) +#define CSR_PMACFG0 (0xBC0) +#define CSR_PMACFG1 (0xBC1) +#define CSR_PMACFG2 (0xBC2) +#define CSR_PMACFG3 (0xBC3) +#define CSR_PMAADDR0 (0xBD0) +#define CSR_PMAADDR1 (0xBD1) +#define CSR_PMAADDR2 (0xBD2) +#define CSR_PMAADDR3 (0xBD3) +#define CSR_PMAADDR4 (0xBD4) +#define CSR_PMAADDR5 (0xBD5) +#define CSR_PMAADDR6 (0xBD6) +#define CSR_PMAADDR7 (0xBD7) +#define CSR_PMAADDR8 (0xBD8) +#define CSR_PMAADDR9 (0xBD9) +#define CSR_PMAADDR10 (0xBDA) +#define CSR_PMAADDR11 (0xBDB) +#define CSR_PMAADDR12 (0xBDC) +#define CSR_PMAADDR13 (0xBDD) +#define CSR_PMAADDR14 (0xBDE) +#define CSR_PMAADDR15 (0xBDF) +#define CSR_CYCLE (0xC00) +#define CSR_CYCLEH (0xC80) +#define CSR_MVENDORID (0xF11) +#define CSR_MARCHID (0xF12) +#define CSR_MIMPID (0xF13) +#define CSR_MHARTID (0xF14) + +/* NON-STANDARD CRS address definition */ +#define CSR_SCOUNTEREN (0x106) +#define CSR_MCOUNTINHIBIT (0x320) +#define CSR_MILMB (0x7C0) +#define CSR_MDLMB (0x7C1) +#define CSR_MECC_CODE (0x7C2) +#define CSR_MNVEC (0x7C3) +#define CSR_MXSTATUS (0x7C4) +#define CSR_MPFT_CTL (0x7C5) +#define CSR_MHSP_CTL (0x7C6) +#define CSR_MSP_BOUND (0x7C7) +#define CSR_MSP_BASE (0x7C8) +#define CSR_MDCAUSE (0x7C9) +#define CSR_MCACHE_CTL (0x7CA) +#define CSR_MCCTLBEGINADDR (0x7CB) +#define CSR_MCCTLCOMMAND (0x7CC) +#define CSR_MCCTLDATA (0x7CD) +#define CSR_MCOUNTERWEN (0x7CE) +#define CSR_MCOUNTERINTEN (0x7CF) +#define CSR_MMISC_CTL (0x7D0) +#define CSR_MCOUNTERMASK_M (0x7D1) +#define CSR_MCOUNTERMASK_S (0x7D2) +#define CSR_MCOUNTERMASK_U (0x7D3) +#define CSR_MCOUNTEROVF (0x7D4) +#define CSR_MSLIDELEG (0x7D5) +#define CSR_MCLK_CTL (0x7DF) +#define CSR_DEXC2DBG (0x7E0) +#define CSR_DDCAUSE (0x7E1) +#define CSR_UITB (0x800) +#define CSR_UCODE (0x801) +#define CSR_UDCAUSE (0x809) +#define CSR_UCCTLBEGINADDR (0x80B) +#define CSR_UCCTLCOMMAND (0x80C) +#define CSR_SLIE (0x9C4) +#define CSR_SLIP (0x9C5) +#define CSR_SDCAUSE (0x9C9) +#define CSR_SCCTLDATA (0x9CD) +#define CSR_SCOUNTERINTEN (0x9CF) +#define CSR_SCOUNTERMASK_M (0x9D1) +#define CSR_SCOUNTERMASK_S (0x9D2) +#define CSR_SCOUNTERMASK_U (0x9D3) +#define CSR_SCOUNTEROVF (0x9D4) +#define CSR_SCOUNTINHIBIT (0x9E0) +#define CSR_SHPMEVENT3 (0x9E3) +#define CSR_SHPMEVENT4 (0x9E4) +#define CSR_SHPMEVENT5 (0x9E5) +#define CSR_SHPMEVENT6 (0x9E6) +#define CSR_MICM_CFG (0xFC0) +#define CSR_MDCM_CFG (0xFC1) +#define CSR_MMSC_CFG (0xFC2) +#define CSR_MMSC_CFG2 (0xFC3) + +/* STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: USTATUS */ +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_USTATUS_UPIE_MASK (0x10U) +#define CSR_USTATUS_UPIE_SHIFT (4U) +#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) +#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_USTATUS_UIE_MASK (0x1U) +#define CSR_USTATUS_UIE_SHIFT (0U) +#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) +#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) + +/* Bitfield definition for register: UIE */ +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UEIE_MASK (0x100U) +#define CSR_UIE_UEIE_SHIFT (8U) +#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) +#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UTIE_MASK (0x10U) +#define CSR_UIE_UTIE_SHIFT (4U) +#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) +#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_USIE_MASK (0x1U) +#define CSR_UIE_USIE_SHIFT (0U) +#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) +#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) + +/* Bitfield definition for register: UTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_UTVEC_BASE_31_2_SHIFT (2U) +#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) +#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: USCRATCH */ +/* + * USCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_USCRATCH_USCRATCH_SHIFT (0U) +#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) +#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) + +/* Bitfield definition for register: UEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_UEPC_EPC_SHIFT (1U) +#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) +#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) + +/* Bitfield definition for register: UCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) +#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 4:User timer interrupt + * 8:User external interrupt + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9-11:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32：Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) +#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: UTVAL */ +/* + * UTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) +#define CSR_UTVAL_UTVAL_SHIFT (0U) +#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) +#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) + +/* Bitfield definition for register: UIP */ +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UEIP_MASK (0x100U) +#define CSR_UIP_UEIP_SHIFT (8U) +#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) +#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UTIP_MASK (0x10U) +#define CSR_UIP_UTIP_SHIFT (4U) +#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) +#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_USIP_MASK (0x1U) +#define CSR_UIP_USIP_SHIFT (0U) +#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) +#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) + +/* Bitfield definition for register: SSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_SSTATUS_SD_MASK (0x80000000UL) +#define CSR_SSTATUS_SD_SHIFT (31U) +#define CSR_SSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SD_MASK) >> CSR_SSTATUS_SD_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect. + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_SSTATUS_MXR_MASK (0x80000UL) +#define CSR_SSTATUS_MXR_SHIFT (19U) +#define CSR_SSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_SSTATUS_MXR_SHIFT) & CSR_SSTATUS_MXR_MASK) +#define CSR_SSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_SSTATUS_MXR_MASK) >> CSR_SSTATUS_MXR_SHIFT) + +/* + * SUM (RW) + * + * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. + * 0:Not Allowed + * 1:Allowed + */ +#define CSR_SSTATUS_SUM_MASK (0x40000UL) +#define CSR_SSTATUS_SUM_SHIFT (18U) +#define CSR_SSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SUM_SHIFT) & CSR_SSTATUS_SUM_MASK) +#define CSR_SSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SUM_MASK) >> CSR_SSTATUS_SUM_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. + * This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggeredwhen XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. + * Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * The same copy of XS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the XS bits to manage deferred context switches of ACE states. Machine mode software should be more conservative in managing context switches using XS bits + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_SSTATUS_XS_MASK (0x18000UL) +#define CSR_SSTATUS_XS_SHIFT (15U) +#define CSR_SSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_XS_MASK) >> CSR_SSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. + * This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * Otherwise, FS is updated to the Dirty state by any instruction that updates fcsr or any f register. + * Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * The same copy of FS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the FS bits to manage deferred context switches of FPU states. Machine mode software should be more conservative in managing context switches using FS bits. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_SSTATUS_FS_MASK (0x6000U) +#define CSR_SSTATUS_FS_SHIFT (13U) +#define CSR_SSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_SSTATUS_FS_SHIFT) & CSR_SSTATUS_FS_MASK) +#define CSR_SSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_FS_MASK) >> CSR_SSTATUS_FS_SHIFT) + +/* + * SPP (RW) + * + * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. + */ +#define CSR_SSTATUS_SPP_MASK (0x100U) +#define CSR_SSTATUS_SPP_SHIFT (8U) +#define CSR_SSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPP_SHIFT) & CSR_SSTATUS_SPP_MASK) +#define CSR_SSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPP_MASK) >> CSR_SSTATUS_SPP_SHIFT) + +/* + * SPIE (RW) + * + * SPIE holds the value of the SIE bit prior to a trap. + */ +#define CSR_SSTATUS_SPIE_MASK (0x20U) +#define CSR_SSTATUS_SPIE_SHIFT (5U) +#define CSR_SSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPIE_SHIFT) & CSR_SSTATUS_SPIE_MASK) +#define CSR_SSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPIE_MASK) >> CSR_SSTATUS_SPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_SSTATUS_UPIE_MASK (0x10U) +#define CSR_SSTATUS_UPIE_SHIFT (4U) +#define CSR_SSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UPIE_SHIFT) & CSR_SSTATUS_UPIE_MASK) +#define CSR_SSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UPIE_MASK) >> CSR_SSTATUS_UPIE_SHIFT) + +/* + * SIE (RW) + * + * S mode interrupt enable bit + * 0 Disabled + * 1 Enabled + */ +#define CSR_SSTATUS_SIE_MASK (0x2U) +#define CSR_SSTATUS_SIE_SHIFT (1U) +#define CSR_SSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SIE_SHIFT) & CSR_SSTATUS_SIE_MASK) +#define CSR_SSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SIE_MASK) >> CSR_SSTATUS_SIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0 Disabled + * 1 Enabled + */ +#define CSR_SSTATUS_UIE_MASK (0x1U) +#define CSR_SSTATUS_UIE_SHIFT (0U) +#define CSR_SSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UIE_SHIFT) & CSR_SSTATUS_UIE_MASK) +#define CSR_SSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UIE_MASK) >> CSR_SSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: SEDELEG */ +/* + * SPF (RW) + * + * SPF indicates whether a Store/AMO Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SPF_MASK (0x8000U) +#define CSR_SEDELEG_SPF_SHIFT (15U) +#define CSR_SEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SPF_SHIFT) & CSR_SEDELEG_SPF_MASK) +#define CSR_SEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SPF_MASK) >> CSR_SEDELEG_SPF_SHIFT) + +/* + * LPF (RW) + * + * LPF indicates whether a Load Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LPF_MASK (0x2000U) +#define CSR_SEDELEG_LPF_SHIFT (13U) +#define CSR_SEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LPF_SHIFT) & CSR_SEDELEG_LPF_MASK) +#define CSR_SEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LPF_MASK) >> CSR_SEDELEG_LPF_SHIFT) + +/* + * IPF (RW) + * + * IPF indicates whether an Instruction Page Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IPF_MASK (0x1000U) +#define CSR_SEDELEG_IPF_SHIFT (12U) +#define CSR_SEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IPF_SHIFT) & CSR_SEDELEG_IPF_MASK) +#define CSR_SEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IPF_MASK) >> CSR_SEDELEG_IPF_SHIFT) + +/* + * UEC (RW) + * + * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_UEC_MASK (0x100U) +#define CSR_SEDELEG_UEC_SHIFT (8U) +#define CSR_SEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_SEDELEG_UEC_SHIFT) & CSR_SEDELEG_UEC_MASK) +#define CSR_SEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_SEDELEG_UEC_MASK) >> CSR_SEDELEG_UEC_SHIFT) + +/* + * SAF (RW) + * + * SAF indicates whether a Store/AMO Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SAF_MASK (0x80U) +#define CSR_SEDELEG_SAF_SHIFT (7U) +#define CSR_SEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAF_SHIFT) & CSR_SEDELEG_SAF_MASK) +#define CSR_SEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAF_MASK) >> CSR_SEDELEG_SAF_SHIFT) + +/* + * SAM (RW) + * + * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_SAM_MASK (0x40U) +#define CSR_SEDELEG_SAM_SHIFT (6U) +#define CSR_SEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAM_SHIFT) & CSR_SEDELEG_SAM_MASK) +#define CSR_SEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAM_MASK) >> CSR_SEDELEG_SAM_SHIFT) + +/* + * LAF (RW) + * + * LAF indicates whether a Load Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LAF_MASK (0x20U) +#define CSR_SEDELEG_LAF_SHIFT (5U) +#define CSR_SEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAF_SHIFT) & CSR_SEDELEG_LAF_MASK) +#define CSR_SEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAF_MASK) >> CSR_SEDELEG_LAF_SHIFT) + +/* + * LAM (RW) + * + * LAM indicates whether a Load Address Misaligned exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_LAM_MASK (0x10U) +#define CSR_SEDELEG_LAM_SHIFT (4U) +#define CSR_SEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAM_SHIFT) & CSR_SEDELEG_LAM_MASK) +#define CSR_SEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAM_MASK) >> CSR_SEDELEG_LAM_SHIFT) + +/* + * B (RW) + * + * B indicates whether an exception triggered by breakpoint will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_B_MASK (0x8U) +#define CSR_SEDELEG_B_SHIFT (3U) +#define CSR_SEDELEG_B_SET(x) (((uint32_t)(x) << CSR_SEDELEG_B_SHIFT) & CSR_SEDELEG_B_MASK) +#define CSR_SEDELEG_B_GET(x) (((uint32_t)(x) & CSR_SEDELEG_B_MASK) >> CSR_SEDELEG_B_SHIFT) + +/* + * II (RW) + * + * II indicates whether an Illegal Instruction exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_II_MASK (0x4U) +#define CSR_SEDELEG_II_SHIFT (2U) +#define CSR_SEDELEG_II_SET(x) (((uint32_t)(x) << CSR_SEDELEG_II_SHIFT) & CSR_SEDELEG_II_MASK) +#define CSR_SEDELEG_II_GET(x) (((uint32_t)(x) & CSR_SEDELEG_II_MASK) >> CSR_SEDELEG_II_SHIFT) + +/* + * IAF (RW) + * + * IAF indicates whether an Instruction Access Fault exception will be delegated to U-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IAF_MASK (0x2U) +#define CSR_SEDELEG_IAF_SHIFT (1U) +#define CSR_SEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAF_SHIFT) & CSR_SEDELEG_IAF_MASK) +#define CSR_SEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAF_MASK) >> CSR_SEDELEG_IAF_SHIFT) + +/* + * IAM (RW) + * + * IAM indicates whether an Instruction Address Misaligned exception will be delegated to U-mode.. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SEDELEG_IAM_MASK (0x1U) +#define CSR_SEDELEG_IAM_SHIFT (0U) +#define CSR_SEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAM_SHIFT) & CSR_SEDELEG_IAM_MASK) +#define CSR_SEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAM_MASK) >> CSR_SEDELEG_IAM_SHIFT) + +/* Bitfield definition for register: SIDELEG */ +/* + * UEI (RW) + * + * UEI indicates whether an U-mode external interrupt will be delegated to S-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_UEI_MASK (0x100U) +#define CSR_SIDELEG_UEI_SHIFT (8U) +#define CSR_SIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UEI_SHIFT) & CSR_SIDELEG_UEI_MASK) +#define CSR_SIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UEI_MASK) >> CSR_SIDELEG_UEI_SHIFT) + +/* + * UTI (RW) + * + * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_UTI_MASK (0x10U) +#define CSR_SIDELEG_UTI_SHIFT (4U) +#define CSR_SIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UTI_SHIFT) & CSR_SIDELEG_UTI_MASK) +#define CSR_SIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UTI_MASK) >> CSR_SIDELEG_UTI_SHIFT) + +/* + * USI (RW) + * + * USI indicates whether an U-mode software interrupt will be delegated to S-mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_SIDELEG_USI_MASK (0x1U) +#define CSR_SIDELEG_USI_SHIFT (0U) +#define CSR_SIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_USI_SHIFT) & CSR_SIDELEG_USI_MASK) +#define CSR_SIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_USI_MASK) >> CSR_SIDELEG_USI_SHIFT) + +/* Bitfield definition for register: SIE */ +/* + * SEIE (RW) + * + * S mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_SEIE_MASK (0x200U) +#define CSR_SIE_SEIE_SHIFT (9U) +#define CSR_SIE_SEIE_SET(x) (((uint32_t)(x) << CSR_SIE_SEIE_SHIFT) & CSR_SIE_SEIE_MASK) +#define CSR_SIE_SEIE_GET(x) (((uint32_t)(x) & CSR_SIE_SEIE_MASK) >> CSR_SIE_SEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_UEIE_MASK (0x100U) +#define CSR_SIE_UEIE_SHIFT (8U) +#define CSR_SIE_UEIE_SET(x) (((uint32_t)(x) << CSR_SIE_UEIE_SHIFT) & CSR_SIE_UEIE_MASK) +#define CSR_SIE_UEIE_GET(x) (((uint32_t)(x) & CSR_SIE_UEIE_MASK) >> CSR_SIE_UEIE_SHIFT) + +/* + * STIE (RW) + * + * S mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_STIE_MASK (0x20U) +#define CSR_SIE_STIE_SHIFT (5U) +#define CSR_SIE_STIE_SET(x) (((uint32_t)(x) << CSR_SIE_STIE_SHIFT) & CSR_SIE_STIE_MASK) +#define CSR_SIE_STIE_GET(x) (((uint32_t)(x) & CSR_SIE_STIE_MASK) >> CSR_SIE_STIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_UTIE_MASK (0x10U) +#define CSR_SIE_UTIE_SHIFT (4U) +#define CSR_SIE_UTIE_SET(x) (((uint32_t)(x) << CSR_SIE_UTIE_SHIFT) & CSR_SIE_UTIE_MASK) +#define CSR_SIE_UTIE_GET(x) (((uint32_t)(x) & CSR_SIE_UTIE_MASK) >> CSR_SIE_UTIE_SHIFT) + +/* + * SSIE (RW) + * + * S mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_SSIE_MASK (0x2U) +#define CSR_SIE_SSIE_SHIFT (1U) +#define CSR_SIE_SSIE_SET(x) (((uint32_t)(x) << CSR_SIE_SSIE_SHIFT) & CSR_SIE_SSIE_MASK) +#define CSR_SIE_SSIE_GET(x) (((uint32_t)(x) & CSR_SIE_SSIE_MASK) >> CSR_SIE_SSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_SIE_USIE_MASK (0x1U) +#define CSR_SIE_USIE_SHIFT (0U) +#define CSR_SIE_USIE_SET(x) (((uint32_t)(x) << CSR_SIE_USIE_SHIFT) & CSR_SIE_USIE_MASK) +#define CSR_SIE_USIE_GET(x) (((uint32_t)(x) & CSR_SIE_USIE_MASK) >> CSR_SIE_USIE_SHIFT) + +/* Bitfield definition for register: STVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_STVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_STVEC_BASE_31_2_SHIFT (2U) +#define CSR_STVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_STVEC_BASE_31_2_SHIFT) & CSR_STVEC_BASE_31_2_MASK) +#define CSR_STVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_STVEC_BASE_31_2_MASK) >> CSR_STVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: SSCRATCH */ +/* + * SSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_SSCRATCH_SSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_SSCRATCH_SSCRATCH_SHIFT (0U) +#define CSR_SSCRATCH_SSCRATCH_SET(x) (((uint32_t)(x) << CSR_SSCRATCH_SSCRATCH_SHIFT) & CSR_SSCRATCH_SSCRATCH_MASK) +#define CSR_SSCRATCH_SSCRATCH_GET(x) (((uint32_t)(x) & CSR_SSCRATCH_SSCRATCH_MASK) >> CSR_SSCRATCH_SSCRATCH_SHIFT) + +/* Bitfield definition for register: SEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_SEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_SEPC_EPC_SHIFT (1U) +#define CSR_SEPC_EPC_SET(x) (((uint32_t)(x) << CSR_SEPC_EPC_SHIFT) & CSR_SEPC_EPC_MASK) +#define CSR_SEPC_EPC_GET(x) (((uint32_t)(x) & CSR_SEPC_EPC_MASK) >> CSR_SEPC_EPC_SHIFT) + +/* Bitfield definition for register: SCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_SCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_SCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_SCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_SCAUSE_INTERRUPT_SHIFT) & CSR_SCAUSE_INTERRUPT_MASK) +#define CSR_SCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_SCAUSE_INTERRUPT_MASK) >> CSR_SCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 256+16:Slave port ECC error interrupt (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt(S-mode) + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:10:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_SCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_SCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_SCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_SCAUSE_EXCEPTION_CODE_SHIFT) & CSR_SCAUSE_EXCEPTION_CODE_MASK) +#define CSR_SCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_SCAUSE_EXCEPTION_CODE_MASK) >> CSR_SCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: STVAL */ +/* + * STVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_STVAL_STVAL_MASK (0xFFFFFFFFUL) +#define CSR_STVAL_STVAL_SHIFT (0U) +#define CSR_STVAL_STVAL_SET(x) (((uint32_t)(x) << CSR_STVAL_STVAL_SHIFT) & CSR_STVAL_STVAL_MASK) +#define CSR_STVAL_STVAL_GET(x) (((uint32_t)(x) & CSR_STVAL_STVAL_MASK) >> CSR_STVAL_STVAL_SHIFT) + +/* Bitfield definition for register: SIP */ +/* + * SEIP (RO) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_SEIP_MASK (0x200U) +#define CSR_SIP_SEIP_SHIFT (9U) +#define CSR_SIP_SEIP_GET(x) (((uint32_t)(x) & CSR_SIP_SEIP_MASK) >> CSR_SIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_UEIP_MASK (0x100U) +#define CSR_SIP_UEIP_SHIFT (8U) +#define CSR_SIP_UEIP_SET(x) (((uint32_t)(x) << CSR_SIP_UEIP_SHIFT) & CSR_SIP_UEIP_MASK) +#define CSR_SIP_UEIP_GET(x) (((uint32_t)(x) & CSR_SIP_UEIP_MASK) >> CSR_SIP_UEIP_SHIFT) + +/* + * STIP (RO) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_STIP_MASK (0x20U) +#define CSR_SIP_STIP_SHIFT (5U) +#define CSR_SIP_STIP_GET(x) (((uint32_t)(x) & CSR_SIP_STIP_MASK) >> CSR_SIP_STIP_SHIFT) + +/* + * UTIP (RO) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_UTIP_MASK (0x10U) +#define CSR_SIP_UTIP_SHIFT (4U) +#define CSR_SIP_UTIP_GET(x) (((uint32_t)(x) & CSR_SIP_UTIP_MASK) >> CSR_SIP_UTIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_SSIP_MASK (0x2U) +#define CSR_SIP_SSIP_SHIFT (1U) +#define CSR_SIP_SSIP_SET(x) (((uint32_t)(x) << CSR_SIP_SSIP_SHIFT) & CSR_SIP_SSIP_MASK) +#define CSR_SIP_SSIP_GET(x) (((uint32_t)(x) & CSR_SIP_SSIP_MASK) >> CSR_SIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_SIP_USIP_MASK (0x1U) +#define CSR_SIP_USIP_SHIFT (0U) +#define CSR_SIP_USIP_SET(x) (((uint32_t)(x) << CSR_SIP_USIP_SHIFT) & CSR_SIP_USIP_MASK) +#define CSR_SIP_USIP_GET(x) (((uint32_t)(x) & CSR_SIP_USIP_MASK) >> CSR_SIP_USIP_SHIFT) + +/* Bitfield definition for register: SATP */ +/* + * MODE (RW) + * + * MODE holds the page translation mode. When MODE is Bare, virtual addresses are equal to physical addresses in S-mode. When MMU is + * not supported in the product, this CSR will be + * hardwired to 0. + * 0:No page translation + * 1:Page-based 32-bit virtual addressing + */ +#define CSR_SATP_MODE_MASK (0x80000000UL) +#define CSR_SATP_MODE_SHIFT (31U) +#define CSR_SATP_MODE_SET(x) (((uint32_t)(x) << CSR_SATP_MODE_SHIFT) & CSR_SATP_MODE_MASK) +#define CSR_SATP_MODE_GET(x) (((uint32_t)(x) & CSR_SATP_MODE_MASK) >> CSR_SATP_MODE_SHIFT) + +/* + * ASID (RW) + * + * ASID holds the address space identifier. + */ +#define CSR_SATP_ASID_MASK (0x7FC00000UL) +#define CSR_SATP_ASID_SHIFT (22U) +#define CSR_SATP_ASID_SET(x) (((uint32_t)(x) << CSR_SATP_ASID_SHIFT) & CSR_SATP_ASID_MASK) +#define CSR_SATP_ASID_GET(x) (((uint32_t)(x) & CSR_SATP_ASID_MASK) >> CSR_SATP_ASID_SHIFT) + +/* + * PPN (RW) + * + * PPN holds the physical page number of the root page table. + */ +#define CSR_SATP_PPN_MASK (0x3FFFFFUL) +#define CSR_SATP_PPN_SHIFT (0U) +#define CSR_SATP_PPN_SET(x) (((uint32_t)(x) << CSR_SATP_PPN_SHIFT) & CSR_SATP_PPN_MASK) +#define CSR_SATP_PPN_GET(x) (((uint32_t)(x) & CSR_SATP_PPN_MASK) >> CSR_SATP_PPN_SHIFT) + +/* Bitfield definition for register: MSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_MSTATUS_SD_MASK (0x80000000UL) +#define CSR_MSTATUS_SD_SHIFT (31U) +#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) + +/* + * TSR (RW) + * + * TSR controls whether executing SRET instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. + * 0: Normal execution + * 1: Raising exceptions + */ +#define CSR_MSTATUS_TSR_MASK (0x400000UL) +#define CSR_MSTATUS_TSR_SHIFT (22U) +#define CSR_MSTATUS_TSR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TSR_SHIFT) & CSR_MSTATUS_TSR_MASK) +#define CSR_MSTATUS_TSR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TSR_MASK) >> CSR_MSTATUS_TSR_SHIFT) + +/* + * TW (RW) + * + * TW controls whether executing WFI instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. + * 0: Normal execution + * 1: Raising exceptions + */ +#define CSR_MSTATUS_TW_MASK (0x200000UL) +#define CSR_MSTATUS_TW_SHIFT (21U) +#define CSR_MSTATUS_TW_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TW_SHIFT) & CSR_MSTATUS_TW_MASK) +#define CSR_MSTATUS_TW_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TW_MASK) >> CSR_MSTATUS_TW_SHIFT) + +/* + * TVM (RW) + * + * TVM controls whether performing certain virtual memory operations in S-mode will raise illegal instruction exceptions. The operations include accessing the satp register and executing the SFENCE.VMA instruction. It is hardwired to 0 when S-mode is not supported. + * 0:Normal execution + * 1:Raising exceptions + */ +#define CSR_MSTATUS_TVM_MASK (0x100000UL) +#define CSR_MSTATUS_TVM_SHIFT (20U) +#define CSR_MSTATUS_TVM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TVM_SHIFT) & CSR_MSTATUS_TVM_MASK) +#define CSR_MSTATUS_TVM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TVM_MASK) >> CSR_MSTATUS_TVM_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_MSTATUS_MXR_MASK (0x80000UL) +#define CSR_MSTATUS_MXR_SHIFT (19U) +#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) +#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) + +/* + * SUM (RW) + * + * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. It is hardwired to 0 when S-mode is not supported. + * 0:Not Allowed + * 1:Allowed + */ +#define CSR_MSTATUS_SUM_MASK (0x40000UL) +#define CSR_MSTATUS_SUM_SHIFT (18U) +#define CSR_MSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SUM_SHIFT) & CSR_MSTATUS_SUM_MASK) +#define CSR_MSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SUM_MASK) >> CSR_MSTATUS_SUM_SHIFT) + +/* + * MPRV (RW) + * + * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. + */ +#define CSR_MSTATUS_MPRV_MASK (0x20000UL) +#define CSR_MSTATUS_MPRV_SHIFT (17U) +#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) +#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggered when XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_XS_MASK (0x18000UL) +#define CSR_MSTATUS_XS_SHIFT (15U) +#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state + * managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_FS_MASK (0x6000U) +#define CSR_MSTATUS_FS_SHIFT (13U) +#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) +#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) + +/* + * MPP (RW) + * + * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. + */ +#define CSR_MSTATUS_MPP_MASK (0x1800U) +#define CSR_MSTATUS_MPP_SHIFT (11U) +#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) +#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) + +/* + * SPP (RW) + * + * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. + */ +#define CSR_MSTATUS_SPP_MASK (0x100U) +#define CSR_MSTATUS_SPP_SHIFT (8U) +#define CSR_MSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPP_SHIFT) & CSR_MSTATUS_SPP_MASK) +#define CSR_MSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPP_MASK) >> CSR_MSTATUS_SPP_SHIFT) + +/* + * MPIE (RW) + * + * MPIE holds the value of the MIE bit prior to a trap. + */ +#define CSR_MSTATUS_MPIE_MASK (0x80U) +#define CSR_MSTATUS_MPIE_SHIFT (7U) +#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) +#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) + +/* + * SPIE (RW) + * + * SPIE holds the value of the SIE bit prior to a trap. + */ +#define CSR_MSTATUS_SPIE_MASK (0x20U) +#define CSR_MSTATUS_SPIE_SHIFT (5U) +#define CSR_MSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPIE_SHIFT) & CSR_MSTATUS_SPIE_MASK) +#define CSR_MSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPIE_MASK) >> CSR_MSTATUS_SPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_MSTATUS_UPIE_MASK (0x10U) +#define CSR_MSTATUS_UPIE_SHIFT (4U) +#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) +#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) + +/* + * MIE (RW) + * + * M mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_MIE_MASK (0x8U) +#define CSR_MSTATUS_MIE_SHIFT (3U) +#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) +#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) + +/* + * SIE (RW) + * + * S mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_SIE_MASK (0x2U) +#define CSR_MSTATUS_SIE_SHIFT (1U) +#define CSR_MSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SIE_SHIFT) & CSR_MSTATUS_SIE_MASK) +#define CSR_MSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SIE_MASK) >> CSR_MSTATUS_SIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_UIE_MASK (0x1U) +#define CSR_MSTATUS_UIE_SHIFT (0U) +#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) +#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: MISA */ +/* + * BASE (RO) + * + * The general-purpose register width of the native base integer ISA. + * 0:Reserved + * 1:32 + * 2:64 + * 3:128 + */ +#define CSR_MISA_BASE_MASK (0xC0000000UL) +#define CSR_MISA_BASE_SHIFT (30U) +#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) + +/* + * Z (RO) + * + * Reserved + */ +#define CSR_MISA_Z_MASK (0x2000000UL) +#define CSR_MISA_Z_SHIFT (25U) +#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) + +/* + * Y (RO) + * + * Reserved + */ +#define CSR_MISA_Y_MASK (0x1000000UL) +#define CSR_MISA_Y_SHIFT (24U) +#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) + +/* + * X (RO) + * + * Non-standard extensions present + */ +#define CSR_MISA_X_MASK (0x800000UL) +#define CSR_MISA_X_SHIFT (23U) +#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) + +/* + * W (RO) + * + * Reserved + */ +#define CSR_MISA_W_MASK (0x400000UL) +#define CSR_MISA_W_SHIFT (22U) +#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) + +/* + * V (RO) + * + * Tentatively reserved for Vector extension + */ +#define CSR_MISA_V_MASK (0x200000UL) +#define CSR_MISA_V_SHIFT (21U) +#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) + +/* + * U (RO) + * + * User mode implemented + * 0:Machine + * 1:Machine + User / Machine + Supervisor + User + */ +#define CSR_MISA_U_MASK (0x100000UL) +#define CSR_MISA_U_SHIFT (20U) +#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) + +/* + * T (RO) + * + * Tentatively reserved for Transactional Memory extension + */ +#define CSR_MISA_T_MASK (0x80000UL) +#define CSR_MISA_T_SHIFT (19U) +#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) + +/* + * S (RO) + * + * Supervisor mode implemented + * 0:Machine / Machine + User + * 1:Machine + Supervisor + User + */ +#define CSR_MISA_S_MASK (0x40000UL) +#define CSR_MISA_S_SHIFT (18U) +#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) + +/* + * R (RO) + * + * Reserved + */ +#define CSR_MISA_R_MASK (0x20000UL) +#define CSR_MISA_R_SHIFT (17U) +#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) + +/* + * Q (RO) + * + * Quad-precision floating-point extension + */ +#define CSR_MISA_Q_MASK (0x10000UL) +#define CSR_MISA_Q_SHIFT (16U) +#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) + +/* + * P (RO) + * + * Tentatively reserved for Packed-SIMD extension + */ +#define CSR_MISA_P_MASK (0x8000U) +#define CSR_MISA_P_SHIFT (15U) +#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) + +/* + * O (RO) + * + * Reserved + */ +#define CSR_MISA_O_MASK (0x4000U) +#define CSR_MISA_O_SHIFT (14U) +#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) + +/* + * N (RO) + * + * User-level interrupts supported + * 0:no + * 1:yes + */ +#define CSR_MISA_N_MASK (0x2000U) +#define CSR_MISA_N_SHIFT (13U) +#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) + +/* + * M (RO) + * + * Integer Multiply/Divide extension + */ +#define CSR_MISA_M_MASK (0x1000U) +#define CSR_MISA_M_SHIFT (12U) +#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) + +/* + * L (RO) + * + * Tentatively reserved for Decimal Floating-Point extension + */ +#define CSR_MISA_L_MASK (0x800U) +#define CSR_MISA_L_SHIFT (11U) +#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) + +/* + * K (RO) + * + * Reserved + */ +#define CSR_MISA_K_MASK (0x400U) +#define CSR_MISA_K_SHIFT (10U) +#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) + +/* + * J (RO) + * + * Tentatively reserved for Dynamically Translated Languages extension + */ +#define CSR_MISA_J_MASK (0x200U) +#define CSR_MISA_J_SHIFT (9U) +#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) + +/* + * I (RO) + * + * RV32I/64I/128I base ISA + */ +#define CSR_MISA_I_MASK (0x100U) +#define CSR_MISA_I_SHIFT (8U) +#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) + +/* + * H (RO) + * + * Reserved + */ +#define CSR_MISA_H_MASK (0x80U) +#define CSR_MISA_H_SHIFT (7U) +#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) + +/* + * G (RO) + * + * Additional standard extensions present + */ +#define CSR_MISA_G_MASK (0x40U) +#define CSR_MISA_G_SHIFT (6U) +#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) + +/* + * F (RO) + * + * Single-precision floating-point extension + * 0:none + * 1:double+single precision / single precision + */ +#define CSR_MISA_F_MASK (0x20U) +#define CSR_MISA_F_SHIFT (5U) +#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) + +/* + * E (RO) + * + * RV32E base ISA + */ +#define CSR_MISA_E_MASK (0x10U) +#define CSR_MISA_E_SHIFT (4U) +#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) + +/* + * D (RO) + * + * Double-precision floating-point extension + * 0:single precision / none + * 1:double+single precision + */ +#define CSR_MISA_D_MASK (0x8U) +#define CSR_MISA_D_SHIFT (3U) +#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) + +/* + * C (RO) + * + * Compressed extension + */ +#define CSR_MISA_C_MASK (0x4U) +#define CSR_MISA_C_SHIFT (2U) +#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) + +/* + * B (RO) + * + * Tentatively reserved for Bit operations extension + */ +#define CSR_MISA_B_MASK (0x2U) +#define CSR_MISA_B_SHIFT (1U) +#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) + +/* + * A (RO) + * + * Atomic extension + * 0:no + * 1:yes + */ +#define CSR_MISA_A_MASK (0x1U) +#define CSR_MISA_A_SHIFT (0U) +#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) + +/* Bitfield definition for register: MEDELEG */ +/* + * SPF (RW) + * + * SPF indicates whether a Store/AMO Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SPF_MASK (0x8000U) +#define CSR_MEDELEG_SPF_SHIFT (15U) +#define CSR_MEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SPF_SHIFT) & CSR_MEDELEG_SPF_MASK) +#define CSR_MEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SPF_MASK) >> CSR_MEDELEG_SPF_SHIFT) + +/* + * LPF (RW) + * + * LPF indicates whether a Load Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LPF_MASK (0x2000U) +#define CSR_MEDELEG_LPF_SHIFT (13U) +#define CSR_MEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LPF_SHIFT) & CSR_MEDELEG_LPF_MASK) +#define CSR_MEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LPF_MASK) >> CSR_MEDELEG_LPF_SHIFT) + +/* + * IPF (RW) + * + * IPF indicates whether an Instruction Page Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IPF_MASK (0x1000U) +#define CSR_MEDELEG_IPF_SHIFT (12U) +#define CSR_MEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IPF_SHIFT) & CSR_MEDELEG_IPF_MASK) +#define CSR_MEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IPF_MASK) >> CSR_MEDELEG_IPF_SHIFT) + +/* + * SEC (RW) + * + * SEC indicates whether an exception triggered by environment call from S-mode will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SEC_MASK (0x200U) +#define CSR_MEDELEG_SEC_SHIFT (9U) +#define CSR_MEDELEG_SEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SEC_SHIFT) & CSR_MEDELEG_SEC_MASK) +#define CSR_MEDELEG_SEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SEC_MASK) >> CSR_MEDELEG_SEC_SHIFT) + +/* + * UEC (RW) + * + * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_UEC_MASK (0x100U) +#define CSR_MEDELEG_UEC_SHIFT (8U) +#define CSR_MEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_UEC_SHIFT) & CSR_MEDELEG_UEC_MASK) +#define CSR_MEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_UEC_MASK) >> CSR_MEDELEG_UEC_SHIFT) + +/* + * SAF (RW) + * + * SAF indicates whether a Store/AMO Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SAF_MASK (0x80U) +#define CSR_MEDELEG_SAF_SHIFT (7U) +#define CSR_MEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAF_SHIFT) & CSR_MEDELEG_SAF_MASK) +#define CSR_MEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAF_MASK) >> CSR_MEDELEG_SAF_SHIFT) + +/* + * SAM (RW) + * + * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to S-mode + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_SAM_MASK (0x40U) +#define CSR_MEDELEG_SAM_SHIFT (6U) +#define CSR_MEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAM_SHIFT) & CSR_MEDELEG_SAM_MASK) +#define CSR_MEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAM_MASK) >> CSR_MEDELEG_SAM_SHIFT) + +/* + * LAF (RW) + * + * LAF indicates whether a Load Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LAF_MASK (0x20U) +#define CSR_MEDELEG_LAF_SHIFT (5U) +#define CSR_MEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAF_SHIFT) & CSR_MEDELEG_LAF_MASK) +#define CSR_MEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAF_MASK) >> CSR_MEDELEG_LAF_SHIFT) + +/* + * LAM (RW) + * + * LAM indicates whether a Load Address Misaligned exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_LAM_MASK (0x10U) +#define CSR_MEDELEG_LAM_SHIFT (4U) +#define CSR_MEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAM_SHIFT) & CSR_MEDELEG_LAM_MASK) +#define CSR_MEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAM_MASK) >> CSR_MEDELEG_LAM_SHIFT) + +/* + * II (RW) + * + * II indicates whether an Illegal Instruction exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_II_MASK (0x4U) +#define CSR_MEDELEG_II_SHIFT (2U) +#define CSR_MEDELEG_II_SET(x) (((uint32_t)(x) << CSR_MEDELEG_II_SHIFT) & CSR_MEDELEG_II_MASK) +#define CSR_MEDELEG_II_GET(x) (((uint32_t)(x) & CSR_MEDELEG_II_MASK) >> CSR_MEDELEG_II_SHIFT) + +/* + * IAF (RW) + * + * IAF indicates whether an Instruction Access Fault exception will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IAF_MASK (0x2U) +#define CSR_MEDELEG_IAF_SHIFT (1U) +#define CSR_MEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAF_SHIFT) & CSR_MEDELEG_IAF_MASK) +#define CSR_MEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAF_MASK) >> CSR_MEDELEG_IAF_SHIFT) + +/* + * IAM (RW) + * + * IAM indicates whether an Instruction Address Misaligned exception will be delegated to S-Mode + * 0:Not delegate + * 1:delegate + */ +#define CSR_MEDELEG_IAM_MASK (0x1U) +#define CSR_MEDELEG_IAM_SHIFT (0U) +#define CSR_MEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAM_SHIFT) & CSR_MEDELEG_IAM_MASK) +#define CSR_MEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAM_MASK) >> CSR_MEDELEG_IAM_SHIFT) + +/* Bitfield definition for register: MIDELEG */ +/* + * SEI (RW) + * + * SEI indicates whether an S-mode external interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_SEI_MASK (0x200U) +#define CSR_MIDELEG_SEI_SHIFT (9U) +#define CSR_MIDELEG_SEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SEI_SHIFT) & CSR_MIDELEG_SEI_MASK) +#define CSR_MIDELEG_SEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SEI_MASK) >> CSR_MIDELEG_SEI_SHIFT) + +/* + * UEI (RW) + * + * UEI indicates whether an U-mode external interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_UEI_MASK (0x100U) +#define CSR_MIDELEG_UEI_SHIFT (8U) +#define CSR_MIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UEI_SHIFT) & CSR_MIDELEG_UEI_MASK) +#define CSR_MIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UEI_MASK) >> CSR_MIDELEG_UEI_SHIFT) + +/* + * STI (RW) + * + * STI indicates whether an S-mode timer interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_STI_MASK (0x20U) +#define CSR_MIDELEG_STI_SHIFT (5U) +#define CSR_MIDELEG_STI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_STI_SHIFT) & CSR_MIDELEG_STI_MASK) +#define CSR_MIDELEG_STI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_STI_MASK) >> CSR_MIDELEG_STI_SHIFT) + +/* + * UTI (RW) + * + * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_UTI_MASK (0x10U) +#define CSR_MIDELEG_UTI_SHIFT (4U) +#define CSR_MIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UTI_SHIFT) & CSR_MIDELEG_UTI_MASK) +#define CSR_MIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UTI_MASK) >> CSR_MIDELEG_UTI_SHIFT) + +/* + * SSI (RW) + * + * SSI indicates whether an S-mode software interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_SSI_MASK (0x2U) +#define CSR_MIDELEG_SSI_SHIFT (1U) +#define CSR_MIDELEG_SSI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SSI_SHIFT) & CSR_MIDELEG_SSI_MASK) +#define CSR_MIDELEG_SSI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SSI_MASK) >> CSR_MIDELEG_SSI_SHIFT) + +/* + * USI (RW) + * + * USI indicates whether an U-mode software interrupt will be delegated to S-mode. + * 0:Not delegate + * 1:delegate + */ +#define CSR_MIDELEG_USI_MASK (0x1U) +#define CSR_MIDELEG_USI_SHIFT (0U) +#define CSR_MIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_USI_SHIFT) & CSR_MIDELEG_USI_MASK) +#define CSR_MIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_USI_MASK) >> CSR_MIDELEG_USI_SHIFT) + +/* Bitfield definition for register: MIE */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_PMOVI_MASK (0x40000UL) +#define CSR_MIE_PMOVI_SHIFT (18U) +#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) +#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_BWEI_MASK (0x20000UL) +#define CSR_MIE_BWEI_SHIFT (17U) +#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) +#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_IMECCI_MASK (0x10000UL) +#define CSR_MIE_IMECCI_SHIFT (16U) +#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) +#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) + +/* + * MEIE (RW) + * + * M mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MEIE_MASK (0x800U) +#define CSR_MIE_MEIE_SHIFT (11U) +#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) +#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) + +/* + * SEIE (RW) + * + * S mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_SEIE_MASK (0x200U) +#define CSR_MIE_SEIE_SHIFT (9U) +#define CSR_MIE_SEIE_SET(x) (((uint32_t)(x) << CSR_MIE_SEIE_SHIFT) & CSR_MIE_SEIE_MASK) +#define CSR_MIE_SEIE_GET(x) (((uint32_t)(x) & CSR_MIE_SEIE_MASK) >> CSR_MIE_SEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UEIE_MASK (0x100U) +#define CSR_MIE_UEIE_SHIFT (8U) +#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) +#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) + +/* + * MTIE (RW) + * + * M mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MTIE_MASK (0x80U) +#define CSR_MIE_MTIE_SHIFT (7U) +#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) +#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) + +/* + * STIE (RW) + * + * S mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_STIE_MASK (0x20U) +#define CSR_MIE_STIE_SHIFT (5U) +#define CSR_MIE_STIE_SET(x) (((uint32_t)(x) << CSR_MIE_STIE_SHIFT) & CSR_MIE_STIE_MASK) +#define CSR_MIE_STIE_GET(x) (((uint32_t)(x) & CSR_MIE_STIE_MASK) >> CSR_MIE_STIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UTIE_MASK (0x10U) +#define CSR_MIE_UTIE_SHIFT (4U) +#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) +#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) + +/* + * MSIE (RW) + * + * M mode software interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MSIE_MASK (0x8U) +#define CSR_MIE_MSIE_SHIFT (3U) +#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) +#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) + +/* + * SSIE (RW) + * + * S mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_SSIE_MASK (0x2U) +#define CSR_MIE_SSIE_SHIFT (1U) +#define CSR_MIE_SSIE_SET(x) (((uint32_t)(x) << CSR_MIE_SSIE_SHIFT) & CSR_MIE_SSIE_MASK) +#define CSR_MIE_SSIE_GET(x) (((uint32_t)(x) & CSR_MIE_SSIE_MASK) >> CSR_MIE_SSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_USIE_MASK (0x1U) +#define CSR_MIE_USIE_SHIFT (0U) +#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) +#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) + +/* Bitfield definition for register: MTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode + */ +#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_MTVEC_BASE_31_2_SHIFT (2U) +#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) +#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: MCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) +#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) +#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) +#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) +#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_IR_MASK (0x4U) +#define CSR_MCOUNTEREN_IR_SHIFT (2U) +#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) +#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_TM_MASK (0x2U) +#define CSR_MCOUNTEREN_TM_SHIFT (1U) +#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) +#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_CY_MASK (0x1U) +#define CSR_MCOUNTEREN_CY_SHIFT (0U) +#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) +#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT3_SEL_SHIFT (4U) +#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) +#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) +#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT4_SEL_SHIFT (4U) +#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) +#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) +#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT5_SEL_SHIFT (4U) +#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) +#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) +#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT6_SEL_SHIFT (4U) +#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) +#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) +#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MSCRATCH */ +/* + * MSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) +#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) +#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) + +/* Bitfield definition for register: MEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_MEPC_EPC_SHIFT (1U) +#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) +#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) + +/* Bitfield definition for register: MCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt + */ +#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) +#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception code + * When interrupt is 1, the value means: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 3:Machine software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 7:Machine timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 11:Machine external interrupt + * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) + * 17:Bus read/write transaction error interrupt (M-mode) + * 18:Performance monitor overflow interrupt (M-mode) + * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt (S-mode) + * When interrupt bit is 0, the value means: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:Environment call from M-mode + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) +#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) +#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: MTVAL */ +/* + * MTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) +#define CSR_MTVAL_MTVAL_SHIFT (0U) +#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) +#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) + +/* Bitfield definition for register: MIP */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_PMOVI_MASK (0x40000UL) +#define CSR_MIP_PMOVI_SHIFT (18U) +#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) +#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_BWEI_MASK (0x20000UL) +#define CSR_MIP_BWEI_SHIFT (17U) +#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) +#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_IMECCI_MASK (0x10000UL) +#define CSR_MIP_IMECCI_SHIFT (16U) +#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) +#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) + +/* + * MEIP (RW) + * + * M mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MEIP_MASK (0x800U) +#define CSR_MIP_MEIP_SHIFT (11U) +#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) +#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) + +/* + * SEIP (RW) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SEIP_MASK (0x200U) +#define CSR_MIP_SEIP_SHIFT (9U) +#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) +#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UEIP_MASK (0x100U) +#define CSR_MIP_UEIP_SHIFT (8U) +#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) +#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) + +/* + * MTIP (RW) + * + * M mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MTIP_MASK (0x80U) +#define CSR_MIP_MTIP_SHIFT (7U) +#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) +#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) + +/* + * STIP (RW) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_STIP_MASK (0x20U) +#define CSR_MIP_STIP_SHIFT (5U) +#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) +#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UTIP_MASK (0x10U) +#define CSR_MIP_UTIP_SHIFT (4U) +#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) +#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) + +/* + * MSIP (RW) + * + * M mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MSIP_MASK (0x8U) +#define CSR_MIP_MSIP_SHIFT (3U) +#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) +#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SSIP_MASK (0x2U) +#define CSR_MIP_SSIP_SHIFT (1U) +#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) +#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_USIP_MASK (0x1U) +#define CSR_MIP_USIP_SHIFT (0U) +#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) +#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) + +/* Bitfield definition for register: PMPCFG0 */ +/* + * PMP3CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) +#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) +#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) + +/* + * PMP2CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) +#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) +#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) + +/* + * PMP1CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) +#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) +#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) +#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) + +/* + * PMP0CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) +#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) +#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) +#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG1 */ +/* + * PMP7CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) +#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) +#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) + +/* + * PMP6CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) +#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) +#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) + +/* + * PMP5CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) +#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) +#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) +#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) + +/* + * PMP4CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) +#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) +#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) +#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG2 */ +/* + * PMP11CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) +#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) +#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) + +/* + * PMP10CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) +#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) +#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) + +/* + * PMP9CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) +#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) +#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) +#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) + +/* + * PMP8CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) +#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) +#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) +#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG3 */ +/* + * PMP15CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) +#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) +#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) + +/* + * PMP14CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) +#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) +#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) + +/* + * PMP13CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) +#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) +#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) +#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) + +/* + * PMP12CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) +#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) +#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) +#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaa0 8 + * aaaa. . . aa01 16 + * aaaa. . . a011 32 + * . . . . . . + * aa01. . . 1111 2^{XLEN} + * a011. . . 1111 2^{XLEN+1} + * 0111. . . 1111 2^{XLEN+2} + * 1111. . . 1111 2^{XLEN+3*1} + */ +#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) +#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) +#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) +#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) +#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) +#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) +#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) +#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) +#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) +#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) +#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) +#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) +#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) +#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) +#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) +#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) +#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register: TSELECT */ +/* + * TRIGGER_INDEX (RW) + * + * This register determines which trigger is accessible through other trigger registers. + */ +#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) +#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) +#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) +#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) + +/* Bitfield definition for register: TDATA1 */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + * 3:The selected trigger is an instruction count trigger + * 4:The selected trigger is an interrupt trigger. + * 5:The selected trigger is an exception trigger. + */ +#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) +#define CSR_TDATA1_TYPE_SHIFT (28U) +#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) +#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_TDATA1_DMODE_MASK (0x8000000UL) +#define CSR_TDATA1_DMODE_SHIFT (27U) +#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) +#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) + +/* + * DATA (RW) + * + * Trigger-specific data + */ +#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) +#define CSR_TDATA1_DATA_SHIFT (0U) +#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) +#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) + +/* Bitfield definition for register: MCONTROL */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + */ +#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) +#define CSR_MCONTROL_TYPE_SHIFT (28U) +#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) +#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) +#define CSR_MCONTROL_DMODE_SHIFT (27U) +#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) +#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) + +/* + * MASKMAX (RO) + * + * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. + */ +#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) +#define CSR_MCONTROL_MASKMAX_SHIFT (21U) +#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_MCONTROL_ACTION_MASK (0xF000U) +#define CSR_MCONTROL_ACTION_SHIFT (12U) +#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) +#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) + +/* + * CHAIN (RW) + * + * Setting this field to enable trigger chain. + * 0:When this trigger matches, the configured action is taken. + * 1:While this trigger does not match, it prevents the trigger with the next index from matching. + * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). + * If Number of Triggers is 4, this field is hardwired + * to 0 on trigger 3 (tselect = 3). + * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). + */ +#define CSR_MCONTROL_CHAIN_MASK (0x800U) +#define CSR_MCONTROL_CHAIN_SHIFT (11U) +#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) +#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) + +/* + * MATCH (RW) + * + * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. + * 2:Matches when the value is greater than (unsigned) or equal to tdata2. + * 3:Matches when the value is less than (unsigned) tdata2 + */ +#define CSR_MCONTROL_MATCH_MASK (0x780U) +#define CSR_MCONTROL_MATCH_SHIFT (7U) +#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) +#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_MCONTROL_M_MASK (0x40U) +#define CSR_MCONTROL_M_SHIFT (6U) +#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) +#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_MCONTROL_S_MASK (0x10U) +#define CSR_MCONTROL_S_SHIFT (4U) +#define CSR_MCONTROL_S_SET(x) (((uint32_t)(x) << CSR_MCONTROL_S_SHIFT) & CSR_MCONTROL_S_MASK) +#define CSR_MCONTROL_S_GET(x) (((uint32_t)(x) & CSR_MCONTROL_S_MASK) >> CSR_MCONTROL_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_MCONTROL_U_MASK (0x8U) +#define CSR_MCONTROL_U_SHIFT (3U) +#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) +#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) + +/* + * EXECUTE (RW) + * + * Setting this field to enable this trigger to compare virtual address of an instruction. + */ +#define CSR_MCONTROL_EXECUTE_MASK (0x4U) +#define CSR_MCONTROL_EXECUTE_SHIFT (2U) +#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) +#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) + +/* + * STORE (RW) + * + * Setting this field to enable this trigger to compare virtual address of a store. + */ +#define CSR_MCONTROL_STORE_MASK (0x2U) +#define CSR_MCONTROL_STORE_SHIFT (1U) +#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) +#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) + +/* + * LOAD (RW) + * + * Setting this field to enable this trigger to compare virtual address of a load. + */ +#define CSR_MCONTROL_LOAD_MASK (0x1U) +#define CSR_MCONTROL_LOAD_SHIFT (0U) +#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) +#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) + +/* Bitfield definition for register: ICOUNT */ +/* + * TYPE (RW) + * + * The selected trigger is an instruction count trigger. + */ +#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) +#define CSR_ICOUNT_TYPE_SHIFT (28U) +#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) +#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) +#define CSR_ICOUNT_DMODE_SHIFT (27U) +#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) +#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) + +/* + * COUNT (RO) + * + * This field is hardwired to 1 for single-stepping support + */ +#define CSR_ICOUNT_COUNT_MASK (0x400U) +#define CSR_ICOUNT_COUNT_SHIFT (10U) +#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ICOUNT_M_MASK (0x200U) +#define CSR_ICOUNT_M_SHIFT (9U) +#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) +#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ICOUNT_S_MASK (0x80U) +#define CSR_ICOUNT_S_SHIFT (7U) +#define CSR_ICOUNT_S_SET(x) (((uint32_t)(x) << CSR_ICOUNT_S_SHIFT) & CSR_ICOUNT_S_MASK) +#define CSR_ICOUNT_S_GET(x) (((uint32_t)(x) & CSR_ICOUNT_S_MASK) >> CSR_ICOUNT_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ICOUNT_U_MASK (0x40U) +#define CSR_ICOUNT_U_SHIFT (6U) +#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) +#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ICOUNT_ACTION_MASK (0x3FU) +#define CSR_ICOUNT_ACTION_SHIFT (0U) +#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) +#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) + +/* Bitfield definition for register: ITRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an interrupt trigger. + */ +#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ITRIGGER_TYPE_SHIFT (28U) +#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) +#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ITRIGGER_DMODE_SHIFT (27U) +#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) +#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ITRIGGER_M_MASK (0x200U) +#define CSR_ITRIGGER_M_SHIFT (9U) +#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) +#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ITRIGGER_S_MASK (0x80U) +#define CSR_ITRIGGER_S_SHIFT (7U) +#define CSR_ITRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_S_SHIFT) & CSR_ITRIGGER_S_MASK) +#define CSR_ITRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_S_MASK) >> CSR_ITRIGGER_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ITRIGGER_U_MASK (0x40U) +#define CSR_ITRIGGER_U_SHIFT (6U) +#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) +#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception. + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ITRIGGER_ACTION_MASK (0x3FU) +#define CSR_ITRIGGER_ACTION_SHIFT (0U) +#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) +#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: ETRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an exception trigger. + */ +#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ETRIGGER_TYPE_SHIFT (28U) +#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) +#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ETRIGGER_DMODE_SHIFT (27U) +#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) +#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) + +/* + * NMI (RW) + * + * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. + */ +#define CSR_ETRIGGER_NMI_MASK (0x400U) +#define CSR_ETRIGGER_NMI_SHIFT (10U) +#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) +#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ETRIGGER_M_MASK (0x200U) +#define CSR_ETRIGGER_M_SHIFT (9U) +#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) +#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) + +/* + * S (RW) + * + * Setting this field to enable this trigger in S-mode. + */ +#define CSR_ETRIGGER_S_MASK (0x80U) +#define CSR_ETRIGGER_S_SHIFT (7U) +#define CSR_ETRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_S_SHIFT) & CSR_ETRIGGER_S_MASK) +#define CSR_ETRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_S_MASK) >> CSR_ETRIGGER_S_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ETRIGGER_U_MASK (0x40U) +#define CSR_ETRIGGER_U_SHIFT (6U) +#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) +#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ETRIGGER_ACTION_MASK (0x3FU) +#define CSR_ETRIGGER_ACTION_SHIFT (0U) +#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) +#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: TDATA2 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA2_DATA_SHIFT (0U) +#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) +#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) + +/* Bitfield definition for register: TDATA3 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA3_DATA_SHIFT (0U) +#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) +#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) + +/* Bitfield definition for register: TEXTRA */ +/* + * MVALUE (RW) + * + * Data used together with MSELECT. + */ +#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) +#define CSR_TEXTRA_MVALUE_SHIFT (26U) +#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) +#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) + +/* + * MSELECT (RW) + * + * 0:Ignore MVALUE. + * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. + */ +#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) +#define CSR_TEXTRA_MSELECT_SHIFT (25U) +#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) +#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) + +/* + * SVALUE (RW) + * + * Data used together with SSELECT. + */ +#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) +#define CSR_TEXTRA_SVALUE_SHIFT (2U) +#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) +#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) + +/* + * SSELECT (RW) + * + * 0:Ignore MVALUE + * 1:This trigger will only match if the lower bits of scontext equal SVALUE + * 2This trigger will only match if satp.ASID equals SVALUE. + */ +#define CSR_TEXTRA_SSELECT_MASK (0x3U) +#define CSR_TEXTRA_SSELECT_SHIFT (0U) +#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) +#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) + +/* Bitfield definition for register: TINFO */ +/* + * INFO (RO) + * + * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that + * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. + * 0:When this bit is set, there is no trigger at this tselect + * 1:Reserved and hardwired to 0. + * 2：When this bit is set, the selected trigger supports type of address/data match trigger + * 3:When this bit is set, the selected trigger supports type of instruction count trigger. + * 4:When this bit is set, the selected trigger supports type of interrupt trigger + * 5:When this bit is set, the selected trigger supports type of exception trigger + * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. + * Others:Reserved for future use. + */ +#define CSR_TINFO_INFO_MASK (0xFFFFU) +#define CSR_TINFO_INFO_SHIFT (0U) +#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) + +/* Bitfield definition for register: TCONTROL */ +/* + * MPTE (RW) + * + * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. + */ +#define CSR_TCONTROL_MPTE_MASK (0x80U) +#define CSR_TCONTROL_MPTE_SHIFT (7U) +#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) +#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) + +/* + * MTE (RW) + * + * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. + * 0:Triggers do not match/fire while the hart is in M-mode. + * 1:Triggers do match/fire while the hart is in M-mode. + */ +#define CSR_TCONTROL_MTE_MASK (0x8U) +#define CSR_TCONTROL_MTE_SHIFT (3U) +#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) +#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) + +/* Bitfield definition for register: MCONTEXT */ +/* + * MCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) +#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) +#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) +#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) + +/* Bitfield definition for register: SCONTEXT */ +/* + * SCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) +#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) +#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) +#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) + +/* Bitfield definition for register: DCSR */ +/* + * XDEBUGVER (RO) + * + * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 + */ +#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) +#define CSR_DCSR_XDEBUGVER_SHIFT (28U) +#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) + +/* + * EBREAKM (RW) + * + * This bit controls the behavior of EBREAK instructions in Machine Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKM_MASK (0x8000U) +#define CSR_DCSR_EBREAKM_SHIFT (15U) +#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) +#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) + +/* + * EBREAKS (RW) + * + * This bit controls the behavior of EBREAK instructions in Supervisor Mode. + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKS_MASK (0x2000U) +#define CSR_DCSR_EBREAKS_SHIFT (13U) +#define CSR_DCSR_EBREAKS_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKS_SHIFT) & CSR_DCSR_EBREAKS_MASK) +#define CSR_DCSR_EBREAKS_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKS_MASK) >> CSR_DCSR_EBREAKS_SHIFT) + +/* + * EBREAKU (RW) + * + * This bit controls the behavior of EBREAK instructions in User/Application Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKU_MASK (0x1000U) +#define CSR_DCSR_EBREAKU_SHIFT (12U) +#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) +#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) + +/* + * STEPIE (RW) + * + * This bit controls whether interrupts are enabled during single stepping + * 0:Disable interrupts during single stepping + * 1:Allow interrupts in single stepping + */ +#define CSR_DCSR_STEPIE_MASK (0x800U) +#define CSR_DCSR_STEPIE_SHIFT (11U) +#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) +#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) + +/* + * STOPCOUNT (RW) + * + * This bit controls whether performance counters are stopped in Debug Mode. + * 0:Do not stop counters in Debug Mode + * 1:Stop counters in Debug Mode + */ +#define CSR_DCSR_STOPCOUNT_MASK (0x400U) +#define CSR_DCSR_STOPCOUNT_SHIFT (10U) +#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) +#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) + +/* + * STOPTIME (RW) + * + * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. + * 0:Do not stop timers in Debug Mode + * 1:Stop timers in Debug Mode + */ +#define CSR_DCSR_STOPTIME_MASK (0x200U) +#define CSR_DCSR_STOPTIME_SHIFT (9U) +#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) +#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) + +/* + * CAUSE (RO) + * + * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger + * 0:Reserved + * 1:EBREAK + * 2:Trigger module + * 3:Halt request + * 4:Single step + * 5:Halt-on-reset + * 6-7:Reserved + */ +#define CSR_DCSR_CAUSE_MASK (0x1C0U) +#define CSR_DCSR_CAUSE_SHIFT (6U) +#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) + +/* + * MPRVEN (RW) + * + * This bit controls whether mstatus.MPRV takes effect in Debug Mode. + * 0:MPRV in mstatus is ignored in Debug Mode. + * 1:MPRV in mstatus takes effect in Debug Mode. + */ +#define CSR_DCSR_MPRVEN_MASK (0x10U) +#define CSR_DCSR_MPRVEN_SHIFT (4U) +#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) +#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) + +/* + * NMIP (RO) + * + * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. + */ +#define CSR_DCSR_NMIP_MASK (0x8U) +#define CSR_DCSR_NMIP_SHIFT (3U) +#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) + +/* + * STEP (RW) + * + * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. + * 0:Single Step Mode is off + * 1:Single Step Mode is on + */ +#define CSR_DCSR_STEP_MASK (0x4U) +#define CSR_DCSR_STEP_SHIFT (2U) +#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) +#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) + +/* + * PRV (RW) + * + * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. + * 0:User/Application + * 1:Supervisor + * 2:Reserved + * 3:Machine + */ +#define CSR_DCSR_PRV_MASK (0x3U) +#define CSR_DCSR_PRV_SHIFT (0U) +#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) +#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) + +/* Bitfield definition for register: DPC */ +/* + * DPC (RW) + * + * Debug Program Counter. Bit 0 is hardwired to 0. + */ +#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) +#define CSR_DPC_DPC_SHIFT (0U) +#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) +#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) + +/* Bitfield definition for register: DSCRATCH0 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) + +/* Bitfield definition for register: DSCRATCH1 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) + +/* Bitfield definition for register: MCYCLE */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLE_COUNTER_SHIFT (0U) +#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) +#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRET */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRET_COUNTER_SHIFT (0U) +#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) +#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) +#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) +#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) +#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) +#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) + +/* Bitfield definition for register: MCYCLEH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLEH_COUNTER_SHIFT (0U) +#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) +#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRETH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRETH_COUNTER_SHIFT (0U) +#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) +#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) +#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) +#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) +#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) +#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) + +/* Bitfield definition for register: PMACFG0 */ +/* + * PMA3CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA3CFG_MASK (0xFF000000UL) +#define CSR_PMACFG0_PMA3CFG_SHIFT (24U) +#define CSR_PMACFG0_PMA3CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA3CFG_SHIFT) & CSR_PMACFG0_PMA3CFG_MASK) +#define CSR_PMACFG0_PMA3CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA3CFG_MASK) >> CSR_PMACFG0_PMA3CFG_SHIFT) + +/* + * PMA2CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA2CFG_MASK (0xFF0000UL) +#define CSR_PMACFG0_PMA2CFG_SHIFT (16U) +#define CSR_PMACFG0_PMA2CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA2CFG_SHIFT) & CSR_PMACFG0_PMA2CFG_MASK) +#define CSR_PMACFG0_PMA2CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA2CFG_MASK) >> CSR_PMACFG0_PMA2CFG_SHIFT) + +/* + * PMA1CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA1CFG_MASK (0xFF00U) +#define CSR_PMACFG0_PMA1CFG_SHIFT (8U) +#define CSR_PMACFG0_PMA1CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA1CFG_SHIFT) & CSR_PMACFG0_PMA1CFG_MASK) +#define CSR_PMACFG0_PMA1CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA1CFG_MASK) >> CSR_PMACFG0_PMA1CFG_SHIFT) + +/* + * PMA0CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG0_PMA0CFG_MASK (0xFFU) +#define CSR_PMACFG0_PMA0CFG_SHIFT (0U) +#define CSR_PMACFG0_PMA0CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA0CFG_SHIFT) & CSR_PMACFG0_PMA0CFG_MASK) +#define CSR_PMACFG0_PMA0CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA0CFG_MASK) >> CSR_PMACFG0_PMA0CFG_SHIFT) + +/* Bitfield definition for register: PMACFG1 */ +/* + * PMA7CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA7CFG_MASK (0xFF000000UL) +#define CSR_PMACFG1_PMA7CFG_SHIFT (24U) +#define CSR_PMACFG1_PMA7CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA7CFG_SHIFT) & CSR_PMACFG1_PMA7CFG_MASK) +#define CSR_PMACFG1_PMA7CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA7CFG_MASK) >> CSR_PMACFG1_PMA7CFG_SHIFT) + +/* + * PMA6CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA6CFG_MASK (0xFF0000UL) +#define CSR_PMACFG1_PMA6CFG_SHIFT (16U) +#define CSR_PMACFG1_PMA6CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA6CFG_SHIFT) & CSR_PMACFG1_PMA6CFG_MASK) +#define CSR_PMACFG1_PMA6CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA6CFG_MASK) >> CSR_PMACFG1_PMA6CFG_SHIFT) + +/* + * PMA5CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA5CFG_MASK (0xFF00U) +#define CSR_PMACFG1_PMA5CFG_SHIFT (8U) +#define CSR_PMACFG1_PMA5CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA5CFG_SHIFT) & CSR_PMACFG1_PMA5CFG_MASK) +#define CSR_PMACFG1_PMA5CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA5CFG_MASK) >> CSR_PMACFG1_PMA5CFG_SHIFT) + +/* + * PMA4CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG1_PMA4CFG_MASK (0xFFU) +#define CSR_PMACFG1_PMA4CFG_SHIFT (0U) +#define CSR_PMACFG1_PMA4CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA4CFG_SHIFT) & CSR_PMACFG1_PMA4CFG_MASK) +#define CSR_PMACFG1_PMA4CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA4CFG_MASK) >> CSR_PMACFG1_PMA4CFG_SHIFT) + +/* Bitfield definition for register: PMACFG2 */ +/* + * PMA11CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA11CFG_MASK (0xFF000000UL) +#define CSR_PMACFG2_PMA11CFG_SHIFT (24U) +#define CSR_PMACFG2_PMA11CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA11CFG_SHIFT) & CSR_PMACFG2_PMA11CFG_MASK) +#define CSR_PMACFG2_PMA11CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA11CFG_MASK) >> CSR_PMACFG2_PMA11CFG_SHIFT) + +/* + * PMA10CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA10CFG_MASK (0xFF0000UL) +#define CSR_PMACFG2_PMA10CFG_SHIFT (16U) +#define CSR_PMACFG2_PMA10CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA10CFG_SHIFT) & CSR_PMACFG2_PMA10CFG_MASK) +#define CSR_PMACFG2_PMA10CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA10CFG_MASK) >> CSR_PMACFG2_PMA10CFG_SHIFT) + +/* + * PMA9CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA9CFG_MASK (0xFF00U) +#define CSR_PMACFG2_PMA9CFG_SHIFT (8U) +#define CSR_PMACFG2_PMA9CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA9CFG_SHIFT) & CSR_PMACFG2_PMA9CFG_MASK) +#define CSR_PMACFG2_PMA9CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA9CFG_MASK) >> CSR_PMACFG2_PMA9CFG_SHIFT) + +/* + * PMA8CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG2_PMA8CFG_MASK (0xFFU) +#define CSR_PMACFG2_PMA8CFG_SHIFT (0U) +#define CSR_PMACFG2_PMA8CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA8CFG_SHIFT) & CSR_PMACFG2_PMA8CFG_MASK) +#define CSR_PMACFG2_PMA8CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA8CFG_MASK) >> CSR_PMACFG2_PMA8CFG_SHIFT) + +/* Bitfield definition for register: PMACFG3 */ +/* + * PMA15CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA15CFG_MASK (0xFF000000UL) +#define CSR_PMACFG3_PMA15CFG_SHIFT (24U) +#define CSR_PMACFG3_PMA15CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA15CFG_SHIFT) & CSR_PMACFG3_PMA15CFG_MASK) +#define CSR_PMACFG3_PMA15CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA15CFG_MASK) >> CSR_PMACFG3_PMA15CFG_SHIFT) + +/* + * PMA14CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA14CFG_MASK (0xFF0000UL) +#define CSR_PMACFG3_PMA14CFG_SHIFT (16U) +#define CSR_PMACFG3_PMA14CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA14CFG_SHIFT) & CSR_PMACFG3_PMA14CFG_MASK) +#define CSR_PMACFG3_PMA14CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA14CFG_MASK) >> CSR_PMACFG3_PMA14CFG_SHIFT) + +/* + * PMA13CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA13CFG_MASK (0xFF00U) +#define CSR_PMACFG3_PMA13CFG_SHIFT (8U) +#define CSR_PMACFG3_PMA13CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA13CFG_SHIFT) & CSR_PMACFG3_PMA13CFG_MASK) +#define CSR_PMACFG3_PMA13CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA13CFG_MASK) >> CSR_PMACFG3_PMA13CFG_SHIFT) + +/* + * PMA12CFG (RW) + * + * See PMACFG Table + */ +#define CSR_PMACFG3_PMA12CFG_MASK (0xFFU) +#define CSR_PMACFG3_PMA12CFG_SHIFT (0U) +#define CSR_PMACFG3_PMA12CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA12CFG_SHIFT) & CSR_PMACFG3_PMA12CFG_MASK) +#define CSR_PMACFG3_PMA12CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA12CFG_MASK) >> CSR_PMACFG3_PMA12CFG_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaaaaaaaaaa Reserved + * . . . . . . + * aaaa. . . aa011111111 Reserved + * aaaa. . . a0111111111 2^{12} + * aaaa. . . 01111111111 2^{13} + * . . . . . . + * aa01. . . 11111111111 2^{XLEN} + * a011. . . 11111111111 2^{XLEN+1} + * 0111. . . 11111111111 2^{XLEN+2} + * 1111. . . 11111111111 Reserved + */ +#define CSR_PMAADDR0_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR0_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR0_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR0_PMAADDR_31_2_SHIFT) & CSR_PMAADDR0_PMAADDR_31_2_MASK) +#define CSR_PMAADDR0_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR0_PMAADDR_31_2_MASK) >> CSR_PMAADDR0_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR1_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR1_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR1_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR1_PMAADDR_31_2_SHIFT) & CSR_PMAADDR1_PMAADDR_31_2_MASK) +#define CSR_PMAADDR1_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR1_PMAADDR_31_2_MASK) >> CSR_PMAADDR1_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR2_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR2_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR2_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR2_PMAADDR_31_2_SHIFT) & CSR_PMAADDR2_PMAADDR_31_2_MASK) +#define CSR_PMAADDR2_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR2_PMAADDR_31_2_MASK) >> CSR_PMAADDR2_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR3_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR3_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR3_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR3_PMAADDR_31_2_SHIFT) & CSR_PMAADDR3_PMAADDR_31_2_MASK) +#define CSR_PMAADDR3_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR3_PMAADDR_31_2_MASK) >> CSR_PMAADDR3_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR4_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR4_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR4_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR4_PMAADDR_31_2_SHIFT) & CSR_PMAADDR4_PMAADDR_31_2_MASK) +#define CSR_PMAADDR4_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR4_PMAADDR_31_2_MASK) >> CSR_PMAADDR4_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR5_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR5_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR5_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR5_PMAADDR_31_2_SHIFT) & CSR_PMAADDR5_PMAADDR_31_2_MASK) +#define CSR_PMAADDR5_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR5_PMAADDR_31_2_MASK) >> CSR_PMAADDR5_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR6_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR6_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR6_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR6_PMAADDR_31_2_SHIFT) & CSR_PMAADDR6_PMAADDR_31_2_MASK) +#define CSR_PMAADDR6_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR6_PMAADDR_31_2_MASK) >> CSR_PMAADDR6_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR7_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR7_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR7_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR7_PMAADDR_31_2_SHIFT) & CSR_PMAADDR7_PMAADDR_31_2_MASK) +#define CSR_PMAADDR7_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR7_PMAADDR_31_2_MASK) >> CSR_PMAADDR7_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR8_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR8_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR8_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR8_PMAADDR_31_2_SHIFT) & CSR_PMAADDR8_PMAADDR_31_2_MASK) +#define CSR_PMAADDR8_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR8_PMAADDR_31_2_MASK) >> CSR_PMAADDR8_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR9_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR9_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR9_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR9_PMAADDR_31_2_SHIFT) & CSR_PMAADDR9_PMAADDR_31_2_MASK) +#define CSR_PMAADDR9_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR9_PMAADDR_31_2_MASK) >> CSR_PMAADDR9_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR10_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR10_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR10_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR10_PMAADDR_31_2_SHIFT) & CSR_PMAADDR10_PMAADDR_31_2_MASK) +#define CSR_PMAADDR10_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR10_PMAADDR_31_2_MASK) >> CSR_PMAADDR10_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR11_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR11_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR11_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR11_PMAADDR_31_2_SHIFT) & CSR_PMAADDR11_PMAADDR_31_2_MASK) +#define CSR_PMAADDR11_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR11_PMAADDR_31_2_MASK) >> CSR_PMAADDR11_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR12_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR12_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR12_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR12_PMAADDR_31_2_SHIFT) & CSR_PMAADDR12_PMAADDR_31_2_MASK) +#define CSR_PMAADDR12_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR12_PMAADDR_31_2_MASK) >> CSR_PMAADDR12_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR13_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR13_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR13_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR13_PMAADDR_31_2_SHIFT) & CSR_PMAADDR13_PMAADDR_31_2_MASK) +#define CSR_PMAADDR13_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR13_PMAADDR_31_2_MASK) >> CSR_PMAADDR13_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR14_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR14_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR14_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR14_PMAADDR_31_2_SHIFT) & CSR_PMAADDR14_PMAADDR_31_2_MASK) +#define CSR_PMAADDR14_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR14_PMAADDR_31_2_MASK) >> CSR_PMAADDR14_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMAADDR */ +/* + * PMAADDR_31_2 (RW) + * + * same as PMAADDR0 + */ +#define CSR_PMAADDR15_PMAADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMAADDR15_PMAADDR_31_2_SHIFT (2U) +#define CSR_PMAADDR15_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR15_PMAADDR_31_2_SHIFT) & CSR_PMAADDR15_PMAADDR_31_2_MASK) +#define CSR_PMAADDR15_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR15_PMAADDR_31_2_MASK) >> CSR_PMAADDR15_PMAADDR_31_2_SHIFT) + +/* Bitfield definition for register: CYCLE */ +/* + * CYCLE (RW) + * + * Cycle Counter + */ +#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) +#define CSR_CYCLE_CYCLE_SHIFT (0U) +#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) +#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) + +/* Bitfield definition for register: CYCLEH */ +/* + * CYCLEH (RW) + * + * Cycle Counter Higher 32-bit + */ +#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) +#define CSR_CYCLEH_CYCLEH_SHIFT (0U) +#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) +#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) + +/* Bitfield definition for register: MVENDORID */ +/* + * MVENDORID (RO) + * + * The manufacturer ID + */ +#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) +#define CSR_MVENDORID_MVENDORID_SHIFT (0U) +#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) + +/* Bitfield definition for register: MARCHID */ +/* + * CPU_ID (RO) + * + * CPU ID + */ +#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) +#define CSR_MARCHID_CPU_ID_SHIFT (0U) +#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) + +/* Bitfield definition for register: MIMPID */ +/* + * MAJOR (RO) + * + * Revision major + */ +#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) +#define CSR_MIMPID_MAJOR_SHIFT (8U) +#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) + +/* + * MINOR (RO) + * + * Revision minor + */ +#define CSR_MIMPID_MINOR_MASK (0xF0U) +#define CSR_MIMPID_MINOR_SHIFT (4U) +#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) + +/* + * EXTENSION (RO) + * + * Revision extension + */ +#define CSR_MIMPID_EXTENSION_MASK (0xFU) +#define CSR_MIMPID_EXTENSION_SHIFT (0U) +#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) + +/* Bitfield definition for register: MHARTID */ +/* + * MHARTID (RO) + * + * Hart ID + */ +#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) +#define CSR_MHARTID_MHARTID_SHIFT (0U) +#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) + +/* NON-STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: SCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_SCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_SCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM6_SHIFT) & CSR_SCOUNTEREN_HPM6_MASK) +#define CSR_SCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM6_MASK) >> CSR_SCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_SCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_SCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM5_SHIFT) & CSR_SCOUNTEREN_HPM5_MASK) +#define CSR_SCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM5_MASK) >> CSR_SCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_SCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_SCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM4_SHIFT) & CSR_SCOUNTEREN_HPM4_MASK) +#define CSR_SCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM4_MASK) >> CSR_SCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_SCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_SCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM3_SHIFT) & CSR_SCOUNTEREN_HPM3_MASK) +#define CSR_SCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM3_MASK) >> CSR_SCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_IR_MASK (0x4U) +#define CSR_SCOUNTEREN_IR_SHIFT (2U) +#define CSR_SCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_IR_SHIFT) & CSR_SCOUNTEREN_IR_MASK) +#define CSR_SCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_IR_MASK) >> CSR_SCOUNTEREN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTEREN_CY_MASK (0x1U) +#define CSR_SCOUNTEREN_CY_SHIFT (0U) +#define CSR_SCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_CY_SHIFT) & CSR_SCOUNTEREN_CY_MASK) +#define CSR_SCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_CY_MASK) >> CSR_SCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) +#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) +#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) +#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) +#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) +#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) +#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) +#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: MILMB */ +/* + * IBPA (RO) + * + * The base physical address of ILM. It has to be an integer multiple of the ILM size + */ +#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) +#define CSR_MILMB_IBPA_SHIFT (10U) +#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MILMB_RWECC_MASK (0x8U) +#define CSR_MILMB_RWECC_SHIFT (3U) +#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) +#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MILMB_ECCEN_MASK (0x6U) +#define CSR_MILMB_ECCEN_SHIFT (1U) +#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) +#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) + +/* + * IEN (RO) + * + * ILM enable control: + * 0:ILM is disabled + * 1:ILM is enabled + */ +#define CSR_MILMB_IEN_MASK (0x1U) +#define CSR_MILMB_IEN_SHIFT (0U) +#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) + +/* Bitfield definition for register: MDLMB */ +/* + * DBPA (RO) + * + * The base physical address of DLM. It has to be an integer multiple of the DLM size + */ +#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) +#define CSR_MDLMB_DBPA_SHIFT (10U) +#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MDLMB_RWECC_MASK (0x8U) +#define CSR_MDLMB_RWECC_SHIFT (3U) +#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) +#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MDLMB_ECCEN_MASK (0x6U) +#define CSR_MDLMB_ECCEN_SHIFT (1U) +#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) +#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) + +/* + * DEN (RO) + * + * DLM enable control: + * 0:DLM is disabled + * 1:DLM is enabled + */ +#define CSR_MDLMB_DEN_MASK (0x1U) +#define CSR_MDLMB_DEN_SHIFT (0U) +#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) + +/* Bitfield definition for register: MECC_CODE */ +/* + * INSN (RO) + * + * Indicates if the parity/ECC error is caused by instruction fetch or data access. + * 0:Data access + * 1:Instruction fetch + */ +#define CSR_MECC_CODE_INSN_MASK (0x400000UL) +#define CSR_MECC_CODE_INSN_SHIFT (22U) +#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) + +/* + * RAMID (RO) + * + * The ID of RAM that caused parity/ECC errors. + * This bit is updated on parity/ECC error exceptions. + * 0–1:Reserved + * 2:Tag RAM of I-Cache + * 3:Data RAM of I-Cache + * 4:Tag RAM of D-Cache + * 5:Data RAM of D-Cache + * 6:Tag RAM of TLB + * 7:Data RAM of TLB + * 8:ILM + * 9:DLM + * 10–15:Reserved + */ +#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) +#define CSR_MECC_CODE_RAMID_SHIFT (18U) +#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) + +/* + * P (RO) + * + * Precise error. This bit is updated on parity/ECC error exceptions. + * 0:Imprecise error + * 1:Precise error + */ +#define CSR_MECC_CODE_P_MASK (0x20000UL) +#define CSR_MECC_CODE_P_SHIFT (17U) +#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) + +/* + * C (RO) + * + * Correctable error. This bit is updated on parity/ECC error exceptions. + * 0:Uncorrectable error + * 1:Correctable error + */ +#define CSR_MECC_CODE_C_MASK (0x10000UL) +#define CSR_MECC_CODE_C_SHIFT (16U) +#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) + +/* + * CODE (RW) + * + * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). + */ +#define CSR_MECC_CODE_CODE_MASK (0x7FU) +#define CSR_MECC_CODE_CODE_SHIFT (0U) +#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) +#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) + +/* Bitfield definition for register: MNVEC */ +/* + * MNVEC (RO) + * + * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. + */ +#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) +#define CSR_MNVEC_MNVEC_SHIFT (0U) +#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) + +/* Bitfield definition for register: MXSTATUS */ +/* + * PDME (RW) + * + * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. + */ +#define CSR_MXSTATUS_PDME_MASK (0x20U) +#define CSR_MXSTATUS_PDME_SHIFT (5U) +#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) +#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) + +/* + * DME (RW) + * + * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. + */ +#define CSR_MXSTATUS_DME_MASK (0x10U) +#define CSR_MXSTATUS_DME_SHIFT (4U) +#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) +#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) + +/* + * PPFT_EN (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) +#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) +#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) +#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) + +/* + * PFT_EN (RW) + * + * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: + * PPFT_EN <= PFT_EN; + * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; + * On executing an MRET instruction: + * PFT_EN <= PPFT_EN; + * This field is hardwired to 0 if the PowerBrake feature is not supported. + */ +#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) +#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) +#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) +#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) + +/* Bitfield definition for register: MPFT_CTL */ +/* + * FAST_INT (RW) + * + * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. + */ +#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) +#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) +#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) +#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) + +/* + * T_LEVEL (RW) + * + * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest + * performance at throttling level 15. + * 0:Level 0 (the highest performance) + * 1-14:Level 1-14 + * 15:Level 15 (the lowest performance) + */ +#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) +#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) +#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) +#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) + +/* Bitfield definition for register: MHSP_CTL */ +/* + * M (RW) + * + * Enables the SP protection and recording mechanism in Machine mode + * 0:The mechanism is disabled in Machine mode. + * 1: The mechanism is enabled in Machine mode. + */ +#define CSR_MHSP_CTL_M_MASK (0x20U) +#define CSR_MHSP_CTL_M_SHIFT (5U) +#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) +#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) + +/* + * S (RW) + * + * Enables the SP protection and recording mechanism in Supervisor mode + * 0:The mechanism is disabled in Supervisor mode + * 1:The mechanism is enabled in Supervisor mode + */ +#define CSR_MHSP_CTL_S_MASK (0x10U) +#define CSR_MHSP_CTL_S_SHIFT (4U) +#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) +#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) + +/* + * U (RW) + * + * Enables the SP protection and recording mechanism in User mode + * 0:The mechanism is disabled in User mode + * 1:The mechanism is enabled in User mode. + */ +#define CSR_MHSP_CTL_U_MASK (0x8U) +#define CSR_MHSP_CTL_U_SHIFT (3U) +#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) +#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) + +/* + * SCHM (RW) + * + * Selects the operating scheme of the stack protection and recording mechanism + * 0:Stack overflow/underflow detection + * 1:Top-of-stack recording + */ +#define CSR_MHSP_CTL_SCHM_MASK (0x4U) +#define CSR_MHSP_CTL_SCHM_SHIFT (2U) +#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) +#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) + +/* + * UDF_EN (RW) + * + * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack underflow protection is disabled + * 1:The stack underflow protection is enabled. + */ +#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) +#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) +#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) +#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) + +/* + * OVF_EN (RW) + * + * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack overflow protection and recording mechanism are disabled. + * 1:The stack overflow protection and recording mechanism are enabled. + */ +#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) +#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) +#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) +#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) + +/* Bitfield definition for register: MSP_BOUND */ +/* + * MSP_BOUND (RW) + * + * Machine SP Bound + */ +#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) +#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) +#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) + +/* Bitfield definition for register: MSP_BASE */ +/* + * SP_BASE (RW) + * + * Machine SP base + */ +#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) +#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) +#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) + +/* Bitfield definition for register: MDCAUSE */ +/* + * PM (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MDCAUSE_PM_MASK (0x60U) +#define CSR_MDCAUSE_PM_SHIFT (5U) +#define CSR_MDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_PM_SHIFT) & CSR_MDCAUSE_PM_MASK) +#define CSR_MDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_PM_MASK) >> CSR_MDCAUSE_PM_SHIFT) + +/* + * MDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the mcause register. + * The value of MDCAUSE for precise exception: + * When mcause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When mcause == 2 (Illegal instruction): + * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When mcause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When mcause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of MDCAUSE for imprecise exception: + * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) +#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) +#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) +#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) + +/* Bitfield definition for register: MCACHE_CTL */ +/* + * DC_WAROUND (RW) + * + * Cache Write-Around threshold + * 0:Disables streaming. All cacheable write misses allocate a cache line according to PMA settings. + * 1:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 4 cache lines. + * 2:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 64 cache lines. + * 3:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 128 cache lines. + */ +#define CSR_MCACHE_CTL_DC_WAROUND_MASK (0x6000U) +#define CSR_MCACHE_CTL_DC_WAROUND_SHIFT (13U) +#define CSR_MCACHE_CTL_DC_WAROUND_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_WAROUND_SHIFT) & CSR_MCACHE_CTL_DC_WAROUND_MASK) +#define CSR_MCACHE_CTL_DC_WAROUND_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_WAROUND_MASK) >> CSR_MCACHE_CTL_DC_WAROUND_SHIFT) + +/* + * DC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1000U) +#define CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT (12U) +#define CSR_MCACHE_CTL_DC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT) + +/* + * IC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) + +/* + * DPREF_EN (RW) + * + * This bit controls hardware prefetch for load/store accesses to cacheable memory regions when D-Cache size is not 0 + * 0:Disable hardware prefetch on load/store memory accesses + * 1:Enable hardware prefetch on load/store memory accesses + */ +#define CSR_MCACHE_CTL_DPREF_EN_MASK (0x400U) +#define CSR_MCACHE_CTL_DPREF_EN_SHIFT (10U) +#define CSR_MCACHE_CTL_DPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DPREF_EN_SHIFT) & CSR_MCACHE_CTL_DPREF_EN_MASK) +#define CSR_MCACHE_CTL_DPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DPREF_EN_MASK) >> CSR_MCACHE_CTL_DPREF_EN_SHIFT) + +/* + * IPREF_EN (RW) + * + * This bit controls hardware prefetch for instruction fetches to cacheable memory regions when Cache size is not 0 + * 0:Disable hardware prefetch on instruction fetches + * 1:Enable hardware prefetch on instruction fetches + */ +#define CSR_MCACHE_CTL_IPREF_EN_MASK (0x200U) +#define CSR_MCACHE_CTL_IPREF_EN_SHIFT (9U) +#define CSR_MCACHE_CTL_IPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IPREF_EN_SHIFT) & CSR_MCACHE_CTL_IPREF_EN_MASK) +#define CSR_MCACHE_CTL_IPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IPREF_EN_MASK) >> CSR_MCACHE_CTL_IPREF_EN_SHIFT) + +/* + * CCTL_SUEN (RW) + * + * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs + * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) +#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) + +/* + * DC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) +#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) +#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) +#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) + +/* + * IC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) +#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) +#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) +#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) + +/* + * DC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * data cache. + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) +#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) +#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) +#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) + +/* + * IC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * instruction cache + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) +#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) +#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) +#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) + +/* + * DC_EN (RW) + * + * Controls if the data cache is enabled or not. + * 0:D-Cache is disabled + * 1:D-Cache is enabled + */ +#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) +#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) +#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) +#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) + +/* + * IC_EN (RW) + * + * Controls if the instruction cache is enabled or not. + * 0:I-Cache is disabled + * 1:I-Cache is enabled + */ +#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) +#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) +#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) +#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) + +/* Bitfield definition for register: MCCTLBEGINADDR */ +/* + * VA (RW) + * + * This register holds the address information required by CCTL operations + */ +#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) +#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: MCCTLCOMMAND */ +/* + * VA (RW) + * + * See CCTL Command Definition Table + */ +#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) +#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: MCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_MCCTLDATA_VA_MASK (0x1FU) +#define CSR_MCCTLDATA_VA_SHIFT (0U) +#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) +#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: MCOUNTERWEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) +#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) +#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) +#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) +#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_IR_MASK (0x4U) +#define CSR_MCOUNTERWEN_IR_SHIFT (2U) +#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) +#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_CY_MASK (0x1U) +#define CSR_MCOUNTERWEN_CY_SHIFT (0U) +#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) +#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) +#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) +#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) +#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) +#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) +#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) +#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: MMISC_CTL */ +/* + * NBLD_EN (RW) + * + * This field controls the blocking behavior of load instructions. When this bit is clear, load instructions accessing non-device regions are blocking. When this bit is set, load instructions will not be blocking on such occasions and bus errors will no longer be reported synchronously. + * 0:Load to memory regions are blocking. + * 1:Load to memory regions are non-blocking. + */ +#define CSR_MMISC_CTL_NBLD_EN_MASK (0x100U) +#define CSR_MMISC_CTL_NBLD_EN_SHIFT (8U) +#define CSR_MMISC_CTL_NBLD_EN_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_NBLD_EN_SHIFT) & CSR_MMISC_CTL_NBLD_EN_MASK) +#define CSR_MMISC_CTL_NBLD_EN_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_NBLD_EN_MASK) >> CSR_MMISC_CTL_NBLD_EN_SHIFT) + +/* + * MSA_UNA (RW) + * + * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. + * Supported instructions: LW/LH/LHU/SW/SH + * 0:Misaligned accesses generate Address Misaligned exceptions. + * 1:Misaligned accesses generate Address Misaligned exceptions. + */ +#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) +#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) +#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) +#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) + +/* + * BRPE (RW) + * + * Branch prediction enable bit. This bit controls all branch prediction structures. + * 0:Disabled + * 1:Enabled + * This bit is hardwired to 0 if branch prediction structure is not supported. + */ +#define CSR_MMISC_CTL_BRPE_MASK (0x8U) +#define CSR_MMISC_CTL_BRPE_SHIFT (3U) +#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) +#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) + +/* + * RVCOMPM (RW) + * + * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions + * 0:Disabled + * 1:Enabled + */ +#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) +#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) +#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) +#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) + +/* + * VEC_PLIC (RW) + * + * Selects the operation mode of PLIC: + * 0:Regular mode + * 1:Vector mode + * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. + */ +#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) +#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) +#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) +#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) +#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) +#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) +#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) +#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) +#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) +#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) +#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) +#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) +#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) +#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) +#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) +#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) +#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) +#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) +#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) +#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) +#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) +#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) +#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) +#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) +#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) +#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_IR_MASK (0x4U) +#define CSR_MCOUNTEROVF_IR_SHIFT (2U) +#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) +#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_CY_MASK (0x1U) +#define CSR_MCOUNTEROVF_CY_SHIFT (0U) +#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) +#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: MSLIDELEG */ +/* + * PMOVI (RW) + * + * Delegate S-mode performance monitor overflow local interrupt to S-mode. + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_PMOVI_MASK (0x40000UL) +#define CSR_MSLIDELEG_PMOVI_SHIFT (18U) +#define CSR_MSLIDELEG_PMOVI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_PMOVI_SHIFT) & CSR_MSLIDELEG_PMOVI_MASK) +#define CSR_MSLIDELEG_PMOVI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_PMOVI_MASK) >> CSR_MSLIDELEG_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Delegate S-mode bus read/write transaction error local interrupt to S-mode + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_BWEI_MASK (0x20000UL) +#define CSR_MSLIDELEG_BWEI_SHIFT (17U) +#define CSR_MSLIDELEG_BWEI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_BWEI_SHIFT) & CSR_MSLIDELEG_BWEI_MASK) +#define CSR_MSLIDELEG_BWEI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_BWEI_MASK) >> CSR_MSLIDELEG_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Delegate S-mode slave-port ECC error local interrupt to S-mode + * 0:Do not delegate to S-mode. + * 1:Delegate to S-mode. + */ +#define CSR_MSLIDELEG_IMECCI_MASK (0x10000UL) +#define CSR_MSLIDELEG_IMECCI_SHIFT (16U) +#define CSR_MSLIDELEG_IMECCI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_IMECCI_SHIFT) & CSR_MSLIDELEG_IMECCI_MASK) +#define CSR_MSLIDELEG_IMECCI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_IMECCI_MASK) >> CSR_MSLIDELEG_IMECCI_SHIFT) + +/* Bitfield definition for register: MCLK_CTL */ +/* + * FUNIT (RW) + * + * Level 2 clock gating enable for function units listed in the following table. + * 16:integer arithmetic unit + * 17:integer permutation unit + * 18:integer mask unit + * 19:integer division unit + * 20:integer multiply and add unit + * 21:floating-point multiply and add + * unit + * 22:floating-point miscellaneous unit + * 23:floating-point division unit + * 24:load/store unit + * 31:25:Reserved + */ +#define CSR_MCLK_CTL_FUNIT_MASK (0xFFFF0000UL) +#define CSR_MCLK_CTL_FUNIT_SHIFT (16U) +#define CSR_MCLK_CTL_FUNIT_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FUNIT_SHIFT) & CSR_MCLK_CTL_FUNIT_MASK) +#define CSR_MCLK_CTL_FUNIT_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FUNIT_MASK) >> CSR_MCLK_CTL_FUNIT_SHIFT) + +/* + * VI (RW) + * + * Level 1 clock gating enable for the vector/floating-point issue queues. + */ +#define CSR_MCLK_CTL_VI_MASK (0x8000U) +#define CSR_MCLK_CTL_VI_SHIFT (15U) +#define CSR_MCLK_CTL_VI_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VI_SHIFT) & CSR_MCLK_CTL_VI_MASK) +#define CSR_MCLK_CTL_VI_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VI_MASK) >> CSR_MCLK_CTL_VI_SHIFT) + +/* + * VR (RW) + * + * Level 1 clock gating enable for the vector/floating-point register file. + */ +#define CSR_MCLK_CTL_VR_MASK (0x4000U) +#define CSR_MCLK_CTL_VR_SHIFT (14U) +#define CSR_MCLK_CTL_VR_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VR_SHIFT) & CSR_MCLK_CTL_VR_MASK) +#define CSR_MCLK_CTL_VR_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VR_MASK) >> CSR_MCLK_CTL_VR_SHIFT) + +/* + * AQ (RW) + * + * Level 1 clock gating enable for ACE load/store queues. + */ +#define CSR_MCLK_CTL_AQ_MASK (0x2000U) +#define CSR_MCLK_CTL_AQ_SHIFT (13U) +#define CSR_MCLK_CTL_AQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_AQ_SHIFT) & CSR_MCLK_CTL_AQ_MASK) +#define CSR_MCLK_CTL_AQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_AQ_MASK) >> CSR_MCLK_CTL_AQ_SHIFT) + +/* + * DQ (RW) + * + * Level 1 clock gating enable for data cache load/store queues. + */ +#define CSR_MCLK_CTL_DQ_MASK (0x1000U) +#define CSR_MCLK_CTL_DQ_SHIFT (12U) +#define CSR_MCLK_CTL_DQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_DQ_SHIFT) & CSR_MCLK_CTL_DQ_MASK) +#define CSR_MCLK_CTL_DQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_DQ_MASK) >> CSR_MCLK_CTL_DQ_SHIFT) + +/* + * UQ (RW) + * + * Level 1 clock gating enable for uncached queues + */ +#define CSR_MCLK_CTL_UQ_MASK (0x800U) +#define CSR_MCLK_CTL_UQ_SHIFT (11U) +#define CSR_MCLK_CTL_UQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_UQ_SHIFT) & CSR_MCLK_CTL_UQ_MASK) +#define CSR_MCLK_CTL_UQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_UQ_MASK) >> CSR_MCLK_CTL_UQ_SHIFT) + +/* + * FP (RW) + * + * Level 1 clock gating enable for scalar floating point issue unit and queues. + */ +#define CSR_MCLK_CTL_FP_MASK (0x400U) +#define CSR_MCLK_CTL_FP_SHIFT (10U) +#define CSR_MCLK_CTL_FP_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FP_SHIFT) & CSR_MCLK_CTL_FP_MASK) +#define CSR_MCLK_CTL_FP_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FP_MASK) >> CSR_MCLK_CTL_FP_SHIFT) + +/* + * CLKGATE (RW) + * + * One-hot clock gating levels. + * 0:Level 1 clock gating in module level + * 1:Level 2 clock gating in unit level + * 2:Level 3 clock gating in VPU level + * 7:3:Reserved + */ +#define CSR_MCLK_CTL_CLKGATE_MASK (0xFFU) +#define CSR_MCLK_CTL_CLKGATE_SHIFT (0U) +#define CSR_MCLK_CTL_CLKGATE_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_CLKGATE_SHIFT) & CSR_MCLK_CTL_CLKGATE_MASK) +#define CSR_MCLK_CTL_CLKGATE_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_CLKGATE_MASK) >> CSR_MCLK_CTL_CLKGATE_SHIFT) + +/* Bitfield definition for register: DEXC2DBG */ +/* + * PMOV (RW) + * + * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) +#define CSR_DEXC2DBG_PMOV_SHIFT (19U) +#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) +#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) + +/* + * SPF (RW) + * + * Indicates whether store page fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SPF_MASK (0x40000UL) +#define CSR_DEXC2DBG_SPF_SHIFT (18U) +#define CSR_DEXC2DBG_SPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SPF_SHIFT) & CSR_DEXC2DBG_SPF_MASK) +#define CSR_DEXC2DBG_SPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SPF_MASK) >> CSR_DEXC2DBG_SPF_SHIFT) + +/* + * LPF (RW) + * + * Indicates whether load fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LPF_MASK (0x20000UL) +#define CSR_DEXC2DBG_LPF_SHIFT (17U) +#define CSR_DEXC2DBG_LPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LPF_SHIFT) & CSR_DEXC2DBG_LPF_MASK) +#define CSR_DEXC2DBG_LPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LPF_MASK) >> CSR_DEXC2DBG_LPF_SHIFT) + +/* + * IPF (RW) + * + * Indicates whether instruction page fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IPF_MASK (0x10000UL) +#define CSR_DEXC2DBG_IPF_SHIFT (16U) +#define CSR_DEXC2DBG_IPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IPF_SHIFT) & CSR_DEXC2DBG_IPF_MASK) +#define CSR_DEXC2DBG_IPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IPF_MASK) >> CSR_DEXC2DBG_IPF_SHIFT) + +/* + * BWE (RW) + * + * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_BWE_MASK (0x8000U) +#define CSR_DEXC2DBG_BWE_SHIFT (15U) +#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) +#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) + +/* + * SLPECC (RW) + * + * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) +#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) +#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) +#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) + +/* + * ACE (RW) + * + * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_ACE_MASK (0x2000U) +#define CSR_DEXC2DBG_ACE_SHIFT (13U) +#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) +#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) + +/* + * HSP (RW) + * + * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_HSP_MASK (0x1000U) +#define CSR_DEXC2DBG_HSP_SHIFT (12U) +#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) +#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) + +/* + * MEC (RW) + * + * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_MEC_MASK (0x800U) +#define CSR_DEXC2DBG_MEC_SHIFT (11U) +#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) +#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) + +/* + * SEC (RW) + * + * Indicates whether S-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SEC_MASK (0x200U) +#define CSR_DEXC2DBG_SEC_SHIFT (9U) +#define CSR_DEXC2DBG_SEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SEC_SHIFT) & CSR_DEXC2DBG_SEC_MASK) +#define CSR_DEXC2DBG_SEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SEC_MASK) >> CSR_DEXC2DBG_SEC_SHIFT) + +/* + * UEC (RW) + * + * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_UEC_MASK (0x100U) +#define CSR_DEXC2DBG_UEC_SHIFT (8U) +#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) +#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) + +/* + * SAF (RW) + * + * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAF_MASK (0x80U) +#define CSR_DEXC2DBG_SAF_SHIFT (7U) +#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) +#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) + +/* + * SAM (RW) + * + * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAM_MASK (0x40U) +#define CSR_DEXC2DBG_SAM_SHIFT (6U) +#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) +#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) + +/* + * LAF (RW) + * + * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAF_MASK (0x20U) +#define CSR_DEXC2DBG_LAF_SHIFT (5U) +#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) +#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) + +/* + * LAM (RW) + * + * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAM_MASK (0x10U) +#define CSR_DEXC2DBG_LAM_SHIFT (4U) +#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) +#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) + +/* + * NMI (RW) + * + * Indicates whether Non-Maskable Interrupt + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_NMI_MASK (0x8U) +#define CSR_DEXC2DBG_NMI_SHIFT (3U) +#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) +#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) + +/* + * II (RW) + * + * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_II_MASK (0x4U) +#define CSR_DEXC2DBG_II_SHIFT (2U) +#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) +#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) + +/* + * IAF (RW) + * + * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAF_MASK (0x2U) +#define CSR_DEXC2DBG_IAF_SHIFT (1U) +#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) +#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) + +/* + * IAM (RW) + * + * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAM_MASK (0x1U) +#define CSR_DEXC2DBG_IAM_SHIFT (0U) +#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) +#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) + +/* Bitfield definition for register: DDCAUSE */ +/* + * SUBTYPE (RO) + * + * Subtypes for main type. + * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. + * 0:Illegal instruction + * 1:Privileged instruction + * 2:Non-existent CSR + * 3:Privilege CSR access + * 4:Read-only CSR update + */ +#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) +#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) +#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) + +/* + * MAINTYPE (RO) + * + * Cause for redirection to Debug Mode. + * 0:Software Breakpoint (EBREAK) + * 1:Instruction Access Misaligned (IAM) + * 2:Instruction Access Fault (IAF) + * 3:Illegal Instruction (II) + * 4:Non-Maskable Interrupt (NMI) + * 5:Load Access Misaligned (LAM) + * 6:Load Access Fault (LAF) + * 7:Store Access Misaligned (SAM) + * 8:Store Access Fault (SAF) + * 9:U-mode Environment Call (UEC) + * 10:S-mode Environment Call (SEC) + * 11:Instruction page fault + * 12:M-mode Environment Call (MEC) + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 16:Imprecise ECC error + * 17;Bus write transaction error + * 18:Performance Counter overflow + * 19–31:Reserved + * 32:Stack overflow exception + * 33:Stack underflow exception + * 34:ACE disabled exception + * 35–39:Reserved + * 40–47:ACE exception + * ≥48:Reserved + */ +#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) +#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) +#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) + +/* Bitfield definition for register: UITB */ +/* + * ADDR (RW) + * + * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. + */ +#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) +#define CSR_UITB_ADDR_SHIFT (2U) +#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) +#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) + +/* + * HW (RO) + * + * This bit specifies if the CoDense instruction table is hardwired. + * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. + * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. + */ +#define CSR_UITB_HW_MASK (0x1U) +#define CSR_UITB_HW_SHIFT (0U) +#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) + +/* Bitfield definition for register: UCODE */ +/* + * OV (RW) + * + * Overflow flag. It will be set by DSP instructions with a saturated result. + * 0:A saturated result is not generated + * 1:A saturated result is generated + */ +#define CSR_UCODE_OV_MASK (0x1U) +#define CSR_UCODE_OV_SHIFT (0U) +#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) +#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) + +/* Bitfield definition for register: UDCAUSE */ +/* + * UDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. + * The value of UDCAUSE for precise exception: + * When ucause == 1 (Instruction access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP instruction access violation + * 3:Bus error + * 4:PMA empty hole access + * When ucause == 2 (Illegal instruction) + * 0:Please parse the utval CSR + * 1:FP disabled exception + * 2:ACE disabled exception + * When ucause == 5 (Load access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP load access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + * When ucause == 7 (Store access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP store access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + */ +#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) +#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) +#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) +#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) + +/* Bitfield definition for register: UCCTLBEGINADDR */ +/* + * VA (RW) + * + * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. + */ +#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) +#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: UCCTLCOMMAND */ +/* + * VA (RW) + * + * See User CCTL Command Definition Table + */ +#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) +#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: SLIE */ +/* + * PMOVI (RW) + * + * Enable S-mode performance monitor overflow local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_PMOVI_MASK (0x40000UL) +#define CSR_SLIE_PMOVI_SHIFT (18U) +#define CSR_SLIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIE_PMOVI_SHIFT) & CSR_SLIE_PMOVI_MASK) +#define CSR_SLIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIE_PMOVI_MASK) >> CSR_SLIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Enable S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_BWEI_MASK (0x20000UL) +#define CSR_SLIE_BWEI_SHIFT (17U) +#define CSR_SLIE_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIE_BWEI_SHIFT) & CSR_SLIE_BWEI_MASK) +#define CSR_SLIE_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIE_BWEI_MASK) >> CSR_SLIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Enable S-mode slave-port ECC error local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIE_IMECCI_MASK (0x10000UL) +#define CSR_SLIE_IMECCI_SHIFT (16U) +#define CSR_SLIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIE_IMECCI_SHIFT) & CSR_SLIE_IMECCI_MASK) +#define CSR_SLIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIE_IMECCI_MASK) >> CSR_SLIE_IMECCI_SHIFT) + +/* Bitfield definition for register: SLIP */ +/* + * PMOVI (RW) + * + * Pending control and status of S-mode performance monitor overflow local interrupt. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_PMOVI_MASK (0x40000UL) +#define CSR_SLIP_PMOVI_SHIFT (18U) +#define CSR_SLIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIP_PMOVI_SHIFT) & CSR_SLIP_PMOVI_MASK) +#define CSR_SLIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIP_PMOVI_MASK) >> CSR_SLIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Pending control and status of S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_BWEI_MASK (0x20000UL) +#define CSR_SLIP_BWEI_SHIFT (17U) +#define CSR_SLIP_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIP_BWEI_SHIFT) & CSR_SLIP_BWEI_MASK) +#define CSR_SLIP_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIP_BWEI_MASK) >> CSR_SLIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Pending control and status of S-mode slave-port ECC error local interrupt.. + * 0:Local interrupt is not enabled. + * 1:Local interrupt is enabled + */ +#define CSR_SLIP_IMECCI_MASK (0x10000UL) +#define CSR_SLIP_IMECCI_SHIFT (16U) +#define CSR_SLIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIP_IMECCI_SHIFT) & CSR_SLIP_IMECCI_MASK) +#define CSR_SLIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIP_IMECCI_MASK) >> CSR_SLIP_IMECCI_SHIFT) + +/* Bitfield definition for register: SDCAUSE */ +/* + * PM (RW) + * + * When scause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: + * 0:User mode + * 1:Supervisor mode + * 2:Reserved + * 3:Machine mode + */ +#define CSR_SDCAUSE_PM_MASK (0x60U) +#define CSR_SDCAUSE_PM_SHIFT (5U) +#define CSR_SDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_PM_SHIFT) & CSR_SDCAUSE_PM_MASK) +#define CSR_SDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_PM_MASK) >> CSR_SDCAUSE_PM_SHIFT) + +/* + * SDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the scause register. See the list below for details. + * The value of SDCAUSE for precise exception: + * When scause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When scause == 2 (Illegal instruction): + * 0:Please parse the stval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When scause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When scause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of SDCAUSE for imprecise exception: + * When scause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When scause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_SDCAUSE_SDCAUSE_MASK (0x7U) +#define CSR_SDCAUSE_SDCAUSE_SHIFT (0U) +#define CSR_SDCAUSE_SDCAUSE_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_SDCAUSE_SHIFT) & CSR_SDCAUSE_SDCAUSE_MASK) +#define CSR_SDCAUSE_SDCAUSE_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_SDCAUSE_MASK) >> CSR_SDCAUSE_SDCAUSE_SHIFT) + +/* Bitfield definition for register: SCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_SCCTLDATA_VA_MASK (0x1FU) +#define CSR_SCCTLDATA_VA_SHIFT (0U) +#define CSR_SCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_SCCTLDATA_VA_SHIFT) & CSR_SCCTLDATA_VA_MASK) +#define CSR_SCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_SCCTLDATA_VA_MASK) >> CSR_SCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: SCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_SCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_SCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM6_SHIFT) & CSR_SCOUNTERINTEN_HPM6_MASK) +#define CSR_SCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM6_MASK) >> CSR_SCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_SCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_SCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM5_SHIFT) & CSR_SCOUNTERINTEN_HPM5_MASK) +#define CSR_SCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM5_MASK) >> CSR_SCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_SCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_SCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM4_SHIFT) & CSR_SCOUNTERINTEN_HPM4_MASK) +#define CSR_SCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM4_MASK) >> CSR_SCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_SCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_SCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM3_SHIFT) & CSR_SCOUNTERINTEN_HPM3_MASK) +#define CSR_SCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM3_MASK) >> CSR_SCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_SCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_SCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_IR_SHIFT) & CSR_SCOUNTERINTEN_IR_MASK) +#define CSR_SCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_IR_MASK) >> CSR_SCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_SCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_SCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_CY_SHIFT) & CSR_SCOUNTERINTEN_CY_MASK) +#define CSR_SCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_CY_MASK) >> CSR_SCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM6_SHIFT) & CSR_SCOUNTERMASK_M_HPM6_MASK) +#define CSR_SCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM6_MASK) >> CSR_SCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM5_SHIFT) & CSR_SCOUNTERMASK_M_HPM5_MASK) +#define CSR_SCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM5_MASK) >> CSR_SCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM4_SHIFT) & CSR_SCOUNTERMASK_M_HPM4_MASK) +#define CSR_SCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM4_MASK) >> CSR_SCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM3_SHIFT) & CSR_SCOUNTERMASK_M_HPM3_MASK) +#define CSR_SCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM3_MASK) >> CSR_SCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_IR_SHIFT) & CSR_SCOUNTERMASK_M_IR_MASK) +#define CSR_SCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_IR_MASK) >> CSR_SCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_CY_SHIFT) & CSR_SCOUNTERMASK_M_CY_MASK) +#define CSR_SCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_CY_MASK) >> CSR_SCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM6_SHIFT) & CSR_SCOUNTERMASK_S_HPM6_MASK) +#define CSR_SCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM6_MASK) >> CSR_SCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM5_SHIFT) & CSR_SCOUNTERMASK_S_HPM5_MASK) +#define CSR_SCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM5_MASK) >> CSR_SCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM4_SHIFT) & CSR_SCOUNTERMASK_S_HPM4_MASK) +#define CSR_SCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM4_MASK) >> CSR_SCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM3_SHIFT) & CSR_SCOUNTERMASK_S_HPM3_MASK) +#define CSR_SCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM3_MASK) >> CSR_SCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_IR_SHIFT) & CSR_SCOUNTERMASK_S_IR_MASK) +#define CSR_SCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_IR_MASK) >> CSR_SCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_CY_SHIFT) & CSR_SCOUNTERMASK_S_CY_MASK) +#define CSR_SCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_CY_MASK) >> CSR_SCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_SCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_SCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM6_SHIFT) & CSR_SCOUNTERMASK_U_HPM6_MASK) +#define CSR_SCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM6_MASK) >> CSR_SCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_SCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_SCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM5_SHIFT) & CSR_SCOUNTERMASK_U_HPM5_MASK) +#define CSR_SCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM5_MASK) >> CSR_SCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_SCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_SCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM4_SHIFT) & CSR_SCOUNTERMASK_U_HPM4_MASK) +#define CSR_SCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM4_MASK) >> CSR_SCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_SCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_SCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM3_SHIFT) & CSR_SCOUNTERMASK_U_HPM3_MASK) +#define CSR_SCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM3_MASK) >> CSR_SCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_SCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_SCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_IR_SHIFT) & CSR_SCOUNTERMASK_U_IR_MASK) +#define CSR_SCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_IR_MASK) >> CSR_SCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_SCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_SCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_CY_SHIFT) & CSR_SCOUNTERMASK_U_CY_MASK) +#define CSR_SCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_CY_MASK) >> CSR_SCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_SCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_SCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM6_SHIFT) & CSR_SCOUNTEROVF_HPM6_MASK) +#define CSR_SCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM6_MASK) >> CSR_SCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_SCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_SCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM5_SHIFT) & CSR_SCOUNTEROVF_HPM5_MASK) +#define CSR_SCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM5_MASK) >> CSR_SCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_SCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_SCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM4_SHIFT) & CSR_SCOUNTEROVF_HPM4_MASK) +#define CSR_SCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM4_MASK) >> CSR_SCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_SCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_SCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM3_SHIFT) & CSR_SCOUNTEROVF_HPM3_MASK) +#define CSR_SCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM3_MASK) >> CSR_SCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_IR_MASK (0x4U) +#define CSR_SCOUNTEROVF_IR_SHIFT (2U) +#define CSR_SCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_IR_SHIFT) & CSR_SCOUNTEROVF_IR_MASK) +#define CSR_SCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_IR_MASK) >> CSR_SCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTEROVF_CY_MASK (0x1U) +#define CSR_SCOUNTEROVF_CY_SHIFT (0U) +#define CSR_SCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_CY_SHIFT) & CSR_SCOUNTEROVF_CY_MASK) +#define CSR_SCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_CY_MASK) >> CSR_SCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: SCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_SCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_SCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM6_SHIFT) & CSR_SCOUNTINHIBIT_HPM6_MASK) +#define CSR_SCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM6_MASK) >> CSR_SCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_SCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_SCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM5_SHIFT) & CSR_SCOUNTINHIBIT_HPM5_MASK) +#define CSR_SCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM5_MASK) >> CSR_SCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_SCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_SCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM4_SHIFT) & CSR_SCOUNTINHIBIT_HPM4_MASK) +#define CSR_SCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM4_MASK) >> CSR_SCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_SCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_SCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM3_SHIFT) & CSR_SCOUNTINHIBIT_HPM3_MASK) +#define CSR_SCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM3_MASK) >> CSR_SCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_SCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_SCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_IR_SHIFT) & CSR_SCOUNTINHIBIT_IR_MASK) +#define CSR_SCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_IR_MASK) >> CSR_SCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_SCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_SCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_TM_SHIFT) & CSR_SCOUNTINHIBIT_TM_MASK) +#define CSR_SCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_TM_MASK) >> CSR_SCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_SCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_SCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_SCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_CY_SHIFT) & CSR_SCOUNTINHIBIT_CY_MASK) +#define CSR_SCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_CY_MASK) >> CSR_SCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: SHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT3_SEL_SHIFT (4U) +#define CSR_SHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_SEL_SHIFT) & CSR_SHPMEVENT3_SEL_MASK) +#define CSR_SHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_SEL_MASK) >> CSR_SHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_TYPE_SHIFT) & CSR_SHPMEVENT3_TYPE_MASK) +#define CSR_SHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_TYPE_MASK) >> CSR_SHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT4_SEL_SHIFT (4U) +#define CSR_SHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_SEL_SHIFT) & CSR_SHPMEVENT4_SEL_MASK) +#define CSR_SHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_SEL_MASK) >> CSR_SHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_TYPE_SHIFT) & CSR_SHPMEVENT4_TYPE_MASK) +#define CSR_SHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_TYPE_MASK) >> CSR_SHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT5_SEL_SHIFT (4U) +#define CSR_SHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_SEL_SHIFT) & CSR_SHPMEVENT5_SEL_MASK) +#define CSR_SHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_SEL_MASK) >> CSR_SHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_TYPE_SHIFT) & CSR_SHPMEVENT5_TYPE_MASK) +#define CSR_SHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_TYPE_MASK) >> CSR_SHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: SHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_SHPMEVENT6_SEL_SHIFT (4U) +#define CSR_SHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_SEL_SHIFT) & CSR_SHPMEVENT6_SEL_MASK) +#define CSR_SHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_SEL_MASK) >> CSR_SHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_SHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_SHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_SHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_TYPE_SHIFT) & CSR_SHPMEVENT6_TYPE_MASK) +#define CSR_SHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_TYPE_MASK) >> CSR_SHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MICM_CFG */ +/* + * SETH (RO) + * + * This bit extends the ISET field. + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MICM_CFG_SETH_SHIFT (24U) +#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) + +/* + * ILM_ECC (RO) + * + * ILM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) +#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) +#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) + +/* + * ILMSZ (RO) + * + * ILM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) +#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) +#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) + +/* + * ILMB (RW) + * + * Number of ILM base registers present + * 0:No ILM base register present + * 1:One ILM base register present + * 2-7:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMB_MASK (0x7000U) +#define CSR_MICM_CFG_ILMB_SHIFT (12U) +#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) +#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) + +/* + * IC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) +#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) +#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) + +/* + * ILCK (RO) + * + * I-Cache locking support + * 0:No locking support + * 1:With locking support + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILCK_MASK (0x200U) +#define CSR_MICM_CFG_ILCK_SHIFT (9U) +#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) + +/* + * ISZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) +#define CSR_MICM_CFG_ISZ_SHIFT (6U) +#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) + +/* + * IWAY (RO) + * + * Associativity of I-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IWAY_MASK (0x38U) +#define CSR_MICM_CFG_IWAY_SHIFT (3U) +#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) + +/* + * ISET (RO) + * + * I-Cache sets (# of cache lines per way): + * When micm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When micm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + */ +#define CSR_MICM_CFG_ISET_MASK (0x7U) +#define CSR_MICM_CFG_ISET_SHIFT (0U) +#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) + +/* Bitfield definition for register: MDCM_CFG */ +/* + * SETH (RO) + * + * This bit extends the DSET field. + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MDCM_CFG_SETH_SHIFT (24U) +#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) + +/* + * DLM_ECC (RO) + * + * DLM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When DLM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) +#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) +#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) + +/* + * DLMSZ (RO) + * + * DLM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) +#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) +#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) + +/* + * DLMB (RO) + * + * Number of DLM base registers present + * 0:No DLM base register present + * 1:One DLM base register present + * 2-7:Reserved + * When DLM is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) +#define CSR_MDCM_CFG_DLMB_SHIFT (12U) +#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) + +/* + * DC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC support + * 1:Has parity support + * 2:Has ECC support + * 3:Reserved + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) +#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) +#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) + +/* + * DLCK (RO) + * + * D-Cache locking support + * 0:No locking support + * 1:With locking support + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLCK_MASK (0x200U) +#define CSR_MDCM_CFG_DLCK_SHIFT (9U) +#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) + +/* + * DSZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) +#define CSR_MDCM_CFG_DSZ_SHIFT (6U) +#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) + +/* + * DWAY (RO) + * + * Associativity of D-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DWAY_MASK (0x38U) +#define CSR_MDCM_CFG_DWAY_SHIFT (3U) +#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) + +/* + * DSET (RO) + * + * D-Cache sets (# of cache lines per way): + * When mdcm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When mdcm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DSET_MASK (0x7U) +#define CSR_MDCM_CFG_DSET_SHIFT (0U) +#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) + +/* Bitfield definition for register: MMSC_CFG */ +/* + * MSC_EXT (RO) + * + * Indicates if the mmsc_cfg2 CSR is present or not. + * 0:The mmsc_cfg2 CSR is not present. + * 1:The mmsc_cfg2 CSR is present + */ +#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) +#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) +#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) + +/* + * PPMA (RO) + * + * Indicates if programmable PMA setup with PMA region CSRs is supported or not + * 0:Programmable PMA setup is not supported. + * 1:Programmable PMA setup is supported. + */ +#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) +#define CSR_MMSC_CFG_PPMA_SHIFT (30U) +#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) + +/* + * EDSP (RO) + * + * Indicates if the DSP extension is supported or not + * 0:The DSP extension is not supported. + * 1:The DSP extension is supported. + */ +#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) +#define CSR_MMSC_CFG_EDSP_SHIFT (29U) +#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) + +/* + * VCCTL (RO) + * + * Indicates the version number of CCTL command operation scheme supported by an implementation + * 0:instruction cache and data cache are not configured. + * 1:instruction cache or data cache is configured. + */ +#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) +#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) +#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) + +/* + * EFHW (RO) + * + * Indicates the support of FLHW and FSHW instructions + * 0:FLHW and FSHW instructions are not supported + * 1:FLHW and FSHW instructions are supported. + */ +#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) +#define CSR_MMSC_CFG_EFHW_SHIFT (17U) +#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) + +/* + * CCTLCSR (RO) + * + * Indicates the presence of CSRs for CCTL operations. + * 0:Feature of CSRs for CCTL operations is not supported. + * 1:Feature of CSRs for CCTL operations is supported. + */ +#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) +#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) +#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) + +/* + * PMNDS (RO) + * + * Indicates if Andes-enhanced performance monitoring feature is present or no. + * 0:Andes-enhanced performance monitoring feature is not supported. + * 1:Andes-enhanced performance monitoring feature is supported. + */ +#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) +#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) +#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) + +/* + * LMSLVP (RO) + * + * Indicates if local memory slave port is present or not. + * 0:Local memory slave port is not present. + * 1:Local memory slave port is implemented. + */ +#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) +#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) +#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) + +/* + * EV5PE (RO) + * + * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) +#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) +#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) + +/* + * VPLIC (RO) + * + * Indicates whether the Andes Vectored PLIC Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) +#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) +#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) + +/* + * ACE (RO) + * + * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ACE_MASK (0x40U) +#define CSR_MMSC_CFG_ACE_SHIFT (6U) +#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) + +/* + * HSP (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_HSP_MASK (0x20U) +#define CSR_MMSC_CFG_HSP_SHIFT (5U) +#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) + +/* + * PFT (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_PFT_MASK (0x10U) +#define CSR_MMSC_CFG_PFT_SHIFT (4U) +#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) + +/* + * ECD (RO) + * + * Indicates whether the Andes CoDense Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ECD_MASK (0x8U) +#define CSR_MMSC_CFG_ECD_SHIFT (3U) +#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) + +/* + * TLB_ECC (RO) + * + * TLB parity/ECC support configuration. + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + */ +#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) +#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) +#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) + +/* + * ECC (RO) + * + * Indicates whether the parity/ECC soft-error protection is implemented or not. + * 0:Not implemented. + * 1:Implemented. + * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. + * micm_cfg.IC_ECC + * micm_cfg.ILM_ECC + * mdcm_cfg.DC_ECC + * mdcm_cfg.DLM_ECC + * mmsc_cfg.TLB_ECC + */ +#define CSR_MMSC_CFG_ECC_MASK (0x1U) +#define CSR_MMSC_CFG_ECC_SHIFT (0U) +#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) + +/* Bitfield definition for register: MMSC_CFG2 */ +/* + * FINV (RO) + * + * Indicates if scalar FPU is implemented in VPU + * 0:Scalar FPU is not implemented in VPU + * 1:Scalar FPU is implemented in VPU + */ +#define CSR_MMSC_CFG2_FINV_MASK (0x20U) +#define CSR_MMSC_CFG2_FINV_SHIFT (5U) +#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) + +/* + * ZFH (RO) + * + * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. + * 0:The FP16 extension is not supported. + * 1:The FP16 extension is supported + */ +#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) +#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) +#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) + +/* + * BF16CVT (RO) + * + * Indicates if the BFLOAT16 conversion extension + * is supported or not. + * 0:The BFLOAT16 conversion extension is not supported + * 1:The BFLOAT16 conversion extension is supported + */ +#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) +#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) +#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) + + +#endif /* HPM_CSR_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_src.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_src.h new file mode 100644 index 00000000..01196a2e --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_dmamux_src.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_SRC_H +#define HPM_DMAMUX_SRC_H + +/* dma mux definitions */ +#define HPM_DMA_SRC_SPI0_RX (0x0UL) +#define HPM_DMA_SRC_SPI0_TX (0x1UL) +#define HPM_DMA_SRC_SPI1_RX (0x2UL) +#define HPM_DMA_SRC_SPI1_TX (0x3UL) +#define HPM_DMA_SRC_SPI2_RX (0x4UL) +#define HPM_DMA_SRC_SPI2_TX (0x5UL) +#define HPM_DMA_SRC_SPI3_RX (0x6UL) +#define HPM_DMA_SRC_SPI3_TX (0x7UL) +#define HPM_DMA_SRC_UART0_RX (0x8UL) +#define HPM_DMA_SRC_UART0_TX (0x9UL) +#define HPM_DMA_SRC_UART1_RX (0xAUL) +#define HPM_DMA_SRC_UART1_TX (0xBUL) +#define HPM_DMA_SRC_UART2_RX (0xCUL) +#define HPM_DMA_SRC_UART2_TX (0xDUL) +#define HPM_DMA_SRC_UART3_RX (0xEUL) +#define HPM_DMA_SRC_UART3_TX (0xFUL) +#define HPM_DMA_SRC_UART4_RX (0x10UL) +#define HPM_DMA_SRC_UART4_TX (0x11UL) +#define HPM_DMA_SRC_UART5_RX (0x12UL) +#define HPM_DMA_SRC_UART5_TX (0x13UL) +#define HPM_DMA_SRC_UART6_RX (0x14UL) +#define HPM_DMA_SRC_UART6_TX (0x15UL) +#define HPM_DMA_SRC_UART7_RX (0x16UL) +#define HPM_DMA_SRC_UART7_TX (0x17UL) +#define HPM_DMA_SRC_MOT0_0 (0x18UL) +#define HPM_DMA_SRC_MOT0_1 (0x19UL) +#define HPM_DMA_SRC_MOT0_2 (0x1AUL) +#define HPM_DMA_SRC_MOT0_3 (0x1BUL) +#define HPM_DMA_SRC_MOT1_0 (0x1CUL) +#define HPM_DMA_SRC_MOT1_1 (0x1DUL) +#define HPM_DMA_SRC_MOT1_2 (0x1EUL) +#define HPM_DMA_SRC_MOT1_3 (0x1FUL) +#define HPM_DMA_SRC_MOT2_0 (0x20UL) +#define HPM_DMA_SRC_MOT2_1 (0x21UL) +#define HPM_DMA_SRC_MOT2_2 (0x22UL) +#define HPM_DMA_SRC_MOT2_3 (0x23UL) +#define HPM_DMA_SRC_MOT3_0 (0x24UL) +#define HPM_DMA_SRC_MOT3_1 (0x25UL) +#define HPM_DMA_SRC_MOT3_2 (0x26UL) +#define HPM_DMA_SRC_MOT3_3 (0x27UL) +#define HPM_DMA_SRC_GPTMR0_0 (0x28UL) +#define HPM_DMA_SRC_GPTMR0_1 (0x29UL) +#define HPM_DMA_SRC_GPTMR0_2 (0x2AUL) +#define HPM_DMA_SRC_GPTMR0_3 (0x2BUL) +#define HPM_DMA_SRC_GPTMR1_0 (0x2CUL) +#define HPM_DMA_SRC_GPTMR1_1 (0x2DUL) +#define HPM_DMA_SRC_GPTMR1_2 (0x2EUL) +#define HPM_DMA_SRC_GPTMR1_3 (0x2FUL) +#define HPM_DMA_SRC_GPTMR2_0 (0x30UL) +#define HPM_DMA_SRC_GPTMR2_1 (0x31UL) +#define HPM_DMA_SRC_GPTMR2_2 (0x32UL) +#define HPM_DMA_SRC_GPTMR2_3 (0x33UL) +#define HPM_DMA_SRC_GPTMR3_0 (0x34UL) +#define HPM_DMA_SRC_GPTMR3_1 (0x35UL) +#define HPM_DMA_SRC_GPTMR3_2 (0x36UL) +#define HPM_DMA_SRC_GPTMR3_3 (0x37UL) +#define HPM_DMA_SRC_I2C0 (0x38UL) +#define HPM_DMA_SRC_I2C1 (0x39UL) +#define HPM_DMA_SRC_I2C2 (0x3AUL) +#define HPM_DMA_SRC_I2C3 (0x3BUL) +#define HPM_DMA_SRC_XPI0_RX (0x3CUL) +#define HPM_DMA_SRC_XPI0_TX (0x3DUL) +#define HPM_DMA_SRC_DAC0 (0x3EUL) +#define HPM_DMA_SRC_DAC1 (0x3FUL) +#define HPM_DMA_SRC_ACMP_0 (0x40UL) +#define HPM_DMA_SRC_ACMP_1 (0x41UL) +#define HPM_DMA_SRC_ACMP_2 (0x42UL) +#define HPM_DMA_SRC_ACMP_3 (0x43UL) +#define HPM_DMA_SRC_MCAN0 (0x44UL) +#define HPM_DMA_SRC_MCAN1 (0x45UL) +#define HPM_DMA_SRC_MCAN2 (0x46UL) +#define HPM_DMA_SRC_MCAN3 (0x47UL) + + + +#endif /* HPM_DMAMUX_SRC_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h new file mode 100644 index 00000000..dfd46a33 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_regs.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_GPIOM_H +#define HPM_GPIOM_H + +typedef struct { + struct { + __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ + } ASSIGN[16]; +} GPIOM_Type; + + +/* Bitfield definition for register of struct array ASSIGN: PIN00 */ +/* + * LOCK (RW) + * + * lock fields in this register, lock can only be cleared by soc reset + * 0: fields can be changed + * 1: fields locked to current value, not changeable + */ +#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) +#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) +#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) +#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) + +/* + * HIDE (RW) + * + * pin value visibility to gpios, + * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 + * bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 + * bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + * bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio + */ +#define GPIOM_ASSIGN_PIN_HIDE_MASK (0xF00U) +#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) +#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) +#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) + +/* + * SELECT (RW) + * + * select which gpio controls chip pin, + * 0: soc gpio0; + * 1: soc gpio1; + * 2: cpu0 fastgpio + * 3: cpu1 fast gpio + */ +#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U) +#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) +#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) +#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) + + + +/* PIN register group index macro definition */ +#define GPIOM_ASSIGN_PIN_PIN00 (0UL) +#define GPIOM_ASSIGN_PIN_PIN01 (1UL) +#define GPIOM_ASSIGN_PIN_PIN02 (2UL) +#define GPIOM_ASSIGN_PIN_PIN03 (3UL) +#define GPIOM_ASSIGN_PIN_PIN04 (4UL) +#define GPIOM_ASSIGN_PIN_PIN05 (5UL) +#define GPIOM_ASSIGN_PIN_PIN06 (6UL) +#define GPIOM_ASSIGN_PIN_PIN07 (7UL) +#define GPIOM_ASSIGN_PIN_PIN08 (8UL) +#define GPIOM_ASSIGN_PIN_PIN09 (9UL) +#define GPIOM_ASSIGN_PIN_PIN10 (10UL) +#define GPIOM_ASSIGN_PIN_PIN11 (11UL) +#define GPIOM_ASSIGN_PIN_PIN12 (12UL) +#define GPIOM_ASSIGN_PIN_PIN13 (13UL) +#define GPIOM_ASSIGN_PIN_PIN14 (14UL) +#define GPIOM_ASSIGN_PIN_PIN15 (15UL) +#define GPIOM_ASSIGN_PIN_PIN16 (16UL) +#define GPIOM_ASSIGN_PIN_PIN17 (17UL) +#define GPIOM_ASSIGN_PIN_PIN18 (18UL) +#define GPIOM_ASSIGN_PIN_PIN19 (19UL) +#define GPIOM_ASSIGN_PIN_PIN20 (20UL) +#define GPIOM_ASSIGN_PIN_PIN21 (21UL) +#define GPIOM_ASSIGN_PIN_PIN22 (22UL) +#define GPIOM_ASSIGN_PIN_PIN23 (23UL) +#define GPIOM_ASSIGN_PIN_PIN24 (24UL) +#define GPIOM_ASSIGN_PIN_PIN25 (25UL) +#define GPIOM_ASSIGN_PIN_PIN26 (26UL) +#define GPIOM_ASSIGN_PIN_PIN27 (27UL) +#define GPIOM_ASSIGN_PIN_PIN28 (28UL) +#define GPIOM_ASSIGN_PIN_PIN29 (29UL) +#define GPIOM_ASSIGN_PIN_PIN30 (30UL) +#define GPIOM_ASSIGN_PIN_PIN31 (31UL) + +/* ASSIGN register group index macro definition */ +#define GPIOM_ASSIGN_GPIOA (0UL) +#define GPIOM_ASSIGN_GPIOB (1UL) +#define GPIOM_ASSIGN_GPIOC (2UL) +#define GPIOM_ASSIGN_GPIOX (13UL) +#define GPIOM_ASSIGN_GPIOY (14UL) +#define GPIOM_ASSIGN_GPIOZ (15UL) + + +#endif /* HPM_GPIOM_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h new file mode 100644 index 00000000..2f2aecb9 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2023 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GPIOM_SOC_DRV_H +#define HPM_GPIOM_SOC_DRV_H + +/** + * @addtogroup gpiom_interface GPIOM driver APIs + * @{ + */ + +/* @brief gpiom control module */ +typedef enum hpm6300_gpiom_gpio { + gpiom_soc_gpio0 = 0, + gpiom_soc_gpio1 = 1, + gpiom_core0_fast = 2, + gpiom_core1_fast = 3, +} gpiom_gpio_t; + +/** + * @} + */ + +#endif /* HPM_GPIOM_SOC_DRV_H */ + diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h new file mode 100644 index 00000000..356e6798 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h @@ -0,0 +1,1018 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_INTERRUPT_H +#define HPM_INTERRUPT_H +#include "riscv/riscv_core.h" +#include "hpm_common.h" +#include "hpm_plic_drv.h" + +/** + * @brief INTERRUPT driver APIs + * @defgroup irq_interface INTERRUPT driver APIs + * @{ + */ + +#define M_MODE 0 /*!< Machine mode */ +#define S_MODE 1 /*!< Supervisor mode */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Machine mode API: these APIs are supposed to be called at machine mode */ + +/** + * @brief Enable global IRQ with mask + * + * @param[in] mask interrupt mask to be enabaled + */ +ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Disable global IRQ with mask + * + * @param[in] mask interrupt mask to be disabled + */ +ATTR_ALWAYS_INLINE static inline void disable_global_irq(uint32_t mask) +{ + clear_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Enable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) +{ + set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Disable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Enable machine timer IRQ + */ +ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) +{ + set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/** + * @brief Disable machine timer IRQ + * + */ +ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/** + * @brief Delegate IRQ handling + * + * @param[in] mask interrupt mask to be delegated + */ +ATTR_ALWAYS_INLINE static inline void delegate_irq(uint32_t mask) +{ + set_csr(CSR_MIDELEG, mask); +} + +/** + * @brief Undelegate IRQ handling + * + * @param[in] mask interrupt mask to be undelegated + */ +ATTR_ALWAYS_INLINE static inline void undelegate_irq(uint32_t mask) +{ + clear_csr(CSR_MIDELEG, mask); +} + + +/* Supervisor mode API: these APIs are supposed to be called at supervisor mode */ + +/** + * @brief Enable global IRQ with mask for supervisor mode + * + * @param[in] mask interrupt mask to be enabaled + */ +ATTR_ALWAYS_INLINE static inline void enable_s_global_irq(uint32_t mask) +{ + set_csr(CSR_SSTATUS, mask); +} + +/** + * @brief Disable global IRQ with mask for supervisor mode + * + * @param[in] mask interrupt mask to be disabled + */ +ATTR_ALWAYS_INLINE static inline void disable_s_global_irq(uint32_t mask) +{ + clear_csr(CSR_SSTATUS, mask); +} + +/** + * @brief Disable IRQ from interrupt controller for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void disable_s_irq_from_intc(void) +{ + clear_csr(CSR_SIE, CSR_SIE_SEIE_MASK); +} + +/** + * @brief Enable IRQ from interrupt controller for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void enable_s_irq_from_intc(void) +{ + set_csr(CSR_SIE, CSR_SIE_SEIE_MASK); +} + +/** + * @brief Enable machine timer IRQ for supervisor mode + */ +ATTR_ALWAYS_INLINE static inline void enable_s_mchtmr_irq(void) +{ + set_csr(CSR_SIE, CSR_SIE_STIE_MASK); +} + +/** + * @brief Disable machine timer IRQ + * + */ +ATTR_ALWAYS_INLINE static inline void disable_s_mchtmr_irq(void) +{ + clear_csr(CSR_SIE, CSR_SIE_STIE_MASK); +} + + +/* + * CPU Machine SWI control + * + * Machine SWI (MSIP) is connected to PLICSW irq 1. + */ +#define PLICSWI 1 + +/** + * @brief Initialize software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) +{ + __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + + +/** + * @brief Enable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) +{ + set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Disable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Trigger software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) +{ + __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); +} + +/** + * @brief Claim software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) +{ + __plic_claim_irq(HPM_PLICSW_BASE, 0); +} + +/** + * @brief Complete software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) +{ + __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + +/* + * @brief Enable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_enable_irq(irq) \ + intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Disable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_disable_irq(irq) \ + intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +#define intc_m_set_threshold(threshold) \ + intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) + +/* + * @brief Complete IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_complete_irq(irq) \ + intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Claim IRQ for machine mode + * + */ +#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) + +/* + * @brief Enable IRQ for machine mode with priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +#define intc_m_enable_irq_with_priority(irq, priority) \ + do { \ + intc_set_irq_priority(irq, priority); \ + intc_m_enable_irq(irq); \ + } while (0) + + + +/* Supervisor mode */ + +/** + * @brief Enable software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_enable_swi(void) +{ + set_csr(CSR_SIE, CSR_SIE_SSIE_MASK); +} + + +/** + * @brief Disable software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_disable_swi(void) +{ + clear_csr(CSR_SIE, CSR_SIE_SSIE_MASK); +} + + +/** + * @brief Trigger software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_trigger_swi(void) +{ + set_csr(CSR_SIP, CSR_SIP_SSIP_MASK); +} + + +/** + * @brief Complete software interrupt for supervisor mode + * + */ +ATTR_ALWAYS_INLINE static inline void intc_s_complete_swi(void) +{ + clear_csr(CSR_SIP, CSR_SIP_SSIP_MASK); +} + +/* + * @brief Enable IRQ for supervisor mode + * + * @param[in] irq Interrupt number + */ +#define intc_s_enable_irq(irq) \ + intc_enable_irq(HPM_PLIC_TARGET_S_MODE, irq) + +/* + * @brief Disable IRQ for supervisor mode + * + * @param[in] irq Interrupt number + */ +#define intc_s_disable_irq(irq) \ + intc_disable_irq(HPM_PLIC_TARGET_S_MODE, irq) + +#define intc_set_s_threshold(threshold) \ + intc_set_threshold(HPM_PLIC_TARGET_S_MODE, threshold) + +/* + * @brief Complete IRQ for supervisor mode + * + * @param[in] irq Interrupt number + */ +#define intc_s_complete_irq(irq) \ + intc_complete_irq(HPM_PLIC_TARGET_S_MODE, irq) + +/* + * @brief Claim IRQ for supervisor mode + * + */ +#define intc_s_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_S_MODE) + +/* + * @brief Enable IRQ for supervisor mode with priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +#define intc_s_enable_irq_with_priority(irq, priority) \ + do { \ + intc_set_irq_priority(irq, priority); \ + intc_s_enable_irq(irq); \ + } while (0) + + +/* + * @brief Enable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) +{ + __plic_enable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) +{ + __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); +} + +/** + * @brief Disable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) +{ + __plic_disable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt threshold + * + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + */ +ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) +{ + __plic_set_threshold(HPM_PLIC_BASE, target, threshold); +} + +/** + * @brief Claim IRQ + * + * @param[in] target Target to handle specific interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) +{ + return __plic_claim_irq(HPM_PLIC_BASE, target); +} + +/** + * @brief Complete IRQ + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Specific IRQ to be completed + * + */ +ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) +{ + __plic_complete_irq(HPM_PLIC_BASE, target, irq); +} + +/* + * Vectored based irq install and uninstall + */ +/* Machine mode */ +extern int __vector_table[]; +extern void default_irq_entry(void); + +/** + * @brief Install ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * @param[in] isr Interrupt service routine + * + */ +ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) +{ + __vector_table[irq] = isr; +} + +/** + * @brief Uninstall ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) +{ + __vector_table[irq] = (int) default_irq_entry; +} + +/* Supervisor mode */ +extern int __vector_s_table[]; +extern void default_s_irq_entry(void); +/** + * @brief Install ISR for certain IRQ for ram based vector table for supervisor mode + * + * @param[in] irq Target interrupt number + * @param[in] isr Interrupt service routine + * + */ +ATTR_ALWAYS_INLINE static inline void install_s_isr(uint32_t irq, uint32_t isr) +{ + __vector_s_table[irq] = isr; +} + +/** + * @brief Uninstall ISR for certain IRQ for ram based vector table for supervisor mode + * + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) +{ + __vector_s_table[irq] = (int) default_s_irq_entry; +} + + +/* + * Inline nested irq entry/exit macros + */ +/* + * @brief Save CSR + * @param[in] r Target CSR to be saved + */ +#define SAVE_CSR(r) register long __##r = read_csr(r); + +/* + * @brief Restore macro + * + * @param[in] r Target CSR to be restored + */ +#define RESTORE_CSR(r) write_csr(r, __##r); + +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH +#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) +#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) +#else +#define SAVE_MXSTATUS() +#define RESTORE_MXSTATUS() +#endif + +#ifdef __riscv_flen +#define SAVE_FCSR() register int __fcsr = read_fcsr(); +#define RESTORE_FCSR() write_fcsr(__fcsr); +#else +#define SAVE_FCSR() +#define RESTORE_FCSR() +#endif + +#ifdef __riscv_dsp +#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) +#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) +#else +#define SAVE_UCODE() +#define RESTORE_UCODE() +#endif + +#ifdef __riscv_flen +#if __riscv_flen == 32 +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 FPU caller registers +FCSR + UCODE (DSP) */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) +#else /* __riscv_flen = 64 */ +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 DFPU caller + FCSR registers + UCODE (DSP) */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20 * 2)) +#endif + +#else +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/ +#define CONTEXT_REG_NUM (4 * (16 + 4)) +#endif + +#ifdef __riscv_flen +/* + * Save FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#if __riscv_flen == 32 +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fswsp ft0, 20*4(sp)\n\ + c.fswsp ft1, 21*4(sp) \n\ + c.fswsp ft2, 22*4(sp) \n\ + c.fswsp ft3, 23*4(sp) \n\ + c.fswsp ft4, 24*4(sp) \n\ + c.fswsp ft5, 25*4(sp) \n\ + c.fswsp ft6, 26*4(sp) \n\ + c.fswsp ft7, 27*4(sp) \n\ + c.fswsp fa0, 28*4(sp) \n\ + c.fswsp fa1, 29*4(sp) \n\ + c.fswsp fa2, 30*4(sp) \n\ + c.fswsp fa3, 31*4(sp) \n\ + c.fswsp fa4, 32*4(sp) \n\ + c.fswsp fa5, 33*4(sp) \n\ + c.fswsp fa6, 34*4(sp) \n\ + c.fswsp fa7, 35*4(sp) \n\ + c.fswsp ft8, 36*4(sp) \n\ + c.fswsp ft9, 37*4(sp) \n\ + c.fswsp ft10, 38*4(sp) \n\ + c.fswsp ft11, 39*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.flwsp ft0, 20*4(sp)\n\ + c.flwsp ft1, 21*4(sp) \n\ + c.flwsp ft2, 22*4(sp) \n\ + c.flwsp ft3, 23*4(sp) \n\ + c.flwsp ft4, 24*4(sp) \n\ + c.flwsp ft5, 25*4(sp) \n\ + c.flwsp ft6, 26*4(sp) \n\ + c.flwsp ft7, 27*4(sp) \n\ + c.flwsp fa0, 28*4(sp) \n\ + c.flwsp fa1, 29*4(sp) \n\ + c.flwsp fa2, 30*4(sp) \n\ + c.flwsp fa3, 31*4(sp) \n\ + c.flwsp fa4, 32*4(sp) \n\ + c.flwsp fa5, 33*4(sp) \n\ + c.flwsp fa6, 34*4(sp) \n\ + c.flwsp fa7, 35*4(sp) \n\ + c.flwsp ft8, 36*4(sp) \n\ + c.flwsp ft9, 37*4(sp) \n\ + c.flwsp ft10, 38*4(sp) \n\ + c.flwsp ft11, 39*4(sp) \n");\ +} +#else /*__riscv_flen == 64*/ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4(sp)\n\ + c.fsdsp ft1, 22*4(sp) \n\ + c.fsdsp ft2, 24*4(sp) \n\ + c.fsdsp ft3, 26*4(sp) \n\ + c.fsdsp ft4, 28*4(sp) \n\ + c.fsdsp ft5, 30*4(sp) \n\ + c.fsdsp ft6, 32*4(sp) \n\ + c.fsdsp ft7, 34*4(sp) \n\ + c.fsdsp fa0, 36*4(sp) \n\ + c.fsdsp fa1, 38*4(sp) \n\ + c.fsdsp fa2, 40*4(sp) \n\ + c.fsdsp fa3, 42*4(sp) \n\ + c.fsdsp fa4, 44*4(sp) \n\ + c.fsdsp fa5, 46*4(sp) \n\ + c.fsdsp fa6, 48*4(sp) \n\ + c.fsdsp fa7, 50*4(sp) \n\ + c.fsdsp ft8, 52*4(sp) \n\ + c.fsdsp ft9, 54*4(sp) \n\ + c.fsdsp ft10, 56*4(sp) \n\ + c.fsdsp ft11, 58*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4(sp)\n\ + c.fldsp ft1, 22*4(sp) \n\ + c.fldsp ft2, 24*4(sp) \n\ + c.fldsp ft3, 26*4(sp) \n\ + c.fldsp ft4, 28*4(sp) \n\ + c.fldsp ft5, 30*4(sp) \n\ + c.fldsp ft6, 32*4(sp) \n\ + c.fldsp ft7, 34*4(sp) \n\ + c.fldsp fa0, 36*4(sp) \n\ + c.fldsp fa1, 38*4(sp) \n\ + c.fldsp fa2, 40*4(sp) \n\ + c.fldsp fa3, 42*4(sp) \n\ + c.fldsp fa4, 44*4(sp) \n\ + c.fldsp fa5, 46*4(sp) \n\ + c.fldsp fa6, 48*4(sp) \n\ + c.fldsp fa7, 50*4(sp) \n\ + c.fldsp ft8, 52*4(sp) \n\ + c.fldsp ft9, 54*4(sp) \n\ + c.fldsp ft10, 56*4(sp) \n\ + c.fldsp ft11, 58*4(sp) \n");\ +} +#endif +#else +#define SAVE_FPU_CONTEXT() +#define RESTORE_FPU_CONTEXT() +#endif + +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("\n\ + c.swsp ra, 0*4(sp) \n\ + c.swsp t0, 1*4(sp) \n\ + c.swsp t1, 2*4(sp) \n\ + c.swsp t2, 3*4(sp) \n\ + c.swsp s0, 4*4(sp) \n\ + c.swsp s1, 5*4(sp) \n\ + c.swsp a0, 6*4(sp) \n\ + c.swsp a1, 7*4(sp) \n\ + c.swsp a2, 8*4(sp) \n\ + c.swsp a3, 9*4(sp) \n\ + c.swsp a4, 10*4(sp) \n\ + c.swsp a5, 11*4(sp) \n\ + c.swsp a6, 12*4(sp) \n\ + c.swsp a7, 13*4(sp) \n\ + c.swsp s2, 14*4(sp) \n\ + c.swsp s3, 15*4(sp) \n\ + c.swsp t3, 16*4(sp) \n\ + c.swsp t4, 17*4(sp) \n\ + c.swsp t5, 18*4(sp) \n\ + c.swsp t6, 19*4(sp)"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("\n\ + c.lwsp ra, 0*4(sp) \n\ + c.lwsp t0, 1*4(sp) \n\ + c.lwsp t1, 2*4(sp) \n\ + c.lwsp t2, 3*4(sp) \n\ + c.lwsp s0, 4*4(sp) \n\ + c.lwsp s1, 5*4(sp) \n\ + c.lwsp a0, 6*4(sp) \n\ + c.lwsp a1, 7*4(sp) \n\ + c.lwsp a2, 8*4(sp) \n\ + c.lwsp a3, 9*4(sp) \n\ + c.lwsp a4, 10*4(sp) \n\ + c.lwsp a5, 11*4(sp) \n\ + c.lwsp a6, 12*4(sp) \n\ + c.lwsp a7, 13*4(sp) \n\ + c.lwsp s2, 14*4(sp) \n\ + c.lwsp s3, 15*4(sp) \n\ + c.lwsp t3, 16*4(sp) \n\ + c.lwsp t4, 17*4(sp) \n\ + c.lwsp t5, 18*4(sp) \n\ + c.lwsp t6, 19*4(sp) \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} + +#ifdef __riscv_flen +#define SAVE_FPU_STATE() { \ + __asm volatile("frsr s1\n"); \ +} + +#define RESTORE_FPU_STATE() { \ + __asm volatile("fssr s1\n"); \ +} +#else +#define SAVE_FPU_STATE() +#define RESTORE_FPU_STATE() +#endif + +#ifdef __riscv_dsp +/* + * Save DSP context + * NOTE: DSP context registers are stored at word offset 41 in the stack + */ +#define SAVE_DSP_CONTEXT() { \ + __asm volatile("rdov s0\n"); \ +} +/* + * @brief Restore DSP context + * @note DSP context registers are stored at word offset 41 in the stack + */ +#define RESTORE_DSP_CONTEXT() {\ + __asm volatile("csrw ucode, s0\n"); \ +} + +#else +#define SAVE_DSP_CONTEXT() +#define RESTORE_DSP_CONTEXT() +#endif + +/* + * @brief Enter Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define ENTER_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrr s2, mepc \n\ + csrr s3, mstatus \n");\ + SAVE_FPU_STATE(); \ + SAVE_DSP_CONTEXT(); \ + __asm volatile ("\n\ + c.li a5, 8\n\ + csrs mstatus, a5\n"); \ +} + +/* + * @brief Complete IRQ Handling + */ +#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ + __asm volatile("\n\ + lui a5, 0x1\n\ + addi a5, a5, -2048\n\ + csrc mie, a5\n"); \ + __asm volatile("\n\ + lui a4, 0xe4200\n");\ + __asm volatile("li a3, %0" : : "i" (irq_num) :); \ + __asm volatile("sw a3, 4(a4)\n\ + fence io, io\n"); \ + __asm volatile("csrs mie, a5"); \ +} + +/* + * @brief Exit Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define EXIT_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrw mstatus, s3 \n\ + csrw mepc, s2 \n");\ + RESTORE_FPU_STATE(); \ + RESTORE_DSP_CONTEXT(); \ +} + + +#define ENTER_NESTED_IRQ_HANDLING_S() {\ + __asm volatile("\n\ + csrr s2, sepc \n\ + csrr s3, sstatus \n");\ + SAVE_FPU_STATE(); \ + SAVE_DSP_CONTEXT(); \ + __asm volatile ("\n\ + c.li a5, 8\n\ + csrs sstatus, a5\n"); \ +} +#define COMPLETE_IRQ_HANDLING_S(irq_num) {\ + __asm volatile("\n\ + lui a5, 0x1\n\ + addi a5, a5, -2048\n\ + csrc sie, a5\n"); \ + __asm volatile("\n\ + lui a4, 0xe4201\n");\ + __asm volatile("li a3, %0" : : "i" (irq_num) :); \ + __asm volatile("sw a3, 4(a4)\n\ + fence io, io\n"); \ + __asm volatile("csrs sie, a5"); \ +} + + +/* + * @brief Exit Nested IRQ Handling at supervisor mode + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * SCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * SSTATUS = word offset 18 + */ +#define EXIT_NESTED_IRQ_HANDLING_S() { \ + __asm volatile("\n\ + csrw sstatus, s3 \n\ + csrw sepc, s2 \n");\ + RESTORE_FPU_STATE(); \ + RESTORE_DSP_CONTEXT(); \ +} + +/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ +#define NESTED_IRQ_ENTER() \ + SAVE_CSR(CSR_MEPC) \ + SAVE_CSR(CSR_MSTATUS) \ + SAVE_MXSTATUS() \ + SAVE_FCSR() \ + SAVE_UCODE() \ + set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +/* @brief Nested IRQ exit macro : Restore CSRs */ +#define NESTED_IRQ_EXIT() \ + RESTORE_CSR(CSR_MSTATUS) \ + RESTORE_CSR(CSR_MEPC) \ + RESTORE_MXSTATUS() \ + RESTORE_FCSR() \ + RESTORE_UCODE() + +/* + * @brief Nested IRQ exit macro : Restore CSRs + * @param[in] irq Target interrupt number + */ +#define NESTED_VPLIC_COMPLETE_INTERRUPT(irq) \ +do { \ + clear_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq); \ + __asm volatile("fence io, io"); \ + set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ +} while (0) + +#ifdef __cplusplus +#define EXTERN_C extern "C" +#else +#define EXTERN_C +#endif + +#define ISR_NAME_M(irq_num) default_isr_##irq_num +#define ISR_NAME_S(irq_num) default_isr_s_##irq_num +/** + * @brief Declare an external interrupt handler for machine mode + * + * @param[in] irq_num - IRQ number index + * @param[in] isr - Application IRQ handler function pointer + */ +#ifndef USE_NONVECTOR_MODE + +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) \ +{ \ + SAVE_CALLER_CONTEXT(); \ + ENTER_NESTED_IRQ_HANDLING_M();\ + __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ + __asm volatile("jalr t1\n");\ + COMPLETE_IRQ_HANDLING_M(irq_num);\ + EXIT_NESTED_IRQ_HANDLING_M();\ + RESTORE_CALLER_CONTEXT();\ + __asm volatile("mret\n");\ +} + +/** + * @brief Declare an external interrupt handler for supervisor mode + * + * @param[in] irq_num - IRQ number index + * @param[in] isr - Application IRQ handler function pointer + */ +#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_s_vector")));\ +EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_s_vector")));\ +void ISR_NAME_S(irq_num)(void) {\ + SAVE_CALLER_CONTEXT(); \ + ENTER_NESTED_IRQ_HANDLING_S();\ + __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ + __asm volatile("jalr t1\n");\ + COMPLETE_IRQ_HANDLING_S(irq_num);\ + EXIT_NESTED_IRQ_HANDLING_S();\ + RESTORE_CALLER_CONTEXT();\ + __asm volatile("sret\n");\ +} + +#else + +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) { \ + isr(); \ +} + +#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_S(irq_num)(void) { \ + isr(); \ +} + +#endif + + +/** + * @brief Declare machine timer interrupt handler + * + * @param[in] isr - MCHTMR IRQ handler function pointer + */ +#define SDK_DECLARE_MCHTMR_ISR(isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ +void mchtmr_isr(void) {\ + isr();\ +} + +/** + * @brief Declare machine software interrupt handler + * + * @param[in] isr - SWI IRQ handler function pointer + */ +#define SDK_DECLARE_SWI_ISR(isr)\ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ +void swi_isr(void) {\ + isr();\ +} + +/* Supervisor mode */ + +/** + * @brief Declare machine timer interrupt handler + * + * @param[in] isr - MCHTMR IRQ handler function pointer + */ +#define SDK_DECLARE_MCHTMR_ISR_S(isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void mchtmr_s_isr(void) __attribute__((section(".isr_vector"))); \ +void mchtmr_s_isr(void) {\ + isr();\ +} + +/** + * @brief Declare machine software interrupt handler + * + * @param[in] isr - SWI IRQ handler function pointer + */ +#define SDK_DECLARE_SWI_ISR_S(isr)\ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void swi_s_isr(void) __attribute__((section(".isr_vector"))); \ +void swi_s_isr(void) {\ + isr();\ +} + +#define CSR_MSTATUS_MPP_S_MODE (0x1) +#define MODE_SWITCH_FROM_M(mstatus, mepc, label, mode) \ +do { \ + if (label) { \ + write_csr(mepc, label); \ + } \ + clear_csr(mstatus, CSR_MSTATUS_MPP_MASK); \ + set_csr(mstatus, CSR_MSTATUS_MPP_SET(mode)); \ +} while(0) + +typedef void (*s_mode_entry)(void); + +/** + * @brief Switch mode to supervisor from machine + * + * @param[in] entry - entry point after mode is switched + */ +static inline void switch_to_s_mode(s_mode_entry entry) +{ + write_csr(CSR_SEPC, entry); + MODE_SWITCH_FROM_M(CSR_MSTATUS, CSR_MEPC, entry, CSR_MSTATUS_MPP_S_MODE); + if (entry) { + __asm("mret"); + } +} +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_INTERRUPT_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_ioc_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ioc_regs.h new file mode 100644 index 00000000..bbbfa47e --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ioc_regs.h @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOC_H +#define HPM_IOC_H + +typedef struct { + struct { + __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ + __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ + } PAD[488]; +} IOC_Type; + + +/* Bitfield definition for register of struct array PAD: FUNC_CTL */ +/* + * LOOP_BACK (RW) + * + * force input on + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) + +/* + * ANALOG (RW) + * + * select analog pin in pad + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) +#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) +#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) +#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) + +/* + * ALT_SELECT (RW) + * + * alt select + * 0: ALT0 + * 1: ALT1 + * … + * 31:ALT31 + */ +#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) + +/* Bitfield definition for register of struct array PAD: PAD_CTL */ +/* + * HYS (RW) + * + * schmitt trigger enable + * 0: disable + * 1: enable + */ +#define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) +#define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) +#define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) +#define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) + +/* + * PRS (RW) + * + * select pull up/down internal resistance strength: + * For pull down, only have 100 Kohm resistance + * For pull up: + * 00: 100 KOhm + * 01: 47 KOhm + * 10: 22 KOhm + * 11: 22 KOhm + */ +#define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) +#define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) +#define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) +#define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) + +/* + * PS (RW) + * + * pull select + * 0: pull down + * 1: pull up + */ +#define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) +#define IOC_PAD_PAD_CTL_PS_SHIFT (18U) +#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) +#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) + +/* + * PE (RW) + * + * pull enable + * 0: pull disable + * 1: pull enable + */ +#define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) +#define IOC_PAD_PAD_CTL_PE_SHIFT (17U) +#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) +#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) + +/* + * KE (RW) + * + * keeper capability enable + * 0: keeper disable + * 1: keeper enable + */ +#define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) +#define IOC_PAD_PAD_CTL_KE_SHIFT (16U) +#define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) +#define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) + +/* + * OD (RW) + * + * open drain + * 0: open drain disable + * 1: open drain enable + */ +#define IOC_PAD_PAD_CTL_OD_MASK (0x100U) +#define IOC_PAD_PAD_CTL_OD_SHIFT (8U) +#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) +#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) + +/* + * SR (RW) + * + * slew rate + * 0: Slow slew rate + * 1: Fast slew rate + */ +#define IOC_PAD_PAD_CTL_SR_MASK (0x40U) +#define IOC_PAD_PAD_CTL_SR_SHIFT (6U) +#define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) +#define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) + +/* + * SPD (RW) + * + * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise + * 00: Slow frequency slew rate(50Mhz) + * 01: Medium frequency slew rate(100 Mhz) + * 10: Fast frequency slew rate(150 Mhz) + * 11: Max frequency slew rate(200Mhz) + */ +#define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) +#define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) +#define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) +#define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) + +/* + * DS (RW) + * + * drive strength + * 1.8V Mode: + * 000: 260 Ohm + * 001: 260 Ohm + * 010: 130 Ohm + * 011: 88 Ohm + * 100: 65 Ohm + * 101: 52 Ohm + * 110: 43 Ohm + * 111: 37 Ohm + * 3.3V Mode: + * 000: 157 Ohm + * 001: 157 Ohm + * 010: 78 Ohm + * 011: 53 Ohm + * 100: 39 Ohm + * 101: 32 Ohm + * 110: 26 Ohm + * 111: 23 Ohm + */ +#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) +#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) +#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) +#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) + + + +/* PAD register group index macro definition */ +#define IOC_PAD_PA00 (0UL) +#define IOC_PAD_PA01 (1UL) +#define IOC_PAD_PA02 (2UL) +#define IOC_PAD_PA03 (3UL) +#define IOC_PAD_PA04 (4UL) +#define IOC_PAD_PA05 (5UL) +#define IOC_PAD_PA06 (6UL) +#define IOC_PAD_PA07 (7UL) +#define IOC_PAD_PA08 (8UL) +#define IOC_PAD_PA09 (9UL) +#define IOC_PAD_PA10 (10UL) +#define IOC_PAD_PA11 (11UL) +#define IOC_PAD_PA12 (12UL) +#define IOC_PAD_PA13 (13UL) +#define IOC_PAD_PA14 (14UL) +#define IOC_PAD_PA15 (15UL) +#define IOC_PAD_PA16 (16UL) +#define IOC_PAD_PA17 (17UL) +#define IOC_PAD_PA18 (18UL) +#define IOC_PAD_PA19 (19UL) +#define IOC_PAD_PA20 (20UL) +#define IOC_PAD_PA21 (21UL) +#define IOC_PAD_PA22 (22UL) +#define IOC_PAD_PA23 (23UL) +#define IOC_PAD_PA24 (24UL) +#define IOC_PAD_PA25 (25UL) +#define IOC_PAD_PA26 (26UL) +#define IOC_PAD_PA27 (27UL) +#define IOC_PAD_PA28 (28UL) +#define IOC_PAD_PA29 (29UL) +#define IOC_PAD_PA30 (30UL) +#define IOC_PAD_PA31 (31UL) +#define IOC_PAD_PB00 (32UL) +#define IOC_PAD_PB01 (33UL) +#define IOC_PAD_PB02 (34UL) +#define IOC_PAD_PB03 (35UL) +#define IOC_PAD_PB04 (36UL) +#define IOC_PAD_PB05 (37UL) +#define IOC_PAD_PB06 (38UL) +#define IOC_PAD_PB07 (39UL) +#define IOC_PAD_PB08 (40UL) +#define IOC_PAD_PB09 (41UL) +#define IOC_PAD_PB10 (42UL) +#define IOC_PAD_PB11 (43UL) +#define IOC_PAD_PB12 (44UL) +#define IOC_PAD_PB13 (45UL) +#define IOC_PAD_PB14 (46UL) +#define IOC_PAD_PB15 (47UL) +#define IOC_PAD_PB16 (48UL) +#define IOC_PAD_PB17 (49UL) +#define IOC_PAD_PB18 (50UL) +#define IOC_PAD_PB19 (51UL) +#define IOC_PAD_PB20 (52UL) +#define IOC_PAD_PB21 (53UL) +#define IOC_PAD_PB22 (54UL) +#define IOC_PAD_PB23 (55UL) +#define IOC_PAD_PB24 (56UL) +#define IOC_PAD_PB25 (57UL) +#define IOC_PAD_PB26 (58UL) +#define IOC_PAD_PB27 (59UL) +#define IOC_PAD_PB28 (60UL) +#define IOC_PAD_PB29 (61UL) +#define IOC_PAD_PB30 (62UL) +#define IOC_PAD_PB31 (63UL) +#define IOC_PAD_PC00 (64UL) +#define IOC_PAD_PC01 (65UL) +#define IOC_PAD_PC02 (66UL) +#define IOC_PAD_PC03 (67UL) +#define IOC_PAD_PC04 (68UL) +#define IOC_PAD_PC05 (69UL) +#define IOC_PAD_PC06 (70UL) +#define IOC_PAD_PC07 (71UL) +#define IOC_PAD_PC08 (72UL) +#define IOC_PAD_PC09 (73UL) +#define IOC_PAD_PC10 (74UL) +#define IOC_PAD_PC11 (75UL) +#define IOC_PAD_PC12 (76UL) +#define IOC_PAD_PC13 (77UL) +#define IOC_PAD_PC14 (78UL) +#define IOC_PAD_PC15 (79UL) +#define IOC_PAD_PC16 (80UL) +#define IOC_PAD_PC17 (81UL) +#define IOC_PAD_PC18 (82UL) +#define IOC_PAD_PC19 (83UL) +#define IOC_PAD_PC20 (84UL) +#define IOC_PAD_PC21 (85UL) +#define IOC_PAD_PC22 (86UL) +#define IOC_PAD_PC23 (87UL) +#define IOC_PAD_PC24 (88UL) +#define IOC_PAD_PC25 (89UL) +#define IOC_PAD_PC26 (90UL) +#define IOC_PAD_PC27 (91UL) +#define IOC_PAD_PX00 (416UL) +#define IOC_PAD_PX01 (417UL) +#define IOC_PAD_PX02 (418UL) +#define IOC_PAD_PX03 (419UL) +#define IOC_PAD_PX04 (420UL) +#define IOC_PAD_PX05 (421UL) +#define IOC_PAD_PX06 (422UL) +#define IOC_PAD_PX07 (423UL) +#define IOC_PAD_PY00 (448UL) +#define IOC_PAD_PY01 (449UL) +#define IOC_PAD_PY02 (450UL) +#define IOC_PAD_PY03 (451UL) +#define IOC_PAD_PY04 (452UL) +#define IOC_PAD_PY05 (453UL) +#define IOC_PAD_PY06 (454UL) +#define IOC_PAD_PY07 (455UL) +#define IOC_PAD_PZ00 (480UL) +#define IOC_PAD_PZ01 (481UL) +#define IOC_PAD_PZ02 (482UL) +#define IOC_PAD_PZ03 (483UL) +#define IOC_PAD_PZ04 (484UL) +#define IOC_PAD_PZ05 (485UL) +#define IOC_PAD_PZ06 (486UL) +#define IOC_PAD_PZ07 (487UL) + + +#endif /* HPM_IOC_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h new file mode 100644 index 00000000..aae3ebd1 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_iomux.h @@ -0,0 +1,958 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOMUX_H +#define HPM_IOMUX_H + +/* IOC_PA00_FUNC_CTL function mux definitions */ +#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA00_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA00_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA00_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA01_FUNC_CTL function mux definitions */ +#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA01_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA01_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA02_FUNC_CTL function mux definitions */ +#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA02_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA02_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA02_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA03_FUNC_CTL function mux definitions */ +#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA03_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA03_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA04_FUNC_CTL function mux definitions */ +#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA04_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA04_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA04_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA04_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA04_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA05_FUNC_CTL function mux definitions */ +#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA05_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA05_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA05_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA05_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA05_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA06_FUNC_CTL function mux definitions */ +#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA06_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA06_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA06_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA06_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA06_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA06_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA06_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA06_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA07_FUNC_CTL function mux definitions */ +#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA07_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA07_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA07_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA07_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA07_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA07_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA07_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA07_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA08_FUNC_CTL function mux definitions */ +#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA08_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA08_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA08_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA08_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA08_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA08_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA08_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PA09_FUNC_CTL function mux definitions */ +#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA09_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA09_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA09_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA09_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA09_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA09_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA09_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PA10_FUNC_CTL function mux definitions */ +#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA10_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA10_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA10_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA10_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA10_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA10_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA10_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA10_FUNC_CTL_PWM3_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA11_FUNC_CTL function mux definitions */ +#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA11_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA11_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA11_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA11_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA11_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA11_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA11_FUNC_CTL_PWM3_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA12_FUNC_CTL function mux definitions */ +#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA12_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA12_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA12_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA12_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA12_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA12_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA12_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA12_FUNC_CTL_TRGM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA13_FUNC_CTL function mux definitions */ +#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA13_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA13_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA13_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA13_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA13_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA13_FUNC_CTL_TRGM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA13_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA14_FUNC_CTL function mux definitions */ +#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA14_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA14_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA14_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA14_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA14_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA14_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA14_FUNC_CTL_TRGM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA14_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA15_FUNC_CTL function mux definitions */ +#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA15_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA15_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA15_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA15_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA15_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA15_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA15_FUNC_CTL_TRGM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA15_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA16_FUNC_CTL function mux definitions */ +#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA16_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA16_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA16_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA16_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA16_FUNC_CTL_TRGM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA16_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA17_FUNC_CTL function mux definitions */ +#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA17_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA17_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA17_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA17_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA17_FUNC_CTL_TRGM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA17_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA18_FUNC_CTL function mux definitions */ +#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA18_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA18_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA18_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA18_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA18_FUNC_CTL_TRGM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA18_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA19_FUNC_CTL function mux definitions */ +#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA19_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA19_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA19_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA19_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA19_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA19_FUNC_CTL_TRGM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA20_FUNC_CTL function mux definitions */ +#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA20_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA20_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA20_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA20_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA20_FUNC_CTL_TRGM1_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA20_FUNC_CTL_PWM3_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA21_FUNC_CTL function mux definitions */ +#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA21_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA21_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA21_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA21_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA21_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA21_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA21_FUNC_CTL_PWM3_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA22_FUNC_CTL function mux definitions */ +#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA22_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA22_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA22_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA22_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA22_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA22_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA22_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA22_FUNC_CTL_PWM3_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA23_FUNC_CTL function mux definitions */ +#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA23_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA23_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA23_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA23_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA23_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA23_FUNC_CTL_PWM3_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA24_FUNC_CTL function mux definitions */ +#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA24_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA24_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA24_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA24_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA24_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA24_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA24_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA24_FUNC_CTL_PWM3_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA25_FUNC_CTL function mux definitions */ +#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA25_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA25_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA25_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA25_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA25_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA25_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA25_FUNC_CTL_PWM3_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA26_FUNC_CTL function mux definitions */ +#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA26_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA26_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA26_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA26_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA26_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA26_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA26_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA26_FUNC_CTL_PWM3_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA27_FUNC_CTL function mux definitions */ +#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA27_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA27_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA27_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA27_FUNC_CTL_PWM3_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA28_FUNC_CTL function mux definitions */ +#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA28_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA28_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA28_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA28_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA28_FUNC_CTL_TRGM1_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA28_FUNC_CTL_TRGM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA29_FUNC_CTL function mux definitions */ +#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA29_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA29_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA29_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA29_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA29_FUNC_CTL_TRGM1_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA29_FUNC_CTL_TRGM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA30_FUNC_CTL function mux definitions */ +#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA30_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA30_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA30_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA30_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA30_FUNC_CTL_TRGM1_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA30_FUNC_CTL_TRGM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PA31_FUNC_CTL function mux definitions */ +#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA31_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA31_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA31_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA31_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA31_FUNC_CTL_TRGM1_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA31_FUNC_CTL_TRGM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB00_FUNC_CTL function mux definitions */ +#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB00_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB00_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB00_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB00_FUNC_CTL_TRGM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB01_FUNC_CTL function mux definitions */ +#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB01_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB01_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB01_FUNC_CTL_TRGM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB02_FUNC_CTL function mux definitions */ +#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB02_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB02_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB02_FUNC_CTL_TRGM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB03_FUNC_CTL function mux definitions */ +#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB03_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB03_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB03_FUNC_CTL_TRGM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB04_FUNC_CTL function mux definitions */ +#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB04_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB04_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB04_FUNC_CTL_TRGM3_P_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB05_FUNC_CTL function mux definitions */ +#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB05_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB05_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB05_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB05_FUNC_CTL_TRGM3_P_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB06_FUNC_CTL function mux definitions */ +#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB06_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB06_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB06_FUNC_CTL_TRGM3_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB07_FUNC_CTL function mux definitions */ +#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB07_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB07_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB07_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB07_FUNC_CTL_TRGM3_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB08_FUNC_CTL function mux definitions */ +#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB08_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB08_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB08_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB09_FUNC_CTL function mux definitions */ +#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB09_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB09_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB09_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB10_FUNC_CTL function mux definitions */ +#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB10_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB10_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB11_FUNC_CTL function mux definitions */ +#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB11_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB11_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PB12_FUNC_CTL function mux definitions */ +#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB12_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB12_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB12_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB12_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB12_FUNC_CTL_TRGM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB13_FUNC_CTL function mux definitions */ +#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB13_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB13_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB13_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB13_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB13_FUNC_CTL_TRGM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB14_FUNC_CTL function mux definitions */ +#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB14_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB14_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB14_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB14_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB14_FUNC_CTL_TRGM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB15_FUNC_CTL function mux definitions */ +#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB15_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB15_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB15_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB15_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB15_FUNC_CTL_TRGM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB16_FUNC_CTL function mux definitions */ +#define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB16_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB16_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB16_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB16_FUNC_CTL_TRGM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB17_FUNC_CTL function mux definitions */ +#define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB17_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB17_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB17_FUNC_CTL_TRGM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB18_FUNC_CTL function mux definitions */ +#define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB18_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB18_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB18_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB18_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB18_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB18_FUNC_CTL_TRGM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB19_FUNC_CTL function mux definitions */ +#define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB19_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB19_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB19_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB19_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB19_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB19_FUNC_CTL_TRGM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB20_FUNC_CTL function mux definitions */ +#define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB20_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB20_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB20_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB20_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB20_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB20_FUNC_CTL_TRGM2_P_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB21_FUNC_CTL function mux definitions */ +#define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB21_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB21_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB21_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB21_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB21_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB21_FUNC_CTL_TRGM2_P_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB22_FUNC_CTL function mux definitions */ +#define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB22_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB22_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB22_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB22_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB22_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB22_FUNC_CTL_TRGM2_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB22_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB22_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB23_FUNC_CTL function mux definitions */ +#define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB23_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB23_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB23_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB23_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB23_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB23_FUNC_CTL_TRGM2_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB23_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB23_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PB24_FUNC_CTL function mux definitions */ +#define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB24_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB24_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB24_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB24_FUNC_CTL_PWM2_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB24_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB25_FUNC_CTL function mux definitions */ +#define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB25_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB25_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB25_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB25_FUNC_CTL_PWM2_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB25_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB26_FUNC_CTL function mux definitions */ +#define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB26_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB26_FUNC_CTL_PWM2_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB26_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB27_FUNC_CTL function mux definitions */ +#define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB27_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB27_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB27_FUNC_CTL_PWM2_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB27_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB28_FUNC_CTL function mux definitions */ +#define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB28_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB28_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB28_FUNC_CTL_TRGM0_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB28_FUNC_CTL_PWM2_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB28_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB29_FUNC_CTL function mux definitions */ +#define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB29_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB29_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB29_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB29_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB29_FUNC_CTL_TRGM0_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB29_FUNC_CTL_PWM2_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB29_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PB30_FUNC_CTL function mux definitions */ +#define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB30_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB30_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB30_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB30_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB30_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB30_FUNC_CTL_TRGM0_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB30_FUNC_CTL_PWM2_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PB31_FUNC_CTL function mux definitions */ +#define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB31_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB31_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB31_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB31_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB31_FUNC_CTL_TRGM0_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB31_FUNC_CTL_PWM2_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC00_FUNC_CTL function mux definitions */ +#define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC00_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC00_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC00_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC00_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC00_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC00_FUNC_CTL_TRGM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC01_FUNC_CTL function mux definitions */ +#define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC01_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC01_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC01_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC01_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC01_FUNC_CTL_TRGM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC01_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC02_FUNC_CTL function mux definitions */ +#define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC02_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC02_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC02_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC02_FUNC_CTL_TRGM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC02_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC03_FUNC_CTL function mux definitions */ +#define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC03_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC03_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC03_FUNC_CTL_TRGM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC04_FUNC_CTL function mux definitions */ +#define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC04_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC04_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC04_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC04_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC04_FUNC_CTL_TRGM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC05_FUNC_CTL function mux definitions */ +#define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC05_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC05_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC05_FUNC_CTL_TRGM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC05_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC06_FUNC_CTL function mux definitions */ +#define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC06_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC06_FUNC_CTL_TRGM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC06_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC07_FUNC_CTL function mux definitions */ +#define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC07_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC07_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PC07_FUNC_CTL_TRGM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC07_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC08_FUNC_CTL function mux definitions */ +#define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC08_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC08_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC08_FUNC_CTL_PWM2_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PC08_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC09_FUNC_CTL function mux definitions */ +#define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC09_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC09_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC09_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC09_FUNC_CTL_PWM2_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) + +/* IOC_PC10_FUNC_CTL function mux definitions */ +#define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC10_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC10_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC10_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PC11_FUNC_CTL function mux definitions */ +#define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC11_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC11_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC11_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PC12_FUNC_CTL function mux definitions */ +#define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC12_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC12_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC12_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PC13_FUNC_CTL function mux definitions */ +#define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC13_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PC13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC13_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC13_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC13_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC13_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC14_FUNC_CTL function mux definitions */ +#define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC14_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC14_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC14_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PC14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC15_FUNC_CTL function mux definitions */ +#define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC15_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC15_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC15_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC16_FUNC_CTL function mux definitions */ +#define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC16_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PC16_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC16_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) + +/* IOC_PC17_FUNC_CTL function mux definitions */ +#define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC17_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PC18_FUNC_CTL function mux definitions */ +#define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC18_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC18_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PC19_FUNC_CTL function mux definitions */ +#define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC19_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC19_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PC20_FUNC_CTL function mux definitions */ +#define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC20_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC20_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC20_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PC20_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC21_FUNC_CTL function mux definitions */ +#define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PC21_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC21_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC21_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PC21_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PC22_FUNC_CTL function mux definitions */ +#define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC22_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC22_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC22_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PC23_FUNC_CTL function mux definitions */ +#define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC23_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PC23_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PC24_FUNC_CTL function mux definitions */ +#define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC24_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC24_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PC25_FUNC_CTL function mux definitions */ +#define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC25_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC25_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PC26_FUNC_CTL function mux definitions */ +#define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC26_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC26_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PC27_FUNC_CTL function mux definitions */ +#define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PC27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PC27_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PC27_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PX00_FUNC_CTL function mux definitions */ +#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX01_FUNC_CTL function mux definitions */ +#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX02_FUNC_CTL function mux definitions */ +#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX02_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX03_FUNC_CTL function mux definitions */ +#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX04_FUNC_CTL function mux definitions */ +#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX05_FUNC_CTL function mux definitions */ +#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX06_FUNC_CTL function mux definitions */ +#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX06_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX07_FUNC_CTL function mux definitions */ +#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX07_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY00_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY00_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY01_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY01_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY02_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY03_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY04_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY04_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY04_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY05_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY05_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY05_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY06_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY07_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ00_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ00_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ01_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ01_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ02_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ02_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ03_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ03_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ04_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ04_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PZ04_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ05_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ05_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PZ05_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) + +/* IOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ06_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ06_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ06_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + +/* IOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PZ07_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PZ07_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PZ07_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) + + +#endif /* HPM_IOMUX_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.c b/common/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.c new file mode 100644 index 00000000..c55600dc --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_l1c_drv.h" +#include + + +#define ASSERT_ADDR_SIZE(addr, size) do { \ + assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ + assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ + } while (0) + +static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) +{ + register uint32_t i; + register uint32_t next_address; + register uint32_t tmp; + register uint32_t csr; + + csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +#define CCTL_VERSION (3U << 18) + + if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { + l1c_cctl_address(address); + next_address = address; + while ((next_address < (address + size)) && (next_address >= address)) { + l1c_cctl_cmd(opcode); + next_address = l1c_cctl_get_address(); + } + } else { + for (i = 0, tmp = 0; tmp < size; i++) { + l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); + tmp += HPM_L1C_CACHELINE_SIZE; + } + } + + write_csr(CSR_MSTATUS, csr); +} + +void l1c_dc_enable(void) +{ + if (!l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); + set_csr(CSR_MCACHE_CTL, +#ifdef L1C_DC_WAROUND_VALUE + HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | +#endif + HPM_MCACHE_CTL_DPREF_EN_MASK + | HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_dc_disable(void) +{ + if (l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_ic_enable(void) +{ + if (!l1c_ic_is_enabled()) { + set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK + | HPM_MCACHE_CTL_CCTL_SUEN_MASK + | HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_ic_disable(void) +{ + if (l1c_ic_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_fence_i(void) +{ + __asm("fence.i"); +} + +void l1c_dc_invalidate_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); +} + +void l1c_dc_writeback_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); +} + +void l1c_dc_flush_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); +} + +void l1c_dc_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); +} + +void l1c_dc_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); +} + +void l1c_dc_writeback(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); +} + +void l1c_dc_flush(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); +} + +void l1c_ic_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); +} + +void l1c_ic_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); +} diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h new file mode 100644 index 00000000..e328193a --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h @@ -0,0 +1,485 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_L1_CACHE_H +#define _HPM_L1_CACHE_H +#include "riscv/riscv_core.h" +#include "hpm_common.h" +#include "hpm_soc.h" + +/** + * + * @brief L1CACHE driver APIs + * @defgroup l1cache_interface L1CACHE driver APIs + * @{ + */ + +/* cache size is 32KB */ +#define HPM_L1C_CACHE_SIZE (uint32_t)(32 * SIZE_1KB) +#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) +#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) +/* cache line size is 64B */ +#define HPM_L1C_CACHELINE_SIZE (64) +/* cache way is 128 */ +#define HPM_L1C_CACHELINES_PER_WAY (128) + +/* mcache_ctl register */ +/* + * Controls if the instruction cache is enabled or not. + * + * 0 I-Cache is disabled + * 1 I-Cache is enabled + */ +#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) +#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) +#define HPM_MCACHE_CTL_IC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) + +/* + * Controls if the data cache is enabled or not. + * + * 0 D-Cache is disabled + * 1 D-Cache is enabled + */ +#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) +#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) +#define HPM_MCACHE_CTL_DC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) + +/* + * Parity/ECC error checking enable control for the instruction cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) +#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_IC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) + +/* + * + * Parity/ECC error checking enable control for the data cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) +#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_DC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. + * It is set to enable CCTL operations to access the ECC codes. This bit + * can be set for injecting ECC errors to test the ECC handler. + * + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) +#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_IC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is + * set to enable CCTL operations to access the ECC codes. This bit can be + * set for injecting + * + * ECC errors to test the ECC handler. + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) +#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_DC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) + +/* + * Enable bit for Superuser-mode and User-mode software to access + * ucctlbeginaddr and ucctlcommand CSRs. + * + * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) +#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) +#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) + +/* + * This bit controls hardware prefetch for instruction fetches to cacheable + * memory regions when I-Cache size is not 0. + * + * 0 Disable hardware prefetch on instruction fetches + * 1 Enable hardware prefetch on instruction fetches + */ +#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) +#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_IPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) + +/* + * This bit controls hardware prefetch for load/store accesses to cacheable + * memory regions when D-Cache size is not 0. + * + * 0 Disable hardware prefetch on load/store memory accesses. + * 1 Enable hardware prefetch on load/store memory accesses. + */ +#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) +#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_DPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) + +/* + * I-Cache miss allocation filling policy Value Meaning + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) +#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) + +/* + * D-Cache miss allocation filling policy + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) +#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) + +/* + * D-Cache Write-Around threshold + * + * 0 Disables streaming. All cacheable write misses allocate a cache line + * according to PMA settings. + * 1 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 4 cache lines. + * 2 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 64 cache lines. + * 3 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 128 cache lines. + */ +#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) +#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) +#define HPM_MCACHE_CTL_DC_WAROUND(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) + +/* CCTL command list */ +#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) +#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) +#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) + +#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) + +#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) + +#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) + +#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) +#define HPM_L1C_CCTL_CMD_FAIL (0UL) + +#ifdef __cplusplus +extern "C" { +#endif +/* get cache control register value */ +__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) +{ + return read_csr(CSR_MCACHE_CTL); +} + +__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; +} + +__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; +} + +/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ +#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) +#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) +#define HPM_MCCTLBEGINADDR_OFFSET(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) +#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) +#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) +#define HPM_MCCTLBEGINADDR_INDEX(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) +#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) +#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) +#define HPM_MCCTLBEGINADDR_WAY(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) + +/* send IX command */ +__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); +} + +/* send command */ +__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) +{ + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) +{ + return read_csr(CSR_MCCTLBEGINADDR); +} + +/* send IX command */ +__attribute__((always_inline)) static inline + void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) +#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) +#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) +#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) +#define HPM_MCCTLDATA_I_TAG_VALID(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) + +#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) +#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) +#define HPM_MCCTLDATA_D_TAG_MESI(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) + +#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) +#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) +#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_TAG(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) + +/* + * @brief Cache control command read address + * + * Send IX read tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] ecc_data ECC value + * @return data read + */ +ATTR_ALWAYS_INLINE static inline + uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + *ecc_data = read_csr(CSR_MECC_CODE); + return read_csr(CSR_MCCTLDATA); +} + +/* + * @brief Cache control command write address + * + * Send IX write tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] data Data to be written + * @param[in] ecc_data ECC of data + */ +ATTR_ALWAYS_INLINE static inline + void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + write_csr(CSR_MCCTLDATA, data); + write_csr(CSR_MECC_CODE, ecc_data); +} + +#define HPM_L1C_CFG_SET_SHIFT (0UL) +#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) +#define HPM_L1C_CFG_WAY_SHIFT (3UL) +#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) +#define HPM_L1C_CFG_SIZE_SHIFT (6UL) +#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) +#define HPM_L1C_CFG_LOCK_SHIFT (9UL) +#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) +#define HPM_L1C_CFG_ECC_SHIFT (10UL) +#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) +#define HPM_L1C_CFG_LMB_SHIFT (12UL) +#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) +#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) +#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) +#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) +#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) +#define HPM_L1C_CFG_SETH_SHIFT (24UL) +#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) + +/** + * @brief Align down based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) + +/** + * @brief Align up based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) + +/** + * @brief Get I-cache configuration + * + * @return I-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) +{ + return read_csr(CSR_MICM_CFG); +} + +/** + * @brief Get D-cache configuration + * + * @return D-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) +{ + return read_csr(CSR_MDCM_CFG); +} + +/* + * @brief D-cache disable + */ +void l1c_dc_disable(void); + +/* + * @brief D-cache enable + */ +void l1c_dc_enable(void); + +/* + * @brief D-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_dc_invalidate(uint32_t address, uint32_t size); + +/* + * @brief D-cache writeback by address + * @param[in] address Start address to be writtenback + * @param[in] size Size of memory to be writtenback + */ +void l1c_dc_writeback(uint32_t address, uint32_t size); + +/* + * @brief D-cache invalidate and writeback by address + * @param[in] address Start address to be invalidated and writtenback + * @param[in] size Size of memory to be invalidted and writtenback + */ +void l1c_dc_flush(uint32_t address, uint32_t size); + +/* + * @brief D-cache fill and lock by address + * @param[in] address Start address to be filled and locked + * @param[in] size Size of memory to be filled and locked + */ +void l1c_dc_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief I-cache disable + */ +void l1c_ic_disable(void); + +/* + * @brief I-cache enable + */ +void l1c_ic_enable(void); + +/* + * @brief I-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_ic_invalidate(uint32_t address, uint32_t size); + +/* + * @brief I-cache fill and lock by address + * @param[in] address Start address to be locked + * @param[in] size Size of memory to be locked + */ +void l1c_ic_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief Invalidate all icache and writeback all dcache + */ +void l1c_fence_i(void); + +/* + * @brief Invalidate all d-cache + */ +void l1c_dc_invalidate_all(void); + +/* + * @brief Writeback all d-cache + */ +void l1c_dc_writeback_all(void); + +/* + * @brief Flush all d-cache + */ +void l1c_dc_flush_all(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _HPM_L1_CACHE_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h new file mode 100644 index 00000000..db03cea0 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MCAN_SOC_H +#define HPM_MCAN_SOC_H + +#include +#include "hpm_mcan_regs.h" + +/** + * @brief TSU External Timebase Sources + */ +#define MCAN_TSU_EXT_TIMEBASE_SRC_MIN (0U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN0 (MCAN_TSU_EXT_TIMEBASE_SRC_MIN) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN1 (1U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN2 (2U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN3 (3U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_PTP (4U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_PTP) + +#ifdef __cpluspus +extern "C" { +#endif + +/** + * @brief Set External Timebase Source for MCAN TSU + * @param [in] ptr MCAN base + * @param [in] src External Timebase source + */ +static inline void mcan_set_tsu_ext_timebase_src(MCAN_Type *ptr, uint8_t src) +{ + ptr->GLB_CTL = (ptr->GLB_CTL & ~MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) | MCAN_GLB_CTL_TSU_TBIN_SEL_SET(src); +} + +/** + * @brief Enable Standby Pin for MCAN + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_standby_pin(MCAN_Type *ptr) +{ + ptr->GLB_CTL |= MCAN_GLB_CTL_M_CAN_STBY_MASK; +} + +/** + * @brief Disable Standby pin for MCAN + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_standby_pin(MCAN_Type *ptr) +{ + ptr->GLB_CTL &= ~MCAN_GLB_CTL_M_CAN_STBY_MASK; +} + +/** + * @brief Get RAM base for MCAN + * @param [in] ptr MCAN base + * @return RAM base for MCAN + */ +static inline uint32_t mcan_get_ram_base(MCAN_Type *ptr) +{ + return (uint32_t) &ptr->MESSAGE_BUFF[0]; +} + +/** + * @brief Get the MCAN RAM offset in the dedicated/shared RAM for + * @param [in] ptr MCAN base + * @return RAM offset for MCAN + */ +static inline uint32_t mcan_get_ram_offset(MCAN_Type *ptr) +{ + return 0U; +} + +/** + * @brief Get MCAN RAM size + * @param [in] ptr MCAN base + * @return RAM size in bytes + */ +static inline uint32_t mcan_get_ram_size(MCAN_Type *ptr) +{ + return sizeof(ptr->MESSAGE_BUFF); +} + +#ifdef __cpluspus +} +#endif + +#endif /* HPM_MCAN_SOC_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_misc.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_misc.h new file mode 100644 index 00000000..9875958d --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_misc.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MISC_H +#define HPM_MISC_H + +#define CORE0_ILM_LOCAL_BASE (0x0U) +#define CORE0_ILM_SIZE_IN_BYTE (0x20000U) +#define CORE0_DLM_LOCAL_BASE (0x80000U) +#define CORE0_DLM_SIZE_IN_BYTE (0x20000U) +#define CORE1_ILM_LOCAL_BASE (0x20000U) +#define CORE1_ILM_SIZE_IN_BYTE (0x20000U) +#define CORE1_DLM_LOCAL_BASE (0xA0000U) +#define CORE1_DLM_SIZE_IN_BYTE (0x20000U) +#define CORE0_ILM_SYSTEM_BASE (0x0U) +#define CORE0_DLM_SYSTEM_BASE (0x80000U) +#define CORE1_ILM_SYSTEM_BASE (0x20000U) +#define CORE1_DLM_SYSTEM_BASE (0xA0000U) + +#define HPM_CORE0 (0U) +#define HPM_CORE1 (1U) + +/* map core local memory(DLM/ILM) to system address */ +static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) +{ + return addr; +} + +/* map system address to core local memory(DLM/ILM) */ +static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) +{ + return addr; +} +#endif /* HPM_MISC_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.c b/common/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.c new file mode 100644 index 00000000..ef0fa1cf --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_otp_drv.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) +#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ +#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) +#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ +#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +void otp_init(void) +{ + +} + +void otp_deinit(void) +{ + +} + +uint32_t otp_read_from_shadow(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP->SHADOW[addr] : HPM_OTPSHW->SHADOW[addr]; + } + + return ret_val; +} + +uint32_t otp_read_from_ip(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = HPM_OTP->FUSE[addr]; + } + return ret_val; +} + +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + do { + uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); + + /* Enable 2.5V LDO for FUSE programming */ + uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); + HPM_PCFG->LDO2P5 = reg_val; + /* Wait until LDO is ready */ + while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { + } + HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; + for (uint32_t i = 0; i < num_of_words; i++) { + HPM_OTP->FUSE[addr++] = *src++; + } + HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; + /* Disable 2.5V LDO after FUSE programming for saving power */ + HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_reload(otp_region_t region) +{ + hpm_stat_t status = status_invalid_argument; + if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { + HPM_OTP->LOAD_REQ = (uint32_t)region; + HPM_OTP->LOAD_COMP = (uint32_t)region; + while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { + + } + status = status_success; + } + + return status; +} + +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); + + HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) + | OTP_REGION_STOP_SET(start + num_of_words); + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + uint32_t lock_mask = 3U << lock_reg_offset; + + OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; + otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) + >> lock_reg_offset); + + if (lock_opt != otp_no_lock) { + status = otp_write_disallowed; + break; + } + + otp_base->SHADOW[addr] = val; + + status = status_success; + } while (false); + + return status; +} diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.h new file mode 100644 index 00000000..09f62879 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_otp_drv.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_OTP_DRV_H +#define HPM_OTP_DRV_H + +/** + * @brief OTP APIs + * @defgroup otp_interface OTP driver APIs + * @{ + */ + +#include "hpm_common.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/** + * @brief OTP region definitions + */ +typedef enum { + otp_region0_mask = 1U, /*!< Address range: [0, 7] */ + otp_region1_mask = 2U, /*!< Address range: [8, 15] */ + otp_region2_mask = 4U, /*!< Address range: [16, 127] */ + otp_region3_mask = 8U, /*!< Address range: user defined */ +} otp_region_t; + +/** + * @brief OTP lock options + */ +typedef enum { + otp_no_lock = 0, + otp_read_only = 1, + otp_permanent_no_lock = 2, + otp_disable_access = 3, + otp_lock_option_max = otp_disable_access, +} otp_lock_option_t; + +enum { + otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), +}; + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ +#ifdef __cpluscplus +extern "C" { +#endif + +/** + * @brief Initialize OTP controller + */ +void otp_init(void); + +/** + * @brief De-initialize OTP controller + */ +void otp_deinit(void); + +/** + * @brief Read the OTP word from shadow register + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_shadow(uint32_t addr); + +/** + * @brief Read the specified OTP word from OTP IP bus + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_ip(uint32_t addr); + +/** + * @brief Program a word to specified OTP field + * @param [in] addr OTP word index + * @param [in] src Pointer to the data to be programmed + * @param [in] num_of_words Number of words to be programmed, only 1 is allowed + * @return API execution status + */ +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + +/** + * @brief Reload a OTP region + * @param [in] region OTP region option + * @return API execution status + */ +hpm_stat_t otp_reload(otp_region_t region); + +/** + * @brief Change the Software lock permission + * @param [in] addr OTP word index + * @param [in] lock_option OTP lcok option + * @return API execution status + */ +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief OTP lock shadow + * @param [in] addr OTP word index + * @param [in] lock_option OTP lock option + * @return API execution status + */ +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief Set the configurable region range + * @param [in] start OTP word start index + * @param [in] num_of_words Number of words in configuration region + * @retval status_out_of_range Invalid range + * @retval status_success Operation is successful + */ +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); + +/** + * @return Write data to OTP shadow register + * @param [in] addr OTP word index + * @param [val] val Data to be written + * @return API execution status + */ +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); + + +#ifdef __cpluscplus +} +#endif +/** + * @} + */ + + + + +#endif diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_pcfg_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h similarity index 100% rename from common/libraries/hpm_sdk/drivers/inc/hpm_pcfg_drv.h rename to common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h new file mode 100644 index 00000000..ebb7b1a4 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h @@ -0,0 +1,925 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PCFG_H +#define HPM_PCFG_H + +typedef struct { + __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ + __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ + __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ + __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ + __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ + __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ + __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ + __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ + __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ + __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ + __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ + __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ + __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ + __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ + __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ + __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ + __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ + __RW uint32_t DEBUG_STOP; /* 0x50: Debug stop config */ + __R uint8_t RESERVED2[12]; /* 0x54 - 0x5F: Reserved */ + __RW uint32_t RC24M; /* 0x60: RC 24M config */ + __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ + __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ + __R uint32_t STATUS; /* 0x6C: RC 24M track status */ +} PCFG_Type; + + +/* Bitfield definition for register: BANDGAP */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) +#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) +#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) +#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) + +/* + * LOWPOWER_MODE (RW) + * + * Banggap work in low power mode, banggap function limited + * 0: banggap works in normal mode + * 1: banggap works in low power mode + */ +#define PCFG_BANDGAP_LOWPOWER_MODE_MASK (0x2000000UL) +#define PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25U) +#define PCFG_BANDGAP_LOWPOWER_MODE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) +#define PCFG_BANDGAP_LOWPOWER_MODE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) >> PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) + +/* + * POWER_SAVE (RW) + * + * Banggap work in power save mode, banggap function normally + * 0: banggap works in high performance mode + * 1: banggap works in power saving mode + */ +#define PCFG_BANDGAP_POWER_SAVE_MASK (0x1000000UL) +#define PCFG_BANDGAP_POWER_SAVE_SHIFT (24U) +#define PCFG_BANDGAP_POWER_SAVE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_POWER_SAVE_SHIFT) & PCFG_BANDGAP_POWER_SAVE_MASK) +#define PCFG_BANDGAP_POWER_SAVE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_POWER_SAVE_MASK) >> PCFG_BANDGAP_POWER_SAVE_SHIFT) + +/* + * VBG_1P0_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) +#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) + +/* + * VBG_P65_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) + +/* + * VBG_P50_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) +#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) +#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) + +/* Bitfield definition for register: LDO1P1 */ +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO1P1_ENABLE_MASK (0x10000UL) +#define PCFG_LDO1P1_ENABLE_SHIFT (16U) +#define PCFG_LDO1P1_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_ENABLE_SHIFT) & PCFG_LDO1P1_ENABLE_MASK) +#define PCFG_LDO1P1_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_ENABLE_MASK) >> PCFG_LDO1P1_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. + * 700: 700mV + * 720: 720mV + * . . . + * 1320:1320mV + */ +#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) +#define PCFG_LDO1P1_VOLT_SHIFT (0U) +#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) +#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) + +/* Bitfield definition for register: LDO2P5 */ +/* + * READY (RO) + * + * Ready flag, will set 1ms after enabled or voltage change + * 0: LDO is not ready for use + * 1: LDO is ready + */ +#define PCFG_LDO2P5_READY_MASK (0x10000000UL) +#define PCFG_LDO2P5_READY_SHIFT (28U) +#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) + +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) +#define PCFG_LDO2P5_ENABLE_SHIFT (16U) +#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) +#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. + * 2125: 2125mV + * 2150: 2150mV + * . . . + * 2900:2900mV + */ +#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) +#define PCFG_LDO2P5_VOLT_SHIFT (0U) +#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) +#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_MODE */ +/* + * READY (RO) + * + * Ready flag + * 0: DCDC is applying new change + * 1: DCDC is ready + */ +#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) +#define PCFG_DCDC_MODE_READY_SHIFT (28U) +#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) + +/* + * MODE (RW) + * + * DCDC work mode + * XX0: trun off + * 001: basic mode + * 011: generic mode + * 101: automatic mode + * 111: expert mode + */ +#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) +#define PCFG_DCDC_MODE_MODE_SHIFT (16U) +#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) +#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) + +/* + * VOLT (RW) + * + * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) +#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) +#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_LPMODE */ +/* + * STBY_VOLT (RW) + * + * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) +#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_PROT */ +/* + * ILIMIT_LP (RW) + * + * over current setting for low power mode + * 0:250mA + * 1:200mA + */ +#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) +#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) +#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) +#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) + +/* + * OVERLOAD_LP (RW) + * + * over current in low power mode + * 0: current is below setting + * 1: overcurrent happened in low power mode + */ +#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) +#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) + +/* + * DISABLE_POWER_LOSS (RW) + * + * disable power loss protection + * 0: power loss protection enabled, DCDC shuts down when power loss + * 1: power loss protection disabled, DCDC try working after power voltage drop + */ +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK (0x800000UL) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT (23U) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) >> PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) + +/* + * POWER_LOSS_FLAG (RO) + * + * power loss + * 0: input power is good + * 1: input power is too low + */ +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) + +/* + * DISABLE_OVERVOLTAGE (RW) + * + * ouput over voltage protection + * 0: protection enabled, DCDC will shut down is output voltage is unexpected high + * 1: protection disabled, DCDC continue to adjust output voltage + */ +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) + +/* + * OVERVOLT_FLAG (RO) + * + * output over voltage flag + * 0: output is normal + * 1: output is unexpected high + */ +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) + +/* + * DISABLE_SHORT (RW) + * + * disable output short circuit protection + * 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected + * 1: short circuit protection disabled + */ +#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) +#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) + +/* + * SHORT_CURRENT (RW) + * + * short circuit current setting + * 0: 2.0A, + * 1: 1.3A + */ +#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) +#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) + +/* + * SHORT_FLAG (RO) + * + * short circuit flag + * 0: current is within limit + * 1: short circuits detected + */ +#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) +#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) +#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) + +/* Bitfield definition for register: DCDC_CURRENT */ +/* + * ESTI_EN (RW) + * + * enable current measure + */ +#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) +#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) + +/* + * VALID (RO) + * + * Current level valid + * 0: data is invalid + * 1: data is valid + */ +#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) +#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) +#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) + +/* + * LEVEL (RO) + * + * DCDC current level, current level is num * 50mA + */ +#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) +#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) +#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) + +/* Bitfield definition for register: DCDC_ADVMODE */ +/* + * EN_RCSCALE (RW) + * + * Enable RC scale + */ +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) + +/* + * DC_C (RW) + * + * Loop C number + */ +#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) +#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) +#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) +#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) + +/* + * DC_R (RW) + * + * Loop R number + */ +#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) +#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) +#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) +#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) + +/* + * EN_FF_DET (RW) + * + * enable feed forward detect + * 0: feed forward detect is disabled + * 1: feed forward detect is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) + +/* + * EN_FF_LOOP (RW) + * + * enable feed forward loop + * 0: feed forward loop is disabled + * 1: feed forward loop is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) + +/* + * EN_AUTOLP (RW) + * + * enable auto enter low power mode + * 0: do not enter low power mode + * 1: enter low power mode if current is detected low + */ +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) + +/* + * EN_DCM_EXIT (RW) + * + * avoid over voltage + * 0: stay in DCM mode when voltage excess + * 1: change to CCM mode when voltage excess + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) + +/* + * EN_SKIP (RW) + * + * enable skip on narrow pulse + * 0: do not skip narrow pulse + * 1: skip narrow pulse + */ +#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) +#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) + +/* + * EN_IDLE (RW) + * + * enable skip when voltage is higher than threshold + * 0: do not skip + * 1: skip if voltage is excess + */ +#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) +#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) + +/* + * EN_DCM (RW) + * + * DCM mode + * 0: CCM mode + * 1: DCM mode + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) + +/* Bitfield definition for register: DCDC_ADVPARAM */ +/* + * MIN_DUT (RW) + * + * minimum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) + +/* + * MAX_DUT (RW) + * + * maximum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) + +/* Bitfield definition for register: DCDC_MISC */ +/* + * EN_HYST (RW) + * + * hysteres enable + */ +#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) +#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) +#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) +#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) + +/* + * HYST_SIGN (RW) + * + * hysteres sign + */ +#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) +#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) +#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) +#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) + +/* + * HYST_THRS (RW) + * + * hysteres threshold + */ +#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) +#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) +#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) +#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) + +/* + * RC_SCALE (RW) + * + * Loop RC scale threshold + */ +#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) +#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) +#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) +#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) + +/* + * DC_FF (RW) + * + * Loop feed forward number + */ +#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) +#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) +#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) +#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) + +/* + * OL_THRE (RW) + * + * overload for threshold for lod power mode + */ +#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) +#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) +#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) +#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) + +/* + * OL_HYST (RW) + * + * current hysteres range + * 0: 12.5mV + * 1: 25mV + */ +#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) +#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) +#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) +#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) + +/* + * DELAY (RW) + * + * enable delay + * 0: delay disabled, + * 1: delay enabled + */ +#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) +#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) +#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) +#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) + +/* + * CLK_SEL (RW) + * + * clock selection + * 0: select DCDC internal oscillator + * 1: select RC24M oscillator + */ +#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) +#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) +#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) +#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) + +/* + * EN_STEP (RW) + * + * enable stepping in voltage change + * 0: stepping disabled, + * 1: steping enabled + */ +#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) +#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) +#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) +#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) + +/* Bitfield definition for register: DCDC_DEBUG */ +/* + * UPDATE_TIME (RW) + * + * DCDC voltage change time in 24M clock cycles, default value is 1mS + */ +#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_START_TIME */ +/* + * START_TIME (RW) + * + * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + */ +#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) +#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) +#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_RESUME_TIME */ +/* + * RESUME_TIME (RW) + * + * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + */ +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) + +/* Bitfield definition for register: POWER_TRAP */ +/* + * TRIGGERED (RW) + * + * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. + * 0: low power trap is not triggered + * 1: low power trap triggered + */ +#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) +#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) +#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) +#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) + +/* + * RETENTION (RW) + * + * DCDC enter standby mode, which will reduce voltage for memory content retention + * 0: Shutdown DCDC + * 1: reduce DCDC voltage + */ +#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) +#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) +#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) +#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) + +/* + * TRAP (RW) + * + * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered + * 0: trap not enabled, pmic side low power function disabled + * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + */ +#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) +#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) +#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) +#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) + +/* Bitfield definition for register: WAKE_CAUSE */ +/* + * CAUSE (RW) + * + * wake up cause, each bit represents one wake up source, write 1 to clear the register bit + * 0: wake up source is not active during last wakeup + * 1: wake up source is active furing last wakeup + * bit 0: pmic_enable + * bit 1: debug wakeup + * bit 4: fuse interrupt + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit11: Security monitor interrupt + * bit12: Security in PMIC event + * bit16: Security violation in BATT + * bit17: GPIO in BATT interrupt + * bit18: BATT Button interrupt + * bit19: RTC alarm interrupt + */ +#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) +#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) +#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: WAKE_MASK */ +/* + * MASK (RW) + * + * mask for wake up sources, each bit represents one wakeup source + * 0: allow source to wake up system + * 1: disallow source to wakeup system + * bit 0: pmic_enable + * bit 1: debug wakeup + * bit 4: fuse interrupt + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit11: Security monitor interrupt + * bit12: Security in PMIC event + * bit16: Security violation in BATT + * bit17: GPIO in BATT interrupt + * bit18: BATT Button interrupt + * bit19: RTC alarm interrupt + */ +#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_MASK_MASK_SHIFT (0U) +#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) +#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) + +/* Bitfield definition for register: SCG_CTRL */ +/* + * SCG (RW) + * + * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral + * 00,01: reserved + * 10: clock is always off + * 11: clock is always on + * bit0-1: fuse + * bit6-7:gpio + * bit8-9:ioc + * bit10-11: timer + * bit12-13:wdog + * bit14-15:uart + * bit16-17:debug + */ +#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) +#define PCFG_SCG_CTRL_SCG_SHIFT (0U) +#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) +#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) + +/* Bitfield definition for register: DEBUG_STOP */ +/* + * CPU1 (RW) + * + * Stop peripheral when CPU1 enter debug mode + * 0: peripheral keep running when CPU1 in debug mode + * 1: peripheral enter debug mode when CPU1 enter debug + */ +#define PCFG_DEBUG_STOP_CPU1_MASK (0x2U) +#define PCFG_DEBUG_STOP_CPU1_SHIFT (1U) +#define PCFG_DEBUG_STOP_CPU1_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU1_SHIFT) & PCFG_DEBUG_STOP_CPU1_MASK) +#define PCFG_DEBUG_STOP_CPU1_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU1_MASK) >> PCFG_DEBUG_STOP_CPU1_SHIFT) + +/* + * CPU0 (RW) + * + * Stop peripheral when CPU0 enter debug mode + * 0: peripheral keep running when CPU0 in debug mode + * 1: peripheral enter debug mode when CPU0 enter debug + */ +#define PCFG_DEBUG_STOP_CPU0_MASK (0x1U) +#define PCFG_DEBUG_STOP_CPU0_SHIFT (0U) +#define PCFG_DEBUG_STOP_CPU0_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU0_SHIFT) & PCFG_DEBUG_STOP_CPU0_MASK) +#define PCFG_DEBUG_STOP_CPU0_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU0_MASK) >> PCFG_DEBUG_STOP_CPU0_SHIFT) + +/* Bitfield definition for register: RC24M */ +/* + * RC_TRIMMED (RW) + * + * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: RC is not trimmed + * 1: RC is trimmed + */ +#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) +#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) +#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) +#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) + +/* + * TRIM_C (RW) + * + * Coarse trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_C_MASK (0x700U) +#define PCFG_RC24M_TRIM_C_SHIFT (8U) +#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) +#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) + +/* + * TRIM_F (RW) + * + * Fine trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_F_MASK (0x1FU) +#define PCFG_RC24M_TRIM_F_SHIFT (0U) +#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) +#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) + +/* Bitfield definition for register: RC24M_TRACK */ +/* + * SEL24M (RW) + * + * Select track reference + * 0: select 32K as reference + * 1: select 24M XTAL as reference + */ +#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) +#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) +#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) +#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) + +/* + * RETURN (RW) + * + * Retrun default value when XTAL loss + * 0: remain last tracking value + * 1: switch to default value + */ +#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) +#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) +#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) +#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) + +/* + * TRACK (RW) + * + * track mode + * 0: RC24M free running + * 1: track RC24M to external XTAL + */ +#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) +#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) +#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) +#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) + +/* Bitfield definition for register: TRACK_TARGET */ +/* + * PRE_DIV (RW) + * + * Divider for reference source + */ +#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) +#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) +#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) +#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) + +/* + * TARGET (RW) + * + * Target frequency multiplier of divided source + */ +#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) +#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) +#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) +#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * SEL32K (RO) + * + * track is using XTAL32K + * 0: track is not using XTAL32K + * 1: track is using XTAL32K + */ +#define PCFG_STATUS_SEL32K_MASK (0x100000UL) +#define PCFG_STATUS_SEL32K_SHIFT (20U) +#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) + +/* + * SEL24M (RO) + * + * track is using XTAL24M + * 0: track is not using XTAL24M + * 1: track is using XTAL24M + */ +#define PCFG_STATUS_SEL24M_MASK (0x10000UL) +#define PCFG_STATUS_SEL24M_SHIFT (16U) +#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) + +/* + * EN_TRIM (RO) + * + * default value takes effect + * 0: default value is invalid + * 1: default value is valid + */ +#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) +#define PCFG_STATUS_EN_TRIM_SHIFT (15U) +#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) + +/* + * TRIM_C (RO) + * + * default coarse trim value + */ +#define PCFG_STATUS_TRIM_C_MASK (0x700U) +#define PCFG_STATUS_TRIM_C_SHIFT (8U) +#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) + +/* + * TRIM_F (RO) + * + * default fine trim value + */ +#define PCFG_STATUS_TRIM_F_MASK (0x1FU) +#define PCFG_STATUS_TRIM_F_SHIFT (0U) +#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) + + + + +#endif /* HPM_PCFG_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_pgpr_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_pgpr_regs.h similarity index 99% rename from common/libraries/hpm_sdk/soc/ip/hpm_pgpr_regs.h rename to common/libraries/hpm_sdk/soc/HPM6280/hpm_pgpr_regs.h index d3c55421..36c19e7d 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_pgpr_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_pgpr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_plic_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_plic_drv.h new file mode 100644 index 00000000..dc0b95e0 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_plic_drv.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLIC_DRV_H +#define HPM_PLIC_DRV_H + +/** + * @brief PLIC driver APIs + * @defgroup plic_interface PLIC driver APIs + * @{ + */ + +#define HPM_PLIC_TARGET_M_MODE 0 +#define HPM_PLIC_TARGET_S_MODE 1 + +/* Feature Register */ +#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) +#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) +#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) + +/* Priority Register - 32 bits per irq */ +#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) +#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 + +/* Pending Register - 1 bit per source */ +#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) +#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 + +/* Enable Register - 0x80 per target */ +#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) +#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 + +/* Priority Threshold Register - 0x1000 per target */ +#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) +#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 + +/* Claim Register - 0x1000 per target */ +#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) +#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#if !defined(__ASSEMBLER__) + +/** + * @brief Set plic feature + * + * @param[in] base PLIC base address + * @param[in] feature Specific feature to be set + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) +{ + *(volatile uint32_t *)(base + HPM_PLIC_FEATURE_OFFSET) = feature; +} + +/** + * @brief Set plic threshold + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, + uint32_t target, + uint32_t threshold) +{ + volatile uint32_t *threshold_ptr = (volatile uint32_t *)(base + + HPM_PLIC_THRESHOLD_OFFSET + + (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); + *threshold_ptr = threshold; +} + +/** + * @brief Set interrupt priority + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * @param[in] priority Priority to be assigned + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, + uint32_t irq, + uint32_t priority) +{ + volatile uint32_t *priority_ptr = (volatile uint32_t *)(base + + HPM_PLIC_PRIORITY_OFFSET + ((irq-1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; +} + +/** + * @brief Set interrupt pending bit + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); + *current_ptr = (1 << (irq & 0x1F)); +} + +/** + * @brief Enable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be enabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current | (1 << (irq & 0x1F)); + *current_ptr = current; +} + +/** + * @brief Disable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be disabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *)(base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current & ~((1 << (irq & 0x1F))); + *current_ptr = current; +} + +/** + * @brief Claim interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to claim interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *)(base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + return *claim_addr; +} + +/** + * @brief Complete interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *)(base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = irq; +} +#endif /* __ASSEMBLER__ */ +/** + * @} + */ +#endif /* HPM_PLIC_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h new file mode 100644 index 00000000..11307e28 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_pmic_iomux.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PMIC_IOMUX_H +#define HPM_PMIC_IOMUX_H + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_WDOG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_UART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_UART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_PMIC_IOMUX_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_ppor_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h similarity index 100% rename from common/libraries/hpm_sdk/drivers/inc/hpm_ppor_drv.h rename to common/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_ppor_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_regs.h similarity index 99% rename from common/libraries/hpm_sdk/soc/ip/hpm_ppor_regs.h rename to common/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_regs.h index 458b5151..17d55b5a 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_ppor_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_romapi.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_romapi.h new file mode 100644 index 00000000..5296bfd1 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_romapi.h @@ -0,0 +1,1000 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_H +#define HPM_ROMAPI_H + +/** + * @brief ROM APIs + * @defgroup romapi_interface ROM APIs + * @{ + */ + +#include "hpm_common.h" +#include "hpm_otp_drv.h" +#include "hpm_romapi_xpi_def.h" +#include "hpm_romapi_xpi_soc_def.h" +#include "hpm_romapi_xpi_nor_def.h" +#include "hpm_romapi_xpi_ram_def.h" +#include "hpm_sdp_drv.h" + +/* XPI0 base address */ +#define HPM_XPI0_BASE (0xF3040000UL) /**< XPI0 Base address */ +/* XPI0 base pointer */ +#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ + + +/*********************************************************************************************************************** + * + * + * Definitions + * + * + **********************************************************************************************************************/ +/** + * @brief Enter Bootloader API argument + */ +typedef union { + uint32_t U; + struct { + uint32_t index: 8; /**< Image index */ + uint32_t peripheral: 8; /**< Boot peripheral */ + uint32_t src: 8; /**< Boot source */ + uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ + }; +} api_boot_arg_t; + +/*EXiP Region Parameter */ +typedef struct { + uint32_t start; /**< Start address, must be 4KB aligned */ + uint32_t len; /**< Must be 4KB aligned */ + uint8_t key[16]; /**< AES Key */ + uint8_t ctr[8]; /**< Initial Vector/Counter */ +} exip_region_param_t; + +#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ +#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ +#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ +#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ +#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ +#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ +#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ +#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ + +/** + * @brief OTP driver interface + */ +typedef struct { + /**< OTP driver interface version */ + uint32_t version; + /**< OTP driver interface: init */ + void (*init)(void); + /**< OTP driver interface: deinit */ + void (*deinit)(void); + /**< OTP driver interface: read from shadow */ + uint32_t (*read_from_shadow)(uint32_t addr); + /**< OTP driver interface: read from ip */ + uint32_t (*read_from_ip)(uint32_t addr); + /**< OTP driver interface: program */ + hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + /**< OTP driver interface: reload */ + hpm_stat_t (*reload)(otp_region_t region); + /**< OTP driver interface: lock */ + hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: lock_shadow */ + hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: set_configurable_region */ + hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); + /**< OTP driver interface: write_shadow_register */ + hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); +} otp_driver_interface_t; + +/** + * @brief XPI driver interface + */ +typedef struct { + /**< XPI driver interface: version */ + uint32_t version; + /**< XPI driver interface: get default configuration */ + hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); + /**< XPI driver interface: get default device configuration */ + hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); + /**< XPI driver interface: initialize the XPI using xpi_config */ + hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); + /**< XPI driver interface: configure the AHB buffer */ + hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); + /**< XPI driver interface: configure the device */ + hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); + /**< XPI driver interface: update instruction talbe */ + hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); + /**< XPI driver interface: transfer command/data using block interface */ + hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); + /**< Software reset the XPI controller */ + void (*software_reset)(XPI_Type *base); + /**< XPI driver interface: Check whether IP is idle */ + bool (*is_idle)(XPI_Type *base); + /**< XPI driver interface: update delay line setting */ + void (*update_dllcr)(XPI_Type *base, + uint32_t serial_root_clk_freq, + uint32_t data_valid_time, + xpi_channel_t channel, + uint32_t dly_target); + /**< XPI driver interface: Get absolute address for APB transfer */ + hpm_stat_t + (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); +} xpi_driver_interface_t; + +/** + * @brief XPI NOR driver interface + */ +typedef struct { + /**< XPI NOR driver interface: API version */ + uint32_t version; + /**< XPI NOR driver interface: Get FLASH configuration */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + /**< XPI NOR driver interface: initialize FLASH */ + hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Enable write access to FLASH */ + hpm_stat_t + (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Get FLASH status register */ + hpm_stat_t (*get_status)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr, + uint16_t *out_status); + /**< XPI NOR driver interface: Wait when FLASH is still busy */ + hpm_stat_t + (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: erase a specified FLASH region */ + hpm_stat_t (*erase)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: Erase the whole FLASH */ + hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Erase specified FLASH sector */ + hpm_stat_t + (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Erase specified FLASH block */ + hpm_stat_t + (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Program data to specified FLASH address */ + hpm_stat_t (*program)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: read data from specified FLASH address */ + hpm_stat_t (*read)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ + hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ + hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ + hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ + hpm_stat_t + (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + + uint32_t reserved0[3]; + + /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ + hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + + /**< XPI NOR driver interface: Get FLASH properties */ + hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); + +} xpi_nor_driver_interface_t; + +/** + * @brief XPI RAM driver interface + */ +typedef struct { + /**< XPI RAM driver interface: API version */ + uint32_t version; + + /**< Get XPI RAM configuration based on cfg_option */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option); + + /**< XPI RAM driver interface: Initialize XPI RAM */ + hpm_stat_t (*init)(XPI_Type *base, xpi_ram_config_t *ram_cfg); +} xpi_ram_driver_interface_t; + +/** + * @brief SDP API interface + */ +typedef struct { + /**< SDP API interface: API version */ + uint32_t version; + /**< SDP API interface: Initialize IP */ + hpm_stat_t (*sdp_ip_init)(void); + /**< SDP API interface: Deinitialize IP */ + hpm_stat_t (*sdp_ip_deinit)(void); + /**< SDP API interface: Set AES key */ + hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); + /**< SDP API interface: AES ECB crypto operation */ + hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); + /**< SDP API interface: AES CBC crypto operation */ + hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *input, + uint8_t *output); + /**< SDP API interface: AES CTR crypto operation */ + hpm_stat_t + (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); + /**< SDP API interface: AES CCM encryption */ + hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); + /**< SDP API interface: AES CCM Decrypt and verify */ + hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); + /**< SDP API interface: memcpy */ + hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); + /**< SDP API interface: memset */ + hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); + /**< SDP API interface: HASH initialization */ + hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); + /**< SDP API interface: HASH update */ + hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); + /**< SDP API interface: HASH finish */ + hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); + /**< SDP API interface: Set SM4 Key */ + hpm_stat_t (*sm4_set_key)(sdp_sm4_ctx_t *sm4_ctx, const uint8_t *key, sdp_sm4_key_bits_t keybits, uint32_t key_idx); + /**< SDP API interface: SM4 Crypto ECB mode */ + hpm_stat_t (*sm4_crypt_ecb)(sdp_sm4_ctx_t *sm4_ctx, sdp_sm4_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); + /**< SDP API Interface: SM4 Crypto CBC mode*/ + hpm_stat_t (*sm4_crypt_cbc)(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *input, + uint8_t *output); + /**< SDP API Interface: SM4 CTR mode */ + hpm_stat_t + (*sm4_crypt_ctr)(sdp_sm4_ctx_t *sm4_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); + /**< SDP API Interface: SM4 CCM Encryption */ + hpm_stat_t (*sm4_ccm_gen_enc)(sdp_sm4_ctx_t *sm4_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); + /**< SDP API Interface: SM4 CCM Decrypt and Verify */ + hpm_stat_t (*sm4_ccm_dec_verify)(sdp_sm4_ctx_t *sm4_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); +} sdp_driver_interface_t; + +/** + * @brief Bootloader API table + */ +typedef struct { + /**< Bootloader API table: version */ + const uint32_t version; + /**< Bootloader API table: copyright string address */ + const char *copyright; + /**< Bootloader API table: run_bootloader API */ + const hpm_stat_t (*run_bootloader)(void *arg); + /**< Bootloader API table: otp driver interface address */ + const otp_driver_interface_t *otp_driver_if; + /**< Bootloader API table: xpi driver interface address */ + const xpi_driver_interface_t *xpi_driver_if; + /**< Bootloader API table: xpi nor driver interface address */ + const xpi_nor_driver_interface_t *xpi_nor_driver_if; + /**< Bootloader API table: xpi ram driver interface address */ + const xpi_ram_driver_interface_t *xpi_ram_driver_if; + /**< Bootloader API table: sdp driver interface address */ + const sdp_driver_interface_t *sdp_driver_if; +} bootloader_api_table_t; + +/**< Bootloader API table Root */ +#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) + + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** + * + * + * Enter bootloader Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Eneter specified Boot mode + * @param [in] ctx Enter bootloader context + * @retval status_invalid Invalid parameters were deteced + */ +static inline hpm_stat_t rom_enter_bootloader(void *ctx) +{ + return ROM_API_TABLE_ROOT->run_bootloader(ctx); +} + +/*********************************************************************************************************************** + * + * + * XPI NOR Driver Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Setup API Runtime environment on demand + */ +static inline void rom_xpi_nor_api_setup(void) +{ + static const uint32_t s_setup_code[] = { + 0x300027f3, 0xf6b36719, 0xe68100e7, 0x90738fd9, 0x80823007, + }; + if (ROM_API_TABLE_ROOT->version == 0x56010000UL) { + typedef void (*api_setup_entry_t)(void); + api_setup_entry_t entry = (api_setup_entry_t) &s_setup_code[0]; + entry(); + } +} + +/** + * @brief Get XPI NOR configuration via cfg_option + * @param [in] base XPI base address + * @param [out] nor_cfg XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_get_config(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option) +{ + rom_xpi_nor_api_setup(); + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); +} + +/** + * @brief Initialize XPI NOR based on nor_config + * @param [in] base XPI base address + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); +} + +/** + * @brief Erase specified FLASH region + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI nOR configuration + * @param[in] start Erase address start address + * @param[in] length Region size to be erased + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); +} + +/** + * @brief Erase specified FLASH sector in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_erase_sector(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH sector in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH blcok in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_erase_block(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH blcok in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase the whole FLASH in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_erase_chip(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); +} + +/** + * @brief Erase the whole FLASH in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); +} + +/** + * @brief Program data to specified FLASH address in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); +} + +/** + * @brief Page-Program data to specified FLASH address in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if + ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); +} + +/** + * @brief Read data from specified FLASH address + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] dst Memory start address to store the data read out from FLASH + * @param [in] start FLASH address for data read + * @param [in] length length of data to be read out + * @return API execution address + */ +static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); +} + +/** + * @brief Automatically configure XPI NOR based on cfg_option + * @param [in] base XPI base address + * @param [out] config XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_auto_config(XPI_Type *base, xpi_nor_config_t *config, xpi_nor_config_option_t *cfg_option) +{ + rom_xpi_nor_api_setup(); + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); +} + +/** + * @brief Get XPI NOR properties + * @param [in] base XPI base address + * @param [in] nor_cfg XPI NOR configuration structure + * @param [in] property_id + * @param [out] value property value retrieved by this API + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_nor_get_property(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); +} + +/** + * @brief Return the status register value on XPI NOR FLASH + * + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] addr FLASH address offset + * @param [out] out_status FLASH status register value + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, uint32_t addr, + uint16_t *out_status) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); +} + +/** + * @brief Configure the XPI Address Remapping Logic + * @param [in] base XPI base address + * @param [in] start Start Address (memory mapped address) + * @param [in] len Size for the remapping region + * @param [in] offset Relative address based on parameter "start" + * @retval true is all parameters are valid + * @retval false if any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) +{ + if ((base != HPM_XPI0) || ((start & 0xFFF) != 0) || ((len & 0xFFF) != 0) + || ((offset & 0xFFF) != 0)) { + return false; + } + static const uint8_t k_mc_xpi_remap_config[] = { + 0x2e, 0x96, 0x23, 0x22, 0xc5, 0x42, 0x23, 0x24, + 0xd5, 0x42, 0x93, 0xe5, 0x15, 0x00, 0x23, 0x20, + 0xb5, 0x42, 0x05, 0x45, 0x82, 0x80, + }; + typedef bool (*remap_config_cb_t)(XPI_Type *, uint32_t, uint32_t, uint32_t); + remap_config_cb_t cb = (remap_config_cb_t) &k_mc_xpi_remap_config; + bool result = cb(base, start, len, offset); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return result; +} + +/** + * @brief Disable XPI Remapping logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_remap_disable(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_disable[] = { + 0x83, 0x27, 0x05, 0x42, 0xf9, 0x9b, 0x23, 0x20, + 0xf5, 0x42, 0x82, 0x80, + }; + typedef void (*remap_disable_cb_t)(XPI_Type *); + remap_disable_cb_t cb = (remap_disable_cb_t) &k_mc_xpi_remap_disable; + cb(base); + fencei(); +} + +/** + * @brief Check whether XPI Remapping is enabled + * @param [in] base XPI base address + * + * @retval true Remapping logic is enabled + * @retval false Remapping logic is disabled + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_is_remap_enabled(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_enabled[] = { + 0x03, 0x25, 0x05, 0x42, 0x05, 0x89, 0x82, 0x80, + }; + typedef void (*remap_chk_cb_t)(XPI_Type *); + remap_chk_cb_t chk_cb = (remap_chk_cb_t) &k_mc_xpi_remap_enabled; + return chk_cb(base); +} + +/** + * @brief Configure Specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + * @param [in] param ExiP Region Parameter + * @retval true All parameters are valid + * @retval false Any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) +{ + if (base != HPM_XPI0) { + return false; + } + static const uint8_t k_mc_exip_region_config[] = { + 0x18, 0x4a, 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, + 0xaa, 0x97, 0x23, 0xa4, 0xe7, 0xd0, 0x4c, 0x4a, + 0x14, 0x42, 0x58, 0x42, 0x23, 0xa6, 0xb7, 0xd0, + 0x4c, 0x46, 0x36, 0x97, 0x13, 0x77, 0x07, 0xc0, + 0x23, 0xa2, 0xb7, 0xd0, 0x0c, 0x46, 0x13, 0x67, + 0x37, 0x00, 0x05, 0x45, 0x23, 0xa0, 0xb7, 0xd0, + 0x0c, 0x4e, 0x23, 0xaa, 0xb7, 0xd0, 0x50, 0x4e, + 0x23, 0xa8, 0xc7, 0xd0, 0x23, 0xac, 0xd7, 0xd0, + 0x23, 0xae, 0xe7, 0xd0, 0x82, 0x80, + }; + typedef void (*exip_region_config_cb_t)(XPI_Type *, uint32_t, exip_region_param_t *); + exip_region_config_cb_t cb = (exip_region_config_cb_t) &k_mc_exip_region_config; + cb(base, index, param); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return true; +} + +/** + * @brief Disable EXiP Feature on specified EXiP Region + * @@param [in] base XPI base address + * @param [in] index EXiP Region index + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) +{ + static const uint8_t k_mc_exip_region_disable[] = { + 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, 0xaa, 0x97, + 0x03, 0xa7, 0xc7, 0xd1, 0x75, 0x9b, 0x23, 0xae, + 0xe7, 0xd0, 0x82, 0x80 + }; + typedef void (*exip_region_disable_cb_t)(XPI_Type *, uint32_t); + exip_region_disable_cb_t cb = (exip_region_disable_cb_t) &k_mc_exip_region_disable; + cb(base, index); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} + +/** + * @brief Enable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_enable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_enable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x37, 0x07, 0x00, 0x80, 0xd9, 0x8f, 0x23, 0x20, + 0xf5, 0xc0, 0x82, 0x80 + }; + typedef void (*exip_enable_cb_t)(XPI_Type *); + exip_enable_cb_t cb = (exip_enable_cb_t) &k_mc_exip_enable; + cb(base); +} + +/** + * @brief Disable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_disable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_disable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x86, 0x07, 0x85, 0x83, 0x23, 0x20, 0xf5, 0xc0, + 0x82, 0x80 + }; + typedef void (*exip_disable_cb_t)(XPI_Type *); + exip_disable_cb_t cb = (exip_disable_cb_t) &k_mc_exip_disable; + cb(base); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} + +/*********************************************************************************************************************** + * + * + * XPI RAM Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Get XPI RAM configuration based on cfg_option + * @param [in] base XPI base address + * @param [out] ram_cfg XPI RAM configuration structure + * @param [in] cfg_option XPI RAM configuration option + * @return API execution status + */ +static inline hpm_stat_t +rom_xpi_ram_get_config(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_ram_driver_if->get_config(base, ram_cfg, cfg_option); +} + +/** + * @brief Initialize XPI RAM + * @param [in] base XPI base address + * @param [in] ram_cfg XPI ram configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_ram_init(XPI_Type *base, xpi_ram_config_t *ram_cfg) +{ + return ROM_API_TABLE_ROOT->xpi_ram_driver_if->init(base, ram_cfg); +} + +/*********************************************************************************************************************** + * + * + * SDP Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Initialize SDP IP + */ +static inline void rom_sdp_init(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); +} + +/** + * @brief De-initialize SDP IP + */ +static inline void rom_sdp_deinit(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); +} + +/** + * @brief Set AES key to SDP + * @param [in] aes_ctx AES context + * @param [in] key AES key buffer + * @param [in] key_bits AES key-bit option + * @param[in] key_idx AES key index + * @return API execution status + */ +static inline hpm_stat_t +rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t key_bits, uint32_t key_idx) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); +} + +/** + * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] len Data length for AES encryption/decryption + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t +rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); +} + +/** + * @brief SDP AES CBC crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] length Data length for AES encryption/decryption + * @param [in] iv Initial vector/nonce + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); +} + +/** + * @brief Set SM4 key to SDP + * @param [in] sm4_ctx SM4 context + * @param [in] key SM4 key buffer + * @param [in] key_bits SM4 key-bit option + * @param[in] key_idx SM4 key index + * @return API execution status + */ +static inline hpm_stat_t +rom_sdp_sm4_set_key(sdp_sm4_ctx_t *sm4_ctx, const uint8_t *key, sdp_sm4_key_bits_t key_bits, uint32_t key_idx) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_set_key(sm4_ctx, key, key_bits, key_idx); +} + +/** + * @brief SDP SM4 ECB crypto operation(Encrypt or Decrypt) + * @param [in] sm4_ctx SM4 context + * @param [in] op SM4 operation: encrypt or decrypt + * @param [in] len Data length for SM4 encryption/decryption + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t +rom_sdp_sm4_crypt_ecb(sdp_sm4_ctx_t *sm4_ctx, sdp_sm4_op_t op, uint32_t len, const uint8_t *in, uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_ecb(sm4_ctx, op, len, in, out); +} + +/** + * @brief SDP SM4 CBC crypto operation(Encrypt or Decrypt) + * @param [in] sm4_ctx SM4 context + * @param [in] op SM4 operation: encrypt or decrypt + * @param [in] length Data length for SM4 encryption/decryption + * @param [in] iv Initial vector/nonce + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_crypt_cbc(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_cbc(sm4_ctx, op, length, iv, in, out); +} + +/** + * @brief HASH initialization + * @param [in] hash_ctx HASH context + * @param [in] alg HASH algorithm + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); +} + +/** + * @brief HASH Update + * @param [in] hash_ctx HASH context + * @param [in] data Data for HASH operation + * @param [in] length of the data for HASH operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); +} + +/** + * @brief HASH finialize + * @param [in] hash_ctx HASH context + * @param [out] digest the output digest + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); +} + +/** + * @brief SDP memcpy operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memcpy + * @param [in] src Source address for memcpy + * @param [in] length Size of data for memcpy operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); +} + +/** + * @brief SDP memset operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memset + * @param [in] pattern pattern for memset + * @param [in] length Size of data for memset operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + + +#endif /* HPM_ROMAPI_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_romapi_xpi_soc_def.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_romapi_xpi_soc_def.h new file mode 100644 index 00000000..5b320c4d --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_romapi_xpi_soc_def.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_XPI_SOC_DEF_H +#define HPM_ROMAPI_XPI_SOC_DEF_H + +#include "hpm_common.h" +#include "hpm_romapi_xpi_def.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) +#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) +#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) +#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) +#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) +#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) +#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) +#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) +#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) + +typedef struct { + struct { + uint8_t priority; /* Offset: 0x00 */ + uint8_t master_idx; /* Offset: 0x01 */ + uint8_t buf_size_in_dword; /* Offset: 0x02 */ + bool enable_prefetch; /* Offset: 0x03 */ + } entry[8]; +} xpi_ahb_buffer_cfg_t; + +typedef struct { + uint8_t data_pads; + xpi_channel_t channel; + xpi_io_group_t io_group; + uint8_t drive_strength; + bool enable_dqs; + bool enable_diff_clk; +} xpi_io_config_t; + +typedef enum { + xpi_freq_type_typical, + xpi_freq_type_mhz, +} clk_freq_type_t; + +typedef enum { + xpi_clk_src_auto, + xpi_clk_src_osc, + xpi_clk_src_pll0clk0, + xpi_clk_src_pll1clk0, + xpi_clk_src_pll1clk1, + xpi_clk_src_pll2clk0, + xpi_clk_src_pll2clk1, + xpi_clk_src_pll3clk0, + xpi_clk_src_pll4clk0, +} xpi_clk_src_t; + + +typedef union { + struct { + uint8_t freq; + bool enable_ddr; + xpi_clk_src_t clk_src; + clk_freq_type_t freq_type; + }; + uint32_t freq_opt; +} xpi_clk_config_t; + +typedef enum { + xpi_clock_bus, + xpi_clock_serial_root, + xpi_clock_serial, +} xpi_clock_t; + +#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml new file mode 100644 index 00000000..f054f3b1 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml @@ -0,0 +1,45633 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h new file mode 100644 index 00000000..3167cbb0 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h @@ -0,0 +1,719 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SOC_H +#define HPM_SOC_H + + +/* List of external IRQs */ +#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ +#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ +#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ +#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ +#define IRQn_GPIO0_X 5 /* GPIO0_X IRQ */ +#define IRQn_GPIO0_Y 6 /* GPIO0_Y IRQ */ +#define IRQn_GPIO0_Z 7 /* GPIO0_Z IRQ */ +#define IRQn_GPIO1_A 8 /* GPIO1_A IRQ */ +#define IRQn_GPIO1_B 9 /* GPIO1_B IRQ */ +#define IRQn_GPIO1_C 10 /* GPIO1_C IRQ */ +#define IRQn_GPIO1_D 11 /* GPIO1_D IRQ */ +#define IRQn_GPIO1_X 12 /* GPIO1_X IRQ */ +#define IRQn_GPIO1_Y 13 /* GPIO1_Y IRQ */ +#define IRQn_GPIO1_Z 14 /* GPIO1_Z IRQ */ +#define IRQn_ADC0 15 /* ADC0 IRQ */ +#define IRQn_ADC1 16 /* ADC1 IRQ */ +#define IRQn_ADC2 17 /* ADC2 IRQ */ +#define IRQn_SDFM 18 /* SDFM IRQ */ +#define IRQn_DAC0 19 /* DAC0 IRQ */ +#define IRQn_DAC1 20 /* DAC1 IRQ */ +#define IRQn_ACMP_0 21 /* ACMP[0] IRQ */ +#define IRQn_ACMP_1 22 /* ACMP[1] IRQ */ +#define IRQn_ACMP_2 23 /* ACMP[2] IRQ */ +#define IRQn_ACMP_3 24 /* ACMP[3] IRQ */ +#define IRQn_SPI0 25 /* SPI0 IRQ */ +#define IRQn_SPI1 26 /* SPI1 IRQ */ +#define IRQn_SPI2 27 /* SPI2 IRQ */ +#define IRQn_SPI3 28 /* SPI3 IRQ */ +#define IRQn_UART0 29 /* UART0 IRQ */ +#define IRQn_UART1 30 /* UART1 IRQ */ +#define IRQn_UART2 31 /* UART2 IRQ */ +#define IRQn_UART3 32 /* UART3 IRQ */ +#define IRQn_UART4 33 /* UART4 IRQ */ +#define IRQn_UART5 34 /* UART5 IRQ */ +#define IRQn_UART6 35 /* UART6 IRQ */ +#define IRQn_UART7 36 /* UART7 IRQ */ +#define IRQn_CAN0 37 /* CAN0 IRQ */ +#define IRQn_CAN1 38 /* CAN1 IRQ */ +#define IRQn_CAN2 39 /* CAN2 IRQ */ +#define IRQn_CAN3 40 /* CAN3 IRQ */ +#define IRQn_PTPC 41 /* PTPC IRQ */ +#define IRQn_WDG0 42 /* WDG0 IRQ */ +#define IRQn_WDG1 43 /* WDG1 IRQ */ +#define IRQn_TSNS 44 /* TSNS IRQ */ +#define IRQn_MBX0A 45 /* MBX0A IRQ */ +#define IRQn_MBX0B 46 /* MBX0B IRQ */ +#define IRQn_MBX1A 47 /* MBX1A IRQ */ +#define IRQn_MBX1B 48 /* MBX1B IRQ */ +#define IRQn_GPTMR0 49 /* GPTMR0 IRQ */ +#define IRQn_GPTMR1 50 /* GPTMR1 IRQ */ +#define IRQn_GPTMR2 51 /* GPTMR2 IRQ */ +#define IRQn_GPTMR3 52 /* GPTMR3 IRQ */ +#define IRQn_I2C0 53 /* I2C0 IRQ */ +#define IRQn_I2C1 54 /* I2C1 IRQ */ +#define IRQn_I2C2 55 /* I2C2 IRQ */ +#define IRQn_I2C3 56 /* I2C3 IRQ */ +#define IRQn_PWM0 57 /* PWM0 IRQ */ +#define IRQn_HALL0 58 /* HALL0 IRQ */ +#define IRQn_QEI0 59 /* QEI0 IRQ */ +#define IRQn_PWM1 60 /* PWM1 IRQ */ +#define IRQn_HALL1 61 /* HALL1 IRQ */ +#define IRQn_QEI1 62 /* QEI1 IRQ */ +#define IRQn_PWM2 63 /* PWM2 IRQ */ +#define IRQn_HALL2 64 /* HALL2 IRQ */ +#define IRQn_QEI2 65 /* QEI2 IRQ */ +#define IRQn_PWM3 66 /* PWM3 IRQ */ +#define IRQn_HALL3 67 /* HALL3 IRQ */ +#define IRQn_QEI3 68 /* QEI3 IRQ */ +#define IRQn_SDP 69 /* SDP IRQ */ +#define IRQn_XPI0 70 /* XPI0 IRQ */ +#define IRQn_XDMA 71 /* XDMA IRQ */ +#define IRQn_HDMA 72 /* HDMA IRQ */ +#define IRQn_RNG 73 /* RNG IRQ */ +#define IRQn_USB0 74 /* USB0 IRQ */ +#define IRQn_PSEC 75 /* PSEC IRQ */ +#define IRQn_PGPIO 76 /* PGPIO IRQ */ +#define IRQn_PWDG 77 /* PWDG IRQ */ +#define IRQn_PTMR 78 /* PTMR IRQ */ +#define IRQn_PUART 79 /* PUART IRQ */ +#define IRQn_FUSE 80 /* FUSE IRQ */ +#define IRQn_SECMON 81 /* SECMON IRQ */ +#define IRQn_RTC 82 /* RTC IRQ */ +#define IRQn_BUTN 83 /* BUTN IRQ */ +#define IRQn_BGPIO 84 /* BGPIO IRQ */ +#define IRQn_BVIO 85 /* BVIO IRQ */ +#define IRQn_BROWNOUT 86 /* BROWNOUT IRQ */ +#define IRQn_SYSCTL 87 /* SYSCTL IRQ */ +#define IRQn_DEBUG_0 88 /* DEBUG[0] IRQ */ +#define IRQn_DEBUG_1 89 /* DEBUG[1] IRQ */ +#define IRQn_LIN0 90 /* LIN0 IRQ */ +#define IRQn_LIN1 91 /* LIN1 IRQ */ +#define IRQn_LIN2 92 /* LIN2 IRQ */ +#define IRQn_LIN3 93 /* LIN3 IRQ */ + +#include "hpm_common.h" + +#include "hpm_gpio_regs.h" +/* Address of GPIO instances */ +/* FGPIO base address */ +#define HPM_FGPIO_BASE (0xC0000UL) +/* FGPIO base pointer */ +#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) +/* GPIO0 base address */ +#define HPM_GPIO0_BASE (0xF0000000UL) +/* GPIO0 base pointer */ +#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) +/* GPIO1 base address */ +#define HPM_GPIO1_BASE (0xF0004000UL) +/* GPIO1 base pointer */ +#define HPM_GPIO1 ((GPIO_Type *) HPM_GPIO1_BASE) +/* PGPIO base address */ +#define HPM_PGPIO_BASE (0xF40DC000UL) +/* PGPIO base pointer */ +#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) +/* BGPIO base address */ +#define HPM_BGPIO_BASE (0xF5014000UL) +/* BGPIO base pointer */ +#define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE) + +/* Address of DM instances */ +/* DM base address */ +#define HPM_DM_BASE (0x30000000UL) + +/* Address of XBUS_SOC instances */ +/* GPV_SOC base address */ +#define HPM_GPV_SOC_BASE (0x30100000UL) + +#include "hpm_plic_regs.h" +/* Address of PLIC instances */ +/* PLIC base address */ +#define HPM_PLIC_BASE (0xE4000000UL) +/* PLIC base pointer */ +#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) + +#include "hpm_mchtmr_regs.h" +/* Address of MCHTMR instances */ +/* MCHTMR base address */ +#define HPM_MCHTMR_BASE (0xE6000000UL) +/* MCHTMR base pointer */ +#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) + +#include "hpm_plic_sw_regs.h" +/* Address of PLICSW instances */ +/* PLICSW base address */ +#define HPM_PLICSW_BASE (0xE6400000UL) +/* PLICSW base pointer */ +#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) + +#include "hpm_gpiom_regs.h" +/* Address of GPIOM instances */ +/* GPIOM base address */ +#define HPM_GPIOM_BASE (0xF0008000UL) +/* GPIOM base pointer */ +#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) + +#include "hpm_adc16_regs.h" +/* Address of ADC16 instances */ +/* ADC0 base address */ +#define HPM_ADC0_BASE (0xF0010000UL) +/* ADC0 base pointer */ +#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) +/* ADC1 base address */ +#define HPM_ADC1_BASE (0xF0014000UL) +/* ADC1 base pointer */ +#define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE) +/* ADC2 base address */ +#define HPM_ADC2_BASE (0xF0018000UL) +/* ADC2 base pointer */ +#define HPM_ADC2 ((ADC16_Type *) HPM_ADC2_BASE) + +#include "hpm_sdm_regs.h" +/* Address of SDM instances */ +/* SDM base address */ +#define HPM_SDM_BASE (0xF001C000UL) +/* SDM base pointer */ +#define HPM_SDM ((SDM_Type *) HPM_SDM_BASE) + +#include "hpm_acmp_regs.h" +/* Address of ACMP instances */ +/* ACMP base address */ +#define HPM_ACMP_BASE (0xF0020000UL) +/* ACMP base pointer */ +#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) + +#include "hpm_dac_regs.h" +/* Address of DAC instances */ +/* DAC0 base address */ +#define HPM_DAC0_BASE (0xF0024000UL) +/* DAC0 base pointer */ +#define HPM_DAC0 ((DAC_Type *) HPM_DAC0_BASE) +/* DAC1 base address */ +#define HPM_DAC1_BASE (0xF0028000UL) +/* DAC1 base pointer */ +#define HPM_DAC1 ((DAC_Type *) HPM_DAC1_BASE) + +#include "hpm_spi_regs.h" +/* Address of SPI instances */ +/* SPI0 base address */ +#define HPM_SPI0_BASE (0xF0030000UL) +/* SPI0 base pointer */ +#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) +/* SPI1 base address */ +#define HPM_SPI1_BASE (0xF0034000UL) +/* SPI1 base pointer */ +#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) +/* SPI2 base address */ +#define HPM_SPI2_BASE (0xF0038000UL) +/* SPI2 base pointer */ +#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) +/* SPI3 base address */ +#define HPM_SPI3_BASE (0xF003C000UL) +/* SPI3 base pointer */ +#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) + +#include "hpm_uart_regs.h" +/* Address of UART instances */ +/* UART0 base address */ +#define HPM_UART0_BASE (0xF0040000UL) +/* UART0 base pointer */ +#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) +/* UART1 base address */ +#define HPM_UART1_BASE (0xF0044000UL) +/* UART1 base pointer */ +#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) +/* UART2 base address */ +#define HPM_UART2_BASE (0xF0048000UL) +/* UART2 base pointer */ +#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) +/* UART3 base address */ +#define HPM_UART3_BASE (0xF004C000UL) +/* UART3 base pointer */ +#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) +/* UART4 base address */ +#define HPM_UART4_BASE (0xF0050000UL) +/* UART4 base pointer */ +#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) +/* UART5 base address */ +#define HPM_UART5_BASE (0xF0054000UL) +/* UART5 base pointer */ +#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) +/* UART6 base address */ +#define HPM_UART6_BASE (0xF0058000UL) +/* UART6 base pointer */ +#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) +/* UART7 base address */ +#define HPM_UART7_BASE (0xF005C000UL) +/* UART7 base pointer */ +#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) +/* PUART base address */ +#define HPM_PUART_BASE (0xF40E4000UL) +/* PUART base pointer */ +#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) + +#include "hpm_mcan_regs.h" +/* Address of MCAN instances */ +/* MCAN0 base address */ +#define HPM_MCAN0_BASE (0xF0080000UL) +/* MCAN0 base pointer */ +#define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE) +/* MCAN1 base address */ +#define HPM_MCAN1_BASE (0xF0084000UL) +/* MCAN1 base pointer */ +#define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE) +/* MCAN2 base address */ +#define HPM_MCAN2_BASE (0xF0088000UL) +/* MCAN2 base pointer */ +#define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE) +/* MCAN3 base address */ +#define HPM_MCAN3_BASE (0xF008C000UL) +/* MCAN3 base pointer */ +#define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE) + +#include "hpm_wdg_regs.h" +/* Address of WDOG instances */ +/* WDG0 base address */ +#define HPM_WDG0_BASE (0xF0090000UL) +/* WDG0 base pointer */ +#define HPM_WDG0 ((WDG_Type *) HPM_WDG0_BASE) +/* WDG1 base address */ +#define HPM_WDG1_BASE (0xF0094000UL) +/* WDG1 base pointer */ +#define HPM_WDG1 ((WDG_Type *) HPM_WDG1_BASE) +/* PWDG base address */ +#define HPM_PWDG_BASE (0xF40E8000UL) +/* PWDG base pointer */ +#define HPM_PWDG ((WDG_Type *) HPM_PWDG_BASE) + +#include "hpm_mbx_regs.h" +/* Address of MBX instances */ +/* MBX0A base address */ +#define HPM_MBX0A_BASE (0xF00A0000UL) +/* MBX0A base pointer */ +#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) +/* MBX0B base address */ +#define HPM_MBX0B_BASE (0xF00A4000UL) +/* MBX0B base pointer */ +#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) +/* MBX1A base address */ +#define HPM_MBX1A_BASE (0xF00A8000UL) +/* MBX1A base pointer */ +#define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE) +/* MBX1B base address */ +#define HPM_MBX1B_BASE (0xF00AC000UL) +/* MBX1B base pointer */ +#define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE) + +#include "hpm_ptpc_regs.h" +/* Address of PTPC instances */ +/* PTPC base address */ +#define HPM_PTPC_BASE (0xF00B0000UL) +/* PTPC base pointer */ +#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) + +#include "hpm_crc_regs.h" +/* Address of CRC instances */ +/* CRC base address */ +#define HPM_CRC_BASE (0xF00B8000UL) +/* CRC base pointer */ +#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) + +#include "hpm_dmamux_regs.h" +/* Address of DMAMUX instances */ +/* DMAMUX base address */ +#define HPM_DMAMUX_BASE (0xF00C0000UL) +/* DMAMUX base pointer */ +#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) + +#include "hpm_dma_regs.h" +/* Address of DMA instances */ +/* HDMA base address */ +#define HPM_HDMA_BASE (0xF00C4000UL) +/* HDMA base pointer */ +#define HPM_HDMA ((DMA_Type *) HPM_HDMA_BASE) +/* XDMA base address */ +#define HPM_XDMA_BASE (0xF3048000UL) +/* XDMA base pointer */ +#define HPM_XDMA ((DMA_Type *) HPM_XDMA_BASE) + +#include "hpm_rng_regs.h" +/* Address of RNG instances */ +/* RNG base address */ +#define HPM_RNG_BASE (0xF00C8000UL) +/* RNG base pointer */ +#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) + +#include "hpm_keym_regs.h" +/* Address of KEYM instances */ +/* KEYM base address */ +#define HPM_KEYM_BASE (0xF00CC000UL) +/* KEYM base pointer */ +#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) + +#include "hpm_pwm_regs.h" +/* Address of PWM instances */ +/* PWM0 base address */ +#define HPM_PWM0_BASE (0xF0200000UL) +/* PWM0 base pointer */ +#define HPM_PWM0 ((PWM_Type *) HPM_PWM0_BASE) +/* PWM1 base address */ +#define HPM_PWM1_BASE (0xF0210000UL) +/* PWM1 base pointer */ +#define HPM_PWM1 ((PWM_Type *) HPM_PWM1_BASE) +/* PWM2 base address */ +#define HPM_PWM2_BASE (0xF0220000UL) +/* PWM2 base pointer */ +#define HPM_PWM2 ((PWM_Type *) HPM_PWM2_BASE) +/* PWM3 base address */ +#define HPM_PWM3_BASE (0xF0230000UL) +/* PWM3 base pointer */ +#define HPM_PWM3 ((PWM_Type *) HPM_PWM3_BASE) + +#include "hpm_hall_regs.h" +/* Address of HALL instances */ +/* HALL0 base address */ +#define HPM_HALL0_BASE (0xF0204000UL) +/* HALL0 base pointer */ +#define HPM_HALL0 ((HALL_Type *) HPM_HALL0_BASE) +/* HALL1 base address */ +#define HPM_HALL1_BASE (0xF0214000UL) +/* HALL1 base pointer */ +#define HPM_HALL1 ((HALL_Type *) HPM_HALL1_BASE) +/* HALL2 base address */ +#define HPM_HALL2_BASE (0xF0224000UL) +/* HALL2 base pointer */ +#define HPM_HALL2 ((HALL_Type *) HPM_HALL2_BASE) +/* HALL3 base address */ +#define HPM_HALL3_BASE (0xF0234000UL) +/* HALL3 base pointer */ +#define HPM_HALL3 ((HALL_Type *) HPM_HALL3_BASE) + +#include "hpm_qei_regs.h" +/* Address of QEI instances */ +/* QEI0 base address */ +#define HPM_QEI0_BASE (0xF0208000UL) +/* QEI0 base pointer */ +#define HPM_QEI0 ((QEI_Type *) HPM_QEI0_BASE) +/* QEI1 base address */ +#define HPM_QEI1_BASE (0xF0218000UL) +/* QEI1 base pointer */ +#define HPM_QEI1 ((QEI_Type *) HPM_QEI1_BASE) +/* QEI2 base address */ +#define HPM_QEI2_BASE (0xF0228000UL) +/* QEI2 base pointer */ +#define HPM_QEI2 ((QEI_Type *) HPM_QEI2_BASE) +/* QEI3 base address */ +#define HPM_QEI3_BASE (0xF0238000UL) +/* QEI3 base pointer */ +#define HPM_QEI3 ((QEI_Type *) HPM_QEI3_BASE) + +#include "hpm_trgm_regs.h" +/* Address of TRGM instances */ +/* TRGM0 base address */ +#define HPM_TRGM0_BASE (0xF020C000UL) +/* TRGM0 base pointer */ +#define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) +/* TRGM1 base address */ +#define HPM_TRGM1_BASE (0xF021C000UL) +/* TRGM1 base pointer */ +#define HPM_TRGM1 ((TRGM_Type *) HPM_TRGM1_BASE) +/* TRGM2 base address */ +#define HPM_TRGM2_BASE (0xF022C000UL) +/* TRGM2 base pointer */ +#define HPM_TRGM2 ((TRGM_Type *) HPM_TRGM2_BASE) +/* TRGM3 base address */ +#define HPM_TRGM3_BASE (0xF023C000UL) +/* TRGM3 base pointer */ +#define HPM_TRGM3 ((TRGM_Type *) HPM_TRGM3_BASE) + +#include "hpm_pla_regs.h" +/* Address of PLA instances */ +/* PLA0 base address */ +#define HPM_PLA0_BASE (0xF020E000UL) +/* PLA0 base pointer */ +#define HPM_PLA0 ((PLA_Type *) HPM_PLA0_BASE) +/* PLA1 base address */ +#define HPM_PLA1_BASE (0xF021E000UL) +/* PLA1 base pointer */ +#define HPM_PLA1 ((PLA_Type *) HPM_PLA1_BASE) + +#include "hpm_synt_regs.h" +/* Address of SYNT instances */ +/* SYNT base address */ +#define HPM_SYNT_BASE (0xF0240000UL) +/* SYNT base pointer */ +#define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) + +/* Address of PLA_X2 instances */ +/* PLA_X2 base address */ +#define HPM_PLA_X2_BASE (0xF024E000UL) + +#include "hpm_usb_regs.h" +/* Address of USB instances */ +/* USB0 base address */ +#define HPM_USB0_BASE (0xF2020000UL) +/* USB0 base pointer */ +#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) + +#include "hpm_gptmr_regs.h" +/* Address of TMR instances */ +/* GPTMR0 base address */ +#define HPM_GPTMR0_BASE (0xF3000000UL) +/* GPTMR0 base pointer */ +#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) +/* GPTMR1 base address */ +#define HPM_GPTMR1_BASE (0xF3004000UL) +/* GPTMR1 base pointer */ +#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) +/* GPTMR2 base address */ +#define HPM_GPTMR2_BASE (0xF3008000UL) +/* GPTMR2 base pointer */ +#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) +/* GPTMR3 base address */ +#define HPM_GPTMR3_BASE (0xF300C000UL) +/* GPTMR3 base pointer */ +#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) +/* PTMR base address */ +#define HPM_PTMR_BASE (0xF40E0000UL) +/* PTMR base pointer */ +#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) + +#include "hpm_i2c_regs.h" +/* Address of I2C instances */ +/* I2C0 base address */ +#define HPM_I2C0_BASE (0xF3020000UL) +/* I2C0 base pointer */ +#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) +/* I2C1 base address */ +#define HPM_I2C1_BASE (0xF3024000UL) +/* I2C1 base pointer */ +#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) +/* I2C2 base address */ +#define HPM_I2C2_BASE (0xF3028000UL) +/* I2C2 base pointer */ +#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) +/* I2C3 base address */ +#define HPM_I2C3_BASE (0xF302C000UL) +/* I2C3 base pointer */ +#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) + +#include "hpm_lin_regs.h" +/* Address of LIN instances */ +/* LIN0 base address */ +#define HPM_LIN0_BASE (0xF3030000UL) +/* LIN0 base pointer */ +#define HPM_LIN0 ((LIN_Type *) HPM_LIN0_BASE) +/* LIN1 base address */ +#define HPM_LIN1_BASE (0xF3034000UL) +/* LIN1 base pointer */ +#define HPM_LIN1 ((LIN_Type *) HPM_LIN1_BASE) +/* LIN2 base address */ +#define HPM_LIN2_BASE (0xF3038000UL) +/* LIN2 base pointer */ +#define HPM_LIN2 ((LIN_Type *) HPM_LIN2_BASE) +/* LIN3 base address */ +#define HPM_LIN3_BASE (0xF303C000UL) +/* LIN3 base pointer */ +#define HPM_LIN3 ((LIN_Type *) HPM_LIN3_BASE) + +#include "hpm_sdp_regs.h" +/* Address of SDP instances */ +/* SDP base address */ +#define HPM_SDP_BASE (0xF304C000UL) +/* SDP base pointer */ +#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) + +/* Address of ROMC instances */ +/* ROMC base address */ +#define HPM_ROMC_BASE (0xF3054000UL) + +#include "hpm_sysctl_regs.h" +/* Address of SYSCTL instances */ +/* SYSCTL base address */ +#define HPM_SYSCTL_BASE (0xF4000000UL) +/* SYSCTL base pointer */ +#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) + +#include "hpm_ioc_regs.h" +/* Address of IOC instances */ +/* IOC base address */ +#define HPM_IOC_BASE (0xF4040000UL) +/* IOC base pointer */ +#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) +/* PIOC base address */ +#define HPM_PIOC_BASE (0xF40D8000UL) +/* PIOC base pointer */ +#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) +/* BIOC base address */ +#define HPM_BIOC_BASE (0xF5010000UL) +/* BIOC base pointer */ +#define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE) + +#include "hpm_otp_regs.h" +/* Address of OTP instances */ +/* OTPSHW base address */ +#define HPM_OTPSHW_BASE (0xF4080000UL) +/* OTPSHW base pointer */ +#define HPM_OTPSHW ((OTP_Type *) HPM_OTPSHW_BASE) +/* OTP base address */ +#define HPM_OTP_BASE (0xF40C8000UL) +/* OTP base pointer */ +#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) + +#include "hpm_ppor_regs.h" +/* Address of PPOR instances */ +/* PPOR base address */ +#define HPM_PPOR_BASE (0xF40C0000UL) +/* PPOR base pointer */ +#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) + +#include "hpm_pcfg_regs.h" +/* Address of PCFG instances */ +/* PCFG base address */ +#define HPM_PCFG_BASE (0xF40C4000UL) +/* PCFG base pointer */ +#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) + +#include "hpm_psec_regs.h" +/* Address of PSEC instances */ +/* PSEC base address */ +#define HPM_PSEC_BASE (0xF40CC000UL) +/* PSEC base pointer */ +#define HPM_PSEC ((PSEC_Type *) HPM_PSEC_BASE) + +#include "hpm_pmon_regs.h" +/* Address of PMON instances */ +/* PMON base address */ +#define HPM_PMON_BASE (0xF40D0000UL) +/* PMON base pointer */ +#define HPM_PMON ((PMON_Type *) HPM_PMON_BASE) + +#include "hpm_pgpr_regs.h" +/* Address of PGPR instances */ +/* PGPR base address */ +#define HPM_PGPR_BASE (0xF40D4000UL) +/* PGPR base pointer */ +#define HPM_PGPR ((PGPR_Type *) HPM_PGPR_BASE) + +#include "hpm_pllctlv2_regs.h" +/* Address of PLLCTLV2 instances */ +/* PLLCTLV2 base address */ +#define HPM_PLLCTLV2_BASE (0xF4100000UL) +/* PLLCTLV2 base pointer */ +#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) + +#include "hpm_tsns_regs.h" +/* Address of TSNS instances */ +/* TSNS base address */ +#define HPM_TSNS_BASE (0xF4104000UL) +/* TSNS base pointer */ +#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) + +/* Address of BACC instances */ +/* BACC base address */ +#define HPM_BACC_BASE (0xF5000000UL) + +#include "hpm_bpor_regs.h" +/* Address of BPOR instances */ +/* BPOR base address */ +#define HPM_BPOR_BASE (0xF5004000UL) +/* BPOR base pointer */ +#define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE) + +#include "hpm_bcfg_regs.h" +/* Address of BCFG instances */ +/* BCFG base address */ +#define HPM_BCFG_BASE (0xF5008000UL) +/* BCFG base pointer */ +#define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE) + +#include "hpm_butn_regs.h" +/* Address of BUTN instances */ +/* BUTN base address */ +#define HPM_BUTN_BASE (0xF500C000UL) +/* BUTN base pointer */ +#define HPM_BUTN ((BUTN_Type *) HPM_BUTN_BASE) + +#include "hpm_bgpr_regs.h" +/* Address of BGPR instances */ +/* BGPR base address */ +#define HPM_BGPR_BASE (0xF5018000UL) +/* BGPR base pointer */ +#define HPM_BGPR ((BGPR_Type *) HPM_BGPR_BASE) + +#include "hpm_bsec_regs.h" +/* Address of BSEC instances */ +/* BSEC base address */ +#define HPM_BSEC_BASE (0xF5040000UL) +/* BSEC base pointer */ +#define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE) + +#include "hpm_rtc_regs.h" +/* Address of RTC instances */ +/* RTC base address */ +#define HPM_RTC_BASE (0xF5044000UL) +/* RTC base pointer */ +#define HPM_RTC ((RTC_Type *) HPM_RTC_BASE) + +#include "hpm_bkey_regs.h" +/* Address of BKEY instances */ +/* BKEY base address */ +#define HPM_BKEY_BASE (0xF5048000UL) +/* BKEY base pointer */ +#define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE) + +#include "hpm_bmon_regs.h" +/* Address of BMON instances */ +/* BMON base address */ +#define HPM_BMON_BASE (0xF504C000UL) +/* BMON base pointer */ +#define HPM_BMON ((BMON_Type *) HPM_BMON_BASE) + +#include "hpm_tamp_regs.h" +/* Address of TAMP instances */ +/* TAMP base address */ +#define HPM_TAMP_BASE (0xF5050000UL) +/* TAMP base pointer */ +#define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE) + +#include "hpm_mono_regs.h" +/* Address of MONO instances */ +/* MONO base address */ +#define HPM_MONO_BASE (0xF5054000UL) +/* MONO base pointer */ +#define HPM_MONO ((MONO_Type *) HPM_MONO_BASE) + + +#include "riscv/riscv_core.h" +#include "hpm_csr_regs.h" +#include "hpm_interrupt.h" +#include "hpm_misc.h" +#include "hpm_dmamux_src.h" +#include "hpm_trgmmux_src.h" +#include "hpm_iomux.h" +#include "hpm_pmic_iomux.h" +#include "hpm_batt_iomux.h" +#include "hpm_ioc_regs.h" +#include "hpm_gpiom_regs.h" +#include "hpm_sysctl_regs.h" +#include "hpm_trgm_regs.h" +#include "hpm_pcfg_regs.h" +#include "hpm_pgpr_regs.h" +#include "hpm_ppor_regs.h" +#include "hpm_bcfg_regs.h" +#include "hpm_bgpr_regs.h" +#include "hpm_bpor_regs.h" +#endif /* HPM_SOC_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h new file mode 100644 index 00000000..33901c90 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SOC_FEATURE_H +#define HPM_SOC_FEATURE_H + +#include "hpm_soc.h" + +/* + * UART section + */ +#define UART_SOC_FIFO_SIZE (16U) +#define UART_SOC_HAS_RXLINE_IDLE_DETECTION (1U) + +/* + * I2C Section + */ +#define I2C_SOC_FIFO_SIZE (4U) +#define I2C_SOC_TRANSFER_COUNT_MAX (256U) + +/* + * PMIC Section + */ +#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) +#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) +#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) +#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) +#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) +#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) + +/* + * PLLCTL Section + */ +#define PLLCTL_SOC_PLL_MAX_COUNT (3U) +/* PLL reference clock in hz */ +#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) +/* only PLL1 and PLL2 have DIV0, DIV1 */ +#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) +#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) + + +/* + * PWM Section + */ +#define PWM_SOC_PWM_MAX_COUNT (8U) +#define PWM_SOC_CMP_MAX_COUNT (24U) +#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) +#define PWM_SOC_OUTPUT_MAX_COUNT (24U) + +/* + * DMA Section + */ +#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) +#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) +#define DMA_SOC_BUS_NUM (1U) +#define DMA_SOC_CHANNEL_NUM (8U) +#define DMA_SOC_MAX_COUNT (2U) +#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) +#define DMA_SOC_HAS_IDLE_FLAG (1U) + +/* + * PDMA Section + */ +#define PDMA_SOC_PS_MAX_COUNT (0U) + +/* + * LCDC Section + */ +#define LCDC_SOC_MAX_LAYER_COUNT (0U) +#define LCDC_SOC_MAX_CSC_LAYER_COUNT (0U) +#define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2) +#define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2) + +/* + * USB Section + */ +#define USB_SOC_MAX_COUNT (1U) + +#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) +#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) +#define USB_SOC_DCD_QTD_ALIGNMENT (32U) +#define USB_SOC_DCD_QHD_ALIGNMENT (64U) +#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (8U) +#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) + +#define USB_SOC_HCD_QTD_BUFFER_COUNT (5U) +#define USB_SOC_HCD_QTD_ALIGNMENT (32U) +#define USB_SOC_HCD_QHD_ALIGNMENT (32U) +#define USB_SOC_HCD_MAX_ENDPOINT_COUNT (8U) +#define USB_SOC_HCD_MAX_XFER_ENDPOINT_COUNT (USB_SOC_HCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) +#define USB_SOC_HCD_DATA_RAM_ADDRESS_ALIGNMENT (4096U) + +/* + * ADC Section + */ +#define ADC_SOC_SEQ_MAX_LEN (16U) +#define ADC_SOC_MAX_TRIG_CH_LEN (4U) +#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) +#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) +#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) +#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (1024U) +#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) + +#define ADC16_SOC_PARAMS_LEN (34U) +#define ADC16_SOC_MAX_CH_NUM (15U) +#define ADC16_SOC_TEMP_CH_EN (0U) +#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) +#define ADC16_SOC_MAX_TRIG_CH_NUM (11U) +#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) + +/* + * SYSCTL Section + */ +#define SYSCTL_SOC_CPU_GPR_COUNT (14U) +#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) + +/* + * PTPC Section + */ +#define PTPC_SOC_TIMER_MAX_COUNT (2U) + +/* + * CAN Section + */ +#define CAN_SOC_MAX_COUNT (2U) + +/* + * SDP Section + */ +#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) +#define SDP_HAS_SM3_SUPPORT (1U) +#define SDP_HAS_SM4_SUPPORT (1U) + +/* + * SOC Privilege mdoe + */ +#define SOC_HAS_S_MODE (1U) + +/* + * DAC Section + */ +#define DAC_SOC_BUFF_ALIGNED_SIZE (32U) +#define DAC_SOC_MAX_DATA (4095U) +#define DAC_SOC_MAX_BUFF_COUNT (65536U) +#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL) + + +/* + * SDXC Section + */ +#define SDXC_SOC_HAS_MISC_CTRL0 (1) +#define SDXC_SOC_HAS_MISC_CTRL1 (1) + +/* + * SPI Section + */ +#define SPI_SOC_TRANSFER_COUNT_MAX (512U) +#define SPI_SOC_FIFO_DEPTH (4U) + +/** + * PWM Section + * + */ +#define PWM_SOC_HRPWM_SUPPORT (1U) +#define PWM_SOC_SHADOW_TRIG_SUPPORT (1U) +#define PWM_SOC_TIMER_RESET_SUPPORT (1U) + +/** + * IOC Section + * + */ +#define IOC_SOC_PAD_MAX (487) + +#endif /* HPM_SOC_FEATURE_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c b/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c new file mode 100644 index 00000000..ffc21973 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sysctl_drv.h" +#include "hpm_soc_feature.h" + +#define SYSCTL_RESOURCE_GROUP0 0 +#define SYSCTL_RESOURCE_GROUP1 1 + +#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | (((cpu) & 1) << 24)) + +static inline bool sysctl_valid_cpu_index(uint8_t cpu) +{ +#ifdef SYSCTL_CPU_CPU1 + return (cpu > SYSCTL_CPU_CPU1) ? false : true; +#else + return (cpu != SYSCTL_CPU_CPU0) ? false : true; +#endif +} + +hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint32_t *data, uint32_t size) +{ + uint32_t i; + if ((!sysctl_valid_cpu_index(cpu)) || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { + return status_invalid_argument; + } + for (i = 0; i < size; i++) { + *(data + i) = ptr->CPU[cpu].GPR[i]; + } + return status_success; +} + +static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + *(data + i) = ptr->CPU[cpu].GPR[start + i]; + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); +} + +hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); +} + +static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, const uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + ptr->CPU[cpu].GPR[start + i] = *(data + i); + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) +{ + hpm_stat_t stat = status_success; + uint16_t gpr_mask; + stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); + if (stat != status_success) { + return stat; + } + if (lock) { + gpr_mask = ((1 << count) - 1) << start; + sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); + } + return stat; +} + +hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) +{ + hpm_stat_t stat = status_success; + uint16_t gpr_mask; + stat = _sysctl_cpu_set_gpr(ptr, 1, start, count, data); + if (stat != status_success) { + return stat; + } + if (lock) { + gpr_mask = ((1 << count) - 1) << start; + sysctl_cpu1_lock_gpr_with_mask(ptr, gpr_mask); + } + return stat; +} + +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) +{ + config->mode = monitor_work_mode_record; + config->accuracy = monitor_accuracy_1khz; + config->reference = monitor_reference_24mhz; + config->divide_by = 1; + config->high_limit = 0; + config->low_limit = 0; + config->start_measure = true; + config->enable_output = false; + config->target = monitor_target_clk_top_cpu0; +} + +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t slice, monitor_config_t *config) +{ + ptr->MONITOR[slice].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); + + if (config->mode == monitor_work_mode_compare) { + ptr->MONITOR[slice].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); + ptr->MONITOR[slice].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); + } + + ptr->MONITOR[slice].CONTROL = (ptr->MONITOR[slice].CONTROL & + ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | + SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | + (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | + SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | + SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | + SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | + SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | + SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); +} + +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output) +{ + uint32_t frequency = 0; + monitor_config_t monitor = { 0 }; + sysctl_monitor_get_default_config(ptr, &monitor); + monitor.target = target; + monitor.enable_output = enable_output; + sysctl_monitor_init(ptr, monitor_index, &monitor); + if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { + frequency = sysctl_monitor_get_current_result(ptr, monitor_index); + } + return frequency; +} + +hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) +{ + if (!sysctl_valid_cpu_index(cpu)) { + return status_invalid_argument; + } + ptr->CPU[cpu].GPR[0] = entry; + ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); + return status_success; +} + +hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry) +{ + return sysctl_set_cpu_entry(ptr, 1, entry); +} + +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) +{ + return sysctl_set_cpu_entry(ptr, 0, entry); +} + +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t linkable_resource, + bool enable) +{ + uint32_t index, offset; + if (linkable_resource < sysctl_resource_linkable_start) { + return status_invalid_argument; + } + + index = (linkable_resource - sysctl_resource_linkable_start) / 32; + offset = (linkable_resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); + break; + case SYSCTL_RESOURCE_GROUP1: + ptr->GROUP1[index].VALUE = (ptr->GROUP1[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); + break; + default: + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); +} + +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); +} + +hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, true); +} + +hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, false); +} + +hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint32_t divide_by) +{ + uint32_t node = (uint32_t) node_index; + if (node >= clock_node_adc_start) { + return status_invalid_argument; + } + + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); + while (sysctl_clock_target_is_busy(ptr, node)) { + } + return status_success; +} + +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node_index, clock_source_t source, uint32_t divide_by) +{ + uint32_t node = (uint32_t) node_index; + if (node >= clock_node_adc_start) { + return status_invalid_argument; + } + + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | + (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); + while (sysctl_clock_target_is_busy(ptr, node)) { + } + return status_success; +} + +hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, + clock_source_t source, + uint32_t cpu_div, + uint32_t axi_sub_div, + uint32_t ahb_sub_div) +{ + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + + uint32_t origin_cpu_div = SYSCTL_CLOCK_CPU_DIV_GET(ptr->CLOCK_CPU[0]) + 1U; + if (origin_cpu_div == cpu_div) { + ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div) | + SYSCTL_CLOCK_CPU_SUB0_DIV_SET(axi_sub_div - 1) | SYSCTL_CLOCK_CPU_SUB1_DIV_SET(ahb_sub_div - 1); + while (sysctl_cpu_clock_any_is_busy(ptr)) { + } + } + ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div - 1) | + SYSCTL_CLOCK_CPU_SUB0_DIV_SET(axi_sub_div - 1) | SYSCTL_CLOCK_CPU_SUB1_DIV_SET(ahb_sub_div - 1); + + while (sysctl_cpu_clock_any_is_busy(ptr)) { + } + + return status_success; +} + +hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source) +{ + if (source >= clock_source_adc_clk_end) { + return status_invalid_argument; + } + uint32_t adc_index = (uint32_t) (node - clock_node_adc_start); + if (adc_index >= ARRAY_SIZE(ptr->ADCCLK)) { + return status_invalid_argument; + } + + ptr->ADCCLK[adc_index] = (ptr->ADCCLK[adc_index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); + + return status_success; +} + +hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source) +{ + if (source >= clock_source_dac_clk_end) { + return status_invalid_argument; + } + uint32_t dac_index = (uint32_t) (node - clock_node_dac_start); + if (dac_index >= ARRAY_SIZE(ptr->DACCLK)) { + return status_invalid_argument; + } + + ptr->DACCLK[dac_index] = (ptr->DACCLK[dac_index] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(source); + + return status_success; +} diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h new file mode 100644 index 00000000..77b31715 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h @@ -0,0 +1,1521 @@ +/** + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SYSCTL_DRV_H +#define HPM_SYSCTL_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_regs.h" + +/** + * + * @brief SYSCTL driver APIs + * @defgroup sysctl_interface SYSCTL driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief Retention domains + */typedef enum { + sysctl_retention_domain_sys = 0, + sysctl_retention_domain_cpu0 = 2, + sysctl_retention_domain_cpu1 = 4, + sysctl_retention_domain_xtal24m = 6, + sysctl_retention_domain_pll0 = 7, + sysctl_retention_domain_pll1 = 8, + sysctl_retention_domain_pll2 = 9, +} sysctl_retention_domain_t; + +/** + * @brief Clock presets + */ +typedef enum { + sysctl_preset_0 = 1 << 0, + sysctl_preset_1 = 1 << 1, + sysctl_preset_2 = 1 << 2, + sysctl_preset_3 = 1 << 3, +} sysctl_preset_t; + +/** + * @brief Reset domains + */ +typedef enum { + sysctl_reset_domain_soc = 0, + sysctl_reset_domain_cpu0, + sysctl_reset_domain_cpu1, +} sysctl_reset_domain_t; + +/** + * @brief Resource + */ +typedef enum { + sysctl_resource_cpu0 = SYSCTL_RESOURCE_CPU0, + sysctl_resource_cpx0 = SYSCTL_RESOURCE_CPX0, + sysctl_resource_cpu1 = SYSCTL_RESOURCE_CPU1, + sysctl_resource_cpx1 = SYSCTL_RESOURCE_CPX1, + sysctl_resource_pow_cpu0 = SYSCTL_RESOURCE_POW_CPU0, + sysctl_resource_pow_cpu1 = SYSCTL_RESOURCE_POW_CPU1, + sysctl_resource_rst_soc = SYSCTL_RESOURCE_RST_SOC, + sysctl_resource_rst_cpu0 = SYSCTL_RESOURCE_RST_CPU0, + sysctl_resource_rst_cpu1 = SYSCTL_RESOURCE_RST_CPU1, + sysctl_resource_xtal = SYSCTL_RESOURCE_CLK_SRC_XTAL, + sysctl_resource_pll0 = SYSCTL_RESOURCE_CLK_SRC_PLL0, + sysctl_resource_clk0_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0, + sysctl_resource_clk1_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0, + sysctl_resource_clk2_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0, + sysctl_resource_pll1 = SYSCTL_RESOURCE_CLK_SRC_PLL1, + sysctl_resource_clk0_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1, + sysctl_resource_clk1_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1, + sysctl_resource_pll2 = SYSCTL_RESOURCE_CLK_SRC_PLL2, + sysctl_resource_clk0_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2, + sysctl_resource_clk1_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2, + sysctl_resource_pll0_ref = SYSCTL_RESOURCE_CLK_SRC_PLL0_REF, + sysctl_resource_pll1_ref = SYSCTL_RESOURCE_CLK_SRC_PLL1_REF, + sysctl_resource_pll2_ref = SYSCTL_RESOURCE_CLK_SRC_PLL2_REF, + + sysctl_resource_clk_top_cpu0 = SYSCTL_RESOURCE_CLK_TOP_CPU0, + sysctl_resource_clk_top_mchtmr0 = SYSCTL_RESOURCE_CLK_TOP_MCT0, + sysctl_resource_clk_top_mchtmr1 = SYSCTL_RESOURCE_CLK_TOP_MCT1, + sysctl_resource_clk_top_xpi0 = SYSCTL_RESOURCE_CLK_TOP_XPI0, + sysctl_resource_clk_top_gptmr0 = SYSCTL_RESOURCE_CLK_TOP_TMR0, + sysctl_resource_clk_top_gptmr1 = SYSCTL_RESOURCE_CLK_TOP_TMR1, + sysctl_resource_clk_top_gptmr2 = SYSCTL_RESOURCE_CLK_TOP_TMR2, + sysctl_resource_clk_top_gptmr3 = SYSCTL_RESOURCE_CLK_TOP_TMR3, + sysctl_resource_clk_top_uart0 = SYSCTL_RESOURCE_CLK_TOP_URT0, + sysctl_resource_clk_top_uart1 = SYSCTL_RESOURCE_CLK_TOP_URT1, + sysctl_resource_clk_top_uart2 = SYSCTL_RESOURCE_CLK_TOP_URT2, + sysctl_resource_clk_top_uart3 = SYSCTL_RESOURCE_CLK_TOP_URT3, + sysctl_resource_clk_top_uart4 = SYSCTL_RESOURCE_CLK_TOP_URT4, + sysctl_resource_clk_top_uart5 = SYSCTL_RESOURCE_CLK_TOP_URT5, + sysctl_resource_clk_top_uart6 = SYSCTL_RESOURCE_CLK_TOP_URT6, + sysctl_resource_clk_top_uart7 = SYSCTL_RESOURCE_CLK_TOP_URT7, + sysctl_resource_clk_top_i2c0 = SYSCTL_RESOURCE_CLK_TOP_I2C0, + sysctl_resource_clk_top_i2c1 = SYSCTL_RESOURCE_CLK_TOP_I2C1, + sysctl_resource_clk_top_i2c2 = SYSCTL_RESOURCE_CLK_TOP_I2C2, + sysctl_resource_clk_top_i2c3 = SYSCTL_RESOURCE_CLK_TOP_I2C3, + sysctl_resource_clk_top_spi0 = SYSCTL_RESOURCE_CLK_TOP_SPI0, + sysctl_resource_clk_top_spi1 = SYSCTL_RESOURCE_CLK_TOP_SPI1, + sysctl_resource_clk_top_spi2 = SYSCTL_RESOURCE_CLK_TOP_SPI2, + sysctl_resource_clk_top_spi3 = SYSCTL_RESOURCE_CLK_TOP_SPI3, + sysctl_resource_clk_top_can0 = SYSCTL_RESOURCE_CLK_TOP_CAN0, + sysctl_resource_clk_top_can1 = SYSCTL_RESOURCE_CLK_TOP_CAN1, + sysctl_resource_clk_top_can2 = SYSCTL_RESOURCE_CLK_TOP_CAN2, + sysctl_resource_clk_top_can3 = SYSCTL_RESOURCE_CLK_TOP_CAN3, + sysctl_resource_clk_top_ptpc = SYSCTL_RESOURCE_CLK_TOP_PTPC, + sysctl_resource_clk_top_ana0 = SYSCTL_RESOURCE_CLK_TOP_ANA0, + sysctl_resource_clk_top_ana1 = SYSCTL_RESOURCE_CLK_TOP_ANA1, + sysctl_resource_clk_top_ana2 = SYSCTL_RESOURCE_CLK_TOP_ANA2, + sysctl_resource_clk_top_ana3 = SYSCTL_RESOURCE_CLK_TOP_ANA3, + sysctl_resource_clk_top_ana4 = SYSCTL_RESOURCE_CLK_TOP_ANA4, + sysctl_resource_clk_top_ref0 = SYSCTL_RESOURCE_CLK_TOP_REF0, + sysctl_resource_clk_top_ref1 = SYSCTL_RESOURCE_CLK_TOP_REF1, + sysctl_resource_clk_top_lin0 = SYSCTL_RESOURCE_CLK_TOP_LIN0, + sysctl_resource_clk_top_lin1 = SYSCTL_RESOURCE_CLK_TOP_LIN1, + sysctl_resource_clk_top_lin2 = SYSCTL_RESOURCE_CLK_TOP_LIN2, + sysctl_resource_clk_top_lin3 = SYSCTL_RESOURCE_CLK_TOP_LIN3, + sysctl_resource_clk_top_adc0 = SYSCTL_RESOURCE_CLK_TOP_ADC0, + sysctl_resource_clk_top_adc1 = SYSCTL_RESOURCE_CLK_TOP_ADC1, + sysctl_resource_clk_top_adc2 = SYSCTL_RESOURCE_CLK_TOP_ADC2, + sysctl_resource_clk_top_dac0 = SYSCTL_RESOURCE_CLK_TOP_DAC0, + sysctl_resource_clk_top_dac1 = SYSCTL_RESOURCE_CLK_TOP_DAC1, + + + sysctl_resource_linkable_start = 256, + sysctl_resource_ahbp = SYSCTL_RESOURCE_AHBP, + sysctl_resource_axis = SYSCTL_RESOURCE_AXIS, + sysctl_resource_axic = SYSCTL_RESOURCE_AXIC, + sysctl_resource_lmm0 = SYSCTL_RESOURCE_LMM0, + sysctl_resource_mchtmr0 = SYSCTL_RESOURCE_MCT0, + sysctl_resource_lmm1 = SYSCTL_RESOURCE_LMM1, + sysctl_resource_mchtmr1 = SYSCTL_RESOURCE_MCT1, + sysctl_resource_rom0 = SYSCTL_RESOURCE_ROM0, + sysctl_resource_ram0 = SYSCTL_RESOURCE_RAM0, + sysctl_resource_i2c0 = SYSCTL_RESOURCE_I2C0, + sysctl_resource_i2c1 = SYSCTL_RESOURCE_I2C1, + sysctl_resource_i2c2 = SYSCTL_RESOURCE_I2C2, + sysctl_resource_i2c3 = SYSCTL_RESOURCE_I2C3, + sysctl_resource_gptmr0 = SYSCTL_RESOURCE_TMR0, + sysctl_resource_gptmr1 = SYSCTL_RESOURCE_TMR1, + sysctl_resource_gptmr2 = SYSCTL_RESOURCE_TMR2, + sysctl_resource_gptmr3 = SYSCTL_RESOURCE_TMR3, + sysctl_resource_gpio = SYSCTL_RESOURCE_GPIO, + sysctl_resource_adc0 = SYSCTL_RESOURCE_ADC0, + sysctl_resource_adc1 = SYSCTL_RESOURCE_ADC1, + sysctl_resource_adc2 = SYSCTL_RESOURCE_ADC2, + sysctl_resource_dac0 = SYSCTL_RESOURCE_DAC0, + sysctl_resource_dac1 = SYSCTL_RESOURCE_DAC1, + sysctl_resource_acmp = SYSCTL_RESOURCE_ACMP, + sysctl_resource_spi0 = SYSCTL_RESOURCE_SPI0, + sysctl_resource_spi1 = SYSCTL_RESOURCE_SPI1, + sysctl_resource_spi2 = SYSCTL_RESOURCE_SPI2, + sysctl_resource_spi3 = SYSCTL_RESOURCE_SPI3, + sysctl_resource_sdm0 = SYSCTL_RESOURCE_SDM0, + sysctl_resource_uart0 = SYSCTL_RESOURCE_URT0, + sysctl_resource_uart1 = SYSCTL_RESOURCE_URT1, + sysctl_resource_uart2 = SYSCTL_RESOURCE_URT2, + sysctl_resource_uart3 = SYSCTL_RESOURCE_URT3, + sysctl_resource_uart4 = SYSCTL_RESOURCE_URT4, + sysctl_resource_uart5 = SYSCTL_RESOURCE_URT5, + sysctl_resource_uart6 = SYSCTL_RESOURCE_URT6, + sysctl_resource_uart7 = SYSCTL_RESOURCE_URT7, + sysctl_resource_lin0 = SYSCTL_RESOURCE_LIN0, + sysctl_resource_lin1 = SYSCTL_RESOURCE_LIN1, + sysctl_resource_lin2 = SYSCTL_RESOURCE_LIN2, + sysctl_resource_lin3 = SYSCTL_RESOURCE_LIN3, + sysctl_resource_ptpc = SYSCTL_RESOURCE_PTPC, + sysctl_resource_can0 = SYSCTL_RESOURCE_CAN0, + sysctl_resource_can1 = SYSCTL_RESOURCE_CAN1, + sysctl_resource_can2 = SYSCTL_RESOURCE_CAN2, + sysctl_resource_can3 = SYSCTL_RESOURCE_CAN3, + sysctl_resource_wdg0 = SYSCTL_RESOURCE_WDG0, + sysctl_resource_wdg1 = SYSCTL_RESOURCE_WDG1, + sysctl_resource_mbx0 = SYSCTL_RESOURCE_MBX0, + sysctl_resource_mbx1 = SYSCTL_RESOURCE_MBX1, + sysctl_resource_crc0 = SYSCTL_RESOURCE_CRC0, + sysctl_resource_mot0 = SYSCTL_RESOURCE_MOT0, + sysctl_resource_mot1 = SYSCTL_RESOURCE_MOT1, + sysctl_resource_mot2 = SYSCTL_RESOURCE_MOT2, + sysctl_resource_mot3 = SYSCTL_RESOURCE_MOT3, + sysctl_resource_msyn = SYSCTL_RESOURCE_MSYN, + sysctl_resource_xpi0 = SYSCTL_RESOURCE_XPI0, + sysctl_resource_dma0 = SYSCTL_RESOURCE_HDMA, + sysctl_resource_dma1 = SYSCTL_RESOURCE_XDMA, + sysctl_resource_kman = SYSCTL_RESOURCE_KMAN, + sysctl_resource_sdp0 = SYSCTL_RESOURCE_SDP0, + sysctl_resource_rng0 = SYSCTL_RESOURCE_RNG0, + sysctl_resource_tsns = SYSCTL_RESOURCE_TSNS, + sysctl_resource_usb0 = SYSCTL_RESOURCE_USB0, + sysctl_resource_ref0 = SYSCTL_RESOURCE_REF0, + sysctl_resource_ref1 = SYSCTL_RESOURCE_REF1, + sysctl_resource_linkable_end, + sysctl_resource_end = sysctl_resource_linkable_end, +} sysctl_resource_t; + +/** + * @brief Resource modes + */ +typedef enum { + sysctl_resource_mode_auto = 0, /*!< Resource clock is automatically managed by system request */ + sysctl_resource_mode_force_on, /*!< Force the resource clock on */ + sysctl_resource_mode_force_off, /*!< Force the resource clock off */ +} sysctl_resource_mode_t; + +/** + * @brief Clock nodes + */ +typedef enum { + clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0, + clock_node_mchtmr1 = SYSCTL_CLOCK_CLK_TOP_MCT1, + clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0, + clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0, + clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1, + clock_node_gptmr2 = SYSCTL_CLOCK_CLK_TOP_TMR2, + clock_node_gptmr3 = SYSCTL_CLOCK_CLK_TOP_TMR3, + clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0, + clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1, + clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2, + clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3, + clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4, + clock_node_uart5 = SYSCTL_CLOCK_CLK_TOP_URT5, + clock_node_uart6 = SYSCTL_CLOCK_CLK_TOP_URT6, + clock_node_uart7 = SYSCTL_CLOCK_CLK_TOP_URT7, + clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0, + clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1, + clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2, + clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3, + clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0, + clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1, + clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2, + clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3, + clock_node_can0 = SYSCTL_CLOCK_CLK_TOP_CAN0, + clock_node_can1 = SYSCTL_CLOCK_CLK_TOP_CAN1, + clock_node_can2 = SYSCTL_CLOCK_CLK_TOP_CAN2, + clock_node_can3 = SYSCTL_CLOCK_CLK_TOP_CAN3, + clock_node_ptpc = SYSCTL_CLOCK_CLK_TOP_PTPC, + clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0, + clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1, + clock_node_ana2 = SYSCTL_CLOCK_CLK_TOP_ANA2, + clock_node_ana3 = SYSCTL_CLOCK_CLK_TOP_ANA3, + clock_node_ana4 = SYSCTL_CLOCK_CLK_TOP_ANA4, + clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0, + clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1, + clock_node_lin0 = SYSCTL_CLOCK_CLK_TOP_LIN0, + clock_node_lin1 = SYSCTL_CLOCK_CLK_TOP_LIN1, + clock_node_lin2 = SYSCTL_CLOCK_CLK_TOP_LIN2, + clock_node_lin3 = SYSCTL_CLOCK_CLK_TOP_LIN3, + + clock_node_adc_start, + clock_node_adc0 = clock_node_adc_start, + clock_node_adc1, + clock_node_adc2, + clock_node_adc3, + + clock_node_dac_start, + clock_node_dac0 = clock_node_dac_start, + clock_node_dac1, + clock_node_end, + + clock_node_core_start = 0xfc, + clock_node_cpu0 = clock_node_core_start, + clock_node_cpu1 = clock_node_cpu0, + clock_node_axi, + clock_node_ahb, +} clock_node_t; + +/** + * @brief General clock sources + */ +typedef enum { + clock_source_osc0_clk0 = 0, + clock_source_pll0_clk0 = 1, + clock_source_pll0_clk1 = 2, + clock_source_pll0_clk2 = 3, + clock_source_pll1_clk0 = 4, + clock_source_pll1_clk1 = 5, + clock_source_pll2_clk0 = 6, + clock_source_pll2_clk1 = 7, + clock_source_general_source_end, +} clock_source_t; + +/** + * @brief ADC clock sources + */ +typedef enum { + clock_source_adc_ana_clock = 0, + clock_source_adc_ahb_clock = 1, + clock_source_adc_clk_end, +} clock_source_adc_t; + +/** + * @brief DAC clock sources + */ +typedef enum { + clock_source_dac_ana_clock = 0, + clock_source_dac_ahb_clock = 1, + clock_source_dac_clk_end, +} clock_source_dac_t; + +/** + * @brief CPU low power mode + */ +typedef enum { + cpu_lp_mode_gate_cpu_clock = 0, + cpu_lp_mode_trigger_system_lp = 0x1, + cpu_lp_mode_ungate_cpu_clock = 0x2, +} cpu_lp_mode_t; + +/** + * @brief Monitor targets + */ +/* Monitor Target types */ +typedef enum { + monitor_target_clk_32k = 0, + monitor_target_clk_irc24m = 1, + monitor_target_clk_xtal_24m = 2, + monitor_target_clk_usb0_phy = 3, + monitor_target_clk_usb1_phy = 4, + monitor_target_clk0_osc0 = 8, + monitor_target_clk0_pll0 = 9, + monitor_target_clk1_pll0 = 10, + monitor_target_clk2_pll0 = 11, + monitor_target_clk0_pll1 = 12, + monitor_target_clk1_pll1 = 13, + monitor_target_clk0_pll2 = 14, + monitor_target_clk1_pll2 = 15, + monitor_target_clk_top_cpu0 = 128, + monitor_target_clk_top_mchtmr0 = 129, + monitor_target_clk_top_mchtmr1 = 130, + monitor_target_clk_top_xpi0 = 131, + monitor_target_clk_top_gptmr0 = 132, + monitor_target_clk_top_gptmr1 = 133, + monitor_target_clk_top_gptmr2 = 134, + monitor_target_clk_top_gptmr3 = 135, + monitor_target_clk_top_uart0 = 136, + monitor_target_clk_top_uart1 = 137, + monitor_target_clk_top_uart2 = 138, + monitor_target_clk_top_uart3 = 139, + monitor_target_clk_top_uart4 = 140, + monitor_target_clk_top_uart5 = 141, + monitor_target_clk_top_uart6 = 142, + monitor_target_clk_top_uart7 = 143, + monitor_target_clk_top_i2c0 = 144, + monitor_target_clk_top_i2c1 = 145, + monitor_target_clk_top_i2c2 = 146, + monitor_target_clk_top_i2c3 = 147, + monitor_target_clk_top_spi0 = 148, + monitor_target_clk_top_spi1 = 149, + monitor_target_clk_top_spi2 = 150, + monitor_target_clk_top_spi3 = 151, + monitor_target_clk_top_can0 = 152, + monitor_target_clk_top_can1 = 153, + monitor_target_clk_top_can2 = 154, + monitor_target_clk_top_can3 = 155, + monitor_target_clk_top_ptpc = 156, + monitor_target_clk_top_ana0 = 157, + monitor_target_clk_top_ana1 = 158, + monitor_target_clk_top_ana2 = 159, + monitor_target_clk_top_ana3 = 160, + monitor_target_clk_top_ana4 = 161, + monitor_target_clk_top_ref0 = 162, + monitor_target_clk_top_ref1 = 163, + monitor_target_clk_top_lin0 = 164, + monitor_target_clk_top_lin1 = 165, + monitor_target_clk_top_lin2 = 166, + monitor_target_clk_top_lin3 = 167, +} monitor_target_t; + +/** + * @brief Monitor work mode + */ +typedef enum { + monitor_work_mode_compare = 0, + monitor_work_mode_record = 1, +} monitor_work_mode_t; + +/** + * @brief Monitor accuracy + */ +typedef enum { + monitor_accuracy_1khz = 0, + monitor_accuracy_1hz = 1, +} monitor_accuracy_t; + +/** + * @brief Monitor reference clock source + */ +typedef enum { + monitor_reference_32khz = 0, + monitor_reference_24mhz = 1, +} monitor_reference_t; + +typedef enum { + cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, + cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, + cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, + cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, +} cpu_event_flag_mask_t; + +/** + * @brief Monitor config + */ +typedef struct monitor_config { + uint8_t divide_by; /**< Divider to be used for OBS output to pads */ + monitor_work_mode_t mode; /**< Monitor work mode */ + monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ + monitor_reference_t reference; /**< Monitor reference clock source */ + monitor_target_t target; /**< Monitor target */ + bool start_measure; /**< Start flag */ + bool enable_output; /**< Enable output to pads if true */ + uint32_t high_limit; /**< Maximum frequency at compare mode */ + uint32_t low_limit; /**< Minimum frequency at compare mode */ +} monitor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Check if monitor result is valid + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * + * @return true if it is valid + */ +static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); +} + +/** + * @brief Get target monitor instance result + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return value of monitor result measured + */ +static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { + } + return ptr->MONITOR[monitor_index].CURRENT; +} + +/** + * @brief Set work mode for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record + */ +static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) +{ + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | + (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); +} + +/** + * @brief Set minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement high limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set frequency limit for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit_high measurement high limit + * @param[in] limit_low measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, + uint8_t monitor_index, + uint32_t limit_high, + uint32_t limit_low) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); + return status_success; +} + +/** + * @brief Get maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current high limit value + */ +static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); +} + +/** + * @brief Get minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current low limit value + */ +static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); +} + +/** + * @brief Measure specific target frequency + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] target monitor target to be measured + * @param[in] enable_output enable clock obs output + * @return frequency of monitor target measured + */ +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output); + +/** + * @brief Link current CPU core its own group + * + * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; +} + +/** + * @brief Unlink current CPU core with its own group + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; +} + +/** + * @brief Check if any resource is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any resource is busy + */ +static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; +} + +/** + * @brief Check if specific target is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return true if target resource is busy + */ +static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; +} + +/** + * @brief Set target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @param[in] mode target resource mode + */ +static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource, + sysctl_resource_mode_t mode) +{ + ptr->RESOURCE[resource] = + (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | + SYSCTL_RESOURCE_MODE_SET(mode); +} + +/** + * @brief Disable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].CLEAR = mask; +} + +/** + * @brief Disable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Disable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_clear_cpu_lp_retention_with_mask(ptr, 1, mask); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].SET = mask; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Enable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t value) +{ + ptr->RETENTION[cpu_index].VALUE = value; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) +{ + sysctl_set_cpu_lp_retention(ptr, 0, value); +} + +/** + * @brief Enable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu1_lp_retention(SYSCTL_Type *ptr, uint32_t value) +{ + sysctl_set_cpu_lp_retention(ptr, 1, value); +} + +/** + * @brief Retain target domain for specific CPU + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, + uint8_t cpu_index, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + uint8_t set_mask = 0x1; + if (domain < sysctl_retention_domain_xtal24m) { + set_mask = retain_mem ? 0x3 : 0x1; + } + ptr->RETENTION[cpu_index].SET = (set_mask << domain); +} + +/** + * @brief Retain target domain for specific CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); +} + +/** + * @brief Retain target domain for specific CPU + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu1_lp_retain_domain(SYSCTL_Type *ptr, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + sysctl_set_cpu_lp_retain_domain(ptr, 1, domain, retain_mem); +} + +/** + * @brief Check if cpu clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_cpu_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK_CPU[0] & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK; +} + +/** + * @brief Check if any clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; +} + +/** + * @brief Check if target clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + * @return true if target clock is busy + */ +static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, uint32_t clock) +{ + return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; +} + +/** + * @brief Set clock preset + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] preset preset + */ +static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) +{ + ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); +} + +/** + * @brief Check if target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken wakeup reset + */ +static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken reset + */ +static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain for all reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Get target CPU wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; +} + +/** + * @brief Get target CPU0 wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) +{ + return sysctl_get_wakeup_source_status(ptr, 0, status_index); +} + +/** + * @brief Get target CPU1 wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_cpu1_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) +{ + return sysctl_get_wakeup_source_status(ptr, 1, status_index); +} + +/** + * @brief Check wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t status_index, + uint32_t mask) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; +} + +/** + * @brief Check CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t status_index, + uint32_t mask) +{ + return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); +} + +/** + * @brief Check CPU1 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_cpu1_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t status_index, + uint32_t mask) +{ + return sysctl_check_wakeup_source_status_with_mask(ptr, 1, status_index, mask); +} + +/** + * @brief Enable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Enable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Enable CPU1 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[1].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Disable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; +} + +/** + * @brief Disable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); +} + + +/** + * @brief Disable CPU1 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + sysctl_disable_wakeup_source_with_mask(ptr, 1, enable_index, mask); +} + +/** + * @brief Disable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be disabled as wakeup source + */ +static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); +} + +/** + * @brief Disable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be disabled as wakeup source + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) +{ + sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); +} + + +/** + * @brief Disable CPU1 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be disabled as wakeup source + */ +static inline void sysctl_disable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) +{ + sysctl_disable_wakeup_source_with_irq(ptr, 1, irq_num); +} + +/** + * @brief Enable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); +} + +/** + * @brief Enable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) +{ + sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); +} + +/** + * @brief Enable CPU1 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) +{ + sysctl_enable_wakeup_source_with_irq(ptr, 1, irq_num); +} + +/** + * @brief Lock CPU gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t gpr_mask) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); +} + + +/** + * @brief Lock CPU0 gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) +{ + sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); +} + +/** + * @brief Lock CPU1 gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) +{ + sysctl_cpu_lock_gpr_with_mask(ptr, 1, gpr_mask); +} + +/** + * @brief Lock CPU lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + */ +static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; +} + +/** + * @brief Lock CPU0 lock + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) +{ + sysctl_cpu_lock(ptr, 0); +} + +/** + * @brief Lock CPU1 lock + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_cpu1_lock(SYSCTL_Type *ptr) +{ + sysctl_cpu_lock(ptr, 1); +} + +/** + * @brief Set CPU low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) +{ + ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); +} + +/** + * @brief Set CPU0 low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) +{ + sysctl_set_cpu_lp_mode(ptr, 0, mode); +} + +/** + * @brief Set CPU1 low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu1_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) +{ + sysctl_set_cpu_lp_mode(ptr, 1, mode); +} + +/** + * @brief Clear CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) +{ + ptr->CPU[cpu_index].LP |= + ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); +} + +/** + * @brief Clear CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) +{ + sysctl_clear_cpu_flags(ptr, 0, flags); +} + +/** + * @brief Clear CPU1 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu1_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) +{ + sysctl_clear_cpu_flags(ptr, 1, flags); +} + +/** + * @brief Get CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + return ptr->CPU[cpu_index].LP & + (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); +} + +/** + * @brief Get CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) +{ + return sysctl_get_cpu_flags(ptr, 0); +} + +/** + * @brief Get CPU1 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu1_flags(SYSCTL_Type *ptr) +{ + return sysctl_get_cpu_flags(ptr, 1); +} + +/** + * @brief Release cpu + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + */ +static inline void sysctl_release_cpu(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->CPU[cpu_index].LP &= ~SYSCTL_CPU_LP_HALT_MASK; +} + +/** + * @brief Release cpu1 + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_release_cpu1(SYSCTL_Type *ptr) +{ + sysctl_release_cpu(ptr, 1); +} + +/** + * @brief Check whether CPU is released or not + * + * @param [in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @retval true CPU is released + * @retval false CPU is on-hold + */ +static inline bool sysctl_is_cpu_released(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + return ((ptr->CPU[cpu_index].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U); +} + +/** + * @brief Check whether CPU1 is released or not + * + * @param [in] ptr SYSCTL_Type base address + * @retval true CPU1 is released + * @retval false CPU1 is on-hold + */ +static inline bool sysctl_is_cpu1_released(SYSCTL_Type *ptr) +{ + return sysctl_is_cpu_released(ptr, 1); +} + +/** + * @brief Config lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @param[in] divide_by clock frequency divider + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); + +/** + * @brief Configure CPU domain clock + * @param ptr SYSCTL base address + * @param source clock source to be used + * @param cpu_div CPU divider + * @param axi_sub_div AXI BUS divider based on divided CPU clock + * @param ahb_sub_div AHB BUS divider based on divided CPU clock + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, + clock_source_t source, + uint32_t cpu_div, + uint32_t axi_sub_div, + uint32_t ahb_sub_div); + +/** + * @brief Set ADC clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source); + + +/** + * @brief Set DAC clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source); + +/** + * @brief Enable group resource + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be modified + * @param[in] resource target resource to be added/removed from group + * @param[in] enable set true to add resource, remove otherwise + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t resource, + bool enable); +/** + * @brief Add resource to CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource resource to be added to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Remove resource from CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be removed to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Add resource to CPU1 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be added to CPU1 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Remove resource from CPU1 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be removed to CPU1 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Get default monitor config + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); + +/** + * @brief Initialize Monitor + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index Monitor instance to be initialized + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); + +/** + * @brief Save data to GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[in] data Pointer to data buffer + * @param[in] lock Set true to lock written GPR registers after setting + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); + +/** + * @brief Get data saved from GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[out] data Pointer of buffer to save data + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); + +/** + * @brief Set data to CPU1 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[in] data Pointer to data buffer + * @param[in] lock Set true to lock written GPR registers after setting + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); + +/** + * @brief Get data saved in CPU1 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[out] data Pointer of buffer to save data + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_get_cpu1_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); + +/** + * @brief Set entry point on CPU boot or wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu CPU index + * @param[in] entry Entry address for CPU + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry); + +/** + * @brief Set entry point on CPU0 wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] entry Entry address for CPU0 on its wakeup + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); + +/** + * @brief Set entry point on either CPU1 boot or wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] entry Entry address for CPU1 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_SYSCTL_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_regs.h new file mode 100644 index 00000000..309fca30 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_regs.h @@ -0,0 +1,1403 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SYSCTL_H +#define HPM_SYSCTL_H + +typedef struct { + __RW uint32_t RESOURCE[322]; /* 0x0 - 0x504: Resource control register for cpu0_core */ + __R uint8_t RESERVED0[760]; /* 0x508 - 0x7FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x800: Group setting */ + __RW uint32_t SET; /* 0x804: Group setting */ + __RW uint32_t CLEAR; /* 0x808: Group setting */ + __RW uint32_t TOGGLE; /* 0x80C: Group setting */ + } GROUP0[3]; + __R uint8_t RESERVED1[16]; /* 0x830 - 0x83F: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x840: Group setting */ + __RW uint32_t SET; /* 0x844: Group setting */ + __RW uint32_t CLEAR; /* 0x848: Group setting */ + __RW uint32_t TOGGLE; /* 0x84C: Group setting */ + } GROUP1[3]; + __R uint8_t RESERVED2[144]; /* 0x870 - 0x8FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ + __RW uint32_t SET; /* 0x904: Affiliate of Group */ + __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ + __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ + } AFFILIATE[2]; + struct { + __RW uint32_t VALUE; /* 0x920: Retention Contol */ + __RW uint32_t SET; /* 0x924: Retention Contol */ + __RW uint32_t CLEAR; /* 0x928: Retention Contol */ + __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */ + } RETENTION[2]; + __R uint8_t RESERVED3[1728]; /* 0x940 - 0xFFF: Reserved */ + struct { + __RW uint32_t STATUS; /* 0x1000: Power Setting */ + __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ + __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ + __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ + } POWER[2]; + __R uint8_t RESERVED4[992]; /* 0x1020 - 0x13FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ + __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ + __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ + __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ + } RESET[3]; + __R uint8_t RESERVED5[976]; /* 0x1430 - 0x17FF: Reserved */ + __RW uint32_t CLOCK_CPU[1]; /* 0x1800: Clock setting */ + __RW uint32_t CLOCK[39]; /* 0x1804 - 0x189C: Clock setting */ + __R uint8_t RESERVED6[864]; /* 0x18A0 - 0x1BFF: Reserved */ + __RW uint32_t ADCCLK[3]; /* 0x1C00 - 0x1C08: Clock setting */ + __RW uint32_t DACCLK[2]; /* 0x1C0C - 0x1C10: Clock setting */ + __R uint8_t RESERVED7[1004]; /* 0x1C14 - 0x1FFF: Reserved */ + __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ + __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ + __R uint32_t CURRENT; /* 0x2404: Clock measure result */ + __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ + __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ + __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ + } MONITOR[4]; + __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ + struct { + __RW uint32_t LP; /* 0x2800: CPU0 LP control */ + __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ + __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ + __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ + __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ + __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ + __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ + } CPU[2]; +} SYSCTL_Type; + + +/* Bitfield definition for register array: RESOURCE */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any nodes + * 1: any of nodes is changing status + */ +#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) +#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: no change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) +#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) + +/* + * MODE (RW) + * + * resource work mode + * 0:auto turn on and off as system required(recommended) + * 1:always on + * 2:always off + * 3:reserved + */ +#define SYSCTL_RESOURCE_MODE_MASK (0x3U) +#define SYSCTL_RESOURCE_MODE_SHIFT (0U) +#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) +#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: VALUE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) +#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: SET */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: add periphera into this group，periphera is needed + */ +#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) +#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: CLEAR */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: delete periphera in this group，periphera is not needed + */ +#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) +#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: TOGGLE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: toggle the result that whether periphera is needed before + */ +#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) +#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP1: VALUE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP1_VALUE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP1_VALUE_LINK_SHIFT (0U) +#define SYSCTL_GROUP1_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_VALUE_LINK_SHIFT) & SYSCTL_GROUP1_VALUE_LINK_MASK) +#define SYSCTL_GROUP1_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_VALUE_LINK_MASK) >> SYSCTL_GROUP1_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP1: SET */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: add periphera into this group，periphera is needed + */ +#define SYSCTL_GROUP1_SET_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP1_SET_LINK_SHIFT (0U) +#define SYSCTL_GROUP1_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_SET_LINK_SHIFT) & SYSCTL_GROUP1_SET_LINK_MASK) +#define SYSCTL_GROUP1_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_SET_LINK_MASK) >> SYSCTL_GROUP1_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP1: CLEAR */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: delete periphera in this group，periphera is not needed + */ +#define SYSCTL_GROUP1_CLEAR_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP1_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_GROUP1_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_CLEAR_LINK_SHIFT) & SYSCTL_GROUP1_CLEAR_LINK_MASK) +#define SYSCTL_GROUP1_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_CLEAR_LINK_MASK) >> SYSCTL_GROUP1_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP1: TOGGLE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: toggle the result that whether periphera is needed before + */ +#define SYSCTL_GROUP1_TOGGLE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP1_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_GROUP1_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) +#define SYSCTL_GROUP1_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) >> SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: VALUE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * bit0: cpu0 depends on group0 + * bit1: cpu0 depends on group1 + * bit2: cpu0 depends on group2 + * bit3: cpu0 depends on group3 + */ +#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) +#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: SET */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0，each bit represents a group + * 0: no effect + * 1: the group is assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) +#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: the group is not assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) +#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: toggle the result that whether the group is assigned to CPU0 before + */ +#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: VALUE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * bit00: soc_mem is kept on while cpu0 stop + * bit01: soc_ctx is kept on while cpu0 stop + * bit02: cpu0_mem is kept on while cpu0 stop + * bit03: cpu0_ctx is kept on while cpu0 stop + * bit04: cpu1_mem is kept on while cpu0 stop + * bit05: cpu1_ctx is kept on while cpu0 stop + * bit06: xtal_hold is kept on while cpu0 stop + * bit07: pll0_hold is kept on while cpu0 stop + * bit08: pll1_hold is kept on while cpu0 stop + * bit09: pll2_hold is kept on while cpu0 stop + */ +#define SYSCTL_RETENTION_VALUE_LINK_MASK (0x3FFU) +#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) +#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: SET */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: keep + */ +#define SYSCTL_RETENTION_SET_LINK_MASK (0x3FFU) +#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) +#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: CLEAR */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: no keep + */ +#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x3FFU) +#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) +#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: TOGGLE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: toggle the result that whether the resource is kept on while CPU0 stop before + */ +#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x3FFU) +#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) +#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array POWER: STATUS */ +/* + * FLAG (RW) + * + * flag represents power cycle happened from last clear of this bit + * 0: power domain did not edurance power cycle since last clear of this bit + * 1: power domain enduranced power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) +#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) +#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) +#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup power cycle happened from last clear of this bit + * 0: power domain did not edurance wakeup power cycle since last clear of this bit + * 1: power domain enduranced wakeup power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) + +/* + * LF_DISABLE (RO) + * + * low fanout power switch disable + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) + +/* + * LF_ACK (RO) + * + * low fanout power switch feedback + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) +#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) +#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) + +/* Bitfield definition for register of struct array POWER: LF_WAIT */ +/* + * WAIT (RW) + * + * wait time for low fan out power switch turn on, default value is 255 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array POWER: OFF_WAIT */ +/* + * WAIT (RW) + * + * wait time for power switch turn off, default value is 15 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONTROL */ +/* + * FLAG (RW) + * + * flag represents reset happened from last clear of this bit + * 0: domain did not edurance reset cycle since last clear of this bit + * 1: domain enduranced reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) +#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup reset happened from last clear of this bit + * 0: domain did not edurance wakeup reset cycle since last clear of this bit + * 1: domain enduranced wakeup reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) + +/* + * HOLD (RW) + * + * perform reset and hold in reset, until ths bit cleared by software + * 0: reset is released for function + * 1: reset is assert and hold + */ +#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) +#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) +#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) +#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) + +/* + * RESET (RW) + * + * perform reset and release imediately + * 0: reset is released + * 1 reset is asserted and will release automaticly + */ +#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) +#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) +#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) +#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONFIG */ +/* + * PRE_WAIT (RW) + * + * wait cycle numbers before assert reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) + +/* + * RSTCLK_NUM (RW) + * + * reset clock number(must be even number) + * 0: 0 cycle + * 1: 0 cycles + * 2: 2 cycles + * 3: 2 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) + +/* + * POST_WAIT (RW) + * + * time guard band for reset release + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: COUNTER */ +/* + * COUNTER (RW) + * + * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) +#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) +#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) +#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) + +/* Bitfield definition for register array: CLOCK_CPU */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_CPU_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_CPU_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK) >> SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_CPU_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_CPU_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_LOC_BUSY_MASK) >> SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_CPU_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_CPU_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_CPU_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) +#define SYSCTL_CLOCK_CPU_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) >> SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) + +/* + * SUB1_DIV (RW) + * + * ahb bus divider, the bus clock is generated by cpu_clock/div + * 0: divider by 1 + * 1: divider by 2 + * … + */ +#define SYSCTL_CLOCK_CPU_SUB1_DIV_MASK (0xF00000UL) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT (20U) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) + +/* + * SUB0_DIV (RW) + * + * axi bus divider, the bus clock is generated by cpu_clock/div + * 0: divider by 1 + * 1: divider by 2 + * … + */ +#define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xF0000UL) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16U) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll0_clk1 + * 3:pll0_clk2 + * 4:pll1_clk0 + * 5:pll1_clk1 + * 6:pll2_clk0 + * 7:pll2_clk1 + */ +#define SYSCTL_CLOCK_CPU_MUX_MASK (0x700U) +#define SYSCTL_CLOCK_CPU_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_CPU_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_MUX_SHIFT) & SYSCTL_CLOCK_CPU_MUX_MASK) +#define SYSCTL_CLOCK_CPU_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_MUX_MASK) >> SYSCTL_CLOCK_CPU_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_CPU_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_CPU_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_CPU_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_DIV_SHIFT) & SYSCTL_CLOCK_CPU_DIV_MASK) +#define SYSCTL_CLOCK_CPU_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_DIV_MASK) >> SYSCTL_CLOCK_CPU_DIV_SHIFT) + +/* Bitfield definition for register array: CLOCK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) +#define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll0_clk1 + * 3:pll0_clk2 + * 4:pll1_clk0 + * 5:pll1_clk1 + * 6:pll2_clk0 + * 7:pll2_clk1 + */ +#define SYSCTL_CLOCK_MUX_MASK (0x700U) +#define SYSCTL_CLOCK_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) +#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) +#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) + +/* Bitfield definition for register array: ADCCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) +#define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ana clock + * 1: ahb clock + */ +#define SYSCTL_ADCCLK_MUX_MASK (0x100U) +#define SYSCTL_ADCCLK_MUX_SHIFT (8U) +#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) +#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) + +/* Bitfield definition for register array: DACCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_DACCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_DACCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_DACCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_GLB_BUSY_MASK) >> SYSCTL_DACCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_DACCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_DACCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_DACCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_LOC_BUSY_MASK) >> SYSCTL_DACCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_DACCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_DACCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_DACCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_PRESERVE_SHIFT) & SYSCTL_DACCLK_PRESERVE_MASK) +#define SYSCTL_DACCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_PRESERVE_MASK) >> SYSCTL_DACCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ana clock + * 1: ahb clock + */ +#define SYSCTL_DACCLK_MUX_MASK (0x100U) +#define SYSCTL_DACCLK_MUX_SHIFT (8U) +#define SYSCTL_DACCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_MUX_SHIFT) & SYSCTL_DACCLK_MUX_MASK) +#define SYSCTL_DACCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_MUX_MASK) >> SYSCTL_DACCLK_MUX_SHIFT) + +/* Bitfield definition for register: GLOBAL00 */ +/* + * MUX (RW) + * + * global clock override request + * bit0: override to preset0 + * bit1: override to preset1 + * bit2: override to preset2 + * bit3: override to preset3 + */ +#define SYSCTL_GLOBAL00_MUX_MASK (0xFU) +#define SYSCTL_GLOBAL00_MUX_SHIFT (0U) +#define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) +#define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CONTROL */ +/* + * VALID (RW) + * + * result is ready for read + * 0: not ready + * 1: result is ready + */ +#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) +#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) +#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) +#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) + +/* + * DIV_BUSY (RO) + * + * divider is applying new setting + */ +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) + +/* + * OUTEN (RW) + * + * enable clock output + */ +#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) +#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) + +/* + * DIV (RW) + * + * output divider + */ +#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) +#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) +#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) + +/* + * HIGH (RW) + * + * clock frequency higher than upper limit + */ +#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) +#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) + +/* + * LOW (RW) + * + * clock frequency lower than lower limit + */ +#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) +#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) +#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) +#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) + +/* + * START (RW) + * + * start measurement + */ +#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) +#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) +#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) +#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) + +/* + * MODE (RW) + * + * work mode, + * 0: register value will be compared to measurement + * 1: upper and lower value will be recordered in register + */ +#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) +#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) +#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) +#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) + +/* + * ACCURACY (RW) + * + * measurement accuracy, + * 0: resolution is 1kHz + * 1: resolution is 1Hz + */ +#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) + +/* + * REFERENCE (RW) + * + * refrence clock selection, + * 0: 32k + * 1: 24M + */ +#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) + +/* + * SELECTION (RW) + * + * clock measurement selection + * 0: clk_32k + * 1: clk_irc24m + * 2: clk_xtal_24m + * 3: clk_usb0_phy + * 8: clk0_osc0 + * 9: clk0_pll0 + * 10: clk1_pll0 + * 11: clk2_pll0 + * 12: clk0_pll1 + * 13: clk1_pll1 + * 14: clk0_pll2 + * 15: clk1_pll2 + * 128: clk_top_cpu0 + * 129: clk_top_mct0 + * 130: clk_top_mct1 + * 131: clk_top_xpi0 + * 132: clk_top_tmr0 + * 133: clk_top_tmr1 + * 134: clk_top_tmr2 + * 135: clk_top_tmr3 + * 136: clk_top_urt0 + * 137: clk_top_urt1 + * 138: clk_top_urt2 + * 139: clk_top_urt3 + * 140: clk_top_urt4 + * 141: clk_top_urt5 + * 142: clk_top_urt6 + * 143: clk_top_urt7 + * 144: clk_top_i2c0 + * 145: clk_top_i2c1 + * 146: clk_top_i2c2 + * 147: clk_top_i2c3 + * 148: clk_top_spi0 + * 149: clk_top_spi1 + * 150: clk_top_spi2 + * 151: clk_top_spi3 + * 152: clk_top_can0 + * 153: clk_top_can1 + * 154: clk_top_can2 + * 155: clk_top_can3 + * 156: clk_top_ptpc + * 157: clk_top_ana0 + * 158: clk_top_ana1 + * 159: clk_top_ana2 + * 160: clk_top_ana3 + * 161: clk_top_ana4 + * 162: clk_top_ref0 + * 163: clk_top_ref1 + * 164: clk_top_lin0 + * 165: clk_top_lin1 + * 166: clk_top_lin2 + * 167: clk_top_lin3 + */ +#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) +#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CURRENT */ +/* + * FREQUENCY (RO) + * + * self updating measure result + */ +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ +/* + * FREQUENCY (RW) + * + * lower frequency + */ +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ +/* + * FREQUENCY (RW) + * + * upper frequency + */ +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array CPU: LP */ +/* + * WAKE_CNT (RW) + * + * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + */ +#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) +#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) +#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) +#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) + +/* + * HALT (RW) + * + * halt request for CPU0, + * 0: CPU0 will start to execute after reset or receive wakeup request + * 1: CPU0 will not start after reset, or wakeup after WFI + */ +#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) +#define SYSCTL_CPU_LP_HALT_SHIFT (16U) +#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) +#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) + +/* + * WAKE (RO) + * + * CPU0 is waking up + * 0: CPU0 wake up not asserted + * 1: CPU0 wake up asserted + */ +#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) +#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) +#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) + +/* + * EXEC (RO) + * + * CPU0 is executing + * 0: CPU0 is not executing + * 1: CPU0 is executing + */ +#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) +#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) +#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) + +/* + * WAKE_FLAG (RW) + * + * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit + * 0: CPU0 wakeup not happened + * 1: CPU0 wake up happened + */ +#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) +#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) + +/* + * SLEEP_FLAG (RW) + * + * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit + * 0: CPU0 sleep not happened + * 1: CPU0 sleep happened + */ +#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) +#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) + +/* + * RESET_FLAG (RW) + * + * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit + * 0: CPU0 reset not happened + * 1: CPU0 reset happened + */ +#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) +#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) +#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) +#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) + +/* + * MODE (RW) + * + * Low power mode, system behavior after WFI + * 00: CPU clock stop after WFI + * 01: System enter low power mode after WFI + * 10: Keep running after WFI + * 11: reserved + */ +#define SYSCTL_CPU_LP_MODE_MASK (0x3U) +#define SYSCTL_CPU_LP_MODE_SHIFT (0U) +#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) +#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) + +/* Bitfield definition for register of struct array CPU: LOCK */ +/* + * GPR (RW) + * + * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + */ +#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) +#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) +#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) +#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) + +/* + * LOCK (RW) + * + * Lock bit for CPU_LOCK + */ +#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) +#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) +#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) +#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) + +/* Bitfield definition for register of struct array CPU: GPR0 */ +/* + * GPR (RW) + * + * register for software to handle resume, can save resume address or status + */ +#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) +#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) +#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) + +/* Bitfield definition for register of struct array CPU: STATUS0 */ +/* + * STATUS (RO) + * + * IRQ values + */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register of struct array CPU: ENABLE0 */ +/* + * ENABLE (RW) + * + * IRQ wakeup enable + */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) + + + +/* RESOURCE register group index macro definition */ +#define SYSCTL_RESOURCE_CPU0 (0UL) +#define SYSCTL_RESOURCE_CPX0 (1UL) +#define SYSCTL_RESOURCE_CPU1 (8UL) +#define SYSCTL_RESOURCE_CPX1 (9UL) +#define SYSCTL_RESOURCE_POW_CPU0 (21UL) +#define SYSCTL_RESOURCE_POW_CPU1 (22UL) +#define SYSCTL_RESOURCE_RST_SOC (23UL) +#define SYSCTL_RESOURCE_RST_CPU0 (24UL) +#define SYSCTL_RESOURCE_RST_CPU1 (25UL) +#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (36UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (37UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (38UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (39UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL2 (40UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (41UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (42UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (43UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (44UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (45UL) +#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) +#define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) +#define SYSCTL_RESOURCE_CLK_TOP_MCT1 (66UL) +#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (67UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR0 (68UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR1 (69UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR2 (70UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR3 (71UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT0 (72UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT1 (73UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT2 (74UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT3 (75UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT4 (76UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT5 (77UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT6 (78UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT7 (79UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (80UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (81UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (82UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (83UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (84UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (85UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (86UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (87UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (88UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (89UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN2 (90UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN3 (91UL) +#define SYSCTL_RESOURCE_CLK_TOP_PTPC (92UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (93UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (94UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (95UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (96UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA4 (97UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF0 (98UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF1 (99UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN0 (100UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN1 (101UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN2 (102UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN3 (103UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (128UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (129UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC2 (130UL) +#define SYSCTL_RESOURCE_CLK_TOP_DAC0 (131UL) +#define SYSCTL_RESOURCE_CLK_TOP_DAC1 (132UL) +#define SYSCTL_RESOURCE_AHBP (256UL) +#define SYSCTL_RESOURCE_AXIS (257UL) +#define SYSCTL_RESOURCE_AXIC (258UL) +#define SYSCTL_RESOURCE_LMM0 (259UL) +#define SYSCTL_RESOURCE_MCT0 (260UL) +#define SYSCTL_RESOURCE_LMM1 (261UL) +#define SYSCTL_RESOURCE_MCT1 (262UL) +#define SYSCTL_RESOURCE_ROM0 (263UL) +#define SYSCTL_RESOURCE_RAM0 (264UL) +#define SYSCTL_RESOURCE_I2C0 (265UL) +#define SYSCTL_RESOURCE_I2C1 (266UL) +#define SYSCTL_RESOURCE_I2C2 (267UL) +#define SYSCTL_RESOURCE_I2C3 (268UL) +#define SYSCTL_RESOURCE_TMR0 (269UL) +#define SYSCTL_RESOURCE_TMR1 (270UL) +#define SYSCTL_RESOURCE_TMR2 (271UL) +#define SYSCTL_RESOURCE_TMR3 (272UL) +#define SYSCTL_RESOURCE_GPIO (273UL) +#define SYSCTL_RESOURCE_ADC0 (274UL) +#define SYSCTL_RESOURCE_ADC1 (275UL) +#define SYSCTL_RESOURCE_ADC2 (276UL) +#define SYSCTL_RESOURCE_DAC0 (277UL) +#define SYSCTL_RESOURCE_DAC1 (278UL) +#define SYSCTL_RESOURCE_ACMP (279UL) +#define SYSCTL_RESOURCE_SPI0 (280UL) +#define SYSCTL_RESOURCE_SPI1 (281UL) +#define SYSCTL_RESOURCE_SPI2 (282UL) +#define SYSCTL_RESOURCE_SPI3 (283UL) +#define SYSCTL_RESOURCE_SDM0 (284UL) +#define SYSCTL_RESOURCE_URT0 (285UL) +#define SYSCTL_RESOURCE_URT1 (286UL) +#define SYSCTL_RESOURCE_URT2 (287UL) +#define SYSCTL_RESOURCE_URT3 (288UL) +#define SYSCTL_RESOURCE_URT4 (289UL) +#define SYSCTL_RESOURCE_URT5 (290UL) +#define SYSCTL_RESOURCE_URT6 (291UL) +#define SYSCTL_RESOURCE_URT7 (292UL) +#define SYSCTL_RESOURCE_LIN0 (293UL) +#define SYSCTL_RESOURCE_LIN1 (294UL) +#define SYSCTL_RESOURCE_LIN2 (295UL) +#define SYSCTL_RESOURCE_LIN3 (296UL) +#define SYSCTL_RESOURCE_PTPC (297UL) +#define SYSCTL_RESOURCE_CAN0 (298UL) +#define SYSCTL_RESOURCE_CAN1 (299UL) +#define SYSCTL_RESOURCE_CAN2 (300UL) +#define SYSCTL_RESOURCE_CAN3 (301UL) +#define SYSCTL_RESOURCE_WDG0 (302UL) +#define SYSCTL_RESOURCE_WDG1 (303UL) +#define SYSCTL_RESOURCE_MBX0 (304UL) +#define SYSCTL_RESOURCE_MBX1 (305UL) +#define SYSCTL_RESOURCE_CRC0 (306UL) +#define SYSCTL_RESOURCE_MOT0 (307UL) +#define SYSCTL_RESOURCE_MOT1 (308UL) +#define SYSCTL_RESOURCE_MOT2 (309UL) +#define SYSCTL_RESOURCE_MOT3 (310UL) +#define SYSCTL_RESOURCE_MSYN (311UL) +#define SYSCTL_RESOURCE_XPI0 (312UL) +#define SYSCTL_RESOURCE_HDMA (313UL) +#define SYSCTL_RESOURCE_XDMA (314UL) +#define SYSCTL_RESOURCE_KMAN (315UL) +#define SYSCTL_RESOURCE_SDP0 (316UL) +#define SYSCTL_RESOURCE_RNG0 (317UL) +#define SYSCTL_RESOURCE_TSNS (318UL) +#define SYSCTL_RESOURCE_USB0 (319UL) +#define SYSCTL_RESOURCE_REF0 (320UL) +#define SYSCTL_RESOURCE_REF1 (321UL) + +/* GROUP0 register group index macro definition */ +#define SYSCTL_GROUP0_LINK0 (0UL) +#define SYSCTL_GROUP0_LINK1 (1UL) +#define SYSCTL_GROUP0_LINK2 (2UL) + +/* GROUP1 register group index macro definition */ +#define SYSCTL_GROUP1_LINK0 (0UL) +#define SYSCTL_GROUP1_LINK1 (1UL) +#define SYSCTL_GROUP1_LINK2 (2UL) + +/* AFFILIATE register group index macro definition */ +#define SYSCTL_AFFILIATE_CPU0 (0UL) +#define SYSCTL_AFFILIATE_CPU1 (1UL) + +/* RETENTION register group index macro definition */ +#define SYSCTL_RETENTION_CPU0 (0UL) +#define SYSCTL_RETENTION_CPU1 (1UL) + +/* POWER register group index macro definition */ +#define SYSCTL_POWER_CPU0 (0UL) +#define SYSCTL_POWER_CPU1 (1UL) + +/* RESET register group index macro definition */ +#define SYSCTL_RESET_SOC (0UL) +#define SYSCTL_RESET_CPU0 (1UL) +#define SYSCTL_RESET_CPU1 (2UL) + +/* CLOCK_CPU register group index macro definition */ +#define SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (0UL) + +/* CLOCK register group index macro definition */ +#define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL) +#define SYSCTL_CLOCK_CLK_TOP_MCT1 (1UL) +#define SYSCTL_CLOCK_CLK_TOP_XPI0 (2UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR0 (3UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR1 (4UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR2 (5UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR3 (6UL) +#define SYSCTL_CLOCK_CLK_TOP_URT0 (7UL) +#define SYSCTL_CLOCK_CLK_TOP_URT1 (8UL) +#define SYSCTL_CLOCK_CLK_TOP_URT2 (9UL) +#define SYSCTL_CLOCK_CLK_TOP_URT3 (10UL) +#define SYSCTL_CLOCK_CLK_TOP_URT4 (11UL) +#define SYSCTL_CLOCK_CLK_TOP_URT5 (12UL) +#define SYSCTL_CLOCK_CLK_TOP_URT6 (13UL) +#define SYSCTL_CLOCK_CLK_TOP_URT7 (14UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C0 (15UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C1 (16UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C2 (17UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C3 (18UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI0 (19UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI1 (20UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI2 (21UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI3 (22UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN0 (23UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN1 (24UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN2 (25UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN3 (26UL) +#define SYSCTL_CLOCK_CLK_TOP_PTPC (27UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA0 (28UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA1 (29UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA2 (30UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA3 (31UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA4 (32UL) +#define SYSCTL_CLOCK_CLK_TOP_REF0 (33UL) +#define SYSCTL_CLOCK_CLK_TOP_REF1 (34UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN0 (35UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN1 (36UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN2 (37UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN3 (38UL) + +/* ADCCLK register group index macro definition */ +#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL) + +/* DACCLK register group index macro definition */ +#define SYSCTL_DACCLK_CLK_TOP_DAC0 (0UL) +#define SYSCTL_DACCLK_CLK_TOP_DAC1 (1UL) + +/* MONITOR register group index macro definition */ +#define SYSCTL_MONITOR_SLICE0 (0UL) +#define SYSCTL_MONITOR_SLICE1 (1UL) +#define SYSCTL_MONITOR_SLICE2 (2UL) +#define SYSCTL_MONITOR_SLICE3 (3UL) + +/* GPR register group index macro definition */ +#define SYSCTL_CPU_GPR_GPR0 (0UL) +#define SYSCTL_CPU_GPR_GPR1 (1UL) +#define SYSCTL_CPU_GPR_GPR2 (2UL) +#define SYSCTL_CPU_GPR_GPR3 (3UL) +#define SYSCTL_CPU_GPR_GPR4 (4UL) +#define SYSCTL_CPU_GPR_GPR5 (5UL) +#define SYSCTL_CPU_GPR_GPR6 (6UL) +#define SYSCTL_CPU_GPR_GPR7 (7UL) +#define SYSCTL_CPU_GPR_GPR8 (8UL) +#define SYSCTL_CPU_GPR_GPR9 (9UL) +#define SYSCTL_CPU_GPR_GPR10 (10UL) +#define SYSCTL_CPU_GPR_GPR11 (11UL) +#define SYSCTL_CPU_GPR_GPR12 (12UL) +#define SYSCTL_CPU_GPR_GPR13 (13UL) + +/* WAKEUP_STATUS register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) + +/* WAKEUP_ENABLE register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) + +/* CPU register group index macro definition */ +#define SYSCTL_CPU_CPU0 (0UL) +#define SYSCTL_CPU_CPU1 (1UL) + + +#endif /* HPM_SYSCTL_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_trgm_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_trgm_regs.h new file mode 100644 index 00000000..cc1b2c58 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_trgm_regs.h @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TRGM_H +#define HPM_TRGM_H + +typedef struct { + __RW uint32_t FILTCFG[20]; /* 0x0 - 0x4C: Filter configure register */ + __R uint8_t RESERVED0[176]; /* 0x50 - 0xFF: Reserved */ + __RW uint32_t TRGOCFG[68]; /* 0x100 - 0x20C: Trigger manager output configure register */ + __R uint8_t RESERVED1[240]; /* 0x210 - 0x2FF: Reserved */ + __RW uint32_t DMACFG[4]; /* 0x300 - 0x30C: DMA request configure register */ + __R uint8_t RESERVED2[240]; /* 0x310 - 0x3FF: Reserved */ + __RW uint32_t GCR; /* 0x400: General Control Register */ +} TRGM_Type; + + +/* Bitfield definition for register array: FILTCFG */ +/* + * OUTINV (RW) + * + * 1- Filter will invert the output + * 0- Filter will not invert the output + */ +#define TRGM_FILTCFG_OUTINV_MASK (0x10000UL) +#define TRGM_FILTCFG_OUTINV_SHIFT (16U) +#define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK) +#define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT) + +/* + * MODE (RW) + * + * This bitfields defines the filter mode + * 000-bypass; + * 100-rapid change mode; + * 101-delay filter mode; + * 110-stalbe low mode; + * 111-stable high mode + */ +#define TRGM_FILTCFG_MODE_MASK (0xE000U) +#define TRGM_FILTCFG_MODE_SHIFT (13U) +#define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK) +#define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT) + +/* + * SYNCEN (RW) + * + * set to enable sychronization input signal with TRGM clock + */ +#define TRGM_FILTCFG_SYNCEN_MASK (0x1000U) +#define TRGM_FILTCFG_SYNCEN_SHIFT (12U) +#define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK) +#define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT) + +/* + * FILTLEN (RW) + * + * This bitfields defines the filter counter length. + */ +#define TRGM_FILTCFG_FILTLEN_MASK (0xFFFU) +#define TRGM_FILTCFG_FILTLEN_SHIFT (0U) +#define TRGM_FILTCFG_FILTLEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT) & TRGM_FILTCFG_FILTLEN_MASK) +#define TRGM_FILTCFG_FILTLEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT) + +/* Bitfield definition for register array: TRGOCFG */ +/* + * OUTINV (RW) + * + * 1- Invert the output + */ +#define TRGM_TRGOCFG_OUTINV_MASK (0x200U) +#define TRGM_TRGOCFG_OUTINV_SHIFT (9U) +#define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK) +#define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT) + +/* + * FEDG2PEN (RW) + * + * 1- The selected input signal falling edge will be convert to an pulse on output. + */ +#define TRGM_TRGOCFG_FEDG2PEN_MASK (0x100U) +#define TRGM_TRGOCFG_FEDG2PEN_SHIFT (8U) +#define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK) +#define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT) + +/* + * REDG2PEN (RW) + * + * 1- The selected input signal rising edge will be convert to an pulse on output. + */ +#define TRGM_TRGOCFG_REDG2PEN_MASK (0x80U) +#define TRGM_TRGOCFG_REDG2PEN_SHIFT (7U) +#define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK) +#define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT) + +/* + * TRIGOSEL (RW) + * + * This bitfield selects one of the TRGM inputs as output. + */ +#define TRGM_TRGOCFG_TRIGOSEL_MASK (0x7FU) +#define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U) +#define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK) +#define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT) + +/* Bitfield definition for register array: DMACFG */ +/* + * DMASRCSEL (RW) + * + * This field selects one of the DMA requests as the DMA request output. + */ +#define TRGM_DMACFG_DMASRCSEL_MASK (0x1FU) +#define TRGM_DMACFG_DMASRCSEL_SHIFT (0U) +#define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK) +#define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT) + +/* Bitfield definition for register: GCR */ +/* + * TRGOPEN (RW) + * + * The bitfield enable the TRGM outputs. + */ +#define TRGM_GCR_TRGOPEN_MASK (0xFFFU) +#define TRGM_GCR_TRGOPEN_SHIFT (0U) +#define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK) +#define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT) + + + +/* FILTCFG register group index macro definition */ +#define TRGM_FILTCFG_PWM_IN0 (0UL) +#define TRGM_FILTCFG_PWM_IN1 (1UL) +#define TRGM_FILTCFG_PWM_IN2 (2UL) +#define TRGM_FILTCFG_PWM_IN3 (3UL) +#define TRGM_FILTCFG_PWM_IN4 (4UL) +#define TRGM_FILTCFG_PWM_IN5 (5UL) +#define TRGM_FILTCFG_PWM_IN6 (6UL) +#define TRGM_FILTCFG_PWM_IN7 (7UL) +#define TRGM_FILTCFG_TRGM_IN0 (8UL) +#define TRGM_FILTCFG_TRGM_IN1 (9UL) +#define TRGM_FILTCFG_TRGM_IN2 (10UL) +#define TRGM_FILTCFG_TRGM_IN3 (11UL) +#define TRGM_FILTCFG_TRGM_IN4 (12UL) +#define TRGM_FILTCFG_TRGM_IN5 (13UL) +#define TRGM_FILTCFG_TRGM_IN6 (14UL) +#define TRGM_FILTCFG_TRGM_IN7 (15UL) +#define TRGM_FILTCFG_TRGM_IN8 (16UL) +#define TRGM_FILTCFG_TRGM_IN9 (17UL) +#define TRGM_FILTCFG_TRGM_IN10 (18UL) +#define TRGM_FILTCFG_TRGM_IN11 (19UL) + +/* TRGOCFG register group index macro definition */ +#define TRGM_TRGOCFG_TRGM_OUT0 (0UL) +#define TRGM_TRGOCFG_TRGM_OUT1 (1UL) +#define TRGM_TRGOCFG_TRGM_OUT2 (2UL) +#define TRGM_TRGOCFG_TRGM_OUT3 (3UL) +#define TRGM_TRGOCFG_TRGM_OUT4 (4UL) +#define TRGM_TRGOCFG_TRGM_OUT5 (5UL) +#define TRGM_TRGOCFG_TRGM_OUT6 (6UL) +#define TRGM_TRGOCFG_TRGM_OUT7 (7UL) +#define TRGM_TRGOCFG_TRGM_OUT8 (8UL) +#define TRGM_TRGOCFG_TRGM_OUT9 (9UL) +#define TRGM_TRGOCFG_TRGM_OUT10 (10UL) +#define TRGM_TRGOCFG_TRGM_OUT11 (11UL) +#define TRGM_TRGOCFG_TRGM_OUTX0 (12UL) +#define TRGM_TRGOCFG_TRGM_OUTX1 (13UL) +#define TRGM_TRGOCFG_PWM_SYNCI (14UL) +#define TRGM_TRGOCFG_PWM_FRCI (15UL) +#define TRGM_TRGOCFG_PWM_FRCSYNCI (16UL) +#define TRGM_TRGOCFG_PWM_SHRLDSYNCI (17UL) +#define TRGM_TRGOCFG_PWM_FAULTI0 (18UL) +#define TRGM_TRGOCFG_PWM_FAULTI1 (19UL) +#define TRGM_TRGOCFG_PWM_FAULTI2 (20UL) +#define TRGM_TRGOCFG_PWM_FAULTI3 (21UL) +#define TRGM_TRGOCFG_PWM_IN8 (22UL) +#define TRGM_TRGOCFG_PWM_IN9 (23UL) +#define TRGM_TRGOCFG_PWM_IN10 (24UL) +#define TRGM_TRGOCFG_PWM_IN11 (25UL) +#define TRGM_TRGOCFG_PWM_IN12 (26UL) +#define TRGM_TRGOCFG_PWM_IN13 (27UL) +#define TRGM_TRGOCFG_PWM_IN14 (28UL) +#define TRGM_TRGOCFG_PWM_IN15 (29UL) +#define TRGM_TRGOCFG_PLA_IN0 (30UL) +#define TRGM_TRGOCFG_PLA_IN1 (31UL) +#define TRGM_TRGOCFG_PLA_IN2 (32UL) +#define TRGM_TRGOCFG_PLA_IN3 (33UL) +#define TRGM_TRGOCFG_PLA_IN4 (34UL) +#define TRGM_TRGOCFG_PLA_IN5 (35UL) +#define TRGM_TRGOCFG_PLA_IN6 (36UL) +#define TRGM_TRGOCFG_PLA_IN7 (37UL) +#define TRGM_TRGOCFG_QEI_A (38UL) +#define TRGM_TRGOCFG_QEI_B (39UL) +#define TRGM_TRGOCFG_QEI_Z (40UL) +#define TRGM_TRGOCFG_QEI_H (41UL) +#define TRGM_TRGOCFG_QEI_PAUSE (42UL) +#define TRGM_TRGOCFG_QEI_SNAPI (43UL) +#define TRGM_TRGOCFG_HALL_U (44UL) +#define TRGM_TRGOCFG_HALL_V (45UL) +#define TRGM_TRGOCFG_HALL_W (46UL) +#define TRGM_TRGOCFG_HALL_SNAPI (47UL) +#define TRGM_TRGOCFG_ADC0_STRGI (48UL) +#define TRGM_TRGOCFG_ADC1_STRGI (49UL) +#define TRGM_TRGOCFG_ADC2_STRGI (50UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0A (52UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0B (53UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0C (54UL) +#define TRGM_TRGOCFG_GPTMRA_SYNCI (55UL) +#define TRGM_TRGOCFG_GPTMRA_IN2 (56UL) +#define TRGM_TRGOCFG_GPTMRA_IN3 (57UL) +#define TRGM_TRGOCFG_DAC_BUF_TRIG (58UL) +#define TRGM_TRGOCFG_DAC0_STEP_TRIG (59UL) +#define TRGM_TRGOCFG_DAC1_STEP_TRIG (60UL) +#define TRGM_TRGOCFG_CMPX_WIN (61UL) +#define TRGM_TRGOCFG_CAN_PTPC0_CAP (62UL) +#define TRGM_TRGOCFG_CAN_PTPC1_CAP (63UL) +#define TRGM_TRGOCFG_SDFM_EVT0 (64UL) +#define TRGM_TRGOCFG_SDFM_EVT1 (65UL) +#define TRGM_TRGOCFG_SDFM_EVT2 (66UL) +#define TRGM_TRGOCFG_SDFM_EVT3 (67UL) + +/* DMACFG register group index macro definition */ +#define TRGM_DMACFG_0 (0UL) +#define TRGM_DMACFG_1 (1UL) +#define TRGM_DMACFG_2 (2UL) +#define TRGM_DMACFG_3 (3UL) + + +#endif /* HPM_TRGM_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h new file mode 100644 index 00000000..70234d90 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h @@ -0,0 +1,734 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TRGMMUX_SRC_H +#define HPM_TRGMMUX_SRC_H + +/* trgm0_input mux definitions */ +#define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) +#define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX0 (0xEUL) +#define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX1 (0xFUL) +#define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX0 (0x10UL) +#define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX1 (0x11UL) +#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) +#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) +#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x1CUL) +#define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x1DUL) +#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x1EUL) +#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x1FUL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x20UL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x21UL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x22UL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x23UL) +#define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x24UL) +#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x25UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x26UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x27UL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPL0 (0x28UL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPL1 (0x29UL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPL2 (0x2AUL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPL3 (0x2BUL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPH0 (0x2CUL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPH1 (0x2DUL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPH2 (0x2EUL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPH3 (0x2FUL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ0 (0x30UL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ1 (0x31UL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ2 (0x32UL) +#define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ3 (0x33UL) +#define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM0_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM0_INPUT_SRC_CMP3_OUT (0x37UL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT0 (0x38UL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT1 (0x39UL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT2 (0x3AUL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT3 (0x3BUL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT4 (0x3CUL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT5 (0x3DUL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT6 (0x3EUL) +#define HPM_TRGM0_INPUT_SRC_PLA0_OUT7 (0x3FUL) + +/* trgm1_input mux definitions */ +#define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) +#define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) +#define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX0 (0xEUL) +#define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX1 (0xFUL) +#define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX0 (0x10UL) +#define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX1 (0x11UL) +#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) +#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) +#define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) +#define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x1CUL) +#define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x1DUL) +#define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x1EUL) +#define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x1FUL) +#define HPM_TRGM1_INPUT_SRC_SYNT1_CH0 (0x20UL) +#define HPM_TRGM1_INPUT_SRC_SYNT1_CH1 (0x21UL) +#define HPM_TRGM1_INPUT_SRC_SYNT1_CH2 (0x22UL) +#define HPM_TRGM1_INPUT_SRC_SYNT1_CH3 (0x23UL) +#define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x24UL) +#define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x25UL) +#define HPM_TRGM1_INPUT_SRC_GPTMR1_OUT2 (0x26UL) +#define HPM_TRGM1_INPUT_SRC_GPTMR1_OUT3 (0x27UL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPL0 (0x28UL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPL1 (0x29UL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPL2 (0x2AUL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPL3 (0x2BUL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPH0 (0x2CUL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPH1 (0x2DUL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPH2 (0x2EUL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPH3 (0x2FUL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ0 (0x30UL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ1 (0x31UL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ2 (0x32UL) +#define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ3 (0x33UL) +#define HPM_TRGM1_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM1_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM1_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM1_INPUT_SRC_CMP3_OUT (0x37UL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT0 (0x38UL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT1 (0x39UL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT2 (0x3AUL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT3 (0x3BUL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT4 (0x3CUL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT5 (0x3DUL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT6 (0x3EUL) +#define HPM_TRGM1_INPUT_SRC_PLA1_OUT7 (0x3FUL) + +/* trgm2_input mux definitions */ +#define HPM_TRGM2_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM2_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P0 (0x2UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P1 (0x3UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P2 (0x4UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P3 (0x5UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P4 (0x6UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P5 (0x7UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P6 (0x8UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P7 (0x9UL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P8 (0xAUL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P9 (0xBUL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P10 (0xCUL) +#define HPM_TRGM2_INPUT_SRC_TRGM2_P11 (0xDUL) +#define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX0 (0xEUL) +#define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX1 (0xFUL) +#define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX0 (0x10UL) +#define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX1 (0x11UL) +#define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX0 (0x12UL) +#define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX1 (0x13UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH8REF (0x14UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH9REF (0x15UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH10REF (0x16UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH11REF (0x17UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH12REF (0x18UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH13REF (0x19UL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH14REF (0x1AUL) +#define HPM_TRGM2_INPUT_SRC_PWM2_CH15REF (0x1BUL) +#define HPM_TRGM2_INPUT_SRC_QEI2_TRGO (0x1CUL) +#define HPM_TRGM2_INPUT_SRC_HALL2_TRGO (0x1DUL) +#define HPM_TRGM2_INPUT_SRC_PTPC_CMP0 (0x1EUL) +#define HPM_TRGM2_INPUT_SRC_PTPC_CMP1 (0x1FUL) +#define HPM_TRGM2_INPUT_SRC_SYNT2_CH0 (0x20UL) +#define HPM_TRGM2_INPUT_SRC_SYNT2_CH1 (0x21UL) +#define HPM_TRGM2_INPUT_SRC_SYNT2CH2 (0x22UL) +#define HPM_TRGM2_INPUT_SRC_SYNT2_CH3 (0x23UL) +#define HPM_TRGM2_INPUT_SRC_USB0_SOF (0x24UL) +#define HPM_TRGM2_INPUT_SRC_DEBUG_FLAG (0x25UL) +#define HPM_TRGM2_INPUT_SRC_GPTMR2_OUT2 (0x26UL) +#define HPM_TRGM2_INPUT_SRC_GPTMR2_OUT3 (0x27UL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPL0 (0x28UL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPL1 (0x29UL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPL2 (0x2AUL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPL3 (0x2BUL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPH0 (0x2CUL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPH1 (0x2DUL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPH2 (0x2EUL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPH3 (0x2FUL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ0 (0x30UL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ1 (0x31UL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ2 (0x32UL) +#define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ3 (0x33UL) +#define HPM_TRGM2_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM2_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM2_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM2_INPUT_SRC_CMP3_OUT (0x37UL) + +/* trgm3_input mux definitions */ +#define HPM_TRGM3_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM3_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P0 (0x2UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P1 (0x3UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P2 (0x4UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P3 (0x5UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P4 (0x6UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P5 (0x7UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P6 (0x8UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P7 (0x9UL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P8 (0xAUL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P9 (0xBUL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P10 (0xCUL) +#define HPM_TRGM3_INPUT_SRC_TRGM3_P11 (0xDUL) +#define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX0 (0xEUL) +#define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX1 (0xFUL) +#define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX0 (0x10UL) +#define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX1 (0x11UL) +#define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX0 (0x12UL) +#define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX1 (0x13UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH8REF (0x14UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH9REF (0x15UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH10REF (0x16UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH11REF (0x17UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH12REF (0x18UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH13REF (0x19UL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH14REF (0x1AUL) +#define HPM_TRGM3_INPUT_SRC_PWM3_CH15REF (0x1BUL) +#define HPM_TRGM3_INPUT_SRC_QEI3_TRGO (0x1CUL) +#define HPM_TRGM3_INPUT_SRC_HALL3_TRGO (0x1DUL) +#define HPM_TRGM3_INPUT_SRC_PTPC_CMP0 (0x1EUL) +#define HPM_TRGM3_INPUT_SRC_PTPC_CMP1 (0x1FUL) +#define HPM_TRGM3_INPUT_SRC_SYNT3_CH0 (0x20UL) +#define HPM_TRGM3_INPUT_SRC_SYNT3_CH1 (0x21UL) +#define HPM_TRGM3_INPUT_SRC_SYNT3_CH2 (0x22UL) +#define HPM_TRGM3_INPUT_SRC_SYNT3_CH3 (0x23UL) +#define HPM_TRGM3_INPUT_SRC_USB0_SOF (0x24UL) +#define HPM_TRGM3_INPUT_SRC_DEBUG_FLAG (0x25UL) +#define HPM_TRGM3_INPUT_SRC_GPTMR3_OUT2 (0x26UL) +#define HPM_TRGM3_INPUT_SRC_GPTMR3_OUT3 (0x27UL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPL0 (0x28UL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPL1 (0x29UL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPL2 (0x2AUL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPL3 (0x2BUL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPH0 (0x2CUL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPH1 (0x2DUL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPH2 (0x2EUL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPH3 (0x2FUL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ0 (0x30UL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ1 (0x31UL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ2 (0x32UL) +#define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ3 (0x33UL) +#define HPM_TRGM3_INPUT_SRC_CMP0_OUT (0x34UL) +#define HPM_TRGM3_INPUT_SRC_CMP1_OUT (0x35UL) +#define HPM_TRGM3_INPUT_SRC_CMP2_OUT (0x36UL) +#define HPM_TRGM3_INPUT_SRC_CMP3_OUT (0x37UL) + +/* trgm0_output mux definitions */ +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN0 (0x1EUL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN1 (0x1FUL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN2 (0x20UL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN3 (0x21UL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN4 (0x22UL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN5 (0x23UL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN6 (0x24UL) +#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN7 (0x25UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) +#define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) +#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x30UL) +#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x31UL) +#define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI (0x32UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) +#define HPM_TRGM0_OUTPUT_SRC_DAC0_BUF_TRG (0x3AUL) +#define HPM_TRGM0_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) +#define HPM_TRGM0_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) +#define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) +#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) +#define HPM_TRGM0_OUTPUT_SRC_SDM_TRG0 (0x40UL) +#define HPM_TRGM0_OUTPUT_SRC_SDM_TRG1 (0x41UL) +#define HPM_TRGM0_OUTPUT_SRC_SDM_TRG2 (0x42UL) +#define HPM_TRGM0_OUTPUT_SRC_SDM_TRG3 (0x43UL) + +/* trgm1_output mux definitions */ +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) +#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) +#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN0 (0x1EUL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN1 (0x1FUL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN2 (0x20UL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN3 (0x21UL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN4 (0x22UL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN5 (0x23UL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN6 (0x24UL) +#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN7 (0x25UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) +#define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) +#define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) +#define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI (0x30UL) +#define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI (0x31UL) +#define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI (0x32UL) +#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) +#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) +#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR1_SYNCI (0x37UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR1_IN2 (0x38UL) +#define HPM_TRGM1_OUTPUT_SRC_GPTMR1_IN3 (0x39UL) +#define HPM_TRGM1_OUTPUT_SRC_DAC1_BUF_TRG (0x3AUL) +#define HPM_TRGM1_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) +#define HPM_TRGM1_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) +#define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) +#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) +#define HPM_TRGM1_OUTPUT_SRC_SDM_TRG4 (0x40UL) +#define HPM_TRGM1_OUTPUT_SRC_SDM_TRG5 (0x41UL) +#define HPM_TRGM1_OUTPUT_SRC_SDM_TRG6 (0x42UL) +#define HPM_TRGM1_OUTPUT_SRC_SDM_TRG7 (0x43UL) + +/* trgm2_output mux definitions */ +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P0 (0x0UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P1 (0x1UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P2 (0x2UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P3 (0x3UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P4 (0x4UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P5 (0x5UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P6 (0x6UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P7 (0x7UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P8 (0x8UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P9 (0x9UL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P10 (0xAUL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P11 (0xBUL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX0 (0xCUL) +#define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX1 (0xDUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_SYNCI (0xEUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCI (0xFUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCSYNCI (0x10UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_SHRLDSYNCI (0x11UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI0 (0x12UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI1 (0x13UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI2 (0x14UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI3 (0x15UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN8 (0x16UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN9 (0x17UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN10 (0x18UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN11 (0x19UL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN12 (0x1AUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN13 (0x1BUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN14 (0x1CUL) +#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN15 (0x1DUL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_A (0x26UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_B (0x27UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_Z (0x28UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_H (0x29UL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_PAUSE (0x2AUL) +#define HPM_TRGM2_OUTPUT_SRC_QEI2_SNAPI (0x2BUL) +#define HPM_TRGM2_OUTPUT_SRC_HALL2_U (0x2CUL) +#define HPM_TRGM2_OUTPUT_SRC_HALL2_V (0x2DUL) +#define HPM_TRGM2_OUTPUT_SRC_HALL2_W (0x2EUL) +#define HPM_TRGM2_OUTPUT_SRC_HALL2_SNAPI (0x2FUL) +#define HPM_TRGM2_OUTPUT_SRC_ADC0_STRGI (0x30UL) +#define HPM_TRGM2_OUTPUT_SRC_ADC1_STRGI (0x31UL) +#define HPM_TRGM2_OUTPUT_SRC_ADC2_STRGI (0x32UL) +#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2A (0x34UL) +#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2B (0x35UL) +#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2C (0x36UL) +#define HPM_TRGM2_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) +#define HPM_TRGM2_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) +#define HPM_TRGM2_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) +#define HPM_TRGM2_OUTPUT_SRC_DAC0_BUF_TRG (0x3AUL) +#define HPM_TRGM2_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) +#define HPM_TRGM2_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) +#define HPM_TRGM2_OUTPUT_SRC_ACMP2_WIN (0x3DUL) +#define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) +#define HPM_TRGM2_OUTPUT_SRC_SDM_TRG8 (0x40UL) +#define HPM_TRGM2_OUTPUT_SRC_SDM_TRG9 (0x41UL) +#define HPM_TRGM2_OUTPUT_SRC_SDM_TRG10 (0x42UL) +#define HPM_TRGM2_OUTPUT_SRC_SDM_TRG11 (0x43UL) + +/* trgm3_output mux definitions */ +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P0 (0x0UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P1 (0x1UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P2 (0x2UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P3 (0x3UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P4 (0x4UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P5 (0x5UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P6 (0x6UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P7 (0x7UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P8 (0x8UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P9 (0x9UL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P10 (0xAUL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P11 (0xBUL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX0 (0xCUL) +#define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX1 (0xDUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_SYNCI (0xEUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCI (0xFUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCSYNCI (0x10UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_SHRLDSYNCI (0x11UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI0 (0x12UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI1 (0x13UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI2 (0x14UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI3 (0x15UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN8 (0x16UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN9 (0x17UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN10 (0x18UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN11 (0x19UL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN12 (0x1AUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN13 (0x1BUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN14 (0x1CUL) +#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN15 (0x1DUL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_A (0x26UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_B (0x27UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_Z (0x28UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_H (0x29UL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_PAUSE (0x2AUL) +#define HPM_TRGM3_OUTPUT_SRC_QEI3_SNAPI (0x2BUL) +#define HPM_TRGM3_OUTPUT_SRC_HALL3_U (0x2CUL) +#define HPM_TRGM3_OUTPUT_SRC_HALL3_V (0x2DUL) +#define HPM_TRGM3_OUTPUT_SRC_HALL3_W (0x2EUL) +#define HPM_TRGM3_OUTPUT_SRC_HALL3_SNAPI (0x2FUL) +#define HPM_TRGM3_OUTPUT_SRC_ADC0_STRGI (0x30UL) +#define HPM_TRGM3_OUTPUT_SRC_ADC1_STRGI (0x31UL) +#define HPM_TRGM3_OUTPUT_SRC_ADC2_STRGI (0x32UL) +#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3A (0x34UL) +#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3B (0x35UL) +#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3C (0x36UL) +#define HPM_TRGM3_OUTPUT_SRC_GPTMR3_SYNCI (0x37UL) +#define HPM_TRGM3_OUTPUT_SRC_GPTMR3_IN2 (0x38UL) +#define HPM_TRGM3_OUTPUT_SRC_GPTMR3_IN3 (0x39UL) +#define HPM_TRGM3_OUTPUT_SRC_DAC1_BUF_TRG (0x3AUL) +#define HPM_TRGM3_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) +#define HPM_TRGM3_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) +#define HPM_TRGM3_OUTPUT_SRC_ACMP3_WIN (0x3DUL) +#define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) +#define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) +#define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG12 (0x40UL) +#define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG13 (0x41UL) +#define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG14 (0x42UL) +#define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG15 (0x43UL) + +/* trgm0_filter mux definitions */ +#define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) +#define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) + +/* trgm1_filter mux definitions */ +#define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) +#define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) +#define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) + +/* trgm2_filter mux definitions */ +#define HPM_TRGM2_FILTER_SRC_PWM2_IN0 (0x0UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN1 (0x1UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN2 (0x2UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN3 (0x3UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN4 (0x4UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN5 (0x5UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN6 (0x6UL) +#define HPM_TRGM2_FILTER_SRC_PWM2_IN7 (0x7UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN0 (0x8UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN1 (0x9UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN2 (0xAUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN3 (0xBUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN4 (0xCUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN5 (0xDUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN6 (0xEUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN7 (0xFUL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN8 (0x10UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN9 (0x11UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN10 (0x12UL) +#define HPM_TRGM2_FILTER_SRC_TRGM2_IN11 (0x13UL) + +/* trgm3_filter mux definitions */ +#define HPM_TRGM3_FILTER_SRC_PWM3_IN0 (0x0UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN1 (0x1UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN2 (0x2UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN3 (0x3UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN4 (0x4UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN5 (0x5UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN6 (0x6UL) +#define HPM_TRGM3_FILTER_SRC_PWM3_IN7 (0x7UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN0 (0x8UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN1 (0x9UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN2 (0xAUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN3 (0xBUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN4 (0xCUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN5 (0xDUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN6 (0xEUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN7 (0xFUL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN8 (0x10UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN9 (0x11UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN10 (0x12UL) +#define HPM_TRGM3_FILTER_SRC_TRGM3_IN11 (0x13UL) + +/* trgm0_dma mux definitions */ +#define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) +#define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) +#define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) +#define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) +#define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) +#define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) + +/* trgm1_dma mux definitions */ +#define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) +#define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) +#define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) +#define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) +#define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) +#define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) +#define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) + +/* trgm2_dma mux definitions */ +#define HPM_TRGM2_DMA_SRC_PWM2_CMP0 (0x0UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP1 (0x1UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP2 (0x2UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP3 (0x3UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP4 (0x4UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP5 (0x5UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP6 (0x6UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP7 (0x7UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP8 (0x8UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP9 (0x9UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP10 (0xAUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP11 (0xBUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP12 (0xCUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP13 (0xDUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP14 (0xEUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP15 (0xFUL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP16 (0x10UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP17 (0x11UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP18 (0x12UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP19 (0x13UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP20 (0x14UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP21 (0x15UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP22 (0x16UL) +#define HPM_TRGM2_DMA_SRC_PWM2_CMP23 (0x17UL) +#define HPM_TRGM2_DMA_SRC_PWM2_RLD (0x18UL) +#define HPM_TRGM2_DMA_SRC_PWM2_HALFRLD (0x19UL) +#define HPM_TRGM2_DMA_SRC_PWM2_XRLD (0x1AUL) +#define HPM_TRGM2_DMA_SRC_QEI2 (0x1BUL) +#define HPM_TRGM2_DMA_SRC_HALL2 (0x1CUL) + +/* trgm3_dma mux definitions */ +#define HPM_TRGM3_DMA_SRC_PWM3_CMP0 (0x0UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP1 (0x1UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP2 (0x2UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP3 (0x3UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP4 (0x4UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP5 (0x5UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP6 (0x6UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP7 (0x7UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP8 (0x8UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP9 (0x9UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP10 (0xAUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP11 (0xBUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP12 (0xCUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP13 (0xDUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP14 (0xEUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP15 (0xFUL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP16 (0x10UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP17 (0x11UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP18 (0x12UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP19 (0x13UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP20 (0x14UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP21 (0x15UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP22 (0x16UL) +#define HPM_TRGM3_DMA_SRC_PWM3_CMP23 (0x17UL) +#define HPM_TRGM3_DMA_SRC_PWM3_RLD (0x18UL) +#define HPM_TRGM3_DMA_SRC_PWM3_HALFRLD (0x19UL) +#define HPM_TRGM3_DMA_SRC_PWM3_XRLD (0x1AUL) +#define HPM_TRGM3_DMA_SRC_QEI3 (0x1BUL) +#define HPM_TRGM3_DMA_SRC_HALL3 (0x1CUL) + + + +#endif /* HPM_TRGMMUX_SRC_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6280/soc_modules.list b/common/libraries/hpm_sdk/soc/HPM6280/soc_modules.list new file mode 100644 index 00000000..92980486 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/soc_modules.list @@ -0,0 +1,40 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause +# +# In this file, all modules available on this part are listed + +CONFIG_HAS_HPMSDK_UART=y +CONFIG_HAS_HPMSDK_FEMC=n +CONFIG_HAS_HPMSDK_SDP=y +CONFIG_HAS_HPMSDK_I2C=y +CONFIG_HAS_HPMSDK_PMP=y +CONFIG_HAS_HPMSDK_RNG=y +CONFIG_HAS_HPMSDK_GPIO=y +CONFIG_HAS_HPMSDK_SPI=y +CONFIG_HAS_HPMSDK_WDG=y +CONFIG_HAS_HPMSDK_DMA=y +CONFIG_HAS_HPMSDK_GPTMR=y +CONFIG_HAS_HPMSDK_PWM=y +CONFIG_HAS_HPMSDK_PLLCTLV2=y +CONFIG_HAS_HPMSDK_USB=y +CONFIG_HAS_HPMSDK_RTC=y +CONFIG_HAS_HPMSDK_ACMP=y +CONFIG_HAS_HPMSDK_I2S=n +CONFIG_HAS_HPMSDK_DAO=n +CONFIG_HAS_HPMSDK_PDM=n +CONFIG_HAS_HPMSDK_VAD=n +CONFIG_HAS_HPMSDK_MCAN=y +CONFIG_HAS_HPMSDK_ENET=n +CONFIG_HAS_HPMSDK_SDXC=n +CONFIG_HAS_HPMSDK_ADC16=y +CONFIG_HAS_HPMSDK_PCFG=y +CONFIG_HAS_HPMSDK_PMU=y +CONFIG_HAS_HPMSDK_PTPC=y +CONFIG_HAS_HPMSDK_MCHTMR=y +CONFIG_HAS_HPMSDK_FFA=n +CONFIG_HAS_HPMSDK_TSNS=y +CONFIG_HAS_HPMSDK_DAC=y +CONFIG_HAS_HPMSDK_CRC=y +CONFIG_HAS_HPMSDK_PLA=y +CONFIG_HAS_HPMSDK_SDM=y +CONFIG_HAS_HPMSDK_LIN=y diff --git a/common/libraries/hpm_sdk/soc/HPM6280/system.c b/common/libraries/hpm_sdk/soc/HPM6280/system.c new file mode 100644 index 00000000..eb12609e --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/system.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" + +#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP +#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 +#endif + +void enable_plic_feature(void) +{ + uint32_t plic_feature = 0; +#ifndef USE_NONVECTOR_MODE + /* enabled vector mode and preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; +#endif +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + /* enabled preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; +#endif + __plic_set_feature(HPM_PLIC_BASE, plic_feature); +} + +__attribute__((weak)) void system_init(void) +{ +#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR + uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ +#endif + +#ifdef USE_S_MODE_IRQ + disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#else + disable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + + disable_irq_from_intc(); +#ifdef USE_S_MODE_IRQ + disable_s_irq_from_intc(); +#endif + + enable_plic_feature(); + enable_irq_from_intc(); + +#ifdef USE_S_MODE_IRQ + delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); + enable_s_irq_from_intc(); +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP + enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#endif +#else +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif +#endif + +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); + l1c_dc_invalidate_all(); +#endif +} diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld new file mode 100644 index 00000000..d2b822b4 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x010A0000, LENGTH = 112K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .vectors ORIGIN(ILM) : AT(etext) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .data : AT(etext + __vector_ram_end__ - __vector_ram_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") +} diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld new file mode 100644 index 00000000..f9cc208a --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x010A0000, LENGTH = 112K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + KEEP(*(.uf2_signature)) + KEEP(*(.start)) + } > XPI0 + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") +} diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld new file mode 100644 index 00000000..70f262a6 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x010A0000, LENGTH = 112K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + /* section information for usbh class */ + .usbh_class_info : { + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") +} diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/initfini.c b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/initfini.c new file mode 100644 index 00000000..7d2b8579 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/initfini.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#ifndef USE_LIBC_INITFINI +#define USE_LIBC_INITFINI 0 +#endif + +#if USE_LIBC_INITFINI + +/* + * The _init() and _fini() will be called respectively when use __libc_init_array() + * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. + * The dummy versions of these functions should be provided. + */ +void _init(void) +{ +} + +void _fini(void) +{ +} + +#else + +/* These magic symbols are provided by the linker. */ +extern void (*__preinit_array_start[])(void) __attribute__((weak)); +extern void (*__preinit_array_end[])(void) __attribute__((weak)); +extern void (*__init_array_start[])(void) __attribute__((weak)); +extern void (*__init_array_end[])(void) __attribute__((weak)); + +/* + * The __libc_init_array()/__libc_fnit_array() function is used to do global + * constructor/destructor and can NOT be compilied to generate the code coverage + * data. We have the function attribute to be 'no_profile_instrument_function' + * to prevent been instrumented for coverage analysis when GCOV=1 is applied. + */ +/* Iterate over all the init routines. */ +void __libc_init_array(void) __attribute__((no_profile_instrument_function)); +void __libc_init_array(void) +{ + uint32_t count; + uint32_t i; + + count = __preinit_array_end - __preinit_array_start; + for (i = 0; i < count; i++) { + __preinit_array_start[i](); + } + + count = __init_array_end - __init_array_start; + for (i = 0; i < count; i++) { + __init_array_start[i](); + } +} + +extern void (*__fini_array_start[])(void) __attribute__((weak)); +extern void (*__fini_array_end[])(void) __attribute__((weak)); + +/* Run all the cleanup routines. */ +void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); +void __libc_fini_array(void) +{ + uint32_t count; + uint32_t i; + + count = __fini_array_end - __fini_array_start; + for (i = count; i > 0; i--) { + __fini_array_start[i - 1](); + } +} + +#endif diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld new file mode 100644 index 00000000..3fa899ea --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01080000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x010A0000, LENGTH = 112K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + KEEP(*(.isr_s_vector)) + KEEP(*(.vector_s_table)) + . = ALIGN(8); + } > ILM + + .rel : { + KEEP(*(.rel*)) + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + . = ALIGN(8); + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); + __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") +} diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld new file mode 100644 index 00000000..280c122b --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + ILM (wx) : ORIGIN = 0x00020000, LENGTH = 128K + DLM (w) : ORIGIN = 0x000A0000, LENGTH = 96K + NONCACHEABLE_RAM (w) : ORIGIN = 0x000B8000, LENGTH = 32K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > ILM + + .rel : { + KEEP(*(.rel*)) + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + . = ALIGN(8); + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > ILM + + .data : AT(etext) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __data_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.tbss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.tcommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .sh_mem (NOLOAD) : { + KEEP(*(.sh_mem)) + } > SHARE_RAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") +} diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S new file mode 100644 index 00000000..ff1c6e89 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_csr_regs.h" + + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + + /* reset mstatus to 0*/ + csrrw x0, mstatus, x0 + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + call c_startup + +#if defined(__SES_RISCV) + /* Initialize the heap */ + la a0, __heap_start__ + la a1, __heap_end__ + sub a1, a1, a0 + la t1, __SEGGER_RTL_init_heap + jalr t1 +#endif + + /* Do global constructors */ + call __libc_init_array + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifndef CONFIG_FREERTOS + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap +#else + #define HANDLER_TRAP freertos_risc_v_trap_handler + #define HANDLER_S_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#endif + +#ifndef USE_NONVECTOR_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + +#if defined (USE_S_MODE_IRQ) + la t0, __vector_s_table + csrw stvec, t0 +#endif + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 +#if defined (USE_S_MODE_IRQ) + la t0, HANDLER_S_TRAP + csrw stvec, t0 +#endif + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidentally */ +1: j 1b + + .weak exit +exit: +1: j 1b + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c new file mode 100644 index 00000000..6032f08f --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include "hpm_interrupt.h" + + +extern void system_init(void); + + +__attribute__((weak)) void _clean_up(void) +{ + /* clean up plic, it will help while debugging */ + disable_irq_from_intc(); + intc_m_set_threshold(0); + for (uint32_t irq = 0; irq < 128; irq++) { + intc_m_complete_irq(irq); + } + /* clear any bits left in plic enable register */ + for (uint32_t i = 0; i < 4; i++) { + *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; + } +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#if defined(FLASH_XIP) || defined(FLASH_UF2) + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc legnth */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while (1) { + ; + } +} + +__attribute__((weak)) void reset_handler(void) +{ + l1c_dc_disable(); + l1c_dc_invalidate_all(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Entry function */ + main(); +} + +/* + * When compiling C++ code with static objects, the compiler inserts + * a call to __cxa_atexit() with __dso_handle as one of the arguments. + * The dummy versions of these symbols should be provided. + */ +__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) +{ +} + +#ifndef __SEGGER_RTL_VERSION +void *__dso_handle = (void *) &__dso_handle; +#endif + +__attribute__((weak)) void _init(void) +{ +} diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf new file mode 100644 index 00000000..06780b3e --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; +define region AXI_SRAM = [from 0x010A0000 size 112k]; +define region SHARE_RAM = [from 0x010BC000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place at start of XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { + section .fast, section .fast.* // "ramfunc" section + }; +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf new file mode 100644 index 00000000..b7b9175a --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; +define region AXI_SRAM = [from 0x010A0000 size 112k]; +define region SHARE_RAM = [from 0x010BC000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .uf2_signature }; +keep { section .usbh_class_info}; diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf new file mode 100644 index 00000000..62908e36 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; +define region AXI_SRAM = [from 0x010A0000 size 112k]; +define region SHARE_RAM = [from 0x010BC000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +keep { section .usbh_class_info}; diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf new file mode 100644 index 00000000..53167b9c --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; +define region AXI_SRAM = [from 0x010A0000 size 112k]; +define region SHARE_RAM = [from 0x010BC000 size 16k]; +define region AHB_SRAM = [from 0xF0300000 size 32k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +/* Placement */ +place at start of ILM { symbol _start }; +place in ILM { block vectors, block vectors_s }; // Vector table section +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in ILM with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in SHARE_RAM { section .sh_mem}; // Share memory +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf new file mode 100644 index 00000000..3110cc33 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region ILM = [from 0x00020000 size 128k]; /* ILM */ +define region DLM = [from 0x000A0000 size 96k]; /* DLM */ +define region NONCACHEABLE_RAM = [from 0x000B8000 size 32k]; /* AXI SRAM1 */ +define region SHARE_RAM = [from 0x010BC000 size 16k]; + +assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; + +/* Blocks */ +define block vectors { section .isr_vector, section .vector_table }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block cherryusb_usbh_class_info { section .usbh_class_info }; +define block framebuffer { section .framebuffer }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; + +/* Symbols */ +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; + +define exported symbol _stack = end of block stack + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +/* Placement */ +place at start of ILM { symbol _start }; +place in ILM { block vectors }; // Vector table section +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in ILM with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in DLM { block cherryusb_usbh_class_info }; +place in DLM { block framebuffer }; +place in DLM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; + +place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in SHARE_RAM { section .sh_mem}; // Share memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/startup.s b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/startup.s new file mode 100644 index 00000000..35e26ba8 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/startup.s @@ -0,0 +1,380 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2021 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : SEGGER_RISCV_crt0.s +Purpose : Generic runtime init startup code for RISC-V CPUs. + Designed to work with the SEGGER linker to produce + smallest possible executables. + + This file does not normally require any customization. + +Additional information: + Preprocessor Definitions + FULL_LIBRARY + If defined then + - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). + - the exit symbol is defined and executes on return from main. + - the exit symbol calls destructors, atexit functions and then + calls SEGGER_SEMIHOST_Exit(). + + If not defined then + - argc and argv are not valid (main is assumed to not take parameters) + - the exit symbol is defined, executes on return from main and + halts in a loop. +*/ + +#include "hpm_csr_regs.h" + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ +#ifndef APP_ENTRY_POINT + #define APP_ENTRY_POINT reset_handler +#endif + +#ifndef ARGSSPACE + #define ARGSSPACE 128 +#endif + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ +// +// Declare a label as function symbol (without switching sections) +// +.macro MARK_FUNC Name + .global \Name + .type \Name, function +\Name: +.endm + +// +// Declare a regular function. +// Functions from the startup are placed in the init section. +// +.macro START_FUNC Name + .section .init.\Name, "ax" + .global \Name +#if __riscv_compressed + .balign 2 +#else + .balign 4 +#endif + .type \Name, function +\Name: +.endm + +// +// Declare a weak function +// +.macro WEAK_FUNC Name + .section .init.\Name, "ax", %progbits + .global \Name + .weak \Name +#if __riscv_compressed + .balign 2 +#else + .balign 4 +#endif + .type \Name, function +\Name: +.endm + +// +// Mark the end of a function and calculate its size +// +.macro END_FUNC name + .size \name,.-\name +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern APP_ENTRY_POINT // typically main + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* _start +* +* Function description +* Entry point for the startup code. +* Usually called by the reset handler. +* Performs all initialisation, based on the entries in the +* linker-generated init table, then calls main(). +* It is device independent, so there should not be any need for an +* end-user to modify it. +* +* Additional information +* At this point, the stack pointer should already have been +* initialized +* - by hardware (such as on Cortex-M), +* - by the device-specific reset handler, +* - or by the debugger (such as for RAM Code). +*/ +#undef L +#define L(label) .L_start_##label + +START_FUNC _start + .option push + .option norelax + lui gp, %hi(__global_pointer$) + addi gp, gp, %lo(__global_pointer$) + lui tp, %hi(__thread_pointer$) + addi tp, tp, %lo(__thread_pointer$) + .option pop + + csrw mstatus, zero + csrw mcause, zero + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + + lui t0, %hi(__stack_end__) + addi sp, t0, %lo(__stack_end__) + +#ifndef __NO_SYSTEM_INIT + // + // Call _init + // + call _init +#endif + // + // Call linker init functions which in turn performs the following: + // * Perform segment init + // * Perform heap init (if used) + // * Call constructors of global Objects (if any exist) + // + la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table +L(RunInit): + lw a0, (s0) // Get next initialization function from table + add s0, s0, 4 // Increment table pointer to point to function arguments + jalr a0 // Call initialization function + j L(RunInit) + // +MARK_FUNC __SEGGER_init_done + // + // Time to call main(), the application entry point. + // + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#ifndef CONFIG_FREERTOS + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap +#else + #define HANDLER_TRAP freertos_risc_v_trap_handler + #define HANDLER_S_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#endif + +#if !defined(USE_NONVECTOR_MODE) + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + +#if defined (USE_S_MODE_IRQ) + la t0, __vector_s_table + csrw stvec, t0 +#endif + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 +#if defined (USE_S_MODE_IRQ) + la t0, HANDLER_S_TRAP + csrw stvec, t0 +#endif + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + +MARK_FUNC start +#ifndef FULL_LIBRARY + // + // In a real embedded application ("Free-standing environment"), + // main() does not get any arguments, + // which means it is not necessary to init a0 and a1. + // + call APP_ENTRY_POINT + tail exit + +END_FUNC _start + // + // end of _start + // Fall-through to exit if main ever returns. + // +MARK_FUNC exit + // + // In a free-standing environment, if returned from application: + // Loop forever. + // + j . + .size exit,.-exit +#else + // + // In a hosted environment, + // we need to load a0 and a1 with argc and argv, in order to handle + // the command line arguments. + // This is required for some programs running under control of a + // debugger, such as automated tests. + // + li a0, ARGSSPACE + la a1, args + call debug_getargs + li a0, ARGSSPACE + la a1, args + + call APP_ENTRY_POINT // Call to application entry point (usually main()) + call exit // Call exit function + j . // If we unexpectedly return from exit, hang. +END_FUNC _start +#endif + +#ifdef FULL_LIBRARY + li a0, ARGSSPACE + la a1, args + call debug_getargs + li a0, ARGSSPACE + la a1, args +#else + li a0, 0 + li a1, 0 +#endif + + call APP_ENTRY_POINT + tail exit + +END_FUNC _start + + // +#ifdef FULL_LIBRARY +/********************************************************************* +* +* exit +* +* Function description +* Exit of the system. +* Called on return from application entry point or explicit call +* to exit. +* +* Additional information +* In a hosted environment exit gracefully, by +* saving the return value, +* calling destructurs of global objects, +* calling registered atexit functions, +* and notifying the host/debugger. +*/ +#undef L +#define L(label) .L_exit_##label + +WEAK_FUNC exit + mv s1, a0 // Save the exit parameter/return result + // + // Call destructors + // + la s0, __dtors_start__ +L(Loop): + la t0, __dtors_end__ + beq s0, t0, L(End) + lw t1, 0(s0) + addi s0, s0, 4 + jalr t1 + j L(Loop) +L(End): + // + // Call atexit functions + // + call _execute_at_exit_fns + // + // Call debug_exit with return result/exit parameter + // + mv a0, s1 + call debug_exit + // + // If execution is not terminated, loop forever + // +L(ExitLoop): + j L(ExitLoop) // Loop forever. +END_FUNC exit +#endif + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE + .size args, .-args + .type args, %object +#endif + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" + +/*************************** End of file ****************************/ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/trap.c b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/trap.c new file mode 100644 index 00000000..72b25741 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/trap.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" + +/********************** MCAUSE exception types **************************************/ +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ +#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ +#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ +#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ +#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ +#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ +#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ +#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +__attribute__((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void swi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) +{ +} + +__attribute__((weak)) long exception_handler(long cause, long epc) +{ + switch (cause) { + case MCAUSE_INSTR_ADDR_MISALIGNED: + break; + case MCAUSE_INSTR_ACCESS_FAULT: + break; + case MCAUSE_ILLEGAL_INSTR: + break; + case MCAUSE_BREAKPOINT: + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + break; + case MCAUSE_LOAD_ACCESS_FAULT: + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + break; + case MCAUSE_ECALL_FROM_USER_MODE: + break; + case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: + break; + case MCAUSE_ECALL_FROM_MACHINE_MODE: + break; + case MCAUSE_INSTR_PAGE_FAULT: + break; + case MCAUSE_LOAD_PAGE_FAULT: + break; + case MCAUSE_STORE_AMO_PAGE_FAULT: + break; + default: + break; + } + /* Unhandled Trap */ + return epc; +} + +__attribute__((weak)) long exception_s_handler(long cause, long epc) +{ + return epc; +} + +__attribute__((weak)) void swi_s_isr(void) +{ +} + +__attribute__((weak)) void mchtmr_s_isr(void) +{ +} + +#ifndef CONFIG_FREERTOS +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))); +#else +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); +#endif +void irq_handler_trap(void) +{ + long mcause = read_csr(CSR_MCAUSE); + long mepc = read_csr(CSR_MEPC); + long mstatus = read_csr(CSR_MSTATUS); +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH + long mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { + /* Machine timer interrupt */ + mchtmr_isr(); + } +#ifdef USE_NONVECTOR_MODE + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { + + typedef void(*isr_func_t)(void); + + /* Machine-level interrupt from PLIC */ + uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + if (irq_index) { + /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + ((isr_func_t)__vector_table[irq_index])(); + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + } +#endif + + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { + /* Machine SWI interrupt */ + swi_isr(); + intc_m_complete_swi(); + } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" + #ifdef __riscv_32e + "mv a0, t0\n" + #else + "mv a0, a7\n" + #endif + "jalr %0\n" + : :"r"(syscall_handler) : "a4" + ); + mepc += 4; + } else { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +#ifndef CONFIG_FREERTOS +void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"), interrupt("supervisor"), aligned(4))); +#else +void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"))); +#endif +void irq_handler_s_trap(void) +{ + long scause = read_csr(CSR_SCAUSE); + long sepc = read_csr(CSR_SEPC); + long sstatus = read_csr(CSR_SSTATUS); + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_TIMER)) { + /* Machine timer interrupt */ + mchtmr_s_isr(); + } +#ifdef USE_NONVECTOR_MODE + else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_EXT)) { + + typedef void(*isr_func_t)(void); + + /* Machine-level interrupt from PLIC */ + uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE); +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + enable_s_global_irq(CSR_SSTATUS_SIE_MASK); +#endif + ((isr_func_t)__vector_s_table[irq_index])(); + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE, irq_index); + + } +#endif + + else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_SOFT)) { + /* Machine SWI interrupt */ + intc_m_claim_swi(); + swi_s_isr(); + intc_s_complete_swi(); + } else if (!(scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_SUPERVISOR_MODE)) { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" + #ifdef __riscv_32e + "mv a0, t0\n" + #else + "mv a0, a7\n" + #endif + "jalr %0\n" + : :"r"(syscall_handler) : "a4" + ); + sepc += 4; + } else { + sepc = exception_s_handler(scause, sepc); + } + + /* Restore CSR */ + write_csr(CSR_SSTATUS, sstatus); + write_csr(CSR_SEPC, sepc); +} diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h new file mode 100644 index 00000000..e48c61d0 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +.global default_irq_handler +.weak default_irq_handler +.align 2 +default_irq_handler: +1: j 1b + +.macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq +.endm + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_HANDLER 18 /* SDFM IRQ handler */ + IRQ_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* UART0 IRQ handler */ + IRQ_HANDLER 30 /* UART1 IRQ handler */ + IRQ_HANDLER 31 /* UART2 IRQ handler */ + IRQ_HANDLER 32 /* UART3 IRQ handler */ + IRQ_HANDLER 33 /* UART4 IRQ handler */ + IRQ_HANDLER 34 /* UART5 IRQ handler */ + IRQ_HANDLER 35 /* UART6 IRQ handler */ + IRQ_HANDLER 36 /* UART7 IRQ handler */ + IRQ_HANDLER 37 /* CAN0 IRQ handler */ + IRQ_HANDLER 38 /* CAN1 IRQ handler */ + IRQ_HANDLER 39 /* CAN2 IRQ handler */ + IRQ_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_HANDLER 41 /* PTPC IRQ handler */ + IRQ_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_HANDLER 44 /* TSNS IRQ handler */ + IRQ_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_HANDLER 69 /* SDP IRQ handler */ + IRQ_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_HANDLER 71 /* XDMA IRQ handler */ + IRQ_HANDLER 72 /* HDMA IRQ handler */ + IRQ_HANDLER 73 /* RNG IRQ handler */ + IRQ_HANDLER 74 /* USB0 IRQ handler */ + IRQ_HANDLER 75 /* PSEC IRQ handler */ + IRQ_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_HANDLER 77 /* PWDG IRQ handler */ + IRQ_HANDLER 78 /* PTMR IRQ handler */ + IRQ_HANDLER 79 /* PUART IRQ handler */ + IRQ_HANDLER 80 /* FUSE IRQ handler */ + IRQ_HANDLER 81 /* SECMON IRQ handler */ + IRQ_HANDLER 82 /* RTC IRQ handler */ + IRQ_HANDLER 83 /* BUTN IRQ handler */ + IRQ_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_HANDLER 85 /* BVIO IRQ handler */ + IRQ_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_HANDLER 93 /* LIN3 IRQ handler */ + + +.global default_irq_s_handler +.weak default_irq_s_handler +.align 2 +default_irq_s_handler: +1: j 1b + +.macro IRQ_S_HANDLER irq + .weak default_isr_s_\irq + .set default_isr_s_\irq, default_irq_s_handler + .long default_isr_s_\irq +.endm + +.section .vector_s_table, "a" +.global __vector_s_table +.align 9 + +__vector_s_table: + .weak default_isr_s_trap + .set default_isr_s_trap, irq_handler_s_trap + .long default_isr_s_trap + IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_S_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_S_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_S_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_S_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_S_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_S_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_S_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_S_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_S_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_S_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_S_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_S_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_S_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_S_HANDLER 18 /* SDFM IRQ handler */ + IRQ_S_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_S_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_S_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_S_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_S_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_S_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_S_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_S_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_S_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_S_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_S_HANDLER 29 /* UART0 IRQ handler */ + IRQ_S_HANDLER 30 /* UART1 IRQ handler */ + IRQ_S_HANDLER 31 /* UART2 IRQ handler */ + IRQ_S_HANDLER 32 /* UART3 IRQ handler */ + IRQ_S_HANDLER 33 /* UART4 IRQ handler */ + IRQ_S_HANDLER 34 /* UART5 IRQ handler */ + IRQ_S_HANDLER 35 /* UART6 IRQ handler */ + IRQ_S_HANDLER 36 /* UART7 IRQ handler */ + IRQ_S_HANDLER 37 /* CAN0 IRQ handler */ + IRQ_S_HANDLER 38 /* CAN1 IRQ handler */ + IRQ_S_HANDLER 39 /* CAN2 IRQ handler */ + IRQ_S_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_S_HANDLER 41 /* PTPC IRQ handler */ + IRQ_S_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_S_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_S_HANDLER 44 /* TSNS IRQ handler */ + IRQ_S_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_S_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_S_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_S_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_S_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_S_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_S_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_S_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_S_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_S_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_S_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_S_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_S_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_S_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_S_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_S_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_S_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_S_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_S_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_S_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_S_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_S_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_S_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_S_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_S_HANDLER 69 /* SDP IRQ handler */ + IRQ_S_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_S_HANDLER 71 /* XDMA IRQ handler */ + IRQ_S_HANDLER 72 /* HDMA IRQ handler */ + IRQ_S_HANDLER 73 /* RNG IRQ handler */ + IRQ_S_HANDLER 74 /* USB0 IRQ handler */ + IRQ_S_HANDLER 75 /* PSEC IRQ handler */ + IRQ_S_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_S_HANDLER 77 /* PWDG IRQ handler */ + IRQ_S_HANDLER 78 /* PTMR IRQ handler */ + IRQ_S_HANDLER 79 /* PUART IRQ handler */ + IRQ_S_HANDLER 80 /* FUSE IRQ handler */ + IRQ_S_HANDLER 81 /* SECMON IRQ handler */ + IRQ_S_HANDLER 82 /* RTC IRQ handler */ + IRQ_S_HANDLER 83 /* BUTN IRQ handler */ + IRQ_S_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_S_HANDLER 85 /* BVIO IRQ handler */ + IRQ_S_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_S_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_S_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_S_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_S_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_S_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_S_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_S_HANDLER 93 /* LIN3 IRQ handler */ diff --git a/common/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml b/common/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml index bcc6ad5c..3d7e93bb 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml +++ b/common/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml @@ -7,7 +7,7 @@ HPM6300 device /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10143,231 +10143,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOC_PIN_PIN28 - GPIO mananger - 0x170 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN29 - GPIO mananger - 0x174 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN30 - GPIO mananger - 0x178 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOC_PIN_PIN31 - GPIO mananger - 0x17c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN00 - GPIO mananger - 0x180 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN01 - GPIO mananger - 0x184 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOD_PIN_PIN02 + ASSIGN_GPIOX_PIN_PIN00 GPIO mananger - 0x188 + 0x680 32 0x00000000 0x80000301 @@ -10402,9 +10180,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN03 + ASSIGN_GPIOX_PIN_PIN01 GPIO mananger - 0x18c + 0x684 32 0x00000000 0x80000301 @@ -10439,9 +10217,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN04 + ASSIGN_GPIOX_PIN_PIN02 GPIO mananger - 0x190 + 0x688 32 0x00000000 0x80000301 @@ -10476,9 +10254,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN05 + ASSIGN_GPIOX_PIN_PIN03 GPIO mananger - 0x194 + 0x68c 32 0x00000000 0x80000301 @@ -10513,9 +10291,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN06 + ASSIGN_GPIOX_PIN_PIN04 GPIO mananger - 0x198 + 0x690 32 0x00000000 0x80000301 @@ -10550,9 +10328,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN07 + ASSIGN_GPIOX_PIN_PIN05 GPIO mananger - 0x19c + 0x694 32 0x00000000 0x80000301 @@ -10587,9 +10365,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN08 + ASSIGN_GPIOX_PIN_PIN06 GPIO mananger - 0x1a0 + 0x698 32 0x00000000 0x80000301 @@ -10624,9 +10402,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN09 + ASSIGN_GPIOX_PIN_PIN07 GPIO mananger - 0x1a4 + 0x69c 32 0x00000000 0x80000301 @@ -10661,9 +10439,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN10 + ASSIGN_GPIOY_PIN_PIN00 GPIO mananger - 0x1a8 + 0x700 32 0x00000000 0x80000301 @@ -10698,9 +10476,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN11 + ASSIGN_GPIOY_PIN_PIN01 GPIO mananger - 0x1ac + 0x704 32 0x00000000 0x80000301 @@ -10735,9 +10513,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN12 + ASSIGN_GPIOY_PIN_PIN02 GPIO mananger - 0x1b0 + 0x708 32 0x00000000 0x80000301 @@ -10772,9 +10550,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN13 + ASSIGN_GPIOY_PIN_PIN03 GPIO mananger - 0x1b4 + 0x70c 32 0x00000000 0x80000301 @@ -10809,9 +10587,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN14 + ASSIGN_GPIOY_PIN_PIN04 GPIO mananger - 0x1b8 + 0x710 32 0x00000000 0x80000301 @@ -10846,9 +10624,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN15 + ASSIGN_GPIOY_PIN_PIN05 GPIO mananger - 0x1bc + 0x714 32 0x00000000 0x80000301 @@ -10883,9 +10661,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN16 + ASSIGN_GPIOY_PIN_PIN06 GPIO mananger - 0x1c0 + 0x718 32 0x00000000 0x80000301 @@ -10920,9 +10698,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN17 + ASSIGN_GPIOY_PIN_PIN07 GPIO mananger - 0x1c4 + 0x71c 32 0x00000000 0x80000301 @@ -10957,9 +10735,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN18 + ASSIGN_GPIOZ_PIN_PIN00 GPIO mananger - 0x1c8 + 0x780 32 0x00000000 0x80000301 @@ -10994,9 +10772,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN19 + ASSIGN_GPIOZ_PIN_PIN01 GPIO mananger - 0x1cc + 0x784 32 0x00000000 0x80000301 @@ -11031,9 +10809,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN20 + ASSIGN_GPIOZ_PIN_PIN02 GPIO mananger - 0x1d0 + 0x788 32 0x00000000 0x80000301 @@ -11068,9 +10846,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN21 + ASSIGN_GPIOZ_PIN_PIN03 GPIO mananger - 0x1d4 + 0x78c 32 0x00000000 0x80000301 @@ -11105,9 +10883,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN22 + ASSIGN_GPIOZ_PIN_PIN04 GPIO mananger - 0x1d8 + 0x790 32 0x00000000 0x80000301 @@ -11142,9 +10920,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOD_PIN_PIN23 + ASSIGN_GPIOZ_PIN_PIN05 GPIO mananger - 0x1dc + 0x794 32 0x00000000 0x80000301 @@ -11179,9 +10957,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOX_PIN_PIN00 + ASSIGN_GPIOZ_PIN_PIN06 GPIO mananger - 0x680 + 0x798 32 0x00000000 0x80000301 @@ -11216,9 +10994,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - ASSIGN_GPIOX_PIN_PIN01 + ASSIGN_GPIOZ_PIN_PIN07 GPIO mananger - 0x684 + 0x79c 32 0x00000000 0x80000301 @@ -11252,1176 +11030,706 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + + + + ADC0 + ADC0 + ADC16 + 0xf0010000 + + 0x0 + 0x1464 + registers + + - ASSIGN_GPIOX_PIN_PIN02 - GPIO mananger - 0x688 + CONFIG_TRG0A + No description avaiable + 0x0 32 0x00000000 - 0x80000301 + 0xFF3F3F7F - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + CHAN3 + channel number for 4th conversion + 24 + 5 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 + INTEN2 + interupt enable for 3rd conversion + 21 1 read-write - - - - ASSIGN_GPIOX_PIN_PIN03 - GPIO mananger - 0x68c - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 + CHAN2 + channel number for 3rd conversion + 16 + 5 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN1 + interupt enable for 2nd conversion + 13 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 + CHAN1 + channel number for 2nd conversion + 8 + 5 read-write - - - - ASSIGN_GPIOX_PIN_PIN04 - GPIO mananger - 0x690 - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + QUEUE_EN + preemption queue enable control + 6 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN0 + interupt enable for 1st conversion + 5 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio + CHAN0 + channel number for 1st conversion 0 - 1 + 5 read-write - ASSIGN_GPIOX_PIN_PIN05 - GPIO mananger - 0x694 + CONFIG_TRG0B + No description avaiable + 0x4 32 0x00000000 - 0x80000301 + 0xFF3F3F7F - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + CHAN3 + channel number for 4th conversion + 24 + 5 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 + INTEN2 + interupt enable for 3rd conversion + 21 1 read-write - - - - ASSIGN_GPIOX_PIN_PIN06 - GPIO mananger - 0x698 - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 + CHAN2 + channel number for 3rd conversion + 16 + 5 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN1 + interupt enable for 2nd conversion + 13 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 + CHAN1 + channel number for 2nd conversion + 8 + 5 read-write - - - - ASSIGN_GPIOX_PIN_PIN07 - GPIO mananger - 0x69c - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + QUEUE_EN + preemption queue enable control + 6 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN0 + interupt enable for 1st conversion + 5 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio + CHAN0 + channel number for 1st conversion 0 - 1 + 5 read-write - ASSIGN_GPIOY_PIN_PIN00 - GPIO mananger - 0x700 + CONFIG_TRG0C + No description avaiable + 0x8 32 0x00000000 - 0x80000301 + 0xFF3F3F7F - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + CHAN3 + channel number for 4th conversion + 24 + 5 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 + INTEN2 + interupt enable for 3rd conversion + 21 1 read-write - - - - ASSIGN_GPIOY_PIN_PIN01 - GPIO mananger - 0x704 - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 + CHAN2 + channel number for 3rd conversion + 16 + 5 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN1 + interupt enable for 2nd conversion + 13 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 + CHAN1 + channel number for 2nd conversion + 8 + 5 read-write - - - - ASSIGN_GPIOY_PIN_PIN02 - GPIO mananger - 0x708 - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + QUEUE_EN + preemption queue enable control + 6 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN0 + interupt enable for 1st conversion + 5 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio + CHAN0 + channel number for 1st conversion 0 - 1 + 5 read-write - ASSIGN_GPIOY_PIN_PIN03 - GPIO mananger - 0x70c + CONFIG_TRG1A + No description avaiable + 0xc 32 0x00000000 - 0x80000301 + 0xFF3F3F7F - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + CHAN3 + channel number for 4th conversion + 24 + 5 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 + INTEN2 + interupt enable for 3rd conversion + 21 1 read-write - - - - ASSIGN_GPIOY_PIN_PIN04 - GPIO mananger - 0x710 - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + CHAN1 + channel number for 2nd conversion 8 - 2 + 5 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 1 read-write + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + - ASSIGN_GPIOY_PIN_PIN05 - GPIO mananger - 0x714 + CONFIG_TRG1B + No description avaiable + 0x10 32 0x00000000 - 0x80000301 + 0xFF3F3F7F - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN3 + interupt enable for 4th conversion + 29 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 + CHAN3 + channel number for 4th conversion + 24 + 5 read-write - - - - ASSIGN_GPIOY_PIN_PIN06 - GPIO mananger - 0x718 - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + INTEN2 + interupt enable for 3rd conversion + 21 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + CHAN2 + channel number for 3rd conversion + 16 + 5 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 + INTEN1 + interupt enable for 2nd conversion + 13 1 read-write - - - - ASSIGN_GPIOY_PIN_PIN07 - GPIO mananger - 0x71c - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN0 + interupt enable for 1st conversion + 5 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio + CHAN0 + channel number for 1st conversion 0 - 1 + 5 read-write - ASSIGN_GPIOY_PIN_PIN08 - GPIO mananger - 0x720 + CONFIG_TRG1C + No description avaiable + 0x14 32 0x00000000 - 0x80000301 + 0xFF3F3F7F - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + CHAN3 + channel number for 4th conversion + 24 + 5 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 + INTEN2 + interupt enable for 3rd conversion + 21 1 read-write - - - - ASSIGN_GPIOY_PIN_PIN09 - GPIO mananger - 0x724 - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 + CHAN2 + channel number for 3rd conversion + 16 + 5 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN1 + interupt enable for 2nd conversion + 13 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 + CHAN1 + channel number for 2nd conversion + 8 + 5 read-write - - - - ASSIGN_GPIOY_PIN_PIN10 - GPIO mananger - 0x728 - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + QUEUE_EN + preemption queue enable control + 6 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN0 + interupt enable for 1st conversion + 5 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio + CHAN0 + channel number for 1st conversion 0 - 1 + 5 read-write - ASSIGN_GPIOY_PIN_PIN11 - GPIO mananger - 0x72c + CONFIG_TRG2A + No description avaiable + 0x18 32 0x00000000 - 0x80000301 + 0xFF3F3F7F - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + CHAN3 + channel number for 4th conversion + 24 + 5 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 + INTEN2 + interupt enable for 3rd conversion + 21 1 read-write - - - - ASSIGN_GPIOZ_PIN_PIN00 - GPIO mananger - 0x780 - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 + CHAN2 + channel number for 3rd conversion + 16 + 5 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN1 + interupt enable for 2nd conversion + 13 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 + CHAN1 + channel number for 2nd conversion + 8 + 5 read-write - - - - ASSIGN_GPIOZ_PIN_PIN01 - GPIO mananger - 0x784 - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + QUEUE_EN + preemption queue enable control + 6 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN0 + interupt enable for 1st conversion + 5 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio + CHAN0 + channel number for 1st conversion 0 - 1 + 5 read-write - ASSIGN_GPIOZ_PIN_PIN02 - GPIO mananger - 0x788 + CONFIG_TRG2B + No description avaiable + 0x1c 32 0x00000000 - 0x80000301 + 0xFF3F3F7F - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + CHAN3 + channel number for 4th conversion + 24 + 5 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 + INTEN2 + interupt enable for 3rd conversion + 21 1 read-write - - - - ASSIGN_GPIOZ_PIN_PIN03 - GPIO mananger - 0x78c - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 + CHAN2 + channel number for 3rd conversion + 16 + 5 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN1 + interupt enable for 2nd conversion + 13 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 + CHAN1 + channel number for 2nd conversion + 8 + 5 read-write - - - - ASSIGN_GPIOZ_PIN_PIN04 - GPIO mananger - 0x790 - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + QUEUE_EN + preemption queue enable control + 6 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + INTEN0 + interupt enable for 1st conversion + 5 + 1 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio + CHAN0 + channel number for 1st conversion 0 - 1 + 5 read-write - ASSIGN_GPIOZ_PIN_PIN05 - GPIO mananger - 0x794 + CONFIG_TRG2C + No description avaiable + 0x20 32 0x00000000 - 0x80000301 + 0xFF3F3F7F - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 1 read-write - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 + CHAN3 + channel number for 4th conversion + 24 + 5 read-write - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 + INTEN2 + interupt enable for 3rd conversion + 21 1 read-write - - - - ASSIGN_GPIOZ_PIN_PIN06 - GPIO mananger - 0x798 - 32 - 0x00000000 - 0x80000301 - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN07 - GPIO mananger - 0x79c - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN08 - GPIO mananger - 0x7a0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN09 - GPIO mananger - 0x7a4 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN10 - GPIO mananger - 0x7a8 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - ASSIGN_GPIOZ_PIN_PIN11 - GPIO mananger - 0x7ac - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - - - ADC0 - ADC0 - ADC16 - 0xf0010000 - - 0x0 - 0x1464 - registers - - - - CONFIG_TRG0A - No description avaiable - 0x0 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 1 read-write @@ -12456,9 +11764,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - CONFIG_TRG0B + CONFIG_TRG3A No description avaiable - 0x4 + 0x24 32 0x00000000 0xFF3F3F7F @@ -12536,9 +11844,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - CONFIG_TRG0C + CONFIG_TRG3B No description avaiable - 0x8 + 0x28 32 0x00000000 0xFF3F3F7F @@ -12616,9 +11924,9 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - CONFIG_TRG1A + CONFIG_TRG3C No description avaiable - 0xc + 0x2c 32 0x00000000 0xFF3F3F7F @@ -12696,666 +12004,316 @@ bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - CONFIG_TRG1B + TRG_DMA_ADDR No description avaiable - 0x10 + 0x30 32 0x00000000 - 0xFF3F3F7F + 0xFFFFFFFC - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 read-write + + + + BUS_RESULT_CHN0 + No description avaiable + 0x400 + 32 + 0x00000000 + 0x0001FFFF + - CHAN2 - channel number for 3rd conversion + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write + read-only - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + BUS_RESULT_CHN1 + No description avaiable + 0x404 + 32 + 0x00000000 + 0x0001FFFF + - INTEN0 - interupt enable for 1st conversion - 5 + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 1 - read-write + read-only - CHAN0 - channel number for 1st conversion + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long 0 - 5 - read-write + 16 + read-only - CONFIG_TRG1C + BUS_RESULT_CHN2 No description avaiable - 0x14 + 0x408 32 0x00000000 - 0xFF3F3F7F + 0x0001FFFF - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write + read-only - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + BUS_RESULT_CHN3 + No description avaiable + 0x40c + 32 + 0x00000000 + 0x0001FFFF + - CHAN2 - channel number for 3rd conversion + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write + read-only - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + BUS_RESULT_CHN4 + No description avaiable + 0x410 + 32 + 0x00000000 + 0x0001FFFF + - INTEN0 - interupt enable for 1st conversion - 5 + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 1 - read-write + read-only - CHAN0 - channel number for 1st conversion + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long 0 - 5 - read-write + 16 + read-only - CONFIG_TRG2A + BUS_RESULT_CHN5 No description avaiable - 0x18 + 0x414 32 0x00000000 - 0xFF3F3F7F + 0x0001FFFF - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - CONFIG_TRG2B - No description avaiable - 0x1c - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 - 1 - read-write + read-only - CHAN0 - channel number for 1st conversion + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long 0 - 5 - read-write + 16 + read-only - CONFIG_TRG2C + BUS_RESULT_CHN6 No description avaiable - 0x20 + 0x418 32 0x00000000 - 0xFF3F3F7F + 0x0001FFFF - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 1 - read-write + read-only - CHAN0 - channel number for 1st conversion + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long 0 - 5 - read-write + 16 + read-only - CONFIG_TRG3A + BUS_RESULT_CHN7 No description avaiable - 0x24 + 0x41c 32 0x00000000 - 0xFF3F3F7F + 0x0001FFFF - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 1 - read-write + read-only - CHAN0 - channel number for 1st conversion + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long 0 - 5 - read-write + 16 + read-only - CONFIG_TRG3B + BUS_RESULT_CHN8 No description avaiable - 0x28 + 0x420 32 0x00000000 - 0xFF3F3F7F + 0x0001FFFF - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 1 - read-write + read-only - CHAN0 - channel number for 1st conversion + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long 0 - 5 - read-write + 16 + read-only - CONFIG_TRG3C + BUS_RESULT_CHN9 No description avaiable - 0x2c + 0x424 32 0x00000000 - 0xFF3F3F7F + 0x0001FFFF - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again 16 - 5 - read-write - - - INTEN1 - interupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interupt enable for 1st conversion - 5 1 - read-write + read-only - CHAN0 - channel number for 1st conversion + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long 0 - 5 - read-write - - - - - TRG_DMA_ADDR - No description avaiable - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write + 16 + read-only - BUS_RESULT_CHN0 + BUS_RESULT_CHN10 No description avaiable - 0x400 + 0x428 32 0x00000000 0x0001FFFF @@ -13382,9 +12340,9 @@ If wait_dis bit is 0, SW can get the current conversion result with holding the - BUS_RESULT_CHN1 + BUS_RESULT_CHN11 No description avaiable - 0x404 + 0x42c 32 0x00000000 0x0001FFFF @@ -13411,9 +12369,9 @@ If wait_dis bit is 0, SW can get the current conversion result with holding the - BUS_RESULT_CHN2 + BUS_RESULT_CHN12 No description avaiable - 0x408 + 0x430 32 0x00000000 0x0001FFFF @@ -13440,299 +12398,9 @@ If wait_dis bit is 0, SW can get the current conversion result with holding the - BUS_RESULT_CHN3 + BUS_RESULT_CHN13 No description avaiable - 0x40c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN4 - No description avaiable - 0x410 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN5 - No description avaiable - 0x414 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN6 - No description avaiable - 0x418 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN7 - No description avaiable - 0x41c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN8 - No description avaiable - 0x420 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN9 - No description avaiable - 0x424 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN10 - No description avaiable - 0x428 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN11 - No description avaiable - 0x42c - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN12 - No description avaiable - 0x430 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - BUS_RESULT_CHN13 - No description avaiable - 0x434 + 0x434 32 0x00000000 0x0001FFFF @@ -13916,14 +12584,14 @@ If cont_en is 0, this bit is not used 0x808 32 0x00000000 - 0x00000FFF + 0x00FFFFFF SEQ_WR_POINTER HW update this field after each dma write, it indicate the next dma write pointer. dma write address is (tar_addr+seq_wr_pointer)*4 0 - 12 + 24 read-only @@ -15829,8 +14497,12 @@ Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_num CLOCK_DIVIDER clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. -set to 3 can genenerate 50MHz adc_clk at 200MHz bus_clk. +0 for same adc_clk and bus_clk, +1 for 1:2, +2 for 1:3, +... +15 for 1:16 +Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk 0 4 read-write @@ -16749,7 +15421,7 @@ MUST set clock_period to 0 or 1 for adc16 reg access COV_END_CNT used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number). +should set to (21-convert_clock_number+1). 8 5 read-write @@ -23695,7 +22367,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -23709,7 +22382,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -23725,7 +22399,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -24006,7 +22681,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -24020,7 +22696,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -24036,7 +22713,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -24317,7 +22995,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -24331,7 +23010,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -24347,7 +23027,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -24628,7 +23309,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -24642,7 +23324,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -24658,7 +23341,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -24939,7 +23623,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -24953,7 +23638,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -24969,7 +23655,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -25250,7 +23937,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -25264,7 +23952,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -25280,7 +23969,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -25561,7 +24251,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -25575,7 +24266,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -25591,7 +24283,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -25872,7 +24565,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -25886,7 +24580,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -25902,7 +24597,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -30892,7 +29588,7 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c 0xf0 32 0x00000000 - 0xFDFFFFE7 + 0xFDFFFFEF FAULTI3EN @@ -30941,7 +29637,7 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c HWSHDWEDG When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. -This bit assign its which edge is used as shadow register hardware load event. +This bit assign its which edge is used as compare shadow register hardware load event. 1- Falling edge 0- Rising edge 24 @@ -31025,6 +29721,13 @@ User should write 1 to this bit after the active FAULT signal de-assert and befo 1 read-write + + TIMERRESET + set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear + 3 + 1 + read-write + FRCTIME This bit field select the force effective time @@ -31034,7 +29737,7 @@ User should write 1 to this bit after the active FAULT signal de-assert and befo 11: no force 1 2 - read-write + write-only SWFRC @@ -39520,7 +38223,7 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 0xf2000000 0x0 - 0x302c + 0x105c registers @@ -40119,152 +38822,6 @@ When set, this bit enables the VLAN Tag inverse matching. The frames that do not - - VERSION - Version Register - 0x20 - 32 - 0x00000000 - 0x0000FFFF - - - USERVER - User-defined Version - 8 - 8 - read-only - - - SNPSVER - Synopsys-defined Version (3.7) - 0 - 8 - read-only - - - - - DEBUGGING - Debug Register - 0x24 - 32 - 0x00000000 - 0x037F0377 - - - TXSTSFSTS - MTL TxStatus FIFO Full Status - When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot accept any more frames for transmission. This bit is reserved in the GMAC-AHB and GMAC-DMA configurations. - 25 - 1 - read-only - - - TXFSTS - MTL Tx FIFO Not Empty Status -When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission. - 24 - 1 - read-only - - - TWCSTS - MTL Tx FIFO Write Controller Status -When high, this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO. - 22 - 1 - read-only - - - TRCSTS - MTL Tx FIFO Read Controller Status -This field indicates the state of the Tx FIFO Read Controller: -- 00: IDLE state -- 01: READ state (transferring data to the MAC transmitter) -- 10: Waiting for TxStatus from the MAC transmitter -- 11: Writing the received TxStatus or flushing the Tx FIFO - 20 - 2 - read-only - - - TXPAUSED - MAC Transmitter in Pause -When high, this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-only mode) and hence does not schedule any frame for transmission. - 19 - 1 - read-only - - - TFCSTS - MAC Transmit Frame Controller Status -This field indicates the state of the MAC Transmit Frame Controller module: -- 00: IDLE state -- 01: Waiting for status of previous frame or IFG or backoff period to be over -- 10: Generating and transmitting a Pause frame (in the full-duplex mode) -- 11: Transferring input frame for transmission - 17 - 2 - read-only - - - TPESTS - MAC GMII or MII Transmit Protocol Engine Status - When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state. - 16 - 1 - read-only - - - RXFSTS - MTL RxFIFO Fill-Level Status -This field gives the status of the fill-level of the Rx FIFO: -- 00: Rx FIFO Empty -- 01: Rx FIFO fill-level below flow-control deactivate threshold -- 10: Rx FIFO fill-level above flow-control activate threshold -- 11: Rx FIFO Full - 8 - 2 - read-only - - - RRCSTS - MTL RxFIFO Read Controller State -This field gives the state of the Rx FIFO read Controller: -- 00: IDLE state -- 01: Reading frame data -- 10: Reading frame status (or timestamp) -- 11: Flushing the frame data and status - 5 - 2 - read-only - - - RWCSTS - MTL Rx FIFO Write Controller Active Status - When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. - 4 - 1 - read-only - - - RFCFCSTS - MAC Receive Frame FIFO Controller Status - When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module. - RFCFCSTS[1] represents the status of small FIFO Read controller. - RFCFCSTS[0] represents the status of small FIFO Write controller. - 1 - 2 - read-only - - - RPESTS - MAC GMII or MII Receive Protocol Engine Status -When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state. - 0 - 1 - read-only - - - RWKFRMFILT Remote Wake-Up Frame Filter Register @@ -40639,7 +39196,7 @@ When set, this bit disables the assertion of the interrupt signal because of the AE Address Enable - This bit is always set to 1. + This bit is RO. The bit value is fixed at 1. 31 1 read-only @@ -40918,15 +39475,8 @@ This field contains the lower 32 bits of the second 6-byte MAC address. The cont 0xd8 32 0x00000000 - 0x0001003F + 0x0000003F - - SMIDRXS - Delay SMII RX Data Sampling with respect to the SMII SYNC Signal When set, the first bit of the SMII RX data is sampled one cycle after the SMII SYNC signal. When reset, the first bit of the SMII RX data is sampled along with the SMII SYNC signal. If the SMII PHY Interface with source synchronous mode is selected during core configuration, this bit is reserved (RO with default value). - 16 - 1 - read-only - FALSCARDET False Carrier Detected @@ -41000,44 +39550,6 @@ When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Regist - - GPIO - General Purpose IO Register - 0xe0 - 32 - 0x00000000 - 0x0F0F0F0F - - - GPIT - No description avaiable - 24 - 4 - read-write - - - GPIE - No description avaiable - 16 - 4 - read-write - - - GPO - No description avaiable - 8 - 4 - read-write - - - GPIS - No description avaiable - 0 - 4 - read-write - - - MMC_CNTRL MMC Control establishes the operating mode of MMC. @@ -42159,16 +40671,16 @@ retried frames. - TXUNICASTFRAMES_GB - Number of good and bad unicast frames transmitted. - 0x13c + RXFRAMECOUNT_GB + Number of good and bad frames received + 0x180 32 0x00000000 0xFFFFFFFF FRMCNT - Number of good and bad unicast frames transmitted. + Number of good and bad frames received. 0 32 read-write @@ -42176,928 +40688,197 @@ retried frames. - TXMULTICASTFRAMES_GB - Number of good and bad multicast frames transmitted. - 0x140 + MMC_IPC_INTR_MASK_RX + MMC IPC Receive Checksum Offload Interrupt Mask maintains +the mask for the interrupt generated from the receive IPC statistic +counters. + 0x200 32 0x00000000 - 0xFFFFFFFF + 0x3FFF3FFF - FRMCNT - Number of good and bad multicast frames transmitted. - 0 - 32 + RXICMPEROIM + MMC Receive ICMP Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. + 29 + 1 read-write - - - - TXBROADCASTFRAMES_GB - Number of good and bad broadcast frames transmitted. - 0x144 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of good and bad broadcast frames transmitted. - 0 - 32 + RXICMPGOIM + MMC Receive ICMP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. + 28 + 1 read-write - - - - TXUNDERFLOWERROR - Number of frames aborted because of frame underflow error. - 0x148 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of frames aborted because of frame underflow error. - 0 - 32 + RXTCPEROIM + MMC Receive TCP Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. + 27 + 1 read-write - - - - TXSINGLECOL_G - Number of successfully transmitted frames after a single collision -in the half-duplex mode. - 0x14c - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of successfully transmitted frames after a single collision in the half-duplex mode. - 0 - 32 + RXTCPGOIM + MMC Receive TCP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. + 26 + 1 read-write - - - - TXMULTICOL_G - Number of successfully transmitted frames after multiple collisions -in the half-duplex mode. - 0x150 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of successfully transmitted frames after multiple collisions in the half-duplex mode. - 0 - 32 + RXUDPEROIM + MMC Receive UDP Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. + 25 + 1 read-write - - - - TXDEFERRED - Number of successfully transmitted frames after a deferral in the -half-duplex mode. - 0x154 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of successfully transmitted frames after a deferral in the half-duplex mode. - 0 - 32 + RXUDPGOIM + MMC Receive IPV6 No Payload Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. + 24 + 1 read-write - - - - TXLATECOL - Number of frames aborted because of late collision error - 0x158 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of frames aborted because of late collision error. - 0 - 32 + RXIPV6NOPAYOIM + MMC Receive IPV6 Header Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. + 23 + 1 read-write - - - - TXEXESSCOL - Number of frames aborted because of excessive (16) collision -errors - 0x15c - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of frames aborted because of excessive (16) collision errors. - 0 - 32 + RXIPV6HEROIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 22 + 1 read-write - - - - TXCARRIERERROR - Number of frames aborted because of carrier sense error (no -carrier or loss of carrier). - 0x160 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of frames aborted because of carrier sense error (no carrier or loss of carrier). - 0 - 32 + RXIPV6GOIM + MMC Receive IPV6 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. + 21 + 1 read-write - - - - TXOCTETCOUNT_G - Number of bytes transmitted, exclusive of preamble, only in good -frames. - 0x164 - 32 - 0x00000000 - 0xFFFFFFFF - - BYTECNT - Number of bytes transmitted, exclusive of preamble, only in good frames. - 0 - 32 + RXIPV4UDSBLOIM + MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. + 20 + 1 read-write - - - - TXFRAMECOUNT_G - Number of good frames transmitted - 0x168 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of good frames transmitted. - 0 - 32 + RXIPV4FRAGOIM + MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. + 19 + 1 read-write - - - - TXEXCESSDEF - Number of frames aborted because of excessive deferral error -(deferred for more than two max-sized frame times). - 0x16c - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of frames aborted because of excessive deferral error (deferred for more than two max-sized frame times). - 0 - 32 + RXIPV4NOPAYOIM + MMC Receive IPV4 No Payload Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. + 18 + 1 read-write - - - - TXPAUSEFRAMES - Number of good Pause frames transmitted - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of good Pause frames transmitted. - 0 - 32 + RXIPV4HEROIM + MMC Receive IPV4 Header Error Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. + 17 + 1 read-write - - - - TXVLANFRAMES_G - Number of good VLAN frames transmitted, exclusive of retried -frames. - 0x174 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of good VLAN frames transmitted, exclusive of retried frames. - 0 - 32 + RXIPV4GOIM + MMC Receive IPV4 Good Octet Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. + 16 + 1 read-write - - - - TXOVERSIZE_G - Number of frames transmitted without errors and with length -greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged -frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC -Configuration Register)). - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). - 0 - 32 + RXICMPERFIM + MMC Receive ICMP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. + 13 + 1 read-write - - - - RXFRAMECOUNT_GB - Number of good and bad frames received - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of good and bad frames received. - 0 - 32 + RXICMPGFIM + MMC Receive ICMP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. + 12 + 1 read-write - - - - RXOCTETCOUNT_G - Number of bytes received, exclusive of preamble, only in good -frames. - 0x184 - 32 - 0x00000000 - 0xFFFFFFFF - - BYTECNT - Number of bytes received, exclusive of preamble, in good and bad frames. - 0 - 32 + RXTCPERFIM + MMC Receive TCP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. + 11 + 1 read-write - - - - RXOCTETCOUNT_GB - Number of bytes received, exclusive of preamble, in good and bad -frames. - 0x188 - 32 - 0x00000000 - 0xFFFFFFFF - - BYTECNT - Number of bytes received, exclusive of preamble, only in good frames. - 0 - 32 + RXTCPGFIM + MMC Receive TCP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. + 10 + 1 read-write - - - - RXBROADCASTFRAMES_G - Number of good broadcast frames received - 0x18c - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of good broadcast frames received. - 0 - 32 + RXUDPERFIM + MMC Receive UDP Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. + 9 + 1 read-write - - - - RXMULTICASTFRAMES_G - Number of good multicast frames received - 0x190 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of good multicast frames received. - 0 - 32 + RXUDPGFIM + MMC Receive UDP Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. + 8 + 1 read-write - - - - RXCRCERROR - Number of frames received with CRC error - 0x194 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of frames received with CRC error. - 0 - 32 + RXIPV6NOPAYFIM + MMC Receive IPV6 No Payload Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. + 7 + 1 read-write - - - - RXALIGNMENTERROR - Number of frames received with alignment (dribble) error. Valid -only in 10/100 mode - 0x198 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of frames received with alignment (dribble) error. Valid only in 10/100 mode. - 0 - 32 + RXIPV6HERFIM + MMC Receive IPV6 Header Error Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. + 6 + 1 read-write - - - - RXRUNTERROR - Number of frames received with runt (<64 bytes and CRC error) -error. - 0x19c - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of frames received with runt (<64 bytes and CRC error) error. - 0 - 32 - read-write - - - - - RXJABBERERROR - Number of giant frames received with length (including CRC) -greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with -CRC error. If Jumbo Frame mode is enabled, then frames of -length greater than 9,018 bytes (9,022 for VLAN tagged) are -considered as giant frames. - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. - 0 - 32 - read-write - - - - - RXUNDERSIZE_G - Number of frames received with length less than 64 bytes, without -any errors. - 0x1a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with length less than 64 bytes, without any errors. - 0 - 32 - read-write - - - - - RXOVERSIZE_G - Number of frames received without errors, with length greater -than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 -bytes if enabled in Bit 27 of Register 0 (MAC Configuration -Register)) - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). - 0 - 32 - read-write - - - - - RX64OCTETS_GB - Number of good and bad frames received with length 64 bytes, -exclusive of preamble. - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length 64 bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX65TO127OCTETS_GB - No description avaiable - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX128TO255OCTETS_GB - No description avaiable - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX256TO511OCTETS_GB - Number of good and bad frames received with length between -256 and 511 (inclusive) bytes, exclusive of preamble. - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX512TO1023OCTETS_GB - Number of good and bad frames received with length between -512 and 1023 (inclusive) bytes, exclusive of preamble. - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX1024TOMAXOCTETS_GB - Number of good and bad frames received with length between -1024 and maxsize (inclusive) bytes, exclusive of preamble. - 0x1c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - RXUNICASTFRAMES_G - Number of received good unicast frames. - 0x1c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of received good unicast frames. - 0 - 32 - read-write - - - - - RXLENGTHERROR - Number of frames received with length error (Length type field ≠ -frame size), for all frames with valid length field. - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with length error (Length type field ≠ frame size), for all frames with valid length field. - 0 - 32 - read-write - - - - - RXOUTOFRANGETYPE - Number of frames received with length field not equal to the valid -frame size (greater than 1,500 but less than 1,536). - 0x1cc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). - 0 - 32 - read-write - - - - - RXPAUSEFRAMES - Number of good and valid Pause frames received. - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and valid Pause frames received. - 0 - 32 - read-write - - - - - RXFIFOOVERFLOW - Number of missed received frames because of FIFO overflow. -This counter is not present in the GMAC-CORE configuration. - 0x1d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of missed received frames because of FIFO overflow. This counter is not present in the GMAC-CORE configuration. - 0 - 32 - read-write - - - - - RXVLANFRAMES_GB - Number of good and bad VLAN frames received. - 0x1d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad VLAN frames received. - 0 - 32 - read-write - - - - - RXWATCHDOGERROR - Number of frames received with error because of watchdog -timeout error (frames with a data load larger than 2,048 bytes or -the value programmed in Register 55 (Watchdog Timeout -Register)). - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with error because of watchdog timeout error (frames with a data load larger than 2,048 bytes or the value programmed in Register 55 (Watchdog Timeout Register)). - 0 - 32 - read-write - - - - - RXRCVERROR - Number of frames received with Receive error or Frame Extension -error on the GMII or MII interface. - 0x1e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with Receive error or Frame Extension error on the GMII or MII interface. - 0 - 32 - read-write - - - - - RXCTRLFRAMES_G - Number of received good control frames - 0x1e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of received good control frames. - 0 - 32 - read-write - - - - - MMC_IPC_INTR_MASK_RX - MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. - 0x200 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - 26 - 1 - read-write - - - RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIM - MMC Receive ICMP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIM - MMC Receive ICMP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIM - MMC Receive TCP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIM - MMC Receive TCP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIM - MMC Receive UDP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIM - MMC Receive UDP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIM - MMC Receive IPV6 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIM - MMC Receive IPV6 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIM - MMC Receive IPV6 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 + RXIPV6GFIM + MMC Receive IPV6 Good Frame Counter Interrupt Mask +Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. + 5 + 1 read-write @@ -43397,106 +41178,161 @@ ICMP payload - RXIPV4_HDRERR_FRMS - Number of IPv4 datagrams received with header (checksum, -length, or version mismatch) errors - 0x214 + L3_L4_CFG_0_L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x400 32 0x00000000 - 0xFFFFFFFF + 0x003DFFFD - FRMCNT - Number of IPv4 datagrams received with header (checksum, length, or version mismatch) errors - 0 - 32 + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 read-write - - - - RXIPV4_NOPAY_FRMS - Number of IPv4 datagram frames received that did not have a -TCP, UDP, or ICMP payload processed by the Checksum engine - 0x218 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine - 0 - 32 + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 read-write - - - - RXIPV4_FRAG_FRMS - Number of good IPv4 datagrams with fragmentation - 0x21c - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of good IPv4 datagrams with fragmentation - 0 - 32 + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 read-write - - - - RXIPV4_UDSBL_FRMS - Number of good IPv4 datagrams received that had a UDP -payload with checksum disabled - 0x220 - 32 - 0x00000000 - 0xFFFFFFFF - - FRMCNT - Number of good IPv4 datagrams received that had a UDP payload with checksum disabled - 0 - 32 + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 read-write - - + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + 0 + 1 + read-write + + + - RXIPV6_GD_FRMS - Number of good IPv6 datagrams received with TCP, UDP, or -ICMP payloads - 0x224 + L3_L4_CFG_0_L4_ADDR + Layer 4 Address Register + 0x404 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. 0 - 32 + 16 read-write - RXIPV6_HDRERR_FRMS - Number of IPv6 datagrams received with header errors (length or -version mismatch) - 0x228 + L3_L4_CFG_0_L3_ADDR_0 + Layer 3 Address 0 Register + 0x410 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of IPv6 datagrams received with header errors (length or version mismatch) + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. 0 32 read-write @@ -43504,18 +41340,17 @@ version mismatch) - RXIPV6_NOPAY_FRMS - Number of IPv6 datagram frames received that did not have a -TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with -fragmentation or security extension headers - 0x22c + L3_L4_CFG_0_L3_ADDR_1 + Layer 3 Address 1 Register + 0x414 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. 0 32 read-write @@ -43523,18 +41358,17 @@ fragmentation or security extension headers - RXUDP_GD_FRMS - Number of good IP datagrams with a good UDP payload. This -counter is not updated when the rxipv4_udsbl_frms counter is -incremented. - 0x230 + L3_L4_CFG_0_L3_ADDR_2 + Layer 3 Address 2 Register + 0x418 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented. + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. 0 32 read-write @@ -43542,17 +41376,16 @@ incremented. - RXUDP_ERR_FRMS - Number of good IP datagrams whose UDP payload has a -checksum error - 0x234 + L3_L4_CFG_0_L3_ADDR_3 + Layer 3 Address 3 Register + 0x41c 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of good IP datagrams whose UDP payload has a checksum error + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. 0 32 read-write @@ -43560,34 +41393,43 @@ checksum error - RXTCP_GD_FRMS - Number of good IP datagrams with a good TCP payload - 0x238 + L3_L4_CFG_1_L4_ADDR + Layer 4 Address Register + 0x434 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of good IP datagrams with a good TCP payload + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. 0 - 32 + 16 read-write - RXTCP_ERR_FRMS - Number of good IP datagrams whose TCP payload has a -checksum error - 0x23c + L3_L4_CFG_1_L3_ADDR_0 + Layer 3 Address 0 Register + 0x440 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of good IP datagrams whose TCP payload has a checksum error + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. 0 32 read-write @@ -43595,16 +41437,17 @@ checksum error - RXICMP_GD_FRMS - Number of good IP datagrams with a good ICMP payload - 0x240 + L3_L4_CFG_1_L3_ADDR_1 + Layer 3 Address 1 Register + 0x444 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of good IP datagrams with a good ICMP payload + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. 0 32 read-write @@ -43612,17 +41455,17 @@ checksum error - RXICMP_ERR_FRMS - Number of good IP datagrams whose ICMP payload has a -checksum error - 0x244 + L3_L4_CFG_1_L3_ADDR_2 + Layer 3 Address 2 Register + 0x448 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of good IP datagrams whose ICMP payload has a checksum error + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. 0 32 read-write @@ -43630,19 +41473,16 @@ checksum error - RXIPV4_GD_OCTETS - Number of bytes received in good IPv4 datagrams encapsulating -TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad -bytes are not included in this counter or in the octet counters listed -below). - 0x250 + L3_L4_CFG_1_L3_ADDR_3 + Layer 3 Address 3 Register + 0x44c 32 0x00000000 0xFFFFFFFF - BYTECNT - Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in the octet counters listed below). + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. 0 32 read-write @@ -43650,37 +41490,43 @@ below). - RXIPV4_HDRERR_OCTETS - Number of bytes received in IPv4 datagrams with header errors -(checksum, length, version mismatch). The value in the Length -field of IPv4 header is used to update this counter. - 0x254 + L3_L4_CFG_2_L4_ADDR + Layer 4 Address Register + 0x464 32 0x00000000 0xFFFFFFFF - BYTECNT - Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. 0 - 32 + 16 read-write - RXIPV4_NOPAY_OCTETS - Number of bytes received in IPv4 datagrams that did not have a -TCP, UDP, or ICMP payload. The value in the IPv4 header’s -Length field is used to update this counter. - 0x258 + L3_L4_CFG_2_L3_ADDR_0 + Layer 3 Address 0 Register + 0x470 32 0x00000000 0xFFFFFFFF - BYTECNT - Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 header’s Length field is used to update this counter. + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. 0 32 read-write @@ -43688,18 +41534,17 @@ Length field is used to update this counter. - RXIPV4_FRAG_OCTETS - Number of bytes received in fragmented IPv4 datagrams. The -value in the IPv4 header’s Length field is used to update this -counter - 0x25c + L3_L4_CFG_2_L3_ADDR_1 + Layer 3 Address 1 Register + 0x474 32 0x00000000 0xFFFFFFFF - BYTECNT - Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header’s Length field is used to update this counter. + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. 0 32 read-write @@ -43707,17 +41552,17 @@ counter - RXIPV4_UDSBL_OCTETS - Number of bytes received in a UDP segment that had the UDP -checksum disabled. This counter does not count IP Header bytes. - 0x260 + L3_L4_CFG_2_L3_ADDR_2 + Layer 3 Address 2 Register + 0x478 32 0x00000000 0xFFFFFFFF - BYTECNT - Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. 0 32 read-write @@ -43725,17 +41570,16 @@ checksum disabled. This counter does not count IP Header bytes. - RXIPV6_GD_OCTETS - Number of bytes received in good IPv6 datagrams encapsulating -TCP, UDP or ICMPv6 data - 0x264 + L3_L4_CFG_2_L3_ADDR_3 + Layer 3 Address 3 Register + 0x47c 32 0x00000000 0xFFFFFFFF - BYTECNT - Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. 0 32 read-write @@ -43743,37 +41587,43 @@ TCP, UDP or ICMPv6 data - RXIPV6_HDRERR_OCTETS - Number of bytes received in IPv6 datagrams with header errors -(length, version mismatch). The value in the IPv6 header’s Length -field is used to update this counter. - 0x268 + L3_L4_CFG_3_L4_ADDR + Layer 4 Address Register + 0x494 32 0x00000000 0xFFFFFFFF - BYTECNT - Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 header’s Length field is used to update this counter. + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. 0 - 32 + 16 read-write - RXIPV6_NOPAY_OCTETS - Number of bytes received in IPv6 datagrams that did not have a -TCP, UDP, or ICMP payload. The value in the IPv6 header’s -Length field is used to update this counter. - 0x26c + L3_L4_CFG_3_L3_ADDR_0 + Layer 3 Address 0 Register + 0x4a0 32 0x00000000 0xFFFFFFFF - BYTECNT - Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 header’s Length field is used to update this counter. + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. 0 32 read-write @@ -43781,17 +41631,17 @@ Length field is used to update this counter. - RXUDP_GD_OCTETS - Number of bytes received in a good UDP segment. This counter -(and the counters below) does not count IP header bytes. - 0x270 + L3_L4_CFG_3_L3_ADDR_1 + Layer 3 Address 1 Register + 0x4a4 32 0x00000000 0xFFFFFFFF - BYTECNT - Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes. + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. 0 32 read-write @@ -43799,17 +41649,17 @@ Length field is used to update this counter. - RXUDP_ERR_OCTETS - Number of bytes received in a UDP segment that had checksum -errors - 0x274 + L3_L4_CFG_3_L3_ADDR_2 + Layer 3 Address 2 Register + 0x4a8 32 0x00000000 0xFFFFFFFF - BYTECNT - Number of bytes received in a UDP segment that had checksum errors + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. 0 32 read-write @@ -43817,16 +41667,16 @@ errors - RXTCP_GD_OCTETS - Number of bytes received in a good TCP segment - 0x278 + L3_L4_CFG_3_L3_ADDR_3 + Layer 3 Address 3 Register + 0x4ac 32 0x00000000 0xFFFFFFFF - BYTECNT - Number of bytes received in a good TCP segment + L3A30 + Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. 0 32 read-write @@ -43834,152 +41684,240 @@ errors - RXTCP_ERR_OCTETS - Number of bytes received in a TCP segment with checksum -errors - 0x27c + VLAN_TAG_INC_RPL + VLAN Tag Inclusion or Replacement Register + 0x584 32 0x00000000 - 0xFFFFFFFF + 0x000FFFFF - BYTECNT - Number of bytes received in a TCP segment with checksum errors + CSVL + C-VLAN or S-VLAN + When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. + 19 + 1 + read-write + + + VLP + VLAN Priority Control +When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. + 18 + 1 + read-write + + + VLC + VLAN Tag Control in Transmit Frames +- 2’b00: No VLAN tag deletion, insertion, or replacement +- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. +- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. +- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). Note: Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. + 16 + 2 + read-write + + + VLT + VLAN Tag for Transmit Frames + This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. 0 - 32 + 16 read-write - RXICMP_GD_OCTETS - Number of bytes received in a good ICMP segment - 0x280 + VLAN_HASH + VLAN Hash Table Register + 0x588 32 0x00000000 - 0xFFFFFFFF + 0x0000FFFF - BYTECNT - Number of bytes received in a good ICMP segment + VLHT + VLAN Hash Table + This field contains the 16-bit VLAN Hash Table. 0 - 32 + 16 read-write - L3_L4_CFG_0_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x400 + TS_CTRL + Timestamp Control Register + 0x700 32 0x00000000 - 0x003DFFFD + 0x1F07FF3F - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 + ATSEN3 + Auxiliary Snapshot 3 Enable +This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. + 28 1 read-write - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 + ATSEN2 + Auxiliary Snapshot 2 Enable +This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. + 27 1 read-write - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 + ATSEN1 + Auxiliary Snapshot 1 Enable +This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. + 26 1 read-write - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + ATSEN0 + Auxiliary Snapshot 0 Enable +This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. + 25 + 1 + read-write + + + ATSFC + Auxiliary Snapshot FIFO Clear +When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. + 24 + 1 + read-write + + + TSENMACADDR + Enable MAC address for PTP Frame Filtering +When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. 18 1 read-write - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + SNAPTYPSEL + Select PTP packets for Taking Snapshots + These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. 16 + 2 + read-write + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master +When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. + 15 1 read-write - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + TSEVNTENA + Enable Timestamp Snapshot for Event Messages +When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. + 14 + 1 + read-write + + + TSIPV4ENA + Enable Processing of PTP Frames Sent over IPv4-UDP + When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. + 13 + 1 + read-write + + + TSIPV6ENA + Enable Processing of PTP Frames Sent over IPv6-UDP +When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. + 12 + 1 + read-write + + + TSIPENA + Enable Processing of PTP over Ethernet Frames +When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets 11 - 5 + 1 read-write - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 + TSVER2ENA + Enable PTP packet Processing for Version 2 Format +When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. + 10 + 1 read-write - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + TSCTRLSSR + Timestamp Digital or Binary Rollover Control +When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. + 9 + 1 + read-write + + + TSENALL + Enable Timestamp for All Frames +When set, the timestamp snapshot is enabled for all frames received by the MAC. + 8 + 1 + read-write + + + TSADDREG + Addend Reg Update +When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. 5 1 read-write - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + TSTRIG + Timestamp Interrupt Trigger Enable +When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt. 4 1 read-write - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + TSUPDT + Timestamp Update +When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. 3 1 read-write - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + TSINIT + Timestamp Initialize +When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. 2 1 read-write - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + TSCFUPDT + Timestamp Fine or Coarse Update +When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. + 1 + 1 + read-write + + + TSENA + Timestamp Enable +When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. 0 1 read-write @@ -43987,43 +41925,71 @@ When set, this bit indicates that the Layer 3 IP Source Address field is enabled - L3_L4_CFG_0_L4_ADDR - Layer 4 Address Register - 0x404 + SUB_SEC_INCR + Sub-Second Increment Register + 0x704 32 0x00000000 - 0xFFFFFFFF + 0x000000FF - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 + SSINC + Sub-second Increment Value +The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. + 0 + 8 read-write + + + + SYST_SEC + System Time - Seconds Register + 0x708 + 32 + 0x00000000 + 0xFFFFFFFF + - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + TSS + Timestamp Second + The value in this field indicates the current value in seconds of the System Time maintained by the MAC. 0 - 16 - read-write + 32 + read-only - L3_L4_CFG_0_L3_ADDR_0 - Layer 3 Address 0 Register - 0x410 + SYST_NSEC + System Time - Nanoseconds Register + 0x70c + 32 + 0x00000000 + 0x7FFFFFFF + + + TSSS + Timestamp Sub Seconds + The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. + 0 + 31 + read-only + + + + + SYST_SEC_UPD + System Time - Seconds Update Register + 0x710 32 0x00000000 0xFFFFFFFF - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + TSS + Timestamp Second + The value in this field indicates the time in seconds to be initialized or added to the system time. 0 32 read-write @@ -44031,35 +41997,43 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - L3_L4_CFG_0_L3_ADDR_1 - Layer 3 Address 1 Register - 0x414 + SYST_NSEC_UPD + System Time - Nanoseconds Update Register + 0x714 32 0x00000000 0xFFFFFFFF - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + ADDSUB + Add or Subtract Time + When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. + 31 + 1 + read-write + + + TSSS + Timestamp Sub Seconds +The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. 0 - 32 + 31 read-write - L3_L4_CFG_0_L3_ADDR_2 - Layer 3 Address 2 Register - 0x418 + TS_ADDEND + Timestamp Addend Register + 0x718 32 0x00000000 0xFFFFFFFF - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + TSAR + Timestamp Addend Register +This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. 0 32 read-write @@ -44067,16 +42041,17 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - L3_L4_CFG_0_L3_ADDR_3 - Layer 3 Address 3 Register - 0x41c + TGTTM_SEC + Target Time Seconds Register + 0x71c 32 0x00000000 0xFFFFFFFF - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + TSTR + Target Time Seconds Register + This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). 0 32 read-write @@ -44084,179 +42059,330 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - L3_L4_CFG_1_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x430 + TGTTM_NSEC + Target Time Nanoseconds Register + 0x720 32 0x00000000 - 0x003DFFFD + 0xFFFFFFFF - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 + TRGTBUSY + Target Time Register Busy + The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. + 31 1 read-write - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 + TTSLO + Target Timestamp Low Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 read-write + + + + SYSTM_H_SEC + System Time - Higher Word Seconds Register + 0x724 + 32 + 0x00000000 + 0x0000FFFF + - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 + TSHWR + Timestamp Higher Word Register +This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. + 0 + 16 read-write + + + + TS_STATUS + Timestamp Status Register + 0x728 + 32 + 0x00000000 + 0x3F0F03FF + - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 + ATSNS + Number of Auxiliary Timestamp Snapshots +This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + 25 + 5 + read-only + + + ATSSTM + Auxiliary Timestamp Snapshot Trigger Missed + This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. + 24 1 - read-write + read-only - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + ATSSTN + Auxiliary Timestamp Snapshot Trigger Identifier +These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: - Bit 16: Auxiliary trigger 0 - Bit 17: Auxiliary trigger 1 - Bit 18: Auxiliary trigger 2 - Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. 16 + 4 + read-only + + + TSTRGTERR3 + Timestamp Target Time Error +This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. + 9 1 - read-write + read-only - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write + TSTARGT3 + Timestamp Target Time Reached for Target Time PPS3 +When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). + 8 + 1 + read-only - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + TSTRGTERR2 + No description avaiable + 7 + 1 + read-only + + + TSTARGT2 + No description avaiable 6 - 5 - read-write + 1 + read-only - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + TSTRGTERR1 + No description avaiable 5 1 - read-write + read-only - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + TSTARGT1 + No description avaiable 4 1 - read-write + read-only - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + TSTRGTERR + No description avaiable 3 1 - read-write + read-only - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + AUXTSTRIG + No description avaiable 2 1 - read-write + read-only - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + TSTARGT + No description avaiable + 1 + 1 + read-only + + + TSSOVF + No description avaiable 0 1 - read-write + read-only - L3_L4_CFG_1_L4_ADDR - Layer 4 Address Register - 0x434 + PPS_CTRL + PPS Control Register + 0x72c 32 0x00000000 - 0xFFFFFFFF + 0x6767777F - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + TRGTMODSEL3 + Target Time Register Mode for PPS3 Output +This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. + 29 + 2 + read-write + + + PPSCMD3 + Flexible PPS3 Output Control +This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 24 + 3 + read-write + + + TRGTMODSEL2 + Target Time Register Mode for PPS2 Output +This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. + 21 + 2 + read-write + + + PPSCMD2 + Flexible PPS2 Output Control +This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. 16 - 16 + 3 read-write - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + TRGTMODSEL1 + Target Time Register Mode for PPS1 Output +This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. + 13 + 2 + read-write + + + PPSEN1 + Flexible PPS1 Output Mode Enable +When set high, Bits[10:8] function as PPSCMD. + 12 + 1 + read-write + + + PPSCMD1 + Flexible PPS1 Output Control +This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. + 8 + 3 + read-write + + + TRGTMODSEL0 + Target Time Register Mode for PPS0 Output + This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: +- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. +- 01: Reserved +- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. +- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. + 5 + 2 + read-write + + + PPSEN0 + Flexible PPS Output Mode Enable +When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. + 4 + 1 + read-write + + + PPSCTRLCMD0 + PPSCTRL0: PPS0 Output Frequency Control +This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: +- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. +- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. +- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. +- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... +- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) +PPSCMD0: Flexible PPS0 Output Control +0000: No Command +0001: START Single Pulse +This command generates single pulse rising at the start point defined in +Target Time Registers and of a duration defined +in the PPS0 Width Register. +0010: START Pulse Train +This command generates the train of pulses rising at the start point +defined in the Target Time Registers and of a duration defined in the +PPS0 Width Register and repeated at interval defined in the PPS +Interval Register. By default, the PPS pulse train is free-running unless +stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train +immediately’ commands. +0011: Cancel START +This command cancels the START Single Pulse and START Pulse Train +commands if the system time has not crossed the programmed start +time. +0100: STOP Pulse train at time +This command stops the train of pulses initiated by the START Pulse +Train command (PPSCMD = 0010) after the time programmed in the +Target Time registers elapses. +0101: STOP Pulse Train immediately +This command immediately stops the train of pulses initiated by the +START Pulse Train command (PPSCMD = 0010). +0110: Cancel STOP Pulse train +This command cancels the STOP pulse train at time command if the +programmed stop time has not elapsed. The PPS pulse train becomes +free-running on the successful execution of this command. +0111-1111: Reserved +Note: These bits get cleared automatically 0 - 16 + 4 read-write - L3_L4_CFG_1_L3_ADDR_0 - Layer 3 Address 0 Register - 0x440 + AUX_TS_NSEC + Auxiliary Timestamp - Nanoseconds Register + 0x730 + 32 + 0x00000000 + 0x7FFFFFFF + + + AUXTSLO + Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. + 0 + 31 + read-only + + + + + AUX_TS_SEC + Auxiliary Timestamp - Seconds Register + 0x734 32 0x00000000 0xFFFFFFFF - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + AUXTSHI + Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. 0 32 - read-write + read-only - L3_L4_CFG_1_L3_ADDR_1 - Layer 3 Address 1 Register - 0x444 + PPS0_INTERVAL + PPS0 Interval Register + 0x760 32 0x00000000 0xFFFFFFFF - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + PPSINT + PPS0 Output Signal Interval +These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. 0 32 read-write @@ -44264,17 +42390,17 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - L3_L4_CFG_1_L3_ADDR_2 - Layer 3 Address 2 Register - 0x448 + PPS0_WIDTH + PPS0 Width Register + 0x764 32 0x00000000 0xFFFFFFFF - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + PPSWIDTH + PPS0 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. 0 32 read-write @@ -44282,16 +42408,17 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - L3_L4_CFG_1_L3_ADDR_3 - Layer 3 Address 3 Register - 0x44c + PPS_1_TGTTM_SEC + PPS Target Time Seconds Register + 0x780 32 0x00000000 0xFFFFFFFF - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + TSTRH1 + PPS1 Target Time Seconds Register +This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). 0 32 read-write @@ -44299,161 +42426,159 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - L3_L4_CFG_2_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x460 + PPS_1_TGTTM_NSEC + PPS Target Time Nanoseconds Register + 0x784 32 0x00000000 - 0x003DFFFD + 0xFFFFFFFF - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 + TRGTBUSY1 + PPS1 Target Time Register Busy +The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 1 read-write - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 + TTSL1 + Target Time Low for PPS1 Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + 0 + 31 read-write + + + + PPS_1_INTERVAL + PPS Interval Register + 0x788 + 32 + 0x00000000 + 0xFFFFFFFF + - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 + PPSINT + PPS1 Output Signal Interval +These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 read-write + + + + PPS_1_WIDTH + PPS Width Register + 0x78c + 32 + 0x00000000 + 0xFFFFFFFF + - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 + PPSWIDTH + PPS1 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + 0 + 32 read-write + + + + PPS_2_TGTTM_SEC + PPS2 Target Time Seconds Register + 0x7a0 + 32 + 0x00000000 + 0xFFFFFFFF + - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 + TSTRH1 + PPS1 Target Time Seconds Register +This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + 0 + 32 read-write + + + + PPS_2_TGTTM_NSEC + PPS Target Time Nanoseconds Register + 0x7a4 + 32 + 0x00000000 + 0xFFFFFFFF + - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 + TRGTBUSY1 + PPS1 Target Time Register Busy +The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 1 read-write - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. + TTSL1 + Target Time Low for PPS1 Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. 0 - 1 + 31 read-write - L3_L4_CFG_2_L4_ADDR - Layer 4 Address Register - 0x464 + PPS_2_INTERVAL + PPS Interval Register + 0x7a8 32 0x00000000 0xFFFFFFFF - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 + PPSINT + PPS1 Output Signal Interval +These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + 0 + 32 read-write + + + + PPS_2_WIDTH + PPS Width Register + 0x7ac + 32 + 0x00000000 + 0xFFFFFFFF + - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. + PPSWIDTH + PPS1 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. 0 - 16 + 32 read-write - L3_L4_CFG_2_L3_ADDR_0 - Layer 3 Address 0 Register - 0x470 + PPS_3_TGTTM_SEC + PPS3 Target Time Seconds Register + 0x7c0 32 0x00000000 0xFFFFFFFF - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + TSTRH1 + PPS1 Target Time Seconds Register +This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). 0 32 read-write @@ -44461,35 +42586,43 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - L3_L4_CFG_2_L3_ADDR_1 - Layer 3 Address 1 Register - 0x474 + PPS_3_TGTTM_NSEC + PPS Target Time Nanoseconds Register + 0x7c4 32 0x00000000 0xFFFFFFFF - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + TRGTBUSY1 + PPS1 Target Time Register Busy +The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + 31 + 1 + read-write + + + TTSL1 + Target Time Low for PPS1 Register +This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. 0 - 32 + 31 read-write - L3_L4_CFG_2_L3_ADDR_2 - Layer 3 Address 2 Register - 0x478 + PPS_3_INTERVAL + PPS Interval Register + 0x7c8 32 0x00000000 0xFFFFFFFF - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + PPSINT + PPS1 Output Signal Interval +These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. 0 32 read-write @@ -44497,16 +42630,17 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - L3_L4_CFG_2_L3_ADDR_3 - Layer 3 Address 3 Register - 0x47c + PPS_3_WIDTH + PPS Width Register + 0x7cc 32 0x00000000 0xFFFFFFFF - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + PPSWIDTH + PPS1 Output Signal Width +These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. 0 32 read-write @@ -44514,179 +42648,157 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - L3_L4_CFG_3_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x490 + DMA_BUS_MODE + Bus Mode Register + 0x1000 32 0x00000000 - 0x003DFFFD + 0xBFFFFFFF - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 + RIB + Rebuild INCRx Burst +When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. + 31 1 read-write - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 + PRWG + Channel Priority +Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. +- 00: The priority weight is 1. +- 01: The priority weight is 2. +- 10: The priority weight is 3. +- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). + 28 + 2 read-write - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 + TXPR + Transmit Priority +When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). + 27 1 read-write - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 + MB + Mixed Burst +When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. + 26 1 read-write - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 + AAL + Address-Aligned Beats +When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. + 25 1 read-write - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 + PBLX8 + PBLx8 Mode +When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. + 24 + 1 read-write - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 + USP + Use Separate PBL +When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. + 23 + 1 read-write - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 + RPBL + Rx DMA PBL +This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. + 17 + 6 read-write - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 + FB + Fixed Burst + This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. + 16 1 read-write - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 + PR + Priority Ratio + These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. +- 00: The Priority Ratio is 1:1. +- 01: The Priority Ratio is 2:1. +- 10: The Priority Ratio is 3:1. +- 11: The Priority Ratio is 4:1. + 14 + 2 read-write - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 + PBL + Programmable Burst Length +These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. + 8 + 6 read-write - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 + ATDS + Alternate Descriptor Size +When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). + 7 1 read-write - - - - L3_L4_CFG_3_L4_ADDR - Layer 4 Address Register - 0x494 - 32 - 0x00000000 - 0xFFFFFFFF - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 + DSL + Descriptor Skip Length +This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. + 2 + 5 read-write - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 + DA + DMA Arbitration Scheme +This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. +- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). +- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. + 1 + 1 read-write - - - - L3_L4_CFG_3_L3_ADDR_0 - Layer 3 Address 0 Register - 0x4a0 - 32 - 0x00000000 - 0xFFFFFFFF - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. + SWR + Software Reset + When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. Note: - The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. 0 - 32 + 1 read-write - L3_L4_CFG_3_L3_ADDR_1 - Layer 3 Address 1 Register - 0x4a4 + DMA_TX_POLL_DEMAND + Transmit Poll Demand Register + 0x1004 32 0x00000000 0xFFFFFFFF - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. + TPD + Transmit Poll Demand +When these bits are written with any value, the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes. 0 32 read-write @@ -44694,17 +42806,17 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - L3_L4_CFG_3_L3_ADDR_2 - Layer 3 Address 2 Register - 0x4a8 + DMA_RX_POLL_DEMAND + Receive Poll Demand Register + 0x1008 32 0x00000000 0xFFFFFFFF - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + RPD + Receive Poll Demand +When these bits are written with any value, the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. If the descriptor is available, the Rx DMA returns to the active state. 0 32 read-write @@ -44712,16 +42824,17 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - L3_L4_CFG_3_L3_ADDR_3 - Layer 3 Address 3 Register - 0x4ac + DMA_RX_DESC_LIST_ADDR + Receive Descriptor List Address Register + 0x100c 32 0x00000000 0xFFFFFFFF - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. + RDESLA + Start of Receive List +This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). 0 32 read-write @@ -44729,17 +42842,17 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - HASH_TABLE_REGISTER0 - Hash Table Register 0 - 0x500 + DMA_TX_DESC_LIST_ADDR + Transmit Descriptor List Address Register + 0x1010 32 0x00000000 0xFFFFFFFF - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. + TDESLA + Start of Transmit List +This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). 0 32 read-write @@ -44747,823 +42860,769 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - HASH_TABLE_REGISTER1 - Hash Table Register 1 - 0x504 + DMA_STATUS + Status Register + 0x1014 32 0x00000000 - 0xFFFFFFFF + 0x7FFFE7FF - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 + GLPII + GLPII: GMAC LPI Interrupt (for Channel 0) +This bit indicates an interrupt event in the LPI logic of the MAC. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. + 30 + 1 read-write - - - - HASH_TABLE_REGISTER2 - Hash Table Register 2 - 0x508 - 32 - 0x00000000 - 0xFFFFFFFF - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 + TTI + Timestamp Trigger Interrupt +This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. + 29 + 1 read-write - - - - HASH_TABLE_REGISTER3 - Hash Table Register 3 - 0x50c - 32 - 0x00000000 - 0xFFFFFFFF - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 + GPI + GMAC PMT Interrupt +This bit indicates an interrupt event in the PMT module of the DWC_gmac. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. + 28 + 1 read-write - - - - HASH_TABLE_REGISTER4 - Hash Table Register 4 - 0x510 - 32 - 0x00000000 - 0xFFFFFFFF - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 + GMI + GMAC MMC Interrupt + This bit reflects an interrupt event in the MMC module of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. + 27 + 1 read-write - - - - HASH_TABLE_REGISTER5 - Hash Table Register 5 - 0x514 - 32 - 0x00000000 - 0xFFFFFFFF - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 + GLI + GMAC Line Interface Interrupt +When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers: - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. + 26 + 1 read-write - - - - HASH_TABLE_REGISTER6 - Hash Table Register 6 - 0x518 - 32 - 0x00000000 - 0xFFFFFFFF - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 + EB + Error Bits +This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. +- 0 0 0: Error during Rx DMA Write Data Transfer +- 0 1 1: Error during Tx DMA Read Data Transfer +- 1 0 0: Error during Rx DMA Descriptor Write Access +- 1 0 1: Error during Tx DMA Descriptor Write Access +- 1 1 0: Error during Rx DMA Descriptor Read Access +- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. + 23 + 3 read-write - - - - HASH_TABLE_REGISTER7 - Hash Table Register 7 - 0x51c - 32 - 0x00000000 - 0xFFFFFFFF - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 + TS + Transmit Process State +This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. +- 3’b000: Stopped; Reset or Stop Transmit Command issued +- 3’b001: Running; Fetching Transmit Transfer Descriptor +- 3’b010: Running; Waiting for status +- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) +- 3’b100: TIME_STAMP write state +- 3’b101: Reserved for future use +- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow +- 3’b111: Running; Closing Transmit Descriptor + 20 + 3 read-write - - - - VLAN_TAG_INC_RPL - VLAN Tag Inclusion or Replacement Register - 0x584 - 32 - 0x00000000 - 0x000FFFFF - - CSVL - C-VLAN or S-VLAN - When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - 19 - 1 + RS + Receive Process State +This field indicates the Receive DMA FSM state. This field does not generate an interrupt. +- 3’b000: Stopped: Reset or Stop Receive Command issued +- 3’b001: Running: Fetching Receive Transfer Descriptor +- 3’b010: Reserved for future use +- 3’b011: Running: Waiting for receive packet +- 3’b100: Suspended: Receive Descriptor Unavailable +- 3’b101: Running: Closing Receive Descriptor +- 3’b110: TIME_STAMP write state +- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory + 17 + 3 read-write - VLP - VLAN Priority Control -When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - 18 + NIS + Normal Interrupt Summary +Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. + 16 1 read-write - VLC - VLAN Tag Control in Transmit Frames -- 2’b00: No VLAN tag deletion, insertion, or replacement -- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. -- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. -- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). Note: Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - 16 - 2 + AIS + Abnormal Interrupt Summary +Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive FIFO Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. + 15 + 1 read-write - VLT - VLAN Tag for Transmit Frames - This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - 0 - 16 + ERI + Early Receive Interrupt +This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). + 14 + 1 read-write - - - - VLAN_HASH - VLAN Hash Table Register - 0x588 - 32 - 0x00000000 - 0x0000FFFF - - VLHT - VLAN Hash Table - This field contains the 16-bit VLAN Hash Table. - 0 - 16 + FBI + Fatal Bus Error Interrupt +This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. + 13 + 1 read-write - - - - TS_CTRL - Timestamp Control Register - 0x700 - 32 - 0x00000000 - 0x1F07FF3F - - ATSEN3 - Auxiliary Snapshot 3 Enable -This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - 28 + ETI + Early Transmit Interrupt +This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. + 10 1 read-write - ATSEN2 - Auxiliary Snapshot 2 Enable -This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - 27 + RWT + Receive Watchdog Timeout +When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. + 9 1 read-write - ATSEN1 - Auxiliary Snapshot 1 Enable -This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - 26 + RPS + Receive Process Stopped +This bit is asserted when the Receive Process enters the Stopped state. + 8 1 read-write - ATSEN0 - Auxiliary Snapshot 0 Enable -This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - 25 + RU + Receive Buffer Unavailable +This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. + 7 1 read-write - ATSFC - Auxiliary Snapshot FIFO Clear -When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - 24 + RI + Receive Interrupt +This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state. + 6 1 read-write - TSENMACADDR - Enable MAC address for PTP Frame Filtering -When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - 18 + UNF + Transmit Underflow +This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. + 5 1 read-write - SNAPTYPSEL - Select PTP packets for Taking Snapshots - These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - 16 - 2 + OVF + Receive Overflow +This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. + 4 + 1 read-write - TSMSTRENA - Enable Snapshot for Messages Relevant to Master -When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - 15 + TJT + Transmit Jabber Timeout +This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. + 3 1 read-write - TSEVNTENA - Enable Timestamp Snapshot for Event Messages -When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - 14 + TU + Transmit Buffer Unavailable +This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. + 2 1 read-write - TSIPV4ENA - Enable Processing of PTP Frames Sent over IPv4-UDP - When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - 13 + TPS + Transmit Process Stopped +This bit is set when the transmission is stopped. + 1 1 read-write - TSIPV6ENA - Enable Processing of PTP Frames Sent over IPv6-UDP -When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - 12 + TI + Transmit Interrupt +This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. + 0 1 read-write + + + + DMA_OP_MODE + Operation Mode Register + 0x1018 + 32 + 0x00000000 + 0x13F1FFFE + - TSIPENA - Enable Processing of PTP over Ethernet Frames -When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - 11 + DT + Disable Dropping of TCP/IP Checksum Error Frames +When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). + 28 1 read-write - TSVER2ENA - Enable PTP packet Processing for Version 2 Format -When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - 10 + RSF + Receive Store and Forward +When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. + 25 1 read-write - TSCTRLSSR - Timestamp Digital or Binary Rollover Control -When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - 9 + DFF + Disable Flushing of Received Frames +When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) + 24 1 read-write - TSENALL - Enable Timestamp for All Frames -When set, the timestamp snapshot is enabled for all frames received by the MAC. - 8 + RFA_2 + MSB of Threshold for Activating Flow Control +If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: +- 100: Full minus 5 KB, that is, FULL — 5 KB +- 101: Full minus 6 KB, that is, FULL — 6 KB +- 110: Full minus 7 KB, that is, FULL — 7 KB +- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + 23 1 read-write - TSADDREG - Addend Reg Update -When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. - 5 + RFD_2 + MSB of Threshold for Deactivating Flow Control +If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: +- 100: Full minus 5 KB, that is, FULL — 5 KB +- 101: Full minus 6 KB, that is, FULL — 6 KB +- 110: Full minus 7 KB, that is, FULL — 7 KB +- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. + 22 1 read-write - TSTRIG - Timestamp Interrupt Trigger Enable -When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt. - 4 + TSF + Transmit Store and Forward +When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the transmission is stopped. + 21 1 read-write - TSUPDT - Timestamp Update -When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - 3 + FTF + Flush Transmit FIFO +When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. + 20 1 read-write - TSINIT - Timestamp Initialize -When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - 2 - 1 + TTC + Transmit Threshold Control +These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. +- 000: 64 +- 001: 128 +- 010: 192 +- 011: 256 +- 100: 40 +- 101: 32 +- 110: 24 +- 111: 16 + 14 + 3 read-write - TSCFUPDT - Timestamp Fine or Coarse Update -When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - 1 + ST + Start or Stop Transmission Command +When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. + 13 1 read-write - TSENA - Timestamp Enable -When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - 0 - 1 + RFD + Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. +- 00: Full minus 1 KB, that is, FULL — 1 KB +- 01: Full minus 2 KB, that is, FULL — 2 KB +- 10: Full minus 3 KB, that is, FULL — 3 KB +- 11: Full minus 4 KB, that is, FULL — 4 KB The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. + 11 + 2 read-write - - - - SUB_SEC_INCR - Sub-Second Increment Register - 0x704 - 32 - 0x00000000 - 0x000000FF - - SSINC - Sub-second Increment Value -The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - 0 - 8 + RFA + Threshold for Activating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. +- 00: Full minus 1 KB, that is, FULL—1KB. +- 01: Full minus 2 KB, that is, FULL—2KB. +- 10: Full minus 3 KB, that is, FULL—3KB. +- 11: Full minus 4 KB, that is, FULL—4KB. These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition + 9 + 2 read-write - - - - SYST_SEC - System Time - Seconds Register - 0x708 - 32 - 0x00000000 - 0xFFFFFFFF - - TSS - Timestamp Second - The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - 0 - 32 - read-only + EFC + Enable HW Flow Control +When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. + 8 + 1 + read-write - - - - SYST_NSEC - System Time - Nanoseconds Register - 0x70c - 32 - 0x00000000 - 0x7FFFFFFF - - TSSS - Timestamp Sub Seconds - The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - 0 - 31 - read-only + FEF + Forward Error Frames +When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features: - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. + 7 + 1 + read-write - - - - SYST_SEC_UPD - System Time - Seconds Update Register - 0x710 - 32 - 0x00000000 - 0xFFFFFFFF - - TSS - Timestamp Second - The value in this field indicates the time in seconds to be initialized or added to the system time. - 0 - 32 + FUF + Forward Undersized Good Frames +When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. + 6 + 1 read-write - - - - SYST_NSEC_UPD - System Time - Nanoseconds Update Register - 0x714 - 32 - 0x00000000 - 0xFFFFFFFF - - ADDSUB - Add or Subtract Time - When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - 31 + DGF + Drop Giant Frames +When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO. Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). + 5 1 read-write - TSSS - Timestamp Sub Seconds -The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - 0 - 31 + RTC + Receive Threshold Control +These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are automatically transferred. The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. +- 00: 64 +- 01: 32 +- 10: 96 +- 11: 128 + 3 + 2 read-write - - - - TS_ADDEND - Timestamp Addend Register - 0x718 - 32 - 0x00000000 - 0xFFFFFFFF - - TSAR - Timestamp Addend Register -This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - 0 - 32 + OSF + Operate on Second Frame +When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. + 2 + 1 read-write - - - - TGTTM_SEC - Target Time Seconds Register - 0x71c - 32 - 0x00000000 - 0xFFFFFFFF - - TSTR - Target Time Seconds Register - This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 + SR + Start or Stop Receive +When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. + 1 + 1 read-write - TGTTM_NSEC - Target Time Nanoseconds Register - 0x720 + DMA_INTR_EN + Interrupt Enable Register + 0x101c 32 0x00000000 - 0xFFFFFFFF + 0x0001E7FF - TRGTBUSY - Target Time Register Busy - The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - 31 + NIE + Normal Interrupt Summary Enable +When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt + 16 1 read-write - TTSLO - Target Timestamp Low Register -This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 + AIE + Abnormal Interrupt Summary Enable +When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error + 15 + 1 read-write - - - - SYSTM_H_SEC - System Time - Higher Word Seconds Register - 0x724 - 32 - 0x00000000 - 0x0000FFFF - - TSHWR - Timestamp Higher Word Register -This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - 0 - 16 + ERE + Early Receive Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. + 14 + 1 read-write - - - - TS_STATUS - Timestamp Status Register - 0x728 - 32 - 0x00000000 - 0x3F0F03FF - - - ATSNS - Number of Auxiliary Timestamp Snapshots -This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 25 - 5 - read-only - - ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed - This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 24 + FBE + Fatal Bus Error Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. + 13 1 - read-only + read-write - ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier -These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. These bits are applicable only if the number of Auxiliary snapshots is more than one. One bit is assigned for each trigger as shown in the following list: - Bit 16: Auxiliary trigger 0 - Bit 17: Auxiliary trigger 1 - Bit 18: Auxiliary trigger 2 - Bit 19: Auxiliary trigger 3 The software can read this register to find the triggers that are set when the timestamp is taken. - 16 - 4 - read-only + ETE + Early Transmit Interrupt Enable +When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. + 10 + 1 + read-write - TSTRGTERR3 - Timestamp Target Time Error -This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. + RWE + Receive Watchdog Timeout Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. 9 1 - read-only + read-write - TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 -When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). + RSE + Receive Stopped Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. 8 1 - read-only + read-write - TSTRGTERR2 - No description avaiable + RUE + Receive Buffer Unavailable Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. 7 1 - read-only + read-write - TSTARGT2 - No description avaiable + RIE + Receive Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. 6 1 - read-only + read-write - TSTRGTERR1 - No description avaiable + UNE + Underflow Interrupt Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. 5 1 - read-only + read-write - TSTARGT1 - No description avaiable + OVE + Overflow Interrupt Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. 4 1 - read-only + read-write - TSTRGTERR - No description avaiable + TJE + Transmit Jabber Timeout Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. 3 1 - read-only + read-write - AUXTSTRIG - No description avaiable + TUE + Transmit Buffer Unavailable Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. 2 1 - read-only + read-write - TSTARGT - No description avaiable + TSE + Transmit Stopped Enable +When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. 1 1 - read-only + read-write - TSSOVF - No description avaiable + TIE + Transmit Interrupt Enable +When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. 0 1 - read-only + read-write - PPS_CTRL - PPS Control Register - 0x72c + DMA_MISS_OVF_CNT + Missed Frame And Buffer Overflow Counter Register + 0x1020 32 0x00000000 - 0x6767677F + 0x1FFFFFFF - TRGTMODSEL3 - Target Time Register Mode for PPS3 Output -This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - 29 - 2 + ONFCNTOVF + Overflow Bit for FIFO Overflow Counter +This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 28 + 1 read-write - PPSCMD3 - Flexible PPS3 Output Control -This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 24 - 3 + OVFFRMCNT + Overflow Frame Counter +This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. + 17 + 11 read-write - TRGTMODSEL2 - Target Time Register Mode for PPS2 Output -This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - 21 - 2 + MISCNTOVF + Overflow Bit for Missed Frame Counter +This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. + 16 + 1 read-write - PPSCMD2 - Flexible PPS2 Output Control -This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. + MISFRMCNT + Missed Frame Counter +This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. + 0 + 16 + read-write + + + + + DMA_RX_INTR_WDOG + Receive Interrupt Watchdog Timer Register + 0x1024 + 32 + 0x00000000 + 0x000000FF + + + RIWT + RI Watchdog Timer Count +This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. + 0 + 8 + read-write + + + + + DMA_AXI_MODE + AXI Bus Mode Register + 0x1028 + 32 + 0x00000000 + 0xC0FF30FF + + + EN_LPI + Enable Low Power Interface (LPI) +When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. + 31 + 1 + read-write + + + LPI_XIT_FRM + Unlock on Magic Packet or Remote Wake-Up Frame +When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. + 30 + 1 + read-write + + + WR_OSR_LMT + AXI Maximum Write Outstanding Request Limit +This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. + 20 + 4 + read-write + + + RD_OSR_LMT + AXI Maximum Read Outstanding Request Limit +This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. 16 - 3 + 4 read-write - TRGTMODSEL1 - Target Time Register Mode for PPS1 Output -This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. + ONEKBBE + 1 KB Boundary Crossing Enable for the GMAC-AXI Master +When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. 13 - 2 + 1 read-write - PPSCMD1 - Flexible PPS1 Output Control -This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 8 - 3 + AXI_AAL + Address-Aligned Beats +This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. + 12 + 1 read-write - TRGTMODSEL0 - Target Time Register Mode for PPS0 Output - This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: -- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. -- 01: Reserved -- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. -- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. + BLEN256 + AXI Burst Length 256 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). + 7 + 1 + read-write + + + BLEN128 + AXI Burst Length 128 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). + 6 + 1 + read-write + + + BLEN64 + AXI Burst Length 64 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). 5 - 2 + 1 read-write - PPSEN0 - Flexible PPS Output Mode Enable -When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. + BLEN32 + AXI Burst Length 32 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). 4 1 read-write - PPSCTRLCMD0 - PPSCTRL0: PPS0 Output Frequency Control -This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: -- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. -- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. -- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. -- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... -- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) -PPSCMD0: Flexible PPS0 Output Control -0000: No Command -0001: START Single Pulse -This command generates single pulse rising at the start point defined in -Target Time Registers and of a duration defined -in the PPS0 Width Register. -0010: START Pulse Train -This command generates the train of pulses rising at the start point -defined in the Target Time Registers and of a duration defined in the -PPS0 Width Register and repeated at interval defined in the PPS -Interval Register. By default, the PPS pulse train is free-running unless -stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train -immediately’ commands. -0011: Cancel START -This command cancels the START Single Pulse and START Pulse Train -commands if the system time has not crossed the programmed start -time. -0100: STOP Pulse train at time -This command stops the train of pulses initiated by the START Pulse -Train command (PPSCMD = 0010) after the time programmed in the -Target Time registers elapses. -0101: STOP Pulse Train immediately -This command immediately stops the train of pulses initiated by the -START Pulse Train command (PPSCMD = 0010). -0110: Cancel STOP Pulse train -This command cancels the STOP pulse train at time command if the -programmed stop time has not elapsed. The PPS pulse train becomes -free-running on the successful execution of this command. -0111-1111: Reserved -Note: These bits get cleared automatically + BLEN16 + AXI Burst Length 16 +When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. + 3 + 1 + read-write + + + BLEN8 + AXI Burst Length 8 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + 2 + 1 + read-write + + + BLEN4 + AXI Burst Length 4 +When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. + 1 + 1 + read-write + + + UNDEF + AXI Undefined Burst Length +This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. 0 - 4 + 1 read-write - AUX_TS_NSEC - Auxiliary Timestamp - Nanoseconds Register - 0x730 + DMA_BUS_STATUS + AHB or AXI Status Register + 0x102c 32 0x00000000 - 0x7FFFFFFF + 0x00000003 - AUXTSLO - Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. + AXIRDSTS + AXI Master Read Channel Status +When high, it indicates that AXI master's read channel is active and transferring data. + 1 + 1 + read-write + + + AXWHSTS + AXI Master Write Channel or AHB Master Status +When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, it indicates that the AHB master interface FSMs are in the non-idle state. 0 - 31 - read-only + 1 + read-write - AUX_TS_SEC - Auxiliary Timestamp - Seconds Register - 0x734 + DMA_CURR_HOST_TX_DESC + Current Host Transmit Descriptor Register + 0x1048 32 0x00000000 0xFFFFFFFF - AUXTSHI - Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. + CURTDESAPTR + Host Transmit Descriptor Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. 0 32 - read-only + read-write - PPS0_INTERVAL - PPS0 Interval Register - 0x760 + DMA_CURR_HOST_RX_DESC + Current Host Receive Descriptor Register + 0x104c 32 0x00000000 0xFFFFFFFF - PPSINT - PPS0 Output Signal Interval -These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + CURRDESAPTR + Host Receive Descriptor Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. 0 32 read-write @@ -45571,17 +43630,17 @@ These bits store the interval between the rising edges of PPS0 signal output in - PPS0_WIDTH - PPS0 Width Register - 0x764 + DMA_CURR_HOST_TX_BUF + Current Host Transmit Buffer Address Register + 0x1050 32 0x00000000 0xFFFFFFFF - PPSWIDTH - PPS0 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + CURTBUFAPTR + Host Transmit Buffer Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. 0 32 read-write @@ -45589,97 +43648,169 @@ These bits store the width between the rising edge and corresponding falling edg - PPS_1_TGTTM_SEC - PPS Target Time Seconds Register - 0x780 + DMA_CURR_HOST_RX_BUF + Current Host Receive Buffer Address Register + 0x1054 32 0x00000000 0xFFFFFFFF - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + CURRBUFAPTR + Host Receive Buffer Address Pointer +Cleared on Reset. Pointer updated by the DMA during operation. 0 32 read-write + + + + NTMR0 + NTMR0 + TMR + 0xf2010000 + + 0x0 + 0x20c + registers + + - PPS_1_TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x784 + CHANNEL_CH0_CR + Control Register + 0x0 32 0x00000000 - 0xFFFFFFFF + 0xFFFC7FFF - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle 31 1 + write-only + + + RESERVED + not exist + 18 + 13 read-write - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 + CNTRST + 1- reset counter + 14 + 1 read-write - - - - PPS_1_INTERVAL - PPS Interval Register - 0x788 - 32 - 0x00000000 - 0xFFFFFFFF - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 read-write - - - - PPS_1_WIDTH - PPS Width Register - 0x78c - 32 - 0x00000000 - 0xFFFFFFFF - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 read-write - + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + - PPS_2_TGTTM_SEC - PPS2 Target Time Seconds Register - 0x7a0 + CHANNEL_CH0_CMP_CMP0 + Comparator register 0 + 0x4 32 - 0x00000000 + 0xFFFFFFFF 0xFFFFFFFF - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + CMP + compare value 0 0 32 read-write @@ -45687,43 +43818,50 @@ This register stores the time in seconds. When the timestamp value matches or ex - PPS_2_TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x7a4 + CHANNEL_CH0_CMP_CMP1 + Comparator register 1 + 0x8 32 - 0x00000000 + 0xFFFFFFFF 0xFFFFFFFF - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 + CMP + compare value 0 + 0 + 32 read-write + + + + CHANNEL_CH0_RLD + Reload register + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + RLD + reload value 0 - 31 + 32 read-write - PPS_2_INTERVAL - PPS Interval Register - 0x7a8 + CHANNEL_CH0_CNTUPTVAL + Counter update value register + 0x10 32 0x00000000 0xFFFFFFFF - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR 0 32 read-write @@ -45731,255 +43869,240 @@ These bits store the interval between the rising edges of PPS1 signal output in - PPS_2_WIDTH - PPS Width Register - 0x7ac + CHANNEL_CH0_CAPPOS + Capture rising edge register + 0x20 32 0x00000000 0xFFFFFFFF - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + CAPPOS + This register contains the counter value captured at input signal rising edge 0 32 - read-write + read-only - PPS_3_TGTTM_SEC - PPS3 Target Time Seconds Register - 0x7c0 + CHANNEL_CH0_CAPNEG + Capture falling edge register + 0x24 32 0x00000000 0xFFFFFFFF - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + CAPNEG + This register contains the counter value captured at input signal falling edge 0 32 - read-write + read-only - PPS_3_TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x7c4 + CHANNEL_CH0_CAPPRD + PWM period measure register + 0x28 32 0x00000000 0xFFFFFFFF - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. 0 - 31 - read-write + 32 + read-only - PPS_3_INTERVAL - PPS Interval Register - 0x7c8 + CHANNEL_CH0_CAPDTY + PWM duty cycle measure register + 0x2c 32 0x00000000 0xFFFFFFFF - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. 0 32 - read-write + read-only - PPS_3_WIDTH - PPS Width Register - 0x7cc + CHANNEL_CH0_CNT + Counter + 0x30 32 0x00000000 0xFFFFFFFF - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. + COUNTER + 32 bit counter value 0 32 - read-write + read-only - DMA_BUS_MODE - Bus Mode Register - 0x1000 + CHANNEL_CH1_CR + Control Register + 0x40 32 0x00000000 - 0xBFFFFFFF + 0xFFFC7FFF - RIB - Rebuild INCRx Burst -When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle 31 1 - read-write + write-only - PRWG - Channel Priority -Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. -- 00: The priority weight is 1. -- 01: The priority weight is 2. -- 10: The priority weight is 3. -- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - 28 - 2 + RESERVED + not exist + 18 + 13 read-write - TXPR - Transmit Priority -When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - 27 + CNTRST + 1- reset counter + 14 1 read-write - MB - Mixed Burst -When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - 26 + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 1 read-write - AAL - Address-Aligned Beats -When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - 25 + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 1 read-write - PBLX8 - PBLx8 Mode -When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - 24 + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 1 read-write - USP - Use Separate PBL -When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - 23 + CEN + 1- counter enable + 10 1 read-write - RPBL - Rx DMA PBL -This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. - 17 - 6 + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 read-write - FB - Fixed Burst - This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - 16 + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 1 read-write - PR - Priority Ratio - These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. -- 00: The Priority Ratio is 1:1. -- 01: The Priority Ratio is 2:1. -- 10: The Priority Ratio is 3:1. -- 11: The Priority Ratio is 4:1. - 14 + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 2 read-write - PBL - Programmable Burst Length -These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - 8 - 6 + DMAEN + 1- enable dma + 5 + 1 read-write - ATDS - Alternate Descriptor Size -When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - 7 + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 1 read-write - DSL - Descriptor Skip Length -This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - 2 - 5 + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 read-write - DA - DMA Arbitration Scheme -This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. -- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). -- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - 1 - 1 + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 read-write + + + + CHANNEL_CH1_CMP_CMP0 + Comparator register 0 + 0x44 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + - SWR - Software Reset - When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. Note: - The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. + CMP + compare value 0 0 - 1 + 32 read-write - DMA_TX_POLL_DEMAND - Transmit Poll Demand Register - 0x1004 + CHANNEL_CH1_CMP_CMP1 + Comparator register 1 + 0x48 32 - 0x00000000 + 0xFFFFFFFF 0xFFFFFFFF - TPD - Transmit Poll Demand -When these bits are written with any value, the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes. + CMP + compare value 0 0 32 read-write @@ -45987,17 +44110,16 @@ When these bits are written with any value, the DMA reads the current descriptor - DMA_RX_POLL_DEMAND - Receive Poll Demand Register - 0x1008 + CHANNEL_CH1_RLD + Reload register + 0x4c 32 - 0x00000000 + 0xFFFFFFFF 0xFFFFFFFF - RPD - Receive Poll Demand -When these bits are written with any value, the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. If the descriptor is available, the Rx DMA returns to the active state. + RLD + reload value 0 32 read-write @@ -46005,17 +44127,16 @@ When these bits are written with any value, the DMA reads the current descriptor - DMA_RX_DESC_LIST_ADDR - Receive Descriptor List Address Register - 0x100c + CHANNEL_CH1_CNTUPTVAL + Counter update value register + 0x50 32 0x00000000 0xFFFFFFFF - RDESLA - Start of Receive List -This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR 0 32 read-write @@ -46023,1031 +44144,892 @@ This field contains the base address of the first descriptor in the Receive Desc - DMA_TX_DESC_LIST_ADDR - Transmit Descriptor List Address Register - 0x1010 + CHANNEL_CH1_CAPPOS + Capture rising edge register + 0x60 32 0x00000000 0xFFFFFFFF - TDESLA - Start of Transmit List -This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). + CAPPOS + This register contains the counter value captured at input signal rising edge 0 32 - read-write + read-only - DMA_STATUS - Status Register - 0x1014 + CHANNEL_CH1_CAPNEG + Capture falling edge register + 0x64 32 0x00000000 - 0x7FFFE7FF + 0xFFFFFFFF - GLPII - GLPII: GMAC LPI Interrupt (for Channel 0) -This bit indicates an interrupt event in the LPI logic of the MAC. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - 30 - 1 - read-write + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + CHANNEL_CH1_CAPPRD + PWM period measure register + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + - TTI - Timestamp Trigger Interrupt -This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - 29 - 1 - read-write + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + CHANNEL_CH1_CAPDTY + PWM duty cycle measure register + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + - GPI - GMAC PMT Interrupt -This bit indicates an interrupt event in the PMT module of the DWC_gmac. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - 28 - 1 - read-write + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH1_CNT + Counter + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + CHANNEL_CH2_CR + Control Register + 0x80 + 32 + 0x00000000 + 0xFFFC7FFF + - GMI - GMAC MMC Interrupt - This bit reflects an interrupt event in the MMC module of the DWC_gmac. The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - 27 + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 1 - read-write + write-only - GLI - GMAC Line Interface Interrupt -When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers: - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - 26 - 1 - read-write - - - EB - Error Bits -This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. -- 0 0 0: Error during Rx DMA Write Data Transfer -- 0 1 1: Error during Tx DMA Read Data Transfer -- 1 0 0: Error during Rx DMA Descriptor Write Access -- 1 0 1: Error during Tx DMA Descriptor Write Access -- 1 1 0: Error during Rx DMA Descriptor Read Access -- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - 23 - 3 - read-write - - - TS - Transmit Process State -This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped; Reset or Stop Transmit Command issued -- 3’b001: Running; Fetching Transmit Transfer Descriptor -- 3’b010: Running; Waiting for status -- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) -- 3’b100: TIME_STAMP write state -- 3’b101: Reserved for future use -- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow -- 3’b111: Running; Closing Transmit Descriptor - 20 - 3 - read-write - - - RS - Receive Process State -This field indicates the Receive DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped: Reset or Stop Receive Command issued -- 3’b001: Running: Fetching Receive Transfer Descriptor -- 3’b010: Reserved for future use -- 3’b011: Running: Waiting for receive packet -- 3’b100: Suspended: Receive Descriptor Unavailable -- 3’b101: Running: Closing Receive Descriptor -- 3’b110: TIME_STAMP write state -- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - 17 - 3 + RESERVED + not exist + 18 + 13 read-write - NIS - Normal Interrupt Summary -Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - 16 + CNTRST + 1- reset counter + 14 1 read-write - AIS - Abnormal Interrupt Summary -Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive FIFO Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - 15 + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 1 read-write - ERI - Early Receive Interrupt -This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - 14 + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 1 read-write - FBI - Fatal Bus Error Interrupt -This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - 13 + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 1 read-write - ETI - Early Transmit Interrupt -This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. + CEN + 1- counter enable 10 1 read-write - RWT - Receive Watchdog Timeout -When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. 9 1 read-write - RPS - Receive Process Stopped -This bit is asserted when the Receive Process enters the Stopped state. + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. 8 1 read-write - RU - Receive Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. - 7 - 1 - read-write - - - RI - Receive Interrupt -This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state. + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; 6 - 1 + 2 read-write - UNF - Transmit Underflow -This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. + DMAEN + 1- enable dma 5 1 read-write - OVF - Receive Overflow -This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set 4 1 read-write - TJT - Transmit Jabber Timeout -This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. + DBGPAUSE + 1- counter will pause if chip is in debug mode 3 1 read-write - TU - Transmit Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - 2 - 1 + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 read-write + + + + CHANNEL_CH2_CMP_CMP0 + Comparator register 0 + 0x84 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + - TPS - Transmit Process Stopped -This bit is set when the transmission is stopped. - 1 - 1 + CMP + compare value 0 + 0 + 32 read-write + + + + CHANNEL_CH2_CMP_CMP1 + Comparator register 1 + 0x88 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + - TI - Transmit Interrupt -This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. + CMP + compare value 0 0 - 1 + 32 read-write - DMA_OP_MODE - Operation Mode Register - 0x1018 + CHANNEL_CH2_RLD + Reload register + 0x8c 32 - 0x00000000 - 0x13F1FFFE + 0xFFFFFFFF + 0xFFFFFFFF - DT - Disable Dropping of TCP/IP Checksum Error Frames -When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - 28 - 1 + RLD + reload value + 0 + 32 read-write + + + + CHANNEL_CH2_CNTUPTVAL + Counter update value register + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + - RSF - Receive Store and Forward -When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - 25 - 1 + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 read-write + + + + CHANNEL_CH2_CAPPOS + Capture rising edge register + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + - DFF - Disable Flushing of Received Frames -When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - 24 - 1 - read-write + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + CHANNEL_CH2_CAPNEG + Capture falling edge register + 0xa4 + 32 + 0x00000000 + 0xFFFFFFFF + - RFA_2 - MSB of Threshold for Activating Flow Control -If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 23 - 1 - read-write + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + CHANNEL_CH2_CAPPRD + PWM period measure register + 0xa8 + 32 + 0x00000000 + 0xFFFFFFFF + - RFD_2 - MSB of Threshold for Deactivating Flow Control -If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 22 - 1 - read-write + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + CHANNEL_CH2_CAPDTY + PWM duty cycle measure register + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + - TSF - Transmit Store and Forward -When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the transmission is stopped. - 21 - 1 - read-write + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CHANNEL_CH2_CNT + Counter + 0xb0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + CHANNEL_CH3_CR + Control Register + 0xc0 + 32 + 0x00000000 + 0xFFFC7FFF + - FTF - Flush Transmit FIFO -When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. - 20 + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 1 + write-only + + + RESERVED + not exist + 18 + 13 read-write - TTC - Transmit Threshold Control -These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. -- 000: 64 -- 001: 128 -- 010: 192 -- 011: 256 -- 100: 40 -- 101: 32 -- 110: 24 -- 111: 16 + CNTRST + 1- reset counter 14 - 3 + 1 read-write - ST - Start or Stop Transmission Command -When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. 13 1 read-write - RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. -- 00: Full minus 1 KB, that is, FULL — 1 KB -- 01: Full minus 2 KB, that is, FULL — 2 KB -- 10: Full minus 3 KB, that is, FULL — 3 KB -- 11: Full minus 4 KB, that is, FULL — 4 KB The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge 11 - 2 + 1 read-write - RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. -- 00: Full minus 1 KB, that is, FULL—1KB. -- 01: Full minus 2 KB, that is, FULL—2KB. -- 10: Full minus 3 KB, that is, FULL—3KB. -- 11: Full minus 4 KB, that is, FULL—4KB. These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - 9 - 2 + CEN + 1- counter enable + 10 + 1 read-write - EFC - Enable HW Flow Control -When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - 8 + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 1 read-write - FEF - Forward Error Frames -When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features: - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - 7 + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 1 read-write - FUF - Forward Undersized Good Frames -When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; 6 - 1 + 2 read-write - DGF - Drop Giant Frames -When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO. Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). + DMAEN + 1- enable dma 5 1 read-write - RTC - Receive Threshold Control -These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are automatically transferred. The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. -- 00: 64 -- 01: 32 -- 10: 96 -- 11: 128 - 3 - 2 + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 read-write - OSF - Operate on Second Frame -When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - 2 + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 1 read-write - SR - Start or Stop Receive -When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - 1 - 1 + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 read-write - DMA_INTR_EN - Interrupt Enable Register - 0x101c + CHANNEL_CH3_CMP_CMP0 + Comparator register 0 + 0xc4 32 - 0x00000000 - 0x0001E7FF + 0xFFFFFFFF + 0xFFFFFFFF - NIE - Normal Interrupt Summary Enable -When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[0]: Transmit Interrupt - Register 5[2]: Transmit Buffer Unavailable - Register 5[6]: Receive Interrupt - Register 5[14]: Early Receive Interrupt - 16 - 1 + CMP + compare value 0 + 0 + 32 read-write + + + + CHANNEL_CH3_CMP_CMP1 + Comparator register 1 + 0xc8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + - AIE - Abnormal Interrupt Summary Enable -When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): - Register 5[1]: Transmit Process Stopped - Register 5[3]: Transmit Jabber Timeout - Register 5[4]: Receive Overflow - Register 5[5]: Transmit Underflow - Register 5[7]: Receive Buffer Unavailable - Register 5[8]: Receive Process Stopped - Register 5[9]: Receive Watchdog Timeout - Register 5[10]: Early Transmit Interrupt - Register 5[13]: Fatal Bus Error - 15 - 1 - read-write - - - ERE - Early Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - 14 - 1 - read-write - - - FBE - Fatal Bus Error Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - 13 - 1 - read-write - - - ETE - Early Transmit Interrupt Enable -When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - 10 - 1 - read-write - - - RWE - Receive Watchdog Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - 9 - 1 - read-write - - - RSE - Receive Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - 8 - 1 - read-write - - - RUE - Receive Buffer Unavailable Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - 7 - 1 - read-write - - - RIE - Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - 6 - 1 - read-write - - - UNE - Underflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - 5 - 1 - read-write - - - OVE - Overflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - 4 - 1 - read-write - - - TJE - Transmit Jabber Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - 3 - 1 - read-write - - - TUE - Transmit Buffer Unavailable Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - 2 - 1 - read-write - - - TSE - Transmit Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - 1 - 1 - read-write - - - TIE - Transmit Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - 0 - 1 + CMP + compare value 0 + 0 + 32 read-write - DMA_MISS_OVF_CNT - Missed Frame And Buffer Overflow Counter Register - 0x1020 + CHANNEL_CH3_RLD + Reload register + 0xcc 32 - 0x00000000 - 0x1FFFFFFF + 0xFFFFFFFF + 0xFFFFFFFF - ONFCNTOVF - Overflow Bit for FIFO Overflow Counter -This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 28 - 1 - read-write - - - OVFFRMCNT - Overflow Frame Counter -This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - 17 - 11 - read-write - - - MISCNTOVF - Overflow Bit for Missed Frame Counter -This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 16 - 1 - read-write - - - MISFRMCNT - Missed Frame Counter -This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. + RLD + reload value 0 - 16 + 32 read-write - DMA_RX_INTR_WDOG - Receive Interrupt Watchdog Timer Register - 0x1024 + CHANNEL_CH3_CNTUPTVAL + Counter update value register + 0xd0 32 0x00000000 - 0x000000FF + 0xFFFFFFFF - RIWT - RI Watchdog Timer Count -This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR 0 - 8 + 32 read-write - DMA_AXI_MODE - AXI Bus Mode Register - 0x1028 + CHANNEL_CH3_CAPPOS + Capture rising edge register + 0xe0 32 0x00000000 - 0xC0FF30FF + 0xFFFFFFFF - EN_LPI - Enable Low Power Interface (LPI) -When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - 31 - 1 - read-write - - - LPI_XIT_FRM - Unlock on Magic Packet or Remote Wake-Up Frame -When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - 30 - 1 - read-write - - - WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit -This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - 20 - 4 - read-write - - - RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit -This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - 16 - 4 - read-write - - - ONEKBBE - 1 KB Boundary Crossing Enable for the GMAC-AXI Master -When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - 13 - 1 - read-write - - - AXI_AAL - Address-Aligned Beats -This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - 12 - 1 - read-write - - - BLEN256 - AXI Burst Length 256 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - 7 - 1 - read-write - - - BLEN128 - AXI Burst Length 128 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - 6 - 1 - read-write - - - BLEN64 - AXI Burst Length 64 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - 5 - 1 - read-write - - - BLEN32 - AXI Burst Length 32 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - 4 - 1 - read-write - - - BLEN16 - AXI Burst Length 16 -When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - 3 - 1 - read-write - - - BLEN8 - AXI Burst Length 8 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. - 2 - 1 - read-write - - - BLEN4 - AXI Burst Length 4 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. Setting this bit has no effect when UNDEF is set to 1. - 1 - 1 - read-write - - - UNDEF - AXI Undefined Burst Length -This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. + CAPPOS + This register contains the counter value captured at input signal rising edge 0 - 1 - read-write + 32 + read-only - DMA_BUS_STATUS - AHB or AXI Status Register - 0x102c + CHANNEL_CH3_CAPNEG + Capture falling edge register + 0xe4 32 0x00000000 - 0x00000003 + 0xFFFFFFFF - AXIRDSTS - AXI Master Read Channel Status -When high, it indicates that AXI master's read channel is active and transferring data. - 1 - 1 - read-write - - - AXWHSTS - AXI Master Write Channel or AHB Master Status -When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, it indicates that the AHB master interface FSMs are in the non-idle state. + CAPNEG + This register contains the counter value captured at input signal falling edge 0 - 1 - read-write + 32 + read-only - DMA_CURR_HOST_TX_DESC - Current Host Transmit Descriptor Register - 0x1048 + CHANNEL_CH3_CAPPRD + PWM period measure register + 0xe8 32 0x00000000 0xFFFFFFFF - CURTDESAPTR - Host Transmit Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. 0 32 - read-write + read-only - DMA_CURR_HOST_RX_DESC - Current Host Receive Descriptor Register - 0x104c + CHANNEL_CH3_CAPDTY + PWM duty cycle measure register + 0xec 32 0x00000000 0xFFFFFFFF - CURRDESAPTR - Host Receive Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. 0 32 - read-write + read-only - DMA_CURR_HOST_TX_BUF - Current Host Transmit Buffer Address Register - 0x1050 + CHANNEL_CH3_CNT + Counter + 0xf0 32 0x00000000 0xFFFFFFFF - CURTBUFAPTR - Host Transmit Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. + COUNTER + 32 bit counter value 0 32 - read-write + read-only - DMA_CURR_HOST_RX_BUF - Current Host Receive Buffer Address Register - 0x1054 + SR + Status register + 0x200 32 0x00000000 0xFFFFFFFF - CURRBUFAPTR - Host Receive Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 + RESERVED + No description avaiable + 16 + 16 read-write - - - - DMA_HW_FEATURE - HW Feature Register - 0x1058 - 32 - 0x00000000 - 0x7FFFFFFF - - ACTPHYIF - Active or selected PHY interface -When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. -- 000: GMII or MII -- 001: RGMII -- 010: SGMII -- 011: TBI -- 100: RMII -- 101: RTBI -- 110: SMII -- 111: RevMII - All Others: Reserved - 28 - 3 - read-write + CH3CMP1F + channel 3 compare value 1 match flag + 15 + 1 + write-only - SAVLANINS - Source Address or VLAN Insertion - 27 + CH3CMP0F + channel 3 compare value 1 match flag + 14 1 - read-write + write-only - FLEXIPPSEN - Flexible Pulse-Per-Second Output - 26 + CH3CAPF + channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 13 1 - read-write + write-only - INTTSEN - Timestamping with Internal System Time - 25 + CH3RLDF + channel 3 counter reload flag + 12 1 - read-write + write-only - ENHDESSEL - Alternate (Enhanced Descriptor) - 24 + CH2CMP1F + channel 2 compare value 1 match flag + 11 1 - read-write + write-only - TXCHCNT - Number of additional Tx Channels - 22 - 2 - read-write + CH2CMP0F + channel 2 compare value 1 match flag + 10 + 1 + write-only - RXCHCNT - Number of additional Rx Channels - 20 - 2 - read-write + CH2CAPF + channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 9 + 1 + write-only - RXFIFOSIZE - Rx FIFO > 2,048 Bytes - 19 + CH2RLDF + channel 2 counter reload flag + 8 1 - read-write + write-only - RXTYP2COE - IP Checksum Offload (Type 2) in Rx - 18 + CH1CMP1F + channel 1 compare value 1 match flag + 7 1 - read-write + write-only - RXTYP1COE - IP Checksum Offload (Type 1) in Rx Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE = 1. - 17 + CH1CMP0F + channel 1 compare value 1 match flag + 6 1 - read-write + write-only - TXCOESEL - Checksum Offload in Tx - 16 + CH1CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 5 + 1 + write-only + + + CH1RLDF + channel 1 counter reload flag + 4 + 1 + write-only + + + CH0CMP1F + channel 1 compare value 1 match flag + 3 + 1 + write-only + + + CH0CMP0F + channel 1 compare value 1 match flag + 2 + 1 + write-only + + + CH0CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 1 + 1 + write-only + + + CH0RLDF + channel 1 counter reload flag + 0 1 + write-only + + + + + IRQEN + Interrupt request enable register + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + RESERVED + No description avaiable + 16 + 16 read-write - AVSEL - AV feature + CH3CMP1EN + 1- generate interrupt request when ch3cmp1f flag is set 15 1 read-write - EEESEL - Energy Efficient Ethernet + CH3CMP0EN + 1- generate interrupt request when ch3cmp0f flag is set 14 1 read-write - TSVER2SEL - IEEE 1588-2008 Advanced timestamp + CH3CAPEN + 1- generate interrupt request when ch3capf flag is set 13 1 read-write - TSVER1SEL - Only IEEE 1588-2002 timestamp + CH3RLDEN + 1- generate interrupt request when ch3rldf flag is set 12 1 read-write - MMCSEL - RMON module + CH2CMP1EN + 1- generate interrupt request when ch2cmp1f flag is set 11 1 read-write - MGKSEL - PMT magic packet + CH2CMP0EN + 1- generate interrupt request when ch2cmp0f flag is set 10 1 read-write - RWKSEL - PMT remote wake-up frame + CH2CAPEN + 1- generate interrupt request when ch2capf flag is set 9 1 read-write - SMASEL - SMA (MDIO) Interface + CH2RLDEN + 1- generate interrupt request when ch2rldf flag is set 8 1 read-write - L3L4FLTREN - Layer 3 and Layer 4 feature + CH1CMP1EN + 1- generate interrupt request when ch1cmp1f flag is set 7 1 read-write - PCSSEL - PCS registers (TBI, SGMII, or RTBI PHY interface) + CH1CMP0EN + 1- generate interrupt request when ch1cmp0f flag is set 6 1 read-write - ADDMACADRSEL - Multiple MAC Address registers + CH1CAPEN + 1- generate interrupt request when ch1capf flag is set 5 1 read-write - HASHSEL - HASH filter + CH1RLDEN + 1- generate interrupt request when ch1rldf flag is set 4 1 read-write - EXTHASHEN - Expanded DA Hash filter + CH0CMP1EN + 1- generate interrupt request when ch0cmp1f flag is set 3 1 read-write - HDSEL - Half-duplex support + CH0CMP0EN + 1- generate interrupt request when ch0cmp0f flag is set 2 1 read-write - GMIISEL - 1000 Mbps support + CH0CAPEN + 1- generate interrupt request when ch0capf flag is set 1 1 read-write - MIISEL - 10 or 100 Mbps support + CH0RLDEN + 1- generate interrupt request when ch0rldf flag is set 0 1 read-write @@ -47055,1439 +45037,2264 @@ When you have multiple PHY interfaces in your configuration, this field indicate - CTRL0 - Control Register 0 - 0x3000 + GCR + Global control register + 0x208 32 0x00000000 - 0x000003FF + 0x0000000F - ENET0_RXCLK_DLY_SEL - No description avaiable - 5 - 5 + SWSYNCT + set this bitfield to trigger software coutner sync event + 0 + 4 read-write + + + + + + GPTMR0 + GPTMR0 + TMR + 0xf3000000 + + + GPTMR1 + GPTMR1 + TMR + 0xf3004000 + + + GPTMR2 + GPTMR2 + TMR + 0xf3008000 + + + GPTMR3 + GPTMR3 + TMR + 0xf300c000 + + + PTMR + PTMR + TMR + 0xf40e0000 + + + USB0 + USB0 + USB + 0xf2020000 + + 0x0 + 0x228 + registers + + + + GPTIMER0LD + General Purpose Timer #0 Load Register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + - ENET0_TXCLK_DLY_SEL - No description avaiable + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. 0 - 5 + 24 read-write - CTRL2 - Control Register 1 - 0x3008 + GPTIMER0CTRL + General Purpose Timer #0 Controller Register + 0x84 32 0x00000000 - 0x2008F400 + 0xC1FFFFFF - ENET0_LPI_IRQ_EN - No description avaiable - 29 + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 1 read-write - ENET0_REFCLK_OE - No description avaiable - 19 + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in n_GPTIMER0LD + 30 1 - read-write + write-only - ENET0_PHY_INF_SEL - No description avaiable - 13 - 3 + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software; +In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the +counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 read-write - ENET0_FLOWCTRL - No description avaiable - 12 - 1 - read-write + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + GPTIMER1LD + General Purpose Timer #1 Load Register + 0x88 + 32 + 0x00000000 + 0x00FFFFFF + - ENET0_RMII_TXCLK_SEL - No description avaiable - 10 - 1 + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 read-write - - - - NTMR0 - NTMR0 - TMR - 0xf2010000 - - 0x0 - 0x20c - registers - - - CHANNEL_CH0_CR - Control Register - 0x0 + GPTIMER1CTRL + General Purpose Timer #1 Controller Register + 0x8c 32 0x00000000 - 0xFFFFFFFF + 0xC1FFFFFF - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run 31 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + 30 + 1 write-only - RESERVED - not exist - 15 - 16 + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and +automatically reload the counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 read-write - CNTRST - 1- reset counter - 14 - 1 + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + SBUSCFG + System Bus Config Register + 0x90 + 32 + 0x00000000 + 0x00000007 + + + AHBBRST + AHBBRST +AHB master interface Burst configuration +These bits control AHB master transfer type sequence (or priority). +NOTE: This register overrides n_BURSTSIZE register when its value is not zero. +000 - Incremental burst of unspecified length only +001 - INCR4 burst, then single transfer +010 - INCR8 burst, INCR4 burst, then single transfer +011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer +100 - Reserved, don't use +101 - INCR4 burst, then incremental burst of unspecified length +110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length +111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0 + 3 read-write + + + + USBCMD + USB Command Register + 0x140 + 32 + 0x00080000 + 0x00FFEB7F + - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 + ITC + ITC +Interrupt Threshold Control -Read/Write. +The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are +shown below. +Value Maximum Interrupt Interval +00000000 - Immediate (no threshold) +00000001 - 1 micro-frame +00000010 - 2 micro-frames +00000100 - 4 micro-frames +00001000 - 8 micro-frames +00010000 - 16 micro-frames +00100000 - 32 micro-frames +01000000 - 64 micro-frames + 16 + 8 read-write - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 + FS_2 + FS_2 +Frame List Size - (Read/Write or Read Only). [host mode only] +This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. +This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. +NOTE: This field is made up from USBCMD bits 15, 3 and 2. +Value Meaning +0b000 - 1024 elements (4096 bytes) Default value +0b001 - 512 elements (2048 bytes) +0b010 - 256 elements (1024 bytes) +0b011 - 128 elements (512 bytes) +0b100 - 64 elements (256 bytes) +0b101 - 32 elements (128 bytes) +0b110 - 16 elements (64 bytes) +0b111 - 8 elements (32 bytes) + 15 1 read-write - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 + ATDTW + ATDTW +Add dTD TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's +linked list. This bit is set and cleared by software. +This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD +to a primed endpoint may go unrecognized. + 14 1 read-write - CEN - 1- counter enable - 10 + SUTW + SUTW +Setup TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. +If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. +This bit would also be cleared by hardware when a hazard detected. + 13 1 read-write - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 + ASPE + ASPE +Asynchronous Schedule Park Mode Enable - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. +NOTE: ASPE bit reset value: '0b' for OTG controller . + 11 1 read-write - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + ASP + ASP +Asynchronous Schedule Park Mode Count - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. +It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. +Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. +This field is set to 3h in all controller core. 8 - 1 + 2 read-write - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; + IAA + IAA +Interrupt on Async Advance Doorbell - Read/Write. +This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. +When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. +The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. +This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. 6 - 2 + 1 read-write - DMAEN - 1- enable dma + ASE + ASE +Asynchronous Schedule Enable - Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Asynchronous Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Asynchronous Schedule. +1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. 5 1 read-write - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + PSE + PSE +Periodic Schedule Enable- Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Periodic Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Periodic Schedule +1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. 4 1 read-write - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 + FS_1 + FS_1 +See description at bit 15 + 2 + 2 + read-write + + + RST + RST +Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. +Host operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. +Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. +Attempting to reset an actively running host controller will result in undefined behavior. +Device operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + 1 1 read-write - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture + RS + RS +Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. +Host operation mode: +When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. +Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). +Device operation mode: +Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. +This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. 0 - 3 + 1 read-write - CHANNEL_CH0_CMP_CMP0 - Comparator register 0 - 0x4 + USBSTS + USB Status Register + 0x144 32 - 0xFFFFFFFF - 0xFFFFFFFF + 0x00000000 + 0x030DF1FF - CMP - compare value 0 - 0 - 32 + TI1 + TI1 +General Purpose Timer Interrupt 1(GPTINT1)--R/WC. +This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this +bit will clear it. + 25 + 1 read-write - - - - CHANNEL_CH0_CMP_CMP1 - Comparator register 1 - 0x8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - CMP - compare value 0 - 0 - 32 + TI0 + TI0 +General Purpose Timer Interrupt 0(GPTINT0)--R/WC. +This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this +bit clears it. + 24 + 1 read-write - - - - CHANNEL_CH0_RLD - Reload register - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - RLD - reload value - 0 - 32 + UPI + USB Host Periodic Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. +This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero. + 19 + 1 read-write - - - - CHANNEL_CH0_CNTUPTVAL - Counter update value register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 + UAI + USB Host Asynchronous Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. +This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero + 18 + 1 read-write - - - - CHANNEL_CH0_CAPPOS - Capture rising edge register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 + NAKI + NAKI +NAK Interrupt Bit--RO. +This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and +corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware +when all Enabled TX/RX Endpoint NAK bits are cleared. + 16 + 1 read-only - - - - CHANNEL_CH0_CAPNEG - Capture falling edge register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 + AS + AS +Asynchronous Schedule Status - Read Only. +This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. +When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 15 + 1 read-only - - - - CHANNEL_CH0_CAPPRD - PWM period measure register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 + PS + PS +Periodic Schedule Status - Read Only. +This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 14 + 1 read-only - - - - CHANNEL_CH0_CAPDTY - PWM duty cycle measure register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 + RCL + RCL +Reclamation - Read Only. +This is a read-only status bit used to detect an empty asynchronous schedule. +Only used in the host operation mode. + 13 + 1 read-only - - - - CHANNEL_CH0_CNT - Counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - COUNTER - 32 bit counter value - 0 - 32 + HCH + HCH +HCHaIted - Read Only. +This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). +Only used in the host operation mode. +Default value is '0b' for OTG core . +This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE +register. +NOTE: HCH bit reset value: '0b' for OTG controller core . + 12 + 1 read-only - - - - CHANNEL_CH1_CR - Control Register - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 + SLI + SLI +DCSuspend - R/WC. +When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. +Only used in device operation mode. + 8 1 - write-only + read-write - RESERVED - not exist - 15 - 16 + SRI + SRI +SOF Received - R/WC. +When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. +Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. +Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. +In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. +Software writes a 1 to this bit to clear it. + 7 + 1 read-write - CNTRST - 1- reset counter - 14 + URI + URI +USB Reset Received - R/WC. +When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. +Software can write a 1 to this bit to clear the USB Reset Received status bit. +Only used in device operation mode. + 6 1 read-write - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 + AAI + AAI +Interrupt on Async Advance - R/WC. +System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. +Only used in host operation mode. + 5 1 read-write - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 + SEI + System Error – RWC. Default = 0b. +In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + 4 1 read-write - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 + FRI + FRI +Frame List Rollover - R/WC. +The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to +zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the +frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the +Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host +Controller sets this bit to a one every time FHINDEX [12] toggles. +Only used in host operation mode. + 3 1 read-write - CEN - 1- counter enable - 10 + PCI + PCI +Port Change Detect - R/WC. +The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. +The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + 2 1 read-write - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 + UEI + UEI +USB Error Interrupt (USBERRINT) - R/WC. +When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + 1 1 read-write - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + UI + UI +USB Interrupt (USBINT) - R/WC. +This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB +transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. +This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when +the actual number of bytes received was less than the expected number of bytes. + 0 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + 0x00000000 + 0x030D01FF + + + TIE1 + TIE1 +General Purpose Timer #1 Interrupt Enable +When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + 25 + 1 + read-write + + + TIE0 + TIE0 +General Purpose Timer #0 Interrupt Enable +When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + 24 + 1 + read-write + + + UPIE + UPIE +USB Host Periodic Interrupt Enable +When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 19 + 1 + read-write + + + UAIE + UAIE +USB Host Asynchronous Interrupt Enable +When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 18 + 1 + read-write + + + NAKE + NAKE +NAK Interrupt Enable +When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + 16 + 1 + read-only + + + SLE + SLE +Sleep Interrupt Enable +When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. 8 1 read-write - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; + SRE + SRE +SOF Received Interrupt Enable +When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + 7 + 1 + read-write + + + URE + URE +USB Reset Interrupt Enable +When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. 6 - 2 + 1 read-write - DMAEN - 1- enable dma + AAE + AAE +Async Advance Interrupt Enable +When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. 5 1 read-write - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + SEE + SEE +System Error Interrupt Enable +When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. 4 1 read-write - DBGPAUSE - 1- counter will pause if chip is in debug mode + FRE + FRE +Frame List Rollover Interrupt Enable +When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. 3 1 read-write - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture + PCE + PCE +Port Change Detect Interrupt Enable +When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + 2 + 1 + read-write + + + UEE + UEE +USB Error Interrupt Enable +When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + 1 + 1 + read-write + + + UE + UE +USB Interrupt Enable +When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. 0 - 3 + 1 read-write - CHANNEL_CH1_CMP_CMP0 - Comparator register 0 - 0x44 + FRINDEX + USB Frame Index Register + 0x14c 32 - 0xFFFFFFFF - 0xFFFFFFFF + 0x00000000 + 0x00003FFF - CMP - compare value 0 + FRINDEX + FRINDEX +Frame Index. +The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. +The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. +USBCMD [Frame List Size] Number Elements N +In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. +In either mode bits 2:0 indicate the current microframe. +The bit field values description below is represented as (Frame List Size) Number Elements N. +00000000000000 - (1024) 12 +00000000000001 - (512) 11 +00000000000010 - (256) 10 +00000000000011 - (128) 9 +00000000000100 - (64) 8 +00000000000101 - (32) 7 +00000000000110 - (16) 6 +00000000000111 - (8) 5 0 - 32 + 14 read-write - CHANNEL_CH1_CMP_CMP1 - Comparator register 1 - 0x48 + DEVICEADDR + Device Address Register + 0x154 32 - 0xFFFFFFFF - 0xFFFFFFFF + 0x00000000 + 0xFF000000 - CMP - compare value 0 - 0 - 32 + USBADR + USBADR +Device Address. +These bits correspond to the USB device address + 25 + 7 + read-write + + + USBADRA + USBADRA +Device Address Advance. Default=0. +When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. +After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. +Hardware will automatically clear this bit on the following conditions: +1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). +2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). +3) Device Reset occurs (USBADR is reset to 0). +NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. +If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + 24 + 1 read-write - CHANNEL_CH1_RLD - Reload register - 0x4c + PERIODICLISTBASE + Frame List Base Address Register + 0x154 32 - 0xFFFFFFFF - 0xFFFFFFFF + 0x00000000 + 0xFFFFF000 - RLD - reload value - 0 - 32 + BASEADR + BASEADR +Base Address (Low). +These bits correspond to memory address signals [31:12], respectively. +Only used by the host controller. + 12 + 20 read-write - CHANNEL_CH1_CNTUPTVAL - Counter update value register - 0x50 + ASYNCLISTADDR + Next Asynch. Address Register + 0x158 32 0x00000000 - 0xFFFFFFFF + 0xFFFFFFE0 - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 + ASYBASE + ASYBASE +Link Pointer Low (LPL). +These bits correspond to memory address signals [31:5], respectively. This field may only reference a +Queue Head (QH). +Only used by the host controller. + 5 + 27 read-write - CHANNEL_CH1_CAPPOS - Capture rising edge register - 0x60 + ENDPTLISTADDR + Endpoint List Address Register + 0x158 32 0x00000000 - 0xFFFFFFFF + 0xFFFFF800 - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only + EPBASE + EPBASE +Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + 11 + 21 + read-write - CHANNEL_CH1_CAPNEG - Capture falling edge register - 0x64 + BURSTSIZE + Programmable Burst Size Register + 0x160 32 0x00000000 - 0xFFFFFFFF + 0x0000FFFF - CAPNEG - This register contains the counter value captured at input signal falling edge + TXPBURST + TXPBURST +Programmable TX Burst Size. +Default value is determined by TXBURST bits in n_HWTXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from system +memory to the USB bus. + 8 + 8 + read-write + + + RXPBURST + RXPBURST +Programmable RX Burst Size. +Default value is determined by TXBURST bits in n_HWRXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from the +USB bus to system memory. 0 - 32 - read-only + 8 + read-write - CHANNEL_CH1_CAPPRD - PWM period measure register - 0x68 + TXFILLTUNING + TX FIFO Fill Tuning Register + 0x164 32 0x00000000 - 0xFFFFFFFF + 0x003F1F7F - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. + TXFIFOTHRES + TXFIFOTHRES +FIFO Burst Threshold. (Read/Write) +This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. +The minimum value is 2 and this value should be a low as possible to maximize USB performance. +A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. +This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + 16 + 6 + read-write + + + TXSCHHEALTH + TXSCHHEALTH +Scheduler Health Counter. (Read/Write To Clear) +Table continues on the next page +This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. + 8 + 5 + read-write + + + TXSCHOH + TXSCHOH +Scheduler Overhead. (Read/Write) [Default = 0] +This register adds an additional fixed offset to the schedule time estimator described above as Tff. +As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. +Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. +The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. +The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. +Default value is '08h' for OTG controller core . 0 - 32 - read-only + 7 + read-write - CHANNEL_CH1_CAPDTY - PWM duty cycle measure register - 0x6c + ENDPTNAK + Endpoint NAK Register + 0x178 32 0x00000000 - 0xFFFFFFFF + 0x00FF00FF - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. + EPTN + EPTN +TX Endpoint NAK - R/WC. +Each TX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received IN token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 8 + read-write + + + EPRN + EPRN +RX Endpoint NAK - R/WC. +Each RX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 0 - 32 - read-only + 8 + read-write - CHANNEL_CH1_CNT - Counter - 0x70 + ENDPTNAKEN + Endpoint NAK Enable Register + 0x17c 32 0x00000000 - 0xFFFFFFFF + 0x00FF00FF - COUNTER - 32 bit counter value + EPTNE + EPTNE +TX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the +corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 8 + read-write + + + EPRNE + EPRNE +RX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the +corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 0 - 32 - read-only + 8 + read-write - CHANNEL_CH2_CR - Control Register - 0x80 + PORTSC1 + Port Status & Control + 0x184 32 0x00000000 - 0xFFFFFFFF + 0x3DFF1FFF - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 + STS + STS +Serial Transceiver Select +1 Serial Interface Engine is selected +0 Parallel Interface signals is selected +Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. +When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + 29 1 - write-only + read-write - RESERVED - not exist - 15 - 16 + PTW + PTW +Parallel Transceiver Width +This bit has no effect if serial interface engine is used. +0 - Select the 8-bit UTMI interface [60MHz] +1 - Select the 16-bit UTMI interface [30MHz] + 28 + 1 read-write - CNTRST - 1- reset counter - 14 + PSPD + PSPD +Port Speed - Read Only. +This register field indicates the speed at which the port is operating. +00 - Full Speed +01 - Low Speed +10 - High Speed +11 - Undefined + 26 + 2 + read-only + + + PFSC + PFSC +Port Force Full Speed Connect - Read/Write. Default = 0b. +When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp +sequence that allows the port to identify itself as High Speed. +0 - Normal operation +1 - Forced to full speed + 24 1 read-write - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 + PHCD + PHCD +PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. +When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY +clock. +NOTE: The PHY clock cannot be disabled if it is being used as the system clock. +In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD +Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend +will be cleared automatically when the host initials resume. Before forcing a resume from the device, the +device controller driver must clear this bit. +In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put +into suspend mode or when no downstream device is connected. Low power suspend is completely +under the control of software. +0 - Enable PHY clock +1 - Disable PHY clock + 23 1 read-write - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 + WKOC + WKOC +Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. +Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. +This field is zero if Port Power(PORTSC1) is zero. + 22 1 read-write - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 + WKDC + WKDC +Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables +the port to be sensitive to device disconnects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 21 1 read-write - CEN - 1- counter enable - 10 + WKCN + WKCN +Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. +Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 20 1 read-write - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 + PTC + PTC +Port Test Control - Read/Write. Default = 0000b. +Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. +The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. +NOTE: Low speed operations are not supported as a peripheral device. +Any other value than zero indicates that the port is operating in test mode. +Value Specific Test +0000 - TEST_MODE_DISABLE +0001 - J_STATE +0010 - K_STATE +0011 - SE0 (host) / NAK (device) +0100 - Packet +0101 - FORCE_ENABLE_HS +0110 - FORCE_ENABLE_FS +0111 - FORCE_ENABLE_LS +1000-1111 - Reserved + 16 + 4 + read-write + + + PP + PP +Port Power (PP)-Read/Write or Read Only. +The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: +PPC +PP Operation +0 +1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. +1 +1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. +When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). +This feature is implemented in all controller cores (PPC = 1). + 12 1 read-write - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + LS + LS +Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal +lines. +In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because +the port controller state machine and the port routing manage the connection of LS and FS. +In device mode, the use of linestate by the device controller driver is not necessary. +The encoding of the bits are: +Bits [11:10] Meaning +00 - SE0 +01 - K-state +10 - J-state +11 - Undefined + 10 + 2 + read-only + + + HSP + HSP +High-Speed Port - Read Only. Default = 0b. +When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the +host/device connected to the port is not in a high-speed mode. +NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + 9 + 1 + read-only + + + PR + PR +Port Reset - Read/Write or Read Only. Default = 0b. +In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. +When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. +In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. 8 1 read-write - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; + SUSP + SUSP +Suspend - Read/Write or Read Only. Default = 0b. +1=Port in suspend state. 0=Port not in suspend state. +In Host Mode: Read/Write. +Port Enabled Bit and Suspend bit of this register define the port states as follows: +Bits [Port Enabled, Suspend] Port State +0x Disable +10 Enable +11 Suspend +When in suspend state, downstream propagation of data is blocked on this port, except for port reset. +The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. +The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. +If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: Read Only. +In device mode this bit is a read only status bit. + 7 + 1 + read-write + + + FPR + FPR +Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. +In Host Mode: +Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. +This bit will automatically change to zero after the resume sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. +Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. +The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. +Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. +This field is zero if Port Power(PORTSC1) is zero in host mode. +This bit is not-EHCI compatible. +In Device mode: +After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. +The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +The bit will be cleared when the device returns to normal operation. + Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. 6 - 2 + 1 read-write - DMAEN - 1- enable dma + OCC + OCC +Over-current Change-R/WC. Default=0. +This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. 5 1 read-write - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + OCA + OCA +Over-current Active-Read Only. Default 0. +This bit will automatically transition from one to zero when the over current condition is removed. +0 - This port does not have an over-current condition. +1 - This port currently has an over-current condition 4 1 - read-write + read-only - DBGPAUSE - 1- counter will pause if chip is in debug mode + PEC + PEC +Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. +In Host Mode: +For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). +Software clears this by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero. +In Device mode: +The device port is always enabled, so this bit is always '0b'. 3 1 read-write - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 + PE + PE +Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. +In Host Mode: +Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. +Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. +Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. +When the port is disabled, (0b) downstream propagation of data is blocked except for reset. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +The device port is always enabled, so this bit is always '1b'. + 2 + 1 read-write - - - - CHANNEL_CH2_CMP_CMP0 - Comparator register 0 - 0x84 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - CMP - compare value 0 - 0 - 32 + CSC + CSC +Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. +In Host Mode: +Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. +For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +This bit is undefined in device controller mode. + 1 + 1 read-write - - - - CHANNEL_CH2_CMP_CMP1 - Comparator register 1 - 0x88 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - CMP - compare value 0 + CCS + CCS +Current Connect Status-Read Only. +In Host Mode: +1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended. 0 - 32 + 1 read-write - CHANNEL_CH2_RLD - Reload register - 0x8c + OTGSC + On-The-Go Status & control Register + 0x1a4 32 - 0xFFFFFFFF - 0xFFFFFFFF + 0x00000000 + 0x07070723 - RLD - reload value - 0 - 32 + ASVIE + ASVIE +A Session Valid Interrupt Enable - Read/Write. + 26 + 1 read-write - - - - CHANNEL_CH2_CNTUPTVAL - Counter update value register - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 + AVVIE + AVVIE +A VBus Valid Interrupt Enable - Read/Write. +Setting this bit enables the A VBus valid interrupt. + 25 + 1 read-write - - - - CHANNEL_CH2_CAPPOS - Capture rising edge register - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only + IDIE + IDIE +USB ID Interrupt Enable - Read/Write. +Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write - - - - CHANNEL_CH2_CAPNEG - Capture falling edge register - 0xa4 - 32 - 0x00000000 - 0xFFFFFFFF - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CHANNEL_CH2_CAPPRD - PWM period measure register - 0xa8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH2_CAPDTY - PWM duty cycle measure register - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CHANNEL_CH2_CNT - Counter - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - CHANNEL_CH3_CR - Control Register - 0xc0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 + ASVIS + ASVIS +A Session Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the A session valid threshold. +Software must write a one to clear this bit. + 18 1 - write-only - - - RESERVED - not exist - 15 - 16 read-write - CNTRST - 1- reset counter - 14 + AVVIS + AVVIS +A VBus Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. +Software must write a one to clear this bit. + 17 1 read-write - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 + IDIS + IDIS +USB ID Interrupt Status - Read/Write. +This bit is set when a change on the ID input has been detected. +Software must write a one to clear this bit. + 16 1 read-write - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 + ASV + ASV +A Session Valid - Read Only. +Indicates VBus is above the A session valid threshold. + 10 1 - read-write + read-only - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 + AVV + AVV +A VBus Valid - Read Only. +Indicates VBus is above the A VBus valid threshold. + 9 1 - read-write + read-only - CEN - 1- counter enable - 10 + ID + ID +USB ID - Read Only. +0 = A device, 1 = B device + 8 1 - read-write + read-only - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 + IDPU + IDPU +ID Pullup - Read/Write +This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input +will not be sampled. + 5 1 read-write - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 + VC + VC +VBUS Charge - Read/Write. +Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + 1 1 read-write - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; - 6 - 2 + VD + VD +VBUS_Discharge - Read/Write. +Setting this bit causes VBus to discharge through a resistor. + 0 + 1 read-write + + + + USBMODE + USB Device Mode Register + 0x1a8 + 32 + 0x00000000 + 0x0000001F + - DMAEN - 1- enable dma - 5 + SDIS + SDIS +Stream Disable Mode. (0 - Inactive [default]; 1 - Active) +Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. +This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. +Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. +Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. +NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for +the scheduler when using this feature. +NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + 4 1 read-write - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 + SLOM + SLOM +Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . +0 - Setup Lockouts On (default); +1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + 3 1 read-write - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 + ES + ES +Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the +host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected +by the value of this bit because they are based upon the 32-bit word. +Bit Meaning +0 - Little Endian [Default] +1 - Big Endian + 2 1 read-write - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture + CM + CM +Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only +implementations. For those designs that contain both host & device capability, the controller defaults to +an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ +device controllers, this register can only be written once after reset. If it is necessary to switch modes, +software must reset the controller by writing to the RESET bit in the USBCMD register before +reprogramming this register. +For OTG controller core, reset value is '00b'. +00 - Idle [Default for combination host/device] +01 - Reserved +10 - Device Controller [Default for device only controller] +11 - Host Controller [Default for host only controller] 0 - 3 + 2 read-write - CHANNEL_CH3_CMP_CMP0 - Comparator register 0 - 0xc4 + ENDPTSETUPSTAT + Endpoint Setup Status Register + 0x1ac 32 - 0xFFFFFFFF - 0xFFFFFFFF + 0x00000000 + 0x000000FF - CMP - compare value 0 + ENDPTSETUPSTAT + ENDPTSETUPSTAT +Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. +Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. +The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. +This register is only used in device mode. 0 - 32 + 8 read-write - CHANNEL_CH3_CMP_CMP1 - Comparator register 1 - 0xc8 + ENDPTPRIME + Endpoint Prime Register + 0x1b0 32 - 0xFFFFFFFF - 0xFFFFFFFF + 0x00000000 + 0x00FF00FF - CMP - compare value 0 - 0 - 32 + PETB + PETB +Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a +buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. +Software should write a one to the corresponding bit when posting a new transfer descriptor to an +endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor +from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated +endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PETB[N] - Endpoint #N, N is in 0..7 + 16 + 8 read-write - - - - CHANNEL_CH3_RLD - Reload register - 0xcc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - RLD - reload value + PERB + PERB +Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. +Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. +Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. +Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PERB[N] - Endpoint #N, N is in 0..7 0 - 32 + 8 read-write - CHANNEL_CH3_CNTUPTVAL - Counter update value register - 0xd0 + ENDPTFLUSH + Endpoint Flush Register + 0x1b4 32 0x00000000 - 0xFFFFFFFF + 0x00FF00FF - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 + FETB + FETB +Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. +If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FETB[N] - Endpoint #N, N is in 0..7 + 16 + 8 read-write - - - - CHANNEL_CH3_CAPPOS - Capture rising edge register - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - CAPPOS - This register contains the counter value captured at input signal rising edge + FERB + FERB +Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FERB[N] - Endpoint #N, N is in 0..7 0 - 32 - read-only + 8 + read-write - CHANNEL_CH3_CAPNEG - Capture falling edge register - 0xe4 + ENDPTSTAT + Endpoint Status Register + 0x1b8 32 0x00000000 - 0xFFFFFFFF + 0x00FF00FF - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 + ETBR + ETBR +Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. +This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. +There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. +This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. +Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. +ETBR[N] - Endpoint #N, N is in 0..7 + 16 + 8 read-only - - - - CHANNEL_CH3_CAPPRD - PWM period measure register - 0xe8 - 32 - 0x00000000 - 0xFFFFFFFF - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. + ERBR + ERBR +Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective +endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a +corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the +ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB +traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the +USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations +when a dTD is retired, and the dQH is updated. +ERBR[N] - Endpoint #N, N is in 0..7 0 - 32 + 8 read-only - CHANNEL_CH3_CAPDTY - PWM duty cycle measure register - 0xec + ENDPTCOMPLETE + Endpoint Complete Register + 0x1bc 32 0x00000000 - 0xFFFFFFFF + 0x00FF00FF - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only + ETCE + ETCE +Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. +If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. +ETCE[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write - - - - CHANNEL_CH3_CNT - Counter - 0xf0 - 32 - 0x00000000 - 0xFFFFFFFF - - COUNTER - 32 bit counter value + ERCE + ERCE +Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred +and software should read the corresponding endpoint queue to determine the transfer status. If the +corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the +USBINT . Writing one clears the corresponding bit in this register. +ERCE[N] - Endpoint #N, N is in 0..7 0 - 32 - read-only + 8 + read-write - SR - Status register - 0x200 + ENDPTCTRL_ENDPTCTRL0 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1c0 32 0x00000000 - 0xFFFFFFFF + 0x00CD00CD - RESERVED - No description avaiable - 16 - 16 + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 read-write - CH3CMP1F - channel 3 compare value 1 match flag - 15 + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 1 write-only - CH3CMP0F - channel 3 compare value 1 match flag - 14 - 1 - write-only + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write - CH3CAPF - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 13 + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 1 - write-only + read-write - CH3RLDF - channel 3 counter reload flag - 12 + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 1 - write-only + read-write - CH2CMP1F - channel 2 compare value 1 match flag - 11 + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 1 write-only - CH2CMP0F - channel 2 compare value 1 match flag - 10 - 1 - write-only + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write - CH2CAPF - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 9 + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 1 - write-only + read-write + + + + ENDPTCTRL_ENDPTCTRL1 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1c4 + 32 + 0x00000000 + 0x00CD00CD + - CH2RLDF - channel 2 counter reload flag - 8 + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 1 - write-only + read-write - CH1CMP1F - channel 1 compare value 1 match flag - 7 + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 1 write-only - CH1CMP0F - channel 1 compare value 1 match flag - 6 - 1 - write-only + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write - CH1CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 5 + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 1 - write-only + read-write - CH1RLDF - channel 1 counter reload flag - 4 + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 1 - write-only + read-write - CH0CMP1F - channel 1 compare value 1 match flag - 3 + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 1 write-only - CH0CMP0F - channel 1 compare value 1 match flag + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt 2 - 1 - write-only - - - CH0CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 1 - 1 - write-only + 2 + read-write - CH0RLDF - channel 1 counter reload flag + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. 0 1 - write-only + read-write - IRQEN - Interrupt request enable register - 0x204 + ENDPTCTRL_ENDPTCTRL2 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1c8 32 0x00000000 - 0xFFFFFFFF + 0x00CD00CD - RESERVED - No description avaiable - 16 - 16 + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 read-write - CH3CMP1EN - 1- generate interrupt request when ch3cmp1f flag is set - 15 + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 read-write - CH3CMP0EN - 1- generate interrupt request when ch3cmp0f flag is set - 14 + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 1 read-write - CH3CAPEN - 1- generate interrupt request when ch3capf flag is set - 13 + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 1 read-write - CH3RLDEN - 1- generate interrupt request when ch3rldf flag is set - 12 + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 read-write - CH2CMP1EN - 1- generate interrupt request when ch2cmp1f flag is set - 11 + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 1 read-write + + + + ENDPTCTRL_ENDPTCTRL3 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1cc + 32 + 0x00000000 + 0x00CD00CD + - CH2CMP0EN - 1- generate interrupt request when ch2cmp0f flag is set - 10 + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 1 read-write - CH2CAPEN - 1- generate interrupt request when ch2capf flag is set - 9 + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 read-write - CH2RLDEN - 1- generate interrupt request when ch2rldf flag is set - 8 + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 1 read-write - CH1CMP1EN - 1- generate interrupt request when ch1cmp1f flag is set + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. 7 1 read-write - CH1CMP0EN - 1- generate interrupt request when ch1cmp0f flag is set + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. 6 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 read-write - CH1CAPEN - 1- generate interrupt request when ch1capf flag is set - 5 + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + ENDPTCTRL_ENDPTCTRL4 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1d0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 1 read-write - CH1RLDEN - 1- generate interrupt request when ch1rldf flag is set - 4 + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 read-write - CH0CMP1EN - 1- generate interrupt request when ch0cmp1f flag is set - 3 + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 1 read-write - CH0CMP0EN - 1- generate interrupt request when ch0cmp0f flag is set - 2 + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 1 read-write - CH0CAPEN - 1- generate interrupt request when ch0capf flag is set - 1 + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 read-write - CH0RLDEN - 1- generate interrupt request when ch0rldf flag is set + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. 0 1 read-write @@ -48495,407 +47302,347 @@ User should set this bit before set CMPEN to 1. - GCR - Global control register - 0x208 + ENDPTCTRL_ENDPTCTRL5 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1d4 32 0x00000000 - 0x0000000F + 0x00CD00CD - SWSYNCT - set this bitfield to trigger software coutner sync event - 0 - 4 + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 read-write - - - - - - GPTMR0 - GPTMR0 - TMR - 0xf3000000 - - - GPTMR1 - GPTMR1 - TMR - 0xf3004000 - - - GPTMR2 - GPTMR2 - TMR - 0xf3008000 - - - GPTMR3 - GPTMR3 - TMR - 0xf300c000 - - - PTMR - PTMR - TMR - 0xf40e0000 - - - USB0 - USB0 - USB - 0xf2020000 - - 0x0 - 0x228 - registers - - - - GPTIMER0LD - General Purpose Timer #0 Load Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 read-write - - - - GPTIMER0CTRL - General Purpose Timer #0 Controller Register - 0x84 - 32 - 0x00000000 - 0xC1FFFFFF - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 1 read-write - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in n_GPTIMER0LD - 30 + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 1 - write-only + read-write - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software; -In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the -counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 1 - read-write + write-only - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write - - - - GPTIMER1LD - General Purpose Timer #1 Load Register - 0x88 - 32 - 0x00000000 - 0x00FFFFFF - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. 0 - 24 + 1 read-write - GPTIMER1CTRL - General Purpose Timer #1 Controller Register - 0x8c + ENDPTCTRL_ENDPTCTRL6 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1d8 32 0x00000000 - 0xC1FFFFFF + 0x00CD00CD - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 1 read-write - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - 30 + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 1 write-only - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and -automatically reload the counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 read-write - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - SBUSCFG - System Bus Config Register - 0x90 - 32 - 0x00000000 - 0x00000007 - - - AHBBRST - AHBBRST -AHB master interface Burst configuration -These bits control AHB master transfer type sequence (or priority). -NOTE: This register overrides n_BURSTSIZE register when its value is not zero. -000 - Incremental burst of unspecified length only -001 - INCR4 burst, then single transfer -010 - INCR8 burst, INCR4 burst, then single transfer -011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer -100 - Reserved, don't use -101 - INCR4 burst, then incremental burst of unspecified length -110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length -111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - 0 - 3 + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 read-write - - - - USBCMD - USB Command Register - 0x140 - 32 - 0x00080000 - 0x00FFEB7F - - ITC - ITC -Interrupt Threshold Control -Read/Write. -The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are -shown below. -Value Maximum Interrupt Interval -00000000 - Immediate (no threshold) -00000001 - 1 micro-frame -00000010 - 2 micro-frames -00000100 - 4 micro-frames -00001000 - 8 micro-frames -00010000 - 16 micro-frames -00100000 - 32 micro-frames -01000000 - 64 micro-frames - 16 - 8 + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 read-write - FS_2 - FS_2 -Frame List Size - (Read/Write or Read Only). [host mode only] -This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. -This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. -NOTE: This field is made up from USBCMD bits 15, 3 and 2. -Value Meaning -0b000 - 1024 elements (4096 bytes) Default value -0b001 - 512 elements (2048 bytes) -0b010 - 256 elements (1024 bytes) -0b011 - 128 elements (512 bytes) -0b100 - 64 elements (256 bytes) -0b101 - 32 elements (128 bytes) -0b110 - 16 elements (64 bytes) -0b111 - 8 elements (32 bytes) - 15 + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 read-write - ATDTW - ATDTW -Add dTD TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's -linked list. This bit is set and cleared by software. -This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD -to a primed endpoint may go unrecognized. - 14 + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 1 read-write + + + + ENDPTCTRL_ENDPTCTRL7 + Endpoint Control0 Register... Endpoint Control7 Register + 0x1dc + 32 + 0x00000000 + 0x00CD00CD + - SUTW - SUTW -Setup TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. -This bit would also be cleared by hardware when a hazard detected. - 13 + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 1 read-write - ASPE - ASPE -Asynchronous Schedule Park Mode Enable - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. -NOTE: ASPE bit reset value: '0b' for OTG controller . - 11 + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 1 - read-write + write-only - ASP - ASP -Asynchronous Schedule Park Mode Count - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. -It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. -Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. -This field is set to 3h in all controller core. - 8 + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 2 read-write - IAA - IAA -Interrupt on Async Advance Doorbell - Read/Write. -This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. -When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. -The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. -This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - 6 + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 1 read-write - ASE - ASE -Asynchronous Schedule Enable - Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Asynchronous Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Asynchronous Schedule. -1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - 5 + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 1 read-write - PSE - PSE -Periodic Schedule Enable- Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Periodic Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Periodic Schedule -1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - 4 + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 1 - read-write + write-only - FS_1 - FS_1 -See description at bit 15 + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt 2 2 read-write - RST - RST -Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. -Host operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. -Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. -Attempting to reset an actively running host controller will result in undefined behavior. -Device operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - 1 - 1 - read-write - - - RS - RS -Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. -Host operation mode: -When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. -Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). -Device operation mode: -Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. -This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. 0 1 read-write @@ -48903,203 +47650,152 @@ This control bit is not directly connected to the pull-up enable, as the pull-up - USBSTS - USB Status Register - 0x144 + OTG_CTRL0 + No description avaiable + 0x200 32 0x00000000 - 0x030DF1FF + 0x020B3F90 - TI1 - TI1 -General Purpose Timer Interrupt 1(GPTINT1)--R/WC. -This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this -bit will clear it. + OTG_WKDPDMCHG_EN + No description avaiable 25 1 read-write - TI0 - TI0 -General Purpose Timer Interrupt 0(GPTINT0)--R/WC. -This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this -bit clears it. - 24 + AUTORESUME_EN + No description avaiable + 19 1 read-write - UPI - USB Host Periodic Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. -This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero. - 19 + OTG_VBUS_WAKEUP_EN + No description avaiable + 17 1 read-write - UAI - USB Host Asynchronous Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. -This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero - 18 + OTG_ID_WAKEUP_EN + No description avaiable + 16 1 read-write - NAKI - NAKI -NAK Interrupt Bit--RO. -This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and -corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware -when all Enabled TX/RX Endpoint NAK bits are cleared. - 16 + OTG_VBUS_SOURCE_SEL + No description avaiable + 13 1 - read-only + read-write - AS - AS -Asynchronous Schedule Status - Read Only. -This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. -When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 15 + OTG_UTMI_SUSPENDM_SW + default 0 for naneng usbphy + 12 1 - read-only + read-write - PS - PS -Periodic Schedule Status - Read Only. -This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 14 + OTG_UTMI_RESET_SW + default 1 for naneng usbphy + 11 1 - read-only + read-write - RCL - RCL -Reclamation - Read Only. -This is a read-only status bit used to detect an empty asynchronous schedule. -Only used in the host operation mode. - 13 + OTG_WAKEUP_INT_ENABLE + No description avaiable + 10 1 - read-only + read-write - HCH - HCH -HCHaIted - Read Only. -This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). -Only used in the host operation mode. -Default value is '0b' for OTG core . -This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE -register. -NOTE: HCH bit reset value: '0b' for OTG controller core . - 12 + OTG_POWER_MASK + No description avaiable + 9 1 - read-only + read-write - SLI - SLI -DCSuspend - R/WC. -When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. -Only used in device operation mode. + OTG_OVER_CUR_POL + No description avaiable 8 1 read-write - SRI - SRI -SOF Received - R/WC. -When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. -Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. -Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. -In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. -Software writes a 1 to this bit to clear it. + OTG_OVER_CUR_DIS + No description avaiable 7 1 read-write - URI - URI -USB Reset Received - R/WC. -When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. -Software can write a 1 to this bit to clear the USB Reset Received status bit. -Only used in device operation mode. - 6 + SER_MODE_SUSPEND_EN + for naneng usbphy, only switch to serial mode when suspend + 4 1 read-write + + + + PHY_CTRL0 + No description avaiable + 0x210 + 32 + 0x00000000 + 0x02007007 + - AAI - AAI -Interrupt on Async Advance - R/WC. -System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. -Only used in host operation mode. - 5 + GPIO_ID_SEL_N + No description avaiable + 25 1 read-write - SEI - System Error – RWC. Default = 0b. -In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - 4 + ID_DIG_OVERRIDE + No description avaiable + 14 1 read-write - FRI - FRI -Frame List Rollover - R/WC. -The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to -zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the -frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the -Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host -Controller sets this bit to a one every time FHINDEX [12] toggles. -Only used in host operation mode. - 3 + SESS_VALID_OVERRIDE + No description avaiable + 13 1 read-write - PCI - PCI -Port Change Detect - R/WC. -The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. -The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + VBUS_VALID_OVERRIDE + No description avaiable + 12 + 1 + read-write + + + ID_DIG_OVERRIDE_EN + No description avaiable 2 1 read-write - UEI - UEI -USB Error Interrupt (USBERRINT) - R/WC. -When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + SESS_VALID_OVERRIDE_EN + No description avaiable 1 1 read-write - UI - UI -USB Interrupt (USBINT) - R/WC. -This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB -transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. -This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when -the actual number of bytes received was less than the expected number of bytes. + VBUS_VALID_OVERRIDE_EN + No description avaiable 0 1 read-write @@ -49107,8041 +47803,1115 @@ the actual number of bytes received was less than the expected number of bytes.< - USBINTR - Interrupt Enable Register - 0x148 + PHY_CTRL1 + No description avaiable + 0x214 32 0x00000000 - 0x030D01FF + 0x00100002 - TIE1 - TIE1 -General Purpose Timer #1 Interrupt Enable -When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - 25 - 1 - read-write - - - TIE0 - TIE0 -General Purpose Timer #0 Interrupt Enable -When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - 24 - 1 - read-write - - - UPIE - UPIE -USB Host Periodic Interrupt Enable -When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 19 + UTMI_CFG_RST_N + No description avaiable + 20 1 read-write - UAIE - UAIE -USB Host Asynchronous Interrupt Enable -When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 18 + UTMI_OTG_SUSPENDM + OTG suspend, not utmi_suspendm + 1 1 read-write + + + + TOP_STATUS + No description avaiable + 0x220 + 32 + 0x00000000 + 0x80000000 + - NAKE - NAKE -NAK Interrupt Enable -When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - 16 - 1 - read-only - - - SLE - SLE -Sleep Interrupt Enable -When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 8 + WAKEUP_INT_STATUS + No description avaiable + 31 1 read-write + + + + PHY_STATUS + No description avaiable + 0x224 + 32 + 0x00000000 + 0x800000F5 + - SRE - SRE -SOF Received Interrupt Enable -When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - 7 + UTMI_CLK_VALID + No description avaiable + 31 1 read-write - URE - URE -USB Reset Interrupt Enable -When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. + LINE_STATE + No description avaiable 6 - 1 + 2 read-write - AAE - AAE -Async Advance Interrupt Enable -When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. + HOST_DISCONNECT + No description avaiable 5 1 read-write - SEE - SEE -System Error Interrupt Enable -When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. + ID_DIG + No description avaiable 4 1 read-write - FRE - FRE -Frame List Rollover Interrupt Enable -When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 3 - 1 - read-write - - - PCE - PCE -Port Change Detect Interrupt Enable -When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + UTMI_SESS_VALID + No description avaiable 2 1 read-write - UEE - UEE -USB Error Interrupt Enable -When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - 1 - 1 - read-write - - - UE - UE -USB Interrupt Enable -When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + VBUS_VALID + No description avaiable 0 1 read-write + + + + SDXC0 + SDXC0 + SDXC + 0xf2030000 + + 0x0 + 0x3008 + registers + + - FRINDEX - USB Frame Index Register - 0x14c + SDMASA + No description avaiable + 0x0 32 0x00000000 - 0x00003FFF + 0xFFFFFFFF - FRINDEX - FRINDEX -Frame Index. -The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. -The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. -USBCMD [Frame List Size] Number Elements N -In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. -In either mode bits 2:0 indicate the current microframe. -The bit field values description below is represented as (Frame List Size) Number Elements N. -00000000000000 - (1024) 12 -00000000000001 - (512) 11 -00000000000010 - (256) 10 -00000000000011 - (128) 9 -00000000000100 - (64) 8 -00000000000101 - (32) 7 -00000000000110 - (16) 6 -00000000000111 - (8) 5 + BLOCKCNT_SDMASA + 32-bit Block Count (SDMA System Address) +- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. +When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. +It can be accessed only if no transaction is executing. Reading this register during data transfers may +return an invalid value. +- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. +The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. +This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. +Following are the values for BLOCKCNT_SDMASA: +- 0xFFFF_FFFF: 4G - 1 Block +- +- 0x0000_0002: 2 Blocks +- 0x0000_0001: 1 Block +- 0x0000_0000: Stop Count +Note: +- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. +The system address must be programmed in the ADMA System Address register. +- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. +Auto CMD23 cannot be used with SDMA. +- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. 0 - 14 + 32 read-write - DEVICEADDR - Device Address Register - 0x154 + BLK_ATTR + No description avaiable + 0x4 32 - 0x00000000 - 0xFF000000 + 0x00020210 + 0xFFFF7FFF - USBADR - USBADR -Device Address. -These bits correspond to the USB device address - 25 - 7 + BLOCK_CNT + 16-bit Block Count +- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. +- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. +Following are the values for BLOCK_CNT: +- 0x0: Stop Count +- 0x1: 1 Block +- 0x2: 2 Blocks +- . +- 0xFFFF: 65535 Blocks +Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. + 16 + 16 read-write - USBADRA - USBADRA -Device Address Advance. Default=0. -When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. -After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. -Hardware will automatically clear this bit on the following conditions: -1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). -2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). -3) Device Reset occurs (USBADR is reset to 0). -NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. -If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - 24 - 1 + SDMA_BUF_BDARY + SDMA Buffer Boundary +These bits specify the size of contiguous buffer in system memory. +The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. +Values: +- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary +- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary +- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary +- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary +- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary +- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary +- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary +- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary + 12 + 3 read-write - - - - PERIODICLISTBASE - Frame List Base Address Register - 0x154 - 32 - 0x00000000 - 0xFFFFF000 - - BASEADR - BASEADR -Base Address (Low). -These bits correspond to memory address signals [31:12], respectively. -Only used by the host controller. - 12 - 20 + XFER_BLOCK_SIZE + Transfer Block Size +These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. +Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: +- 0x1: 1 byte +- 0x2: 2 bytes +- 0x3: 3 bytes +- . +- 0x1FF: 511 byte +- 0x200: 512 byt es +- . +- 0x800: 2048 bytes +Note: This register must be programmed with a non-zero value for data transfer. + 0 + 12 read-write - ASYNCLISTADDR - Next Asynch. Address Register - 0x158 + CMD_ARG + No description avaiable + 0x8 32 0x00000000 - 0xFFFFFFE0 + 0xFFFFFFFF - ASYBASE - ASYBASE -Link Pointer Low (LPL). -These bits correspond to memory address signals [31:5], respectively. This field may only reference a -Queue Head (QH). -Only used by the host controller. - 5 - 27 + ARGUMNET + Command Argument +These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. + 0 + 32 read-write - ENDPTLISTADDR - Endpoint List Address Register - 0x158 + CMD_XFER + No description avaiable + 0xc 32 0x00000000 - 0xFFFFF800 + 0x3FFF01FF - EPBASE - EPBASE -Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - 11 - 21 + CMD_INDEX + Command Index +These bits are set to the command number that is specified in bits 45-40 of the Command Format. + 24 + 6 read-write - - - - BURSTSIZE - Programmable Burst Size Register - 0x160 - 32 - 0x00000000 - 0x0000FFFF - - TXPBURST - TXPBURST -Programmable TX Burst Size. -Default value is determined by TXBURST bits in n_HWTXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from system -memory to the USB bus. - 8 - 8 + CMD_TYPE + Command Type +These bits indicate the command type. +Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. +Values: +0x3 (ABORT_CMD): Abort +0x2 (RESUME_CMD): Resume +0x1 (SUSPEND_CMD): Suspend +0x0 (NORMAL_CMD): Normal + 22 + 2 read-write - RXPBURST - RXPBURST -Programmable RX Burst Size. -Default value is determined by TXBURST bits in n_HWRXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from the -USB bus to system memory. - 0 - 8 + DATA_PRESENT_SEL + Data Present Select +This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: +Command using the CMD line +Command with no data transfer but using busy signal on the DAT[0] line +Resume Command +Values: +0x0 (NO_DATA): No Data Present +0x1 (DATA): Data Present + 21 + 1 read-write - - - - TXFILLTUNING - TX FIFO Fill Tuning Register - 0x164 - 32 - 0x00000000 - 0x003F1F7F - - TXFIFOTHRES - TXFIFOTHRES -FIFO Burst Threshold. (Read/Write) -This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. -The minimum value is 2 and this value should be a low as possible to maximize USB performance. -A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. -This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + CMD_IDX_CHK_ENABLE + Command Index Check Enable +This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. +If the value is not the same, it is reported as a Command Index error. +Note: +Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. +For the tuning command, this bit must always be set to enable the index check. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 20 + 1 + read-write + + + CMD_CRC_CHK_ENABLE + Command CRC Check Enable +This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. +Note: +CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. +For the tuning command, this bit must always be set to 1 to enable the CRC check. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable + 19 + 1 + read-write + + + SUB_CMD_FLAG + Sub Command Flag +This bit distinguishes between a main command and a sub command. +Values: +0x0 (MAIN): Main Command +0x1 (SUB): Sub Command + 18 + 1 + read-write + + + RESP_TYPE_SELECT + Response Type Select +This bit indicates the type of response expected from the card. +Values: +0x0 (NO_RESP): No Response +0x1 (RESP_LEN_136): Response Length 136 +0x2 (RESP_LEN_48): Response Length 48 +0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response 16 - 6 + 2 read-write - TXSCHHEALTH - TXSCHHEALTH -Scheduler Health Counter. (Read/Write To Clear) -Table continues on the next page -This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. + RESP_INT_DISABLE + Response Interrupt Disable +The Host Controller supports response check function to avoid overhead of response error check by the Host driver. +Response types of only R1 and R5 can be checked by the Controller. +If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. +If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. +The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. +Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. +Values: +- 0x0 (ENABLED): Response Interrupt is enabled +- 0x1 (DISABLED): Response Interrupt is disabled 8 - 5 + 1 read-write - TXSCHOH - TXSCHOH -Scheduler Overhead. (Read/Write) [Default = 0] -This register adds an additional fixed offset to the schedule time estimator described above as Tff. -As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. -Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. -The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. -The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. -Default value is '08h' for OTG controller core . + RESP_ERR_CHK_ENABLE + Response Error Check Enable +The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. +If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. +Note: +- Response error check must not be enabled for any response type other than R1 and R5. +- Response check must not be enabled for the tuning command. +Values: +- 0x0 (DISABLED): Response Error Check is disabled +- 0x1 (ENABLED): Response Error Check is enabled + 7 + 1 + read-write + + + RESP_TYPE + Response Type R1/R5 +This bit selects either R1 or R5 as a response type when the Response Error Check is selected. +Error statuses checked in R1: +OUT_OF_RANGE +ADDRESS_ERROR +BLOCK_LEN_ERROR +WP_VIOLATION +CARD_IS_LOCKED +COM_CRC_ERROR +CARD_ECC_FAILED +CC_ERROR +ERROR +Response Flags checked in R5: +COM_CRC_ERROR +ERROR +FUNCTION_NUMBER +OUT_OF_RANGE +Values: +0x0 (RESP_R1): R1 (Memory) +0x1 (RESP_R5): R5 (SDIO) + 6 + 1 + read-write + + + MULTI_BLK_SEL + Multi/Single Block Select +This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. +Values: +0x0 (SINGLE): Single Block +0x1 (MULTI): Multiple Block + 5 + 1 + read-write + + + DATA_XFER_DIR + Data Transfer Direction Select +This bit defines the direction of DAT line data transfers. +This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. +Values: +0x1 (READ): Read (Card to Host) +0x0 (WRITE): Write (Host to Card) + 4 + 1 + read-write + + + AUTO_CMD_ENABLE + Auto Command Enable +This field determines use of Auto Command functions. +Note: In SDIO, this field must be set as 00b (Auto Command Disabled). +Values: +0x0 (AUTO_CMD_DISABLED): Auto Command Disabled +0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable +0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable +0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel + 2 + 2 + read-write + + + BLOCK_COUNT_ENABLE + Block Count Enable +This bit is used to enable the Block Count register, which is relevant for multiple block transfers. +If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. +The Host Driver must set this bit to 0 when ADMA is used. +Values: +0x1 (ENABLED): Enable +0x0 (DISABLED): Disable + 1 + 1 + read-write + + + DMA_ENABLE + DMA Enable +This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. +You can select one of the DMA modes by using DMA Select in the Host Control 1 register. +Values: +0x1 (ENABLED): DMA Data transfer +0x0 (DISABLED): No data transfer or Non-DMA data transfer 0 - 7 + 1 read-write - ENDPTNAK - Endpoint NAK Register - 0x178 + RESP_RESP01 + No description avaiable + 0x10 32 0x00000000 - 0x00FF00FF + 0xFFFFFFFF - EPTN - EPTN -TX Endpoint NAK - R/WC. -Each TX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received IN token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 8 - read-write + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. + 0 + 32 + read-only + + + + RESP_RESP23 + No description avaiable + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + - EPRN - EPRN -RX Endpoint NAK - R/WC. -Each RX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. 0 - 8 - read-write + 32 + read-only - ENDPTNAKEN - Endpoint NAK Enable Register - 0x17c + RESP_RESP45 + No description avaiable + 0x18 32 0x00000000 - 0x00FF00FF + 0xFFFFFFFF - EPTNE - EPTNE -TX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the -corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 8 - read-write + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. + 0 + 32 + read-only + + + + RESP_RESP67 + No description avaiable + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + - EPRNE - EPRNE -RX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the -corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 + RESP01 + Command Response +These bits reflect 39-8 bits of SD/eMMC Response Field. +Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. 0 - 8 - read-write + 32 + read-only - PORTSC1 - Port Status & Control - 0x184 + BUF_DATA + No description avaiable + 0x20 32 0x00000000 - 0x3DFF1FFF + 0xFFFFFFFF - STS - STS -Serial Transceiver Select -1 Serial Interface Engine is selected -0 Parallel Interface signals is selected -Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. -When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - 29 - 1 + BUF_DATA + Buffer Data +These bits enable access to the Host Controller packet buffer. + 0 + 32 read-write + + + + PSTATE + No description avaiable + 0x24 + 32 + 0x00000000 + 0x19FF0FFF + - PTW - PTW -Parallel Transceiver Width -This bit has no effect if serial interface engine is used. -0 - Select the 8-bit UTMI interface [60MHz] -1 - Select the 16-bit UTMI interface [30MHz] + SUB_CMD_STAT + Sub Command Status +This bit is used to distinguish between a main command and a sub command status. +Values: +0x0 (FALSE): Main Command Status +0x1 (TRUE): Sub Command Status 28 1 - read-write + read-only - PSPD - PSPD -Port Speed - Read Only. -This register field indicates the speed at which the port is operating. -00 - Full Speed -01 - Low Speed -10 - High Speed -11 - Undefined - 26 - 2 + CMD_ISSUE_ERR + Command Not Issued by Error +This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. +Values: +0x0 (FALSE): No error for issuing a command +0x1 (TRUE): Command cannot be issued + 27 + 1 read-only - PFSC - PFSC -Port Force Full Speed Connect - Read/Write. Default = 0b. -When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp -sequence that allows the port to identify itself as High Speed. -0 - Normal operation -1 - Forced to full speed + CMD_LINE_LVL + Command-Line Signal Level +This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. 24 1 - read-write + read-only - PHCD - PHCD -PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. -When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY -clock. -NOTE: The PHY clock cannot be disabled if it is being used as the system clock. -In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD -Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend -will be cleared automatically when the host initials resume. Before forcing a resume from the device, the -device controller driver must clear this bit. -In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put -into suspend mode or when no downstream device is connected. Low power suspend is completely -under the control of software. -0 - Enable PHY clock -1 - Disable PHY clock - 23 - 1 - read-write + DAT_3_0 + DAT[3:0] Line Signal Level +This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. + 20 + 4 + read-only - WKOC - WKOC -Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. -Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. -This field is zero if Port Power(PORTSC1) is zero. - 22 + WR_PROTECT_SW_LVL + Write Protect Switch Pin Level +This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. +Values: +0x0 (FALSE): Write protected +0x1 (TRUE): Write enabled + 19 1 - read-write + read-only - WKDC - WKDC -Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables -the port to be sensitive to device disconnects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 21 + CARD_DETECT_PIN_LEVEL + Card Detect Pin Level +This bit reflects the inverse synchronized value of the card_detect_n signal. +Values: +0x0 (FALSE): No card present +0x1 (TRUE): Card Present + 18 1 - read-write + read-only - WKCN - WKCN -Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. -Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 20 + CARD_STABLE + Card Stable +This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. +Values: +0x0 (FALSE): Reset or Debouncing +0x1 (TRUE): No Card or Inserted + 17 1 - read-write + read-only - PTC - PTC -Port Test Control - Read/Write. Default = 0000b. -Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. -The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. -NOTE: Low speed operations are not supported as a peripheral device. -Any other value than zero indicates that the port is operating in test mode. -Value Specific Test -0000 - TEST_MODE_DISABLE -0001 - J_STATE -0010 - K_STATE -0011 - SE0 (host) / NAK (device) -0100 - Packet -0101 - FORCE_ENABLE_HS -0110 - FORCE_ENABLE_FS -0111 - FORCE_ENABLE_LS -1000-1111 - Reserved + CARD_INSERTED + Card Inserted +This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. +Values: +0x0 (FALSE): Reset, Debouncing, or No card +0x1 (TRUE): Card Inserted 16 - 4 - read-write + 1 + read-only - PP - PP -Port Power (PP)-Read/Write or Read Only. -The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: -PPC -PP Operation -0 -1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. -1 -1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. -When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). -This feature is implemented in all controller cores (PPC = 1). - 12 + BUF_RD_ENABLE + Buffer Read Enable +This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. +Values: +0x0 (DISABLED): Read disable +0x1 (ENABLED): Read enable + 11 1 - read-write + read-only - LS - LS -Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal -lines. -In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because -the port controller state machine and the port routing manage the connection of LS and FS. -In device mode, the use of linestate by the device controller driver is not necessary. -The encoding of the bits are: -Bits [11:10] Meaning -00 - SE0 -01 - K-state -10 - J-state -11 - Undefined + BUF_WR_ENABLE + Buffer Write Enable +This bit is used for non-DMA transfers. This bit is set if space is available for writing data. +Values: +0x0 (DISABLED): Write disable +0x1 (ENABLED): Write enable 10 - 2 + 1 read-only - HSP - HSP -High-Speed Port - Read Only. Default = 0b. -When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the -host/device connected to the port is not in a high-speed mode. -NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + RD_XFER_ACTIVE + Read Transfer Active +This bit indicates whether a read transfer is active for SD/eMMC mode. +Values: +0x0 (INACTIVE): No valid data +0x1 (ACTIVE): Transferring data 9 1 read-only - PR - PR -Port Reset - Read/Write or Read Only. Default = 0b. -In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. -When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. -In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + WR_XFER_ACTIVE + Write Transfer Active +This status indicates whether a write transfer is active for SD/eMMC mode. +Values: +0x0 (INACTIVE): No valid data +0x1 (ACTIVE): Transferring data 8 1 - read-write - - - SUSP - SUSP -Suspend - Read/Write or Read Only. Default = 0b. -1=Port in suspend state. 0=Port not in suspend state. -In Host Mode: Read/Write. -Port Enabled Bit and Suspend bit of this register define the port states as follows: -Bits [Port Enabled, Suspend] Port State -0x Disable -10 Enable -11 Suspend -When in suspend state, downstream propagation of data is blocked on this port, except for port reset. -The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. -The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. -If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: Read Only. -In device mode this bit is a read only status bit. - 7 - 1 - read-write - - - FPR - FPR -Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. -In Host Mode: -Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. -This bit will automatically change to zero after the resume sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. -Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. -The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. -Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. -This field is zero if Port Power(PORTSC1) is zero in host mode. -This bit is not-EHCI compatible. -In Device mode: -After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. -The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -The bit will be cleared when the device returns to normal operation. - Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - 6 - 1 - read-write - - - OCC - OCC -Over-current Change-R/WC. Default=0. -This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - 5 - 1 - read-write + read-only - OCA - OCA -Over-current Active-Read Only. Default 0. -This bit will automatically transition from one to zero when the over current condition is removed. -0 - This port does not have an over-current condition. -1 - This port currently has an over-current condition + DAT_7_4 + DAT[7:4] Line Signal Level +This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. 4 - 1 + 4 read-only - PEC - PEC -Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. -In Host Mode: -For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -Software clears this by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero. -In Device mode: -The device port is always enabled, so this bit is always '0b'. + RE_TUNE_REQ + Re-Tuning Request +SDXC does not generate retuning request. The software must maintain the Retuning timer. 3 1 - read-write + read-only - PE - PE -Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. -In Host Mode: -Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. -Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. -Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. -When the port is disabled, (0b) downstream propagation of data is blocked except for reset. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -The device port is always enabled, so this bit is always '1b'. + DAT_LINE_ACTIVE + DAT Line Active ( +This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. +In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. +In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. +For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. +Values: +0x0 (INACTIVE): DAT Line Inactive +0x1 (ACTIVE): DAT Line Active 2 1 - read-write + read-only - CSC - CSC -Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. -In Host Mode: -Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. -For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -This bit is undefined in device controller mode. + DAT_INHIBIT + Command Inhibit (DAT) +This bit is generated if either DAT line active or Read transfer active is set to 1. +If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. +Values: +0x0 (READY): Can issue command which used DAT line +0x1 (NOT_READY): Cannot issue command which used DAT line 1 1 - read-write + read-only - CCS - CCS -Current Connect Status-Read Only. -In Host Mode: -1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended. + CMD_INHIBIT + Command Inhibit (CMD) +This bit indicates the following : +If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. +This bit is set when the command register is written. This bit is cleared when the command response is received. +This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. +Values: +0x0 (READY): Host Controller is ready to issue a command +0x1 (NOT_READY): Host Controller is not ready to issue a command 0 1 - read-write + read-only - OTGSC - On-The-Go Status & control Register - 0x1a4 + PROT_CTRL + No description avaiable + 0x28 32 0x00000000 - 0x07070723 + 0x070F0F3E - ASVIE - ASVIE -A Session Valid Interrupt Enable - Read/Write. + CARD_REMOVAL + Wakeup Event Enable on SD Card Removal +This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. +For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable 26 1 read-write - AVVIE - AVVIE -A VBus Valid Interrupt Enable - Read/Write. -Setting this bit enables the A VBus valid interrupt. + CARD_INSERT + Wakeup Event Enable on SD Card Insertion +This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. +FN_WUS (Wake Up Support) in CIS does not affect this bit. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable 25 1 read-write - IDIE - IDIE -USB ID Interrupt Enable - Read/Write. -Setting this bit enables the USB ID interrupt. + CARD_INT + Wakeup Event Enable on Card Interrupt +This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. +This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. +Values: +0x0 (DISABLED): Disable +0x1 (ENABLED): Enable 24 1 read-write - ASVIS - ASVIS -A Session Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the A session valid threshold. -Software must write a one to clear this bit. - 18 + INT_AT_BGAP + Interrupt At Block Gap +This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. +Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. +Values: +0x0 (DISABLE): Disabled +0x1 (ENABLE): Enabled + 19 1 read-write - AVVIS - AVVIS -A VBus Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. -Software must write a one to clear this bit. - 17 + RD_WAIT_CTRL + Read Wait Control +This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. +Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. +Values: +0x0 (DISABLE): Disable Read Wait Control +0x1 (ENABLE): Enable Read Wait Control + 18 1 read-write - IDIS - IDIS -USB ID Interrupt Status - Read/Write. -This bit is set when a change on the ID input has been detected. -Software must write a one to clear this bit. - 16 + CONTINUE_REQ + Continue Request +This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. +The Host Controller automatically clears this bit when the transaction restarts. +If stop at block gap request is set to 1, any write to this bit is ignored. +Values: +0x0 (NO_AFFECT): No Affect +0x1 (RESTART): Restart + 17 1 read-write - ASV - ASV -A Session Valid - Read Only. -Indicates VBus is above the A session valid threshold. - 10 + STOP_BG_REQ + Stop At Block Gap Request +This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. +Values: +0x0 (XFER): Transfer +0x1 (STOP): Stop + 16 1 - read-only + read-write - AVV - AVV -A VBus Valid - Read Only. -Indicates VBus is above the A VBus valid threshold. + SD_BUS_VOL_VDD1 + SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD +These bits enable the Host Driver to select the voltage level for an SD/eMMC card. +Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. +If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. +The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. +SD Bus Voltage Select options: +0x7 : 3.3V(Typical) +0x6 : 3.0V(Typical) +0x5 : 1.8V(Typical) for Embedded +0x4 : 0x0 - Reserved +eMMC Bus Voltage Select options: +0x7 : 3.3V(Typical) +0x6 : 1.8V(Typical) +0x5 : 1.2V(Typical) +0x4 : 0x0 - Reserved +Values: +0x7 (V_3_3): 3.3V (Typ.) +0x6 (V_3_0): 3.0V (Typ.) +0x5 (V_1_8): 1.8V (Typ.) for Embedded +0x4 (RSVD4): Reserved +0x3 (RSVD3): Reserved +0x2 (RSVD2): Reserved +0x1 (RSVD1): Reserved +0x0 (RSVD0): Reserved 9 - 1 - read-only + 3 + read-write - ID - ID -USB ID - Read Only. -0 = A device, 1 = B device + SD_BUS_PWR_VDD1 + SD Bus Power for VDD1 +This bit enables VDD1 power of the card. +This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. +Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. +In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_IN bit in the CLK_CTRL_R register. +Values: +0x0 (OFF): Power off +0x1 (ON): Power on 8 1 - read-only + read-write - IDPU - IDPU -ID Pullup - Read/Write -This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input -will not be sampled. + EXT_DAT_XFER + Extended Data Transfer Width +This bit controls 8-bit bus width mode of embedded device. +Values: +0x1 (EIGHT_BIT): 8-bit Bus Width +0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width 5 1 read-write - VC - VC -VBUS Charge - Read/Write. -Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - 1 + DMA_SEL + DMA Select +This field is used to select the DMA type. +When Host Version 4 Enable is 1 in Host Control 2 register: +0x0 : SDMA is selected +0x1 : Reserved +0x2 : ADMA2 is selected +0x3 : ADMA2 or ADMA3 is selected +When Host Version 4 Enable is 0 in Host Control 2 register: +0x0 : SDMA is selected +0x1 : Reserved +0x2 : 32-bit Address ADMA2 is selected +0x3 : 64-bit Address ADMA2 is selected +Values: +0x0 (SDMA): SDMA is selected +0x1 (RSVD_BIT): Reserved +0x2 (ADMA2): ADMA2 is selected +0x3 (ADMA2_3): ADMA2 or ADMA3 is selected + 3 + 2 + read-write + + + HIGH_SPEED_EN + High Speed Enable +this bit is used to determine the selection of preset value for High Speed mode. +Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. +Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. +Values: +0x1 (HIGH_SPEED): High Speed mode +0x0 (NORMAL_SPEED): Normal Speed mode + 2 1 read-write - VD - VD -VBUS_Discharge - Read/Write. -Setting this bit causes VBus to discharge through a resistor. - 0 + DAT_XFER_WIDTH + Data Transfer Width +For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. +The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. +Values: +0x1 (FOUR_BIT): 4-bit mode +0x0 (ONE_BIT): 1-bit mode + 1 1 read-write - USBMODE - USB Device Mode Register - 0x1a8 + SYS_CTRL + No description avaiable + 0x2c 32 0x00000000 - 0x0000001F + 0x070FFFEF - SDIS - SDIS -Stream Disable Mode. (0 - Inactive [default]; 1 - Active) -Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. -This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. -Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. -Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. -NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for -the scheduler when using this feature. -NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - 4 - 1 - read-write - - - SLOM - SLOM -Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . -0 - Setup Lockouts On (default); -1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - 3 - 1 - read-write - - - ES - ES -Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the -host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected -by the value of this bit because they are based upon the 32-bit word. -Bit Meaning -0 - Little Endian [Default] -1 - Big Endian - 2 - 1 - read-write - - - CM - CM -Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only -implementations. For those designs that contain both host & device capability, the controller defaults to -an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ -device controllers, this register can only be written once after reset. If it is necessary to switch modes, -software must reset the controller by writing to the RESET bit in the USBCMD register before -reprogramming this register. -For OTG controller core, reset value is '00b'. -00 - Idle [Default for combination host/device] -01 - Reserved -10 - Device Controller [Default for device only controller] -11 - Host Controller [Default for host only controller] - 0 - 2 - read-write - - - - - ENDPTSETUPSTAT - Endpoint Setup Status Register - 0x1ac - 32 - 0x00000000 - 0x000000FF - - - ENDPTSETUPSTAT - ENDPTSETUPSTAT -Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. -Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. -The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. -This register is only used in device mode. - 0 - 8 - read-write - - - - - ENDPTPRIME - Endpoint Prime Register - 0x1b0 - 32 - 0x00000000 - 0x00FF00FF - - - PETB - PETB -Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a -buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. -Software should write a one to the corresponding bit when posting a new transfer descriptor to an -endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor -from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated -endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PETB[N] - Endpoint #N, N is in 0..7 - 16 - 8 - read-write - - - PERB - PERB -Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. -Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. -Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. -Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PERB[N] - Endpoint #N, N is in 0..7 - 0 - 8 - read-write - - - - - ENDPTFLUSH - Endpoint Flush Register - 0x1b4 - 32 - 0x00000000 - 0x00FF00FF - - - FETB - FETB -Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. -If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FETB[N] - Endpoint #N, N is in 0..7 - 16 - 8 - read-write - - - FERB - FERB -Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FERB[N] - Endpoint #N, N is in 0..7 - 0 - 8 - read-write - - - - - ENDPTSTAT - Endpoint Status Register - 0x1b8 - 32 - 0x00000000 - 0x00FF00FF - - - ETBR - ETBR -Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. -This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. -There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. -This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. -Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. -ETBR[N] - Endpoint #N, N is in 0..7 - 16 - 8 - read-only - - - ERBR - ERBR -Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective -endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a -corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the -ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB -traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the -USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations -when a dTD is retired, and the dQH is updated. -ERBR[N] - Endpoint #N, N is in 0..7 - 0 - 8 - read-only - - - - - ENDPTCOMPLETE - Endpoint Complete Register - 0x1bc - 32 - 0x00000000 - 0x00FF00FF - - - ETCE - ETCE -Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. -If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. -ETCE[N] - Endpoint #N, N is in 0..7 - 16 - 8 - read-write - - - ERCE - ERCE -Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred -and software should read the corresponding endpoint queue to determine the transfer status. If the -corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the -USBINT . Writing one clears the corresponding bit in this register. -ERCE[N] - Endpoint #N, N is in 0..7 - 0 - 8 - read-write - - - - - ENDPTCTRL_ENDPTCTRL0 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1c0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL1 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1c4 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL2 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1c8 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL3 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1cc - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL4 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1d0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL5 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1d4 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL6 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1d8 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - ENDPTCTRL_ENDPTCTRL7 - Endpoint Control0 Register... Endpoint Control7 Register - 0x1dc - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - OTG_CTRL0 - No description avaiable - 0x200 - 32 - 0x00000000 - 0x020B3F90 - - - OTG_WKDPDMCHG_EN - No description avaiable - 25 - 1 - read-write - - - AUTORESUME_EN - No description avaiable - 19 - 1 - read-write - - - OTG_VBUS_WAKEUP_EN - No description avaiable - 17 - 1 - read-write - - - OTG_ID_WAKEUP_EN - No description avaiable - 16 - 1 - read-write - - - OTG_VBUS_SOURCE_SEL - No description avaiable - 13 - 1 - read-write - - - OTG_UTMI_SUSPENDM_SW - default 0 for naneng usbphy - 12 - 1 - read-write - - - OTG_UTMI_RESET_SW - default 1 for naneng usbphy - 11 - 1 - read-write - - - OTG_WAKEUP_INT_ENABLE - No description avaiable - 10 - 1 - read-write - - - OTG_POWER_MASK - No description avaiable - 9 - 1 - read-write - - - OTG_OVER_CUR_POL - No description avaiable - 8 - 1 - read-write - - - OTG_OVER_CUR_DIS - No description avaiable - 7 - 1 - read-write - - - SER_MODE_SUSPEND_EN - for naneng usbphy, only switch to serial mode when suspend - 4 - 1 - read-write - - - - - PHY_CTRL0 - No description avaiable - 0x210 - 32 - 0x00000000 - 0x02007007 - - - GPIO_ID_SEL_N - No description avaiable - 25 - 1 - read-write - - - ID_DIG_OVERRIDE - No description avaiable - 14 - 1 - read-write - - - SESS_VALID_OVERRIDE - No description avaiable - 13 - 1 - read-write - - - VBUS_VALID_OVERRIDE - No description avaiable - 12 - 1 - read-write - - - ID_DIG_OVERRIDE_EN - No description avaiable - 2 - 1 - read-write - - - SESS_VALID_OVERRIDE_EN - No description avaiable - 1 - 1 - read-write - - - VBUS_VALID_OVERRIDE_EN - No description avaiable - 0 - 1 - read-write - - - - - PHY_CTRL1 - No description avaiable - 0x214 - 32 - 0x00000000 - 0x00100002 - - - UTMI_CFG_RST_N - No description avaiable - 20 - 1 - read-write - - - UTMI_OTG_SUSPENDM - OTG suspend, not utmi_suspendm - 1 - 1 - read-write - - - - - TOP_STATUS - No description avaiable - 0x220 - 32 - 0x00000000 - 0x80000000 - - - WAKEUP_INT_STATUS - No description avaiable - 31 - 1 - read-write - - - - - PHY_STATUS - No description avaiable - 0x224 - 32 - 0x00000000 - 0x800000F5 - - - UTMI_CLK_VALID - No description avaiable - 31 - 1 - read-write - - - LINE_STATE - No description avaiable - 6 - 2 - read-write - - - HOST_DISCONNECT - No description avaiable - 5 - 1 - read-write - - - ID_DIG - No description avaiable - 4 - 1 - read-write - - - UTMI_SESS_VALID - No description avaiable - 2 - 1 - read-write - - - VBUS_VALID - No description avaiable - 0 - 1 - read-write - - - - - - - SDXC0 - SDXC0 - SDXC - 0xf2030000 - - 0x0 - 0x3008 - registers - - - - SDMASA - No description avaiable - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKCNT_SDMASA - 32-bit Block Count (SDMA System Address) -- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. -When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. -It can be accessed only if no transaction is executing. Reading this register during data transfers may -return an invalid value. -- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. -The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. -This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. -Following are the values for BLOCKCNT_SDMASA: -- 0xFFFF_FFFF: 4G - 1 Block -- -- 0x0000_0002: 2 Blocks -- 0x0000_0001: 1 Block -- 0x0000_0000: Stop Count -Note: -- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. -The system address must be programmed in the ADMA System Address register. -- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. -Auto CMD23 cannot be used with SDMA. -- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. - 0 - 32 - read-write - - - - - BLK_ATTR - No description avaiable - 0x4 - 32 - 0x00020210 - 0xFFFF7FFF - - - BLOCK_CNT - 16-bit Block Count -- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. -- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. -Following are the values for BLOCK_CNT: -- 0x0: Stop Count -- 0x1: 1 Block -- 0x2: 2 Blocks -- . -- 0xFFFF: 65535 Blocks -Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. - 16 - 16 - read-write - - - SDMA_BUF_BDARY - SDMA Buffer Boundary -These bits specify the size of contiguous buffer in system memory. -The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. -Values: -- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary -- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary -- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary -- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary -- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary -- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary -- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary -- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary - 12 - 3 - read-write - - - XFER_BLOCK_SIZE - Transfer Block Size -These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. -Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: -- 0x1: 1 byte -- 0x2: 2 bytes -- 0x3: 3 bytes -- . -- 0x1FF: 511 byte -- 0x200: 512 byt es -- . -- 0x800: 2048 bytes -Note: This register must be programmed with a non-zero value for data transfer. - 0 - 12 - read-write - - - - - CMD_ARG - No description avaiable - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGUMNET - Command Argument -These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. - 0 - 32 - read-write - - - - - CMD_XFER - No description avaiable - 0xc - 32 - 0x00000000 - 0x3FFF01FF - - - CMD_INDEX - Command Index -These bits are set to the command number that is specified in bits 45-40 of the Command Format. - 24 - 6 - read-write - - - CMD_TYPE - Command Type -These bits indicate the command type. -Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. -Values: -0x3 (ABORT_CMD): Abort -0x2 (RESUME_CMD): Resume -0x1 (SUSPEND_CMD): Suspend -0x0 (NORMAL_CMD): Normal - 22 - 2 - read-write - - - DATA_PRESENT_SEL - Data Present Select -This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: -Command using the CMD line -Command with no data transfer but using busy signal on the DAT[0] line -Resume Command -Values: -0x0 (NO_DATA): No Data Present -0x1 (DATA): Data Present - 21 - 1 - read-write - - - CMD_IDX_CHK_ENABLE - Command Index Check Enable -This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. -If the value is not the same, it is reported as a Command Index error. -Note: -Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. -For the tuning command, this bit must always be set to enable the index check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 20 - 1 - read-write - - - CMD_CRC_CHK_ENABLE - Command CRC Check Enable -This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. -Note: -CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. -For the tuning command, this bit must always be set to 1 to enable the CRC check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 19 - 1 - read-write - - - SUB_CMD_FLAG - Sub Command Flag -This bit distinguishes between a main command and a sub command. -Values: -0x0 (MAIN): Main Command -0x1 (SUB): Sub Command - 18 - 1 - read-write - - - RESP_TYPE_SELECT - Response Type Select -This bit indicates the type of response expected from the card. -Values: -0x0 (NO_RESP): No Response -0x1 (RESP_LEN_136): Response Length 136 -0x2 (RESP_LEN_48): Response Length 48 -0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response - 16 - 2 - read-write - - - RESP_INT_DISABLE - Response Interrupt Disable -The Host Controller supports response check function to avoid overhead of response error check by the Host driver. -Response types of only R1 and R5 can be checked by the Controller. -If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. -If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. -The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. -Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. -Values: -- 0x0 (ENABLED): Response Interrupt is enabled -- 0x1 (DISABLED): Response Interrupt is disabled - 8 - 1 - read-write - - - RESP_ERR_CHK_ENABLE - Response Error Check Enable -The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. -Note: -- Response error check must not be enabled for any response type other than R1 and R5. -- Response check must not be enabled for the tuning command. -Values: -- 0x0 (DISABLED): Response Error Check is disabled -- 0x1 (ENABLED): Response Error Check is enabled - 7 - 1 - read-write - - - RESP_TYPE - Response Type R1/R5 -This bit selects either R1 or R5 as a response type when the Response Error Check is selected. -Error statuses checked in R1: -OUT_OF_RANGE -ADDRESS_ERROR -BLOCK_LEN_ERROR -WP_VIOLATION -CARD_IS_LOCKED -COM_CRC_ERROR -CARD_ECC_FAILED -CC_ERROR -ERROR -Response Flags checked in R5: -COM_CRC_ERROR -ERROR -FUNCTION_NUMBER -OUT_OF_RANGE -Values: -0x0 (RESP_R1): R1 (Memory) -0x1 (RESP_R5): R5 (SDIO) - 6 - 1 - read-write - - - MULTI_BLK_SEL - Multi/Single Block Select -This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. -Values: -0x0 (SINGLE): Single Block -0x1 (MULTI): Multiple Block - 5 - 1 - read-write - - - DATA_XFER_DIR - Data Transfer Direction Select -This bit defines the direction of DAT line data transfers. -This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. -Values: -0x1 (READ): Read (Card to Host) -0x0 (WRITE): Write (Host to Card) - 4 - 1 - read-write - - - AUTO_CMD_ENABLE - Auto Command Enable -This field determines use of Auto Command functions. -Note: In SDIO, this field must be set as 00b (Auto Command Disabled). -Values: -0x0 (AUTO_CMD_DISABLED): Auto Command Disabled -0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable -0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable -0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel - 2 - 2 - read-write - - - BLOCK_COUNT_ENABLE - Block Count Enable -This bit is used to enable the Block Count register, which is relevant for multiple block transfers. -If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. -The Host Driver must set this bit to 0 when ADMA is used. -Values: -0x1 (ENABLED): Enable -0x0 (DISABLED): Disable - 1 - 1 - read-write - - - DMA_ENABLE - DMA Enable -This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. -You can select one of the DMA modes by using DMA Select in the Host Control 1 register. -Values: -0x1 (ENABLED): DMA Data transfer -0x0 (DISABLED): No data transfer or Non-DMA data transfer - 0 - 1 - read-write - - - - - RESP_RESP01 - No description avaiable - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. - 0 - 32 - read-only - - - - - RESP_RESP23 - No description avaiable - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. - 0 - 32 - read-only - - - - - RESP_RESP45 - No description avaiable - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. - 0 - 32 - read-only - - - - - RESP_RESP67 - No description avaiable - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register. - 0 - 32 - read-only - - - - - BUF_DATA - No description avaiable - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUF_DATA - Buffer Data -These bits enable access to the Host Controller packet buffer. - 0 - 32 - read-write - - - - - PSTATE - No description avaiable - 0x24 - 32 - 0x00000000 - 0x19FF0FFF - - - SUB_CMD_STAT - Sub Command Status -This bit is used to distinguish between a main command and a sub command status. -Values: -0x0 (FALSE): Main Command Status -0x1 (TRUE): Sub Command Status - 28 - 1 - read-only - - - CMD_ISSUE_ERR - Command Not Issued by Error -This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. -Values: -0x0 (FALSE): No error for issuing a command -0x1 (TRUE): Command cannot be issued - 27 - 1 - read-only - - - CMD_LINE_LVL - Command-Line Signal Level -This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. - 24 - 1 - read-only - - - DAT_3_0 - DAT[3:0] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. - 20 - 4 - read-only - - - WR_PROTECT_SW_LVL - Write Protect Switch Pin Level -This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. -Values: -0x0 (FALSE): Write protected -0x1 (TRUE): Write enabled - 19 - 1 - read-only - - - CARD_DETECT_PIN_LEVEL - Card Detect Pin Level -This bit reflects the inverse synchronized value of the card_detect_n signal. -Values: -0x0 (FALSE): No card present -0x1 (TRUE): Card Present - 18 - 1 - read-only - - - CARD_STABLE - Card Stable -This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. -Values: -0x0 (FALSE): Reset or Debouncing -0x1 (TRUE): No Card or Inserted - 17 - 1 - read-only - - - CARD_INSERTED - Card Inserted -This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. -Values: -0x0 (FALSE): Reset, Debouncing, or No card -0x1 (TRUE): Card Inserted - 16 - 1 - read-only - - - BUF_RD_ENABLE - Buffer Read Enable -This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. -Values: -0x0 (DISABLED): Read disable -0x1 (ENABLED): Read enable - 11 - 1 - read-only - - - BUF_WR_ENABLE - Buffer Write Enable -This bit is used for non-DMA transfers. This bit is set if space is available for writing data. -Values: -0x0 (DISABLED): Write disable -0x1 (ENABLED): Write enable - 10 - 1 - read-only - - - RD_XFER_ACTIVE - Read Transfer Active -This bit indicates whether a read transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 9 - 1 - read-only - - - WR_XFER_ACTIVE - Write Transfer Active -This status indicates whether a write transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 8 - 1 - read-only - - - DAT_7_4 - DAT[7:4] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. - 4 - 4 - read-only - - - RE_TUNE_REQ - Re-Tuning Request -SDXC does not generate retuning request. The software must maintain the Retuning timer. - 3 - 1 - read-only - - - DAT_LINE_ACTIVE - DAT Line Active ( -This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. -In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. -In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. -For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. -Values: -0x0 (INACTIVE): DAT Line Inactive -0x1 (ACTIVE): DAT Line Active - 2 - 1 - read-only - - - DAT_INHIBIT - Command Inhibit (DAT) -This bit is generated if either DAT line active or Read transfer active is set to 1. -If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. -Values: -0x0 (READY): Can issue command which used DAT line -0x1 (NOT_READY): Cannot issue command which used DAT line - 1 - 1 - read-only - - - CMD_INHIBIT - Command Inhibit (CMD) -This bit indicates the following : -If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. -This bit is set when the command register is written. This bit is cleared when the command response is received. -This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. -Values: -0x0 (READY): Host Controller is ready to issue a command -0x1 (NOT_READY): Host Controller is not ready to issue a command - 0 - 1 - read-only - - - - - PROT_CTRL - No description avaiable - 0x28 - 32 - 0x00000000 - 0x070F0F3E - - - CARD_REMOVAL - Wakeup Event Enable on SD Card Removal -This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. -For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 26 - 1 - read-write - - - CARD_INSERT - Wakeup Event Enable on SD Card Insertion -This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. -FN_WUS (Wake Up Support) in CIS does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 25 - 1 - read-write - - - CARD_INT - Wakeup Event Enable on Card Interrupt -This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. -This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 24 - 1 - read-write - - - INT_AT_BGAP - Interrupt At Block Gap -This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. -Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. -Values: -0x0 (DISABLE): Disabled -0x1 (ENABLE): Enabled - 19 - 1 - read-write - - - RD_WAIT_CTRL - Read Wait Control -This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. -Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. -Values: -0x0 (DISABLE): Disable Read Wait Control -0x1 (ENABLE): Enable Read Wait Control - 18 - 1 - read-write - - - CONTINUE_REQ - Continue Request -This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. -The Host Controller automatically clears this bit when the transaction restarts. -If stop at block gap request is set to 1, any write to this bit is ignored. -Values: -0x0 (NO_AFFECT): No Affect -0x1 (RESTART): Restart - 17 - 1 - read-write - - - STOP_BG_REQ - Stop At Block Gap Request -This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. -Values: -0x0 (XFER): Transfer -0x1 (STOP): Stop - 16 - 1 - read-write - - - SD_BUS_VOL_VDD1 - SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD -These bits enable the Host Driver to select the voltage level for an SD/eMMC card. -Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. -If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. -The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. -SD Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 3.0V(Typical) -0x5 : 1.8V(Typical) for Embedded -0x4 : 0x0 - Reserved -eMMC Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 1.8V(Typical) -0x5 : 1.2V(Typical) -0x4 : 0x0 - Reserved -Values: -0x7 (V_3_3): 3.3V (Typ.) -0x6 (V_3_0): 3.0V (Typ.) -0x5 (V_1_8): 1.8V (Typ.) for Embedded -0x4 (RSVD4): Reserved -0x3 (RSVD3): Reserved -0x2 (RSVD2): Reserved -0x1 (RSVD1): Reserved -0x0 (RSVD0): Reserved - 9 - 3 - read-write - - - SD_BUS_PWR_VDD1 - SD Bus Power for VDD1 -This bit enables VDD1 power of the card. -This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. -Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. -In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_IN bit in the CLK_CTRL_R register. -Values: -0x0 (OFF): Power off -0x1 (ON): Power on - 8 - 1 - read-write - - - EXT_DAT_XFER - Extended Data Transfer Width -This bit controls 8-bit bus width mode of embedded device. -Values: -0x1 (EIGHT_BIT): 8-bit Bus Width -0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width - 5 - 1 - read-write - - - DMA_SEL - DMA Select -This field is used to select the DMA type. -When Host Version 4 Enable is 1 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : ADMA2 is selected -0x3 : ADMA2 or ADMA3 is selected -When Host Version 4 Enable is 0 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : 32-bit Address ADMA2 is selected -0x3 : 64-bit Address ADMA2 is selected -Values: -0x0 (SDMA): SDMA is selected -0x1 (RSVD_BIT): Reserved -0x2 (ADMA2): ADMA2 is selected -0x3 (ADMA2_3): ADMA2 or ADMA3 is selected - 3 - 2 - read-write - - - HIGH_SPEED_EN - High Speed Enable -this bit is used to determine the selection of preset value for High Speed mode. -Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. -Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. -Values: -0x1 (HIGH_SPEED): High Speed mode -0x0 (NORMAL_SPEED): Normal Speed mode - 2 - 1 - read-write - - - DAT_XFER_WIDTH - Data Transfer Width -For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. -The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. -Values: -0x1 (FOUR_BIT): 4-bit mode -0x0 (ONE_BIT): 1-bit mode - 1 - 1 - read-write - - - - - SYS_CTRL - No description avaiable - 0x2c - 32 - 0x00000000 - 0x070FFFEF - - - SW_RST_DAT - Software Reset For DAT line -This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. -The following registers and bits are cleared by this bit: -Buffer Data Port register --Buffer is cleared and initialized. -Present state register --Buffer Read Enable --Buffer Write Enable --Read Transfer Active --Write Transfer Active --DAT Line Active --Command Inhibit (DAT) -Block Gap Control register --Continue Request --Stop At Block Gap Request -Normal Interrupt status register --Buffer Read Ready --Buffer Write Ready --DMA Interrupt --Block Gap Event --Transfer Complete -In UHS-II mode, this bit shall be set to 0 -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 26 - 1 - read-write - - - SW_RST_CMD - Software Reset For CMD line -This bit resets only a part of the command circuit to be able to issue a command. -It bit is also used to initialize a UHS-II command circuit. -This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. -Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. -The following registers and bits are cleared by this bit: -Present State register : Command Inhibit (CMD) bit -Normal Interrupt Status register : Command Complete bit -Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 25 - 1 - read-write - - - SW_RST_ALL - Software Reset For All -This reset affects the entire Host Controller except for the card detection circuit. -During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. -All registers are reset except the capabilities register. -If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 24 - 1 - read-write - - - TOUT_CNT - Data Timeout Counter Value. -This value determines the interval by which DAT line timeouts are detected. -The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. -When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). -The values for these bits are: -0xF : Reserved -0xE : TMCLK x 2^27 -......... -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 -Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. - 16 - 4 - read-write - - - FREQ_SEL - SDCLK/RCLK Frequency Select -These bits are used to select the frequency of the SDCLK signal. -These bits depend on setting of Preset Value Enable in the Host Control 2 register. -If Preset Value Enable = 0, these bits are set by the Host Driver. -If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. -The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. -10-bit Divided Clock Mode: -0x3FF : 1/2046 Divided clock -.......... -N : 1/2N Divided Clock -.......... -0x002 : 1/4 Divided Clock -0x001 : 1/2 Divided Clock -0x000 : Base clock (10MHz - 255 MHz) -Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: -0x3FF : Base clock * M /1024 -.......... -N-1 : Base clock * M /N -.......... -0x002 : Base clock * M /3 -0x001 : Base clock * M /2 -0x000 : Base clock * M - 8 - 8 - read-write - - - UPPER_FREQ_SEL - These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. -The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. - 6 - 2 - read-write - - - CLK_GEN_SELECT - Clock Generator Select -This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. -If Preset Value Enable = 0, this bit is set by the Host Driver. -If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. -The value is reflected on the card_clk_gen_sel signal. -Values: -0x0 (FALSE): Divided Clock Mode -0x1 (TRUE): Programmable Clock Mode - 5 - 1 - read-write - - - PLL_ENABLE - PLL Enable -This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). -When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. -Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): PLL is in low power mode -0x1 (TRUE): PLL is enabled - 3 - 1 - read-write - - - SD_CLK_EN - SD/eMMC Clock Enable -This bit stops the SDCLK or RCLK when set to 0. -The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. -The value is reflected on the clk2card_on pin. -Values: -0x0 (FALSE): Disable providing SDCLK/RCLK -0x1 (TRUE): Enable providing SDCLK/RCLK - 2 - 1 - read-write - - - INTERNAL_CLK_STABLE - Internal Clock Stable -This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. -This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, -and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. -Values: -0x0 (FALSE): Not Ready -0x1 (TRUE): Ready - 1 - 1 - read-write - - - INTERNAL_CLK_EN - Internal Clock Enable -This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. -The Host Controller must stop its internal clock to enter a very low power state. -However, registers can still be read and written to. The value is reflected on the intclk_en signal. -Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): Stop -0x1 (TRUE): Oscillate - 0 - 1 - read-write - - - - - INT_STAT - No description avaiable - 0x30 - 32 - 0x00000000 - 0x1FFFF1FF - - - BOOT_ACK_ERR - Boot Acknowledgement Error -This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. -In SD/UHS-II mode, this bit is irrelevant. - 28 - 1 - read-write - - - RESP_ERR - Response Error -Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 27 - 1 - read-write - - - TUNING_ERR - Tuning Error -This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure -(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). -By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. -To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. -The Tuning Error is higher priority than the other error interrupts generated during data transfer. -By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. -This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 26 - 1 - read-write - - - ADMA_ERR - ADMA Error -This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: -Error response received from System bus (Master I/F) -ADMA3,ADMA2 Descriptors invalid -CQE Task or Transfer descriptors invalid -When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. -In eMMC CQE mode: -The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. -ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. -The Host Driver may find that Valid bit is not set at the error descriptor. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 25 - 1 - read-write - - - AUTO_CMD_ERR - Auto CMD Error -This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. -This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. -D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 24 - 1 - read-write - - - CUR_LMT_ERR - Current Limit Error -By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. -If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. -A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. -A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. -The Host Controller may require some sampling time to detect the current limit. -SDXC Host Controller does not support this function, this bit is always set to 0. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Power Fail - 23 - 1 - read-write - - - DATA_END_BIT_ERR - Data End Bit Error -This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 22 - 1 - read-write - - - DATA_CRC_ERR - Data CRC Error -This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, -when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 21 - 1 - read-write - - - DATA_TOUT_ERR - Data Timeout Error -This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: -Busy timeout for R1b, R5b type -Busy timeout after Write CRC status -Write CRC Status timeout -Read Data timeout -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 20 - 1 - read-write - - - CMD_IDX_ERR - Command Index Error -This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR - Command End Bit Error -This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): End Bit error generated - 18 - 1 - read-write - - - CMD_CRC_ERR - Command CRC Error -Command CRC Error is generated in SD/eMMC mode for following two cases. -If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. -The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. -If the Host Controller drives the CMD line to 1 level, -but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. -The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. -Values: -0x0 (FALSE): No error -0x1 (TRUE): CRC error generated - 17 - 1 - read-write - - - CMD_TOUT_ERR - Command Timeout Error -In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. -If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 16 - 1 - read-write - - - ERR_INTERRUPT - Error Interrupt -If any of the bits in the Error Interrupt Status register are set, then this bit is set. -Values: -0x0 (FALSE): No Error -0x1 (TRUE): Error - 15 - 1 - read-only - - - CQE_EVENT - Command Queuing Event -This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): Command Queuing Event is detected - 14 - 1 - read-write - - - FX_EVENT - FX Event -This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): FX Event is detected - 13 - 1 - read-only - - - RE_TUNE_EVENT - Re-tuning Event -This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. - 12 - 1 - read-only - - - CARD_INTERRUPT - Card Interrupt -This bit reflects the synchronized value of: -DAT[1] Interrupt Input for SD Mode -DAT[2] Interrupt Input for UHS-II Mode -Values: -0x0 (FALSE): No Card Interrupt -0x1 (TRUE): Generate Card Interrupt - 8 - 1 - read-only - - - CARD_REMOVAL - Card Removal -This bit is set if the Card Inserted in the Present State register changes from 1 to 0. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Removed - 7 - 1 - read-write - - - CARD_INSERTION - Card Insertion -This bit is set if the Card Inserted in the Present State register changes from 0 to 1. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Inserted - 6 - 1 - read-write - - - BUF_RD_READY - Buffer Read Ready -This bit is set if the Buffer Read Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to read buffer -0x1 (TRUE): Ready to read buffer - 5 - 1 - read-write - - - BUF_WR_READY - Buffer Write Ready -This bit is set if the Buffer Write Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to write buffer -0x1 (TRUE): Ready to write buffer - 4 - 1 - read-write - - - DMA_INTERRUPT - DMA Interrupt -This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. -In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. -This interrupt is not generated after a Transfer Complete. -Values: -0x0 (FALSE): No DMA Interrupt -0x1 (TRUE): DMA Interrupt is generated - 3 - 1 - read-write - - - BGAP_EVENT - Block Gap Event -This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. -Values: -0x0 (FALSE): No Block Gap Event -0x1 (TRUE): Transaction stopped at block gap - 2 - 1 - read-write - - - XFER_COMPLETE - Transfer Complete -This bit is set when a read/write transfer and a command with status busy is completed. -Values: -0x0 (FALSE): Not complete -0x1 (TRUE): Command execution is completed - 1 - 1 - read-write - - - CMD_COMPLETE - Command Complete -In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. -This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. -Values: -0x0 (FALSE): No command complete -0x1 (TRUE): Command Complete - 0 - 1 - read-write - - - - - INT_STAT_EN - No description avaiable - 0x34 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_STAT_EN - Boot Acknowledgment Error (eMMC Mode only) -Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (ERROR_INT_STAT_R). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_STAT_EN - Response Error Status Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_STAT_EN - Tuning Error Status Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_STAT_EN - ADMA Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_STAT_EN - Auto CMD Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_STAT_EN - Current Limit Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_STAT_EN - Data End Bit Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_STAT_EN - Data CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_STAT_EN - Data Timeout Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_STAT_EN - Command Index Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 19 - 1 - read-write - - - CMD_END_BIT_ERR_STAT_EN - Command End Bit Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_STAT_EN - Command CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_STAT_EN - Command Timeout Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_STAT_EN - CQE Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_STAT_EN - FX Event Status Enable -This bit is added from Version 4.10. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_STAT_EN - Re-Tuning Event (UHS-I only) Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_STAT_EN - Card Interrupt Status Enable -If this bit is set to 0, the Host Controller clears the interrupt request to the System. -The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. -The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. -By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_STAT_EN - Card Removal Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_STAT_EN - Card Insertion Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_STAT_EN - Buffer Read Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_STAT_EN - Buffer Write Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_STAT_EN - DMA Interrupt Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_STAT_EN - Block Gap Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_STAT_EN - Transfer Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_STAT_EN - Command Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - INT_SIGNAL_EN - No description avaiable - 0x38 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_SIGNAL_EN - Boot Acknowledgment Error (eMMC Mode only). -Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgement Error in Error Interrupt Status register is set. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_SIGNAL_EN - Response Error Signal Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_SIGNAL_EN - Tuning Error Signal Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_SIGNAL_EN - ADMA Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_SIGNAL_EN - Auto CMD Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_SIGNAL_EN - Current Limit Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_SIGNAL_EN - Data End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_SIGNAL_EN - Data CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_SIGNAL_EN - Data Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_SIGNAL_EN - Command Index Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR_SIGNAL_EN - Command End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_SIGNAL_EN - Command CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_SIGNAL_EN - Command Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_SIGNAL_EN - Command Queuing Engine Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_SIGNAL_EN - FX Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_SIGNAL_EN - Re-Tuning Event (UHS-I only) Signal Enable. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_SIGNAL_EN - Card Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_SIGNAL_EN - Card Removal Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_SIGNAL_EN - Card Insertion Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_SIGNAL_EN - Buffer Read Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_SIGNAL_EN - Buffer Write Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_SIGNAL_EN - DMA Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_SIGNAL_EN - Block Gap Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_SIGNAL_EN - Transfer Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_SIGNAL_EN - Command Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - AC_HOST_CTRL - No description avaiable - 0x3c - 32 - 0x00000000 - 0xDCCF00BF - - - PRESET_VAL_ENABLE - Preset Value Enable -This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. -When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. -These values are selected from set of Preset Value registers based on selected speed mode. -Values: -0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver -0x1 (TRUE): Automatic Selection by Preset Value are Enabled - 31 - 1 - read-write - - - ASYNC_INT_ENABLE - Asynchronous Interrupt Enable -This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. -Values: -0x0 (FALSE): Disabled -0x1 (TRUE): Enabled - 30 - 1 - read-write - - - HOST_VER4_ENABLE - Host Version 4 Enable -This bit selects either Version 3.00 compatible mode or Version 4 mode. -Functions of following fields are modified for Host Version 4 mode: -SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) -ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register -64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 -Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register -32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register -Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, -UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). -Values: -0x0 (FALSE): Version 3.00 compatible mode -0x1 (TRUE): Version 4 mode - 28 - 1 - read-write - - - CMD23_ENABLE - CMD23 Enable -If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. -Values: -0x0 (FALSE): Auto CMD23 is disabled -0x1 (TRUE): Auto CMD23 is enabled - 27 - 1 - read-write - - - ADMA2_LEN_MODE - ADMA2 Length Mode -This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. -Values: -0x0 (FALSE): 16-bit Data Length Mode -0x1 (TRUE): 26-bit Data Length Mode - 26 - 1 - read-write - - - SAMPLE_CLK_SEL - Sampling Clock Select -This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. -This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). -Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. -The value is reflected on the sample_cclk_sel pin. -Values: -0x0 (FALSE): Fixed clock is used to sample data -0x1 (TRUE): Tuned clock is used to sample data - 23 - 1 - read-write - - - EXEC_TUNING - Execute Tuning -This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. -Values: -0x0 (FALSE): Not Tuned or Tuning completed -0x1 (TRUE): Execute Tuning - 22 - 1 - read-write - - - SIGNALING_EN - 1.8V Signaling Enable -This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. -Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. -Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. -Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). -Values: -0x0 (V_3_3): 3.3V Signalling -0x1 (V_1_8): 1.8V Signalling - 19 - 1 - read-write - - - UHS_MODE_SEL - UHS Mode/eMMC Speed Mode Select -These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. -UHS Mode (SD/UHS-II mode only): -0x0 (SDR12): SDR12/Legacy -0x1 (SDR25): SDR25/High Speed SDR -0x2 (SDR50): SDR50 -0x3 (SDR104): SDR104/HS200 -0x4 (DDR50): DDR50/High Speed DDR -0x5 (RSVD5): Reserved -0x6 (RSVD6): Reserved -0x7 (UHS2): UHS-II/HS400 -eMMC Speed Mode (eMMC mode only): -0x0: Legacy -0x1: High Speed SDR -0x2: Reserved -0x3: HS200 -0x4: High Speed DDR -0x5: Reserved -0x6: Reserved -0x7: HS400 - 16 - 3 - read-write - - - CMD_NOT_ISSUED_AUTO_CMD12 - Command Not Issued By Auto CMD12 Error -If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Issued -0x0 (FALSE): No Error - 7 - 1 - read-only - - - AUTO_CMD_RESP_ERR - Auto CMD Response Error -This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. -This status is ignored if any bit between D00 to D04 is set to 1. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 5 - 1 - read-only - - - AUTO_CMD_IDX_ERR - Auto CMD Index Error -This bit is set if the command index error occurs in response to a command. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 4 - 1 - read-only - - - AUTO_CMD_EBIT_ERR - Auto CMD End Bit Error -This bit is set when detecting that the end bit of command response is 0. -Values: -0x1 (TRUE): End Bit Error Generated -0x0 (FALSE): No Error - 3 - 1 - read-only - - - AUTO_CMD_CRC_ERR - Auto CMD CRC Error -This bit is set when detecting a CRC error in the command response. -Values: -0x1 (TRUE): CRC Error Generated -0x0 (FALSE): No Error - 2 - 1 - read-only - - - AUTO_CMD_TOUT_ERR - Auto CMD Timeout Error -This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. -If this bit is set to 1, error status bits (D04-D01) are meaningless. -Values: -0x1 (TRUE): Time out -0x0 (FALSE): No Error - 1 - 1 - read-only - - - AUTO_CMD12_NOT_EXEC - Auto CMD12 Not Executed -If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. -Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. - If this bit is set to 1, error status bits (D04-D01) is meaningless. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Executed -0x0 (FALSE): Executed - 0 - 1 - read-only - - - - - CAPABILITIES1 - No description avaiable - 0x40 - 32 - 0x00000000 - 0xE7EFFFBF - - - SLOT_TYPE_R - Slot Type -These bits indicate usage of a slot by a specific Host System. -Values: -0x0 (REMOVABLE_SLOT): Removable Card Slot -0x1 (EMBEDDED_SLOT): Embedded Slot for one Device -0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) -0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices - 30 - 2 - read-only - - - ASYNC_INT_SUPPORT - Asynchronous Interrupt Support (SD Mode only) -Values: -0x0 (FALSE): Asynchronous Interrupt Not Supported -0x1 (TRUE): Asynchronous Interrupt Supported - 29 - 1 - read-only - - - VOLT_18 - Voltage Support for 1.8V -Values: -0x0 (FALSE): 1.8V Not Supported -0x1 (TRUE): 1.8V Supported - 26 - 1 - read-only - - - VOLT_30 - Voltage Support for SD 3.0V or Embedded 1.2V -Values: -0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported -0x1 (TRUE): SD 3.0V or Embedded Supported - 25 - 1 - read-only - - - VOLT_33 - Voltage Support for 3.3V -Values: -0x0 (FALSE): 3.3V Not Supported -0x1 (TRUE): 3.3V Supported - 24 - 1 - read-only - - - SUS_RES_SUPPORT - Suspense/Resume Support -This bit indicates whether the Host Controller supports Suspend/Resume functionality. -If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. -Values: -0x0 (FALSE): Not Supported -0x1 (TRUE): Supported - 23 - 1 - read-only - - - SDMA_SUPPORT - SDMA Support -This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. -Values: -0x0 (FALSE): SDMA not Supported -0x1 (TRUE): SDMA Supported - 22 - 1 - read-only - - - HIGH_SPEED_SUPPORT - High Speed Support -This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. -Values: -0x0 (FALSE): High Speed not Supported -0x1 (TRUE): High Speed Supported - 21 - 1 - read-only - - - ADMA2_SUPPORT - ADMA2 Support -This bit indicates whether the Host Controller is capable of using ADMA2. -Values: -0x0 (FALSE): ADMA2 not Supported -0x1 (TRUE): ADMA2 Supported - 19 - 1 - read-only - - - EMBEDDED_8_BIT - 8-bit Support for Embedded Device -This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. -Values: -0x0 (FALSE): 8-bit Bus Width not Supported -0x1 (TRUE): 8-bit Bus Width Supported - 18 - 1 - read-only - - - MAX_BLK_LEN - Maximum Block Length -This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. -The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit -Values: -0x0 (ZERO): 512 Byte -0x1 (ONE): 1024 Byte -0x2 (TWO): 2048 Byte -0x3 (THREE): Reserved - 16 - 2 - read-only - - - BASE_CLK_FREQ - Base Clock Frequency for SD clock -These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. -6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. -The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............. --0x3F : 63 MHz --0x40-0xFF : Not Supported -8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............ --0xFF : 255 MHz -If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. -If these bits are all 0, the Host system has to get information using a different method. - 8 - 8 - read-only - - - TOUT_CLK_UNIT - Timeout Clock Unit -This bit shows the unit of base clock frequency used to detect Data TImeout Error. -Values: -0x0 (KHZ): KHz -0x1 (MHZ): MHz - 7 - 1 - read-only - - - TOUT_CLK_FREQ - Timeout Clock Frequency -This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. -0x00 : Get information through another method -0x01 : 1KHz / 1MHz -0x02 : 2KHz / 2MHz -0x03 : 3KHz / 3MHz - ........... -0x3F : 63KHz / 63MHz - 0 - 6 - read-only - - - - - CAPABILITIES2 - No description avaiable - 0x44 - 32 - 0x00000000 - 0x18FFEF7F - - - VDD2_18V_SUPPORT - 1.8V VDD2 Support -This bit indicates support of VDD2 for the Host System. -0x0 (FALSE): 1.8V VDD2 is not Supported -0x1 (TRUE): 1.8V VDD2 is Supported - 28 - 1 - read-only - - - ADMA3_SUPPORT - ADMA3 Support -This bit indicates whether the Host Controller is capable of using ADMA3. -Values: -0x0 (FALSE): ADMA3 not Supported -0x1 (TRUE): ADMA3 Supported - 27 - 1 - read-only - - - CLK_MUL - Clock Multiplier -These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. -0x0: Clock Multiplier is not Supported -0x1: Clock Multiplier M = 2 -0x2: Clock Multiplier M = 3 - ......... -0xFF: Clock Multiplier M = 256 - 16 - 8 - read-only - - - RE_TUNING_MODES - Re-Tuning Modes (UHS-I only) -These bits select the re-tuning method and limit the maximum data length. -Values: -0x0 (MODE1): Timer -0x1 (MODE2): Timer and Re-Tuning Request (Not supported) -0x2 (MODE3): Auto Re-Tuning (for transfer) -0x3 (RSVD_MODE): Reserved - 14 - 2 - read-only - - - USE_TUNING_SDR50 - Use Tuning for SDR50 (UHS-I only) -Values: -0x0 (ZERO): SDR50 does not require tuning -0x1 (ONE): SDR50 requires tuning - 13 - 1 - read-only - - - RETUNE_CNT - Timer Count for Re-Tuning (UHS-I only) -0x0: Re-Tuning Timer disabled -0x1: 1 seconds -0x2: 2 seconds -0x3: 4 seconds - ........ -0xB: 1024 seconds -0xC: Reserved -0xD: Reserved -0xE: Reserved -0xF: Get information from other source - 8 - 4 - read-only - - - DRV_TYPED - Driver Type D Support (UHS-I only) -This bit indicates support of Driver Type D for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type D is not supported -0x1 (TRUE): Driver Type D is supported - 6 - 1 - read-only - - - DRV_TYPEC - Driver Type C Support (UHS-I only) -This bit indicates support of Driver Type C for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type C is not supported -0x1 (TRUE): Driver Type C is supported - 5 - 1 - read-only - - - DRV_TYPEA - Driver Type A Support (UHS-I only) -This bit indicates support of Driver Type A for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type A is not supported -0x1 (TRUE): Driver Type A is supported - 4 - 1 - read-only - - - UHS2_SUPPORT - UHS-II Support (UHS-II only) -This bit indicates whether Host Controller supports UHS-II. -Values: -0x0 (FALSE): UHS-II is not supported -0x1 (TRUE): UHS-II is supported - 3 - 1 - read-only - - - DDR50_SUPPORT - DDR50 Support (UHS-I only) -Values: -0x0 (FALSE): DDR50 is not supported -0x1 (TRUE): DDR50 is supported - 2 - 1 - read-only - - - SDR104_SUPPORT - SDR104 Support (UHS-I only) -This bit mentions that SDR104 requires tuning. -Values: -0x0 (FALSE): SDR104 is not supported -0x1 (TRUE): SDR104 is supported - 1 - 1 - read-only - - - SDR50_SUPPORT - SDR50 Support (UHS-I only) -This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. -Values: -0x0 (FALSE): SDR50 is not supported -0x1 (TRUE): SDR50 is supported - 0 - 1 - read-only - - - - - CURR_CAPABILITIES1 - No description avaiable - 0x48 - 32 - 0x00000000 - 0x00FFFFFF - - - MAX_CUR_18V - Maximum Current for 1.8V -This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 16 - 8 - read-only - - - MAX_CUR_30V - Maximum Current for 3.0V -This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 8 - 8 - read-only - - - MAX_CUR_33V - Maximum Current for 3.3V -This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - CURR_CAPABILITIES2 - No description avaiable - 0x4c - 32 - 0x00000000 - 0x000000FF - - - MAX_CUR_VDD2_18V - Maximum Current for 1.8V VDD2 -This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - FORCE_EVENT - No description avaiable - 0x50 - 32 - 0x00000000 - 0x1FFF00BF - - - FORCE_BOOT_ACK_ERR - Force Event for Boot Ack error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Boot ack Error Status is set - 28 - 1 - write-only - - - FORCE_RESP_ERR - Force Event for Response Error (SD Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Response Error Status is set - 27 - 1 - write-only - - - FORCE_TUNING_ERR - Force Event for Tuning Error (UHS-I Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Tuning Error Status is set - 26 - 1 - write-only - - - FORCE_ADMA_ERR - Force Event for ADMA Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): ADMA Error Status is set - 25 - 1 - write-only - - - FORCE_AUTO_CMD_ERR - Force Event for Auto CMD Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Auto CMD Error Status is set - 24 - 1 - write-only - - - FORCE_CUR_LMT_ERR - Force Event for Current Limit Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Current Limit Error Status is set - 23 - 1 - write-only - - - FORCE_DATA_END_BIT_ERR - Force Event for Data End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data End Bit Error Status is set - 22 - 1 - write-only - - - FORCE_DATA_CRC_ERR - Force Event for Data CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data CRC Error Status is set - 21 - 1 - write-only - - - FORCE_DATA_TOUT_ERR - Force Event for Data Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data Timeout Error Status is set - 20 - 1 - write-only - - - FORCE_CMD_IDX_ERR - Force Event for Command Index Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Index Error Status is set - 19 - 1 - write-only - - - FORCE_CMD_END_BIT_ERR - Force Event for Command End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command End Bit Error Status is set - 18 - 1 - write-only - - - FORCE_CMD_CRC_ERR - Force Event for Command CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command CRC Error Status is set - 17 - 1 - write-only - - - FORCE_CMD_TOUT_ERR - Force Event for Command Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Timeout Error Status is set - 16 - 1 - write-only - - - FORCE_CMD_NOT_ISSUED_AUTO_CMD12 - Force Event for Command Not Issued By Auto CMD12 Error -Values: -0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set -0x0 (FALSE): Not Affected - 7 - 1 - write-only - - - FORCE_AUTO_CMD_RESP_ERR - Force Event for Auto CMD Response Error -Values: -0x1 (TRUE): Auto CMD Response Error Status is set -0x0 (FALSE): Not Affected - 5 - 1 - write-only - - - FORCE_AUTO_CMD_IDX_ERR - Force Event for Auto CMD Index Error -Values: -0x1 (TRUE): Auto CMD Index Error Status is set -0x0 (FALSE): Not Affected - 4 - 1 - write-only - - - FORCE_AUTO_CMD_EBIT_ERR - Force Event for Auto CMD End Bit Error -Values: -0x1 (TRUE): Auto CMD End Bit Error Status is set -0x0 (FALSE): Not Affected - 3 - 1 - write-only - - - FORCE_AUTO_CMD_CRC_ERR - Force Event for Auto CMD CRC Error -Values: -0x1 (TRUE): Auto CMD CRC Error Status is set -0x0 (FALSE): Not Affected - 2 - 1 - write-only - - - FORCE_AUTO_CMD_TOUT_ERR - Force Event for Auto CMD Timeout Error -Values: -0x1 (TRUE): Auto CMD Timeout Error Status is set -0x0 (FALSE): Not Affected - 1 - 1 - write-only - - - FORCE_AUTO_CMD12_NOT_EXEC - Force Event for Auto CMD12 Not Executed -Values: -0x1 (TRUE): Auto CMD12 Not Executed Status is set -0x0 (FALSE): Not Affected - 0 - 1 - write-only - - - - - ADMA_ERR_STAT - No description avaiable - 0x54 - 32 - 0x00000000 - 0x00000007 - - - ADMA_LEN_ERR - ADMA Length Mismatch Error States -This error occurs in the following instances: -While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length -When the total data length cannot be divided by the block length -Values: -0x0 (NO_ERR): No Error -0x1 (ERROR): Error - 2 - 1 - read-only - - - ADMA_ERR_STATES - ADMA Error States -These bits indicate the state of ADMA when an error occurs during ADMA data transfer. -Values: -0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor -0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor -0x2 (UNUSED): Never set this state -0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor - 0 - 2 - read-only - - - - - ADMA_SYS_ADDR - No description avaiable - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_SA - ADMA System Address -These bits indicate the lower 32 bits of the ADMA system address. -SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location -ADMA2: This register stores the byte address of the executing command of the descriptor table -ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. - 0 - 32 - read-write - - - - - PRESET_INIT - No description avaiable - 0x60 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_DS - No description avaiable - 0x62 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_HS - No description avaiable - 0x64 - 16 - 0x0001 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_SDR12 - No description avaiable - 0x66 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_SDR25 - No description avaiable - 0x68 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_SDR50 - No description avaiable - 0x6a - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_SDR104 - No description avaiable - 0x6c - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_DDR50 - No description avaiable - 0x6e - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - PRESET_UHS2 - No description avaiable - 0x74 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - ADMA_ID_ADDR - No description avaiable - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_ID_ADDR - ADMA Integrated Descriptor Address -These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. -The start address of Integrated Descriptor is set to these register bits. -The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. - 0 - 32 - read-write - - - - - P_EMBEDDED_CNTRL - No description avaiable - 0xe6 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Offset Address of Embedded Control register. - 0 - 12 - read-only - - - - - P_VENDOR_SPECIFIC_AREA - No description avaiable - 0xe8 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Base offset Address for Vendor-Specific registers. - 0 - 12 - read-only - - - - - P_VENDOR2_SPECIFIC_AREA - No description avaiable - 0xea - 16 - 0x0000 - 0xFFFF - - - REG_OFFSET_ADDR - Base offset Address for Command Queuing registers. - 0 - 16 - read-only - - - - - SLOT_INTR_STATUS - No description avaiable - 0xfc - 16 - 0x0000 - 0x00FF - - - INTR_SLOT - Interrupt signal for each Slot -These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. -A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. - By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. -Bit 00: Slot 1 -Bit 01: Slot 2 -Bit 02: Slot 3 -.......... -.......... -Bit 07: Slot 8 -Note: MSHC Host Controller support single card slot. This register shall always return 0. - 0 - 8 - read-only - - - - - CQVER - No description avaiable - 0x180 - 32 - 0x00000000 - 0x00000FFF - - - EMMC_VER_MAHOR - This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. - 8 - 4 - read-only - - - EMMC_VER_MINOR - This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. - 4 - 4 - read-only - - - EMMC_VER_SUFFIX - This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. - 0 - 4 - read-only - - - - - CQCAP - No description avaiable - 0x184 - 32 - 0x00000000 - 0x1000F3FF - - - CRYPTO_SUPPORT - Crypto Support -This bit indicates whether the Host Controller supports cryptographic operations. -Values: -0x0 (FALSE): Crypto not Supported -0x1 (TRUE): Crypto Supported - 28 - 1 - read-only - - - ITCFMUL - Internal Timer Clock Frequency Multiplier (ITCFMUL) -This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS -polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. -Values: -0x0 (CLK_1KHz): 1KHz clock -0x1 (CLK_10KHz): 10KHz clock -0x2 (CLK_100KHz): 100KHz clock -0x3 (CLK_1MHz): 1MHz clock -0x4 (CLK_10MHz): 10MHz clock - 12 - 4 - read-only - - - ITCFVAL - Internal Timer Clock Frequency Value (ITCFVAL) -This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. - 0 - 10 - read-only - - - - - CQCFG - No description avaiable - 0x188 - 32 - 0x00000000 - 0x00001101 - - - DCMD_EN - This bit indicates to the hardware whether the Task -Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. -Values: -0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor -0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor - 12 - 1 - read-write - - - TASK_DESC_SIZE - Bit Value Description -This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). -Values: -0x1 (TASK_DESC_128b): Task descriptor size is 128 bits -0x0 (TASK_DESC_64b): Task descriptor size is 64 bit - 8 - 1 - read-write - - - CQ_EN - No description avaiable - 0 - 1 - read-write - - - - - CQCTL - No description avaiable - 0x18c - 32 - 0x00000000 - 0x00000101 - - - CLR_ALL_TASKS - Clear all tasks -This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. -Values: -0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller -0x0 (NO_EFFECT): Programming 0 has no effect - 8 - 1 - read-write - - - HALT - Halt request and resume -Values: -0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. -For example, issuing a Discard Task command (CMDQ_TASK_MGMT). -When the software writes 1, CQE completes the ongoing task (if any in progress). -After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. -The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. -0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity - 0 - 1 - read-write - - - - - CQIS - No description avaiable - 0x190 - 32 - 0x00000000 - 0x0000000F - - - TCL - Task cleared interrupt -This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. -The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). -A value of 1 clears this status bit. -Values: -0x1 (SET): TCL Interrupt is set -0x0 (NOTSET): TCL Interrupt is not set - 3 - 1 - read-write - - - RED - Response error detected interrupt -This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status -field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. -A value of 1 clears this status bit. -Values: -0x1 (SET): RED Interrupt is set -0x0 (NOTSET): RED Interrupt is not set - 2 - 1 - read-write - - - TCC - Task complete interrupt -This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: -A task is completed and the INT bit is set in its Task Descriptor -Interrupt caused by Interrupt Coalescing logic due to timeout -Interrupt Coalescing logic reached the configured threshold -A value of 1 clears this status bit - 1 - 1 - read-write - - - HAC - Halt complete interrupt -This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. -A value of 1 clears this status bit. -Values: -0x1 (SET): HAC Interrupt is set -0x0 (NOTSET): HAC Interrupt is not set - 0 - 1 - read-write - - - - - CQISE - No description avaiable - 0x194 - 32 - 0x00000000 - 0x0000000F - - - TCL_STE - Task cleared interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCL is disabled - 3 - 1 - read-write - - - RED_STE - Response error detected interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.RED is disabled - 2 - 1 - read-write - - - TCC_STE - Task complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCC is disabled - 1 - 1 - read-write - - - HAC_STE - Halt complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.HAC is disabled - 0 - 1 - read-write - - - - - CQISGE - No description avaiable - 0x198 - 32 - 0x00000000 - 0x0000000F - - - TCL_SGE - Task cleared interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled - 3 - 1 - read-write - - - RED_SGE - Response error detected interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled - 2 - 1 - read-write - - - TCC_SGE - Task complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled - 1 - 1 - read-write - - - HAC_SGE - Halt complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled - 0 - 1 - read-write - - - - - CQIC - No description avaiable - 0x19c - 32 - 0x00000000 - 0x80119FFF - - - INTC_EN - Interrupt Coalescing Enable Bit -Values: -0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated -0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) - 31 - 1 - read-write - - - INTC_STAT - Interrupt Coalescing Status Bit -This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt -coalescing (that is, this is set if and only if INTC counter > 0). -Values: -0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) -0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) - 20 - 1 - read-only - - - INTC_RST - Counter and Timer Reset -When host driver writes 1, the interrupt coalescing timer and counter are reset. -Values: -0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset -0x0 (NO_EFFECT): No Effect - 16 - 1 - write-only - - - INTC_TH_WEN - Interrupt Coalescing Counter Threshold Write Enable -When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets INTC_TH_WEN -0x0 (WEN_CLR): Clears INTC_TH_WEN - 15 - 1 - write-only - - - INTC_TH - Interrupt Coalescing Counter Threshold filed -Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. -Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. -The counter is reset by software during the interrupt service routine. -The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. -0x0: Interrupt coalescing feature disabled -0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes -0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes -........ -0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes -To write to this field, the INTC_TH_WEN bit must be set during the same write operation. - 8 - 5 - write-only - - - TOUT_VAL_WEN - When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets TOUT_VAL_WEN -0x0 (WEN_CLR): clears TOUT_VAL_WEN - 7 - 1 - write-only - - - TOUT_VAL - Interrupt Coalescing Timeout Value -Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. -Timer Operation: The timer is reset by software during the interrupt service routine. -It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. -When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. -The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -0x0: Timer is disabled. Timeout-based interrupt is not generated -0x1: Timeout on 01x1024 cycles of timer clock frequency -0x2: Timeout on 02x1024 cycles of timer clock frequency -........ -0x7f: Timeout on 127x1024 cycles of timer clock frequency -In order to write to this field, the TOUT_VAL_WEN bit must -be set at the same write operation. - 0 - 7 - read-write - - - - - CQTDLBA - No description avaiable - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDLBA - This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. -The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. -This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE - 0 - 32 - read-write - - - - - CQTDBR - No description avaiable - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DBR - The software configures TDLBA and TDLBAU, and enable -CQE in CQCFG before using this register. -Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. -Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. -CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. -CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to -the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. -The corresponding bit is cleared to 0 by CQE in one of the following events: -A task execution is completed (with success or error). -The task is cleared using CQTCLR register. -All tasks are cleared using CQCTL register. -CQE is disabled using CQCFG register. -Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. -In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. -If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. - 0 - 32 - read-write - - - - - CQTCN - No description avaiable - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - TCN - Task Completion Notification -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has completed execution (with success or errors) -Bit-N(0): Task-N has not completed, could be pending or not submitted. -On task completion, software may read this register to know tasks that have completed. After reading this register, -software may clear the relevant bit fields by writing 1 to the corresponding bits. - 0 - 32 - read-write - - - - - CQDQS - No description avaiable - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DQS - Device Queue Status -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Device has marked task N as ready for execution -Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. -Host controller updates this register with response of the Device Queue Status command. - 0 - 32 - read-write - - - - - CQDPT - No description avaiable - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DPT - Device-Pending Tasks -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution -Bit-N(0): Task-N is not yet queued. -Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. -The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. -Software reads this register in the task-discard procedure to determine if the task is queued in the device - 0 - 32 - read-write - - - - - CQTCLR - No description avaiable - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TCLR - Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. -This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. -When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. -CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. -Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. - 0 - 32 - read-write - - - - - CQSSC1 - No description avaiable - 0x1c0 - 32 - 0x00000000 - 0x000FFFFF - - - SQSCMD_BLK_CNT - This field indicates when SQS CMD is sent while data transfer is in progress. -A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. -0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. -0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. -0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. -0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. -........ -0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. -Should be programmed only when CQCFG.CQ_EN is 0 - 16 - 4 - read-write - - - SQSCMD_IDLE_TMR - This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. -Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. -When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. -Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). -For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). -If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. -Should be programmed only when CQCFG.CQ_EN is '0' - 0 - 16 - read-write - - - - - CQSSC2 - No description avaiable - 0x1c4 - 32 - 0x00000000 - 0x0000FFFF - - - SQSCMD_RCA - This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. -CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. - 0 - 16 - read-write - - - - - CQCRDCT - No description avaiable - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DCMD_RESP - This register contains the response of the command generated by the last direct command (DCMD) task that was sent. -Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. - 0 - 32 - read-only - - - - - CQRMEM - No description avaiable - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP_ERR_MASK - The bits of this field are bit mapped to the device response. -This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. -1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. -0: When a R1/R1b response is received, bit i in the device status is ignored. -The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. -Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. - 0 - 32 - read-write - - - - - CQTERRI - No description avaiable - 0x1d4 - 32 - 0x00000000 - 0x1F3F9F3F - - - TRANS_ERR_TASKID - This field captures the ID of the task that was executed and whose data transfer has errors. - 24 - 5 - read-only - - - TRANS_ERR_CMD_INDX - This field captures the index of the command that was executed and whose data transfer has errors. - 16 - 6 - read-only - - - RESP_ERR_FIELDS_VALID - This bit is updated when an error is detected while a command transaction was in progress. -Values: -0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields -0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX - 15 - 1 - read-only - - - RESP_ERR_TASKID - This field captures the ID of the task which was executed on the command line when the error occurred. - 8 - 5 - read-only - - - RESP_ERR_CMD_INDX - This field captures the index of the command that was executed on the command line when the error occurred - 0 - 6 - read-only - - - - - CQCRI - No description avaiable - 0x1d8 - 32 - 0x00000000 - 0x0000003F - - - CMD_RESP_INDX - Last Command Response index -This field stores the index of the last received command response. Controller updates the value every time a command response is received - 0 - 6 - read-only - - - - - CQCRA - No description avaiable - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_RESP_ARG - Last Command Response argument -This field stores the argument of the last received command response. Controller updates the value every time a command response is received. - 0 - 32 - read-only - - - - - MSHC_VER_ID - No description avaiable - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_ID - No description avaiable - 0 - 32 - read-only - - - - - MSHC_VER_TYPE - No description avaiable - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_TYPE - No description avaiable - 0 - 32 - read-only - - - - - MSHC_CTRL - No description avaiable - 0x508 - 32 - 0x00000000 - 0x00000001 - - - CMD_CONFLICT_CHECK - No description avaiable - 0 - 1 - read-write - - - - - MBIU_CTRL - Y - 0x510 - 32 - 0x00000000 - 0x0000000F - - - BURST_INCR16_EN - No description avaiable - 3 - 1 - read-write - - - BURST_INCR8_EN - No description avaiable - 2 - 1 - read-write - - - BUSRT_INCR4_EN - No description avaiable - 1 - 1 - read-write - - - UNDEFL_INCR_EN - No description avaiable - 0 - 1 - read-write - - - - - EMMC_BOOT_CTRL - No description avaiable - 0x52c - 32 - 0x00000000 - 0xF181070F - - - BOOT_TOUT_CNT - Boot Ack Timeout Counter Value. -This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. -0xF : Reserved -0xE : TMCLK x 2^27 - ............ -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 - 28 - 4 - read-write - - - BOOT_ACK_ENABLE - Boot Acknowledge Enable -When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. -Values: -0x1 (TRUE): Boot Ack enable -0x0 (FALSE): Boot Ack disable - 24 - 1 - read-write - - - VALIDATE_BOOT - Validate Mandatory Boot Enable bit -This bit is used to validate the MAN_BOOT_EN bit. -Values: -0x1 (TRUE): Validate Mandatory boot enable bit -0x0 (FALSE): Ignore Mandatory boot Enable bit - 23 - 1 - write-only - - - MAN_BOOT_EN - Mandatory Boot Enable -This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. -Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. -Values: -0x1 (MAN_BOOT_EN): Mandatory boot enable -0x0 (MAN_BOOT_DIS): Mandatory boot disable - 16 - 1 - read-write - - - CQE_PREFETCH_DISABLE - Enable or Disable CQE's PREFETCH feature -This field allows Software to disable CQE's data prefetch feature when set to 1. -Values: -0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers -0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled - 10 - 1 - read-write - - - CQE_ALGO_SEL - Scheduler algorithm selected for execution -This bit selects the Algorithm used for selecting one of the many ready tasks for execution. -Values: -0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks -0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings - 9 - 1 - read-write - - - ENH_STROBE_ENABLE - Enhanced Strobe Enable -This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. -Values: -0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode -0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode - 8 - 1 - read-write - - - EMMC_RST_N_OE - Output Enable control for EMMC Device Reset signal PAD -control. -This field drived sd_rst_n_oe output of SDXC -Values: -0x1 (ENABLE): sd_rst_n_oe is 1 -0x0 (DISABLE): sd_rst_n_oe is 0 - 3 - 1 - read-write - - - EMMC_RST_N - EMMC Device Reset signal control. -This register field controls the sd_rst_n output of SDXC -Values: -0x1 (RST_DEASSERT): Reset to eMMC device is deasserted -0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) - 2 - 1 - read-write - - - DISABLE_DATA_CRC_CHK - Disable Data CRC Check -This bit controls masking of CRC16 error for Card Write in eMMC mode. -This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, -which may generate CRC error. This CRC error can be masked using this bit during bus testing. -Values: -0x1 (DISABLE): DATA CRC check is disabled -0x0 (ENABLE): DATA CRC check is enabled - 1 - 1 - read-write - - - CARD_IS_EMMC - eMMC Card present -This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. -Values: -0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card -0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card - 0 - 1 - read-write - - - - - AUTO_TUNING_CTRL - No description avaiable - 0x540 - 32 - 0x00000000 - 0x7F1F0F1F - - - SWIN_TH_VAL - Sampling window threshold value setting -The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps -can use values from 0x0 to 0x1F. -This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' -0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. -0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. -0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. -........ -0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. - 24 - 7 - read-write - - - POST_CHANGE_DLY - Time taken for phase switching and stable clock output. -Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 19 - 2 - read-write - - - PRE_CHANGE_DLY - Maximum Latency specification between cclk_tx and cclk_rx. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 17 - 2 - read-write - - - TUNE_CLK_STOP_EN - Clock stopping control for Tuning and auto-tuning circuit. -When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. -This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. - Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. -Values: -0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change -0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching - 16 - 1 - read-write - - - WIN_EDGE_SEL - This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. -0x0: User selection disabled. Tuning calculated edges are used. -0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. -0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess -... -0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. - 8 - 4 - read-write - - - SW_TUNE_EN - This fields enables software-managed tuning flow. -Values: -0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AT_STAT_R.CENTER_PH_CODE Field is now writable. -0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled - 4 - 1 - read-write - - - RPT_TUNE_ERR - Framing errors are not generated when executing tuning. -This debug bit allows users to report these errors. -Values: -0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors -0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. - 3 - 1 - read-write - - - SWIN_TH_EN - Sampling window Threshold enable -Selects the tuning mode -Field should be programmed only when SAMPLE_CLK_SEL is '0' -Values: -0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold -set by SWIN_TH_VAL field -0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window - 2 - 1 - read-write - - - CI_SEL - Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. -Values: -0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval -0x1 (WHEN_IN_IDLE): Driven at the end of the transfer - 1 - 1 - read-write - - - AT_EN - Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. -Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. -This field should be programmed only when CLK_CTRL_R.SD_CLK_EN is 0. -Values: -0x1 (AT_ENABLE): AutoTuning is enabled -0x0 (AT_DISABLE): AutoTuning is disabled - 0 - 1 - read-write - - - - - AUTO_TUNING_STAT - No description avaiable - 0x544 - 32 - 0x00000000 - 0x00FFFFFF - - - L_EDGE_PH_CODE - Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. - 16 - 8 - read-only - - - R_EDGE_PH_CODE - Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. - 8 - 8 - read-only - - - CENTER_PH_CODE - Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AT_CTRL_R.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel - 0 - 8 - read-write - - - - - MISC_CTRL0 - No description avaiable - 0x3000 - 32 - 0x00000000 - 0xD0020FFF - - - IRQ_EN - No description avaiable - 30 - 2 - read-write - - - CARDCLK_INV_EN - No description avaiable - 28 - 1 - read-write - - - PAD_CLK_SEL_B - No description avaiable - 17 - 1 - read-write - - - FREQ_SEL_SW_EN - No description avaiable - 11 - 1 - read-write - - - TMCLK_EN - No description avaiable - 10 - 1 - read-write - - - FREQ_SEL_SW - No description avaiable - 0 - 10 - read-write - - - - - MISC_CTRL1 - No description avaiable - 0x3004 - 32 - 0x00000000 - 0xB3F3F8FF - - - CARD_ACTIVE - No description avaiable - 31 - 1 - read-write - - - CARD_ACTIVE_PERIOD_SEL - No description avaiable - 28 - 2 - read-write - - - TUNING_CARD_CLK_SEL - No description avaiable - 20 - 6 - read-write - - - TUNING_STROBE_SEL - No description avaiable - 12 - 6 - read-write - - - STROBE_IN_ENABLE - No description avaiable - 11 - 1 - read-write - - - AUTOTUNING_CCLK_SEL0 - No description avaiable - 7 - 1 - read-write - - - CCLK_RX_DLY_SW_FORCE - No description avaiable - 6 - 1 - read-write - - - CCLK_RX_DLY_SW_SEL - No description avaiable - 0 - 6 - read-write - - - - - - - I2C0 - I2C0 - I2C - 0xf3020000 - - 0x0 - 0x34 - registers - - - - CFG - Configuration Register - 0x10 - 32 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 2 - 30 - read-write - - - FIFOSIZE - FIFO Size: -0: 2 bytes -1: 4 bytes -2: 8 bytes -3: 16 bytes - 0 - 2 - read-only - - - - - INTEN - Interrupt Enable Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 10 - 22 - read-write - - - CMPL - Set to enable the Completion Interrupt. -Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. -Slave: interrupts when a transaction addressing the controller is completed. - 9 - 1 - read-write - - - BYTERECV - Set to enable the Byte Receive Interrupt. -Interrupts when a byte of data is received -Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - 8 - 1 - read-write - - - BYTETRANS - Set to enable the Byte Transmit Interrupt. -Interrupts when a byte of data is transmitted. - 7 - 1 - read-write - - - START - Set to enable the START Condition Interrupt. -Interrupts when a START condition/repeated START condition is detected. - 6 - 1 - read-write - - - STOP - Set to enable the STOP Condition Interrupt -Interrupts when a STOP condition is detected. - 5 - 1 - read-write - - - ARBLOSE - Set to enable the Arbitration Lose Interrupt. -Master: interrupts when the controller loses the bus arbitration -Slave: not available in this mode. - 4 - 1 - read-write - - - ADDRHIT - Set to enable the Address Hit Interrupt. -Master: interrupts when the addressed slave returned an ACK. -Slave: interrupts when the controller is addressed. - 3 - 1 - read-write - - - FIFOHALF - Set to enable the FIFO Half Interrupt. -Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. -Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. -This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - 2 - 1 - read-write - - - FIFOFULL - Set to enable the FIFO Full Interrupt. -Interrupts when the FIFO is full. - 1 - 1 - read-write - - - FIFOEMPTY - Set to enabled the FIFO Empty Interrupt -Interrupts when the FIFO is empty. - 0 - 1 - read-write - - - - - STATUS - Status Register - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 15 - 17 - read-write - - - LINESDA - Indicates the current status of the SDA line on the bus -1: high -0: low - 14 - 1 - read-only - - - LINESCL - Indicates the current status of the SCL line on the bus -1: high -0: low - 13 - 1 - read-only - - - GENCALL - Indicates that the address of the current transaction is a general call address: -1: General call -0: Not general call - 12 - 1 - read-only - - - BUSBUSY - Indicates that the bus is busy -The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus -1: Busy -0: Not busy - 11 - 1 - read-only - - - ACK - Indicates the type of the last received/transmitted acknowledgement bit: -1: ACK -0: NACK - 10 - 1 - read-only - - - CMPL - Transaction Completion -Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration -Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - 9 - 1 - write-only - - - BYTERECV - Indicates that a byte of data has been received. - 8 - 1 - write-only - - - BYTETRANS - Indicates that a byte of data has been transmitted. - 7 - 1 - write-only - - - START - Indicates that a START Condition or a repeated START condition has been transmitted/received. - 6 - 1 - write-only - - - STOP - Indicates that a STOP Condition has been transmitted/received. - 5 - 1 - write-only - - - ARBLOSE - Indicates that the controller has lost the bus arbitration. - 4 - 1 - write-only - - - ADDRHIT - Master: indicates that a slave has responded to the transaction. -Slave: indicates that a transaction is targeting the controller (including the General Call). - 3 - 1 - write-only - - - FIFOHALF - Transmitter: Indicates that the FIFO is half-empty. - 2 - 1 - read-only - - - FIFOFULL - Indicates that the FIFO is full. - 1 - 1 - read-only - - - FIFOEMPTY - Indicates that the FIFO is empty. - 0 - 1 - read-only - - - - - ADDR - Address Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 10 - 22 - read-write - - - ADDR - The slave address. -For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - 0 - 10 - read-write - - - - - DATA - Data Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 8 - 24 - read-write - - - DATA - Write this register to put one byte of data to the FIFO. -Read this register to get one byte of data from the FIFO. - 0 - 8 - read-write - - - - - CTRL - Control Register - 0x24 - 32 - 0x00001E00 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 13 - 19 - read-write - - - PHASE_START - Enable this bit to send a START condition at the beginning of transaction. -Master mode only. - 12 - 1 - read-write - - - PHASE_ADDR - Enable this bit to send the address after START condition. -Master mode only. - 11 - 1 - read-write - - - PHASE_DATA - Enable this bit to send the data after Address phase. -Master mode only. - 10 - 1 - read-write - - - PHASE_STOP - Enable this bit to send a STOP condition at the end of a transaction. -Master mode only. - 9 - 1 - read-write - - - DIR - Transaction direction -Master: Set this bit to determine the direction for the next transaction. -0: Transmitter -1: Receiver -Slave: The direction of the last received transaction. -0: Receiver -1: Transmitter - 8 - 1 - read-write - - - DATACNT - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means 256 bytes. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 0 - 8 - read-write - - - - - CMD - Command Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 3 - 29 - read-write - - - CMD - Write this register with the following values to perform the corresponding actions: -0x0: no action -0x1: issue a data transaction (Master only) -0x2: respond with an ACK to the received byte -0x3: respond with a NACK to the received byte -0x4: clear the FIFO -0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) -When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. -Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - 0 - 3 - read-write - - - - - SETUP - Setup Register - 0x2c - 32 - 0x05252100 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 29 - 3 - read-write - - - T_SUDAT - T_SUDAT defines the data setup time before releasing the SCL. -Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) -tpclk = PCLK period -TPM = The multiplier value in Timing Parameter Multiplier Register - 24 - 5 - read-write - - - T_SP - T_SP defines the pulse width of spikes that must be suppressed by the input filter. -Pulse width = T_SP * tpclk* (TPM+1) - 21 - 3 - read-write - - - T_HDDAT - T_HDDAT defines the data hold time after SCL goes LOW -Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - 16 - 5 - read-write - - - RESERVED - No description avaiable - 14 - 2 - read-write - - - T_SCLRADIO - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. -SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) -1: ratio = 2 -0: ratio = 1 -This field is only valid when the controller is in the master mode. - 13 - 1 - read-write - - - T_SCLHI - The HIGH period of generated SCL clock is defined by T_SCLHi. -SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) -The T_SCLHi value must be greater than T_SP and T_HDDAT values. -This field is only valid when the controller is in the master mode. - 4 - 9 - read-write - - - DMAEN - Enable the direct memory access mode data transfer. -1: Enable -0: Disable - 3 - 1 - read-write - - - MASTER - Configure this device as a master or a slave. -1: Master mode -0: Slave mode - 2 - 1 - read-write - - - ADDRESSING - I2C addressing mode: -1: 10-bit addressing mode -0: 7-bit addressing mode - 1 - 1 - read-write - - - IICEN - Enable the I2C controller. -1: Enable -0: Disable - 0 - 1 - read-write - - - - - TPM - I2C Timing Paramater Multiplier - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - No description avaiable - 5 - 27 - read-write - - - TPM - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - 0 - 5 - read-write - - - - - - - I2C1 - I2C1 - I2C - 0xf3024000 - - - I2C2 - I2C2 - I2C - 0xf3028000 - - - I2C3 - I2C3 - I2C - 0xf302c000 - - - SDP - SDP - SDP - 0xf304c000 - - 0x0 - 0x60 - registers - - - - SDPCR - SDP control register - 0x0 - 32 - 0x30000000 - 0xFFFE0101 - - - SFTRST - soft reset. -Write 1 then 0, to reset the SDP block. - 31 - 1 - read-write - - - CLKGAT - Clock Gate for the SDP main logic. -Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - 30 - 1 - read-write - - - CIPDIS - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. -1, Cipher is disabled in this chip. -0, Cipher is enabled in this chip. - 29 - 1 - read-only - - - HASDIS - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. -1, HASH is disabled in this chip. -0, HASH is enabled in this chip. - 28 - 1 - read-only - - - RESERVED - Not used - 24 - 4 - read-only - - - CIPHEN - Cipher Enablement, controlled by SW. -1, Cipher is Enabled. -0, Cipher is Disabled. - 23 - 1 - read-write - - - HASHEN - HASH Enablement, controlled by SW. -1, HASH is Enabled. -0, HASH is Disabled. - 22 - 1 - read-write - - - MCPEN - Memory Copy Enablement, controlled by SW. -1, Memory copy is Enabled. -0, Memory copy is Disabled. - 21 - 1 - read-write - - - CONFEN - Constant Fill to memory, controlled by SW. -1, Constant fill is Enabled. -0, Constant fill is Disabled. - 20 - 1 - read-write - - - DCRPDI - Decryption Disable bit, Write to 1 to disable the decryption. - 19 - 1 - read-write - - - RESERVED - Reserved - 18 - 1 - read-write - - - TSTPKT0IRQ - Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - 17 - 1 - read-write - - - RDSCEN - when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) -when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - 8 - 1 - read-write - - - INTEN - Interrupt Enablement, controlled by SW. -1, SDP interrupt is enabled. -0, SDP interrupt is disabled. - 0 - 1 - read-write - - - - - MODCTRL - Mod control register. - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - AESALG - AES algorithem selection. -0x0 = AES 128; -0x1 = AES 256; -Others, reserved. - 28 - 4 - read-write - - - AESMOD - AES mode selection. -0x0 = ECB; -0x1 = CBC; -Others, reserved. - 24 - 4 - read-write - - - AESKS - AES Key Selection. -These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: -0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. -0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -.... -0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. -0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. -0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. -0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. -0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. -0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. -0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. -0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. -0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. -0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. -0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. -0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. -0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. -Other values, reserved. - 18 - 6 - read-write - - - RESERVED - Not used - 17 - 1 - read-only - - - AESDIR - AES direction -1x1, AES Decryption -1x0, AES Encryption. - 16 - 1 - read-write - - - HASALG - HASH Algorithem selection. -0x0 SHA1 — -0x1 CRC32 — -0x2 SHA256 — - 12 - 4 - read-write - - - CRCEN - CRC enable. -1x1, CRC is enabled. -1x0, CRC is disabled. - 11 - 1 - read-write - - - HASCHK - HASH Check Enable Bit. -1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; -1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. -For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - 10 - 1 - read-write - - - HASOUT - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. -0 INPUT HASH -1 OUTPUT HASH - 9 - 1 - read-write - - - RESERVED - Not used - 8 - 1 - read-only - - - RESERVED - Not used - 6 - 2 - read-only - - - DINSWP - Decide whether the SDP byteswaps the input data (big-endian data); -When all bits are set, the data is assumed to be in the big-endian format - 4 - 2 - read-write - - - DOUTSWP - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - 2 - 2 - read-write - - - KEYSWP - Decide whether the SDP byteswaps the Key (big-endian data). -When all bits are set, the data is assumed to be in the big-endian format - 0 - 2 - read-write - - - - - PKTCNT - packet counter registers. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESERVED - Not used - 31 - 1 - read-write - - - RESERVED - Not used - 30 - 1 - read-write - - - RESERVED - Not used - 24 - 6 - read-only - - - CNTVAL - This read-only field shows the current (instantaneous) value of the packet counter - 16 - 8 - read-only - - - RESERVED - Not used - 8 - 8 - read-only - - - CNTINCR - The value written to this field is added to the spacket count. - 0 - 8 - read-write - - - - - STA - Status Registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TAG - packet tag. - 24 - 8 - read-only - - - IRQ - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - 23 - 1 - write-only - - - RESERVED - Not used - 21 - 2 - read-only - - - CHN1PKT0 - the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - 20 - 1 - write-only - - - AESBSY - AES Busy - 19 - 1 - read-only - - - HASBSY - Hashing Busy - 18 - 1 - read-only - - - PKTCNT0 - Packet Counter registers reachs to ZERO now. - 17 - 1 - write-only - - - PKTDON - Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - 16 - 1 - write-only - - - RESERVED - Not used - 6 - 10 - read-only - - - ERRSET - Working mode setup error. - 5 - 1 - write-only - - - ERRPKT - Packet head access error, or status update error. - 4 - 1 - write-only - - - ERRSRC - Source Buffer Access Error - 3 - 1 - write-only - - - ERRDST - Destination Buffer Error - 2 - 1 - write-only - - - ERRHAS - Hashing Check Error - 1 - 1 - write-only - - - ERRCHAIN - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - 0 + SW_RST_DAT + Software Reset For DAT line +This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. +The following registers and bits are cleared by this bit: +Buffer Data Port register +-Buffer is cleared and initialized. +Present state register +-Buffer Read Enable +-Buffer Write Enable +-Read Transfer Active +-Write Transfer Active +-DAT Line Active +-Command Inhibit (DAT) +Block Gap Control register +-Continue Request +-Stop At Block Gap Request +Normal Interrupt status register +-Buffer Read Ready +-Buffer Write Ready +-DMA Interrupt +-Block Gap Event +-Transfer Complete +In UHS-II mode, this bit shall be set to 0 +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 26 1 - write-only - - - - - KEYADDR - Key Address - 0x10 - 32 - 0x00000040 - 0xFFFFFFFF - - - RESERVED - Not used - 24 - 8 - read-only - - - INDEX - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. -Key index pointer. The valid indices are 0-[number_keys]. -In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - 16 - 8 - read-write - - - RESERVED - Not used - 2 - 14 - read-only - - - SUBWRD - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field -increments; To write a key, the software must first write the desired key index/subword to this register. - 0 - 2 - read-write - - - - - KEYDAT - Key Data - 0x14 - 32 - 0x00000030 - 0xFFFFFFFF - - - KEYDAT - This register provides the write access to the key/key subword specified by the key index register. -Writing this location updates the selected subword for the key located at the index -specified by the key index register. The write also triggers the SUBWORD field of the -KEY register to increment to the next higher word in the key - 0 - 32 - read-write - - - - - CIPHIV_CIPHIV0 - Cipher Initializtion Vector 0 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - CIPHIV_CIPHIV1 - Cipher Initializtion Vector 1 - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - CIPHIV_CIPHIV2 - Cipher Initializtion Vector 2 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - CIPHIV_CIPHIV3 - Cipher Initializtion Vector 3 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - HASWRD_HASWRD0 - Hash Data Word 0 - 0x28 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD1 - Hash Data Word 1 - 0x2c - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD2 - Hash Data Word 2 - 0x30 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD3 - Hash Data Word 3 - 0x34 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD4 - Hash Data Word 4 - 0x38 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD5 - Hash Data Word 5 - 0x3c - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD6 - Hash Data Word 6 - 0x40 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - HASWRD_HASWRD7 - Hash Data Word 7 - 0x44 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - CMDPTR - Command Pointer - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMDPTR - current command addresses the register points to the multiword -descriptor that is to be executed (or is currently being executed) - 0 - 32 read-write - - - - NPKTPTR - Next Packet Address Pointer - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - NPKTPTR - Next Packet Address Pointer - 0 - 32 - read-write - - - - - PKTCTL - Packet Control Registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - + SW_RST_CMD + Software Reset For CMD line +This bit resets only a part of the command circuit to be able to issue a command. +It bit is also used to initialize a UHS-II command circuit. +This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. +Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. +The following registers and bits are cleared by this bit: +Present State register : Command Inhibit (CMD) bit +Normal Interrupt Status register : Command Complete bit +Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset + 25 + 1 + read-write + - PKTTAG - packet tag + SW_RST_ALL + Software Reset For All +This reset affects the entire Host Controller except for the card detection circuit. +During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. +All registers are reset except the capabilities register. +If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. +Values: +0x0 (FALSE): Work +0x1 (TRUE): Reset 24 - 8 + 1 read-write - RESERVED - Not used - 7 - 17 + TOUT_CNT + Data Timeout Counter Value. +This value determines the interval by which DAT line timeouts are detected. +The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. +When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). +The values for these bits are: +0xF : Reserved +0xE : TMCLK x 2^27 +......... +0x1 : TMCLK x 2^14 +0x0 : TMCLK x 2^13 +Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. + 16 + 4 read-write - CIPHIV - Load Initial Vector for the AES in this packet. - 6 - 1 + FREQ_SEL + SDCLK/RCLK Frequency Select +These bits are used to select the frequency of the SDCLK signal. +These bits depend on setting of Preset Value Enable in the Host Control 2 register. +If Preset Value Enable = 0, these bits are set by the Host Driver. +If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. +The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. +10-bit Divided Clock Mode: +0x3FF : 1/2046 Divided clock +.......... +N : 1/2N Divided Clock +.......... +0x002 : 1/4 Divided Clock +0x001 : 1/2 Divided Clock +0x000 : Base clock (10MHz - 255 MHz) +Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: +0x3FF : Base clock * M /1024 +.......... +N-1 : Base clock * M /N +.......... +0x002 : Base clock * M /3 +0x001 : Base clock * M /2 +0x000 : Base clock * M + 8 + 8 read-write - HASFNL - Hash Termination packet - 5 - 1 + UPPER_FREQ_SEL + These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. +The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. + 6 + 2 read-write - HASINI - Hash Initialization packat - 4 + CLK_GEN_SELECT + Clock Generator Select +This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. +If Preset Value Enable = 0, this bit is set by the Host Driver. +If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. +The value is reflected on the card_clk_gen_sel signal. +Values: +0x0 (FALSE): Divided Clock Mode +0x1 (TRUE): Programmable Clock Mode + 5 1 read-write - CHAIN - whether the next command pointer register must be loaded into the channel's current descriptor -pointer. + PLL_ENABLE + PLL Enable +This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). +When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. +Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . +Values: +0x0 (FALSE): PLL is in low power mode +0x1 (TRUE): PLL is enabled 3 1 read-write - DCRSEMA - whether the channel's semaphore must be decremented at the end of the current operation. -When the semaphore reaches a value of zero, no more operations are issued from the channel. + SD_CLK_EN + SD/eMMC Clock Enable +This bit stops the SDCLK or RCLK when set to 0. +The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. +The value is reflected on the clk2card_on pin. +Values: +0x0 (FALSE): Disable providing SDCLK/RCLK +0x1 (TRUE): Enable providing SDCLK/RCLK 2 1 read-write - PKTINT - Reflects whether the channel must issue an interrupt upon the completion of the packet + INTERNAL_CLK_STABLE + Internal Clock Stable +This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. +This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, +and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. +Values: +0x0 (FALSE): Not Ready +0x1 (TRUE): Ready 1 1 read-write - RESERVED - Not used + INTERNAL_CLK_EN + Internal Clock Enable +This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. +The Host Controller must stop its internal clock to enter a very low power state. +However, registers can still be read and written to. The value is reflected on the intclk_en signal. +Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . +Values: +0x0 (FALSE): Stop +0x1 (TRUE): Oscillate 0 1 read-write @@ -57149,395 +48919,328 @@ When the semaphore reaches a value of zero, no more operations are issued from t - PKTSRC - Packet Memory Source Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTSRC - Packet Memory Source Address - 0 - 32 - read-write - - - - - PKTDST - Packet Memory Destination Address - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTDST - Packet Memory Destination Address - 0 - 32 - read-write - - - - - PKTBUF - Packet buffer size. - 0x5c + INT_STAT + No description avaiable + 0x30 32 0x00000000 - 0xFFFFFFFF + 0x1FFFF1FF - PKTBUF - No description avaiable - 0 - 32 + BOOT_ACK_ERR + Boot Acknowledgement Error +This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. +In SD/UHS-II mode, this bit is irrelevant. + 28 + 1 read-write - - - - - - FEMC - FEMC - FEMC - 0xf3050000 - - 0x0 - 0x154 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x1FFF0007 - - BTO - Bus timeout cycles -AXI Bus timeout cycle is as following (255*(2^BTO)): -00000b - 255*1 -00001-11110b - 255*2 - 255*2^30 -11111b - 255*2^31 - 24 - 5 + RESP_ERR + Response Error +Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. +If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 27 + 1 read-write - CTO - Command Execution timeout cycles -When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is -generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is -CTO*1024 cycle. - 16 - 8 + TUNING_ERR + Tuning Error +This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure +(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). +By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. +To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. +The Tuning Error is higher priority than the other error interrupts generated during data transfer. +By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. +This is applicable in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 26 + 1 read-write - DQS - DQS (read strobe) mode -0b - Dummy read strobe loopbacked internally -1b - Dummy read strobe loopbacked from DQS pad - 2 + ADMA_ERR + ADMA Error +This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: +Error response received from System bus (Master I/F) +ADMA3,ADMA2 Descriptors invalid +CQE Task or Transfer descriptors invalid +When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. +In eMMC CQE mode: +The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. +ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. +The Host Driver may find that Valid bit is not set at the error descriptor. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 25 1 read-write - DIS - Module Disable -0b - Module enabled -1b - Module disabled - 1 + AUTO_CMD_ERR + Auto CMD Error +This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. +This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. +D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 24 1 read-write - RST - Software Reset -Reset all internal logic in SEMC except configuration register - 0 + CUR_LMT_ERR + Current Limit Error +By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. +If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. +A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. +A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. +The Host Controller may require some sampling time to detect the current limit. +SDXC Host Controller does not support this function, this bit is always set to 0. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Power Fail + 23 1 read-write - - - - IOCTRL - IO Mux Control Register - 0x4 - 32 - 0x00000000 - 0x000000F0 - - IO_CSX - IO_CSX output selection -0001b - SDRAM CS1 -0110b - SRAM CE# - 4 - 4 + DATA_END_BIT_ERR + Data End Bit Error +This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 22 + 1 read-write - - - - BMW0 - Bus (AXI) Weight Control Register 0 - 0x8 - 32 - 0x00000000 - 0x00FFFFFF - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 + DATA_CRC_ERR + Data CRC Error +This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, +when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 21 + 1 read-write - SH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 + DATA_TOUT_ERR + Data Timeout Error +This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: +Busy timeout for R1b, R5b type +Busy timeout after Write CRC status +Write CRC Status timeout +Read Data timeout +Values: +0x0 (FALSE): No error +0x1 (TRUE): Time out + 20 + 1 read-write - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 + CMD_IDX_ERR + Command Index Error +This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 19 + 1 read-write - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 + CMD_END_BIT_ERR + Command End Bit Error +This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. +Values: +0x0 (FALSE): No error +0x1 (TRUE): End Bit error generated + 18 + 1 read-write - - - - BMW1 - Bus (AXI) Weight Control Register 1 - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - BR - Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current -executing command. - 24 - 8 + CMD_CRC_ERR + Command CRC Error +Command CRC Error is generated in SD/eMMC mode for following two cases. +If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. +The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. +If the Host Controller drives the CMD line to 1 level, +but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. +The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. +Values: +0x0 (FALSE): No error +0x1 (TRUE): CRC error generated + 17 + 1 read-write - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. + CMD_TOUT_ERR + Command Timeout Error +In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. +If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. +Values: +0x0 (FALSE): No error +0x1 (TRUE): Time out 16 - 8 - read-write - - - PH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 + 1 read-write - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write + ERR_INTERRUPT + Error Interrupt +If any of the bits in the Error Interrupt Status register are set, then this bit is set. +Values: +0x0 (FALSE): No Error +0x1 (TRUE): Error + 15 + 1 + read-only - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 + CQE_EVENT + Command Queuing Event +This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. +Values: +0x0 (FALSE): No Event +0x1 (TRUE): Command Queuing Event is detected + 14 + 1 read-write - - - - BR_BASE0 - Base Register 0 (for SDRAM CS0 device) - 0x10 - 32 - 0x00000000 - 0xFFFFF03F - - BASE - Base Address -This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low -position 12 bits are all zero. - 12 - 20 - read-write + FX_EVENT + FX Event +This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. +Values: +0x0 (FALSE): No Event +0x1 (TRUE): FX Event is detected + 13 + 1 + read-only - SIZE - Memory size -00000b - 4KB -00001b - 8KB -00010b - 16KB -00011b - 32KB -00100b - 64KB -00101b - 128KB -00110b - 256KB -00111b - 512KB -01000b - 1MB -01001b - 2MB -01010b - 4MB -01011b - 8MB -01100b - 16MB -01101b - 32MB -01110b - 64MB -01111b - 128MB -10000b - 256MB -10001b - 512MB -10010b - 1GB -10011b - 2GB -10100-11111b - 4GB - 1 - 5 + RE_TUNE_EVENT + Re-tuning Event +This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. + 12 + 1 + read-only + + + CARD_INTERRUPT + Card Interrupt +This bit reflects the synchronized value of: +DAT[1] Interrupt Input for SD Mode +DAT[2] Interrupt Input for UHS-II Mode +Values: +0x0 (FALSE): No Card Interrupt +0x1 (TRUE): Generate Card Interrupt + 8 + 1 + read-only + + + CARD_REMOVAL + Card Removal +This bit is set if the Card Inserted in the Present State register changes from 1 to 0. +Values: +0x0 (FALSE): Card state stable or Debouncing +0x1 (TRUE): Card Removed + 7 + 1 read-write - VLD - Valid - 0 + CARD_INSERTION + Card Insertion +This bit is set if the Card Inserted in the Present State register changes from 0 to 1. +Values: +0x0 (FALSE): Card state stable or Debouncing +0x1 (TRUE): Card Inserted + 6 1 read-write - - - - BR_BASE1 - Base Register 1 (for SDRAM CS1 device) - 0x14 - 32 - 0x00000000 - 0xFFFFF03F - - BASE - Base Address -This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low -position 12 bits are all zero. - 12 - 20 + BUF_RD_READY + Buffer Read Ready +This bit is set if the Buffer Read Enable changes from 0 to 1. +Values: +0x0 (FALSE): Not ready to read buffer +0x1 (TRUE): Ready to read buffer + 5 + 1 read-write - SIZE - Memory size -00000b - 4KB -00001b - 8KB -00010b - 16KB -00011b - 32KB -00100b - 64KB -00101b - 128KB -00110b - 256KB -00111b - 512KB -01000b - 1MB -01001b - 2MB -01010b - 4MB -01011b - 8MB -01100b - 16MB -01101b - 32MB -01110b - 64MB -01111b - 128MB -10000b - 256MB -10001b - 512MB -10010b - 1GB -10011b - 2GB -10100-11111b - 4GB - 1 - 5 + BUF_WR_READY + Buffer Write Ready +This bit is set if the Buffer Write Enable changes from 0 to 1. +Values: +0x0 (FALSE): Not ready to write buffer +0x1 (TRUE): Ready to write buffer + 4 + 1 read-write - VLD - Valid - 0 + DMA_INTERRUPT + DMA Interrupt +This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. +In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. +This interrupt is not generated after a Transfer Complete. +Values: +0x0 (FALSE): No DMA Interrupt +0x1 (TRUE): DMA Interrupt is generated + 3 1 read-write - - - - BR_BASE6 - Base Register 6 (for SRAM device) - 0x28 - 32 - 0x00000000 - 0xFFFFF03F - - BASE - Base Address -This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low -position 12 bits are all zero. - 12 - 20 + BGAP_EVENT + Block Gap Event +This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. +Values: +0x0 (FALSE): No Block Gap Event +0x1 (TRUE): Transaction stopped at block gap + 2 + 1 read-write - SIZE - Memory size -00000b - 4KB -00001b - 8KB -00010b - 16KB -00011b - 32KB -00100b - 64KB -00101b - 128KB -00110b - 256KB -00111b - 512KB -01000b - 1MB -01001b - 2MB -01010b - 4MB -01011b - 8MB -01100b - 16MB -01101b - 32MB -01110b - 64MB -01111b - 128MB -10000b - 256MB -10001b - 512MB -10010b - 1GB -10011b - 2GB -10100-11111b - 4GB + XFER_COMPLETE + Transfer Complete +This bit is set when a read/write transfer and a command with status busy is completed. +Values: +0x0 (FALSE): Not complete +0x1 (TRUE): Command execution is completed 1 - 5 + 1 read-write - VLD - Valid + CMD_COMPLETE + Command Complete +In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. +This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. +Values: +0x0 (FALSE): No command complete +0x1 (TRUE): Command Complete 0 1 read-write @@ -57545,554 +49248,526 @@ position 12 bits are all zero. - INTEN - Interrupt Enable Register - 0x38 + INT_STAT_EN + No description avaiable + 0x34 32 0x00000000 - 0x0000000F + 0x1FFF71FF - AXIBUSERR - AXI BUS error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 3 + BOOT_ACK_ERR_STAT_EN + Boot Acknowledgment Error (eMMC Mode only) +Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (ERROR_INT_STAT_R). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 28 1 read-write - AXICMDERR - AXI command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 2 + RESP_ERR_STAT_EN + Response Error Status Enable (SD Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 27 1 read-write - IPCMDERR - IP command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 1 + TUNING_ERR_STAT_EN + Tuning Error Status Enable (UHS-I Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 26 1 read-write - IPCMDDONE - IP command done interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 0 + ADMA_ERR_STAT_EN + ADMA Error Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 25 1 read-write - - - - INTR - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000000F - - AXIBUSERR - AXI bus error interrupt -AXI Bus error interrupt is generated in following cases: -• AXI address is invalid -• AXI 8-bit or 16-bit WRAP write/read - 3 + AUTO_CMD_ERR_STAT_EN + Auto CMD Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 24 1 - write-only + read-write - AXICMDERR - AXI command error interrupt -AXI command error interrupt is generated when AXI command execution timeout. - 2 + CUR_LMT_ERR_STAT_EN + Current Limit Error Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 23 1 - write-only + read-write - IPCMDERR - IP command error done interrupt -IP command error interrupt is generated in following case: -• IP Command Address target invalid device space -• IP Command Code unsupported -• IP Command triggered when previous command - 1 + DATA_END_BIT_ERR_STAT_EN + Data End Bit Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 22 1 - write-only + read-write - IPCMDDONE - IP command normal done interrupt - 0 + DATA_CRC_ERR_STAT_EN + Data CRC Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 21 1 - write-only + read-write - - - - SDRCTRL0 - SDRAM Control Register 0 - 0x40 - 32 - 0x00000000 - 0x00004FFB - - BANK2 - 2 Bank selection bit -0b - SDRAM device has 4 banks. -1b - SDRAM device has 2 banks. - 14 + DATA_TOUT_ERR_STAT_EN + Data Timeout Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 20 1 read-write - CAS - CAS Latency -00b - 1 -01b - 1 -10b - 2 -11b - 3 - 10 - 2 + CMD_IDX_ERR_STAT_EN + Command Index Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 19 + 1 read-write - COL - Column address bit number -00b - 12 bit -01b - 11 bit -10b - 10 bit -11b - 9 bit - 8 - 2 + CMD_END_BIT_ERR_STAT_EN + Command End Bit Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 18 + 1 read-write - COL8 - Column 8 selection bit -0b - Column address bit number is decided by COL field. -1b - Column address bit number is 8. COL field is ignored. - 7 + CMD_CRC_ERR_STAT_EN + Command CRC Error Status Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 17 1 read-write - BURSTLEN - Burst Length -000b - 1 -001b - 2 -010b - 4 -011b - 8 -100b - 8 -101b - 8 -110b - 8 -111b - 8 - 4 - 3 + CMD_TOUT_ERR_STAT_EN + Command Timeout Error Status Enable (SD/eMMC Mode only). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 16 + 1 read-write - HIGHBAND - high band select -0: use data[15:0] for 16bit SDRAM; -1: use data[31:16] for 16bit SDRAM; -only used when Port Size is 16bit(PORTSZ=01b) - 3 + CQE_EVENT_STAT_EN + CQE Event Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 14 1 read-write - PORTSZ - Port Size -00b - 8bit -01b - 16bit -10b - 32bit - 0 - 2 + FX_EVENT_STAT_EN + FX Event Status Enable +This bit is added from Version 4.10. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 13 + 1 read-write - - - - SDRCTRL1 - SDRAM Control Register 1 - 0x44 - 32 - 0x00000000 - 0x00FFFFFF - - ACT2PRE - ACT to Precharge minimum time -It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - 20 - 4 + RE_TUNE_EVENT_STAT_EN + Re-Tuning Event (UHS-I only) Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 12 + 1 read-write - CKEOFF - CKE OFF minimum time -It is promised clock suspend last at leat CKEOFF+1 clock cycles. - 16 - 4 + CARD_INTERRUPT_STAT_EN + Card Interrupt Status Enable +If this bit is set to 0, the Host Controller clears the interrupt request to the System. +The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. +The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. +By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 8 + 1 read-write - WRC - Write recovery time -It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - 13 - 3 + CARD_REMOVAL_STAT_EN + Card Removal Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 7 + 1 read-write - RFRC - Refresh recovery time -It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - 8 - 5 + CARD_INSERTION_STAT_EN + Card Insertion Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 6 + 1 read-write - ACT2RW - ACT to Read/Write wait time -It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - 4 - 4 + BUF_RD_READY_STAT_EN + Buffer Read Ready Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 5 + 1 read-write - PRE2ACT - PRECHARGE to ACT/Refresh wait time -It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - 0 - 4 + BUF_WR_READY_STAT_EN + Buffer Write Ready Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 4 + 1 read-write - - - - SDRCTRL2 - SDRAM Control Register 2 - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - ITO - SDRAM Idle timeout -It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is -considered idle when there is no AXI Bus transfer and no SDRAM command pending. -00000000b - IDLE timeout period is 256*Prescale period. -00000001-11111111b - IDLE timeout period is ITO*Prescale period. - 24 - 8 + DMA_INTERRUPT_STAT_EN + DMA Interrupt Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 3 + 1 read-write - ACT2ACT - ACT to ACT wait time -It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This -could help to meet tRRD timing requirement by SDRAM device. - 16 - 8 + BGAP_EVENT_STAT_EN + Block Gap Event Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 2 + 1 read-write - REF2REF - Refresh to Refresh wait time -It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. -This could help to meet tRFC timing requirement by SDRAM device. - 8 - 8 + XFER_COMPLETE_STAT_EN + Transfer Complete Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 1 + 1 read-write - SRRC - Self Refresh Recovery time -It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. + CMD_COMPLETE_STAT_EN + Command Complete Status Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled 0 - 8 + 1 read-write - SDRCTRL3 - SDRAM Control Register 3 - 0x4c + INT_SIGNAL_EN + No description avaiable + 0x38 32 0x00000000 - 0xFFFFFF0F + 0x1FFF71FF - UT - Refresh urgent threshold -Internal refresh request is generated on every Refresh period. Before internal request timer count up to -urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh -request is handled in lower priority than any pending AXI command or IP command to SDRAM device. -When internal request timer count up to this urgent threshold, refresh request is considered as urgent -refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP -command to SDRAM device. -NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as -urgent refresh request. -Refresh urgent threshold is as follwoing: -00000000b - 256*Prescaler period -00000001-11111111b - UT*Prescaler period - 24 - 8 + BOOT_ACK_ERR_SIGNAL_EN + Boot Acknowledgment Error (eMMC Mode only). +Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgement Error in Error Interrupt Status register is set. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 28 + 1 read-write - RT - Refresh timer period -Refresh timer period is as following: -00000000b - 256*Prescaler period -00000001-11111111b - RT*Prescaler period - 16 - 8 + RESP_ERR_SIGNAL_EN + Response Error Signal Enable (SD Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 27 + 1 read-write - PRESCALE - Prescaler timer period -Prescaler timer period is as following: -00000000b - 256*16 clock cycles -00000001-11111111b - PRESCALE*16 clock cycles - 8 - 8 + TUNING_ERR_SIGNAL_EN + Tuning Error Signal Enable (UHS-I Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 26 + 1 read-write - REBL - Refresh burst length -It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The -number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. -000b - 1 -001b - 2 -010b - 3 -011b - 4 -100b - 5 -101b - 6 -110b - 7 -111b - 8 - 1 - 3 + ADMA_ERR_SIGNAL_EN + ADMA Error Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 25 + 1 read-write - REN - Refresh enable - 0 + AUTO_CMD_ERR_SIGNAL_EN + Auto CMD Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 24 1 read-write - - - - SRCTRL0 - SRAM control register 0 - 0x70 - 32 - 0x00000000 - 0x00000F01 - - ADVH - ADV hold state -0b - ADV is high during address hold state -1b - ADV is low during address hold state - 11 + CUR_LMT_ERR_SIGNAL_EN + Current Limit Error Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 23 1 read-write - ADVP - ADV polarity -0b - ADV is active low -1b - ADV is active high - 10 + DATA_END_BIT_ERR_SIGNAL_EN + Data End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 22 1 read-write - ADM - address data mode -00b - address and data MUX mode -11b - address and data non-MUX mode - 8 - 2 + DATA_CRC_ERR_SIGNAL_EN + Data CRC Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 21 + 1 read-write - PORTSZ - port size -0b - 8bit -1b - 16bit - 0 + DATA_TOUT_ERR_SIGNAL_EN + Data Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 20 1 read-write - - - - SRCTRL1 - SRAM control register 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - OEH - OE high time, is OEH+1 clock cycles - 28 - 4 + CMD_IDX_ERR_SIGNAL_EN + Command Index Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): No error +0x1 (TRUE): Error + 19 + 1 read-write - OEL - OE low time, is OEL+1 clock cycles - 24 - 4 + CMD_END_BIT_ERR_SIGNAL_EN + Command End Bit Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 18 + 1 read-write - WEH - WE high time, is WEH+1 clock cycles - 20 - 4 + CMD_CRC_ERR_SIGNAL_EN + Command CRC Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 17 + 1 read-write - WEL - WE low time, is WEL+1 clock cycles + CMD_TOUT_ERR_SIGNAL_EN + Command Timeout Error Signal Enable (SD/eMMC Mode only) +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled 16 - 4 + 1 read-write - AH - Address hold time, is AH+1 clock cycles + CQE_EVENT_SIGNAL_EN + Command Queuing Engine Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 14 + 1 + read-write + + + FX_EVENT_SIGNAL_EN + FX Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 13 + 1 + read-write + + + RE_TUNE_EVENT_SIGNAL_EN + Re-Tuning Event (UHS-I only) Signal Enable. +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled 12 - 4 + 1 read-write - AS - Address setup time, is AS+1 clock cycles + CARD_INTERRUPT_SIGNAL_EN + Card Interrupt Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled 8 - 4 + 1 read-write - CEH - Chip enable hold time, is CEH+1 clock cycles - 4 - 4 + CARD_REMOVAL_SIGNAL_EN + Card Removal Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 7 + 1 read-write - CES - Chip enable setup time, is CES+1 clock cycles - 0 - 4 + CARD_INSERTION_SIGNAL_EN + Card Insertion Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 6 + 1 read-write - - - - SADDR - IP Command Control Register 0 - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - SA - Slave address - 0 - 32 + BUF_RD_READY_SIGNAL_EN + Buffer Read Ready Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 5 + 1 read-write - - - - DATSZ - IP Command Control Register 1 - 0x94 - 32 - 0x00000000 - 0x00000007 - - DATSZ - Data Size in Byte -When IP command is not a write/read operation, DATSZ field would be ignored. -000b - 4 -001b - 1 -010b - 2 -011b - 3 -100b - 4 -101b - 4 -110b - 4 -111b - 4 - 0 - 3 + BUF_WR_READY_SIGNAL_EN + Buffer Write Ready Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled + 4 + 1 read-write - - - - BYTEMSK - IP Command Control Register 2 - 0x98 - 32 - 0x00000000 - 0x0000000F - - BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) -0b - Byte Unmasked -1b - Byte Masked + DMA_INTERRUPT_SIGNAL_EN + DMA Interrupt Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled 3 1 read-write - BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) -0b - Byte Unmasked -1b - Byte Masked + BGAP_EVENT_SIGNAL_EN + Block Gap Event Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled 2 1 read-write - BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) -0b - Byte Unmasked -1b - Byte Masked + XFER_COMPLETE_SIGNAL_EN + Transfer Complete Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled 1 1 read-write - BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) -0b - Byte Unmasked -1b - Byte Masked + CMD_COMPLETE_SIGNAL_EN + Command Complete Signal Enable +Values: +0x0 (FALSE): Masked +0x1 (TRUE): Enabled 0 1 read-write @@ -58100,3429 +49775,3310 @@ When IP command is not a write/read operation, DATSZ field would be ignored. - IPCMD - IP Command Register - 0x9c + AC_HOST_CTRL + No description avaiable + 0x3c 32 0x00000000 - 0xFFFFFFFF + 0xDCCF00BF - KEY - This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory -device is selected by BRx settings and IPCR0 registers. + PRESET_VAL_ENABLE + Preset Value Enable +This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. +When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. +These values are selected from set of Preset Value registers based on selected speed mode. +Values: +0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver +0x1 (TRUE): Automatic Selection by Preset Value are Enabled + 31 + 1 + read-write + + + ASYNC_INT_ENABLE + Asynchronous Interrupt Enable +This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. +Values: +0x0 (FALSE): Disabled +0x1 (TRUE): Enabled + 30 + 1 + read-write + + + HOST_VER4_ENABLE + Host Version 4 Enable +This bit selects either Version 3.00 compatible mode or Version 4 mode. +Functions of following fields are modified for Host Version 4 mode: +SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) +ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register +64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 +Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register +32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register +Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, +UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). +Values: +0x0 (FALSE): Version 3.00 compatible mode +0x1 (TRUE): Version 4 mode + 28 + 1 + read-write + + + CMD23_ENABLE + CMD23 Enable +If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. +Values: +0x0 (FALSE): Auto CMD23 is disabled +0x1 (TRUE): Auto CMD23 is enabled + 27 + 1 + read-write + + + ADMA2_LEN_MODE + ADMA2 Length Mode +This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. +Values: +0x0 (FALSE): 16-bit Data Length Mode +0x1 (TRUE): 26-bit Data Length Mode + 26 + 1 + read-write + + + SAMPLE_CLK_SEL + Sampling Clock Select +This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. +This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). +Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. +The value is reflected on the sample_cclk_sel pin. +Values: +0x0 (FALSE): Fixed clock is used to sample data +0x1 (TRUE): Tuned clock is used to sample data + 23 + 1 + read-write + + + EXEC_TUNING + Execute Tuning +This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. +Values: +0x0 (FALSE): Not Tuned or Tuning completed +0x1 (TRUE): Execute Tuning + 22 + 1 + read-write + + + SIGNALING_EN + 1.8V Signaling Enable +This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. +Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. +Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. +Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). +Values: +0x0 (V_3_3): 3.3V Signalling +0x1 (V_1_8): 1.8V Signalling + 19 + 1 + read-write + + + UHS_MODE_SEL + UHS Mode/eMMC Speed Mode Select +These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. +UHS Mode (SD/UHS-II mode only): +0x0 (SDR12): SDR12/Legacy +0x1 (SDR25): SDR25/High Speed SDR +0x2 (SDR50): SDR50 +0x3 (SDR104): SDR104/HS200 +0x4 (DDR50): DDR50/High Speed DDR +0x5 (RSVD5): Reserved +0x6 (RSVD6): Reserved +0x7 (UHS2): UHS-II/HS400 +eMMC Speed Mode (eMMC mode only): +0x0: Legacy +0x1: High Speed SDR +0x2: Reserved +0x3: HS200 +0x4: High Speed DDR +0x5: Reserved +0x6: Reserved +0x7: HS400 16 - 16 - write-only + 3 + read-write - CMD - SDRAM Commands: -• 0x8: READ -• 0x9: WRITE -• 0xA: MODESET -• 0xB: ACTIVE -• 0xC: AUTO REFRESH -• 0xD: SELF REFRESH -• 0xE: PRECHARGE -• 0xF: PRECHARGE ALL -• Others: RSVD -NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - 0 - 16 - read-write + CMD_NOT_ISSUED_AUTO_CMD12 + Command Not Issued By Auto CMD12 Error +If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. +This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. +Values: +0x1 (TRUE): Not Issued +0x0 (FALSE): No Error + 7 + 1 + read-only - - - - IPTX - TX DATA Register - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - DAT - Data - 0 - 32 - read-write + AUTO_CMD_RESP_ERR + Auto CMD Response Error +This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. +This status is ignored if any bit between D00 to D04 is set to 1. +Values: +0x1 (TRUE): Error +0x0 (FALSE): No Error + 5 + 1 + read-only - - - - IPRX - RX DATA Register - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - DAT - Data - 0 - 32 - read-write + AUTO_CMD_IDX_ERR + Auto CMD Index Error +This bit is set if the command index error occurs in response to a command. +Values: +0x1 (TRUE): Error +0x0 (FALSE): No Error + 4 + 1 + read-only - - - - STAT0 - Status Register 0 - 0xc0 - 32 - 0x00000000 - 0x00000001 - - IDLE - Indicating whether it is in IDLE state. -When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no -pending device access. - 0 + AUTO_CMD_EBIT_ERR + Auto CMD End Bit Error +This bit is set when detecting that the end bit of command response is 0. +Values: +0x1 (TRUE): End Bit Error Generated +0x0 (FALSE): No Error + 3 1 read-only - - - - DLYCFG - Delay Line Config Register - 0x150 - 32 - 0x00000000 - 0x0000203F - - OE - delay clock output enable, should be set after setting DLYEN and DLYSEL - 13 + AUTO_CMD_CRC_ERR + Auto CMD CRC Error +This bit is set when detecting a CRC error in the command response. +Values: +0x1 (TRUE): CRC Error Generated +0x0 (FALSE): No Error + 2 1 - read-write + read-only - DLYSEL - delay line select, 0 for 1 cell, 31 for all 32 cells + AUTO_CMD_TOUT_ERR + Auto CMD Timeout Error +This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. +If this bit is set to 1, error status bits (D04-D01) are meaningless. +Values: +0x1 (TRUE): Time out +0x0 (FALSE): No Error 1 - 5 - read-write + 1 + read-only - DLYEN - delay line enable + AUTO_CMD12_NOT_EXEC + Auto CMD12 Not Executed +If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. +Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. + If this bit is set to 1, error status bits (D04-D01) is meaningless. +This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. +Values: +0x1 (TRUE): Not Executed +0x0 (FALSE): Executed 0 1 - read-write + read-only - - - - FFA - FFA - FFA - 0xf3058000 - - 0x0 - 0x48 - registers - - - CTRL + CAPABILITIES1 No description avaiable - 0x0 + 0x40 32 0x00000000 - 0xFFFFFE01 + 0xE7EFFFBF - SFTRST - software reset the module if asserted to be 1. -EN is only active after this bit is zero. - 31 - 1 - read-write + SLOT_TYPE_R + Slot Type +These bits indicate usage of a slot by a specific Host System. +Values: +0x0 (REMOVABLE_SLOT): Removable Card Slot +0x1 (EMBEDDED_SLOT): Embedded Slot for one Device +0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) +0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices + 30 + 2 + read-only - RSV - Reserved - 9 - 22 - read-write + ASYNC_INT_SUPPORT + Asynchronous Interrupt Support (SD Mode only) +Values: +0x0 (FALSE): Asynchronous Interrupt Not Supported +0x1 (TRUE): Asynchronous Interrupt Supported + 29 + 1 + read-only - EN - Asserted to enable the module - 0 + VOLT_18 + Voltage Support for 1.8V +Values: +0x0 (FALSE): 1.8V Not Supported +0x1 (TRUE): 1.8V Supported + 26 1 - read-write + read-only - - - - STATUS - No description avaiable - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - RSV - Reserved - 8 - 24 + VOLT_30 + Voltage Support for SD 3.0V or Embedded 1.2V +Values: +0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported +0x1 (TRUE): SD 3.0V or Embedded Supported + 25 + 1 read-only - FIR_OV - FIR Overflow err - 7 + VOLT_33 + Voltage Support for 3.3V +Values: +0x0 (FALSE): 3.3V Not Supported +0x1 (TRUE): 3.3V Supported + 24 1 read-only - FFT_OV - FFT Overflow Err - 6 + SUS_RES_SUPPORT + Suspense/Resume Support +This bit indicates whether the Host Controller supports Suspend/Resume functionality. +If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. +Values: +0x0 (FALSE): Not Supported +0x1 (TRUE): Supported + 23 1 read-only - WR_ERR - AXI Data Write Error - 5 + SDMA_SUPPORT + SDMA Support +This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. +Values: +0x0 (FALSE): SDMA not Supported +0x1 (TRUE): SDMA Supported + 22 1 read-only - RD_NXT_ERR - AXI Read Bus Error for NXT DATA - 4 + HIGH_SPEED_SUPPORT + High Speed Support +This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. +Values: +0x0 (FALSE): High Speed not Supported +0x1 (TRUE): High Speed Supported + 21 1 read-only - RD_ERR - AXI Data Read Error - 3 + ADMA2_SUPPORT + ADMA2 Support +This bit indicates whether the Host Controller is capable of using ADMA2. +Values: +0x0 (FALSE): ADMA2 not Supported +0x1 (TRUE): ADMA2 Supported + 19 1 read-only - RSV - Reserved - 2 + EMBEDDED_8_BIT + 8-bit Support for Embedded Device +This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. +Values: +0x0 (FALSE): 8-bit Bus Width not Supported +0x1 (TRUE): 8-bit Bus Width Supported + 18 1 read-only - NXT_CMD_RD_DONE - Indicate that next command sequence is already read into the module. - 1 + MAX_BLK_LEN + Maximum Block Length +This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. +The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit +Values: +0x0 (ZERO): 512 Byte +0x1 (ONE): 1024 Byte +0x2 (TWO): 2048 Byte +0x3 (THREE): Reserved + 16 + 2 + read-only + + + BASE_CLK_FREQ + Base Clock Frequency for SD clock +These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. +6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. +The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. +-0x00 : Get information through another method +-0x01 : 1 MHz +-0x02 : 2 MHz +-............. +-0x3F : 63 MHz +-0x40-0xFF : Not Supported +8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. +-0x00 : Get information through another method +-0x01 : 1 MHz +-0x02 : 2 MHz +-............ +-0xFF : 255 MHz +If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. +If these bits are all 0, the Host system has to get information using a different method. + 8 + 8 + read-only + + + TOUT_CLK_UNIT + Timeout Clock Unit +This bit shows the unit of base clock frequency used to detect Data TImeout Error. +Values: +0x0 (KHZ): KHz +0x1 (MHZ): MHz + 7 1 read-only - OP_CMD_DONE - Indicate that operation cmd is done, and data are available in system memory. + TOUT_CLK_FREQ + Timeout Clock Frequency +This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. +0x00 : Get information through another method +0x01 : 1KHz / 1MHz +0x02 : 2KHz / 2MHz +0x03 : 3KHz / 3MHz + ........... +0x3F : 63KHz / 63MHz 0 - 1 + 6 read-only - INT_EN + CAPABILITIES2 No description avaiable - 0x8 + 0x44 32 0x00000000 - 0xFFFFFFFF + 0x18FFEF7F - WRSV1 - Reserved - 8 - 24 - read-write + VDD2_18V_SUPPORT + 1.8V VDD2 Support +This bit indicates support of VDD2 for the Host System. +0x0 (FALSE): 1.8V VDD2 is not Supported +0x1 (TRUE): 1.8V VDD2 is Supported + 28 + 1 + read-only - FIR_OV - FIR Overflow err - 7 + ADMA3_SUPPORT + ADMA3 Support +This bit indicates whether the Host Controller is capable of using ADMA3. +Values: +0x0 (FALSE): ADMA3 not Supported +0x1 (TRUE): ADMA3 Supported + 27 1 - read-write + read-only - FFT_OV - FFT Overflow Err - 6 - 1 - read-write + CLK_MUL + Clock Multiplier +These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. +0x0: Clock Multiplier is not Supported +0x1: Clock Multiplier M = 2 +0x2: Clock Multiplier M = 3 + ......... +0xFF: Clock Multiplier M = 256 + 16 + 8 + read-only - WR_ERR - Enable Data Write Error interrupt - 5 - 1 - read-write + RE_TUNING_MODES + Re-Tuning Modes (UHS-I only) +These bits select the re-tuning method and limit the maximum data length. +Values: +0x0 (MODE1): Timer +0x1 (MODE2): Timer and Re-Tuning Request (Not supported) +0x2 (MODE3): Auto Re-Tuning (for transfer) +0x3 (RSVD_MODE): Reserved + 14 + 2 + read-only - RD_NXT_ERR - Enable Read Bus Error for NXT DATA interrupt - 4 + USE_TUNING_SDR50 + Use Tuning for SDR50 (UHS-I only) +Values: +0x0 (ZERO): SDR50 does not require tuning +0x1 (ONE): SDR50 requires tuning + 13 1 - read-write + read-only - RD_ERR - Enable Data Read Error interrupt - 3 + RETUNE_CNT + Timer Count for Re-Tuning (UHS-I only) +0x0: Re-Tuning Timer disabled +0x1: 1 seconds +0x2: 2 seconds +0x3: 4 seconds + ........ +0xB: 1024 seconds +0xC: Reserved +0xD: Reserved +0xE: Reserved +0xF: Get information from other source + 8 + 4 + read-only + + + DRV_TYPED + Driver Type D Support (UHS-I only) +This bit indicates support of Driver Type D for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type D is not supported +0x1 (TRUE): Driver Type D is supported + 6 1 - read-write + read-only - RSV - Write as zero - 2 + DRV_TYPEC + Driver Type C Support (UHS-I only) +This bit indicates support of Driver Type C for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type C is not supported +0x1 (TRUE): Driver Type C is supported + 5 1 - read-write + read-only - NXT_CMD_RD_DONE - Indicate that next command sequence is already read into the module. - 1 + DRV_TYPEA + Driver Type A Support (UHS-I only) +This bit indicates support of Driver Type A for 1.8 Signaling. +Values: +0x0 (FALSE): Driver Type A is not supported +0x1 (TRUE): Driver Type A is supported + 4 1 - read-write + read-only - OP_CMD_DONE - Indicate that operation cmd is done, and data are available in system memory. - 0 + UHS2_SUPPORT + UHS-II Support (UHS-II only) +This bit indicates whether Host Controller supports UHS-II. +Values: +0x0 (FALSE): UHS-II is not supported +0x1 (TRUE): UHS-II is supported + 3 1 - read-write + read-only - - - - OP_CTRL - No description avaiable - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - NXT_ADDR - The address for the next command. -It will be processed after CUR_CMD is executed and done.. + DDR50_SUPPORT + DDR50 Support (UHS-I only) +Values: +0x0 (FALSE): DDR50 is not supported +0x1 (TRUE): DDR50 is supported 2 - 30 - read-write + 1 + read-only - NXT_EN - Whether NXT_CMD is enabled. -Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. + SDR104_SUPPORT + SDR104 Support (UHS-I only) +This bit mentions that SDR104 requires tuning. +Values: +0x0 (FALSE): SDR104 is not supported +0x1 (TRUE): SDR104 is supported 1 1 - read-write + read-only - EN - Whether CUR_CMD is enabled. -Asserted to enable the CUR_CMD + SDR50_SUPPORT + SDR50 Support (UHS-I only) +This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. +Values: +0x0 (FALSE): SDR50 is not supported +0x1 (TRUE): SDR50 is supported 0 1 - read-write + read-only - OP_CMD + CURR_CAPABILITIES1 No description avaiable - 0x24 + 0x48 32 0x00000000 - 0x01FFFEFF + 0x00FFFFFF - CONJ_C - asserted to have conjuate value for coefs in computation - 24 - 1 - read-write - - - CMD - The Command Used: -0: FIR -2: FFT -Others: Reserved - 18 - 6 - read-write - - - OUTD_TYPE - Output data type: -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - 15 - 3 - read-write - - - COEF_TYPE - Coef data type (used for FIR): -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - 12 - 3 - read-write + MAX_CUR_18V + Maximum Current for 1.8V +This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 16 + 8 + read-only - IND_TYPE - Input data type: -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - 9 - 3 - read-write + MAX_CUR_30V + Maximum Current for 3.0V +This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA + 8 + 8 + read-only - NXT_CMD_LEN - The length of nxt commands in 32-bit words + MAX_CUR_33V + Maximum Current for 3.3V +This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA 0 8 - read-write + read-only - OP_REG0 + CURR_CAPABILITIES2 No description avaiable - 0x28 + 0x4c 32 0x00000000 - 0xFFFFFFFF + 0x000000FF - CT - Contents + MAX_CUR_VDD2_18V + Maximum Current for 1.8V VDD2 +This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. +0: Get information through another method +1: 4mA +2: 8mA +3: 13mA +....... +255: 1020mA 0 - 32 - read-write + 8 + read-only - OP_FIR_MISC + FORCE_EVENT No description avaiable - 0x28 + 0x50 32 0x00000000 - 0x00003FFF + 0x1FFF00BF - FIR_COEF_TAPS - Length of FIR coefs - 0 - 14 - read-write + FORCE_BOOT_ACK_ERR + Force Event for Boot Ack error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Boot ack Error Status is set + 28 + 1 + write-only - - - - OP_FFT_MISC - No description avaiable - 0x28 - 32 - 0x00000000 - 0x000007FF - - FFT_LEN - FFT length -0:8, -..., -n:2^(3+n) - 7 - 4 - read-write + FORCE_RESP_ERR + Force Event for Response Error (SD Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Response Error Status is set + 27 + 1 + write-only - IFFT - Asserted to indicate IFFT - 6 + FORCE_TUNING_ERR + Force Event for Tuning Error (UHS-I Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Tuning Error Status is set + 26 1 - read-write + write-only - RSV - Reserved. Should be written as zero - 4 - 2 - read-write + FORCE_ADMA_ERR + Force Event for ADMA Error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): ADMA Error Status is set + 25 + 1 + write-only - TMP_BLK - Memory block for indata. Should be assigned as 1 - 2 - 2 - read-write + FORCE_AUTO_CMD_ERR + Force Event for Auto CMD Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Auto CMD Error Status is set + 24 + 1 + write-only - IND_BLK - Memory block for indata. Should be assigned as 0 - 0 - 2 - read-write + FORCE_CUR_LMT_ERR + Force Event for Current Limit Error +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Current Limit Error Status is set + 23 + 1 + write-only - - - - OP_REG1 - No description avaiable - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - CT - Contents - 0 - 32 - read-write + FORCE_DATA_END_BIT_ERR + Force Event for Data End Bit Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data End Bit Error Status is set + 22 + 1 + write-only - - - - OP_FIR_MISC1 - No description avaiable - 0x2c - 32 - 0x00000000 - 0x003FFFFF - - OUTD_MEM_BLK - Should be assigned as 0 - 20 - 2 - read-write + FORCE_DATA_CRC_ERR + Force Event for Data CRC Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data CRC Error Status is set + 21 + 1 + write-only - COEF_MEM_BLK - Should be assigned as 1 - 18 - 2 - read-write + FORCE_DATA_TOUT_ERR + Force Event for Data Timeout Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Data Timeout Error Status is set + 20 + 1 + write-only - IND_MEM_BLK - Should be assigned as 2 - 16 - 2 - read-write + FORCE_CMD_IDX_ERR + Force Event for Command Index Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command Index Error Status is set + 19 + 1 + write-only - FIR_DATA_TAPS - The input data data length - 0 - 16 - read-write + FORCE_CMD_END_BIT_ERR + Force Event for Command End Bit Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command End Bit Error Status is set + 18 + 1 + write-only - - - - OP_REG2 - No description avaiable - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - CT - Contents - 0 - 32 - read-write + FORCE_CMD_CRC_ERR + Force Event for Command CRC Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command CRC Error Status is set + 17 + 1 + write-only - - - - OP_FFT_INRBUF - No description avaiable - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - LOC - The input (real) data buffer pointer - 0 - 32 - read-write + FORCE_CMD_TOUT_ERR + Force Event for Command Timeout Error (SD/eMMC Mode only) +Values: +0x0 (FALSE): Not Affected +0x1 (TRUE): Command Timeout Error Status is set + 16 + 1 + write-only - - - - OP_REG3 - No description avaiable - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - CT - Contents - 0 - 32 - read-write + FORCE_CMD_NOT_ISSUED_AUTO_CMD12 + Force Event for Command Not Issued By Auto CMD12 Error +Values: +0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set +0x0 (FALSE): Not Affected + 7 + 1 + write-only - - - - OP_FIR_INBUF - No description avaiable - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - LOC - The input data buffer pointer - 0 - 32 - read-write + FORCE_AUTO_CMD_RESP_ERR + Force Event for Auto CMD Response Error +Values: +0x1 (TRUE): Auto CMD Response Error Status is set +0x0 (FALSE): Not Affected + 5 + 1 + write-only - - - - OP_REG4 - No description avaiable - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - CT - Contents - 0 - 32 - read-write + FORCE_AUTO_CMD_IDX_ERR + Force Event for Auto CMD Index Error +Values: +0x1 (TRUE): Auto CMD Index Error Status is set +0x0 (FALSE): Not Affected + 4 + 1 + write-only - - - - OP_FIR_COEFBUF - No description avaiable - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - LOC - The coef buf pointer - 0 - 32 - read-write + FORCE_AUTO_CMD_EBIT_ERR + Force Event for Auto CMD End Bit Error +Values: +0x1 (TRUE): Auto CMD End Bit Error Status is set +0x0 (FALSE): Not Affected + 3 + 1 + write-only - - - - OP_FFT_OUTRBUF - No description avaiable - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - LOC - The output (real) data buffer pointer - 0 - 32 - read-write + FORCE_AUTO_CMD_CRC_ERR + Force Event for Auto CMD CRC Error +Values: +0x1 (TRUE): Auto CMD CRC Error Status is set +0x0 (FALSE): Not Affected + 2 + 1 + write-only - - - - OP_REG5 - No description avaiable - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - CT - Contents - 0 - 32 - read-write + FORCE_AUTO_CMD_TOUT_ERR + Force Event for Auto CMD Timeout Error +Values: +0x1 (TRUE): Auto CMD Timeout Error Status is set +0x0 (FALSE): Not Affected + 1 + 1 + write-only - - - - OP_FIR_OUTBUF - No description avaiable - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - LOC - The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） + FORCE_AUTO_CMD12_NOT_EXEC + Force Event for Auto CMD12 Not Executed +Values: +0x1 (TRUE): Auto CMD12 Not Executed Status is set +0x0 (FALSE): Not Affected 0 - 32 - read-write + 1 + write-only - OP_REG6 + ADMA_ERR_STAT No description avaiable - 0x40 + 0x54 32 0x00000000 - 0xFFFFFFFF + 0x00000007 - CT - Contents + ADMA_LEN_ERR + ADMA Length Mismatch Error States +This error occurs in the following instances: +While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length +When the total data length cannot be divided by the block length +Values: +0x0 (NO_ERR): No Error +0x1 (ERROR): Error + 2 + 1 + read-only + + + ADMA_ERR_STATES + ADMA Error States +These bits indicate the state of ADMA when an error occurs during ADMA data transfer. +Values: +0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor +0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor +0x2 (UNUSED): Never set this state +0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor 0 - 32 - read-write + 2 + read-only - OP_REG7 + ADMA_SYS_ADDR No description avaiable - 0x44 + 0x58 32 0x00000000 0xFFFFFFFF - CT - Contents + ADMA_SA + ADMA System Address +These bits indicate the lower 32 bits of the ADMA system address. +SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location +ADMA2: This register stores the byte address of the executing command of the descriptor table +ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. 0 32 read-write - - - - SYSCTL - SYSCTL - SYSCTL - 0xf4000000 - - 0x0 - 0x2c00 - registers - - - RESOURCE_CPU0 - Resource control register for cpu0_core - 0x0 - 32 - 0x00000000 - 0xC0000003 + PRESET_INIT + No description avaiable + 0x60 + 16 + 0x0000 + 0x07FF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. 0 - 2 - read-write + 10 + read-only - RESOURCE_CPX0 - Resource control register for cpu0_subsys - 0x4 - 32 - 0x00000000 - 0xC0000003 + PRESET_DS + No description avaiable + 0x62 + 16 + 0x0000 + 0x07FF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. 0 - 2 - read-write + 10 + read-only - RESOURCE_POW_CPU0 - Resource control register for pow_cpu0 - 0x54 - 32 - 0x00000000 - 0xC0000003 + PRESET_HS + No description avaiable + 0x64 + 16 + 0x0001 + 0x07FF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. 0 - 2 - read-write + 10 + read-only - RESOURCE_RST_SOC - Resource control register for rst_soc - 0x58 - 32 - 0x00000000 - 0xC0000003 + PRESET_SDR12 + No description avaiable + 0x66 + 16 + 0x0000 + 0x07FF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. 0 - 2 - read-write + 10 + read-only - RESOURCE_RST_CPU0 - Resource control register for rst_cpu0 - 0x5c - 32 - 0x00000000 - 0xC0000003 + PRESET_SDR25 + No description avaiable + 0x68 + 16 + 0x0000 + 0x07FF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. 0 - 2 - read-write + 10 + read-only - RESOURCE_CLK_SRC_XTAL - Resource control register for xtal - 0x80 - 32 - 0x00000000 - 0xC0000003 + PRESET_SDR50 + No description avaiable + 0x6a + 16 + 0x0000 + 0x07FF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. 0 - 2 - read-write + 10 + read-only - RESOURCE_CLK_SRC_PLL0 - Resource control register for pll0 - 0x84 - 32 - 0x00000000 - 0xC0000003 + PRESET_SDR104 + No description avaiable + 0x6c + 16 + 0x0000 + 0x07FF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. 0 - 2 - read-write + 10 + read-only - RESOURCE_CLK_SRC_CLK0_PLL0 - Resource control register for clk0_pll0 - 0x88 - 32 - 0x00000000 - 0xC0000003 + PRESET_DDR50 + No description avaiable + 0x6e + 16 + 0x0000 + 0x07FF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 1 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. + 0 + 10 + read-only + + + + + PRESET_UHS2 + No description avaiable + 0x74 + 16 + 0x0000 + 0x07FF + + + CLK_GEN_SEL_VAL + Clock Generator Select Value +This bit is effective when the Host Controller supports a programmable clock generator. +Values: +0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator +0x1 (PROG): Programmable Clock Generator + 10 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + FREQ_SEL_VAL + SDCLK/RCLK Frequency Select Value +10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. 0 - 2 - read-write + 10 + read-only - RESOURCE_CLK_SRC_CLK1_PLL0 - Resource control register for clk1_pll0 - 0x8c + ADMA_ID_ADDR + No description avaiable + 0x78 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + ADMA_ID_ADDR + ADMA Integrated Descriptor Address +These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. +The start address of Integrated Descriptor is set to these register bits. +The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. + 0 + 32 + read-write + + + + P_EMBEDDED_CNTRL + No description avaiable + 0xe6 + 16 + 0x0000 + 0x0FFF + - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 + REG_OFFSET_ADDR + Offset Address of Embedded Control register. + 0 + 12 read-only + + + + P_VENDOR_SPECIFIC_AREA + No description avaiable + 0xe8 + 16 + 0x0000 + 0x0FFF + - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + REG_OFFSET_ADDR + Base offset Address for Vendor-Specific registers. 0 - 2 - read-write + 12 + read-only - RESOURCE_CLK_SRC_CLK2_PLL0 - Resource control register for clk2_pll0 - 0x90 - 32 - 0x00000000 - 0xC0000003 + P_VENDOR2_SPECIFIC_AREA + No description avaiable + 0xea + 16 + 0x0000 + 0xFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 + REG_OFFSET_ADDR + Base offset Address for Command Queuing registers. + 0 + 16 read-only + + + + SLOT_INTR_STATUS + No description avaiable + 0xfc + 16 + 0x0000 + 0x00FF + - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + INTR_SLOT + Interrupt signal for each Slot +These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. +A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. + By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. +Bit 00: Slot 1 +Bit 01: Slot 2 +Bit 02: Slot 3 +.......... +.......... +Bit 07: Slot 8 +Note: MSHC Host Controller support single card slot. This register shall always return 0. 0 - 2 - read-write + 8 + read-only - RESOURCE_CLK_SRC_PLL1 - Resource control register for pll1 - 0x94 + CQVER + No description avaiable + 0x180 32 0x00000000 - 0xC0000003 + 0x00000FFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 + EMMC_VER_MAHOR + This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. + 8 + 4 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 + EMMC_VER_MINOR + This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. + 4 + 4 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + EMMC_VER_SUFFIX + This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. 0 - 2 - read-write + 4 + read-only - RESOURCE_CLK_SRC_CLK0_PLL1 - Resource control register for clk0_pll1 - 0x98 + CQCAP + No description avaiable + 0x184 32 0x00000000 - 0xC0000003 + 0x1000F3FF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + CRYPTO_SUPPORT + Crypto Support +This bit indicates whether the Host Controller supports cryptographic operations. +Values: +0x0 (FALSE): Crypto not Supported +0x1 (TRUE): Crypto Supported + 28 1 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 + ITCFMUL + Internal Timer Clock Frequency Multiplier (ITCFMUL) +This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS +polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. +Values: +0x0 (CLK_1KHz): 1KHz clock +0x1 (CLK_10KHz): 10KHz clock +0x2 (CLK_100KHz): 100KHz clock +0x3 (CLK_1MHz): 1MHz clock +0x4 (CLK_10MHz): 10MHz clock + 12 + 4 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + ITCFVAL + Internal Timer Clock Frequency Value (ITCFVAL) +This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. 0 - 2 - read-write + 10 + read-only - RESOURCE_CLK_SRC_CLK1_PLL1 - Resource control register for clk1_pll1 - 0x9c + CQCFG + No description avaiable + 0x188 32 0x00000000 - 0xC0000003 + 0x00001101 - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + DCMD_EN + This bit indicates to the hardware whether the Task +Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. +Values: +0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor +0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor + 12 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + TASK_DESC_SIZE + Bit Value Description +This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). +Values: +0x1 (TASK_DESC_128b): Task descriptor size is 128 bits +0x0 (TASK_DESC_64b): Task descriptor size is 64 bit + 8 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + CQ_EN + No description avaiable 0 - 2 + 1 read-write - RESOURCE_CLK_SRC_PLL2 - Resource control register for pll2 - 0xa0 + CQCTL + No description avaiable + 0x18c 32 0x00000000 - 0xC0000003 + 0x00000101 - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + CLR_ALL_TASKS + Clear all tasks +This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. +Values: +0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller +0x0 (NO_EFFECT): Programming 0 has no effect + 8 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + HALT + Halt request and resume +Values: +0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. +For example, issuing a Discard Task command (CMDQ_TASK_MGMT). +When the software writes 1, CQE completes the ongoing task (if any in progress). +After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. +The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. +0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity 0 - 2 + 1 read-write - RESOURCE_CLK_SRC_CLK0_PLL2 - Resource control register for clk0_pll2 - 0xa4 + CQIS + No description avaiable + 0x190 32 0x00000000 - 0xC0000003 + 0x0000000F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + TCL + Task cleared interrupt +This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. +The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). +A value of 1 clears this status bit. +Values: +0x1 (SET): TCL Interrupt is set +0x0 (NOTSET): TCL Interrupt is not set + 3 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + RED + Response error detected interrupt +This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status +field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. +A value of 1 clears this status bit. +Values: +0x1 (SET): RED Interrupt is set +0x0 (NOTSET): RED Interrupt is not set + 2 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + TCC + Task complete interrupt +This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: +A task is completed and the INT bit is set in its Task Descriptor +Interrupt caused by Interrupt Coalescing logic due to timeout +Interrupt Coalescing logic reached the configured threshold +A value of 1 clears this status bit + 1 + 1 + read-write + + + HAC + Halt complete interrupt +This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. +A value of 1 clears this status bit. +Values: +0x1 (SET): HAC Interrupt is set +0x0 (NOTSET): HAC Interrupt is not set 0 - 2 + 1 read-write - RESOURCE_CLK_SRC_CLK1_PLL2 - Resource control register for clk1_pll2 - 0xa8 + CQISE + No description avaiable + 0x194 32 0x00000000 - 0xC0000003 + 0x0000000F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + TCL_STE + Task cleared interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.TCL is disabled + 3 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + RED_STE + Response error detected interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.RED is disabled + 2 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + TCC_STE + Task complete interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.TCC is disabled + 1 + 1 + read-write + + + HAC_STE + Halt complete interrupt status enable +Values: +0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active +0x0 (INT_STS_DISABLE): CQIS.HAC is disabled 0 - 2 + 1 read-write - RESOURCE_CLK_SRC_PLL0_REF - Resource control register for pll0 ref clock - 0xac + CQISGE + No description avaiable + 0x198 32 0x00000000 - 0xC0000003 + 0x0000000F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + TCL_SGE + Task cleared interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled + 3 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + RED_SGE + Response error detected interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled + 2 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + TCC_SGE + Task complete interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled + 1 + 1 + read-write + + + HAC_SGE + Halt complete interrupt signal enable +Values: +0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active +0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled 0 - 2 + 1 read-write - RESOURCE_CLK_SRC_PLL1_REF - Resource control register for pll1 ref clock - 0xb0 + CQIC + No description avaiable + 0x19c 32 0x00000000 - 0xC0000003 + 0x80119FFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status + INTC_EN + Interrupt Coalescing Enable Bit +Values: +0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated +0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) 31 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + INTC_STAT + Interrupt Coalescing Status Bit +This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt +coalescing (that is, this is set if and only if INTC counter > 0). +Values: +0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) +0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) + 20 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write + INTC_RST + Counter and Timer Reset +When host driver writes 1, the interrupt coalescing timer and counter are reset. +Values: +0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset +0x0 (NO_EFFECT): No Effect + 16 + 1 + write-only - - - - RESOURCE_CLK_SRC_PLL2_REF - Resource control register for pll2 ref clock - 0xb4 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + INTC_TH_WEN + Interrupt Coalescing Counter Threshold Write Enable +When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. +Values: +0x1 (WEN_SET): Sets INTC_TH_WEN +0x0 (WEN_CLR): Clears INTC_TH_WEN + 15 1 - read-only + write-only + + + INTC_TH + Interrupt Coalescing Counter Threshold filed +Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. +Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. +The counter is reset by software during the interrupt service routine. +The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. +0x0: Interrupt coalescing feature disabled +0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes +0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes +........ +0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes +To write to this field, the INTC_TH_WEN bit must be set during the same write operation. + 8 + 5 + write-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + TOUT_VAL_WEN + When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. +Values: +0x1 (WEN_SET): Sets TOUT_VAL_WEN +0x0 (WEN_CLR): clears TOUT_VAL_WEN + 7 1 - read-only + write-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + TOUT_VAL + Interrupt Coalescing Timeout Value +Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. +Timer Operation: The timer is reset by software during the interrupt service routine. +It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. +When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. +The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. +0x0: Timer is disabled. Timeout-based interrupt is not generated +0x1: Timeout on 01x1024 cycles of timer clock frequency +0x2: Timeout on 02x1024 cycles of timer clock frequency +........ +0x7f: Timeout on 127x1024 cycles of timer clock frequency +In order to write to this field, the TOUT_VAL_WEN bit must +be set at the same write operation. 0 - 2 + 7 read-write - RESOURCE_CLK_TOP_CPU0 - Resource control register for clk_top_cpu0 - 0x100 + CQTDLBA + No description avaiable + 0x1a0 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + TDLBA + This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. +The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. +This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE 0 - 2 + 32 read-write - RESOURCE_CLK_TOP_MCT0 - Resource control register for clk_top_mct0 - 0x104 + CQTDBR + No description avaiable + 0x1a8 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + DBR + The software configures TDLBA and TDLBAU, and enable +CQE in CQCFG before using this register. +Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. +Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. +CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. +CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to +the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. +The corresponding bit is cleared to 0 by CQE in one of the following events: +A task execution is completed (with success or error). +The task is cleared using CQTCLR register. +All tasks are cleared using CQCTL register. +CQE is disabled using CQCFG register. +Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. +In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. +If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. 0 - 2 + 32 read-write - RESOURCE_CLK_TOP_FEMC - Resource control register for clk_top_femc - 0x108 + CQTCN + No description avaiable + 0x1ac 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + TCN + Task Completion Notification +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Task-N has completed execution (with success or errors) +Bit-N(0): Task-N has not completed, could be pending or not submitted. +On task completion, software may read this register to know tasks that have completed. After reading this register, +software may clear the relevant bit fields by writing 1 to the corresponding bits. 0 - 2 + 32 read-write - RESOURCE_CLK_TOP_XPI0 - Resource control register for clk_top_xpi0 - 0x10c + CQDQS + No description avaiable + 0x1b0 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + DQS + Device Queue Status +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Device has marked task N as ready for execution +Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. +Host controller updates this register with response of the Device Queue Status command. 0 - 2 + 32 read-write - RESOURCE_CLK_TOP_XPI1 - Resource control register for clk_top_xpi1 - 0x110 + CQDPT + No description avaiable + 0x1b4 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + DPT + Device-Pending Tasks +Each of the 32 bits are bit mapped to the 32 tasks. +Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution +Bit-N(0): Task-N is not yet queued. +Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. +The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. +Software reads this register in the task-discard procedure to determine if the task is queued in the device 0 - 2 + 32 read-write - RESOURCE_CLK_TOP_TMR0 - Resource control register for clk_top_tmr0 - 0x114 + CQTCLR + No description avaiable + 0x1b8 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + TCLR + Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. +This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. +When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. +CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. +Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. 0 - 2 + 32 read-write - RESOURCE_CLK_TOP_TMR1 - Resource control register for clk_top_tmr1 - 0x118 + CQSSC1 + No description avaiable + 0x1c0 32 0x00000000 - 0xC0000003 + 0x000FFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + SQSCMD_BLK_CNT + This field indicates when SQS CMD is sent while data transfer is in progress. +A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. +0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. +0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. +0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. +0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. +........ +0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. +Should be programmed only when CQCFG.CQ_EN is 0 + 16 + 4 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + SQSCMD_IDLE_TMR + This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. +Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. +When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. +Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. +The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). +For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). +If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. +Should be programmed only when CQCFG.CQ_EN is '0' 0 - 2 + 16 read-write - RESOURCE_CLK_TOP_TMR2 - Resource control register for clk_top_tmr2 - 0x11c + CQSSC2 + No description avaiable + 0x1c4 32 0x00000000 - 0xC0000003 + 0x0000FFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + SQSCMD_RCA + This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. +CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. 0 - 2 + 16 read-write - RESOURCE_CLK_TOP_TMR3 - Resource control register for clk_top_tmr3 - 0x120 + CQCRDCT + No description avaiable + 0x1c8 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + DCMD_RESP + This register contains the response of the command generated by the last direct command (DCMD) task that was sent. +Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. 0 - 2 - read-write + 32 + read-only - RESOURCE_CLK_TOP_URT0 - Resource control register for clk_top_urt0 - 0x124 + CQRMEM + No description avaiable + 0x1d0 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + RESP_ERR_MASK + The bits of this field are bit mapped to the device response. +This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. +1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. +0: When a R1/R1b response is received, bit i in the device status is ignored. +The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. +Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. 0 - 2 + 32 read-write - RESOURCE_CLK_TOP_URT1 - Resource control register for clk_top_urt1 - 0x128 + CQTERRI + No description avaiable + 0x1d4 32 0x00000000 - 0xC0000003 + 0x1F3F9F3F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 + TRANS_ERR_TASKID + This field captures the ID of the task that was executed and whose data transfer has errors. + 24 + 5 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + TRANS_ERR_CMD_INDX + This field captures the index of the command that was executed and whose data transfer has errors. + 16 + 6 + read-only + + + RESP_ERR_FIELDS_VALID + This bit is updated when an error is detected while a command transaction was in progress. +Values: +0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields +0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX + 15 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + RESP_ERR_TASKID + This field captures the ID of the task which was executed on the command line when the error occurred. + 8 + 5 + read-only + + + RESP_ERR_CMD_INDX + This field captures the index of the command that was executed on the command line when the error occurred 0 - 2 - read-write + 6 + read-only - RESOURCE_CLK_TOP_URT2 - Resource control register for clk_top_urt2 - 0x12c + CQCRI + No description avaiable + 0x1d8 32 0x00000000 - 0xC0000003 + 0x0000003F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + CMD_RESP_INDX + Last Command Response index +This field stores the index of the last received command response. Controller updates the value every time a command response is received 0 - 2 - read-write + 6 + read-only - RESOURCE_CLK_TOP_URT3 - Resource control register for clk_top_urt3 - 0x130 + CQCRA + No description avaiable + 0x1dc 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 + CMD_RESP_ARG + Last Command Response argument +This field stores the argument of the last received command response. Controller updates the value every time a command response is received. + 0 + 32 read-only + + + + MSHC_VER_ID + No description avaiable + 0x500 + 32 + 0x00000000 + 0xFFFFFFFF + - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 + VER_ID + No description avaiable + 0 + 32 read-only + + + + MSHC_VER_TYPE + No description avaiable + 0x504 + 32 + 0x00000000 + 0xFFFFFFFF + - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + VER_TYPE + No description avaiable 0 - 2 - read-write + 32 + read-only - RESOURCE_CLK_TOP_URT4 - Resource control register for clk_top_urt4 - 0x134 + MBIU_CTRL + Y + 0x510 32 0x00000000 - 0xC0000003 + 0x0000000F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + BURST_INCR16_EN + No description avaiable + 3 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + BURST_INCR8_EN + No description avaiable + 2 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + BUSRT_INCR4_EN + No description avaiable + 1 + 1 + read-write + + + UNDEFL_INCR_EN + No description avaiable 0 - 2 + 1 read-write - RESOURCE_CLK_TOP_URT5 - Resource control register for clk_top_urt5 - 0x138 + EMMC_BOOT_CTRL + No description avaiable + 0x52c 32 0x00000000 - 0xC0000003 + 0xF181070F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + BOOT_TOUT_CNT + Boot Ack Timeout Counter Value. +This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. +0xF : Reserved +0xE : TMCLK x 2^27 + ............ +0x1 : TMCLK x 2^14 +0x0 : TMCLK x 2^13 + 28 + 4 + read-write + + + BOOT_ACK_ENABLE + Boot Acknowledge Enable +When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. +Values: +0x1 (TRUE): Boot Ack enable +0x0 (FALSE): Boot Ack disable + 24 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + VALIDATE_BOOT + Validate Mandatory Boot Enable bit +This bit is used to validate the MAN_BOOT_EN bit. +Values: +0x1 (TRUE): Validate Mandatory boot enable bit +0x0 (FALSE): Ignore Mandatory boot Enable bit + 23 1 - read-only + write-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + MAN_BOOT_EN + Mandatory Boot Enable +This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. +Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. +Values: +0x1 (MAN_BOOT_EN): Mandatory boot enable +0x0 (MAN_BOOT_DIS): Mandatory boot disable + 16 + 1 read-write - - - - RESOURCE_CLK_TOP_URT6 - Resource control register for clk_top_urt6 - 0x13c - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + CQE_PREFETCH_DISABLE + Enable or Disable CQE's PREFETCH feature +This field allows Software to disable CQE's data prefetch feature when set to 1. +Values: +0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers +0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled + 10 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + CQE_ALGO_SEL + Scheduler algorithm selected for execution +This bit selects the Algorithm used for selecting one of the many ready tasks for execution. +Values: +0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks +0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings + 9 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + ENH_STROBE_ENABLE + Enhanced Strobe Enable +This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. +Values: +0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode +0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode + 8 + 1 read-write - - - - RESOURCE_CLK_TOP_URT7 - Resource control register for clk_top_urt7 - 0x140 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + EMMC_RST_N_OE + Output Enable control for EMMC Device Reset signal PAD +control. +This field drived sd_rst_n_oe output of SDXC +Values: +0x1 (ENABLE): sd_rst_n_oe is 1 +0x0 (DISABLE): sd_rst_n_oe is 0 + 3 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + EMMC_RST_N + EMMC Device Reset signal control. +This register field controls the sd_rst_n output of SDXC +Values: +0x1 (RST_DEASSERT): Reset to eMMC device is deasserted +0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) + 2 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + DISABLE_DATA_CRC_CHK + Disable Data CRC Check +This bit controls masking of CRC16 error for Card Write in eMMC mode. +This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, +which may generate CRC error. This CRC error can be masked using this bit during bus testing. +Values: +0x1 (DISABLE): DATA CRC check is disabled +0x0 (ENABLE): DATA CRC check is enabled + 1 + 1 + read-write + + + CARD_IS_EMMC + eMMC Card present +This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. +Values: +0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card +0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card 0 - 2 + 1 read-write - RESOURCE_CLK_TOP_I2C0 - Resource control register for clk_top_i2c0 - 0x144 + AUTO_TUNING_CTRL + No description avaiable + 0x540 32 0x00000000 - 0xC0000003 + 0x7F1F0F1F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + SWIN_TH_VAL + Sampling window threshold value setting +The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps +can use values from 0x0 to 0x1F. +This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' +0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. +0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. +0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. +........ +0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. + 24 + 7 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + POST_CHANGE_DLY + Time taken for phase switching and stable clock output. +Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. +Values: +0x0 (LATENCY_LT_1): Less than 1-cycle latency +0x1 (LATENCY_LT_2): Less than 2-cycle latency +0x2 (LATENCY_LT_3): Less than 3-cycle latency +0x3 (LATENCY_LT_4): Less than 4-cycle latency + 19 + 2 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 + PRE_CHANGE_DLY + Maximum Latency specification between cclk_tx and cclk_rx. +Values: +0x0 (LATENCY_LT_1): Less than 1-cycle latency +0x1 (LATENCY_LT_2): Less than 2-cycle latency +0x2 (LATENCY_LT_3): Less than 3-cycle latency +0x3 (LATENCY_LT_4): Less than 4-cycle latency + 17 2 read-write - - - - RESOURCE_CLK_TOP_I2C1 - Resource control register for clk_top_i2c1 - 0x148 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + TUNE_CLK_STOP_EN + Clock stopping control for Tuning and auto-tuning circuit. +When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. +This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. + Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. +Values: +0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change +0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching + 16 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + WIN_EDGE_SEL + This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. +0x0: User selection disabled. Tuning calculated edges are used. +0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. +0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess +... +0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. + 8 + 4 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + SW_TUNE_EN + This fields enables software-managed tuning flow. +Values: +0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AT_STAT_R.CENTER_PH_CODE Field is now writable. +0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled + 4 + 1 read-write - - - - RESOURCE_CLK_TOP_I2C2 - Resource control register for clk_top_i2c2 - 0x14c - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + RPT_TUNE_ERR + Framing errors are not generated when executing tuning. +This debug bit allows users to report these errors. +Values: +0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors +0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. + 3 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + SWIN_TH_EN + Sampling window Threshold enable +Selects the tuning mode +Field should be programmed only when SAMPLE_CLK_SEL is '0' +Values: +0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold +set by SWIN_TH_VAL field +0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window + 2 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + CI_SEL + Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. +Values: +0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval +0x1 (WHEN_IN_IDLE): Driven at the end of the transfer + 1 + 1 + read-write + + + AT_EN + Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. +Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. +This field should be programmed only when CLK_CTRL_R.SD_CLK_EN is 0. +Values: +0x1 (AT_ENABLE): AutoTuning is enabled +0x0 (AT_DISABLE): AutoTuning is disabled 0 - 2 + 1 read-write - RESOURCE_CLK_TOP_I2C3 - Resource control register for clk_top_i2c3 - 0x150 + AUTO_TUNING_STAT + No description avaiable + 0x544 32 0x00000000 - 0xC0000003 + 0x00FFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 + L_EDGE_PH_CODE + Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. + 16 + 8 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 + R_EDGE_PH_CODE + Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. + 8 + 8 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + CENTER_PH_CODE + Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AT_CTRL_R.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel 0 - 2 + 8 read-write - RESOURCE_CLK_TOP_SPI0 - Resource control register for clk_top_spi0 - 0x154 + MISC_CTRL0 + No description avaiable + 0x3000 32 0x00000000 - 0xC0000003 + 0x10020FFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + CARDCLK_INV_EN + set to invert card_clk, for slow speed card to meet 5ns setup timing. +May cause glitch on clock, should be set before enable clk(in core cfg) + 28 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + PAD_CLK_SEL_B + set to use internal clock directly, may have timing issue; +clr to use clock loopback from pad. + 17 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + FREQ_SEL_SW_EN + set to use FREQ_SEL_SW as card clock divider; +clear to use core logic as clock divider. + 11 + 1 + read-write + + + TMCLK_EN + set to force enable tmclk; +clear to use core signal intclk_en to control it + 10 + 1 + read-write + + + FREQ_SEL_SW + software card clock divider, it will be used only when FREQ_SEL_SW_EN is set 0 - 2 + 10 read-write - RESOURCE_CLK_TOP_SPI1 - Resource control register for clk_top_spi1 - 0x158 + MISC_CTRL1 + No description avaiable + 0x3004 32 0x00000000 - 0xC0000003 + 0xB0000000 - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status + CARD_ACTIVE + SW write 1 to start card clock delay counter(delay time is configed by CARD_ACTIVE_PERIOD_SEL). +When counter finished, this bit will be cleared by hardware. +Write 1 when this bit is 1 will cause unknown result(actually no use except write at exact finish time) 31 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 + CARD_ACTIVE_PERIOD_SEL + card clock delay config. +00 for 100 cycle; 01 for 74 cycle; 10 for 128 cycle; 11 for 256 cycle + 28 2 read-write + + + + I2C0 + I2C0 + I2C + 0xf3020000 + + 0x0 + 0x34 + registers + + - RESOURCE_CLK_TOP_SPI2 - Resource control register for clk_top_spi2 - 0x15c + CFG + Configuration Register + 0x10 32 - 0x00000000 - 0xC0000003 + 0x00000001 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + RESERVED + No description avaiable + 2 + 30 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + FIFOSIZE + FIFO Size: +0: 2 bytes +1: 4 bytes +2: 8 bytes +3: 16 bytes 0 2 - read-write + read-only - RESOURCE_CLK_TOP_SPI3 - Resource control register for clk_top_spi3 - 0x160 + INTEN + Interrupt Enable Register + 0x14 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + RESERVED + No description avaiable + 10 + 22 + read-write + + + CMPL + Set to enable the Completion Interrupt. +Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. +Slave: interrupts when a transaction addressing the controller is completed. + 9 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + BYTERECV + Set to enable the Byte Receive Interrupt. +Interrupts when a byte of data is received +Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. + 8 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + BYTETRANS + Set to enable the Byte Transmit Interrupt. +Interrupts when a byte of data is transmitted. + 7 + 1 read-write - - - - RESOURCE_CLK_TOP_CAN0 - Resource control register for clk_top_can0 - 0x164 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + START + Set to enable the START Condition Interrupt. +Interrupts when a START condition/repeated START condition is detected. + 6 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + STOP + Set to enable the STOP Condition Interrupt +Interrupts when a STOP condition is detected. + 5 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + ARBLOSE + Set to enable the Arbitration Lose Interrupt. +Master: interrupts when the controller loses the bus arbitration +Slave: not available in this mode. + 4 + 1 read-write - - - - RESOURCE_CLK_TOP_CAN1 - Resource control register for clk_top_can1 - 0x168 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + ADDRHIT + Set to enable the Address Hit Interrupt. +Master: interrupts when the addressed slave returned an ACK. +Slave: interrupts when the controller is addressed. + 3 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + FIFOHALF + Set to enable the FIFO Half Interrupt. +Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. +Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. +This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. + 2 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + FIFOFULL + Set to enable the FIFO Full Interrupt. +Interrupts when the FIFO is full. + 1 + 1 + read-write + + + FIFOEMPTY + Set to enabled the FIFO Empty Interrupt +Interrupts when the FIFO is empty. 0 - 2 + 1 read-write - RESOURCE_CLK_TOP_PTPC - Resource control register for clk_top_ptpc - 0x16c + STATUS + Status Register + 0x18 32 - 0x00000000 - 0xC0000003 + 0x00000001 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + RESERVED + No description avaiable + 15 + 17 + read-write + + + LINESDA + Indicates the current status of the SDA line on the bus +1: high +0: low + 14 1 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + LINESCL + Indicates the current status of the SCL line on the bus +1: high +0: low + 13 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write + GENCALL + Indicates that the address of the current transaction is a general call address: +1: General call +0: Not general call + 12 + 1 + read-only - - - - RESOURCE_CLK_TOP_ANA0 - Resource control register for clk_top_ana0 - 0x170 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + BUSBUSY + Indicates that the bus is busy +The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus +1: Busy +0: Not busy + 11 1 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + ACK + Indicates the type of the last received/transmitted acknowledgement bit: +1: ACK +0: NACK + 10 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write + CMPL + Transaction Completion +Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration +Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. + 9 + 1 + write-only - - - - RESOURCE_CLK_TOP_ANA1 - Resource control register for clk_top_ana1 - 0x174 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + BYTERECV + Indicates that a byte of data has been received. + 8 1 - read-only + write-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + BYTETRANS + Indicates that a byte of data has been transmitted. + 7 1 - read-only + write-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write + START + Indicates that a START Condition or a repeated START condition has been transmitted/received. + 6 + 1 + write-only + + + STOP + Indicates that a STOP Condition has been transmitted/received. + 5 + 1 + write-only + + + ARBLOSE + Indicates that the controller has lost the bus arbitration. + 4 + 1 + write-only + + + ADDRHIT + Master: indicates that a slave has responded to the transaction. +Slave: indicates that a transaction is targeting the controller (including the General Call). + 3 + 1 + write-only - - - - RESOURCE_CLK_TOP_ANA2 - Resource control register for clk_top_ana2 - 0x178 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + FIFOHALF + Transmitter: Indicates that the FIFO is half-empty. + 2 1 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + FIFOFULL + Indicates that the FIFO is full. + 1 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + FIFOEMPTY + Indicates that the FIFO is empty. 0 - 2 - read-write + 1 + read-only - RESOURCE_CLK_TOP_ANA3 - Resource control register for clk_top_ana3 - 0x17c + ADDR + Address Register + 0x1c 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + RESERVED + No description avaiable + 10 + 22 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + ADDR + The slave address. +For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid 0 - 2 + 10 read-write - RESOURCE_CLK_TOP_AUD0 - Resource control register for clk_top_aud0 - 0x180 + DATA + Data Register + 0x20 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + RESERVED + No description avaiable + 8 + 24 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + DATA + Write this register to put one byte of data to the FIFO. +Read this register to get one byte of data from the FIFO. 0 - 2 + 8 read-write - RESOURCE_CLK_TOP_AUD1 - Resource control register for clk_top_aud1 - 0x184 + CTRL + Control Register + 0x24 32 - 0x00000000 - 0xC0000003 + 0x00001E00 + 0x000F9FFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + RESERVED + No description avaiable + 15 + 5 + read-write + + + PHASE_START + Enable this bit to send a START condition at the beginning of transaction. +Master mode only. + 12 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + PHASE_ADDR + Enable this bit to send the address after START condition. +Master mode only. + 11 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + PHASE_DATA + Enable this bit to send the data after Address phase. +Master mode only. + 10 + 1 read-write - - - - RESOURCE_CLK_TOP_ETH0 - Resource control register for clk_top_eth0 - 0x188 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + PHASE_STOP + Enable this bit to send a STOP condition at the end of a transaction. +Master mode only. + 9 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + DIR + Transaction direction +Master: Set this bit to determine the direction for the next transaction. +0: Transmitter +1: Receiver +Slave: The direction of the last received transaction. +0: Receiver +1: Transmitter + 8 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + DATACNT + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. 0 - 2 + 8 read-write - RESOURCE_CLK_TOP_PTP0 - Resource control register for clk_top_ptp0 - 0x18c + CMD + Command Register + 0x28 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + RESERVED + No description avaiable + 3 + 29 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + CMD + Write this register with the following values to perform the corresponding actions: +0x0: no action +0x1: issue a data transaction (Master only) +0x2: respond with an ACK to the received byte +0x3: respond with a NACK to the received byte +0x4: clear the FIFO +0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) +When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. +Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. 0 - 2 + 3 read-write - RESOURCE_CLK_TOP_REF0 - Resource control register for clk_top_ref0 - 0x190 + SETUP + Setup Register + 0x2c 32 - 0x00000000 - 0xC0000003 + 0x05252100 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + RESERVED + No description avaiable + 29 + 3 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + T_SUDAT + T_SUDAT defines the data setup time before releasing the SCL. +Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) +tpclk = PCLK period +TPM = The multiplier value in Timing Parameter Multiplier Register + 24 + 5 read-write - - - - RESOURCE_CLK_TOP_REF1 - Resource control register for clk_top_ref1 - 0x194 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + T_SP + T_SP defines the pulse width of spikes that must be suppressed by the input filter. +Pulse width = T_SP * tpclk* (TPM+1) + 21 + 3 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + T_HDDAT + T_HDDAT defines the data hold time after SCL goes LOW +Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) + 16 + 5 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 + RESERVED + No description avaiable + 14 2 read-write - - - - RESOURCE_CLK_TOP_NTM0 - Resource control register for clk_top_ntm0 - 0x198 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + T_SCLRADIO + The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. +SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) +1: ratio = 2 +0: ratio = 1 +This field is only valid when the controller is in the master mode. + 13 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + T_SCLHI + The HIGH period of generated SCL clock is defined by T_SCLHi. +SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) +The T_SCLHi value must be greater than T_SP and T_HDDAT values. +This field is only valid when the controller is in the master mode. + 4 + 9 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + DMAEN + Enable the direct memory access mode data transfer. +1: Enable +0: Disable + 3 + 1 read-write - - - - RESOURCE_CLK_TOP_SDC0 - Resource control register for clk_top_sdc0 - 0x19c - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + MASTER + Configure this device as a master or a slave. +1: Master mode +0: Slave mode + 2 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + ADDRESSING + I2C addressing mode: +1: 10-bit addressing mode +0: 7-bit addressing mode + 1 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + IICEN + Enable the I2C controller. +1: Enable +0: Disable 0 - 2 + 1 read-write - RESOURCE_CLK_TOP_ADC0 - Resource control register for clk_top_adc0 - 0x200 + TPM + I2C Timing Paramater Multiplier + 0x30 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + RESERVED + No description avaiable + 5 + 27 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + TPM + A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). 0 - 2 + 5 read-write + + + + I2C1 + I2C1 + I2C + 0xf3024000 + + + I2C2 + I2C2 + I2C + 0xf3028000 + + + I2C3 + I2C3 + I2C + 0xf302c000 + + + SDP + SDP + SDP + 0xf304c000 + + 0x0 + 0x60 + registers + + - RESOURCE_CLK_TOP_ADC1 - Resource control register for clk_top_adc1 - 0x204 + SDPCR + SDP control register + 0x0 32 - 0x00000000 - 0xC0000003 + 0x30000000 + 0xFFFE0101 - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status + SFTRST + soft reset. +Write 1 then 0, to reset the SDP block. 31 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status + CLKGAT + Clock Gate for the SDP main logic. +Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. 30 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 read-write - - - - RESOURCE_CLK_TOP_ADC2 - Resource control register for clk_top_adc2 - 0x208 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + CIPDIS + Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. +1, Cipher is disabled in this chip. +0, Cipher is enabled in this chip. + 29 1 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + HASDIS + HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. +1, HASH is disabled in this chip. +0, HASH is enabled in this chip. + 28 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write + RESERVED + Not used + 24 + 4 + read-only - - - - RESOURCE_CLK_TOP_DAC0 - Resource control register for clk_top_dac0 - 0x20c - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + CIPHEN + Cipher Enablement, controlled by SW. +1, Cipher is Enabled. +0, Cipher is Disabled. + 23 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + HASHEN + HASH Enablement, controlled by SW. +1, HASH is Enabled. +0, HASH is Disabled. + 22 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + MCPEN + Memory Copy Enablement, controlled by SW. +1, Memory copy is Enabled. +0, Memory copy is Disabled. + 21 + 1 read-write - - - - RESOURCE_CLK_TOP_I2S0 - Resource control register for clk_top_i2s0 - 0x210 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + CONFEN + Constant Fill to memory, controlled by SW. +1, Constant fill is Enabled. +0, Constant fill is Disabled. + 20 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + DCRPDI + Decryption Disable bit, Write to 1 to disable the decryption. + 19 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + RESERVED + Reserved + 18 + 1 read-write - - - - RESOURCE_CLK_TOP_I2S1 - Resource control register for clk_top_i2s1 - 0x214 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + TSTPKT0IRQ + Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. + 17 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + RDSCEN + when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) +when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) + 8 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + INTEN + Interrupt Enablement, controlled by SW. +1, SDP interrupt is enabled. +0, SDP interrupt is disabled. 0 - 2 + 1 read-write - RESOURCE_AHBP - Resource control register for ahbapb_bus - 0x400 + MODCTRL + Mod control register. + 0x4 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + AESALG + AES algorithem selection. +0x0 = AES 128; +0x1 = AES 256; +0x8 = SM4； +Others, reserved. + 28 + 4 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + AESMOD + AES mode selection. +0x0 = ECB; +0x1 = CBC; +Others, reserved. + 24 + 4 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + AESKS + AES Key Selection. +These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: +0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. +0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +.... +0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. +0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. +0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. +0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. +0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. +0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. +0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. +0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. +0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. +0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. +0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. +0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. +0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. +Other values, reserved. + 18 + 6 read-write - - - - RESOURCE_AXIS - Resource control register for soc_bus - 0x404 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + RESERVED + Not used + 17 1 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + AESDIR + AES direction +1x1, AES Decryption +1x0, AES Encryption. + 16 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + HASALG + HASH Algorithem selection. +0x0 SHA1 — +0x1 CRC32 — +0x2 SHA256 — + 12 + 4 read-write - - - - RESOURCE_AXIC - Resource control register for conn_bus - 0x408 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + CRCEN + CRC enable. +1x1, CRC is enabled. +1x0, CRC is disabled. + 11 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + HASCHK + HASH Check Enable Bit. +1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; +1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. +For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. + 10 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + HASOUT + When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. +0 INPUT HASH +1 OUTPUT HASH + 9 + 1 read-write - - - - RESOURCE_FEMC - Resource control register for femc - 0x40c - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + RESERVED + Not used + 8 1 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 + RESERVED + Not used + 6 + 2 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + DINSWP + Decide whether the SDP byteswaps the input data (big-endian data); +When all bits are set, the data is assumed to be in the big-endian format + 4 + 2 + read-write + + + DOUTSWP + Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format + 2 + 2 + read-write + + + KEYSWP + Decide whether the SDP byteswaps the Key (big-endian data). +When all bits are set, the data is assumed to be in the big-endian format 0 2 read-write @@ -61530,272 +53086,207 @@ n:2^(3+n) - RESOURCE_ROM0 - Resource control register for rom - 0x410 + PKTCNT + packet counter registers. + 0x8 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status + RESERVED + Not used 31 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status + RESERVED + Not used 30 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write + RESERVED + Not used + 24 + 6 + read-only - - - - RESOURCE_LMM0 - Resource control register for lmm0 - 0x414 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 + CNTVAL + This read-only field shows the current (instantaneous) value of the packet counter + 16 + 8 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 + RESERVED + Not used + 8 + 8 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + CNTINCR + The value written to this field is added to the spacket count. 0 - 2 + 8 read-write - RESOURCE_RAM0 - Resource control register for axi_sram - 0x418 + STA + Status Registers + 0xc 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 + TAG + packet tag. + 24 + 8 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + IRQ + interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. + 23 1 - read-only + write-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 + RESERVED + Not used + 21 2 - read-write + read-only - - - - RESOURCE_MCT0 - Resource control register for mchtmr0 - 0x41c - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + CHN1PKT0 + the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. + 20 + 1 + write-only + + + AESBSY + AES Busy + 19 1 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + HASBSY + Hashing Busy + 18 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write + PKTCNT0 + Packet Counter registers reachs to ZERO now. + 17 + 1 + write-only - - - - RESOURCE_XPI0 - Resource control register for xpi0 - 0x420 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + PKTDON + Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. + 16 1 + write-only + + + RESERVED + Not used + 6 + 10 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + ERRSET + Working mode setup error. + 5 1 - read-only + write-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write + ERRPKT + Packet head access error, or status update error. + 4 + 1 + write-only - - - - RESOURCE_XPI1 - Resource control register for xpi1 - 0x424 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + ERRSRC + Source Buffer Access Error + 3 1 - read-only + write-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + ERRDST + Destination Buffer Error + 2 1 - read-only + write-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + ERRHAS + Hashing Check Error + 1 + 1 + write-only + + + ERRCHAIN + buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. 0 - 2 - read-write + 1 + write-only - RESOURCE_SDP0 - Resource control register for sdp - 0x428 + KEYADDR + Key Address + 0x10 32 - 0x00000000 - 0xC0000003 + 0x00000040 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 + RESERVED + Not used + 24 + 8 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 + INDEX + To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. +Key index pointer. The valid indices are 0-[number_keys]. +In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. + 16 + 8 + read-write + + + RESERVED + Not used + 2 + 14 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + SUBWRD + Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field +increments; To write a key, the software must first write the desired key index/subword to this register. 0 2 read-write @@ -61803,1169 +53294,914 @@ n:2^(3+n) - RESOURCE_RNG0 - Resource control register for rng - 0x42c + KEYDAT + Key Data + 0x14 32 - 0x00000000 - 0xC0000003 + 0x00000030 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + KEYDAT + This register provides the write access to the key/key subword specified by the key index register. +Writing this location updates the selected subword for the key located at the index +specified by the key index register. The write also triggers the SUBWORD field of the +KEY register to increment to the next higher word in the key 0 - 2 + 32 read-write - RESOURCE_KMAN - Resource control register for keym - 0x430 + CIPHIV_CIPHIV0 + Cipher Initializtion Vector 0 + 0x18 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + CIPHIV + cipher initialization vector. 0 - 2 + 32 read-write - RESOURCE_DMA0 - Resource control register for hdma - 0x434 + CIPHIV_CIPHIV1 + Cipher Initializtion Vector 1 + 0x1c 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + CIPHIV + cipher initialization vector. 0 - 2 + 32 read-write - RESOURCE_DMA1 - Resource control register for xdma - 0x438 + CIPHIV_CIPHIV2 + Cipher Initializtion Vector 2 + 0x20 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + CIPHIV + cipher initialization vector. 0 - 2 + 32 read-write - RESOURCE_FFA0 - Resource control register for ffa - 0x43c + CIPHIV_CIPHIV3 + Cipher Initializtion Vector 3 + 0x24 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + HASWRD_HASWRD0 + Hash Data Word 0 + 0x28 + 32 + 0x00000030 + 0xFFFFFFFF + - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + HASWRD_HASWRD1 + Hash Data Word 1 + 0x2c + 32 + 0x00000030 + 0xFFFFFFFF + - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. 0 - 2 + 32 read-write - RESOURCE_GPIO - Resource control register for gpio - 0x440 + HASWRD_HASWRD2 + Hash Data Word 2 + 0x30 32 - 0x00000000 - 0xC0000003 + 0x00000030 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + HASWRD_HASWRD3 + Hash Data Word 3 + 0x34 + 32 + 0x00000030 + 0xFFFFFFFF + - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + HASWRD_HASWRD4 + Hash Data Word 4 + 0x38 + 32 + 0x00000030 + 0xFFFFFFFF + - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. 0 - 2 + 32 read-write - RESOURCE_MBX0 - Resource control register for mbx - 0x444 + HASWRD_HASWRD5 + Hash Data Word 5 + 0x3c 32 - 0x00000000 - 0xC0000003 + 0x00000030 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. 0 - 2 + 32 read-write - RESOURCE_WDG0 - Resource control register for wdg0 - 0x448 + HASWRD_HASWRD6 + Hash Data Word 6 + 0x40 32 - 0x00000000 - 0xC0000003 + 0x00000030 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. 0 - 2 + 32 read-write - RESOURCE_WDG1 - Resource control register for wdg1 - 0x44c + HASWRD_HASWRD7 + Hash Data Word 7 + 0x44 32 - 0x00000000 - 0xC0000003 + 0x00000030 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. 0 - 2 + 32 read-write - RESOURCE_TSNS - Resource control register for tsns - 0x450 + CMDPTR + Command Pointer + 0x48 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + CMDPTR + current command addresses the register points to the multiword +descriptor that is to be executed (or is currently being executed) 0 - 2 + 32 read-write - RESOURCE_TMR0 - Resource control register for tmr0 - 0x454 + NPKTPTR + Next Packet Address Pointer + 0x4c 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + NPKTPTR + Next Packet Address Pointer 0 - 2 + 32 read-write - RESOURCE_TMR1 - Resource control register for tmr1 - 0x458 + PKTCTL + Packet Control Registers + 0x50 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + PKTTAG + packet tag + 24 + 8 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + RESERVED + Not used + 7 + 17 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + CIPHIV + Load Initial Vector for the AES in this packet. + 6 + 1 read-write - - - - RESOURCE_TMR2 - Resource control register for tmr2 - 0x45c - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + HASFNL + Hash Termination packet + 5 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + HASINI + Hash Initialization packat + 4 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + CHAIN + whether the next command pointer register must be loaded into the channel's current descriptor +pointer. + 3 + 1 read-write - - - - RESOURCE_TMR3 - Resource control register for tmr3 - 0x460 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + DCRSEMA + whether the channel's semaphore must be decremented at the end of the current operation. +When the semaphore reaches a value of zero, no more operations are issued from the channel. + 2 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + PKTINT + Reflects whether the channel must issue an interrupt upon the completion of the packet + 1 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + RESERVED + Not used 0 - 2 + 1 read-write - RESOURCE_URT0 - Resource control register for uart0 - 0x464 + PKTSRC + Packet Memory Source Address + 0x54 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + PKTSRC + Packet Memory Source Address 0 - 2 + 32 read-write - RESOURCE_URT1 - Resource control register for uart1 - 0x468 + PKTDST + Packet Memory Destination Address + 0x58 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + PKTDST + Packet Memory Destination Address 0 - 2 + 32 read-write - RESOURCE_URT2 - Resource control register for uart2 - 0x46c + PKTBUF + Packet buffer size. + 0x5c 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + PKTBUF + No description avaiable 0 - 2 + 32 read-write + + + + FEMC + FEMC + FEMC + 0xf3050000 + + 0x0 + 0x154 + registers + + - RESOURCE_URT3 - Resource control register for uart3 - 0x470 + CTRL + Control Register + 0x0 32 0x00000000 - 0xC0000003 + 0x1FFF0007 - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + BTO + Bus timeout cycles +AXI Bus timeout cycle is as following (255*(2^BTO)): +00000b - 255*1 +00001-11110b - 255*2 - 255*2^30 +11111b - 255*2^31 + 24 + 5 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + CTO + Command Execution timeout cycles +When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is +generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is +CTO*1024 cycle. + 16 + 8 read-write - - - - RESOURCE_URT4 - Resource control register for uart4 - 0x474 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + DQS + DQS (read strobe) mode +0b - Dummy read strobe loopbacked internally +1b - Dummy read strobe loopbacked from DQS pad + 2 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + DIS + Module Disable +0b - Module enabled +1b - Module disabled + 1 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + RST + Software Reset +Reset all internal logic in SEMC except configuration register 0 - 2 + 1 read-write - RESOURCE_URT5 - Resource control register for uart5 - 0x478 + IOCTRL + IO Mux Control Register + 0x4 32 0x00000000 - 0xC0000003 + 0x000000F0 - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + IO_CSX + IO_CSX output selection +0001b - SDRAM CS1 +0110b - SRAM CE# + 4 + 4 read-write - RESOURCE_URT6 - Resource control register for uart6 - 0x47c + BMW0 + Bus (AXI) Weight Control Register 0 + 0x8 32 0x00000000 - 0xC0000003 + 0x00FFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + RWS + Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is +same as current executing command with read/write operation switch. + 16 + 8 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + SH + Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is +same as current executing command without read/write operation switch. + 8 + 8 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + AGE + Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is +multiplied by WAGE to get weight score. + 4 + 4 + read-write + + + QOS + Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator +for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS +is multiplied by WQOS to get weight score. 0 - 2 + 4 read-write - RESOURCE_URT7 - Resource control register for uart7 - 0x480 + BMW1 + Bus (AXI) Weight Control Register 1 + 0xc 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + BR + Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current +executing command. + 24 + 8 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + RWS + Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is +same as current executing command with read/write operation switch. + 16 + 8 read-write - - - - RESOURCE_I2C0 - Resource control register for i2c0 - 0x484 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + PH + Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is +same as current executing command without read/write operation switch. + 8 + 8 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + AGE + Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is +multiplied by WAGE to get weight score. + 4 + 4 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + QOS + Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator +for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS +is multiplied by WQOS to get weight score. 0 - 2 + 4 read-write - RESOURCE_I2C1 - Resource control register for i2c1 - 0x488 + BR_BASE0 + Base Register 0 (for SDRAM CS0 device) + 0x10 32 0x00000000 - 0xC0000003 + 0xFFFFF03F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + BASE + Base Address +This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low +position 12 bits are all zero. + 12 + 20 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + SIZE + Memory size +00000b - 4KB +00001b - 8KB +00010b - 16KB +00011b - 32KB +00100b - 64KB +00101b - 128KB +00110b - 256KB +00111b - 512KB +01000b - 1MB +01001b - 2MB +01010b - 4MB +01011b - 8MB +01100b - 16MB +01101b - 32MB +01110b - 64MB +01111b - 128MB +10000b - 256MB +10001b - 512MB +10010b - 1GB +10011b - 2GB +10100-11111b - 4GB + 1 + 5 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + VLD + Valid 0 - 2 + 1 read-write - RESOURCE_I2C2 - Resource control register for i2c2 - 0x48c + BR_BASE1 + Base Register 1 (for SDRAM CS1 device) + 0x14 32 0x00000000 - 0xC0000003 + 0xFFFFF03F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + BASE + Base Address +This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low +position 12 bits are all zero. + 12 + 20 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + SIZE + Memory size +00000b - 4KB +00001b - 8KB +00010b - 16KB +00011b - 32KB +00100b - 64KB +00101b - 128KB +00110b - 256KB +00111b - 512KB +01000b - 1MB +01001b - 2MB +01010b - 4MB +01011b - 8MB +01100b - 16MB +01101b - 32MB +01110b - 64MB +01111b - 128MB +10000b - 256MB +10001b - 512MB +10010b - 1GB +10011b - 2GB +10100-11111b - 4GB + 1 + 5 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + VLD + Valid 0 - 2 + 1 read-write - RESOURCE_I2C3 - Resource control register for i2c3 - 0x490 + BR_BASE6 + Base Register 6 (for SRAM device) + 0x28 32 0x00000000 - 0xC0000003 + 0xFFFFF03F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + BASE + Base Address +This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low +position 12 bits are all zero. + 12 + 20 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + SIZE + Memory size +00000b - 4KB +00001b - 8KB +00010b - 16KB +00011b - 32KB +00100b - 64KB +00101b - 128KB +00110b - 256KB +00111b - 512KB +01000b - 1MB +01001b - 2MB +01010b - 4MB +01011b - 8MB +01100b - 16MB +01101b - 32MB +01110b - 64MB +01111b - 128MB +10000b - 256MB +10001b - 512MB +10010b - 1GB +10011b - 2GB +10100-11111b - 4GB + 1 + 5 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + VLD + Valid 0 - 2 + 1 read-write - RESOURCE_SPI0 - Resource control register for spi0 - 0x494 + INTEN + Interrupt Enable Register + 0x38 32 0x00000000 - 0xC0000003 + 0x0000000F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + AXIBUSERR + AXI BUS error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 3 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + AXICMDERR + AXI command error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 2 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + IPCMDERR + IP command error interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled + 1 + 1 + read-write + + + IPCMDDONE + IP command done interrupt enable +0b - Interrupt is disabled +1b - Interrupt is enabled 0 - 2 + 1 read-write - RESOURCE_SPI1 - Resource control register for spi1 - 0x498 + INTR + Interrupt Status Register + 0x3c 32 0x00000000 - 0xC0000003 + 0x0000000F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + AXIBUSERR + AXI bus error interrupt +AXI Bus error interrupt is generated in following cases: +• AXI address is invalid +• AXI 8-bit or 16-bit WRAP write/read + 3 1 - read-only + write-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + AXICMDERR + AXI command error interrupt +AXI command error interrupt is generated when AXI command execution timeout. + 2 1 - read-only + write-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + IPCMDERR + IP command error done interrupt +IP command error interrupt is generated in following case: +• IP Command Address target invalid device space +• IP Command Code unsupported +• IP Command triggered when previous command + 1 + 1 + write-only + + + IPCMDDONE + IP command normal done interrupt 0 - 2 - read-write + 1 + write-only - RESOURCE_SPI2 - Resource control register for spi2 - 0x49c + SDRCTRL0 + SDRAM Control Register 0 + 0x40 32 0x00000000 - 0xC0000003 + 0x00004FFB - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + BANK2 + 2 Bank selection bit +0b - SDRAM device has 4 banks. +1b - SDRAM device has 2 banks. + 14 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + CAS + CAS Latency +00b - 1 +01b - 1 +10b - 2 +11b - 3 + 10 + 2 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 + COL + Column address bit number +00b - 12 bit +01b - 11 bit +10b - 10 bit +11b - 9 bit + 8 2 read-write - - - - RESOURCE_SPI3 - Resource control register for spi3 - 0x4a0 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + COL8 + Column 8 selection bit +0b - Column address bit number is decided by COL field. +1b - Column address bit number is 8. COL field is ignored. + 7 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + BURSTLEN + Burst Length +000b - 1 +001b - 2 +010b - 4 +011b - 8 +100b - 8 +101b - 8 +110b - 8 +111b - 8 + 4 + 3 + read-write + + + HIGHBAND + high band select +0: use data[15:0] for 16bit SDRAM; +1: use data[31:16] for 16bit SDRAM; +only used when Port Size is 16bit(PORTSZ=01b) + 3 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + PORTSZ + Port Size +00b - 8bit +01b - 16bit +10b - 32bit 0 2 read-write @@ -62973,837 +54209,796 @@ n:2^(3+n) - RESOURCE_CAN0 - Resource control register for can0 - 0x4a4 + SDRCTRL1 + SDRAM Control Register 1 + 0x44 32 0x00000000 - 0xC0000003 + 0x00FFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + ACT2PRE + ACT to Precharge minimum time +It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. + 20 + 4 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + CKEOFF + CKE OFF minimum time +It is promised clock suspend last at leat CKEOFF+1 clock cycles. + 16 + 4 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + WRC + Write recovery time +It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. + 13 + 3 read-write - - - - RESOURCE_CAN1 - Resource control register for can1 - 0x4a8 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + RFRC + Refresh recovery time +It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. + 8 + 5 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + ACT2RW + ACT to Read/Write wait time +It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. + 4 + 4 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + PRE2ACT + PRECHARGE to ACT/Refresh wait time +It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. 0 - 2 + 4 read-write - RESOURCE_PTPC - Resource control register for ptpc - 0x4ac + SDRCTRL2 + SDRAM Control Register 2 + 0x48 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + ITO + SDRAM Idle timeout +It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is +considered idle when there is no AXI Bus transfer and no SDRAM command pending. +00000000b - IDLE timeout period is 256*Prescale period. +00000001-11111111b - IDLE timeout period is ITO*Prescale period. + 24 + 8 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + ACT2ACT + ACT to ACT wait time +It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This +could help to meet tRRD timing requirement by SDRAM device. + 16 + 8 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + REF2REF + Refresh to Refresh wait time +It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. +This could help to meet tRFC timing requirement by SDRAM device. + 8 + 8 + read-write + + + SRRC + Self Refresh Recovery time +It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. 0 - 2 + 8 read-write - RESOURCE_ADC0 - Resource control register for adc0 - 0x4b0 + SDRCTRL3 + SDRAM Control Register 3 + 0x4c 32 0x00000000 - 0xC0000003 + 0xFFFFFF0F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + UT + Refresh urgent threshold +Internal refresh request is generated on every Refresh period. Before internal request timer count up to +urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh +request is handled in lower priority than any pending AXI command or IP command to SDRAM device. +When internal request timer count up to this urgent threshold, refresh request is considered as urgent +refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP +command to SDRAM device. +NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as +urgent refresh request. +Refresh urgent threshold is as follwoing: +00000000b - 256*Prescaler period +00000001-11111111b - UT*Prescaler period + 24 + 8 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + RT + Refresh timer period +Refresh timer period is as following: +00000000b - 256*Prescaler period +00000001-11111111b - RT*Prescaler period + 16 + 8 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + PRESCALE + Prescaler timer period +Prescaler timer period is as following: +00000000b - 256*16 clock cycles +00000001-11111111b - PRESCALE*16 clock cycles + 8 + 8 + read-write + + + REBL + Refresh burst length +It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The +number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. +000b - 1 +001b - 2 +010b - 3 +011b - 4 +100b - 5 +101b - 6 +110b - 7 +111b - 8 + 1 + 3 + read-write + + + REN + Refresh enable 0 - 2 + 1 read-write - RESOURCE_ADC1 - Resource control register for adc1 - 0x4b4 + SRCTRL0 + SRAM control register 0 + 0x70 32 0x00000000 - 0xC0000003 + 0x00000F01 - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + ADVH + ADV hold state +0b - ADV is high during address hold state +1b - ADV is low during address hold state + 11 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + ADVP + ADV polarity +0b - ADV is active low +1b - ADV is active high + 10 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 + ADM + address data mode +00b - address and data MUX mode +11b - address and data non-MUX mode + 8 2 read-write + + PORTSZ + port size +0b - 8bit +1b - 16bit + 0 + 1 + read-write + - RESOURCE_ADC2 - Resource control register for adc2 - 0x4b8 + SRCTRL1 + SRAM control register 1 + 0x74 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + OEH + OE high time, is OEH+1 clock cycles + 28 + 4 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + OEL + OE low time, is OEL+1 clock cycles + 24 + 4 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + WEH + WE high time, is WEH+1 clock cycles + 20 + 4 + read-write + + + WEL + WE low time, is WEL+1 clock cycles + 16 + 4 + read-write + + + AH + Address hold time, is AH+1 clock cycles + 12 + 4 + read-write + + + AS + Address setup time, is AS+1 clock cycles + 8 + 4 + read-write + + + CEH + Chip enable hold time, is CEH+1 clock cycles + 4 + 4 + read-write + + + CES + Chip enable setup time, is CES+1 clock cycles 0 - 2 + 4 read-write - RESOURCE_DAC0 - Resource control register for dac - 0x4bc + SADDR + IP Command Control Register 0 + 0x90 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + SA + Slave address 0 - 2 + 32 read-write - RESOURCE_ACMP - Resource control register for acmp - 0x4c0 + DATSZ + IP Command Control Register 1 + 0x94 32 0x00000000 - 0xC0000003 + 0x00000007 - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + DATSZ + Data Size in Byte +When IP command is not a write/read operation, DATSZ field would be ignored. +000b - 4 +001b - 1 +010b - 2 +011b - 3 +100b - 4 +101b - 4 +110b - 4 +111b - 4 0 - 2 + 3 read-write - RESOURCE_I2S0 - Resource control register for i2s0 - 0x4c4 + BYTEMSK + IP Command Control Register 2 + 0x98 32 0x00000000 - 0xC0000003 + 0x0000000F - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + BM3 + Byte Mask for Byte 3 (IPTXD bit 31:24) +0b - Byte Unmasked +1b - Byte Masked + 3 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + BM2 + Byte Mask for Byte 2 (IPTXD bit 23:16) +0b - Byte Unmasked +1b - Byte Masked + 2 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + BM1 + Byte Mask for Byte 1 (IPTXD bit 15:8) +0b - Byte Unmasked +1b - Byte Masked + 1 + 1 + read-write + + + BM0 + Byte Mask for Byte 0 (IPTXD bit 7:0) +0b - Byte Unmasked +1b - Byte Masked 0 - 2 + 1 read-write - RESOURCE_I2S1 - Resource control register for i2s1 - 0x4c8 + IPCMD + IP Command Register + 0x9c 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + KEY + This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory +device is selected by BRx settings and IPCR0 registers. + 16 + 16 + write-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + CMD + SDRAM Commands: +• 0x8: READ +• 0x9: WRITE +• 0xA: MODESET +• 0xB: ACTIVE +• 0xC: AUTO REFRESH +• 0xD: SELF REFRESH +• 0xE: PRECHARGE +• 0xF: PRECHARGE ALL +• Others: RSVD +NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. 0 - 2 + 16 read-write - RESOURCE_PDM0 - Resource control register for pdm - 0x4cc + IPTX + TX DATA Register + 0xa0 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + DAT + Data 0 - 2 + 32 read-write - RESOURCE_DAO - Resource control register for dao - 0x4d0 + IPRX + RX DATA Register + 0xb0 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + DAT + Data 0 - 2 + 32 read-write - RESOURCE_MSYN - Resource control register for msyn - 0x4d4 + STAT0 + Status Register 0 + 0xc0 32 0x00000000 - 0xC0000003 + 0x00000001 - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + IDLE + Indicating whether it is in IDLE state. +When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no +pending device access. + 0 1 read-only + + + + DLYCFG + Delay Line Config Register + 0x150 + 32 + 0x00000000 + 0x0000203F + - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + OE + delay clock output enable, should be set after setting DLYEN and DLYSEL + 13 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + DLYSEL + delay line select, 0 for 1 cell, 31 for all 32 cells + 1 + 5 + read-write + + + DLYEN + delay line enable 0 - 2 + 1 read-write + + + + FFA + FFA + FFA + 0xf3058000 + + 0x0 + 0x48 + registers + + - RESOURCE_MOT0 - Resource control register for mot0 - 0x4d8 + CTRL + No description avaiable + 0x0 32 0x00000000 - 0xC0000003 + 0xFFFFFE01 - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status + SFTRST + software reset the module if asserted to be 1. +EN is only active after this bit is zero. 31 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + RSV + Reserved + 9 + 22 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + EN + Asserted to enable the module 0 - 2 + 1 read-write - RESOURCE_MOT1 - Resource control register for mot1 - 0x4dc + STATUS + No description avaiable + 0x4 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 + RSV + Reserved + 8 + 24 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + FIR_OV + FIR Overflow err + 7 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write + FFT_OV + FFT Overflow Err + 6 + 1 + read-only - - - - RESOURCE_ETH0 - Resource control register for enet - 0x4e0 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + WR_ERR + AXI Data Write Error + 5 1 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + RD_NXT_ERR + AXI Read Bus Error for NXT DATA + 4 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write + RD_ERR + AXI Data Read Error + 3 + 1 + read-only - - - - RESOURCE_NTM0 - Resource control register for ntmr - 0x4e4 - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + RSV + Reserved + 2 1 read-only - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + NXT_CMD_RD_DONE + Indicate that next command sequence is already read into the module. + 1 1 read-only - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + OP_CMD_DONE + Indicate that operation cmd is done, and data are available in system memory. 0 - 2 - read-write + 1 + read-only - RESOURCE_SDC0 - Resource control register for sdxc - 0x4e8 + INT_EN + No description avaiable + 0x8 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + WRSV1 + Reserved + 8 + 24 + read-write + + + FIR_OV + FIR Overflow err + 7 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + FFT_OV + FFT Overflow Err + 6 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 + WR_ERR + Enable Data Write Error interrupt + 5 + 1 + read-write + + + RD_NXT_ERR + Enable Read Bus Error for NXT DATA interrupt + 4 + 1 + read-write + + + RD_ERR + Enable Data Read Error interrupt + 3 + 1 read-write - - - - RESOURCE_USB0 - Resource control register for usb - 0x4ec - 32 - 0x00000000 - 0xC0000003 - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + RSV + Write as zero + 2 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + NXT_CMD_RD_DONE + Indicate that next command sequence is already read into the module. + 1 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + OP_CMD_DONE + Indicate that operation cmd is done, and data are available in system memory. 0 - 2 + 1 read-write - RESOURCE_REF0 - Resource control register for ref0 - 0x4f0 + OP_CTRL + No description avaiable + 0x20 32 0x00000000 - 0xC0000003 + 0xFFFFFFFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only + NXT_ADDR + The address for the next command. +It will be processed after CUR_CMD is executed and done.. + 2 + 30 + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 + NXT_EN + Whether NXT_CMD is enabled. +Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. + 1 1 - read-only + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + EN + Whether CUR_CMD is enabled. +Asserted to enable the CUR_CMD 0 - 2 + 1 read-write - RESOURCE_REF1 - Resource control register for ref1 - 0x4f4 + OP_CMD + No description avaiable + 0x24 32 0x00000000 - 0xC0000003 + 0x01FFFEFF - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 + CONJ_C + asserted to have conjuate value for coefs in computation + 24 1 - read-only + read-write - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only + CMD + The Command Used: +0: FIR +2: FFT +Others: Reserved + 18 + 6 + read-write - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved + OUTD_TYPE + Output data type: +0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 + 15 + 3 + read-write + + + COEF_TYPE + Coef data type (used for FIR): +0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 + 12 + 3 + read-write + + + IND_TYPE + Input data type: +0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 + 9 + 3 + read-write + + + NXT_CMD_LEN + The length of nxt commands in 32-bit words 0 - 2 + 8 read-write - GROUP0_LINK0_VALUE - Group setting - 0x800 + OP_REG0 + No description avaiable + 0x28 32 0x00000000 0xFFFFFFFF - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed + CT + Contents 0 32 read-write @@ -63811,56 +55006,81 @@ n:2^(3+n) - GROUP0_LINK0_SET - Group setting - 0x804 + OP_FIR_MISC + No description avaiable + 0x28 32 0x00000000 - 0xFFFFFFFF + 0x00003FFF - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: add periphera into this group，periphera is needed + FIR_COEF_TAPS + Length of FIR coefs 0 - 32 + 14 read-write - GROUP0_LINK0_CLEAR - Group setting - 0x808 + OP_FFT_MISC + No description avaiable + 0x28 32 0x00000000 - 0xFFFFFFFF + 0x000007FF - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: delete periphera in this group，periphera is not needed + FFT_LEN + FFT length +0:8, +..., +n:2^(3+n) + 7 + 4 + read-write + + + IFFT + Asserted to indicate IFFT + 6 + 1 + read-write + + + RSV + Reserved. Should be written as zero + 4 + 2 + read-write + + + TMP_BLK + Memory block for indata. Should be assigned as 1 + 2 + 2 + read-write + + + IND_BLK + Memory block for indata. Should be assigned as 0 0 - 32 + 2 read-write - GROUP0_LINK0_TOGGLE - Group setting - 0x80c + OP_REG1 + No description avaiable + 0x2c 32 0x00000000 0xFFFFFFFF - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: toggle the result that whether periphera is needed before + CT + Contents 0 32 read-write @@ -63868,37 +55088,54 @@ n:2^(3+n) - GROUP0_LINK1_VALUE - Group setting - 0x810 + OP_FIR_MISC1 + No description avaiable + 0x2c 32 0x00000000 - 0xFFFFFFFF + 0x003FFFFF - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed + OUTD_MEM_BLK + Should be assigned as 0 + 20 + 2 + read-write + + + COEF_MEM_BLK + Should be assigned as 1 + 18 + 2 + read-write + + + IND_MEM_BLK + Should be assigned as 2 + 16 + 2 + read-write + + + FIR_DATA_TAPS + The input data data length 0 - 32 + 16 read-write - GROUP0_LINK1_SET - Group setting - 0x814 + OP_REG2 + No description avaiable + 0x30 32 0x00000000 0xFFFFFFFF - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: add periphera into this group，periphera is needed + CT + Contents 0 32 read-write @@ -63906,18 +55143,16 @@ n:2^(3+n) - GROUP0_LINK1_CLEAR - Group setting - 0x818 + OP_FFT_INRBUF + No description avaiable + 0x30 32 0x00000000 0xFFFFFFFF - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: delete periphera in this group，periphera is not needed + LOC + The input (real) data buffer pointer 0 32 read-write @@ -63925,18 +55160,16 @@ n:2^(3+n) - GROUP0_LINK1_TOGGLE - Group setting - 0x81c + OP_REG3 + No description avaiable + 0x34 32 0x00000000 0xFFFFFFFF - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: toggle the result that whether periphera is needed before + CT + Contents 0 32 read-write @@ -63944,489 +55177,478 @@ n:2^(3+n) - AFFILIATE_CPU0_VALUE - Affiliate of Group - 0x900 + OP_FIR_INBUF + No description avaiable + 0x34 32 0x00000000 - 0x0000000F + 0xFFFFFFFF - LINK - Affiliate groups of cpu0, each bit represents a group -bit0: cpu0 depends on group0 -bit1: cpu0 depends on group1 -bit2: cpu0 depends on group2 -bit3: cpu0 depends on group3 + LOC + The input data buffer pointer 0 - 4 + 32 read-write - AFFILIATE_CPU0_SET - Affiliate of Group - 0x904 + OP_REG4 + No description avaiable + 0x38 32 0x00000000 - 0x0000000F + 0xFFFFFFFF - LINK - Affiliate groups of cpu0，each bit represents a group -0: no effect -1: the group is assigned to CPU0 + CT + Contents 0 - 4 + 32 read-write - AFFILIATE_CPU0_CLEAR - Affiliate of Group - 0x908 + OP_FIR_COEFBUF + No description avaiable + 0x38 32 0x00000000 - 0x0000000F + 0xFFFFFFFF - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: the group is not assigned to CPU0 + LOC + The coef buf pointer 0 - 4 + 32 read-write - AFFILIATE_CPU0_TOGGLE - Affiliate of Group - 0x90c + OP_FFT_OUTRBUF + No description avaiable + 0x38 32 0x00000000 - 0x0000000F + 0xFFFFFFFF - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: toggle the result that whether the group is assigned to CPU0 before + LOC + The output (real) data buffer pointer 0 - 4 + 32 read-write - RETENTION_CPU0_VALUE - Retention Contol - 0x920 + OP_REG5 + No description avaiable + 0x3c 32 0x00000000 - 0x000000FF + 0xFFFFFFFF - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -bit00: soc_mem is kept on while cpu stop, -bit01: soc_ctx is kept on while cpu stop, -bit02: cpu0_mem is kept on while cpu stop, -bit03: cpu0_ctx is kept on while cpu stop, -bit04: xtal_hold is kept on while cpu stop, -bit05: pll0_hold is kept on while cpu stop, -bit06: pll1_hold is kept on while cpu stop, -bit07: pll2_hold is kept on while cpu stop, + CT + Contents 0 - 8 + 32 read-write - RETENTION_CPU0_SET - Retention Contol - 0x924 + OP_FIR_OUTBUF + No description avaiable + 0x3c 32 0x00000000 - 0x000000FF + 0xFFFFFFFF - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: keep + LOC + The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） 0 - 8 + 32 read-write - RETENTION_CPU0_CLEAR - Retention Contol - 0x928 + OP_REG6 + No description avaiable + 0x40 32 0x00000000 - 0x000000FF + 0xFFFFFFFF - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: no keep + CT + Contents 0 - 8 + 32 read-write - RETENTION_CPU0_TOGGLE - Retention Contol - 0x92c + OP_REG7 + No description avaiable + 0x44 32 0x00000000 - 0x000000FF + 0xFFFFFFFF - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: toggle the result that whether the resource is kept on while CPU0 stop before + CT + Contents 0 - 8 + 32 read-write + + + + SYSCTL + SYSCTL + SYSCTL + 0xf4000000 + + 0x0 + 0x2c00 + registers + + - POWER_CPU0_STATUS - Power Setting - 0x1000 + RESOURCE_CPU0 + Resource control register for cpu0_core + 0x0 32 - 0x80000000 - 0xC0001100 + 0x00000000 + 0xC0000003 - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status 31 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 read-only - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - POWER_CPU0_LF_WAIT - Power Setting - 0x1004 - 32 - 0x00000255 - 0x000FFFFF - + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 20 + 2 read-write - POWER_CPU0_OFF_WAIT - Power Setting - 0x100c + RESOURCE_CPX0 + Resource control register for cpu0_subsys + 0x4 32 - 0x00000015 - 0x000FFFFF + 0x00000000 + 0xC0000003 - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 20 + 2 read-write - RESET_SOC_CONTROL - Reset Setting - 0x1400 + RESOURCE_POW_CPU0 + Resource control register for pow_cpu0 + 0x54 32 - 0x80000000 - 0xC0000011 + 0x00000000 + 0xC0000003 - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status 31 1 - read-write + read-only - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status 30 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write + read-only - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automaticly + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 1 + 2 read-write - RESET_SOC_CONFIG - Reset Setting - 0x1404 + RESOURCE_RST_SOC + Resource control register for rst_soc + 0x58 32 - 0x00643203 - 0x00FFFFFF + 0x00000000 + 0xC0000003 - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - RESET_SOC_COUNTER - Reset Setting - 0x140c + RESOURCE_RST_CPU0 + Resource control register for rst_cpu0 + 0x5c 32 - 0x00000003 - 0x000FFFFF + 0x00000000 + 0xC0000003 - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 20 + 2 read-write - RESET_CPU0_CONTROL - Reset Setting - 0x1410 + RESOURCE_CLK_SRC_XTAL + Resource control register for xtal + 0x80 32 - 0x80000000 - 0xC0000011 + 0x00000000 + 0xC0000003 - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status 31 1 - read-write + read-only - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status 30 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write + read-only - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automaticly + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 1 + 2 read-write - RESET_CPU0_CONFIG - Reset Setting - 0x1414 + RESOURCE_CLK_SRC_PLL0 + Resource control register for pll0 + 0x84 32 - 0x00643203 - 0x00FFFFFF + 0x00000000 + 0xC0000003 - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - RESET_CPU0_COUNTER - Reset Setting - 0x141c + RESOURCE_CLK_SRC_CLK0_PLL0 + Resource control register for clk0_pll0 + 0x88 32 - 0x00000003 - 0x000FFFFF + 0x00000000 + 0xC0000003 - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 20 + 2 read-write - CLOCK_CPU_CLK_TOP_CPU0 - Clock setting - 0x1800 + RESOURCE_CLK_SRC_CLK1_PLL0 + Resource control register for clk1_pll0 + 0x8c 32 0x00000000 - 0xD0FF0FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -64435,82 +55657,76 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - SUB1_DIV - ahb bus divider, the bus clock is generated by cpu_clock/div -0: divider by 1 -1: divider by 2 -… - 20 - 4 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_CLK_SRC_CLK2_PLL0 + Resource control register for clk2_pll0 + 0x90 + 32 + 0x00000000 + 0xC0000003 + - SUB0_DIV - axi bus divider, the bus clock is generated by cpu_clock/div -0: divider by 1 -1: divider by 2 -… - 16 - 4 - read-write + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_MCT0 - Clock setting - 0x1804 + RESOURCE_CLK_SRC_PLL1 + Resource control register for pll1 + 0x94 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -64519,62 +55735,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_FEMC - Clock setting - 0x1808 + RESOURCE_CLK_SRC_CLK0_PLL1 + Resource control register for clk0_pll1 + 0x98 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -64583,62 +55774,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_XPI0 - Clock setting - 0x180c + RESOURCE_CLK_SRC_CLK1_PLL1 + Resource control register for clk1_pll1 + 0x9c 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -64647,62 +55813,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_XPI1 - Clock setting - 0x1810 + RESOURCE_CLK_SRC_PLL2 + Resource control register for pll2 + 0xa0 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -64711,62 +55852,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_TMR0 - Clock setting - 0x1814 + RESOURCE_CLK_SRC_CLK0_PLL2 + Resource control register for clk0_pll2 + 0xa4 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -64775,62 +55891,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_TMR1 - Clock setting - 0x1818 + RESOURCE_CLK_SRC_CLK1_PLL2 + Resource control register for clk1_pll2 + 0xa8 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -64839,62 +55930,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_TMR2 - Clock setting - 0x181c + RESOURCE_CLK_SRC_PLL0_REF + Resource control register for pll0 ref clock + 0xac 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -64903,62 +55969,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_TMR3 - Clock setting - 0x1820 + RESOURCE_CLK_SRC_PLL1_REF + Resource control register for pll1 ref clock + 0xb0 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -64967,62 +56008,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_URT0 - Clock setting - 0x1824 + RESOURCE_CLK_SRC_PLL2_REF + Resource control register for pll2 ref clock + 0xb4 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65031,62 +56047,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_URT1 - Clock setting - 0x1828 + RESOURCE_CLK_TOP_CPU0 + Resource control register for clk_top_cpu0 + 0x100 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65095,62 +56086,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_URT2 - Clock setting - 0x182c + RESOURCE_CLK_TOP_MCT0 + Resource control register for clk_top_mct0 + 0x104 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65159,62 +56125,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_URT3 - Clock setting - 0x1830 + RESOURCE_CLK_TOP_FEMC + Resource control register for clk_top_femc + 0x108 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65223,62 +56164,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_URT4 - Clock setting - 0x1834 + RESOURCE_CLK_TOP_XPI0 + Resource control register for clk_top_xpi0 + 0x10c 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65287,62 +56203,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_URT5 - Clock setting - 0x1838 + RESOURCE_CLK_TOP_XPI1 + Resource control register for clk_top_xpi1 + 0x110 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65351,62 +56242,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_URT6 - Clock setting - 0x183c + RESOURCE_CLK_TOP_TMR0 + Resource control register for clk_top_tmr0 + 0x114 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65415,62 +56281,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_URT7 - Clock setting - 0x1840 + RESOURCE_CLK_TOP_TMR1 + Resource control register for clk_top_tmr1 + 0x118 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65479,62 +56320,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_I2C0 - Clock setting - 0x1844 + RESOURCE_CLK_TOP_TMR2 + Resource control register for clk_top_tmr2 + 0x11c 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65543,62 +56359,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_I2C1 - Clock setting - 0x1848 + RESOURCE_CLK_TOP_TMR3 + Resource control register for clk_top_tmr3 + 0x120 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65607,62 +56398,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_I2C2 - Clock setting - 0x184c + RESOURCE_CLK_TOP_URT0 + Resource control register for clk_top_urt0 + 0x124 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65671,62 +56437,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_I2C3 - Clock setting - 0x1850 + RESOURCE_CLK_TOP_URT1 + Resource control register for clk_top_urt1 + 0x128 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65735,62 +56476,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_SPI0 - Clock setting - 0x1854 + RESOURCE_CLK_TOP_URT2 + Resource control register for clk_top_urt2 + 0x12c 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65799,62 +56515,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_SPI1 - Clock setting - 0x1858 + RESOURCE_CLK_TOP_URT3 + Resource control register for clk_top_urt3 + 0x130 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65863,62 +56554,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_SPI2 - Clock setting - 0x185c + RESOURCE_CLK_TOP_URT4 + Resource control register for clk_top_urt4 + 0x134 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65927,62 +56593,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_SPI3 - Clock setting - 0x1860 + RESOURCE_CLK_TOP_URT5 + Resource control register for clk_top_urt5 + 0x138 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -65991,62 +56632,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_CAN0 - Clock setting - 0x1864 + RESOURCE_CLK_TOP_URT6 + Resource control register for clk_top_urt6 + 0x13c 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66055,62 +56671,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_CAN1 - Clock setting - 0x1868 + RESOURCE_CLK_TOP_URT7 + Resource control register for clk_top_urt7 + 0x140 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66119,62 +56710,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_PTPC - Clock setting - 0x186c + RESOURCE_CLK_TOP_I2C0 + Resource control register for clk_top_i2c0 + 0x144 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66183,62 +56749,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_ANA0 - Clock setting - 0x1870 + RESOURCE_CLK_TOP_I2C1 + Resource control register for clk_top_i2c1 + 0x148 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66247,62 +56788,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_ANA1 - Clock setting - 0x1874 + RESOURCE_CLK_TOP_I2C2 + Resource control register for clk_top_i2c2 + 0x14c 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66311,62 +56827,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_ANA2 - Clock setting - 0x1878 + RESOURCE_CLK_TOP_I2C3 + Resource control register for clk_top_i2c3 + 0x150 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66375,62 +56866,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_ANA3 - Clock setting - 0x187c + RESOURCE_CLK_TOP_SPI0 + Resource control register for clk_top_spi0 + 0x154 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66439,62 +56905,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_AUD0 - Clock setting - 0x1880 + RESOURCE_CLK_TOP_SPI1 + Resource control register for clk_top_spi1 + 0x158 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66503,62 +56944,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_AUD1 - Clock setting - 0x1884 + RESOURCE_CLK_TOP_SPI2 + Resource control register for clk_top_spi2 + 0x15c 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66567,62 +56983,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_ETH0 - Clock setting - 0x1888 + RESOURCE_CLK_TOP_SPI3 + Resource control register for clk_top_spi3 + 0x160 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66631,62 +57022,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_PTP0 - Clock setting - 0x188c + RESOURCE_CLK_TOP_CAN0 + Resource control register for clk_top_can0 + 0x164 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66695,62 +57061,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_REF0 - Clock setting - 0x1890 + RESOURCE_CLK_TOP_CAN1 + Resource control register for clk_top_can1 + 0x168 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66759,62 +57100,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_REF1 - Clock setting - 0x1894 + RESOURCE_CLK_TOP_PTPC + Resource control register for clk_top_ptpc + 0x16c 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66823,62 +57139,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_NTM0 - Clock setting - 0x1898 + RESOURCE_CLK_TOP_ANA0 + Resource control register for clk_top_ana0 + 0x170 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66887,62 +57178,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - CLOCK_CLK_TOP_SDC0 - Clock setting - 0x189c + RESOURCE_CLK_TOP_ANA1 + Resource control register for clk_top_ana1 + 0x174 32 0x00000000 - 0xD0000FFF + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -66951,62 +57217,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - ADCCLK_CLK_TOP_ADC0 - Clock setting - 0x1c00 + RESOURCE_CLK_TOP_ANA2 + Resource control register for clk_top_ana2 + 0x178 32 0x00000000 - 0xD0000100 + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -67015,44 +57256,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock -1: ahb clock - 8 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write - ADCCLK_CLK_TOP_ADC1 - Clock setting - 0x1c04 + RESOURCE_CLK_TOP_ANA3 + Resource control register for clk_top_ana3 + 0x17c 32 0x00000000 - 0xD0000100 + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -67061,44 +57295,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock -1: ahb clock - 8 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write - ADCCLK_CLK_TOP_ADC2 - Clock setting - 0x1c08 + RESOURCE_CLK_TOP_AUD0 + Resource control register for clk_top_aud0 + 0x180 32 0x00000000 - 0xD0000100 + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -67107,44 +57334,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock -1: ahb clock - 8 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write - DACCLK_CLK_TOP_DAC0 - Clock setting - 0x1c0c + RESOURCE_CLK_TOP_AUD1 + Resource control register for clk_top_aud1 + 0x184 32 0x00000000 - 0xD0000100 + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -67153,44 +57373,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock -1: ahb clock - 8 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write - I2SCLK_CLK_TOP_I2S0 - Clock setting - 0x1c10 + RESOURCE_CLK_TOP_ETH0 + Resource control register for clk_top_eth0 + 0x188 32 0x00000000 - 0xD0000100 + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -67199,44 +57412,37 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: aud clock 0 -1: aud clock 1 - 8 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write - I2SCLK_CLK_TOP_I2S1 - Clock setting - 0x1c14 + RESOURCE_CLK_TOP_PTP0 + Resource control register for clk_top_ptp0 + 0x18c 32 0x00000000 - 0xD0000100 + 0xC0000003 GLB_BUSY global busy -0: no changes pending to any clock +0: no changes pending to any nodes 1: any of nodes is changing status 31 1 @@ -67245,713 +57451,604 @@ Note, clock cycle is base on 24M LOC_BUSY local busy -0: a change is pending for current node +0: no change is pending for current node 1: current node is changing status 30 1 read-only - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: aud clock 0 -1: aud clock 1 - 8 - 1 - read-write - - - - - GLOBAL00 - Clock senario - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - MUX - global clock override request -bit0: override to preset0 -bit1: override to preset1 -bit2: override to preset2 -bit3: override to preset3 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 4 + 2 read-write - MONITOR_SLICE0_CONTROL - Clock measure and monitor control - 0x2400 + RESOURCE_CLK_TOP_REF0 + Resource control register for clk_top_ref0 + 0x190 32 0x00000000 - 0x89FFD7FF + 0xC0000003 - VALID - result is ready for read -0: not ready -1: result is ready + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status 31 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 read-only - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - MONITOR_SLICE0_CURRENT - Clock measure result - 0x2404 + RESOURCE_CLK_TOP_REF1 + Resource control register for clk_top_ref1 + 0x194 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - FREQUENCY - self updating measure result - 0 - 32 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 read-only - - - - MONITOR_SLICE0_LOW_LIMIT - Clock lower limit - 0x2408 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - FREQUENCY - lower frequency - 0 - 32 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - - - - MONITOR_SLICE0_HIGH_LIMIT - Clock upper limit - 0x240c - 32 - 0x00000000 - 0xFFFFFFFF - - FREQUENCY - upper frequency + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - MONITOR_SLICE1_CONTROL - Clock measure and monitor control - 0x2420 + RESOURCE_CLK_TOP_NTM0 + Resource control register for clk_top_ntm0 + 0x198 32 0x00000000 - 0x89FFD7FF + 0xC0000003 - VALID - result is ready for read -0: not ready -1: result is ready + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status 31 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 read-only - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - MONITOR_SLICE1_CURRENT - Clock measure result - 0x2424 + RESOURCE_CLK_TOP_SDC0 + Resource control register for clk_top_sdc0 + 0x19c 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - FREQUENCY - self updating measure result - 0 - 32 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 read-only - - - - MONITOR_SLICE1_LOW_LIMIT - Clock lower limit - 0x2428 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - FREQUENCY - lower frequency - 0 - 32 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - - - - MONITOR_SLICE1_HIGH_LIMIT - Clock upper limit - 0x242c - 32 - 0x00000000 - 0xFFFFFFFF - - FREQUENCY - upper frequency + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - MONITOR_SLICE2_CONTROL - Clock measure and monitor control - 0x2440 + RESOURCE_CLK_TOP_ADC0 + Resource control register for clk_top_adc0 + 0x200 32 0x00000000 - 0x89FFD7FF + 0xC0000003 - VALID - result is ready for read -0: not ready -1: result is ready + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status 31 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 read-only - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SELECTION - clock measurement selection + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - MONITOR_SLICE2_CURRENT - Clock measure result - 0x2444 + RESOURCE_CLK_TOP_ADC1 + Resource control register for clk_top_adc1 + 0x204 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - FREQUENCY - self updating measure result - 0 - 32 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 read-only - - - - MONITOR_SLICE2_LOW_LIMIT - Clock lower limit - 0x2448 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - FREQUENCY - lower frequency + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - MONITOR_SLICE2_HIGH_LIMIT - Clock upper limit - 0x244c + RESOURCE_CLK_TOP_ADC2 + Resource control register for clk_top_adc2 + 0x208 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - FREQUENCY - upper frequency + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - MONITOR_SLICE3_CONTROL - Clock measure and monitor control - 0x2460 + RESOURCE_CLK_TOP_DAC0 + Resource control register for clk_top_dac0 + 0x20c 32 0x00000000 - 0x89FFD7FF + 0xC0000003 - VALID - result is ready for read -0: not ready -1: result is ready + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status 31 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 read-only - OUTEN - enable clock output - 24 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write - - - DIV - output divider - 16 - 8 - read-write + read-only - HIGH - clock frequency higher than upper limit - 15 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_CLK_TOP_I2S0 + Resource control register for clk_top_i2s0 + 0x210 + 32 + 0x00000000 + 0xC0000003 + - LOW - clock frequency lower than lower limit - 14 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - START - start measurement - 12 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_CLK_TOP_I2S1 + Resource control register for clk_top_i2s1 + 0x214 + 32 + 0x00000000 + 0xC0000003 + - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SELECTION - clock measurement selection + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 8 + 2 read-write - MONITOR_SLICE3_CURRENT - Clock measure result - 0x2464 + RESOURCE_AHBP + Resource control register for ahbapb_bus + 0x400 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - FREQUENCY - self updating measure result - 0 - 32 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 read-only - - - - MONITOR_SLICE3_LOW_LIMIT - Clock lower limit - 0x2468 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - FREQUENCY - lower frequency + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - MONITOR_SLICE3_HIGH_LIMIT - Clock upper limit - 0x246c + RESOURCE_AXIS + Resource control register for soc_bus + 0x404 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - FREQUENCY - upper frequency + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_LP - CPU0 LP control - 0x2800 + RESOURCE_AXIC + Resource control register for conn_bus + 0x408 32 - 0x00001000 - 0xFF013703 + 0x00000000 + 0xC0000003 - WAKE_CNT - CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - 24 - 8 - read-write + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_FEMC + Resource control register for femc + 0x40c + 32 + 0x00000000 + 0xC0000003 + - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 read-only - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 read-only - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wake up happened - 10 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_ROM0 + Resource control register for rom + 0x410 + 32 + 0x00000000 + 0xC0000003 + - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 reset not happened -1: CPU0 reset happened - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 2 read-write @@ -67959,5892 +58056,6810 @@ bit3: override to preset3 - CPU_CPU0_LOCK - CPU0 Lock GPR - 0x2804 + RESOURCE_LMM0 + Resource control register for lmm0 + 0x414 32 - 0x00000002 - 0x0000FFFE + 0x00000000 + 0xC0000003 - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only - LOCK - Lock bit for CPU_LOCK - 1 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write - CPU_CPU0_GPR_GPR0 - CPU0 GPR0 - 0x2808 + RESOURCE_RAM0 + Resource control register for axi_sram + 0x418 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_GPR_GPR1 - CPU0 GPR1 - 0x280c + RESOURCE_MCT0 + Resource control register for mchtmr0 + 0x41c 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only - - - - CPU_CPU0_GPR_GPR2 - CPU0 GPR2 - 0x2810 - 32 - 0x00000000 - 0xFFFFFFFF - - GPR - register for software to handle resume, can save resume address or status + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_GPR_GPR3 - CPU0 GPR3 - 0x2814 + RESOURCE_XPI0 + Resource control register for xpi0 + 0x420 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_GPR_GPR4 - CPU0 GPR4 - 0x2818 + RESOURCE_XPI1 + Resource control register for xpi1 + 0x424 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_GPR_GPR5 - CPU0 GPR5 - 0x281c + RESOURCE_SDP0 + Resource control register for sdp + 0x428 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_GPR_GPR6 - CPU0 GPR6 - 0x2820 + RESOURCE_RNG0 + Resource control register for rng + 0x42c 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_GPR_GPR7 - CPU0 GPR7 - 0x2824 + RESOURCE_KMAN + Resource control register for keym + 0x430 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_GPR_GPR8 - CPU0 GPR8 - 0x2828 + RESOURCE_DMA0 + Resource control register for hdma + 0x434 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_GPR_GPR9 - CPU0 GPR9 - 0x282c + RESOURCE_DMA1 + Resource control register for xdma + 0x438 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_GPR_GPR10 - CPU0 GPR10 - 0x2830 + RESOURCE_FFA0 + Resource control register for ffa + 0x43c 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_GPR_GPR11 - CPU0 GPR11 - 0x2834 + RESOURCE_GPIO + Resource control register for gpio + 0x440 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_GPR_GPR12 - CPU0 GPR12 - 0x2838 + RESOURCE_MBX0 + Resource control register for mbx + 0x444 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_GPR_GPR13 - CPU0 GPR13 - 0x283c + RESOURCE_WDG0 + Resource control register for wdg0 + 0x448 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - GPR - register for software to handle resume, can save resume address or status + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_WAKEUP_STATUS_STATUS0 - CPU0 wakeup IRQ status - 0x2840 + RESOURCE_WDG1 + Resource control register for wdg1 + 0x44c 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - STATUS - IRQ values - 0 - 32 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 read-only - - - - CPU_CPU0_WAKEUP_STATUS_STATUS1 - CPU0 wakeup IRQ status - 0x2844 - 32 - 0x00000000 - 0xFFFFFFFF - - STATUS - IRQ values - 0 - 32 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 read-only - - - - CPU_CPU0_WAKEUP_STATUS_STATUS2 - CPU0 wakeup IRQ status - 0x2848 - 32 - 0x00000000 - 0xFFFFFFFF - - STATUS - IRQ values + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 - read-only + 2 + read-write - CPU_CPU0_WAKEUP_STATUS_STATUS3 - CPU0 wakeup IRQ status - 0x284c + RESOURCE_TSNS + Resource control register for tsns + 0x450 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - STATUS - IRQ values - 0 - 32 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 read-only - - - - CPU_CPU0_WAKEUP_ENABLE_ENABLE0 - CPU0 wakeup IRQ enable - 0x2880 - 32 - 0x00000000 - 0xFFFFFFFF - - ENABLE - IRQ wakeup enable + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_WAKEUP_ENABLE_ENABLE1 - CPU0 wakeup IRQ enable - 0x2884 + RESOURCE_TMR0 + Resource control register for tmr0 + 0x454 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - ENABLE - IRQ wakeup enable + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_WAKEUP_ENABLE_ENABLE2 - CPU0 wakeup IRQ enable - 0x2888 + RESOURCE_TMR1 + Resource control register for tmr1 + 0x458 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - ENABLE - IRQ wakeup enable + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - CPU_CPU0_WAKEUP_ENABLE_ENABLE3 - CPU0 wakeup IRQ enable - 0x288c + RESOURCE_TMR2 + Resource control register for tmr2 + 0x45c 32 0x00000000 - 0xFFFFFFFF + 0xC0000003 - ENABLE - IRQ wakeup enable + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 32 + 2 read-write - - - - IOC - IOC - IOC - 0xf4040000 - - 0x0 - 0xf60 - registers - - - PAD_PA00_FUNC_CTL - ALT SELECT - 0x0 + RESOURCE_TMR3 + Resource control register for tmr3 + 0x460 32 0x00000000 - 0x0001011F + 0xC0000003 - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - ANALOG - select analog pin in pad -0: disable -1: enable - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 5 + 2 read-write - PAD_PA00_PAD_CTL - PAD SETTINGS - 0x4 + RESOURCE_URT0 + Resource control register for uart0 + 0x464 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xC0000003 - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_URT1 + Resource control register for uart1 + 0x468 + 32 + 0x00000000 + 0xC0000003 + - PE - pull enable -0: pull disable -1: pull enable - 17 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_URT2 + Resource control register for uart2 + 0x46c + 32 + 0x00000000 + 0xC0000003 + - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 3 + 2 read-write - PAD_PA01_FUNC_CTL - ALT SELECT - 0x8 + RESOURCE_URT3 + Resource control register for uart3 + 0x470 32 0x00000000 - 0x0001011F + 0xC0000003 - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - ANALOG - select analog pin in pad -0: disable -1: enable - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 5 + 2 read-write - PAD_PA01_PAD_CTL - PAD SETTINGS - 0xc + RESOURCE_URT4 + Resource control register for uart4 + 0x474 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xC0000003 - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + read-only - PS - pull select -0: pull down -1: pull up - 18 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_URT5 + Resource control register for uart5 + 0x478 + 32 + 0x00000000 + 0xC0000003 + - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - OD - open drain -0: open drain disable -1: open drain enable - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_URT6 + Resource control register for uart6 + 0x47c + 32 + 0x00000000 + 0xC0000003 + - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 3 + 2 read-write - PAD_PA02_FUNC_CTL - ALT SELECT - 0x10 + RESOURCE_URT7 + Resource control register for uart7 + 0x480 32 0x00000000 - 0x0001011F + 0xC0000003 - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - ANALOG - select analog pin in pad -0: disable -1: enable - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 5 + 2 read-write - PAD_PA02_PAD_CTL - PAD SETTINGS - 0x14 + RESOURCE_I2C0 + Resource control register for i2c0 + 0x484 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xC0000003 - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_I2C1 + Resource control register for i2c1 + 0x488 + 32 + 0x00000000 + 0xC0000003 + - PE - pull enable -0: pull disable -1: pull enable - 17 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_I2C2 + Resource control register for i2c2 + 0x48c + 32 + 0x00000000 + 0xC0000003 + - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 3 + 2 read-write - PAD_PA03_FUNC_CTL - ALT SELECT - 0x18 + RESOURCE_I2C3 + Resource control register for i2c3 + 0x490 32 0x00000000 - 0x0001011F + 0xC0000003 - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - ANALOG - select analog pin in pad -0: disable -1: enable - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 5 + 2 read-write - PAD_PA03_PAD_CTL - PAD SETTINGS - 0x1c + RESOURCE_SPI0 + Resource control register for spi0 + 0x494 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xC0000003 - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_SPI1 + Resource control register for spi1 + 0x498 + 32 + 0x00000000 + 0xC0000003 + - PE - pull enable -0: pull disable -1: pull enable - 17 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_SPI2 + Resource control register for spi2 + 0x49c + 32 + 0x00000000 + 0xC0000003 + - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 3 + 2 read-write - PAD_PA04_FUNC_CTL - ALT SELECT - 0x20 + RESOURCE_SPI3 + Resource control register for spi3 + 0x4a0 32 0x00000000 - 0x0001011F + 0xC0000003 - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - ANALOG - select analog pin in pad -0: disable -1: enable - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 5 + 2 read-write - PAD_PA04_PAD_CTL - PAD SETTINGS - 0x24 + RESOURCE_CAN0 + Resource control register for can0 + 0x4a4 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xC0000003 - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - PE - pull enable -0: pull disable -1: pull enable - 17 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_CAN1 + Resource control register for can1 + 0x4a8 + 32 + 0x00000000 + 0xC0000003 + - OD - open drain -0: open drain disable -1: open drain enable - 8 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write + read-only - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 3 + 2 read-write - PAD_PA05_FUNC_CTL - ALT SELECT - 0x28 + RESOURCE_PTPC + Resource control register for ptpc + 0x4ac 32 0x00000000 - 0x0001011F + 0xC0000003 - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - ANALOG - select analog pin in pad -0: disable -1: enable - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 5 + 2 read-write - PAD_PA05_PAD_CTL - PAD SETTINGS - 0x2c + RESOURCE_ADC0 + Resource control register for adc0 + 0x4b0 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xC0000003 - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - PE - pull enable -0: pull disable -1: pull enable - 17 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_ADC1 + Resource control register for adc1 + 0x4b4 + 32 + 0x00000000 + 0xC0000003 + - OD - open drain -0: open drain disable -1: open drain enable - 8 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write + read-only - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 3 + 2 read-write - PAD_PA06_FUNC_CTL - ALT SELECT - 0x30 + RESOURCE_ADC2 + Resource control register for adc2 + 0x4b8 32 0x00000000 - 0x0001011F + 0xC0000003 - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - ANALOG - select analog pin in pad -0: disable -1: enable - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 5 + 2 read-write - PAD_PA06_PAD_CTL - PAD SETTINGS - 0x34 + RESOURCE_DAC0 + Resource control register for dac + 0x4bc 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xC0000003 - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + read-only - PS - pull select -0: pull down -1: pull up - 18 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_ACMP + Resource control register for acmp + 0x4c0 + 32 + 0x00000000 + 0xC0000003 + - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - OD - open drain -0: open drain disable -1: open drain enable - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_I2S0 + Resource control register for i2s0 + 0x4c4 + 32 + 0x00000000 + 0xC0000003 + - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 3 + 2 read-write - PAD_PA07_FUNC_CTL - ALT SELECT - 0x38 + RESOURCE_I2S1 + Resource control register for i2s1 + 0x4c8 32 0x00000000 - 0x0001011F + 0xC0000003 - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - ANALOG - select analog pin in pad -0: disable -1: enable - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 5 + 2 read-write - PAD_PA07_PAD_CTL - PAD SETTINGS - 0x3c + RESOURCE_PDM0 + Resource control register for pdm + 0x4cc 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xC0000003 - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_DAO + Resource control register for dao + 0x4d0 + 32 + 0x00000000 + 0xC0000003 + - PE - pull enable -0: pull disable -1: pull enable - 17 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_MSYN + Resource control register for msyn + 0x4d4 + 32 + 0x00000000 + 0xC0000003 + - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 3 + 2 read-write - PAD_PA08_FUNC_CTL - ALT SELECT - 0x40 + RESOURCE_MOT0 + Resource control register for mot0 + 0x4d8 32 0x00000000 - 0x0001011F + 0xC0000003 - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - ANALOG - select analog pin in pad -0: disable -1: enable - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 5 + 2 read-write - PAD_PA08_PAD_CTL - PAD SETTINGS - 0x44 + RESOURCE_MOT1 + Resource control register for mot1 + 0x4dc 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xC0000003 - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_ETH0 + Resource control register for enet + 0x4e0 + 32 + 0x00000000 + 0xC0000003 + - PE - pull enable -0: pull disable -1: pull enable - 17 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_NTM0 + Resource control register for ntmr + 0x4e4 + 32 + 0x00000000 + 0xC0000003 + - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 3 + 2 read-write - PAD_PA09_FUNC_CTL - ALT SELECT - 0x48 + RESOURCE_SDC0 + Resource control register for sdxc + 0x4e8 32 0x00000000 - 0x0001011F + 0xC0000003 - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - ANALOG - select analog pin in pad -0: disable -1: enable - 8 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved 0 - 5 + 2 read-write - PAD_PA09_PAD_CTL - PAD SETTINGS - 0x4c + RESOURCE_USB0 + Resource control register for usb + 0x4ec 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xC0000003 - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 2 read-write + + + + RESOURCE_REF0 + Resource control register for ref0 + 0x4f0 + 32 + 0x00000000 + 0xC0000003 + - PS - pull select -0: pull down -1: pull up - 18 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - PE - pull enable -0: pull disable -1: pull enable - 17 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 read-write + + + + RESOURCE_REF1 + Resource control register for ref1 + 0x4f4 + 32 + 0x00000000 + 0xC0000003 + - OD - open drain -0: open drain disable -1: open drain enable - 8 + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 2 read-write + + + + GROUP0_LINK0_VALUE + Group setting + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed 0 - 3 + 32 read-write - PAD_PA10_FUNC_CTL - ALT SELECT - 0x50 + GROUP0_LINK0_SET + Group setting + 0x804 32 0x00000000 - 0x0001011F + 0xFFFFFFFF - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 read-write + + + + GROUP0_LINK0_CLEAR + Group setting + 0x808 + 32 + 0x00000000 + 0xFFFFFFFF + - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 read-write + + + + GROUP0_LINK0_TOGGLE + Group setting + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before 0 - 5 + 32 read-write - PAD_PA10_PAD_CTL - PAD SETTINGS - 0x54 + GROUP0_LINK1_VALUE + Group setting + 0x810 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xFFFFFFFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 read-write + + + + GROUP0_LINK1_SET + Group setting + 0x814 + 32 + 0x00000000 + 0xFFFFFFFF + - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 read-write + + + + GROUP0_LINK1_CLEAR + Group setting + 0x818 + 32 + 0x00000000 + 0xFFFFFFFF + - PS - pull select -0: pull down -1: pull up - 18 - 1 + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 read-write + + + + GROUP0_LINK1_TOGGLE + Group setting + 0x81c + 32 + 0x00000000 + 0xFFFFFFFF + - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 read-write + + + + AFFILIATE_CPU0_VALUE + Affiliate of Group + 0x900 + 32 + 0x00000000 + 0x0000000F + - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + LINK + Affiliate groups of cpu0, each bit represents a group +bit0: cpu0 depends on group0 +bit1: cpu0 depends on group1 +bit2: cpu0 depends on group2 +bit3: cpu0 depends on group3 + 0 + 4 read-write + + + + AFFILIATE_CPU0_SET + Affiliate of Group + 0x904 + 32 + 0x00000000 + 0x0000000F + - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 + LINK + Affiliate groups of cpu0，each bit represents a group +0: no effect +1: the group is assigned to CPU0 + 0 + 4 read-write + + + + AFFILIATE_CPU0_CLEAR + Affiliate of Group + 0x908 + 32 + 0x00000000 + 0x0000000F + - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: the group is not assigned to CPU0 + 0 + 4 read-write + + + + AFFILIATE_CPU0_TOGGLE + Affiliate of Group + 0x90c + 32 + 0x00000000 + 0x0000000F + - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: toggle the result that whether the group is assigned to CPU0 before + 0 + 4 read-write - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + + + + RETENTION_CPU0_VALUE + Retention Contol + 0x920 + 32 + 0x00000000 + 0x000000FF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +bit00: soc_mem is kept on while cpu stop, +bit01: soc_ctx is kept on while cpu stop, +bit02: cpu0_mem is kept on while cpu stop, +bit03: cpu0_ctx is kept on while cpu stop, +bit04: xtal_hold is kept on while cpu stop, +bit05: pll0_hold is kept on while cpu stop, +bit06: pll1_hold is kept on while cpu stop, +bit07: pll2_hold is kept on while cpu stop, 0 - 3 + 8 read-write - PAD_PA11_FUNC_CTL - ALT SELECT - 0x58 + RETENTION_CPU0_SET + Retention Contol + 0x924 32 0x00000000 - 0x0001011F + 0x000000FF - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: keep + 0 + 8 read-write + + + + RETENTION_CPU0_CLEAR + Retention Contol + 0x928 + 32 + 0x00000000 + 0x000000FF + - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: no keep + 0 + 8 read-write + + + + RETENTION_CPU0_TOGGLE + Retention Contol + 0x92c + 32 + 0x00000000 + 0x000000FF + - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: toggle the result that whether the resource is kept on while CPU0 stop before 0 - 5 + 8 read-write - PAD_PA11_PAD_CTL - PAD SETTINGS - 0x5c + POWER_CPU0_STATUS + Power Setting + 0x1000 32 - 0x01010056 - 0x01370177 + 0x80000000 + 0xC0001100 - HYS - schmitt trigger enable -0: disable -1: enable - 24 + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 1 read-write - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 read-write - PS - pull select -0: pull down -1: pull up - 18 + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 1 - read-write + read-only - PE - pull enable -0: pull disable -1: pull enable - 17 + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 1 + read-only + + + + + POWER_CPU0_LF_WAIT + Power Setting + 0x1004 + 32 + 0x00000255 + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 read-write + + + + POWER_CPU0_OFF_WAIT + Power Setting + 0x100c + 32 + 0x00000015 + 0x000FFFFF + - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 read-write + + + + RESET_SOC_CONTROL + Reset Setting + 0x1400 + 32 + 0x80000000 + 0xC0000011 + - OD - open drain -0: open drain disable -1: open drain enable - 8 + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 1 read-write - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold 4 - 2 + 1 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly 0 - 3 + 1 read-write - PAD_PA12_FUNC_CTL - ALT SELECT - 0x60 + RESET_SOC_CONFIG + Reset Setting + 0x1404 32 - 0x00000000 - 0x0001011F + 0x00643203 + 0x00FFFFFF - LOOP_BACK - force input on -0: disable -1: enable + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M 16 - 1 + 8 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M 8 - 1 + 8 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M 0 - 5 + 8 read-write - PAD_PA12_PAD_CTL - PAD SETTINGS - 0x64 + RESET_SOC_COUNTER + Reset Setting + 0x140c 32 - 0x01010056 - 0x01370177 + 0x00000003 + 0x000FFFFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 read-write + + + + RESET_CPU0_CONTROL + Reset Setting + 0x1410 + 32 + 0x80000000 + 0xC0000011 + - OD - open drain -0: open drain disable -1: open drain enable - 8 + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 1 read-write - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold 4 - 2 + 1 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly 0 - 3 + 1 read-write - PAD_PA13_FUNC_CTL - ALT SELECT - 0x68 + RESET_CPU0_CONFIG + Reset Setting + 0x1414 32 - 0x00000000 - 0x0001011F + 0x00643203 + 0x00FFFFFF - LOOP_BACK - force input on -0: disable -1: enable + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M 16 - 1 + 8 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M 8 - 1 + 8 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M 0 - 5 + 8 read-write - PAD_PA13_PAD_CTL - PAD SETTINGS - 0x6c + RESET_CPU0_COUNTER + Reset Setting + 0x141c 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 + 0x00000003 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 read-write + + + + CLOCK_CPU_CLK_TOP_CPU0 + Clock setting + 0x1800 + 32 + 0x00000000 + 0xD0FF0FFF + - PS - pull select -0: pull down -1: pull up - 18 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PE - pull enable -0: pull disable -1: pull enable - 17 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 + SUB1_DIV + ahb bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 20 + 4 read-write - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 + SUB0_DIV + axi bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 16 + 4 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA14_FUNC_CTL - ALT SELECT - 0x70 + CLOCK_CLK_TOP_MCT0 + Clock setting + 0x1804 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA14_PAD_CTL - PAD SETTINGS - 0x74 + CLOCK_CLK_TOP_FEMC + Clock setting + 0x1808 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 read-write + + + + CLOCK_CLK_TOP_XPI0 + Clock setting + 0x180c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + - OD - open drain -0: open drain disable -1: open drain enable - 8 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA15_FUNC_CTL - ALT SELECT - 0x78 + CLOCK_CLK_TOP_XPI1 + Clock setting + 0x1810 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA15_PAD_CTL - PAD SETTINGS - 0x7c + CLOCK_CLK_TOP_TMR0 + Clock setting + 0x1814 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 read-write + + + + CLOCK_CLK_TOP_TMR1 + Clock setting + 0x1818 + 32 + 0x00000000 + 0xD0000FFF + - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - OD - open drain -0: open drain disable -1: open drain enable - 8 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA16_FUNC_CTL - ALT SELECT - 0x80 + CLOCK_CLK_TOP_TMR2 + Clock setting + 0x181c 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA16_PAD_CTL - PAD SETTINGS - 0x84 + CLOCK_CLK_TOP_TMR3 + Clock setting + 0x1820 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 read-write + + + + CLOCK_CLK_TOP_URT0 + Clock setting + 0x1824 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + - OD - open drain -0: open drain disable -1: open drain enable - 8 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA17_FUNC_CTL - ALT SELECT - 0x88 + CLOCK_CLK_TOP_URT1 + Clock setting + 0x1828 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA17_PAD_CTL - PAD SETTINGS - 0x8c + CLOCK_CLK_TOP_URT2 + Clock setting + 0x182c 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 read-write + + + + CLOCK_CLK_TOP_URT3 + Clock setting + 0x1830 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + - OD - open drain -0: open drain disable -1: open drain enable - 8 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA18_FUNC_CTL - ALT SELECT - 0x90 + CLOCK_CLK_TOP_URT4 + Clock setting + 0x1834 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA18_PAD_CTL - PAD SETTINGS - 0x94 + CLOCK_CLK_TOP_URT5 + Clock setting + 0x1838 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 read-write + + + + CLOCK_CLK_TOP_URT6 + Clock setting + 0x183c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + - OD - open drain -0: open drain disable -1: open drain enable - 8 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA19_FUNC_CTL - ALT SELECT - 0x98 + CLOCK_CLK_TOP_URT7 + Clock setting + 0x1840 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA19_PAD_CTL - PAD SETTINGS - 0x9c + CLOCK_CLK_TOP_I2C0 + Clock setting + 0x1844 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 read-write + + + + CLOCK_CLK_TOP_I2C1 + Clock setting + 0x1848 + 32 + 0x00000000 + 0xD0000FFF + - OD - open drain -0: open drain disable -1: open drain enable - 8 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA20_FUNC_CTL - ALT SELECT - 0xa0 + CLOCK_CLK_TOP_I2C2 + Clock setting + 0x184c 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA20_PAD_CTL - PAD SETTINGS - 0xa4 + CLOCK_CLK_TOP_I2C3 + Clock setting + 0x1850 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 read-write + + + + CLOCK_CLK_TOP_SPI0 + Clock setting + 0x1854 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + - OD - open drain -0: open drain disable -1: open drain enable - 8 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA21_FUNC_CTL - ALT SELECT - 0xa8 + CLOCK_CLK_TOP_SPI1 + Clock setting + 0x1858 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA21_PAD_CTL - PAD SETTINGS - 0xac + CLOCK_CLK_TOP_SPI2 + Clock setting + 0x185c 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 read-write + + + + CLOCK_CLK_TOP_SPI3 + Clock setting + 0x1860 + 32 + 0x00000000 + 0xD0000FFF + - OD - open drain -0: open drain disable -1: open drain enable - 8 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA22_FUNC_CTL - ALT SELECT - 0xb0 + CLOCK_CLK_TOP_CAN0 + Clock setting + 0x1864 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA22_PAD_CTL - PAD SETTINGS - 0xb4 + CLOCK_CLK_TOP_CAN1 + Clock setting + 0x1868 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 read-write + + + + CLOCK_CLK_TOP_PTPC + Clock setting + 0x186c + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + - OD - open drain -0: open drain disable -1: open drain enable - 8 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA23_FUNC_CTL - ALT SELECT - 0xb8 + CLOCK_CLK_TOP_ANA0 + Clock setting + 0x1870 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA23_PAD_CTL - PAD SETTINGS - 0xbc + CLOCK_CLK_TOP_ANA1 + Clock setting + 0x1874 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 read-write + + + + CLOCK_CLK_TOP_ANA2 + Clock setting + 0x1878 + 32 + 0x00000000 + 0xD0000FFF + - OD - open drain -0: open drain disable -1: open drain enable - 8 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA24_FUNC_CTL - ALT SELECT - 0xc0 + CLOCK_CLK_TOP_ANA3 + Clock setting + 0x187c 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA24_PAD_CTL - PAD SETTINGS - 0xc4 + CLOCK_CLK_TOP_AUD0 + Clock setting + 0x1880 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 read-write + + + + CLOCK_CLK_TOP_AUD1 + Clock setting + 0x1884 + 32 + 0x00000000 + 0xD0000FFF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + - OD - open drain -0: open drain disable -1: open drain enable - 8 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA25_FUNC_CTL - ALT SELECT - 0xc8 + CLOCK_CLK_TOP_ETH0 + Clock setting + 0x1888 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA25_PAD_CTL - PAD SETTINGS - 0xcc + CLOCK_CLK_TOP_PTP0 + Clock setting + 0x188c 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only - PS - pull select -0: pull down -1: pull up - 18 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 read-write + + + + CLOCK_CLK_TOP_REF0 + Clock setting + 0x1890 + 32 + 0x00000000 + 0xD0000FFF + - OD - open drain -0: open drain disable -1: open drain enable - 8 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 + 8 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA26_FUNC_CTL - ALT SELECT - 0xd0 + CLOCK_CLK_TOP_REF1 + Clock setting + 0x1894 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA26_PAD_CTL - PAD SETTINGS - 0xd4 + CLOCK_CLK_TOP_NTM0 + Clock setting + 0x1898 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000FFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - PE - pull enable -0: pull disable -1: pull enable - 17 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - OD - open drain -0: open drain disable -1: open drain enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + 4 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 3 + 8 read-write - PAD_PA27_FUNC_CTL - ALT SELECT - 0xd8 + CLOCK_CLK_TOP_SDC0 + Clock setting + 0x189c 32 0x00000000 - 0x0001011F + 0xD0000FFF - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll2_clk0 +7:pll2_clk1 8 - 1 + 4 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 0 - 5 + 8 read-write - PAD_PA27_PAD_CTL - PAD SETTINGS - 0xdc + ADCCLK_CLK_TOP_ADC0 + Clock setting + 0x1c00 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000100 - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + read-only - PS - pull select -0: pull down -1: pull up - 18 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - PE - pull enable -0: pull disable -1: pull enable - 17 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + MUX + current mux +0: ana clock +1: ahb clock + 8 1 read-write + + + + ADCCLK_CLK_TOP_ADC1 + Clock setting + 0x1c04 + 32 + 0x00000000 + 0xD0000100 + - OD - open drain -0: open drain disable -1: open drain enable - 8 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 read-write - PAD_PA28_FUNC_CTL - ALT SELECT - 0xe0 + ADCCLK_CLK_TOP_ADC2 + Clock setting + 0x1c08 32 0x00000000 - 0x0001011F + 0xD0000100 - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - ANALOG - select analog pin in pad -0: disable -1: enable - 8 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 + MUX + current mux +0: ana clock +1: ahb clock + 8 + 1 read-write - PAD_PA28_PAD_CTL - PAD SETTINGS - 0xe4 + DACCLK_CLK_TOP_DAC0 + Clock setting + 0x1c0c 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xD0000100 - HYS - schmitt trigger enable -0: disable -1: enable - 24 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + read-only - PS - pull select -0: pull down -1: pull up - 18 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - PE - pull enable -0: pull disable -1: pull enable - 17 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + MUX + current mux +0: ana clock +1: ahb clock + 8 1 read-write + + + + I2SCLK_CLK_TOP_I2S0 + Clock setting + 0x1c10 + 32 + 0x00000000 + 0xD0000100 + - OD - open drain -0: open drain disable -1: open drain enable - 8 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 1 - read-write + read-only - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 1 - read-write + read-only - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 + MUX + current mux +0: aud clock 0 +1: aud clock 1 + 8 + 1 read-write - PAD_PA29_FUNC_CTL - ALT SELECT - 0xe8 + I2SCLK_CLK_TOP_I2S1 + Clock setting + 0x1c14 32 0x00000000 - 0x0001011F + 0xD0000100 - LOOP_BACK - force input on -0: disable -1: enable - 16 + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 1 read-write - ANALOG - select analog pin in pad -0: disable -1: enable + MUX + current mux +0: aud clock 0 +1: aud clock 1 8 1 read-write + + + + GLOBAL00 + Clock senario + 0x2000 + 32 + 0x00000000 + 0x0000000F + - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + MUX + global clock override request +bit0: override to preset0 +bit1: override to preset1 +bit2: override to preset2 +bit3: override to preset3 0 - 5 + 4 read-write - PAD_PA29_PAD_CTL - PAD SETTINGS - 0xec + MONITOR_SLICE0_CONTROL + Clock measure and monitor control + 0x2400 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0x89FFD7FF - HYS - schmitt trigger enable -0: disable -1: enable + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output 24 1 read-write - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 + DIV + output divider + 16 + 8 read-write - PS - pull select -0: pull down -1: pull up - 18 + HIGH + clock frequency higher than upper limit + 15 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 + LOW + clock frequency lower than lower limit + 14 1 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + START + start measurement + 12 1 read-write - OD - open drain -0: open drain disable -1: open drain enable - 8 + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 1 read-write - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + SELECTION + clock measurement selection 0 - 3 + 8 read-write - PAD_PA30_FUNC_CTL - ALT SELECT - 0xf0 + MONITOR_SLICE0_CURRENT + Clock measure result + 0x2404 32 0x00000000 - 0x0001011F + 0xFFFFFFFF - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + MONITOR_SLICE0_LOW_LIMIT + Clock lower limit + 0x2408 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 + FREQUENCY + lower frequency + 0 + 32 read-write + + + + MONITOR_SLICE0_HIGH_LIMIT + Clock upper limit + 0x240c + 32 + 0x00000000 + 0xFFFFFFFF + - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + FREQUENCY + upper frequency 0 - 5 + 32 read-write - PAD_PA30_PAD_CTL - PAD SETTINGS - 0xf4 + MONITOR_SLICE1_CONTROL + Clock measure and monitor control + 0x2420 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0x89FFD7FF - HYS - schmitt trigger enable -0: disable -1: enable + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output 24 1 read-write - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 + DIV + output divider + 16 + 8 read-write - PS - pull select -0: pull down -1: pull up - 18 + HIGH + clock frequency higher than upper limit + 15 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 + LOW + clock frequency lower than lower limit + 14 1 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + START + start measurement + 12 1 read-write - OD - open drain -0: open drain disable -1: open drain enable - 8 + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 1 read-write - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + SELECTION + clock measurement selection 0 - 3 + 8 read-write - PAD_PA31_FUNC_CTL - ALT SELECT - 0xf8 + MONITOR_SLICE1_CURRENT + Clock measure result + 0x2424 32 0x00000000 - 0x0001011F + 0xFFFFFFFF - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + MONITOR_SLICE1_LOW_LIMIT + Clock lower limit + 0x2428 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 + FREQUENCY + lower frequency + 0 + 32 read-write + + + + MONITOR_SLICE1_HIGH_LIMIT + Clock upper limit + 0x242c + 32 + 0x00000000 + 0xFFFFFFFF + - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + FREQUENCY + upper frequency 0 - 5 + 32 read-write - PAD_PA31_PAD_CTL - PAD SETTINGS - 0xfc + MONITOR_SLICE2_CONTROL + Clock measure and monitor control + 0x2440 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0x89FFD7FF - HYS - schmitt trigger enable -0: disable -1: enable - 24 + VALID + result is ready for read +0: not ready +1: result is ready + 31 1 read-write - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 read-write - PS - pull select -0: pull down -1: pull up - 18 + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 + LOW + clock frequency lower than lower limit + 14 1 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + START + start measurement + 12 1 read-write - OD - open drain -0: open drain disable -1: open drain enable - 8 + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 1 read-write - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + SELECTION + clock measurement selection 0 - 3 + 8 read-write - PAD_PB00_FUNC_CTL - ALT SELECT - 0x100 + MONITOR_SLICE2_CURRENT + Clock measure result + 0x2444 32 0x00000000 - 0x0001011F + 0xFFFFFFFF - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + MONITOR_SLICE2_LOW_LIMIT + Clock lower limit + 0x2448 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 + FREQUENCY + lower frequency + 0 + 32 read-write + + + + MONITOR_SLICE2_HIGH_LIMIT + Clock upper limit + 0x244c + 32 + 0x00000000 + 0xFFFFFFFF + - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + FREQUENCY + upper frequency 0 - 5 + 32 read-write - PAD_PB00_PAD_CTL - PAD SETTINGS - 0x104 + MONITOR_SLICE3_CONTROL + Clock measure and monitor control + 0x2460 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0x89FFD7FF - HYS - schmitt trigger enable -0: disable -1: enable + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output 24 1 read-write - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 + DIV + output divider + 16 + 8 read-write - PS - pull select -0: pull down -1: pull up - 18 + HIGH + clock frequency higher than upper limit + 15 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 + LOW + clock frequency lower than lower limit + 14 1 read-write - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + START + start measurement + 12 1 read-write - OD - open drain -0: open drain disable -1: open drain enable - 8 + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 1 read-write - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + SELECTION + clock measurement selection 0 - 3 + 8 read-write - PAD_PB01_FUNC_CTL - ALT SELECT - 0x108 + MONITOR_SLICE3_CURRENT + Clock measure result + 0x2464 32 0x00000000 - 0x0001011F + 0xFFFFFFFF - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + MONITOR_SLICE3_LOW_LIMIT + Clock lower limit + 0x2468 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 + FREQUENCY + lower frequency + 0 + 32 read-write + + + + MONITOR_SLICE3_HIGH_LIMIT + Clock upper limit + 0x246c + 32 + 0x00000000 + 0xFFFFFFFF + - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + FREQUENCY + upper frequency 0 - 5 + 32 read-write - PAD_PB01_PAD_CTL - PAD SETTINGS - 0x10c + CPU_CPU0_LP + CPU0 LP control + 0x2800 32 - 0x01010056 - 0x01370177 + 0x00001000 + 0xFF013703 - HYS - schmitt trigger enable -0: disable -1: enable + WAKE_CNT + CPU0 wake up counter, counter satuated at 255, write 0x00 to clear 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 + 8 read-write - PS - pull select -0: pull down -1: pull up - 18 + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 1 read-write - PE - pull enable -0: pull disable -1: pull enable - 17 + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 1 - read-write + read-only - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 1 - read-write + read-only - OD - open drain -0: open drain disable -1: open drain enable - 8 + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wake up happened + 10 1 read-write - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 1 read-write - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 reset not happened +1: CPU0 reset happened + 8 + 1 read-write - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved 0 - 3 + 2 read-write - PAD_PB02_FUNC_CTL - ALT SELECT - 0x110 + CPU_CPU0_LOCK + CPU0 Lock GPR + 0x2804 32 - 0x00000000 - 0x0001011F + 0x00000002 + 0x0000FFFE - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 read-write - ANALOG - select analog pin in pad -0: disable -1: enable - 8 + LOCK + Lock bit for CPU_LOCK + 1 1 read-write + + + + CPU_CPU0_GPR_GPR0 + CPU0 GPR0 + 0x2808 + 32 + 0x00000000 + 0xFFFFFFFF + - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + GPR + register for software to handle resume, can save resume address or status 0 - 5 + 32 read-write - PAD_PB02_PAD_CTL - PAD SETTINGS - 0x114 + CPU_CPU0_GPR_GPR1 + CPU0 GPR1 + 0x280c 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xFFFFFFFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 + GPR + register for software to handle resume, can save resume address or status + 0 + 32 read-write + + + + CPU_CPU0_GPR_GPR2 + CPU0 GPR2 + 0x2810 + 32 + 0x00000000 + 0xFFFFFFFF + - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 + GPR + register for software to handle resume, can save resume address or status + 0 + 32 read-write + + + + CPU_CPU0_GPR_GPR3 + CPU0 GPR3 + 0x2814 + 32 + 0x00000000 + 0xFFFFFFFF + - PS - pull select -0: pull down -1: pull up - 18 - 1 + GPR + register for software to handle resume, can save resume address or status + 0 + 32 read-write + + + + CPU_CPU0_GPR_GPR4 + CPU0 GPR4 + 0x2818 + 32 + 0x00000000 + 0xFFFFFFFF + - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 + GPR + register for software to handle resume, can save resume address or status + 0 + 32 read-write + + + + CPU_CPU0_GPR_GPR5 + CPU0 GPR5 + 0x281c + 32 + 0x00000000 + 0xFFFFFFFF + - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 + GPR + register for software to handle resume, can save resume address or status + 0 + 32 read-write + + + + CPU_CPU0_GPR_GPR6 + CPU0 GPR6 + 0x2820 + 32 + 0x00000000 + 0xFFFFFFFF + - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 + GPR + register for software to handle resume, can save resume address or status + 0 + 32 read-write + + + + CPU_CPU0_GPR_GPR7 + CPU0 GPR7 + 0x2824 + 32 + 0x00000000 + 0xFFFFFFFF + - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 + GPR + register for software to handle resume, can save resume address or status + 0 + 32 read-write + + + + CPU_CPU0_GPR_GPR8 + CPU0 GPR8 + 0x2828 + 32 + 0x00000000 + 0xFFFFFFFF + - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + GPR + register for software to handle resume, can save resume address or status + 0 + 32 read-write + + + + CPU_CPU0_GPR_GPR9 + CPU0 GPR9 + 0x282c + 32 + 0x00000000 + 0xFFFFFFFF + - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + GPR + register for software to handle resume, can save resume address or status 0 - 3 + 32 read-write - PAD_PB03_FUNC_CTL - ALT SELECT - 0x118 + CPU_CPU0_GPR_GPR10 + CPU0 GPR10 + 0x2830 32 0x00000000 - 0x0001011F + 0xFFFFFFFF - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 + GPR + register for software to handle resume, can save resume address or status + 0 + 32 read-write + + + + CPU_CPU0_GPR_GPR11 + CPU0 GPR11 + 0x2834 + 32 + 0x00000000 + 0xFFFFFFFF + - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 + GPR + register for software to handle resume, can save resume address or status + 0 + 32 read-write + + + + CPU_CPU0_GPR_GPR12 + CPU0 GPR12 + 0x2838 + 32 + 0x00000000 + 0xFFFFFFFF + - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 + GPR + register for software to handle resume, can save resume address or status 0 - 5 + 32 read-write - PAD_PB03_PAD_CTL - PAD SETTINGS - 0x11c + CPU_CPU0_GPR_GPR13 + CPU0 GPR13 + 0x283c 32 - 0x01010056 - 0x01370177 + 0x00000000 + 0xFFFFFFFF - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 + GPR + register for software to handle resume, can save resume address or status + 0 + 32 read-write + + + + CPU_CPU0_WAKEUP_STATUS_STATUS0 + CPU0 wakeup IRQ status + 0x2840 + 32 + 0x00000000 + 0xFFFFFFFF + - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write + STATUS + IRQ values + 0 + 32 + read-only + + + + CPU_CPU0_WAKEUP_STATUS_STATUS1 + CPU0 wakeup IRQ status + 0x2844 + 32 + 0x00000000 + 0xFFFFFFFF + - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write + STATUS + IRQ values + 0 + 32 + read-only + + + + CPU_CPU0_WAKEUP_STATUS_STATUS2 + CPU0 wakeup IRQ status + 0x2848 + 32 + 0x00000000 + 0xFFFFFFFF + - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write + STATUS + IRQ values + 0 + 32 + read-only + + + + CPU_CPU0_WAKEUP_STATUS_STATUS3 + CPU0 wakeup IRQ status + 0x284c + 32 + 0x00000000 + 0xFFFFFFFF + - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write + STATUS + IRQ values + 0 + 32 + read-only + + + + CPU_CPU0_WAKEUP_ENABLE_ENABLE0 + CPU0 wakeup IRQ enable + 0x2880 + 32 + 0x00000000 + 0xFFFFFFFF + - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 + ENABLE + IRQ wakeup enable + 0 + 32 read-write + + + + CPU_CPU0_WAKEUP_ENABLE_ENABLE1 + CPU0 wakeup IRQ enable + 0x2884 + 32 + 0x00000000 + 0xFFFFFFFF + - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 + ENABLE + IRQ wakeup enable + 0 + 32 read-write + + + + CPU_CPU0_WAKEUP_ENABLE_ENABLE2 + CPU0 wakeup IRQ enable + 0x2888 + 32 + 0x00000000 + 0xFFFFFFFF + - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 + ENABLE + IRQ wakeup enable + 0 + 32 read-write + + + + CPU_CPU0_WAKEUP_ENABLE_ENABLE3 + CPU0 wakeup IRQ enable + 0x288c + 32 + 0x00000000 + 0xFFFFFFFF + - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm + ENABLE + IRQ wakeup enable 0 - 3 + 32 read-write + + + + IOC + IOC + IOC + 0xf4040000 + + 0x0 + 0xf40 + registers + + - PAD_PB04_FUNC_CTL + PAD_PA00_FUNC_CTL ALT SELECT - 0x120 + 0x0 32 0x00000000 0x0001011F @@ -73881,9 +64896,9 @@ For pull up: - PAD_PB04_PAD_CTL + PAD_PA00_PAD_CTL PAD SETTINGS - 0x124 + 0x4 32 0x01010056 0x01370177 @@ -73994,9 +65009,9 @@ For pull up: - PAD_PB05_FUNC_CTL + PAD_PA01_FUNC_CTL ALT SELECT - 0x128 + 0x8 32 0x00000000 0x0001011F @@ -74033,9 +65048,9 @@ For pull up: - PAD_PB05_PAD_CTL + PAD_PA01_PAD_CTL PAD SETTINGS - 0x12c + 0xc 32 0x01010056 0x01370177 @@ -74146,9 +65161,9 @@ For pull up: - PAD_PB06_FUNC_CTL + PAD_PA02_FUNC_CTL ALT SELECT - 0x130 + 0x10 32 0x00000000 0x0001011F @@ -74185,9 +65200,9 @@ For pull up: - PAD_PB06_PAD_CTL + PAD_PA02_PAD_CTL PAD SETTINGS - 0x134 + 0x14 32 0x01010056 0x01370177 @@ -74298,9 +65313,9 @@ For pull up: - PAD_PB07_FUNC_CTL + PAD_PA03_FUNC_CTL ALT SELECT - 0x138 + 0x18 32 0x00000000 0x0001011F @@ -74337,9 +65352,9 @@ For pull up: - PAD_PB07_PAD_CTL + PAD_PA03_PAD_CTL PAD SETTINGS - 0x13c + 0x1c 32 0x01010056 0x01370177 @@ -74450,9 +65465,9 @@ For pull up: - PAD_PB08_FUNC_CTL + PAD_PA04_FUNC_CTL ALT SELECT - 0x140 + 0x20 32 0x00000000 0x0001011F @@ -74489,9 +65504,9 @@ For pull up: - PAD_PB08_PAD_CTL + PAD_PA04_PAD_CTL PAD SETTINGS - 0x144 + 0x24 32 0x01010056 0x01370177 @@ -74602,9 +65617,9 @@ For pull up: - PAD_PB09_FUNC_CTL + PAD_PA05_FUNC_CTL ALT SELECT - 0x148 + 0x28 32 0x00000000 0x0001011F @@ -74641,9 +65656,9 @@ For pull up: - PAD_PB09_PAD_CTL + PAD_PA05_PAD_CTL PAD SETTINGS - 0x14c + 0x2c 32 0x01010056 0x01370177 @@ -74754,9 +65769,9 @@ For pull up: - PAD_PB10_FUNC_CTL + PAD_PA06_FUNC_CTL ALT SELECT - 0x150 + 0x30 32 0x00000000 0x0001011F @@ -74793,9 +65808,9 @@ For pull up: - PAD_PB10_PAD_CTL + PAD_PA06_PAD_CTL PAD SETTINGS - 0x154 + 0x34 32 0x01010056 0x01370177 @@ -74906,9 +65921,9 @@ For pull up: - PAD_PB11_FUNC_CTL + PAD_PA07_FUNC_CTL ALT SELECT - 0x158 + 0x38 32 0x00000000 0x0001011F @@ -74945,9 +65960,9 @@ For pull up: - PAD_PB11_PAD_CTL + PAD_PA07_PAD_CTL PAD SETTINGS - 0x15c + 0x3c 32 0x01010056 0x01370177 @@ -75058,9 +66073,9 @@ For pull up: - PAD_PB12_FUNC_CTL + PAD_PA08_FUNC_CTL ALT SELECT - 0x160 + 0x40 32 0x00000000 0x0001011F @@ -75097,9 +66112,9 @@ For pull up: - PAD_PB12_PAD_CTL + PAD_PA08_PAD_CTL PAD SETTINGS - 0x164 + 0x44 32 0x01010056 0x01370177 @@ -75210,9 +66225,9 @@ For pull up: - PAD_PB13_FUNC_CTL + PAD_PA09_FUNC_CTL ALT SELECT - 0x168 + 0x48 32 0x00000000 0x0001011F @@ -75249,9 +66264,9 @@ For pull up: - PAD_PB13_PAD_CTL + PAD_PA09_PAD_CTL PAD SETTINGS - 0x16c + 0x4c 32 0x01010056 0x01370177 @@ -75362,9 +66377,9 @@ For pull up: - PAD_PB14_FUNC_CTL + PAD_PA10_FUNC_CTL ALT SELECT - 0x170 + 0x50 32 0x00000000 0x0001011F @@ -75401,9 +66416,9 @@ For pull up: - PAD_PB14_PAD_CTL + PAD_PA10_PAD_CTL PAD SETTINGS - 0x174 + 0x54 32 0x01010056 0x01370177 @@ -75514,9 +66529,9 @@ For pull up: - PAD_PB15_FUNC_CTL + PAD_PA11_FUNC_CTL ALT SELECT - 0x178 + 0x58 32 0x00000000 0x0001011F @@ -75553,9 +66568,9 @@ For pull up: - PAD_PB15_PAD_CTL + PAD_PA11_PAD_CTL PAD SETTINGS - 0x17c + 0x5c 32 0x01010056 0x01370177 @@ -75666,9 +66681,9 @@ For pull up: - PAD_PB16_FUNC_CTL + PAD_PA12_FUNC_CTL ALT SELECT - 0x180 + 0x60 32 0x00000000 0x0001011F @@ -75705,9 +66720,9 @@ For pull up: - PAD_PB16_PAD_CTL + PAD_PA12_PAD_CTL PAD SETTINGS - 0x184 + 0x64 32 0x01010056 0x01370177 @@ -75818,9 +66833,9 @@ For pull up: - PAD_PB17_FUNC_CTL + PAD_PA13_FUNC_CTL ALT SELECT - 0x188 + 0x68 32 0x00000000 0x0001011F @@ -75857,9 +66872,9 @@ For pull up: - PAD_PB17_PAD_CTL + PAD_PA13_PAD_CTL PAD SETTINGS - 0x18c + 0x6c 32 0x01010056 0x01370177 @@ -75970,9 +66985,9 @@ For pull up: - PAD_PB18_FUNC_CTL + PAD_PA14_FUNC_CTL ALT SELECT - 0x190 + 0x70 32 0x00000000 0x0001011F @@ -76009,9 +67024,9 @@ For pull up: - PAD_PB18_PAD_CTL + PAD_PA14_PAD_CTL PAD SETTINGS - 0x194 + 0x74 32 0x01010056 0x01370177 @@ -76122,9 +67137,9 @@ For pull up: - PAD_PB19_FUNC_CTL + PAD_PA15_FUNC_CTL ALT SELECT - 0x198 + 0x78 32 0x00000000 0x0001011F @@ -76161,9 +67176,9 @@ For pull up: - PAD_PB19_PAD_CTL + PAD_PA15_PAD_CTL PAD SETTINGS - 0x19c + 0x7c 32 0x01010056 0x01370177 @@ -76274,9 +67289,9 @@ For pull up: - PAD_PB20_FUNC_CTL + PAD_PA16_FUNC_CTL ALT SELECT - 0x1a0 + 0x80 32 0x00000000 0x0001011F @@ -76313,9 +67328,9 @@ For pull up: - PAD_PB20_PAD_CTL + PAD_PA16_PAD_CTL PAD SETTINGS - 0x1a4 + 0x84 32 0x01010056 0x01370177 @@ -76426,9 +67441,9 @@ For pull up: - PAD_PB21_FUNC_CTL + PAD_PA17_FUNC_CTL ALT SELECT - 0x1a8 + 0x88 32 0x00000000 0x0001011F @@ -76465,9 +67480,9 @@ For pull up: - PAD_PB21_PAD_CTL + PAD_PA17_PAD_CTL PAD SETTINGS - 0x1ac + 0x8c 32 0x01010056 0x01370177 @@ -76578,9 +67593,9 @@ For pull up: - PAD_PB22_FUNC_CTL + PAD_PA18_FUNC_CTL ALT SELECT - 0x1b0 + 0x90 32 0x00000000 0x0001011F @@ -76617,9 +67632,9 @@ For pull up: - PAD_PB22_PAD_CTL + PAD_PA18_PAD_CTL PAD SETTINGS - 0x1b4 + 0x94 32 0x01010056 0x01370177 @@ -76730,9 +67745,9 @@ For pull up: - PAD_PB23_FUNC_CTL + PAD_PA19_FUNC_CTL ALT SELECT - 0x1b8 + 0x98 32 0x00000000 0x0001011F @@ -76769,9 +67784,9 @@ For pull up: - PAD_PB23_PAD_CTL + PAD_PA19_PAD_CTL PAD SETTINGS - 0x1bc + 0x9c 32 0x01010056 0x01370177 @@ -76882,9 +67897,9 @@ For pull up: - PAD_PB24_FUNC_CTL + PAD_PA20_FUNC_CTL ALT SELECT - 0x1c0 + 0xa0 32 0x00000000 0x0001011F @@ -76921,9 +67936,9 @@ For pull up: - PAD_PB24_PAD_CTL + PAD_PA20_PAD_CTL PAD SETTINGS - 0x1c4 + 0xa4 32 0x01010056 0x01370177 @@ -77034,9 +68049,9 @@ For pull up: - PAD_PB25_FUNC_CTL + PAD_PA21_FUNC_CTL ALT SELECT - 0x1c8 + 0xa8 32 0x00000000 0x0001011F @@ -77073,9 +68088,9 @@ For pull up: - PAD_PB25_PAD_CTL + PAD_PA21_PAD_CTL PAD SETTINGS - 0x1cc + 0xac 32 0x01010056 0x01370177 @@ -77186,9 +68201,9 @@ For pull up: - PAD_PB26_FUNC_CTL + PAD_PA22_FUNC_CTL ALT SELECT - 0x1d0 + 0xb0 32 0x00000000 0x0001011F @@ -77225,9 +68240,9 @@ For pull up: - PAD_PB26_PAD_CTL + PAD_PA22_PAD_CTL PAD SETTINGS - 0x1d4 + 0xb4 32 0x01010056 0x01370177 @@ -77338,9 +68353,9 @@ For pull up: - PAD_PB27_FUNC_CTL + PAD_PA23_FUNC_CTL ALT SELECT - 0x1d8 + 0xb8 32 0x00000000 0x0001011F @@ -77377,9 +68392,9 @@ For pull up: - PAD_PB27_PAD_CTL + PAD_PA23_PAD_CTL PAD SETTINGS - 0x1dc + 0xbc 32 0x01010056 0x01370177 @@ -77490,9 +68505,9 @@ For pull up: - PAD_PB28_FUNC_CTL + PAD_PA24_FUNC_CTL ALT SELECT - 0x1e0 + 0xc0 32 0x00000000 0x0001011F @@ -77529,9 +68544,9 @@ For pull up: - PAD_PB28_PAD_CTL + PAD_PA24_PAD_CTL PAD SETTINGS - 0x1e4 + 0xc4 32 0x01010056 0x01370177 @@ -77642,9 +68657,9 @@ For pull up: - PAD_PB29_FUNC_CTL + PAD_PA25_FUNC_CTL ALT SELECT - 0x1e8 + 0xc8 32 0x00000000 0x0001011F @@ -77681,9 +68696,9 @@ For pull up: - PAD_PB29_PAD_CTL + PAD_PA25_PAD_CTL PAD SETTINGS - 0x1ec + 0xcc 32 0x01010056 0x01370177 @@ -77794,9 +68809,9 @@ For pull up: - PAD_PB30_FUNC_CTL + PAD_PA26_FUNC_CTL ALT SELECT - 0x1f0 + 0xd0 32 0x00000000 0x0001011F @@ -77833,9 +68848,9 @@ For pull up: - PAD_PB30_PAD_CTL + PAD_PA26_PAD_CTL PAD SETTINGS - 0x1f4 + 0xd4 32 0x01010056 0x01370177 @@ -77946,9 +68961,9 @@ For pull up: - PAD_PB31_FUNC_CTL + PAD_PA27_FUNC_CTL ALT SELECT - 0x1f8 + 0xd8 32 0x00000000 0x0001011F @@ -77985,9 +69000,9 @@ For pull up: - PAD_PB31_PAD_CTL + PAD_PA27_PAD_CTL PAD SETTINGS - 0x1fc + 0xdc 32 0x01010056 0x01370177 @@ -78098,9 +69113,9 @@ For pull up: - PAD_PC00_FUNC_CTL + PAD_PA28_FUNC_CTL ALT SELECT - 0x200 + 0xe0 32 0x00000000 0x0001011F @@ -78137,9 +69152,9 @@ For pull up: - PAD_PC00_PAD_CTL + PAD_PA28_PAD_CTL PAD SETTINGS - 0x204 + 0xe4 32 0x01010056 0x01370177 @@ -78250,9 +69265,9 @@ For pull up: - PAD_PC01_FUNC_CTL + PAD_PA29_FUNC_CTL ALT SELECT - 0x208 + 0xe8 32 0x00000000 0x0001011F @@ -78289,9 +69304,9 @@ For pull up: - PAD_PC01_PAD_CTL + PAD_PA29_PAD_CTL PAD SETTINGS - 0x20c + 0xec 32 0x01010056 0x01370177 @@ -78402,9 +69417,9 @@ For pull up: - PAD_PC02_FUNC_CTL + PAD_PA30_FUNC_CTL ALT SELECT - 0x210 + 0xf0 32 0x00000000 0x0001011F @@ -78441,9 +69456,9 @@ For pull up: - PAD_PC02_PAD_CTL + PAD_PA30_PAD_CTL PAD SETTINGS - 0x214 + 0xf4 32 0x01010056 0x01370177 @@ -78554,9 +69569,9 @@ For pull up: - PAD_PC03_FUNC_CTL + PAD_PA31_FUNC_CTL ALT SELECT - 0x218 + 0xf8 32 0x00000000 0x0001011F @@ -78593,9 +69608,9 @@ For pull up: - PAD_PC03_PAD_CTL + PAD_PA31_PAD_CTL PAD SETTINGS - 0x21c + 0xfc 32 0x01010056 0x01370177 @@ -78706,9 +69721,9 @@ For pull up: - PAD_PC04_FUNC_CTL + PAD_PB00_FUNC_CTL ALT SELECT - 0x220 + 0x100 32 0x00000000 0x0001011F @@ -78745,9 +69760,9 @@ For pull up: - PAD_PC04_PAD_CTL + PAD_PB00_PAD_CTL PAD SETTINGS - 0x224 + 0x104 32 0x01010056 0x01370177 @@ -78858,9 +69873,9 @@ For pull up: - PAD_PC05_FUNC_CTL + PAD_PB01_FUNC_CTL ALT SELECT - 0x228 + 0x108 32 0x00000000 0x0001011F @@ -78897,9 +69912,9 @@ For pull up: - PAD_PC05_PAD_CTL + PAD_PB01_PAD_CTL PAD SETTINGS - 0x22c + 0x10c 32 0x01010056 0x01370177 @@ -79010,9 +70025,9 @@ For pull up: - PAD_PC06_FUNC_CTL + PAD_PB02_FUNC_CTL ALT SELECT - 0x230 + 0x110 32 0x00000000 0x0001011F @@ -79049,9 +70064,9 @@ For pull up: - PAD_PC06_PAD_CTL + PAD_PB02_PAD_CTL PAD SETTINGS - 0x234 + 0x114 32 0x01010056 0x01370177 @@ -79162,9 +70177,9 @@ For pull up: - PAD_PC07_FUNC_CTL + PAD_PB03_FUNC_CTL ALT SELECT - 0x238 + 0x118 32 0x00000000 0x0001011F @@ -79201,9 +70216,9 @@ For pull up: - PAD_PC07_PAD_CTL + PAD_PB03_PAD_CTL PAD SETTINGS - 0x23c + 0x11c 32 0x01010056 0x01370177 @@ -79314,9 +70329,9 @@ For pull up: - PAD_PC08_FUNC_CTL + PAD_PB04_FUNC_CTL ALT SELECT - 0x240 + 0x120 32 0x00000000 0x0001011F @@ -79353,9 +70368,9 @@ For pull up: - PAD_PC08_PAD_CTL + PAD_PB04_PAD_CTL PAD SETTINGS - 0x244 + 0x124 32 0x01010056 0x01370177 @@ -79466,9 +70481,9 @@ For pull up: - PAD_PC09_FUNC_CTL + PAD_PB05_FUNC_CTL ALT SELECT - 0x248 + 0x128 32 0x00000000 0x0001011F @@ -79505,9 +70520,9 @@ For pull up: - PAD_PC09_PAD_CTL + PAD_PB05_PAD_CTL PAD SETTINGS - 0x24c + 0x12c 32 0x01010056 0x01370177 @@ -79618,9 +70633,9 @@ For pull up: - PAD_PC10_FUNC_CTL + PAD_PB06_FUNC_CTL ALT SELECT - 0x250 + 0x130 32 0x00000000 0x0001011F @@ -79657,9 +70672,9 @@ For pull up: - PAD_PC10_PAD_CTL + PAD_PB06_PAD_CTL PAD SETTINGS - 0x254 + 0x134 32 0x01010056 0x01370177 @@ -79770,9 +70785,9 @@ For pull up: - PAD_PC11_FUNC_CTL + PAD_PB07_FUNC_CTL ALT SELECT - 0x258 + 0x138 32 0x00000000 0x0001011F @@ -79809,9 +70824,9 @@ For pull up: - PAD_PC11_PAD_CTL + PAD_PB07_PAD_CTL PAD SETTINGS - 0x25c + 0x13c 32 0x01010056 0x01370177 @@ -79922,9 +70937,9 @@ For pull up: - PAD_PC12_FUNC_CTL + PAD_PB08_FUNC_CTL ALT SELECT - 0x260 + 0x140 32 0x00000000 0x0001011F @@ -79961,9 +70976,9 @@ For pull up: - PAD_PC12_PAD_CTL + PAD_PB08_PAD_CTL PAD SETTINGS - 0x264 + 0x144 32 0x01010056 0x01370177 @@ -80074,9 +71089,9 @@ For pull up: - PAD_PC13_FUNC_CTL + PAD_PB09_FUNC_CTL ALT SELECT - 0x268 + 0x148 32 0x00000000 0x0001011F @@ -80113,9 +71128,9 @@ For pull up: - PAD_PC13_PAD_CTL + PAD_PB09_PAD_CTL PAD SETTINGS - 0x26c + 0x14c 32 0x01010056 0x01370177 @@ -80226,9 +71241,9 @@ For pull up: - PAD_PC14_FUNC_CTL + PAD_PB10_FUNC_CTL ALT SELECT - 0x270 + 0x150 32 0x00000000 0x0001011F @@ -80265,9 +71280,9 @@ For pull up: - PAD_PC14_PAD_CTL + PAD_PB10_PAD_CTL PAD SETTINGS - 0x274 + 0x154 32 0x01010056 0x01370177 @@ -80378,9 +71393,9 @@ For pull up: - PAD_PC15_FUNC_CTL + PAD_PB11_FUNC_CTL ALT SELECT - 0x278 + 0x158 32 0x00000000 0x0001011F @@ -80417,9 +71432,9 @@ For pull up: - PAD_PC15_PAD_CTL + PAD_PB11_PAD_CTL PAD SETTINGS - 0x27c + 0x15c 32 0x01010056 0x01370177 @@ -80530,9 +71545,9 @@ For pull up: - PAD_PC16_FUNC_CTL + PAD_PB12_FUNC_CTL ALT SELECT - 0x280 + 0x160 32 0x00000000 0x0001011F @@ -80569,9 +71584,9 @@ For pull up: - PAD_PC16_PAD_CTL + PAD_PB12_PAD_CTL PAD SETTINGS - 0x284 + 0x164 32 0x01010056 0x01370177 @@ -80682,9 +71697,9 @@ For pull up: - PAD_PC17_FUNC_CTL + PAD_PB13_FUNC_CTL ALT SELECT - 0x288 + 0x168 32 0x00000000 0x0001011F @@ -80721,9 +71736,9 @@ For pull up: - PAD_PC17_PAD_CTL + PAD_PB13_PAD_CTL PAD SETTINGS - 0x28c + 0x16c 32 0x01010056 0x01370177 @@ -80834,9 +71849,9 @@ For pull up: - PAD_PC18_FUNC_CTL + PAD_PB14_FUNC_CTL ALT SELECT - 0x290 + 0x170 32 0x00000000 0x0001011F @@ -80873,9 +71888,9 @@ For pull up: - PAD_PC18_PAD_CTL + PAD_PB14_PAD_CTL PAD SETTINGS - 0x294 + 0x174 32 0x01010056 0x01370177 @@ -80986,9 +72001,9 @@ For pull up: - PAD_PC19_FUNC_CTL + PAD_PB15_FUNC_CTL ALT SELECT - 0x298 + 0x178 32 0x00000000 0x0001011F @@ -81025,9 +72040,9 @@ For pull up: - PAD_PC19_PAD_CTL + PAD_PB15_PAD_CTL PAD SETTINGS - 0x29c + 0x17c 32 0x01010056 0x01370177 @@ -81138,9 +72153,9 @@ For pull up: - PAD_PC20_FUNC_CTL + PAD_PB16_FUNC_CTL ALT SELECT - 0x2a0 + 0x180 32 0x00000000 0x0001011F @@ -81177,9 +72192,9 @@ For pull up: - PAD_PC20_PAD_CTL + PAD_PB16_PAD_CTL PAD SETTINGS - 0x2a4 + 0x184 32 0x01010056 0x01370177 @@ -81290,9 +72305,9 @@ For pull up: - PAD_PC21_FUNC_CTL + PAD_PB17_FUNC_CTL ALT SELECT - 0x2a8 + 0x188 32 0x00000000 0x0001011F @@ -81329,9 +72344,9 @@ For pull up: - PAD_PC21_PAD_CTL + PAD_PB17_PAD_CTL PAD SETTINGS - 0x2ac + 0x18c 32 0x01010056 0x01370177 @@ -81442,9 +72457,9 @@ For pull up: - PAD_PC22_FUNC_CTL + PAD_PB18_FUNC_CTL ALT SELECT - 0x2b0 + 0x190 32 0x00000000 0x0001011F @@ -81481,9 +72496,9 @@ For pull up: - PAD_PC22_PAD_CTL + PAD_PB18_PAD_CTL PAD SETTINGS - 0x2b4 + 0x194 32 0x01010056 0x01370177 @@ -81594,9 +72609,9 @@ For pull up: - PAD_PC23_FUNC_CTL + PAD_PB19_FUNC_CTL ALT SELECT - 0x2b8 + 0x198 32 0x00000000 0x0001011F @@ -81633,9 +72648,9 @@ For pull up: - PAD_PC23_PAD_CTL + PAD_PB19_PAD_CTL PAD SETTINGS - 0x2bc + 0x19c 32 0x01010056 0x01370177 @@ -81746,9 +72761,9 @@ For pull up: - PAD_PC24_FUNC_CTL + PAD_PB20_FUNC_CTL ALT SELECT - 0x2c0 + 0x1a0 32 0x00000000 0x0001011F @@ -81785,9 +72800,9 @@ For pull up: - PAD_PC24_PAD_CTL + PAD_PB20_PAD_CTL PAD SETTINGS - 0x2c4 + 0x1a4 32 0x01010056 0x01370177 @@ -81898,9 +72913,9 @@ For pull up: - PAD_PC25_FUNC_CTL + PAD_PB21_FUNC_CTL ALT SELECT - 0x2c8 + 0x1a8 32 0x00000000 0x0001011F @@ -81937,9 +72952,9 @@ For pull up: - PAD_PC25_PAD_CTL + PAD_PB21_PAD_CTL PAD SETTINGS - 0x2cc + 0x1ac 32 0x01010056 0x01370177 @@ -82050,9 +73065,9 @@ For pull up: - PAD_PC26_FUNC_CTL + PAD_PB22_FUNC_CTL ALT SELECT - 0x2d0 + 0x1b0 32 0x00000000 0x0001011F @@ -82089,9 +73104,9 @@ For pull up: - PAD_PC26_PAD_CTL + PAD_PB22_PAD_CTL PAD SETTINGS - 0x2d4 + 0x1b4 32 0x01010056 0x01370177 @@ -82202,9 +73217,9 @@ For pull up: - PAD_PC27_FUNC_CTL + PAD_PB23_FUNC_CTL ALT SELECT - 0x2d8 + 0x1b8 32 0x00000000 0x0001011F @@ -82241,9 +73256,9 @@ For pull up: - PAD_PC27_PAD_CTL + PAD_PB23_PAD_CTL PAD SETTINGS - 0x2dc + 0x1bc 32 0x01010056 0x01370177 @@ -82354,9 +73369,9 @@ For pull up: - PAD_PC28_FUNC_CTL + PAD_PB24_FUNC_CTL ALT SELECT - 0x2e0 + 0x1c0 32 0x00000000 0x0001011F @@ -82393,9 +73408,9 @@ For pull up: - PAD_PC28_PAD_CTL + PAD_PB24_PAD_CTL PAD SETTINGS - 0x2e4 + 0x1c4 32 0x01010056 0x01370177 @@ -82506,9 +73521,9 @@ For pull up: - PAD_PC29_FUNC_CTL + PAD_PB25_FUNC_CTL ALT SELECT - 0x2e8 + 0x1c8 32 0x00000000 0x0001011F @@ -82545,9 +73560,9 @@ For pull up: - PAD_PC29_PAD_CTL + PAD_PB25_PAD_CTL PAD SETTINGS - 0x2ec + 0x1cc 32 0x01010056 0x01370177 @@ -82658,9 +73673,9 @@ For pull up: - PAD_PC30_FUNC_CTL + PAD_PB26_FUNC_CTL ALT SELECT - 0x2f0 + 0x1d0 32 0x00000000 0x0001011F @@ -82697,9 +73712,9 @@ For pull up: - PAD_PC30_PAD_CTL + PAD_PB26_PAD_CTL PAD SETTINGS - 0x2f4 + 0x1d4 32 0x01010056 0x01370177 @@ -82810,9 +73825,9 @@ For pull up: - PAD_PC31_FUNC_CTL + PAD_PB27_FUNC_CTL ALT SELECT - 0x2f8 + 0x1d8 32 0x00000000 0x0001011F @@ -82849,9 +73864,9 @@ For pull up: - PAD_PC31_PAD_CTL + PAD_PB27_PAD_CTL PAD SETTINGS - 0x2fc + 0x1dc 32 0x01010056 0x01370177 @@ -82962,9 +73977,9 @@ For pull up: - PAD_PD00_FUNC_CTL + PAD_PB28_FUNC_CTL ALT SELECT - 0x300 + 0x1e0 32 0x00000000 0x0001011F @@ -83001,9 +74016,9 @@ For pull up: - PAD_PD00_PAD_CTL + PAD_PB28_PAD_CTL PAD SETTINGS - 0x304 + 0x1e4 32 0x01010056 0x01370177 @@ -83114,9 +74129,9 @@ For pull up: - PAD_PD01_FUNC_CTL + PAD_PB29_FUNC_CTL ALT SELECT - 0x308 + 0x1e8 32 0x00000000 0x0001011F @@ -83153,9 +74168,9 @@ For pull up: - PAD_PD01_PAD_CTL + PAD_PB29_PAD_CTL PAD SETTINGS - 0x30c + 0x1ec 32 0x01010056 0x01370177 @@ -83266,9 +74281,9 @@ For pull up: - PAD_PD02_FUNC_CTL + PAD_PB30_FUNC_CTL ALT SELECT - 0x310 + 0x1f0 32 0x00000000 0x0001011F @@ -83305,9 +74320,9 @@ For pull up: - PAD_PD02_PAD_CTL + PAD_PB30_PAD_CTL PAD SETTINGS - 0x314 + 0x1f4 32 0x01010056 0x01370177 @@ -83418,9 +74433,9 @@ For pull up: - PAD_PD03_FUNC_CTL + PAD_PB31_FUNC_CTL ALT SELECT - 0x318 + 0x1f8 32 0x00000000 0x0001011F @@ -83457,9 +74472,9 @@ For pull up: - PAD_PD03_PAD_CTL + PAD_PB31_PAD_CTL PAD SETTINGS - 0x31c + 0x1fc 32 0x01010056 0x01370177 @@ -83570,9 +74585,9 @@ For pull up: - PAD_PD04_FUNC_CTL + PAD_PC00_FUNC_CTL ALT SELECT - 0x320 + 0x200 32 0x00000000 0x0001011F @@ -83609,9 +74624,9 @@ For pull up: - PAD_PD04_PAD_CTL + PAD_PC00_PAD_CTL PAD SETTINGS - 0x324 + 0x204 32 0x01010056 0x01370177 @@ -83722,9 +74737,9 @@ For pull up: - PAD_PD05_FUNC_CTL + PAD_PC01_FUNC_CTL ALT SELECT - 0x328 + 0x208 32 0x00000000 0x0001011F @@ -83761,9 +74776,9 @@ For pull up: - PAD_PD05_PAD_CTL + PAD_PC01_PAD_CTL PAD SETTINGS - 0x32c + 0x20c 32 0x01010056 0x01370177 @@ -83874,9 +74889,9 @@ For pull up: - PAD_PD06_FUNC_CTL + PAD_PC02_FUNC_CTL ALT SELECT - 0x330 + 0x210 32 0x00000000 0x0001011F @@ -83913,9 +74928,9 @@ For pull up: - PAD_PD06_PAD_CTL + PAD_PC02_PAD_CTL PAD SETTINGS - 0x334 + 0x214 32 0x01010056 0x01370177 @@ -84026,9 +75041,9 @@ For pull up: - PAD_PD07_FUNC_CTL + PAD_PC03_FUNC_CTL ALT SELECT - 0x338 + 0x218 32 0x00000000 0x0001011F @@ -84065,9 +75080,9 @@ For pull up: - PAD_PD07_PAD_CTL + PAD_PC03_PAD_CTL PAD SETTINGS - 0x33c + 0x21c 32 0x01010056 0x01370177 @@ -84178,9 +75193,9 @@ For pull up: - PAD_PD08_FUNC_CTL + PAD_PC04_FUNC_CTL ALT SELECT - 0x340 + 0x220 32 0x00000000 0x0001011F @@ -84217,9 +75232,9 @@ For pull up: - PAD_PD08_PAD_CTL + PAD_PC04_PAD_CTL PAD SETTINGS - 0x344 + 0x224 32 0x01010056 0x01370177 @@ -84330,9 +75345,9 @@ For pull up: - PAD_PD09_FUNC_CTL + PAD_PC05_FUNC_CTL ALT SELECT - 0x348 + 0x228 32 0x00000000 0x0001011F @@ -84369,9 +75384,9 @@ For pull up: - PAD_PD09_PAD_CTL + PAD_PC05_PAD_CTL PAD SETTINGS - 0x34c + 0x22c 32 0x01010056 0x01370177 @@ -84482,9 +75497,9 @@ For pull up: - PAD_PD10_FUNC_CTL + PAD_PC06_FUNC_CTL ALT SELECT - 0x350 + 0x230 32 0x00000000 0x0001011F @@ -84521,9 +75536,9 @@ For pull up: - PAD_PD10_PAD_CTL + PAD_PC06_PAD_CTL PAD SETTINGS - 0x354 + 0x234 32 0x01010056 0x01370177 @@ -84634,9 +75649,9 @@ For pull up: - PAD_PD11_FUNC_CTL + PAD_PC07_FUNC_CTL ALT SELECT - 0x358 + 0x238 32 0x00000000 0x0001011F @@ -84673,9 +75688,9 @@ For pull up: - PAD_PD11_PAD_CTL + PAD_PC07_PAD_CTL PAD SETTINGS - 0x35c + 0x23c 32 0x01010056 0x01370177 @@ -84786,9 +75801,9 @@ For pull up: - PAD_PD12_FUNC_CTL + PAD_PC08_FUNC_CTL ALT SELECT - 0x360 + 0x240 32 0x00000000 0x0001011F @@ -84825,9 +75840,9 @@ For pull up: - PAD_PD12_PAD_CTL + PAD_PC08_PAD_CTL PAD SETTINGS - 0x364 + 0x244 32 0x01010056 0x01370177 @@ -84938,9 +75953,9 @@ For pull up: - PAD_PD13_FUNC_CTL + PAD_PC09_FUNC_CTL ALT SELECT - 0x368 + 0x248 32 0x00000000 0x0001011F @@ -84977,9 +75992,9 @@ For pull up: - PAD_PD13_PAD_CTL + PAD_PC09_PAD_CTL PAD SETTINGS - 0x36c + 0x24c 32 0x01010056 0x01370177 @@ -85090,9 +76105,9 @@ For pull up: - PAD_PD14_FUNC_CTL + PAD_PC10_FUNC_CTL ALT SELECT - 0x370 + 0x250 32 0x00000000 0x0001011F @@ -85129,9 +76144,9 @@ For pull up: - PAD_PD14_PAD_CTL + PAD_PC10_PAD_CTL PAD SETTINGS - 0x374 + 0x254 32 0x01010056 0x01370177 @@ -85242,9 +76257,9 @@ For pull up: - PAD_PD15_FUNC_CTL + PAD_PC11_FUNC_CTL ALT SELECT - 0x378 + 0x258 32 0x00000000 0x0001011F @@ -85281,9 +76296,9 @@ For pull up: - PAD_PD15_PAD_CTL + PAD_PC11_PAD_CTL PAD SETTINGS - 0x37c + 0x25c 32 0x01010056 0x01370177 @@ -85394,9 +76409,9 @@ For pull up: - PAD_PD16_FUNC_CTL + PAD_PC12_FUNC_CTL ALT SELECT - 0x380 + 0x260 32 0x00000000 0x0001011F @@ -85433,9 +76448,9 @@ For pull up: - PAD_PD16_PAD_CTL + PAD_PC12_PAD_CTL PAD SETTINGS - 0x384 + 0x264 32 0x01010056 0x01370177 @@ -85546,9 +76561,9 @@ For pull up: - PAD_PD17_FUNC_CTL + PAD_PC13_FUNC_CTL ALT SELECT - 0x388 + 0x268 32 0x00000000 0x0001011F @@ -85585,9 +76600,9 @@ For pull up: - PAD_PD17_PAD_CTL + PAD_PC13_PAD_CTL PAD SETTINGS - 0x38c + 0x26c 32 0x01010056 0x01370177 @@ -85698,9 +76713,9 @@ For pull up: - PAD_PD18_FUNC_CTL + PAD_PC14_FUNC_CTL ALT SELECT - 0x390 + 0x270 32 0x00000000 0x0001011F @@ -85737,9 +76752,9 @@ For pull up: - PAD_PD18_PAD_CTL + PAD_PC14_PAD_CTL PAD SETTINGS - 0x394 + 0x274 32 0x01010056 0x01370177 @@ -85850,9 +76865,9 @@ For pull up: - PAD_PD19_FUNC_CTL + PAD_PC15_FUNC_CTL ALT SELECT - 0x398 + 0x278 32 0x00000000 0x0001011F @@ -85889,9 +76904,9 @@ For pull up: - PAD_PD19_PAD_CTL + PAD_PC15_PAD_CTL PAD SETTINGS - 0x39c + 0x27c 32 0x01010056 0x01370177 @@ -86002,9 +77017,9 @@ For pull up: - PAD_PD20_FUNC_CTL + PAD_PC16_FUNC_CTL ALT SELECT - 0x3a0 + 0x280 32 0x00000000 0x0001011F @@ -86041,9 +77056,9 @@ For pull up: - PAD_PD20_PAD_CTL + PAD_PC16_PAD_CTL PAD SETTINGS - 0x3a4 + 0x284 32 0x01010056 0x01370177 @@ -86154,9 +77169,9 @@ For pull up: - PAD_PD21_FUNC_CTL + PAD_PC17_FUNC_CTL ALT SELECT - 0x3a8 + 0x288 32 0x00000000 0x0001011F @@ -86193,9 +77208,9 @@ For pull up: - PAD_PD21_PAD_CTL + PAD_PC17_PAD_CTL PAD SETTINGS - 0x3ac + 0x28c 32 0x01010056 0x01370177 @@ -86306,9 +77321,9 @@ For pull up: - PAD_PD22_FUNC_CTL + PAD_PC18_FUNC_CTL ALT SELECT - 0x3b0 + 0x290 32 0x00000000 0x0001011F @@ -86345,9 +77360,9 @@ For pull up: - PAD_PD22_PAD_CTL + PAD_PC18_PAD_CTL PAD SETTINGS - 0x3b4 + 0x294 32 0x01010056 0x01370177 @@ -86458,9 +77473,9 @@ For pull up: - PAD_PD23_FUNC_CTL + PAD_PC19_FUNC_CTL ALT SELECT - 0x3b8 + 0x298 32 0x00000000 0x0001011F @@ -86497,9 +77512,9 @@ For pull up: - PAD_PD23_PAD_CTL + PAD_PC19_PAD_CTL PAD SETTINGS - 0x3bc + 0x29c 32 0x01010056 0x01370177 @@ -86610,9 +77625,9 @@ For pull up: - PAD_PX00_FUNC_CTL + PAD_PC20_FUNC_CTL ALT SELECT - 0xd00 + 0x2a0 32 0x00000000 0x0001011F @@ -86649,9 +77664,9 @@ For pull up: - PAD_PX00_PAD_CTL + PAD_PC20_PAD_CTL PAD SETTINGS - 0xd04 + 0x2a4 32 0x01010056 0x01370177 @@ -86762,9 +77777,9 @@ For pull up: - PAD_PX01_FUNC_CTL + PAD_PC21_FUNC_CTL ALT SELECT - 0xd08 + 0x2a8 32 0x00000000 0x0001011F @@ -86801,9 +77816,9 @@ For pull up: - PAD_PX01_PAD_CTL + PAD_PC21_PAD_CTL PAD SETTINGS - 0xd0c + 0x2ac 32 0x01010056 0x01370177 @@ -86914,9 +77929,9 @@ For pull up: - PAD_PX02_FUNC_CTL + PAD_PC22_FUNC_CTL ALT SELECT - 0xd10 + 0x2b0 32 0x00000000 0x0001011F @@ -86953,9 +77968,9 @@ For pull up: - PAD_PX02_PAD_CTL + PAD_PC22_PAD_CTL PAD SETTINGS - 0xd14 + 0x2b4 32 0x01010056 0x01370177 @@ -87066,9 +78081,9 @@ For pull up: - PAD_PX03_FUNC_CTL + PAD_PC23_FUNC_CTL ALT SELECT - 0xd18 + 0x2b8 32 0x00000000 0x0001011F @@ -87105,9 +78120,9 @@ For pull up: - PAD_PX03_PAD_CTL + PAD_PC23_PAD_CTL PAD SETTINGS - 0xd1c + 0x2bc 32 0x01010056 0x01370177 @@ -87218,9 +78233,9 @@ For pull up: - PAD_PX04_FUNC_CTL + PAD_PC24_FUNC_CTL ALT SELECT - 0xd20 + 0x2c0 32 0x00000000 0x0001011F @@ -87257,9 +78272,9 @@ For pull up: - PAD_PX04_PAD_CTL + PAD_PC24_PAD_CTL PAD SETTINGS - 0xd24 + 0x2c4 32 0x01010056 0x01370177 @@ -87370,9 +78385,9 @@ For pull up: - PAD_PX05_FUNC_CTL + PAD_PC25_FUNC_CTL ALT SELECT - 0xd28 + 0x2c8 32 0x00000000 0x0001011F @@ -87409,9 +78424,9 @@ For pull up: - PAD_PX05_PAD_CTL + PAD_PC25_PAD_CTL PAD SETTINGS - 0xd2c + 0x2cc 32 0x01010056 0x01370177 @@ -87522,9 +78537,9 @@ For pull up: - PAD_PX06_FUNC_CTL + PAD_PC26_FUNC_CTL ALT SELECT - 0xd30 + 0x2d0 32 0x00000000 0x0001011F @@ -87561,9 +78576,9 @@ For pull up: - PAD_PX06_PAD_CTL + PAD_PC26_PAD_CTL PAD SETTINGS - 0xd34 + 0x2d4 32 0x01010056 0x01370177 @@ -87674,9 +78689,9 @@ For pull up: - PAD_PX07_FUNC_CTL + PAD_PC27_FUNC_CTL ALT SELECT - 0xd38 + 0x2d8 32 0x00000000 0x0001011F @@ -87713,9 +78728,9 @@ For pull up: - PAD_PX07_PAD_CTL + PAD_PC27_PAD_CTL PAD SETTINGS - 0xd3c + 0x2dc 32 0x01010056 0x01370177 @@ -87826,9 +78841,9 @@ For pull up: - PAD_PY00_FUNC_CTL + PAD_PX00_FUNC_CTL ALT SELECT - 0xe00 + 0xd00 32 0x00000000 0x0001011F @@ -87865,9 +78880,9 @@ For pull up: - PAD_PY00_PAD_CTL + PAD_PX00_PAD_CTL PAD SETTINGS - 0xe04 + 0xd04 32 0x01010056 0x01370177 @@ -87978,9 +78993,9 @@ For pull up: - PAD_PY01_FUNC_CTL + PAD_PX01_FUNC_CTL ALT SELECT - 0xe08 + 0xd08 32 0x00000000 0x0001011F @@ -88017,9 +79032,9 @@ For pull up: - PAD_PY01_PAD_CTL + PAD_PX01_PAD_CTL PAD SETTINGS - 0xe0c + 0xd0c 32 0x01010056 0x01370177 @@ -88130,9 +79145,9 @@ For pull up: - PAD_PY02_FUNC_CTL + PAD_PX02_FUNC_CTL ALT SELECT - 0xe10 + 0xd10 32 0x00000000 0x0001011F @@ -88169,9 +79184,9 @@ For pull up: - PAD_PY02_PAD_CTL + PAD_PX02_PAD_CTL PAD SETTINGS - 0xe14 + 0xd14 32 0x01010056 0x01370177 @@ -88282,9 +79297,9 @@ For pull up: - PAD_PY03_FUNC_CTL + PAD_PX03_FUNC_CTL ALT SELECT - 0xe18 + 0xd18 32 0x00000000 0x0001011F @@ -88321,9 +79336,9 @@ For pull up: - PAD_PY03_PAD_CTL + PAD_PX03_PAD_CTL PAD SETTINGS - 0xe1c + 0xd1c 32 0x01010056 0x01370177 @@ -88434,9 +79449,9 @@ For pull up: - PAD_PY04_FUNC_CTL + PAD_PX04_FUNC_CTL ALT SELECT - 0xe20 + 0xd20 32 0x00000000 0x0001011F @@ -88473,9 +79488,9 @@ For pull up: - PAD_PY04_PAD_CTL + PAD_PX04_PAD_CTL PAD SETTINGS - 0xe24 + 0xd24 32 0x01010056 0x01370177 @@ -88586,9 +79601,9 @@ For pull up: - PAD_PY05_FUNC_CTL + PAD_PX05_FUNC_CTL ALT SELECT - 0xe28 + 0xd28 32 0x00000000 0x0001011F @@ -88625,9 +79640,9 @@ For pull up: - PAD_PY05_PAD_CTL + PAD_PX05_PAD_CTL PAD SETTINGS - 0xe2c + 0xd2c 32 0x01010056 0x01370177 @@ -88738,9 +79753,9 @@ For pull up: - PAD_PY06_FUNC_CTL + PAD_PX06_FUNC_CTL ALT SELECT - 0xe30 + 0xd30 32 0x00000000 0x0001011F @@ -88777,9 +79792,9 @@ For pull up: - PAD_PY06_PAD_CTL + PAD_PX06_PAD_CTL PAD SETTINGS - 0xe34 + 0xd34 32 0x01010056 0x01370177 @@ -88890,9 +79905,9 @@ For pull up: - PAD_PY07_FUNC_CTL + PAD_PX07_FUNC_CTL ALT SELECT - 0xe38 + 0xd38 32 0x00000000 0x0001011F @@ -88929,9 +79944,9 @@ For pull up: - PAD_PY07_PAD_CTL + PAD_PX07_PAD_CTL PAD SETTINGS - 0xe3c + 0xd3c 32 0x01010056 0x01370177 @@ -89042,9 +80057,9 @@ For pull up: - PAD_PY08_FUNC_CTL + PAD_PY00_FUNC_CTL ALT SELECT - 0xe40 + 0xe00 32 0x00000000 0x0001011F @@ -89081,9 +80096,9 @@ For pull up: - PAD_PY08_PAD_CTL + PAD_PY00_PAD_CTL PAD SETTINGS - 0xe44 + 0xe04 32 0x01010056 0x01370177 @@ -89194,9 +80209,9 @@ For pull up: - PAD_PY09_FUNC_CTL + PAD_PY01_FUNC_CTL ALT SELECT - 0xe48 + 0xe08 32 0x00000000 0x0001011F @@ -89233,9 +80248,9 @@ For pull up: - PAD_PY09_PAD_CTL + PAD_PY01_PAD_CTL PAD SETTINGS - 0xe4c + 0xe0c 32 0x01010056 0x01370177 @@ -89346,9 +80361,9 @@ For pull up: - PAD_PY10_FUNC_CTL + PAD_PY02_FUNC_CTL ALT SELECT - 0xe50 + 0xe10 32 0x00000000 0x0001011F @@ -89385,9 +80400,9 @@ For pull up: - PAD_PY10_PAD_CTL + PAD_PY02_PAD_CTL PAD SETTINGS - 0xe54 + 0xe14 32 0x01010056 0x01370177 @@ -89498,9 +80513,9 @@ For pull up: - PAD_PY11_FUNC_CTL + PAD_PY03_FUNC_CTL ALT SELECT - 0xe58 + 0xe18 32 0x00000000 0x0001011F @@ -89537,9 +80552,9 @@ For pull up: - PAD_PY11_PAD_CTL + PAD_PY03_PAD_CTL PAD SETTINGS - 0xe5c + 0xe1c 32 0x01010056 0x01370177 @@ -89650,9 +80665,9 @@ For pull up: - PAD_PZ00_FUNC_CTL + PAD_PY04_FUNC_CTL ALT SELECT - 0xf00 + 0xe20 32 0x00000000 0x0001011F @@ -89689,9 +80704,9 @@ For pull up: - PAD_PZ00_PAD_CTL + PAD_PY04_PAD_CTL PAD SETTINGS - 0xf04 + 0xe24 32 0x01010056 0x01370177 @@ -89802,9 +80817,9 @@ For pull up: - PAD_PZ01_FUNC_CTL + PAD_PY05_FUNC_CTL ALT SELECT - 0xf08 + 0xe28 32 0x00000000 0x0001011F @@ -89841,9 +80856,9 @@ For pull up: - PAD_PZ01_PAD_CTL + PAD_PY05_PAD_CTL PAD SETTINGS - 0xf0c + 0xe2c 32 0x01010056 0x01370177 @@ -89954,9 +80969,9 @@ For pull up: - PAD_PZ02_FUNC_CTL + PAD_PY06_FUNC_CTL ALT SELECT - 0xf10 + 0xe30 32 0x00000000 0x0001011F @@ -89993,9 +81008,9 @@ For pull up: - PAD_PZ02_PAD_CTL + PAD_PY06_PAD_CTL PAD SETTINGS - 0xf14 + 0xe34 32 0x01010056 0x01370177 @@ -90106,9 +81121,9 @@ For pull up: - PAD_PZ03_FUNC_CTL + PAD_PY07_FUNC_CTL ALT SELECT - 0xf18 + 0xe38 32 0x00000000 0x0001011F @@ -90145,9 +81160,9 @@ For pull up: - PAD_PZ03_PAD_CTL + PAD_PY07_PAD_CTL PAD SETTINGS - 0xf1c + 0xe3c 32 0x01010056 0x01370177 @@ -90258,9 +81273,9 @@ For pull up: - PAD_PZ04_FUNC_CTL + PAD_PZ00_FUNC_CTL ALT SELECT - 0xf20 + 0xf00 32 0x00000000 0x0001011F @@ -90297,9 +81312,9 @@ For pull up: - PAD_PZ04_PAD_CTL + PAD_PZ00_PAD_CTL PAD SETTINGS - 0xf24 + 0xf04 32 0x01010056 0x01370177 @@ -90410,9 +81425,9 @@ For pull up: - PAD_PZ05_FUNC_CTL + PAD_PZ01_FUNC_CTL ALT SELECT - 0xf28 + 0xf08 32 0x00000000 0x0001011F @@ -90449,9 +81464,9 @@ For pull up: - PAD_PZ05_PAD_CTL + PAD_PZ01_PAD_CTL PAD SETTINGS - 0xf2c + 0xf0c 32 0x01010056 0x01370177 @@ -90562,9 +81577,9 @@ For pull up: - PAD_PZ06_FUNC_CTL + PAD_PZ02_FUNC_CTL ALT SELECT - 0xf30 + 0xf10 32 0x00000000 0x0001011F @@ -90601,9 +81616,9 @@ For pull up: - PAD_PZ06_PAD_CTL + PAD_PZ02_PAD_CTL PAD SETTINGS - 0xf34 + 0xf14 32 0x01010056 0x01370177 @@ -90714,9 +81729,9 @@ For pull up: - PAD_PZ07_FUNC_CTL + PAD_PZ03_FUNC_CTL ALT SELECT - 0xf38 + 0xf18 32 0x00000000 0x0001011F @@ -90753,9 +81768,9 @@ For pull up: - PAD_PZ07_PAD_CTL + PAD_PZ03_PAD_CTL PAD SETTINGS - 0xf3c + 0xf1c 32 0x01010056 0x01370177 @@ -90866,9 +81881,9 @@ For pull up: - PAD_PZ08_FUNC_CTL + PAD_PZ04_FUNC_CTL ALT SELECT - 0xf40 + 0xf20 32 0x00000000 0x0001011F @@ -90905,9 +81920,9 @@ For pull up: - PAD_PZ08_PAD_CTL + PAD_PZ04_PAD_CTL PAD SETTINGS - 0xf44 + 0xf24 32 0x01010056 0x01370177 @@ -91018,9 +82033,9 @@ For pull up: - PAD_PZ09_FUNC_CTL + PAD_PZ05_FUNC_CTL ALT SELECT - 0xf48 + 0xf28 32 0x00000000 0x0001011F @@ -91057,9 +82072,9 @@ For pull up: - PAD_PZ09_PAD_CTL + PAD_PZ05_PAD_CTL PAD SETTINGS - 0xf4c + 0xf2c 32 0x01010056 0x01370177 @@ -91170,9 +82185,9 @@ For pull up: - PAD_PZ10_FUNC_CTL + PAD_PZ06_FUNC_CTL ALT SELECT - 0xf50 + 0xf30 32 0x00000000 0x0001011F @@ -91209,9 +82224,9 @@ For pull up: - PAD_PZ10_PAD_CTL + PAD_PZ06_PAD_CTL PAD SETTINGS - 0xf54 + 0xf34 32 0x01010056 0x01370177 @@ -91322,9 +82337,9 @@ For pull up: - PAD_PZ11_FUNC_CTL + PAD_PZ07_FUNC_CTL ALT SELECT - 0xf58 + 0xf38 32 0x00000000 0x0001011F @@ -91361,9 +82376,9 @@ For pull up: - PAD_PZ11_PAD_CTL + PAD_PZ07_PAD_CTL PAD SETTINGS - 0xf5c + 0xf3c 32 0x01010056 0x01370177 @@ -97811,7 +88826,7 @@ bit19: RTC alarm interrupt SCG control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: clock gated according to low power flow +00,01: reserved 10: clock is always off 11: clock is always on bit0-1: fuse @@ -100317,7 +91332,7 @@ bit4: GPIO 0x0 32 0x00000000 - 0x811F1F1F + 0x831F1F1F VBG_TRIMMED @@ -100328,6 +91343,15 @@ bit4: GPIO 1 read-write + + LP_MODE + Bandgap works in low power mode +0: not in low power mode +1: bandgap work in low power mode + 25 + 1 + read-write + POWER_SAVE Bandgap works in power save mode diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h index c7676218..6c662767 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_batt_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -55,27 +55,5 @@ #define IOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -/* IOC_PZ08_FUNC_CTL function mux definitions */ -#define IOC_PZ08_FUNC_CTL_BGPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ08_FUNC_CTL_TAMP_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ09_FUNC_CTL function mux definitions */ -#define IOC_PZ09_FUNC_CTL_BGPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ09_FUNC_CTL_TAMP_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ10_FUNC_CTL function mux definitions */ -#define IOC_PZ10_FUNC_CTL_BGPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ10_FUNC_CTL_HIBERNATE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ10_FUNC_CTL_TAMP_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PZ11_FUNC_CTL function mux definitions */ -#define IOC_PZ11_FUNC_CTL_BGPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ11_FUNC_CTL_STANDBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ11_FUNC_CTL_TAMP_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - #endif /* HPM_BATT_IOMUX_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_drv.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_drv.h new file mode 100644 index 00000000..00dfb6fc --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_drv.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BCFG_DRV_H +#define HPM_BCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_bcfg_regs.h" + +/** + * + * @brief BCFG driver APIs + * @defgroup bcfg_interface BCFG driver APIs + * @ingroup io_interfaces + * @{ + */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief enable VBAT LP mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_enable_lp_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG |= BCFG_VBG_CFG_LP_MODE_MASK; +} + +/** + * @brief disable VBAT LP mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_disable_lp_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG &= ~BCFG_VBG_CFG_LP_MODE_MASK; +} + +/** + * @brief enable power save mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_enable_power_save_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG |= BCFG_VBG_CFG_POWER_SAVE_MASK; +} + +/** + * @brief disable power save mode + * + * @param[in] ptr base address + */ +static inline void bcfg_vbg_disable_power_save_mode(BCFG_Type *ptr) +{ + ptr->VBG_CFG &= ~BCFG_VBG_CFG_POWER_SAVE_MASK; +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BCFG_DRV_H */ + diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_regs.h new file mode 100644 index 00000000..b1933ddb --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_bcfg_regs.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BCFG_H +#define HPM_BCFG_H + +typedef struct { + __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */ + __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ + __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */ + __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */ + __RW uint32_t CLK_CFG; /* 0x10: Clock config */ +} BCFG_Type; + + +/* Bitfield definition for register: VBG_CFG */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL) +#define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U) +#define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) +#define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) + +/* + * LP_MODE (RW) + * + * Bandgap works in low power mode + * 0: not in low power mode + * 1: bandgap work in low power mode + */ +#define BCFG_VBG_CFG_LP_MODE_MASK (0x2000000UL) +#define BCFG_VBG_CFG_LP_MODE_SHIFT (25U) +#define BCFG_VBG_CFG_LP_MODE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_LP_MODE_SHIFT) & BCFG_VBG_CFG_LP_MODE_MASK) +#define BCFG_VBG_CFG_LP_MODE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_LP_MODE_MASK) >> BCFG_VBG_CFG_LP_MODE_SHIFT) + +/* + * POWER_SAVE (RW) + * + * Bandgap works in power save mode + * 0: not in power save mode + * 1: bandgap work in power save mode + */ +#define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL) +#define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U) +#define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK) +#define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT) + +/* + * VBG_1P0 (RW) + * + * Bandgap 1.0V output trim + */ +#define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL) +#define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U) +#define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK) +#define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT) + +/* + * VBG_P65 (RW) + * + * Bandgap 0.65V output trim + */ +#define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U) +#define BCFG_VBG_CFG_VBG_P65_SHIFT (8U) +#define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK) +#define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT) + +/* + * VBG_P50 (RW) + * + * Bandgap 0.50V output trim + */ +#define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU) +#define BCFG_VBG_CFG_VBG_P50_SHIFT (0U) +#define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK) +#define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT) + +/* Bitfield definition for register: IRC32K_CFG */ +/* + * IRC_TRIMMED (RW) + * + * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: irc is not trimmed + * 1: irc is trimmed + */ +#define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) +#define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) + +/* + * CAPEX7_TRIM (RW) + * + * IRC32K bit 7 + */ +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) + +/* + * CAPEX6_TRIM (RW) + * + * IRC32K bit 6 + */ +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) + +/* + * CAP_TRIM (RW) + * + * capacitor trim bits + */ +#define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU) +#define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U) +#define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) +#define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) + +/* Bitfield definition for register: XTAL32K_CFG */ +/* + * HYST_EN (RW) + * + * crystal 32k hysteres enable + */ +#define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U) +#define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U) +#define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK) +#define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT) + +/* + * GMSEL (RW) + * + * crystal 32k gm selection + */ +#define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U) +#define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U) +#define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK) +#define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT) + +/* + * CFG (RW) + * + * crystal 32k config + */ +#define BCFG_XTAL32K_CFG_CFG_MASK (0x10U) +#define BCFG_XTAL32K_CFG_CFG_SHIFT (4U) +#define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK) +#define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT) + +/* + * AMP (RW) + * + * crystal 32k amplifier + */ +#define BCFG_XTAL32K_CFG_AMP_MASK (0x3U) +#define BCFG_XTAL32K_CFG_AMP_SHIFT (0U) +#define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK) +#define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT) + +/* Bitfield definition for register: CLK_CFG */ +/* + * XTAL_SEL (RO) + * + * crystal selected + */ +#define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL) +#define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U) +#define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT) + +/* + * KEEP_IRC (RW) + * + * force irc32k run + */ +#define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL) +#define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U) +#define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK) +#define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT) + +/* + * FORCE_XTAL (RW) + * + * force switch to crystal + */ +#define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U) +#define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U) +#define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK) +#define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT) + + + + +#endif /* HPM_BCFG_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h new file mode 100644 index 00000000..b5b4531e --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BGPR_H +#define HPM_BGPR_H + +typedef struct { + __RW uint32_t BATT_GPR0; /* 0x0: Generic control */ + __RW uint32_t BATT_GPR1; /* 0x4: Generic control */ + __RW uint32_t BATT_GPR2; /* 0x8: Generic control */ + __RW uint32_t BATT_GPR3; /* 0xC: Generic control */ + __RW uint32_t BATT_GPR4; /* 0x10: Generic control */ + __RW uint32_t BATT_GPR5; /* 0x14: Generic control */ + __RW uint32_t BATT_GPR6; /* 0x18: Generic control */ + __RW uint32_t BATT_GPR7; /* 0x1C: Generic control */ +} BGPR_Type; + + +/* Bitfield definition for register: BATT_GPR0 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR0_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR0_GPR_SHIFT (0U) +#define BGPR_BATT_GPR0_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR0_GPR_SHIFT) & BGPR_BATT_GPR0_GPR_MASK) +#define BGPR_BATT_GPR0_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR0_GPR_MASK) >> BGPR_BATT_GPR0_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR1 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR1_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR1_GPR_SHIFT (0U) +#define BGPR_BATT_GPR1_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR1_GPR_SHIFT) & BGPR_BATT_GPR1_GPR_MASK) +#define BGPR_BATT_GPR1_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR1_GPR_MASK) >> BGPR_BATT_GPR1_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR2 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR2_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR2_GPR_SHIFT (0U) +#define BGPR_BATT_GPR2_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR2_GPR_SHIFT) & BGPR_BATT_GPR2_GPR_MASK) +#define BGPR_BATT_GPR2_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR2_GPR_MASK) >> BGPR_BATT_GPR2_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR3 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR3_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR3_GPR_SHIFT (0U) +#define BGPR_BATT_GPR3_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR3_GPR_SHIFT) & BGPR_BATT_GPR3_GPR_MASK) +#define BGPR_BATT_GPR3_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR3_GPR_MASK) >> BGPR_BATT_GPR3_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR4 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR4_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR4_GPR_SHIFT (0U) +#define BGPR_BATT_GPR4_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR4_GPR_SHIFT) & BGPR_BATT_GPR4_GPR_MASK) +#define BGPR_BATT_GPR4_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR4_GPR_MASK) >> BGPR_BATT_GPR4_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR5 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR5_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR5_GPR_SHIFT (0U) +#define BGPR_BATT_GPR5_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR5_GPR_SHIFT) & BGPR_BATT_GPR5_GPR_MASK) +#define BGPR_BATT_GPR5_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR5_GPR_MASK) >> BGPR_BATT_GPR5_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR6 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR6_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR6_GPR_SHIFT (0U) +#define BGPR_BATT_GPR6_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR6_GPR_SHIFT) & BGPR_BATT_GPR6_GPR_MASK) +#define BGPR_BATT_GPR6_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR6_GPR_MASK) >> BGPR_BATT_GPR6_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR7 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR7_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR7_GPR_SHIFT (0U) +#define BGPR_BATT_GPR7_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR7_GPR_SHIFT) & BGPR_BATT_GPR7_GPR_MASK) +#define BGPR_BATT_GPR7_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR7_GPR_MASK) >> BGPR_BATT_GPR7_GPR_SHIFT) + + + + +#endif /* HPM_BGPR_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_drv.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_drv.h new file mode 100644 index 00000000..e37bac24 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_drv.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BPOR_DRV_H +#define HPM_BPOR_DRV_H + +#include "hpm_common.h" +#include "hpm_bpor_regs.h" + +/** + * + * @brief BPOR driver APIs + * @defgroup bpor_interface BPOR driver APIs + * @ingroup io_interfaces + * @{ + * + */ + +/** @brief Define BPOR power on cause */ +typedef enum { + bpor_power_on_cause_wbutn = 1 << 0, + bpor_power_on_cause_safety_violation = 1 << 1, + bpor_power_on_cause_rtc_0 = 1 << 2, + bpor_power_on_cause_rtc_1 = 1 << 3, + bpor_power_on_cause_gpio = 1 << 4 +} bpor_power_on_cause_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get power on cause + * + * @param[in] ptr BPOR base address + * @retval POR_CAUSE register value + */ +static inline uint32_t bpor_get_power_on_cause(BPOR_Type *ptr) +{ + return ptr->POR_CAUSE; +} + +/** + * @brief Clear power on cause + * + * @param[in] ptr BPOR base address + * @param[in] mask cause status to be cleared + */ +static inline void bpor_clear_power_on_cause(BPOR_Type *ptr, uint8_t mask) +{ + ptr->POR_CAUSE |= mask; +} + +/** + * @brief enable power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be enabled + */ +static inline void bpor_enable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) +{ + ptr->POR_SELECT |= cause; +} + +/** + * @brief disable power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be disabled + */ +static inline void bpor_disable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) +{ + ptr->POR_SELECT &= ~cause; +} + +/** + * @brief Set power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be used + */ +static inline void bpor_set_power_on_cause(BPOR_Type *ptr, uint8_t cause) +{ + ptr->POR_SELECT = (ptr->POR_SELECT & ~BPOR_POR_SELECT_SELECT_MASK) | cause; +} + +/** + * @brief Enable register value retention when power down occurs + * + * @param[in] ptr BPOR base address + */ +static inline void bpor_enable_reg_value_retention(BPOR_Type *ptr) +{ + ptr->POR_CONFIG |= BPOR_POR_CONFIG_RETENTION_MASK; +} + +/** + * @brief Disable register value retention when power down occurs + * + * @param[in] ptr BPOR base address + */ +static inline void bpor_disable_reg_value_retention(BPOR_Type *ptr) +{ + ptr->POR_CONFIG &= ~BPOR_POR_CONFIG_RETENTION_MASK; +} + +/** + * @brief Set power down counter + * + * @param[in] ptr BPOR base address + * @param[in] counter counter value + */ +static inline void bpor_set_power_down_counter(BPOR_Type *ptr, uint16_t counter) +{ + ptr->POR_CONTROL = BPOR_POR_CONTROL_COUNTER_SET(counter); +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BPOR_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_regs.h new file mode 100644 index 00000000..539c5840 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_bpor_regs.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BPOR_H +#define HPM_BPOR_H + +typedef struct { + __RW uint32_t POR_CAUSE; /* 0x0: Power on cause */ + __RW uint32_t POR_SELECT; /* 0x4: Power on select */ + __RW uint32_t POR_CONFIG; /* 0x8: Power on reset config */ + __RW uint32_t POR_CONTROL; /* 0xC: Power down control */ +} BPOR_Type; + + +/* Bitfield definition for register: POR_CAUSE */ +/* + * CAUSE (RW) + * + * Power on cause, each bit represnts one cause, write 1 to clear each bit + * bit0: wakeup button + * bit1: security violation + * bit2: RTC alarm 0 + * bit3: RTC alarm 1 + * bit4: GPIO + */ +#define BPOR_POR_CAUSE_CAUSE_MASK (0x1FU) +#define BPOR_POR_CAUSE_CAUSE_SHIFT (0U) +#define BPOR_POR_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << BPOR_POR_CAUSE_CAUSE_SHIFT) & BPOR_POR_CAUSE_CAUSE_MASK) +#define BPOR_POR_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & BPOR_POR_CAUSE_CAUSE_MASK) >> BPOR_POR_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: POR_SELECT */ +/* + * SELECT (RW) + * + * Power on cause select, each bit represnts one cause, value 1 enables corresponding cause + * bit0: wakeup button + * bit1: security violation + * bit2: RTC alarm 0 + * bit3: RTC alarm 1 + * bit4: GPIO + */ +#define BPOR_POR_SELECT_SELECT_MASK (0x1FU) +#define BPOR_POR_SELECT_SELECT_SHIFT (0U) +#define BPOR_POR_SELECT_SELECT_SET(x) (((uint32_t)(x) << BPOR_POR_SELECT_SELECT_SHIFT) & BPOR_POR_SELECT_SELECT_MASK) +#define BPOR_POR_SELECT_SELECT_GET(x) (((uint32_t)(x) & BPOR_POR_SELECT_SELECT_MASK) >> BPOR_POR_SELECT_SELECT_SHIFT) + +/* Bitfield definition for register: POR_CONFIG */ +/* + * RETENTION (RW) + * + * retention battery domain setting + * 0: battery reset on reset pin reset happen + * 1: battery domain retention when reset pin reset happen + */ +#define BPOR_POR_CONFIG_RETENTION_MASK (0x1U) +#define BPOR_POR_CONFIG_RETENTION_SHIFT (0U) +#define BPOR_POR_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << BPOR_POR_CONFIG_RETENTION_SHIFT) & BPOR_POR_CONFIG_RETENTION_MASK) +#define BPOR_POR_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & BPOR_POR_CONFIG_RETENTION_MASK) >> BPOR_POR_CONFIG_RETENTION_SHIFT) + +/* Bitfield definition for register: POR_CONTROL */ +/* + * COUNTER (RW) + * + * Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 + */ +#define BPOR_POR_CONTROL_COUNTER_MASK (0xFFFFU) +#define BPOR_POR_CONTROL_COUNTER_SHIFT (0U) +#define BPOR_POR_CONTROL_COUNTER_SET(x) (((uint32_t)(x) << BPOR_POR_CONTROL_COUNTER_SHIFT) & BPOR_POR_CONTROL_COUNTER_MASK) +#define BPOR_POR_CONTROL_COUNTER_GET(x) (((uint32_t)(x) & BPOR_POR_CONTROL_COUNTER_MASK) >> BPOR_POR_CONTROL_COUNTER_SHIFT) + + + + +#endif /* HPM_BPOR_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c b/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c index 77d767fb..f800e4ac 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,8 +9,6 @@ #include "hpm_soc.h" #include "hpm_common.h" #include "hpm_pllctlv2_drv.h" -#include "hpm_csr_regs.h" -#include "riscv/riscv_core.h" /*********************************************************************************************************************** * Definitions **********************************************************************************************************************/ @@ -445,10 +443,11 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint * changes, the AXI and AHB clock changes accordingly, here the driver ensures the * AXI and AHB bus clock frequency is in valid range. */ - uint32_t expected_freq = get_frequency_for_source(src) / div; + clock_source_t source = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); + uint32_t expected_freq = get_frequency_for_source(source) / div; uint32_t axi_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; - sysctl_config_cpu0_domain_clock(HPM_SYSCTL, src, div, axi_sub_div, ahb_sub_div); + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, source, div, axi_sub_div, ahb_sub_div); } else { status = status_clk_shared_cpu0; } @@ -522,39 +521,23 @@ void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) } } - -static uint64_t get_core_mcycle(void) -{ - uint64_t result; - uint32_t resultl_first = read_csr(CSR_CYCLE); - uint32_t resulth = read_csr(CSR_CYCLEH); - uint32_t resultl_second = read_csr(CSR_CYCLE); - if (resultl_first < resultl_second) { - result = ((uint64_t)resulth << 32) | resultl_first; /* if MCYCLE didn't roll over, return the value directly */ - } else { - resulth = read_csr(CSR_MCYCLEH); - result = ((uint64_t)resulth << 32) | resultl_second; /* if MCYCLE rolled over, need to get the MCYCLEH again */ - } - return result; - } - void clock_cpu_delay_us(uint32_t us) { uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = get_core_mcycle() + ticks_per_us * us; - while (get_core_mcycle() < expected_ticks) { + uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; + while (hpm_csr_get_core_cycle() < expected_ticks) { } } void clock_cpu_delay_ms(uint32_t ms) { uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = get_core_mcycle() + (uint64_t)ticks_per_us * 1000UL * ms; - while (get_core_mcycle() < expected_ticks) { + uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * ms; + while (hpm_csr_get_core_cycle() < expected_ticks) { } } void clock_update_core_clock(void) { hpm_core_clock = clock_get_frequency(clock_cpu0); -} \ No newline at end of file +} diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h index 59e1cf42..b0bada18 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,6 +9,7 @@ #include "hpm_common.h" #include "hpm_sysctl_drv.h" +#include "hpm_csr_drv.h" /** diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h index da161186..88d1c2a5 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_csr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h index 5784c0aa..82a6d7f8 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_dmamux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h index ff00a964..6d462fce 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -93,7 +93,6 @@ typedef struct { #define GPIOM_ASSIGN_GPIOA (0UL) #define GPIOM_ASSIGN_GPIOB (1UL) #define GPIOM_ASSIGN_GPIOC (2UL) -#define GPIOM_ASSIGN_GPIOD (3UL) #define GPIOM_ASSIGN_GPIOX (13UL) #define GPIOM_ASSIGN_GPIOY (14UL) #define GPIOM_ASSIGN_GPIOZ (15UL) diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h index 666b3783..356e6798 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h @@ -498,7 +498,7 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) */ #define RESTORE_CSR(r) write_csr(r, __##r); -#if SUPPORT_PFT_ARCH +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH #define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) #define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) #else diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h index 9dee6f8c..bbbfa47e 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ioc_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,7 +13,7 @@ typedef struct { struct { __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ - } PAD[492]; + } PAD[488]; } IOC_Type; @@ -282,34 +282,6 @@ typedef struct { #define IOC_PAD_PC25 (89UL) #define IOC_PAD_PC26 (90UL) #define IOC_PAD_PC27 (91UL) -#define IOC_PAD_PC28 (92UL) -#define IOC_PAD_PC29 (93UL) -#define IOC_PAD_PC30 (94UL) -#define IOC_PAD_PC31 (95UL) -#define IOC_PAD_PD00 (96UL) -#define IOC_PAD_PD01 (97UL) -#define IOC_PAD_PD02 (98UL) -#define IOC_PAD_PD03 (99UL) -#define IOC_PAD_PD04 (100UL) -#define IOC_PAD_PD05 (101UL) -#define IOC_PAD_PD06 (102UL) -#define IOC_PAD_PD07 (103UL) -#define IOC_PAD_PD08 (104UL) -#define IOC_PAD_PD09 (105UL) -#define IOC_PAD_PD10 (106UL) -#define IOC_PAD_PD11 (107UL) -#define IOC_PAD_PD12 (108UL) -#define IOC_PAD_PD13 (109UL) -#define IOC_PAD_PD14 (110UL) -#define IOC_PAD_PD15 (111UL) -#define IOC_PAD_PD16 (112UL) -#define IOC_PAD_PD17 (113UL) -#define IOC_PAD_PD18 (114UL) -#define IOC_PAD_PD19 (115UL) -#define IOC_PAD_PD20 (116UL) -#define IOC_PAD_PD21 (117UL) -#define IOC_PAD_PD22 (118UL) -#define IOC_PAD_PD23 (119UL) #define IOC_PAD_PX00 (416UL) #define IOC_PAD_PX01 (417UL) #define IOC_PAD_PX02 (418UL) @@ -326,10 +298,6 @@ typedef struct { #define IOC_PAD_PY05 (453UL) #define IOC_PAD_PY06 (454UL) #define IOC_PAD_PY07 (455UL) -#define IOC_PAD_PY08 (456UL) -#define IOC_PAD_PY09 (457UL) -#define IOC_PAD_PY10 (458UL) -#define IOC_PAD_PY11 (459UL) #define IOC_PAD_PZ00 (480UL) #define IOC_PAD_PZ01 (481UL) #define IOC_PAD_PZ02 (482UL) @@ -338,10 +306,6 @@ typedef struct { #define IOC_PAD_PZ05 (485UL) #define IOC_PAD_PZ06 (486UL) #define IOC_PAD_PZ07 (487UL) -#define IOC_PAD_PZ08 (488UL) -#define IOC_PAD_PZ09 (489UL) -#define IOC_PAD_PZ10 (490UL) -#define IOC_PAD_PZ11 (491UL) #endif /* HPM_IOC_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h index 9ecf033f..0a2a8a2f 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -753,7 +753,6 @@ #define IOC_PC18_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC18_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) #define IOC_PC18_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC18_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PC19_FUNC_CTL function mux definitions */ #define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -761,7 +760,6 @@ #define IOC_PC19_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC19_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) #define IOC_PC19_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC19_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PC20_FUNC_CTL function mux definitions */ #define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -805,7 +803,6 @@ #define IOC_PC24_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC24_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) #define IOC_PC24_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC24_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PC25_FUNC_CTL function mux definitions */ #define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -813,7 +810,6 @@ #define IOC_PC25_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PC25_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) #define IOC_PC25_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC25_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PC26_FUNC_CTL function mux definitions */ #define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -831,259 +827,6 @@ #define IOC_PC27_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PC27_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -/* IOC_PC28_FUNC_CTL function mux definitions */ -#define IOC_PC28_FUNC_CTL_GPIO_C_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC28_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC28_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC28_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC28_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC29_FUNC_CTL function mux definitions */ -#define IOC_PC29_FUNC_CTL_GPIO_C_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC29_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC29_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC29_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC29_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC30_FUNC_CTL function mux definitions */ -#define IOC_PC30_FUNC_CTL_GPIO_C_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC30_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC30_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC30_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC31_FUNC_CTL function mux definitions */ -#define IOC_PC31_FUNC_CTL_GPIO_C_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC31_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC31_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC31_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD00_FUNC_CTL function mux definitions */ -#define IOC_PD00_FUNC_CTL_GPIO_D_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD00_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD00_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD00_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD00_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD00_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD00_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD00_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD00_FUNC_CTL_TRGM1_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD01_FUNC_CTL function mux definitions */ -#define IOC_PD01_FUNC_CTL_GPIO_D_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD01_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD01_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD01_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD01_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD01_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD01_FUNC_CTL_XPI1_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD01_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD02_FUNC_CTL function mux definitions */ -#define IOC_PD02_FUNC_CTL_GPIO_D_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD02_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD02_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD02_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD02_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD02_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD02_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD02_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD02_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD03_FUNC_CTL function mux definitions */ -#define IOC_PD03_FUNC_CTL_GPIO_D_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD03_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD03_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD03_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD03_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD03_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD03_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD03_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD03_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD03_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD04_FUNC_CTL function mux definitions */ -#define IOC_PD04_FUNC_CTL_GPIO_D_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD04_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD04_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD04_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD04_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD04_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD04_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD04_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD04_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD05_FUNC_CTL function mux definitions */ -#define IOC_PD05_FUNC_CTL_GPIO_D_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD05_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD05_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD05_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD05_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD05_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD05_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD05_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD06_FUNC_CTL function mux definitions */ -#define IOC_PD06_FUNC_CTL_GPIO_D_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD06_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD06_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD06_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD06_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD06_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD06_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD06_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD06_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD07_FUNC_CTL function mux definitions */ -#define IOC_PD07_FUNC_CTL_GPIO_D_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD07_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD07_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD07_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD07_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD07_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD07_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD07_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD08_FUNC_CTL function mux definitions */ -#define IOC_PD08_FUNC_CTL_GPIO_D_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD08_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD08_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD08_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD08_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD08_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD08_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD09_FUNC_CTL function mux definitions */ -#define IOC_PD09_FUNC_CTL_GPIO_D_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD09_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD09_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD09_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD09_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD10_FUNC_CTL function mux definitions */ -#define IOC_PD10_FUNC_CTL_GPIO_D_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD10_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD10_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD10_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD10_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD10_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD11_FUNC_CTL function mux definitions */ -#define IOC_PD11_FUNC_CTL_GPIO_D_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD11_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD11_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD11_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD11_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD11_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD11_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD12_FUNC_CTL function mux definitions */ -#define IOC_PD12_FUNC_CTL_GPIO_D_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD12_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD12_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD12_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD12_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD12_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD13_FUNC_CTL function mux definitions */ -#define IOC_PD13_FUNC_CTL_GPIO_D_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD13_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD13_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD13_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD13_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD13_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD14_FUNC_CTL function mux definitions */ -#define IOC_PD14_FUNC_CTL_GPIO_D_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD14_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD14_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD14_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD14_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD14_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD14_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD14_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD15_FUNC_CTL function mux definitions */ -#define IOC_PD15_FUNC_CTL_GPIO_D_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD15_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD15_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD15_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD15_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD15_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD15_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD15_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD16_FUNC_CTL function mux definitions */ -#define IOC_PD16_FUNC_CTL_GPIO_D_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD16_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD16_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD16_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD16_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD16_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD16_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD16_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD17_FUNC_CTL function mux definitions */ -#define IOC_PD17_FUNC_CTL_GPIO_D_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD17_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD17_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD17_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD17_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD17_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD17_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD18_FUNC_CTL function mux definitions */ -#define IOC_PD18_FUNC_CTL_GPIO_D_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD18_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD18_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD18_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD18_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD18_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD18_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD19_FUNC_CTL function mux definitions */ -#define IOC_PD19_FUNC_CTL_GPIO_D_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD19_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD19_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD19_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD19_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD19_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD20_FUNC_CTL function mux definitions */ -#define IOC_PD20_FUNC_CTL_GPIO_D_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD20_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD20_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD20_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD20_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD20_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD20_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD21_FUNC_CTL function mux definitions */ -#define IOC_PD21_FUNC_CTL_GPIO_D_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD21_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD21_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD21_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD21_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD21_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD21_FUNC_CTL_ETH0_COL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD22_FUNC_CTL function mux definitions */ -#define IOC_PD22_FUNC_CTL_GPIO_D_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD22_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) - -/* IOC_PD23_FUNC_CTL function mux definitions */ -#define IOC_PD23_FUNC_CTL_GPIO_D_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD23_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) - /* IOC_PX00_FUNC_CTL function mux definitions */ #define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) @@ -1169,18 +912,6 @@ #define IOC_PY07_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PY07_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -/* IOC_PY08_FUNC_CTL function mux definitions */ -#define IOC_PY08_FUNC_CTL_GPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PY09_FUNC_CTL function mux definitions */ -#define IOC_PY09_FUNC_CTL_GPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PY10_FUNC_CTL function mux definitions */ -#define IOC_PY10_FUNC_CTL_GPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PY11_FUNC_CTL function mux definitions */ -#define IOC_PY11_FUNC_CTL_GPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - /* IOC_PZ00_FUNC_CTL function mux definitions */ #define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PZ00_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) @@ -1221,17 +952,5 @@ #define IOC_PZ07_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PZ07_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -/* IOC_PZ08_FUNC_CTL function mux definitions */ -#define IOC_PZ08_FUNC_CTL_GPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PZ09_FUNC_CTL function mux definitions */ -#define IOC_PZ09_FUNC_CTL_GPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PZ10_FUNC_CTL function mux definitions */ -#define IOC_PZ10_FUNC_CTL_GPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PZ11_FUNC_CTL function mux definitions */ -#define IOC_PZ11_FUNC_CTL_GPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - #endif /* HPM_IOMUX_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h new file mode 100644 index 00000000..e99e0837 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h @@ -0,0 +1,639 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PCFG_DRV_H +#define HPM_PCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_pcfg_regs.h" + +/** + * + * @brief PCFG driver APIs + * @defgroup pcfg_interface PCFG driver APIs + * @ingroup io_interfaces + * @{ + */ +#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW (0x1UL) + +#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) +#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) +#define PCFG_PERIPH_SET_CLOCK_AUTO(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW << (p)) + +/* @brief PCFG irc24m reference */ +typedef enum { + pcfg_irc24m_reference_32k = 0, + pcfg_irc24m_reference_24m_xtal = 1 +} pcfg_irc24m_reference_t; + +/* @brief PCFG dcdc current limit */ +typedef enum { + pcfg_dcdc_lp_current_limit_250ma = 0, + pcfg_dcdc_lp_current_limit_200ma = 1, +} pcfg_dcdc_lp_current_limit_t; + +/* @brief PCFG dcdc current hys */ +typedef enum { + pcfg_dcdc_current_hys_12_5mv = 0, + pcfg_dcdc_current_hys_25mv = 1, +} pcfg_dcdc_current_hys_t; + +/* @brief PCFG dcdc mode */ +typedef enum { + pcfg_dcdc_mode_off = 0, + pcfg_dcdc_mode_basic = 1, + pcfg_dcdc_mode_general = 3, + pcfg_dcdc_mode_expert = 7, +} pcfg_dcdc_mode_t; + +/* @brief PCFG pmc domain peripherals */ +typedef enum { + pcfg_pmc_periph_fuse = 0, + pcfg_pmc_periph_ram = 2, + pcfg_pmc_periph_vad = 4, + pcfg_pmc_periph_gpio = 6, + pcfg_pmc_periph_ioc = 8, + pcfg_pmc_periph_timer = 10, + pcfg_pmc_periph_wdog = 12, + pcfg_pmc_periph_uart = 14, + pcfg_pmc_periph_debug = 16, +} pcfg_pmc_periph_t; + +/* @brief PCFG status */ +enum { + status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), +}; + +/* @brief PCFG irc24m config */ +typedef struct { + uint32_t freq_in_hz; + pcfg_irc24m_reference_t reference; + bool return_to_default_on_xtal_loss; + bool free_run; +} pcfg_irc24m_config_t; + + +#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ + ((uint32_t) (mode) << ((module) << 1)) + +#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE0 (PCFG_DEBUG_STOP_CPU0_MASK) +#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE0 (0) +#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE1 (PCFG_DEBUG_STOP_CPU1_MASK) +#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE1 (0) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief bandgap disable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_POWER_SAVE_MASK; +} + +/** + * @brief bandgap enable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_enable_power_save_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP |= PCFG_BANDGAP_POWER_SAVE_MASK; +} + +/** + * @brief bandgap disable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_LOWPOWER_MODE_MASK; +} + +/** + * @brief bandgap enable low power mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP |= PCFG_BANDGAP_LOWPOWER_MODE_MASK; +} + +/** + * @brief check if bandgap is trimmed or not + * + * @param[in] ptr base address + * + * @retval true if bandgap is trimmed + */ +static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) +{ + return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief bandgap reload trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief turn off LDO 1V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo1p1_turn_off(PCFG_Type *ptr) +{ + ptr->LDO1P1 &= ~PCFG_LDO1P1_ENABLE_MASK; +} + +/** + * @brief turn of LDO 1V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo1p1_turn_on(PCFG_Type *ptr) +{ + ptr->LDO1P1 |= PCFG_LDO1P1_ENABLE_MASK; +} + +/** + * @brief turn off LDO2P5 + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) +{ + ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief turn on LDO 2.5V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) +{ + ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief check if LDO 2.5V is stable + * + * @param[in] ptr base address + * + * @retval true if LDO2P5 is stable + */ +static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) +{ + return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); +} + +/* + * @brief check if DCDC is stable or not + * @param[in] ptr base address + * @retval true if DCDC is stable + */ +static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) +{ + return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); +} + +/* + * @brief set DCDC work mode + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) +{ + ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); +} + +/** + * @brief set low power current limit + * + * @param[in] ptr base address + * @param[in] limit current limit at low power mode + * @param[in] over_limit set to true means current is greater than limit + */ +static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) +{ + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) + | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(over_limit); +} + +/** + * @brief disable power loss protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief enable power loss protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief check if power loss flag is set + * + * @param[in] ptr base address + * + * @retval true if power loss is set + */ +static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); +} + +/** + * @brief disable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief enable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief checkover voltage flag + * + * @param[in] ptr base address + * @retval true if flag is set + */ +static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; +} + +/** + * @brief disable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief enable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief check if measured current is valid + * + * @param[in] ptr base address + * + * @retval true if measured current is valid + */ +static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) +{ + return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; +} + +/** + * @brief get DCDC start time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc start time in cycles + */ +static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); +} + +/** + * @brief get DCDC resume time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc resuem time in cycles + */ +static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); +} + +/** + * @brief set DCDC start time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles start time in cycles + */ +static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); +} + +/** + * @brief set DCDC resuem time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles resume time in cycles + */ +static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); +} + +/** + * @brief set dcdc current hysteres range + * + * @param[in] ptr base address + * @param[in] range current hysteres range + */ +static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) +{ + ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); +} + +/** + * @brief disable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief enable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief check if power trap is triggered + * + * @param[in] ptr base address + * + * @retval true if power trap is triggered + */ +static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) +{ + return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief clear power trap trigger flag + * + * @param[in] ptr base address + */ +static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief disable dcdc retention + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief enable dcdc retention to retain soc sram data + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief clear wakeup cause flag + * + * @param[in] ptr base address + * @param[in] mask mask of flags to be cleared + */ +static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_CAUSE |= mask; +} + +/** + * @brief get wakeup cause + * + * @param[in] ptr base address + * + * @retval mask of wake cause + */ +static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) +{ + return ptr->WAKE_CAUSE; +} + +/** + * @brief enable wakeup source + * + * @param[in] ptr base address + * @param[in] mask wakeup source mask + */ +static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK &= ~mask; +} + +/** + * @brief disable wakeup source + * + * @param[in] ptr base address + * @param[in] mask source to be disabled as wakeup source + */ +static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK |= mask; +} + +/** + * @brief set clock gate mode in vpmc domain + * + * @param[in] ptr base address + * @param[in] mode clock gate mode mask + */ +static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) +{ + ptr->SCG_CTRL = mode; +} + +/** + * @brief Disable CPU0 debug stop notficiation to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_disable_cpu0_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU0_MASK; +} + +/** + * @brief Enable CPU0 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_enable_cpu0_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU0_MASK; +} + +/** + * @brief Disable CPU1 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_disable_cpu1_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU1_MASK; +} + +/** + * @brief Enable CPU1 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_enable_cpu1_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU1_MASK; +} + +/** + * @brief Configure CPU core debug stop notification to peripherals + * + * @param[in] ptr + * @param[in] mask + */ +static inline void pcfg_config_debug_stop_notification(PCFG_Type *ptr, uint8_t mask) +{ + ptr->DEBUG_STOP = mask; +} + +/** + * @brief check if irc24m is trimmed + * + * @param[in] ptr base address + * + * @retval true if it is trimmed + */ +static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) +{ + return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief reload irc24m trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) +{ + ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief config irc24m track + * + * @param[in] ptr base address + * @param[in] config config data + */ +void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); + +/* + * @brief set DCDC voltage at standby mode + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 2.5V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set DCDC voltage + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 1V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief get current DCDC current level in mA + * + * @param[in] ptr base address + * @retval Current level at mA + */ +uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_PCFG_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_pcfg_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h similarity index 99% rename from common/libraries/hpm_sdk/soc/ip/hpm_pcfg_regs.h rename to common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h index cfbfc66d..1240a9cf 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_pcfg_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -735,7 +735,7 @@ typedef struct { * SCG (RW) * * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral - * 00,01: clock gated according to low power flow + * 00,01: reserved * 10: clock is always off * 11: clock is always on * bit0-1: fuse diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_pgpr_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_pgpr_regs.h new file mode 100644 index 00000000..36c19e7d --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_pgpr_regs.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PGPR_H +#define HPM_PGPR_H + +typedef struct { + __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ + __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ + __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ + __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ + __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ + __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ + __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ + __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ + __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ + __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ + __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ + __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ + __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ + __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ + __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ + __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ +} PGPR_Type; + + +/* Bitfield definition for register: PMIC_GPR00 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) +#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR01 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) +#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR02 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) +#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR03 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) +#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR04 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) +#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR05 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) +#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR06 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) +#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR07 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) +#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR08 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) +#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR09 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) +#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR10 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) +#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR11 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) +#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR12 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) +#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR13 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) +#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR14 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) +#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR15 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) +#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) + + + + +#endif /* HPM_PGPR_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h index f66c1e5b..56c1a22b 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_pmic_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -57,27 +57,5 @@ #define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -/* IOC_PY08_FUNC_CTL function mux definitions */ -#define IOC_PY08_FUNC_CTL_PGPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY08_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY09_FUNC_CTL function mux definitions */ -#define IOC_PY09_FUNC_CTL_PGPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY09_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY10_FUNC_CTL function mux definitions */ -#define IOC_PY10_FUNC_CTL_PGPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY10_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* IOC_PY11_FUNC_CTL function mux definitions */ -#define IOC_PY11_FUNC_CTL_PGPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY11_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - #endif /* HPM_PMIC_IOMUX_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h new file mode 100644 index 00000000..b1eb6e6a --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PPOR_DRV_H +#define HPM_PPOR_DRV_H +#include "hpm_ppor_regs.h" + +typedef enum { + ppor_reset_brownout = 1 << 0, + ppor_reset_temperature = 1 << 1, + ppor_reset_pin = 1 << 2, + ppor_reset_debug = 1 << 4, + ppor_reset_security_violation = 1 << 5, + ppor_reset_jtag = 1 << 6, + ppor_reset_cpu0_lockup = 1 << 8, + ppor_reset_cpu1_lockup = 1 << 9, + ppor_reset_cpu0_request = 1 << 10, + ppor_reset_cpu1_request = 1 << 11, + ppor_reset_wdog0 = 1 << 16, + ppor_reset_wdog1 = 1 << 17, + ppor_reset_wdog2 = 1 << 18, + ppor_reset_wdog3 = 1 << 19, + ppor_reset_pmic_wdog = 1 << 20, + ppor_reset_software = 1 << 31, +} ppor_reset_source_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * perform software reset in counter * (1/24Mhz) seconds + */ +static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) +{ + ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } + +/* + * clear enable reset source according to the given mask + */ +static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE &= ~mask; +} + +/* + * set enable reset source according to the given mask + */ +static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE |= mask; +} + +/* + * set enable reset source + */ +static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) +{ + ptr->RESET_ENABLE = reset_sources; +} + +/* + * get enabled reset source + */ +static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) +{ + return ptr->RESET_ENABLE; +} + +/* + * get reset status + */ +static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) +{ + return ptr->RESET_STATUS; +} + +/* + * get reset flags + */ +static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) +{ + return ptr->RESET_FLAG; +} + +/* + * clear reset flags + */ +static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_FLAG |= mask; +} + +/* + * set cold reset + */ +static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_COLD = mask; +} + +/* + * clear cold reset + */ +static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_COLD &= ~mask; +} + +/* + * set hot reset + */ +static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOT = mask; +} + +/* + * clear hot reset + */ +static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOT &= ~mask; +} + +#ifdef __cplusplus +} +#endif +#endif diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_regs.h new file mode 100644 index 00000000..17d55b5a --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_regs.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PPOR_H +#define HPM_PPOR_H + +typedef struct { + __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ + __RW uint32_t RESET_STATUS; /* 0x4: reset source status */ + __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ + __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ + __RW uint32_t RESET_HOT; /* 0x10: reset type triggered by reset */ + __RW uint32_t RESET_COLD; /* 0x14: reset type attribute */ + __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */ + __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ +} PPOR_Type; + + +/* Bitfield definition for register: RESET_FLAG */ +/* + * FLAG (W1C) + * + * reset reason of last hard reset, write 1 to clear each bit + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) +#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) +#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) + +/* Bitfield definition for register: RESET_STATUS */ +/* + * STATUS (RW) + * + * current status of reset sources + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) +#define PPOR_RESET_STATUS_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_STATUS_STATUS_SHIFT) & PPOR_RESET_STATUS_STATUS_MASK) +#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_HOLD */ +/* + * STATUS (RW) + * + * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_HOLD_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOLD_STATUS_SHIFT (0U) +#define PPOR_RESET_HOLD_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_STATUS_SHIFT) & PPOR_RESET_HOLD_STATUS_MASK) +#define PPOR_RESET_HOLD_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_STATUS_MASK) >> PPOR_RESET_HOLD_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_ENABLE */ +/* + * ENABLE (RW) + * + * enable of reset sources + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) +#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) +#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) + +/* Bitfield definition for register: RESET_HOT */ +/* + * TYPE (RW) + * + * reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_HOT_TYPE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOT_TYPE_SHIFT (0U) +#define PPOR_RESET_HOT_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_HOT_TYPE_SHIFT) & PPOR_RESET_HOT_TYPE_MASK) +#define PPOR_RESET_HOT_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_HOT_TYPE_MASK) >> PPOR_RESET_HOT_TYPE_SHIFT) + +/* Bitfield definition for register: RESET_COLD */ +/* + * FLAG (RW) + * + * perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_COLD_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_COLD_FLAG_SHIFT (0U) +#define PPOR_RESET_COLD_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_COLD_FLAG_SHIFT) & PPOR_RESET_COLD_FLAG_MASK) +#define PPOR_RESET_COLD_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_COLD_FLAG_MASK) >> PPOR_RESET_COLD_FLAG_SHIFT) + +/* Bitfield definition for register: SOFTWARE_RESET */ +/* + * COUNTER (RW) + * + * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + */ +#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) +#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) +#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) +#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) + + + + +#endif /* HPM_PPOR_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h index d269433e..24242560 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_romapi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -52,6 +52,14 @@ typedef union { }; } api_boot_arg_t; +/*EXiP Region Parameter */ +typedef struct { + uint32_t start; /**< Start address, must be 4KB aligned */ + uint32_t len; /**< Must be 4KB aligned */ + uint8_t key[16]; /**< AES Key */ + uint8_t ctr[8]; /**< Initial Vector/Counter */ +} exip_region_param_t; + #define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ #define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ #define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ @@ -629,6 +637,158 @@ static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, xpi_xfer_channel return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); } +/** + * @brief Configure the XPI Address Remapping Logic + * @param [in] base XPI base address + * @param [in] start Start Address (memory mapped address) + * @param [in] len Size for the remapping region + * @param [in] offset Relative address based on parameter "start" + * @retval true is all parameters are valid + * @retval false if any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) +{ + if (((base != HPM_XPI0) && (base != HPM_XPI1)) || ((start & 0xFFF) != 0) || ((len & 0xFFF) != 0) + || ((offset & 0xFFF) != 0)) { + return false; + } + static const uint8_t k_mc_xpi_remap_config[] = { + 0x2e, 0x96, 0x23, 0x22, 0xc5, 0x42, 0x23, 0x24, + 0xd5, 0x42, 0x93, 0xe5, 0x15, 0x00, 0x23, 0x20, + 0xb5, 0x42, 0x05, 0x45, 0x82, 0x80, + }; + typedef bool (*remap_config_cb_t)(XPI_Type *, uint32_t, uint32_t, uint32_t); + remap_config_cb_t cb = (remap_config_cb_t) &k_mc_xpi_remap_config; + bool result = cb(base, start, len, offset); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return result; +} + +/** + * @brief Disable XPI Remapping logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_remap_disable(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_disable[] = { + 0x83, 0x27, 0x05, 0x42, 0xf9, 0x9b, 0x23, 0x20, + 0xf5, 0x42, 0x82, 0x80, + }; + typedef void (*remap_disable_cb_t)(XPI_Type *); + remap_disable_cb_t cb = (remap_disable_cb_t) &k_mc_xpi_remap_disable; + cb(base); + fencei(); +} + +/** + * @brief Check whether XPI Remapping is enabled + * @param [in] base XPI base address + * + * @retval true Remapping logic is enabled + * @retval false Remapping logic is disabled + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_is_remap_enabled(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_enabled[] = { + 0x03, 0x25, 0x05, 0x42, 0x05, 0x89, 0x82, 0x80, + }; + typedef void (*remap_chk_cb_t)(XPI_Type *); + remap_chk_cb_t chk_cb = (remap_chk_cb_t) &k_mc_xpi_remap_enabled; + return chk_cb(base); +} + +/** + * @brief Configure Specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + * @param [in] param ExiP Region Parameter + * @retval true All parameters are valid + * @retval false Any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) +{ + if (base != HPM_XPI0) { + return false; + } + static const uint8_t k_mc_exip_region_config[] = { + 0x18, 0x4a, 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, + 0xaa, 0x97, 0x23, 0xa4, 0xe7, 0xd0, 0x4c, 0x4a, + 0x14, 0x42, 0x58, 0x42, 0x23, 0xa6, 0xb7, 0xd0, + 0x4c, 0x46, 0x36, 0x97, 0x13, 0x77, 0x07, 0xc0, + 0x23, 0xa2, 0xb7, 0xd0, 0x0c, 0x46, 0x13, 0x67, + 0x37, 0x00, 0x05, 0x45, 0x23, 0xa0, 0xb7, 0xd0, + 0x0c, 0x4e, 0x23, 0xaa, 0xb7, 0xd0, 0x50, 0x4e, + 0x23, 0xa8, 0xc7, 0xd0, 0x23, 0xac, 0xd7, 0xd0, + 0x23, 0xae, 0xe7, 0xd0, 0x82, 0x80, + }; + typedef void (*exip_region_config_cb_t)(XPI_Type *, uint32_t, exip_region_param_t *); + exip_region_config_cb_t cb = (exip_region_config_cb_t) &k_mc_exip_region_config; + cb(base, index, param); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return true; +} + +/** + * @brief Disable EXiP Feature on specified EXiP Region + * @@param [in] base XPI base address + * @param [in] index EXiP Region index + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) +{ + static const uint8_t k_mc_exip_region_disable[] = { + 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, 0xaa, 0x97, + 0x03, 0xa7, 0xc7, 0xd1, 0x75, 0x9b, 0x23, 0xae, + 0xe7, 0xd0, 0x82, 0x80 + }; + typedef void (*exip_region_disable_cb_t)(XPI_Type *, uint32_t); + exip_region_disable_cb_t cb = (exip_region_disable_cb_t) &k_mc_exip_region_disable; + cb(base, index); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} + +/** + * @brief Enable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_enable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_enable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x37, 0x07, 0x00, 0x80, 0xd9, 0x8f, 0x23, 0x20, + 0xf5, 0xc0, 0x82, 0x80 + }; + typedef void (*exip_enable_cb_t)(XPI_Type *); + exip_enable_cb_t cb = (exip_enable_cb_t) &k_mc_exip_enable; + cb(base); +} + +/** + * @brief Disable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_disable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_disable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x86, 0x07, 0x85, 0x83, 0x23, 0x20, 0xf5, 0xc0, + 0x82, 0x80 + }; + typedef void (*exip_disable_cb_t)(XPI_Type *); + exip_disable_cb_t cb = (exip_disable_cb_t) &k_mc_exip_disable; + cb(base); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} /*********************************************************************************************************************** * diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml index 1d2478f3..58ab2895 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml @@ -3253,146 +3253,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -3473,26 +3333,6 @@ - - - - - - - - - - - - - - - - - - - - @@ -3533,26 +3373,6 @@ - - - - - - - - - - - - - - - - - - - - @@ -3782,7 +3602,7 @@ - + @@ -4481,7 +4301,7 @@ - + @@ -5180,7 +5000,7 @@ - + @@ -9344,6 +9164,7 @@ + @@ -10119,6 +9940,7 @@ + @@ -12334,24 +12156,6 @@ - - - - - - - - - - - - - - - - - - @@ -12446,7 +12250,6 @@ - @@ -12457,12 +12260,6 @@ - - - - - - @@ -12613,132 +12410,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -12802,128 +12476,36 @@ - - + + + + + + + + + + + + + - - + + + - - + + - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - - - - - - - - - - - - - @@ -12940,20 +12522,6 @@ - - - - - - - - - - - - - - @@ -12970,20 +12538,6 @@ - - - - - - - - - - - - - - @@ -13000,30 +12554,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -13106,6 +12636,7 @@ + @@ -13294,51 +12825,11 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -13381,7 +12872,7 @@ - + @@ -13424,7 +12915,7 @@ - + @@ -13467,7 +12958,7 @@ - + @@ -13553,7 +13044,7 @@ - + @@ -13596,7 +13087,7 @@ - + @@ -13639,7 +13130,7 @@ - + @@ -13682,7 +13173,7 @@ - + @@ -13768,7 +13259,7 @@ - + @@ -13811,7 +13302,7 @@ - + @@ -13854,7 +13345,7 @@ - + @@ -13897,7 +13388,7 @@ - + @@ -13983,7 +13474,7 @@ - + @@ -14026,7 +13517,7 @@ - + @@ -14069,7 +13560,7 @@ - + @@ -14112,7 +13603,7 @@ - + @@ -14198,7 +13689,7 @@ - + @@ -14241,7 +13732,7 @@ - + @@ -14284,7 +13775,7 @@ - + @@ -14327,7 +13818,7 @@ - + @@ -14413,7 +13904,7 @@ - + @@ -14456,7 +13947,7 @@ - + @@ -14499,7 +13990,7 @@ - + @@ -14542,7 +14033,7 @@ - + @@ -15317,9 +14808,6 @@ - - - @@ -15357,7 +14845,6 @@ - @@ -15367,12 +14854,6 @@ - - - - - - @@ -15420,7 +14901,7 @@ - + @@ -15495,7 +14976,7 @@ - + @@ -15570,7 +15051,7 @@ - + @@ -15645,7 +15126,7 @@ - + @@ -18717,12 +18198,12 @@ - + - + @@ -18733,12 +18214,12 @@ - + - + @@ -18749,12 +18230,12 @@ - + - + @@ -18765,12 +18246,12 @@ - + - + @@ -18781,12 +18262,12 @@ - + - + @@ -18797,12 +18278,12 @@ - + - + @@ -18813,12 +18294,12 @@ - + - + @@ -18829,12 +18310,12 @@ - + - + @@ -18845,12 +18326,12 @@ - + - + @@ -18861,12 +18342,12 @@ - + - + @@ -18877,12 +18358,12 @@ - + - + @@ -18893,12 +18374,12 @@ - + - + @@ -18909,12 +18390,12 @@ - + - + @@ -18925,12 +18406,12 @@ - + - + @@ -18941,12 +18422,12 @@ - + - + @@ -18957,12 +18438,12 @@ - + - + @@ -18973,12 +18454,12 @@ - + - + @@ -18989,12 +18470,12 @@ - + - + @@ -19005,12 +18486,12 @@ - + - + @@ -19021,12 +18502,12 @@ - + - + @@ -19037,12 +18518,12 @@ - + - + @@ -19053,12 +18534,12 @@ - + - + @@ -19069,12 +18550,12 @@ - + - + @@ -19085,12 +18566,12 @@ - + - + @@ -19101,12 +18582,14 @@ - + + + - + @@ -19117,12 +18600,12 @@ - + - + @@ -19133,12 +18616,12 @@ - + - + @@ -19149,12 +18632,12 @@ - + - + @@ -19165,12 +18648,12 @@ - + - + @@ -19181,12 +18664,12 @@ - + - + @@ -19197,12 +18680,12 @@ - + - + @@ -19213,12 +18696,12 @@ - + - + @@ -19229,12 +18712,12 @@ - + - + @@ -19245,12 +18728,12 @@ - + - + @@ -19261,12 +18744,12 @@ - + - + @@ -19277,12 +18760,12 @@ - + - + @@ -19293,12 +18776,12 @@ - + - + @@ -19309,12 +18792,12 @@ - + - + @@ -19325,12 +18808,12 @@ - + - + @@ -19341,12 +18824,12 @@ - + - + @@ -19357,12 +18840,12 @@ - + - + @@ -19373,12 +18856,12 @@ - + - + @@ -19389,12 +18872,12 @@ - + - + @@ -19405,12 +18888,12 @@ - + - + @@ -19421,12 +18904,12 @@ - + - + @@ -19437,12 +18920,12 @@ - + - + @@ -19453,12 +18936,12 @@ - + - + @@ -19469,12 +18952,12 @@ - + - + @@ -19485,12 +18968,12 @@ - + - + @@ -19501,12 +18984,12 @@ - + - + @@ -19517,12 +19000,12 @@ - + - + @@ -19533,12 +19016,12 @@ - + - + @@ -19549,12 +19032,12 @@ - + - + @@ -19565,12 +19048,12 @@ - + - + @@ -19581,12 +19064,12 @@ - + - + @@ -19597,12 +19080,12 @@ - + - + @@ -19613,12 +19096,12 @@ - + - + @@ -19629,12 +19112,12 @@ - + - + @@ -19645,12 +19128,12 @@ - + - + @@ -19661,12 +19144,12 @@ - + - + @@ -19677,14 +19160,12 @@ - - - + - + @@ -19695,12 +19176,12 @@ - + - + @@ -19711,12 +19192,12 @@ - + - + @@ -19727,12 +19208,12 @@ - + - + @@ -19743,12 +19224,12 @@ - + - + @@ -19759,12 +19240,12 @@ - + - + @@ -19775,12 +19256,12 @@ - + - + @@ -19791,12 +19272,12 @@ - + - + @@ -19807,12 +19288,12 @@ - + - + @@ -19823,12 +19304,12 @@ - + - + @@ -19839,12 +19320,12 @@ - + - + @@ -19855,12 +19336,12 @@ - + - + @@ -19871,12 +19352,12 @@ - + - + @@ -19887,12 +19368,12 @@ - + - + @@ -19903,12 +19384,12 @@ - + - + @@ -19919,12 +19400,12 @@ - + - + @@ -19935,12 +19416,12 @@ - + - + @@ -19951,12 +19432,12 @@ - + - + @@ -19967,12 +19448,12 @@ - + - + @@ -19983,12 +19464,12 @@ - + - + @@ -19999,12 +19480,12 @@ - + - + @@ -20015,12 +19496,12 @@ - + - + @@ -20031,12 +19512,12 @@ - + - + @@ -20047,12 +19528,12 @@ - + - + @@ -20063,12 +19544,12 @@ - + - + @@ -20079,12 +19560,12 @@ - + - + @@ -20095,12 +19576,12 @@ - + - + @@ -20111,12 +19592,12 @@ - + - + @@ -20127,12 +19608,12 @@ - + - + @@ -20143,12 +19624,12 @@ - + - + @@ -20159,12 +19640,12 @@ - + - + @@ -20175,12 +19656,12 @@ - + - + @@ -20191,12 +19672,12 @@ - + - + @@ -20207,12 +19688,12 @@ - + - + @@ -20223,12 +19704,12 @@ - + - + @@ -20239,12 +19720,12 @@ - + - + @@ -20255,12 +19736,12 @@ - + - + @@ -20271,12 +19752,12 @@ - + - + @@ -20287,12 +19768,12 @@ - + - + @@ -20303,12 +19784,12 @@ - + - + @@ -20319,12 +19800,12 @@ - + - + @@ -20335,12 +19816,12 @@ - + - + @@ -20351,12 +19832,12 @@ - + - + @@ -20367,12 +19848,12 @@ - + - + @@ -20383,12 +19864,12 @@ - + - + @@ -20399,12 +19880,12 @@ - + - + @@ -20415,12 +19896,12 @@ - + - + @@ -20431,12 +19912,12 @@ - + - + @@ -20447,12 +19928,12 @@ - + - + @@ -20463,12 +19944,12 @@ - + - + @@ -20479,12 +19960,12 @@ - + - + @@ -20495,12 +19976,12 @@ - + - + @@ -20511,12 +19992,12 @@ - + - + @@ -20527,12 +20008,12 @@ - + - + @@ -20543,12 +20024,12 @@ - + - + @@ -20559,1742 +20040,12 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -22305,12 +20056,12 @@ - + - + @@ -22321,12 +20072,12 @@ - + - + @@ -22337,12 +20088,12 @@ - + - + @@ -22353,12 +20104,12 @@ - + - + @@ -22369,12 +20120,12 @@ - + - + @@ -22385,12 +20136,12 @@ - + - + @@ -22401,12 +20152,12 @@ - + - + @@ -22417,12 +20168,12 @@ - + - + @@ -22433,12 +20184,12 @@ - + - + @@ -22449,12 +20200,12 @@ - + - + @@ -22465,12 +20216,12 @@ - + - + @@ -22481,12 +20232,12 @@ - + - + @@ -22497,12 +20248,12 @@ - + - + @@ -22513,12 +20264,12 @@ - + - + @@ -22529,12 +20280,12 @@ - + - + @@ -22545,12 +20296,12 @@ - + - + @@ -22561,12 +20312,12 @@ - + - + @@ -22577,12 +20328,12 @@ - + - + @@ -22593,12 +20344,12 @@ - + - + @@ -22609,12 +20360,12 @@ - + - + @@ -22625,12 +20376,12 @@ - + - + @@ -22641,12 +20392,12 @@ - + - + @@ -22657,12 +20408,12 @@ - + - + @@ -22673,12 +20424,12 @@ - + - + @@ -22689,12 +20440,14 @@ - + + + - + @@ -22705,12 +20458,12 @@ - + - + @@ -22721,12 +20474,12 @@ - + - + @@ -22737,12 +20490,12 @@ - + - + @@ -22753,12 +20506,12 @@ - + - + @@ -22769,12 +20522,12 @@ - + - + @@ -22785,12 +20538,12 @@ - + - + @@ -22801,12 +20554,12 @@ - + - + @@ -22817,12 +20570,12 @@ - + - + @@ -22833,12 +20586,12 @@ - + - + @@ -22849,12 +20602,12 @@ - + - + @@ -22865,12 +20618,12 @@ - + - + @@ -22881,12 +20634,12 @@ - + - + @@ -22897,12 +20650,12 @@ - + - + @@ -22913,12 +20666,12 @@ - + - + @@ -22929,12 +20682,12 @@ - + - + @@ -22945,12 +20698,12 @@ - + - + @@ -22961,12 +20714,12 @@ - + - + @@ -22977,12 +20730,12 @@ - + - + @@ -22993,12 +20746,12 @@ - + - + @@ -23009,12 +20762,12 @@ - + - + @@ -23025,12 +20778,12 @@ - + - + @@ -23041,12 +20794,12 @@ - + - + @@ -23057,12 +20810,12 @@ - + - + @@ -23073,12 +20826,12 @@ - + - + @@ -23089,12 +20842,12 @@ - + - + @@ -23105,12 +20858,12 @@ - + - + @@ -23121,12 +20874,12 @@ - + - + @@ -23137,12 +20890,12 @@ - + - + @@ -23153,12 +20906,12 @@ - + - + @@ -23169,12 +20922,12 @@ - + - + @@ -23185,12 +20938,12 @@ - + - + @@ -23201,12 +20954,12 @@ - + - + @@ -23217,12 +20970,12 @@ - + - + @@ -23233,12 +20986,12 @@ - + - + @@ -23249,12 +21002,12 @@ - + - + @@ -23265,12 +21018,12 @@ - + - + @@ -23281,12 +21034,12 @@ - + - + @@ -23297,12 +21050,12 @@ - + - + @@ -23313,12 +21066,12 @@ - + - + @@ -23329,12 +21082,12 @@ - + - + @@ -23345,12 +21098,12 @@ - + - + @@ -23361,12 +21114,12 @@ - + - + @@ -23377,12 +21130,12 @@ - + - + @@ -23393,12 +21146,12 @@ - + - + @@ -23409,12 +21162,12 @@ - + - + @@ -23425,12 +21178,12 @@ - + - + @@ -23441,12 +21194,12 @@ - + - + @@ -23457,12 +21210,12 @@ - + - + @@ -23473,12 +21226,12 @@ - + - + @@ -23489,12 +21242,12 @@ - + - + @@ -23505,12 +21258,12 @@ - + - + @@ -23521,12 +21274,12 @@ - + - + @@ -23537,12 +21290,12 @@ - + - + @@ -23553,12 +21306,12 @@ - + - + @@ -23569,12 +21322,12 @@ - + - + @@ -23585,12 +21338,12 @@ - + - + @@ -23601,12 +21354,12 @@ - + - + @@ -23617,12 +21370,12 @@ - + - + @@ -23633,12 +21386,12 @@ - + - + @@ -23649,12 +21402,12 @@ - + - + @@ -23665,12 +21418,12 @@ - + - + @@ -23681,12 +21434,12 @@ - + - + @@ -23697,12 +21450,12 @@ - + - + @@ -23713,12 +21466,12 @@ - + - + @@ -23729,12 +21482,12 @@ - + - + @@ -23745,12 +21498,12 @@ - + - + @@ -23761,12 +21514,12 @@ - + - + @@ -23777,12 +21530,12 @@ - + - + @@ -23793,12 +21546,12 @@ - + - + @@ -23809,12 +21562,12 @@ - + - + @@ -23825,12 +21578,12 @@ - + - + @@ -23841,12 +21594,12 @@ - + - + @@ -23857,12 +21610,12 @@ - + - + @@ -23873,12 +21626,12 @@ - + - + @@ -23889,12 +21642,12 @@ - + - + @@ -23905,12 +21658,12 @@ - + - + @@ -23921,12 +21674,12 @@ - + - + @@ -23937,12 +21690,12 @@ - + - + @@ -23953,12 +21706,12 @@ - + - + @@ -23969,12 +21722,12 @@ - + - + @@ -23985,12 +21738,12 @@ - + - + @@ -24001,12 +21754,12 @@ - + - + @@ -24017,12 +21770,12 @@ - + - + @@ -24033,12 +21786,12 @@ - + - + @@ -24049,12 +21802,12 @@ - + - + @@ -24065,12 +21818,12 @@ - + - + @@ -24081,12 +21834,12 @@ - + - + @@ -24097,12 +21850,12 @@ - + - + @@ -24113,12 +21866,12 @@ - + - + @@ -24129,12 +21882,12 @@ - + - + @@ -24145,12 +21898,12 @@ - + - + @@ -24161,12 +21914,12 @@ - + - + @@ -24177,12 +21930,12 @@ - + - + @@ -24193,12 +21946,12 @@ - + - + @@ -24209,12 +21962,12 @@ - + - + @@ -24225,12 +21978,12 @@ - + - + @@ -24241,12 +21994,12 @@ - + - + @@ -24257,12 +22010,12 @@ - + - + @@ -24273,12 +22026,12 @@ - + - + @@ -24289,12 +22042,12 @@ - + - + @@ -24305,12 +22058,12 @@ - + - + @@ -24321,12 +22074,12 @@ - + - + @@ -24337,12 +22090,12 @@ - + - + @@ -24353,12 +22106,12 @@ - + - + @@ -24369,12 +22122,12 @@ - + - + @@ -24385,12 +22138,12 @@ - + - + @@ -24401,12 +22154,12 @@ - + - + @@ -24417,12 +22170,12 @@ - + - + @@ -24433,12 +22186,12 @@ - + - + @@ -24449,12 +22202,12 @@ - + - + @@ -24465,12 +22218,12 @@ - + - + @@ -24481,12 +22234,12 @@ - + - + @@ -24497,12 +22250,12 @@ - + - + @@ -24513,12 +22266,12 @@ - + - + @@ -24529,12 +22282,12 @@ - + - + @@ -26758,6 +24511,7 @@ + diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h index 4a84fa40..51e90f70 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -644,4 +644,10 @@ #include "hpm_gpiom_regs.h" #include "hpm_sysctl_regs.h" #include "hpm_trgm_regs.h" +#include "hpm_pcfg_regs.h" +#include "hpm_pgpr_regs.h" +#include "hpm_ppor_regs.h" +#include "hpm_bcfg_regs.h" +#include "hpm_bgpr_regs.h" +#include "hpm_bpor_regs.h" #endif /* HPM_SOC_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h index 7b89ffff..125a6eb7 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -31,6 +31,7 @@ */ #define I2S_SOC_MAX_CHANNEL_NUM (16U) #define I2S_SOC_MAX_TX_CHANNEL_NUM (8U) +#define I2S_SOC_MAX_TX_FIFO_DEPTH (8U) #define PDM_I2S HPM_I2S0 #define DAO_I2S HPM_I2S1 #define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U) @@ -108,9 +109,12 @@ #define ENET_SOC_DESC_ADDR_ALIGNMENT (32U) #define ENET_SOC_BUFF_ADDR_ALIGNMENT (4U) #define ENET_SOC_ADDR_MAX_COUNT (5U) -#define ENET_SOC_ADVANCED_TIMESTAMP_EN (1U) -#define ENET_SOC_IPC_FULL_CHKSUM_OFFLOAD_ENGINE (0U) -#define ENET_SOC_ALT_EHD_DES_LEN (ENET_SOC_ADVANCED_TIMESTAMP_EN || ENET_SOC_IPC_FULL_CHKSUM_OFFLOAD_ENGINE) ? (8U) : (4U) +#define ENET_SOC_ALT_EHD_DES_MIN_LEN (4U) +#define ENET_SOC_ALT_EHD_DES_MAX_LEN (8U) +#define ENET_SOC_ALT_EHD_DES_LEN (8U) +#define ENET_SOC_PPS_MAX_COUNT (2L) +#define ENET_SOC_PPS1_EN (1U) + /* * ADC Section */ @@ -124,8 +128,10 @@ #define ADC16_SOC_PARAMS_LEN (34U) #define ADC16_SOC_MAX_CH_NUM (15U) -#define ADC16_SOC_TEMP_CH_NUM (16U) +#define ADC16_SOC_TEMP_CH_EN (0U) +#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) #define ADC16_SOC_MAX_TRIG_CH_NUM (11U) +#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) /* * SYSCTL Section @@ -194,5 +200,20 @@ * OTP Section */ #define OTP_SOC_UUID_IDX (88U) +#define OTP_SOC_UUID_LEN (16U) /* in bytes */ + +/** + * PWM Section + * + */ +#define PWM_SOC_HRPWM_SUPPORT (0U) +#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) +#define PWM_SOC_TIMER_RESET_SUPPORT (1U) + +/** + * IOC Section + * + */ +#define IOC_SOC_PAD_MAX (487) #endif /* HPM_SOC_FEATURE_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h index 69d15211..22416c7d 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h @@ -1,5 +1,5 @@ /** - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -25,15 +25,11 @@ typedef enum { sysctl_retention_domain_sys = 0, sysctl_retention_domain_cpu0 = 2, - sysctl_retention_domain_cpu1 = 4, - sysctl_retention_domain_conn = 6, - sysctl_retention_domain_vis = 8, - sysctl_retention_domain_xtal24m = 10, - sysctl_retention_domain_pll0 = 11, - sysctl_retention_domain_pll1 = 12, - sysctl_retention_domain_pll2 = 13, - sysctl_retention_domain_pll3 = 14, - sysctl_retention_domain_pll4 = 15, + + sysctl_retention_domain_xtal24m = 4, + sysctl_retention_domain_pll0 = 5, + sysctl_retention_domain_pll1 = 6, + sysctl_retention_domain_pll2 = 7, } sysctl_retention_domain_t; /** @@ -51,10 +47,7 @@ typedef enum { */ typedef enum { sysctl_reset_domain_soc = 0, - sysctl_reset_domain_con, - sysctl_reset_domain_vis, sysctl_reset_domain_cpu0, - sysctl_reset_domain_cpu1, } sysctl_reset_domain_t; /** @@ -339,23 +332,19 @@ typedef enum { monitor_target_clk_irc24m = 1, monitor_target_clk_xtal_24m = 2, monitor_target_clk_usb0_phy = 3, - monitor_target_clk_usb1_phy = 4, + monitor_target_clk0_osc0 = 8, monitor_target_clk0_pll0 = 9, - monitor_target_clk0_pll1 = 10, - monitor_target_clk1_pll1 = 11, - monitor_target_clk0_pll2 = 12, - monitor_target_clk1_pll2 = 13, - monitor_target_clk0_pll3 = 14, - monitor_target_clk0_pll4 = 15, + monitor_target_clk1_pll0 = 10, + monitor_target_clk2_pll0 = 11, + monitor_target_clk0_pll1 = 12, + monitor_target_clk1_pll1 = 13, + monitor_target_clk0_pll2 = 14, + monitor_target_clk1_pll2 = 15, + monitor_target_clk_top_cpu0 = 128, monitor_target_clk_top_mchtmr0 = 129, - monitor_target_clk_top_cpu1 = 130, - monitor_target_clk_top_mchtmr1 = 131, - monitor_target_clk_top_axi0 = 132, - monitor_target_clk_top_axi1 = 133, - monitor_target_clk_top_axi2 = 134, - monitor_target_clk_top_ahb0 = 135, + monitor_target_clk_top_femc = 136, monitor_target_clk_top_xpi0 = 137, monitor_target_clk_top_xpi1 = 138, @@ -363,10 +352,7 @@ typedef enum { monitor_target_clk_top_gptmr1 = 140, monitor_target_clk_top_gptmr2 = 141, monitor_target_clk_top_gptmr3 = 142, - monitor_target_clk_top_gptmr4 = 143, - monitor_target_clk_top_gptmr5 = 144, - monitor_target_clk_top_gptmr6 = 145, - monitor_target_clk_top_gptmr7 = 146, + monitor_target_clk_top_uart0 = 147, monitor_target_clk_top_uart1 = 148, monitor_target_clk_top_uart2 = 149, @@ -375,14 +361,7 @@ typedef enum { monitor_target_clk_top_uart5 = 152, monitor_target_clk_top_uart6 = 153, monitor_target_clk_top_uart7 = 154, - monitor_target_clk_top_uart8 = 155, - monitor_target_clk_top_uart9 = 156, - monitor_target_clk_top_uarta = 157, - monitor_target_clk_top_uartb = 158, - monitor_target_clk_top_uartc = 159, - monitor_target_clk_top_uartd = 160, - monitor_target_clk_top_uarte = 161, - monitor_target_clk_top_uartf = 162, + monitor_target_clk_top_i2c0 = 163, monitor_target_clk_top_i2c1 = 164, monitor_target_clk_top_i2c2 = 165, @@ -393,28 +372,25 @@ typedef enum { monitor_target_clk_top_spi3 = 170, monitor_target_clk_top_can0 = 171, monitor_target_clk_top_can1 = 172, - monitor_target_clk_top_can2 = 173, - monitor_target_clk_top_can3 = 174, + monitor_target_clk_top_ptpc = 175, monitor_target_clk_top_ana0 = 176, monitor_target_clk_top_ana1 = 177, monitor_target_clk_top_ana2 = 178, - monitor_target_clk_top_aud0 = 179, - monitor_target_clk_top_aud1 = 180, - monitor_target_clk_top_aud2 = 181, - monitor_target_clk_top_dis0 = 182, - monitor_target_clk_top_cam0 = 183, - monitor_target_clk_top_cam1 = 184, + monitor_target_clk_top_ana3 = 179, + monitor_target_clk_top_aud0 = 180, + monitor_target_clk_top_aud1 = 181, + monitor_target_clk_top_eth0 = 185, - monitor_target_clk_top_eth1 = 186, + monitor_target_clk_top_ptp0 = 187, - monitor_target_clk_top_ptp1 = 188, + monitor_target_clk_top_ref0 = 189, monitor_target_clk_top_ref1 = 190, monitor_target_clk_top_ntmr0 = 191, - monitor_target_clk_top_ntmr1 = 192, + monitor_target_clk_top_sdxc0 = 193, - monitor_target_clk_top_sdxc1 = 194, + } monitor_target_t; /** diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h index ae1824c6..656458e9 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h index 3ebe6f7f..7532e4ad 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_trgm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h index ab2130b5..3d473dc7 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6360/system.c b/common/libraries/hpm_sdk/soc/HPM6360/system.c index 48ea8ead..3f742ad6 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/system.c +++ b/common/libraries/hpm_sdk/soc/HPM6360/system.c @@ -10,6 +10,10 @@ #include "hpm_soc.h" #include "hpm_l1c_drv.h" +#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP +#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 +#endif + void enable_plic_feature(void) { uint32_t plic_feature = 0; @@ -17,7 +21,7 @@ void enable_plic_feature(void) /* enabled vector mode and preemptive priority interrupt */ plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; #endif -#ifndef DISABLE_IRQ_PREEMPTIVE +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) /* enabled preemptive priority interrupt */ plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; #endif @@ -48,10 +52,14 @@ __attribute__((weak)) void system_init(void) #ifdef USE_S_MODE_IRQ delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); enable_s_irq_from_intc(); +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#endif #else +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP enable_global_irq(CSR_MSTATUS_MIE_MASK); #endif +#endif #ifndef CONFIG_NOT_ENABLE_ICACHE l1c_ic_enable(); diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld index 8b11547c..36c06531 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld @@ -157,11 +157,16 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld index 1d483be1..16001067 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld @@ -16,7 +16,7 @@ MEMORY DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) - SDRAM_NONCACHABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M + SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k } @@ -162,11 +162,16 @@ SECTIONS . = ALIGN(8); } > SDRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld index 8fbdb1c7..3fda3e42 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld @@ -180,11 +180,16 @@ SECTIONS . = ALIGN(8); } > SDRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > SDRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld index f93ca682..20679a56 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld @@ -161,11 +161,16 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld index 0d4d2ca7..77978af9 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld @@ -179,11 +179,16 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld index b0b5194a..1718fbbd 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld @@ -155,11 +155,16 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > AXI_SRAM_NONCACHEABLE + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S index a262a527..01aca3d0 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S @@ -46,6 +46,15 @@ _start: */ call c_startup +#if defined(__SES_RISCV) + /* Initialize the heap */ + la a0, __heap_start__ + la a1, __heap_end__ + sub a1, a1, a0 + la t1, __SEGGER_RTL_init_heap + jalr t1 +#endif + /* Do global constructors */ call __libc_init_array diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c index 5d01919b..6032f08f 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c @@ -100,7 +100,7 @@ __attribute__((weak)) void reset_handler(void) * a call to __cxa_atexit() with __dso_handle as one of the arguments. * The dummy versions of these symbols should be provided. */ -void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) +__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) { } diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c index a008dede..72b25741 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c @@ -109,7 +109,7 @@ void irq_handler_trap(void) long mcause = read_csr(CSR_MCAUSE); long mepc = read_csr(CSR_MEPC); long mstatus = read_csr(CSR_MSTATUS); -#if SUPPORT_PFT_ARCH +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH long mxstatus = read_csr(CSR_MXSTATUS); #endif #ifdef __riscv_dsp @@ -140,7 +140,7 @@ void irq_handler_trap(void) uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); if (irq_index) { /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ -#ifndef DISABLE_IRQ_PREEMPTIVE +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) enable_global_irq(CSR_MSTATUS_MIE_MASK); #endif ((isr_func_t)__vector_table[irq_index])(); @@ -176,7 +176,7 @@ void irq_handler_trap(void) /* Restore CSR */ write_csr(CSR_MSTATUS, mstatus); write_csr(CSR_MEPC, mepc); -#if SUPPORT_PFT_ARCH +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH write_csr(CSR_MXSTATUS, mxstatus); #endif #ifdef __riscv_dsp @@ -217,7 +217,7 @@ void irq_handler_s_trap(void) /* Machine-level interrupt from PLIC */ uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE); -#ifndef DISABLE_IRQ_PREEMPTIVE +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) enable_s_global_irq(CSR_SSTATUS_SIE_MASK); #endif ((isr_func_t)__vector_s_table[irq_index])(); diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h index 0ce7f255..27938d76 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml b/common/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml index 03d4e30b..e93db450 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml +++ b/common/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml @@ -7,7 +7,7 @@ HPM6700/HPM6400 device /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -20943,8 +20943,12 @@ Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_num CLOCK_DIVIDER clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. -set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk +0 for same adc_clk and bus_clk, +1 for 1:2, +2 for 1:3, +... +15 for 1:16 +Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk 0 4 read-write @@ -22540,14 +22544,14 @@ If cont_en is 0, this bit is not used 0x808 32 0x00000000 - 0x00000FFF + 0x00FFFFFF SEQ_WR_POINTER HW update this field after each dma write, it indicate the next dma write pointer. dma write address is (tar_addr+seq_wr_pointer)*4 0 - 12 + 24 read-only @@ -23725,8 +23729,12 @@ Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_num CLOCK_DIVIDER clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. -set to 3 can genenerate 50MHz adc_clk at 200MHz bus_clk. +0 for same adc_clk and bus_clk, +1 for 1:2, +2 for 1:3, +... +15 for 1:16 +Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk 0 4 read-write @@ -24645,7 +24653,7 @@ MUST set clock_period to 0 or 1 for adc16 reg access COV_END_CNT used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number). +should set to (21-convert_clock_number+1). 8 5 read-write @@ -30928,7 +30936,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -30942,7 +30951,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -30958,7 +30968,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -31239,7 +31250,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -31253,7 +31265,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -31269,7 +31282,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -31550,7 +31564,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -31564,7 +31579,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -31580,7 +31596,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -31861,7 +31878,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -31875,7 +31893,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -31891,7 +31910,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -32172,7 +32192,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -32186,7 +32207,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -32202,7 +32224,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -32483,7 +32506,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -32497,7 +32521,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -32513,7 +32538,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -32794,7 +32820,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -32808,7 +32835,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -32824,7 +32852,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -33105,7 +33134,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers -0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception +0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 24 4 read-write @@ -33119,7 +33149,8 @@ The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 21 3 read-write @@ -33135,7 +33166,8 @@ See field SrcBurstSize above for the definition of burst transfer byte number an 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer -0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception +0x6-x7: Reserved, setting this field with a reserved value triggers the error exception +for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 18 3 read-write @@ -38186,7 +38218,7 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c HWSHDWEDG When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. -This bit assign its which edge is used as shadow register hardware load event. +This bit assign its which edge is used as compare shadow register hardware load event. 1- Falling edge 0- Rising edge 24 @@ -38279,7 +38311,7 @@ User should write 1 to this bit after the active FAULT signal de-assert and befo 11: no force 1 2 - read-write + write-only SWFRC @@ -46823,7 +46855,7 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 0x0 32 0x00000000 - 0xFFFFFFFF + 0xFFF0001F SW_RST @@ -46890,13 +46922,6 @@ So a good procedure to stop and turn on the display is: 4 read-write - - RSV - Reserved - 5 - 15 - read-write - INV_PXDATA Indicates if value at the output (pixel data output) needs to be negated. @@ -47192,7 +47217,7 @@ So a good procedure to stop and turn on the display is: 0x1c 32 0x00000000 - 0xFFFFFFFF + 0xFFFFFF0F DMA_ERR @@ -47215,19 +47240,12 @@ So a good procedure to stop and turn on the display is: 8 read-write - - RSV - Reserved - 4 - 4 - read-write - URGENT_UNDERRUN Asserted when the output buffer urgent underrun condition encountered 3 1 - read-only + read-write VS_BLANK @@ -50722,15 +50740,8 @@ typically -16 (0x1F0). 0x400 32 0x00000000 - 0xFFFFFFFF + 0x0000007F - - RSV - Reserved - 7 - 25 - read-write - SEL_NUM Selected CLUT Number @@ -50784,8 +50795,15 @@ Hardware will automatically clear this bit when selected CLUT is updated accordi 0x0 32 0x00000000 - 0x3F9A8C7F + 0xBF9AAFFF + + RSV + Reserved + 31 + 1 + read-write + COLOR_EXT If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. @@ -50881,6 +50899,13 @@ When asserted, this bit clears RXFIFO on every SOF. 1 read-write + + RSV + Reserved + 13 + 1 + read-write + STORAGE_MODE 00: Normal Mode (one plane mode) @@ -50891,11 +50916,21 @@ When asserted, this bit clears RXFIFO on every SOF. 2 read-write + + RSV + Reserved + 7 + 3 + read-write + COLOR_FORMATS input color formats: -0010b: 24bit: RGB888 -0100b: 16bit: RGB565 +0010b:24bit:RGB888 +0011b:24bit:RGB666 +0100b:16bit:RGB565 +0101b:16bit:RGB444 +0110b:16bit:RGB555 0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) YUV YCrCb @@ -50910,6 +50945,7 @@ Note: YUV420 is not supported. the bit width of the sensor 0: 8 bits 1: 10 bits +3:24bits Others: Undefined 0 3 @@ -50923,8 +50959,15 @@ Others: Undefined 0x4 32 0x00000000 - 0x00003A4D + 0xFFFFFF5F + + RSV + Reserved + 14 + 18 + read-write + ERR_CL_BWID_CFG_INT_EN The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable @@ -50948,6 +50991,13 @@ Others: Undefined 1 read-write + + RSV + Reserved + 10 + 1 + read-write + EOF_INT_EN End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. @@ -50957,6 +51007,13 @@ Others: Undefined 1 read-write + + RSV + Reserved + 8 + 1 + read-write + RF_OR_INTEN RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. @@ -50966,6 +51023,13 @@ Others: Undefined 1 read-write + + RSV + Reserved + 4 + 1 + read-write + FB2_DMA_DONE_INTEN Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA @@ -50986,6 +51050,13 @@ transfer done. 1 read-write + + RSV + Reserved + 1 + 1 + read-write + SOF_INT_EN Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. @@ -51003,7 +51074,7 @@ transfer done. 0x10 32 0x00000000 - 0xFFFF8E2F + 0xFFFF8FEF FRMCNT_15_0 @@ -51037,6 +51108,13 @@ transfer done. 3 read-write + + RSV + Reserved + 6 + 3 + read-write + DMA_REQ_EN_RFF DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. @@ -51061,8 +51139,15 @@ transfer done. 0x24 32 0x00000000 - 0x000C26C4 + 0xFFFFA7FC + + RSV + Reserved + 20 + 12 + read-write + ERR_CL_BWID_CFG The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found @@ -51077,6 +51162,13 @@ transfer done. 1 write-only + + RSV + Reserved + 15 + 3 + read-write + RF_OR_INT RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing @@ -51105,6 +51197,13 @@ transfer done. 1 write-only + + RSV + Reserved + 8 + 1 + read-write + EOF_INT End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) @@ -51123,6 +51222,13 @@ transfer done. 1 write-only + + RSV + Reserved + 3 + 3 + read-write + HRESP_ERR_INT Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing @@ -51141,7 +51247,7 @@ transfer done. 0x30 32 0x00000000 - 0xFFFFFFFC + 0xFFFFFFFF PTR @@ -51151,6 +51257,13 @@ In Two-Plane Mode, Y buffer1 30 read-write + + RSV + Reserved + 0 + 2 + read-write + @@ -51159,7 +51272,7 @@ In Two-Plane Mode, Y buffer1 0x34 32 0x00000000 - 0xFFFFFFFC + 0xFFFFFFFF PTR @@ -51169,6 +51282,13 @@ In Two-Plane Mode, Y buffer2 30 read-write + + RSV + Reserved + 0 + 2 + read-write + @@ -51177,8 +51297,15 @@ In Two-Plane Mode, Y buffer2 0x38 32 0x00000000 - 0x0000FFFF + 0xFFFFFFFF + + RSV + Reserved + 16 + 16 + read-write + LINEBSP_STRIDE Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. @@ -51221,7 +51348,7 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 0x4c 32 0x00000000 - 0x80000780 + 0xFFFFE7BF CAM_ENABLE @@ -51230,6 +51357,13 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 1 read-write + + RSV + Reserved + 13 + 18 + read-write + AWQOS AWQOS for bus fabric arbitration @@ -51237,6 +51371,13 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 4 read-write + + RSV + Reserved + 0 + 6 + read-write + @@ -51293,7 +51434,7 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 0x58 32 0x00000000 - 0xC00001FF + 0xFFFFFFFF BINARY_EN @@ -51309,6 +51450,13 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 1 read-write + + RSV + Reserved + 9 + 21 + read-write + BIG_END Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. @@ -51355,7 +51503,7 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 0x70 32 0x00000000 - 0xDFFFFFFF + 0xFFFFFFFF YCBCR_MODE @@ -51375,6 +51523,13 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 1 read-write + + RSV + Reserved + 29 + 1 + read-write + C0 Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) @@ -51406,8 +51561,15 @@ typically -16 (0x1F0). 0x74 32 0x00000000 - 0x07FF07FF + 0xFFFFFFFF + + RSV + Reserved + 27 + 5 + read-write + C1 Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). @@ -51415,6 +51577,13 @@ typically -16 (0x1F0). 11 read-write + + RSV + Reserved + 11 + 5 + read-write + C4 Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). @@ -51430,8 +51599,15 @@ typically -16 (0x1F0). 0x78 32 0x00000000 - 0x07FF07FF + 0xFFFFFFFF + + RSV + Reserved + 27 + 5 + read-write + C2 Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). @@ -51439,6 +51615,13 @@ typically -16 (0x1F0). 11 read-write + + RSV + Reserved + 11 + 5 + read-write + C3 Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). @@ -51454,8 +51637,15 @@ typically -16 (0x1F0). 0x7c 32 0x00000000 - 0x00FFFFFF + 0xFFFFFFFF + + RSV + Reserved + 24 + 8 + read-write + LIMIT Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. @@ -51471,8 +51661,15 @@ typically -16 (0x1F0). 0x80 32 0x00000000 - 0x00FFFFFF + 0xFFFFFFFF + + RSV + Reserved + 24 + 8 + read-write + LIMIT Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. @@ -57866,7 +58063,7 @@ Write 0 to exit software reset mode. 0x8 32 0x00000000 - 0xFFFFFFFF + 0xFFFF0F3F DSTALPHA @@ -57882,28 +58079,6 @@ Write 0 to exit software reset mode. 8 read-write - - DSTALPHA_OP - The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream -1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) -2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream -Others: Reserved - 14 - 2 - read-write - - - SRCALPHA_OP - The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream -1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) -2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream -Others: Reserved - 12 - 2 - read-write - ABLEND_MODE Alpha Blending Mode @@ -57928,13 +58103,6 @@ Others: Reserved. 4 read-write - - RSV - Not suppoted yet - 6 - 2 - read-write - FORMAT Output buffer format. @@ -60244,7 +60412,7 @@ The selection of the Huffman table for the encoding of the DC coefficients in th 0xf2000000 0x0 - 0x302c + 0x105c registers @@ -60843,152 +61011,6 @@ When set, this bit enables the VLAN Tag inverse matching. The frames that do not - - VERSION - Version Register - 0x20 - 32 - 0x00000000 - 0x0000FFFF - - - USERVER - User-defined Version - 8 - 8 - read-only - - - SNPSVER - Synopsys-defined Version (3.7) - 0 - 8 - read-only - - - - - DEBUGGING - Debug Register - 0x24 - 32 - 0x00000000 - 0x037F0377 - - - TXSTSFSTS - MTL TxStatus FIFO Full Status - When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot accept any more frames for transmission. This bit is reserved in the GMAC-AHB and GMAC-DMA configurations. - 25 - 1 - read-only - - - TXFSTS - MTL Tx FIFO Not Empty Status -When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission. - 24 - 1 - read-only - - - TWCSTS - MTL Tx FIFO Write Controller Status -When high, this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO. - 22 - 1 - read-only - - - TRCSTS - MTL Tx FIFO Read Controller Status -This field indicates the state of the Tx FIFO Read Controller: -- 00: IDLE state -- 01: READ state (transferring data to the MAC transmitter) -- 10: Waiting for TxStatus from the MAC transmitter -- 11: Writing the received TxStatus or flushing the Tx FIFO - 20 - 2 - read-only - - - TXPAUSED - MAC Transmitter in Pause -When high, this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-only mode) and hence does not schedule any frame for transmission. - 19 - 1 - read-only - - - TFCSTS - MAC Transmit Frame Controller Status -This field indicates the state of the MAC Transmit Frame Controller module: -- 00: IDLE state -- 01: Waiting for status of previous frame or IFG or backoff period to be over -- 10: Generating and transmitting a Pause frame (in the full-duplex mode) -- 11: Transferring input frame for transmission - 17 - 2 - read-only - - - TPESTS - MAC GMII or MII Transmit Protocol Engine Status - When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state. - 16 - 1 - read-only - - - RXFSTS - MTL RxFIFO Fill-Level Status -This field gives the status of the fill-level of the Rx FIFO: -- 00: Rx FIFO Empty -- 01: Rx FIFO fill-level below flow-control deactivate threshold -- 10: Rx FIFO fill-level above flow-control activate threshold -- 11: Rx FIFO Full - 8 - 2 - read-only - - - RRCSTS - MTL RxFIFO Read Controller State -This field gives the state of the Rx FIFO read Controller: -- 00: IDLE state -- 01: Reading frame data -- 10: Reading frame status (or timestamp) -- 11: Flushing the frame data and status - 5 - 2 - read-only - - - RWCSTS - MTL Rx FIFO Write Controller Active Status - When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. - 4 - 1 - read-only - - - RFCFCSTS - MAC Receive Frame FIFO Controller Status - When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module. - RFCFCSTS[1] represents the status of small FIFO Read controller. - RFCFCSTS[0] represents the status of small FIFO Write controller. - 1 - 2 - read-only - - - RPESTS - MAC GMII or MII Receive Protocol Engine Status -When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state. - 0 - 1 - read-only - - - RWKFRMFILT Remote Wake-Up Frame Filter Register @@ -61363,7 +61385,7 @@ When set, this bit disables the assertion of the interrupt signal because of the AE Address Enable - This bit is always set to 1. + This bit is RO. The bit value is fixed at 1. 31 1 read-only @@ -61642,15 +61664,8 @@ This field contains the lower 32 bits of the second 6-byte MAC address. The cont 0xd8 32 0x00000000 - 0x0001003F + 0x0000003F - - SMIDRXS - Delay SMII RX Data Sampling with respect to the SMII SYNC Signal When set, the first bit of the SMII RX data is sampled one cycle after the SMII SYNC signal. When reset, the first bit of the SMII RX data is sampled along with the SMII SYNC signal. If the SMII PHY Interface with source synchronous mode is selected during core configuration, this bit is reserved (RO with default value). - 16 - 1 - read-only - FALSCARDET False Carrier Detected @@ -61724,44 +61739,6 @@ When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Regist - - GPIO - General Purpose IO Register - 0xe0 - 32 - 0x00000000 - 0x0F0F0F0F - - - GPIT - No description avaiable - 24 - 4 - read-write - - - GPIE - No description avaiable - 16 - 4 - read-write - - - GPO - No description avaiable - 8 - 4 - read-write - - - GPIS - No description avaiable - 0 - 4 - read-write - - - MMC_CNTRL MMC Control establishes the operating mode of MMC. @@ -62882,289 +62859,6 @@ retried frames. - - TXUNICASTFRAMES_GB - Number of good and bad unicast frames transmitted. - 0x13c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad unicast frames transmitted. - 0 - 32 - read-write - - - - - TXMULTICASTFRAMES_GB - Number of good and bad multicast frames transmitted. - 0x140 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad multicast frames transmitted. - 0 - 32 - read-write - - - - - TXBROADCASTFRAMES_GB - Number of good and bad broadcast frames transmitted. - 0x144 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad broadcast frames transmitted. - 0 - 32 - read-write - - - - - TXUNDERFLOWERROR - Number of frames aborted because of frame underflow error. - 0x148 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of frame underflow error. - 0 - 32 - read-write - - - - - TXSINGLECOL_G - Number of successfully transmitted frames after a single collision -in the half-duplex mode. - 0x14c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of successfully transmitted frames after a single collision in the half-duplex mode. - 0 - 32 - read-write - - - - - TXMULTICOL_G - Number of successfully transmitted frames after multiple collisions -in the half-duplex mode. - 0x150 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of successfully transmitted frames after multiple collisions in the half-duplex mode. - 0 - 32 - read-write - - - - - TXDEFERRED - Number of successfully transmitted frames after a deferral in the -half-duplex mode. - 0x154 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of successfully transmitted frames after a deferral in the half-duplex mode. - 0 - 32 - read-write - - - - - TXLATECOL - Number of frames aborted because of late collision error - 0x158 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of late collision error. - 0 - 32 - read-write - - - - - TXEXESSCOL - Number of frames aborted because of excessive (16) collision -errors - 0x15c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of excessive (16) collision errors. - 0 - 32 - read-write - - - - - TXCARRIERERROR - Number of frames aborted because of carrier sense error (no -carrier or loss of carrier). - 0x160 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of carrier sense error (no carrier or loss of carrier). - 0 - 32 - read-write - - - - - TXOCTETCOUNT_G - Number of bytes transmitted, exclusive of preamble, only in good -frames. - 0x164 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes transmitted, exclusive of preamble, only in good frames. - 0 - 32 - read-write - - - - - TXFRAMECOUNT_G - Number of good frames transmitted - 0x168 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good frames transmitted. - 0 - 32 - read-write - - - - - TXEXCESSDEF - Number of frames aborted because of excessive deferral error -(deferred for more than two max-sized frame times). - 0x16c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames aborted because of excessive deferral error (deferred for more than two max-sized frame times). - 0 - 32 - read-write - - - - - TXPAUSEFRAMES - Number of good Pause frames transmitted - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good Pause frames transmitted. - 0 - 32 - read-write - - - - - TXVLANFRAMES_G - Number of good VLAN frames transmitted, exclusive of retried -frames. - 0x174 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good VLAN frames transmitted, exclusive of retried frames. - 0 - 32 - read-write - - - - - TXOVERSIZE_G - Number of frames transmitted without errors and with length -greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged -frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC -Configuration Register)). - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). - 0 - 32 - read-write - - - RXFRAMECOUNT_GB Number of good and bad frames received @@ -63182,454 +62876,6 @@ Configuration Register)). - - RXOCTETCOUNT_G - Number of bytes received, exclusive of preamble, only in good -frames. - 0x184 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received, exclusive of preamble, in good and bad frames. - 0 - 32 - read-write - - - - - RXOCTETCOUNT_GB - Number of bytes received, exclusive of preamble, in good and bad -frames. - 0x188 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received, exclusive of preamble, only in good frames. - 0 - 32 - read-write - - - - - RXBROADCASTFRAMES_G - Number of good broadcast frames received - 0x18c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good broadcast frames received. - 0 - 32 - read-write - - - - - RXMULTICASTFRAMES_G - Number of good multicast frames received - 0x190 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good multicast frames received. - 0 - 32 - read-write - - - - - RXCRCERROR - Number of frames received with CRC error - 0x194 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with CRC error. - 0 - 32 - read-write - - - - - RXALIGNMENTERROR - Number of frames received with alignment (dribble) error. Valid -only in 10/100 mode - 0x198 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with alignment (dribble) error. Valid only in 10/100 mode. - 0 - 32 - read-write - - - - - RXRUNTERROR - Number of frames received with runt (<64 bytes and CRC error) -error. - 0x19c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with runt (<64 bytes and CRC error) error. - 0 - 32 - read-write - - - - - RXJABBERERROR - Number of giant frames received with length (including CRC) -greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with -CRC error. If Jumbo Frame mode is enabled, then frames of -length greater than 9,018 bytes (9,022 for VLAN tagged) are -considered as giant frames. - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. - 0 - 32 - read-write - - - - - RXUNDERSIZE_G - Number of frames received with length less than 64 bytes, without -any errors. - 0x1a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with length less than 64 bytes, without any errors. - 0 - 32 - read-write - - - - - RXOVERSIZE_G - Number of frames received without errors, with length greater -than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 -bytes if enabled in Bit 27 of Register 0 (MAC Configuration -Register)) - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). - 0 - 32 - read-write - - - - - RX64OCTETS_GB - Number of good and bad frames received with length 64 bytes, -exclusive of preamble. - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length 64 bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX65TO127OCTETS_GB - No description avaiable - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX128TO255OCTETS_GB - No description avaiable - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX256TO511OCTETS_GB - Number of good and bad frames received with length between -256 and 511 (inclusive) bytes, exclusive of preamble. - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX512TO1023OCTETS_GB - Number of good and bad frames received with length between -512 and 1023 (inclusive) bytes, exclusive of preamble. - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. - 0 - 32 - read-write - - - - - RX1024TOMAXOCTETS_GB - Number of good and bad frames received with length between -1024 and maxsize (inclusive) bytes, exclusive of preamble. - 0x1c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - RXUNICASTFRAMES_G - Number of received good unicast frames. - 0x1c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of received good unicast frames. - 0 - 32 - read-write - - - - - RXLENGTHERROR - Number of frames received with length error (Length type field ≠ -frame size), for all frames with valid length field. - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with length error (Length type field ≠ frame size), for all frames with valid length field. - 0 - 32 - read-write - - - - - RXOUTOFRANGETYPE - Number of frames received with length field not equal to the valid -frame size (greater than 1,500 but less than 1,536). - 0x1cc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). - 0 - 32 - read-write - - - - - RXPAUSEFRAMES - Number of good and valid Pause frames received. - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and valid Pause frames received. - 0 - 32 - read-write - - - - - RXFIFOOVERFLOW - Number of missed received frames because of FIFO overflow. -This counter is not present in the GMAC-CORE configuration. - 0x1d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of missed received frames because of FIFO overflow. This counter is not present in the GMAC-CORE configuration. - 0 - 32 - read-write - - - - - RXVLANFRAMES_GB - Number of good and bad VLAN frames received. - 0x1d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad VLAN frames received. - 0 - 32 - read-write - - - - - RXWATCHDOGERROR - Number of frames received with error because of watchdog -timeout error (frames with a data load larger than 2,048 bytes or -the value programmed in Register 55 (Watchdog Timeout -Register)). - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with error because of watchdog timeout error (frames with a data load larger than 2,048 bytes or the value programmed in Register 55 (Watchdog Timeout Register)). - 0 - 32 - read-write - - - - - RXRCVERROR - Number of frames received with Receive error or Frame Extension -error on the GMII or MII interface. - 0x1e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of frames received with Receive error or Frame Extension error on the GMII or MII interface. - 0 - 32 - read-write - - - - - RXCTRLFRAMES_G - Number of received good control frames - 0x1e4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of received good control frames. - 0 - 32 - read-write - - - MMC_IPC_INTR_MASK_RX MMC IPC Receive Checksum Offload Interrupt Mask maintains @@ -64121,52 +63367,161 @@ ICMP payload - RXIPV4_HDRERR_FRMS - Number of IPv4 datagrams received with header (checksum, -length, or version mismatch) errors - 0x214 + L3_L4_CFG_0_L3_L4_CTRL + Layer 3 and Layer 4 Control Register + 0x400 32 0x00000000 - 0xFFFFFFFF + 0x003DFFFD - FRMCNT - Number of IPv4 datagrams received with header (checksum, length, or version mismatch) errors + L4DPIM0 + Layer 4 Destination Port Inverse Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. + 21 + 1 + read-write + + + L4DPM0 + Layer 4 Destination Port Match Enable + When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. + 20 + 1 + read-write + + + L4SPIM0 + Layer 4 Source Port Inverse Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. + 19 + 1 + read-write + + + L4SPM0 + Layer 4 Source Port Match Enable +When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. + 18 + 1 + read-write + + + L4PEN0 + Layer 4 Protocol Enable +When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. + 16 + 1 + read-write + + + L3HDBM0 + Layer 3 IP DA Higher Bits Match + IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - … +- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 11 + 5 + read-write + + + L3HSBM0 + Layer 3 IP SA Higher Bits Match + IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: +- 0: No bits are masked. +- 1: LSb[0] is masked. +- 2: Two LSbs [1:0] are masked. - ... +- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. + 6 + 5 + read-write + + + L3DAIM0 + Layer 3 IP DA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. + 5 + 1 + read-write + + + L3DAM0 + Layer 3 IP DA Match Enable +When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. + 4 + 1 + read-write + + + L3SAIM0 + Layer 3 IP SA Inverse Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. + 3 + 1 + read-write + + + L3SAM0 + Layer 3 IP SA Match Enable +When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. + 2 + 1 + read-write + + + L3PEN0 + Layer 3 Protocol Enable + When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. 0 - 32 + 1 read-write - RXIPV4_NOPAY_FRMS - Number of IPv4 datagram frames received that did not have a -TCP, UDP, or ICMP payload processed by the Checksum engine - 0x218 + L3_L4_CFG_0_L4_ADDR + Layer 4 Address Register + 0x404 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine + L4DP0 + Layer 4 Destination Port Number Field +When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. + 16 + 16 + read-write + + + L4SP0 + Layer 4 Source Port Number Field + When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. 0 - 32 + 16 read-write - RXIPV4_FRAG_FRMS - Number of good IPv4 datagrams with fragmentation - 0x21c + L3_L4_CFG_0_L3_ADDR_0 + Layer 3 Address 0 Register + 0x410 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of good IPv4 datagrams with fragmentation + L3A00 + Layer 3 Address 0 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. 0 32 read-write @@ -64174,17 +63529,17 @@ TCP, UDP, or ICMP payload processed by the Checksum engine - RXIPV4_UDSBL_FRMS - Number of good IPv4 datagrams received that had a UDP -payload with checksum disabled - 0x220 + L3_L4_CFG_0_L3_ADDR_1 + Layer 3 Address 1 Register + 0x414 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of good IPv4 datagrams received that had a UDP payload with checksum disabled + L3A10 + Layer 3 Address 1 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. 0 32 read-write @@ -64192,17 +63547,17 @@ payload with checksum disabled - RXIPV6_GD_FRMS - Number of good IPv6 datagrams received with TCP, UDP, or -ICMP payloads - 0x224 + L3_L4_CFG_0_L3_ADDR_2 + Layer 3 Address 2 Register + 0x418 32 0x00000000 0xFFFFFFFF - FRMCNT - Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads + L3A20 + Layer 3 Address 2 Field + When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. 0 32 read-write @@ -64210,590 +63565,9 @@ ICMP payloads - RXIPV6_HDRERR_FRMS - Number of IPv6 datagrams received with header errors (length or -version mismatch) - 0x228 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of IPv6 datagrams received with header errors (length or version mismatch) - 0 - 32 - read-write - - - - - RXIPV6_NOPAY_FRMS - Number of IPv6 datagram frames received that did not have a -TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with -fragmentation or security extension headers - 0x22c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers - 0 - 32 - read-write - - - - - RXUDP_GD_FRMS - Number of good IP datagrams with a good UDP payload. This -counter is not updated when the rxipv4_udsbl_frms counter is -incremented. - 0x230 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented. - 0 - 32 - read-write - - - - - RXUDP_ERR_FRMS - Number of good IP datagrams whose UDP payload has a -checksum error - 0x234 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams whose UDP payload has a checksum error - 0 - 32 - read-write - - - - - RXTCP_GD_FRMS - Number of good IP datagrams with a good TCP payload - 0x238 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams with a good TCP payload - 0 - 32 - read-write - - - - - RXTCP_ERR_FRMS - Number of good IP datagrams whose TCP payload has a -checksum error - 0x23c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams whose TCP payload has a checksum error - 0 - 32 - read-write - - - - - RXICMP_GD_FRMS - Number of good IP datagrams with a good ICMP payload - 0x240 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams with a good ICMP payload - 0 - 32 - read-write - - - - - RXICMP_ERR_FRMS - Number of good IP datagrams whose ICMP payload has a -checksum error - 0x244 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IP datagrams whose ICMP payload has a checksum error - 0 - 32 - read-write - - - - - RXIPV4_GD_OCTETS - Number of bytes received in good IPv4 datagrams encapsulating -TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad -bytes are not included in this counter or in the octet counters listed -below). - 0x250 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in the octet counters listed below). - 0 - 32 - read-write - - - - - RXIPV4_HDRERR_OCTETS - Number of bytes received in IPv4 datagrams with header errors -(checksum, length, version mismatch). The value in the Length -field of IPv4 header is used to update this counter. - 0x254 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. - 0 - 32 - read-write - - - - - RXIPV4_NOPAY_OCTETS - Number of bytes received in IPv4 datagrams that did not have a -TCP, UDP, or ICMP payload. The value in the IPv4 header’s -Length field is used to update this counter. - 0x258 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 header’s Length field is used to update this counter. - 0 - 32 - read-write - - - - - RXIPV4_FRAG_OCTETS - Number of bytes received in fragmented IPv4 datagrams. The -value in the IPv4 header’s Length field is used to update this -counter - 0x25c - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header’s Length field is used to update this counter. - 0 - 32 - read-write - - - - - RXIPV4_UDSBL_OCTETS - Number of bytes received in a UDP segment that had the UDP -checksum disabled. This counter does not count IP Header bytes. - 0x260 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. - 0 - 32 - read-write - - - - - RXIPV6_GD_OCTETS - Number of bytes received in good IPv6 datagrams encapsulating -TCP, UDP or ICMPv6 data - 0x264 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data - 0 - 32 - read-write - - - - - RXIPV6_HDRERR_OCTETS - Number of bytes received in IPv6 datagrams with header errors -(length, version mismatch). The value in the IPv6 header’s Length -field is used to update this counter. - 0x268 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 header’s Length field is used to update this counter. - 0 - 32 - read-write - - - - - RXIPV6_NOPAY_OCTETS - Number of bytes received in IPv6 datagrams that did not have a -TCP, UDP, or ICMP payload. The value in the IPv6 header’s -Length field is used to update this counter. - 0x26c - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 header’s Length field is used to update this counter. - 0 - 32 - read-write - - - - - RXUDP_GD_OCTETS - Number of bytes received in a good UDP segment. This counter -(and the counters below) does not count IP header bytes. - 0x270 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes. - 0 - 32 - read-write - - - - - RXUDP_ERR_OCTETS - Number of bytes received in a UDP segment that had checksum -errors - 0x274 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a UDP segment that had checksum errors - 0 - 32 - read-write - - - - - RXTCP_GD_OCTETS - Number of bytes received in a good TCP segment - 0x278 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a good TCP segment - 0 - 32 - read-write - - - - - RXTCP_ERR_OCTETS - Number of bytes received in a TCP segment with checksum -errors - 0x27c - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a TCP segment with checksum errors - 0 - 32 - read-write - - - - - RXICMP_GD_OCTETS - Number of bytes received in a good ICMP segment - 0x280 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYTECNT - Number of bytes received in a good ICMP segment - 0 - 32 - read-write - - - - - L3_L4_CFG_0_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x400 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L3_L4_CFG_0_L4_ADDR - Layer 4 Address Register - 0x404 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_L4_CFG_0_L3_ADDR_0 - Layer 3 Address 0 Register - 0x410 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_0_L3_ADDR_1 - Layer 3 Address 1 Register - 0x414 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_L4_CFG_0_L3_ADDR_2 - Layer 3 Address 2 Register - 0x418 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_L4_CFG_0_L3_ADDR_3 - Layer 3 Address 3 Register - 0x41c + L3_L4_CFG_0_L3_ADDR_3 + Layer 3 Address 3 Register + 0x41c 32 0x00000000 0xFFFFFFFF @@ -64807,124 +63581,6 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - - L3_L4_CFG_1_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x430 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - L3_L4_CFG_1_L4_ADDR Layer 4 Address Register @@ -65022,124 +63678,6 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - - L3_L4_CFG_2_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x460 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - L3_L4_CFG_2_L4_ADDR Layer 4 Address Register @@ -65237,124 +63775,6 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - - L3_L4_CFG_3_L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x490 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - L3_L4_CFG_3_L4_ADDR Layer 4 Address Register @@ -65452,150 +63872,6 @@ When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer - - HASH_TABLE_REGISTER0 - Hash Table Register 0 - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER1 - Hash Table Register 1 - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER2 - Hash Table Register 2 - 0x508 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER3 - Hash Table Register 3 - 0x50c - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER4 - Hash Table Register 4 - 0x510 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER5 - Hash Table Register 5 - 0x514 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER6 - Hash Table Register 6 - 0x518 - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - - - HASH_TABLE_REGISTER7 - Hash Table Register 7 - 0x51c - 32 - 0x00000000 - 0xFFFFFFFF - - - HT31T0 - First 32 bits of Hash Table - This field contains the first 32 Bits (31:0) of the Hash table. - 0 - 32 - read-write - - - VLAN_TAG_INC_RPL VLAN Tag Inclusion or Replacement Register @@ -66127,7 +64403,7 @@ When set, this bit indicates that the value of system time is greater than or eq 0x72c 32 0x00000000 - 0x6767677F + 0x6767777F TRGTMODSEL3 @@ -66169,6 +64445,14 @@ This field indicates the Target Time registers (register 480 and 481) mode for P 2 read-write + + PPSEN1 + Flexible PPS1 Output Mode Enable +When set high, Bits[10:8] function as PPSCMD. + 12 + 1 + read-write + PPSCMD1 Flexible PPS1 Output Control @@ -67570,283 +65854,6 @@ Cleared on Reset. Pointer updated by the DMA during operation. - - DMA_HW_FEATURE - HW Feature Register - 0x1058 - 32 - 0x00000000 - 0x7FFFFFFF - - - ACTPHYIF - Active or selected PHY interface -When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. -- 000: GMII or MII -- 001: RGMII -- 010: SGMII -- 011: TBI -- 100: RMII -- 101: RTBI -- 110: SMII -- 111: RevMII - All Others: Reserved - 28 - 3 - read-write - - - SAVLANINS - Source Address or VLAN Insertion - 27 - 1 - read-write - - - FLEXIPPSEN - Flexible Pulse-Per-Second Output - 26 - 1 - read-write - - - INTTSEN - Timestamping with Internal System Time - 25 - 1 - read-write - - - ENHDESSEL - Alternate (Enhanced Descriptor) - 24 - 1 - read-write - - - TXCHCNT - Number of additional Tx Channels - 22 - 2 - read-write - - - RXCHCNT - Number of additional Rx Channels - 20 - 2 - read-write - - - RXFIFOSIZE - Rx FIFO > 2,048 Bytes - 19 - 1 - read-write - - - RXTYP2COE - IP Checksum Offload (Type 2) in Rx - 18 - 1 - read-write - - - RXTYP1COE - IP Checksum Offload (Type 1) in Rx Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE = 1. - 17 - 1 - read-write - - - TXCOESEL - Checksum Offload in Tx - 16 - 1 - read-write - - - AVSEL - AV feature - 15 - 1 - read-write - - - EEESEL - Energy Efficient Ethernet - 14 - 1 - read-write - - - TSVER2SEL - IEEE 1588-2008 Advanced timestamp - 13 - 1 - read-write - - - TSVER1SEL - Only IEEE 1588-2002 timestamp - 12 - 1 - read-write - - - MMCSEL - RMON module - 11 - 1 - read-write - - - MGKSEL - PMT magic packet - 10 - 1 - read-write - - - RWKSEL - PMT remote wake-up frame - 9 - 1 - read-write - - - SMASEL - SMA (MDIO) Interface - 8 - 1 - read-write - - - L3L4FLTREN - Layer 3 and Layer 4 feature - 7 - 1 - read-write - - - PCSSEL - PCS registers (TBI, SGMII, or RTBI PHY interface) - 6 - 1 - read-write - - - ADDMACADRSEL - Multiple MAC Address registers - 5 - 1 - read-write - - - HASHSEL - HASH filter - 4 - 1 - read-write - - - EXTHASHEN - Expanded DA Hash filter - 3 - 1 - read-write - - - HDSEL - Half-duplex support - 2 - 1 - read-write - - - GMIISEL - 1000 Mbps support - 1 - 1 - read-write - - - MIISEL - 10 or 100 Mbps support - 0 - 1 - read-write - - - - - CTRL0 - Control Register 0 - 0x3000 - 32 - 0x00000000 - 0x000003FF - - - ENET0_RXCLK_DLY_SEL - No description avaiable - 5 - 5 - read-write - - - ENET0_TXCLK_DLY_SEL - No description avaiable - 0 - 5 - read-write - - - - - CTRL2 - Control Register 1 - 0x3008 - 32 - 0x00000000 - 0x2008F400 - - - ENET0_LPI_IRQ_EN - No description avaiable - 29 - 1 - read-write - - - ENET0_REFCLK_OE - No description avaiable - 19 - 1 - read-write - - - ENET0_PHY_INF_SEL - No description avaiable - 13 - 3 - read-write - - - ENET0_FLOWCTRL - No description avaiable - 12 - 1 - read-write - - - ENET0_RMII_TXCLK_SEL - No description avaiable - 10 - 1 - read-write - - - @@ -67872,7 +65879,7 @@ When you have multiple PHY interfaces in your configuration, this field indicate 0x0 32 0x00000000 - 0xFFFFFFFF + 0xFFFC7FFF CNTUPT @@ -67885,8 +65892,8 @@ This bit will be auto cleared after 1 cycle RESERVED not exist - 15 - 16 + 18 + 13 read-write @@ -68147,7 +66154,7 @@ User should set this bit before set CMPEN to 1. 0x40 32 0x00000000 - 0xFFFFFFFF + 0xFFFC7FFF CNTUPT @@ -68160,8 +66167,8 @@ This bit will be auto cleared after 1 cycle RESERVED not exist - 15 - 16 + 18 + 13 read-write @@ -68422,7 +66429,7 @@ User should set this bit before set CMPEN to 1. 0x80 32 0x00000000 - 0xFFFFFFFF + 0xFFFC7FFF CNTUPT @@ -68435,8 +66442,8 @@ This bit will be auto cleared after 1 cycle RESERVED not exist - 15 - 16 + 18 + 13 read-write @@ -68697,7 +66704,7 @@ User should set this bit before set CMPEN to 1. 0xc0 32 0x00000000 - 0xFFFFFFFF + 0xFFFC7FFF CNTUPT @@ -68710,8 +66717,8 @@ This bit will be auto cleared after 1 cycle RESERVED not exist - 15 - 16 + 18 + 13 read-write @@ -72364,7 +70371,8 @@ Values: RESP_ERR_CHK_ENABLE Response Error Check Enable -The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. +The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. +If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. Note: - Response error check must not be enabled for any response type other than R1 and R5. - Response check must not be enabled for the tuning command. @@ -73161,7 +71169,8 @@ In SD/UHS-II mode, this bit is irrelevant. RESP_ERR Response Error -Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. +Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. +If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. Values: 0x0 (FALSE): No error 0x1 (TRUE): Error @@ -76024,23 +74033,6 @@ This field stores the argument of the last received command response. Controller - - MSHC_CTRL - No description avaiable - 0x508 - 32 - 0x00000000 - 0x00000001 - - - CMD_CONFLICT_CHECK - No description avaiable - 0 - 1 - read-write - - - MBIU_CTRL Y @@ -76688,6 +74680,7 @@ set from pad， two option here: Configuration Register 0x10 32 + 0x00000001 0xFFFFFFFF @@ -77005,13 +74998,13 @@ Read this register to get one byte of data from the FIFO. 0x24 32 0x00001E00 - 0xFFFFFFFF + 0x000F9FFF RESERVED No description avaiable - 13 - 19 + 15 + 5 read-write @@ -77062,7 +75055,7 @@ Slave: The direction of the last received transaction. DATACNT Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means 256 bytes. DataCnt will be decreased by one for each byte transmitted/received. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. @@ -77272,7 +75265,7 @@ This field is only valid when the controller is in the master mode.0x0 32 0x30000000 - 0xFFFE0101 + 0xFFFE0001 SFTRST @@ -77372,14 +75365,6 @@ Write to 1 will clock gate for most logic of the SDP block, dynamic power saving 1 read-write - - RDSCEN - when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) -when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - 8 - 1 - read-write - INTEN Interrupt Enablement, controlled by SW. @@ -77404,6 +75389,7 @@ when set to "0", the 1st data packet descriptor loacted in the memeory(pointed b AES algorithem selection. 0x0 = AES 128; 0x1 = AES 256; +0x8 = SM4； Others, reserved. 28 4 @@ -124884,7 +122870,7 @@ bit19: RTC alarm interrupt SCG control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: clock gated according to low power flow +00,01: reserved 10: clock is always off 11: clock is always on bit0-1: fuse diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_acmp_soc_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_acmp_soc_drv.h new file mode 100644 index 00000000..4b8d4831 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_acmp_soc_drv.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_ACMP_SOC_DRV_H +#define HPM_ACMP_SOC_DRV_H + +#include "hpm_soc.h" + +static inline void acmp_enable_bandgap(void) +{ + uint32_t clk_div_temp; + + clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(HPM_ADC3->CONV_CFG1); + + /* Set input clock divider temporarily */ + HPM_ADC3->CONV_CFG1 = (HPM_ADC3->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); + + /* Enable ADC config clock */ + HPM_ADC3->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; + + /* Enable bandgap_en */ + HPM_ADC3->ADC16_CONFIG0 |= ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK; + + /* Recover input clock divider */ + HPM_ADC3->CONV_CFG1 = (HPM_ADC3->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) + | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); + + /* Disable ADC config clock */ + HPM_ADC3->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; +} + +#endif /* HPM_ACMP_SOC_DRV_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h index c7676218..83698146 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_batt_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_bcfg_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_drv.h similarity index 100% rename from common/libraries/hpm_sdk/drivers/inc/hpm_bcfg_drv.h rename to common/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_drv.h diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_bcfg_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_regs.h similarity index 99% rename from common/libraries/hpm_sdk/soc/ip/hpm_bcfg_regs.h rename to common/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_regs.h index 597885c0..a2fd6616 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_bcfg_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_bcfg_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h new file mode 100644 index 00000000..b5b4531e --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BGPR_H +#define HPM_BGPR_H + +typedef struct { + __RW uint32_t BATT_GPR0; /* 0x0: Generic control */ + __RW uint32_t BATT_GPR1; /* 0x4: Generic control */ + __RW uint32_t BATT_GPR2; /* 0x8: Generic control */ + __RW uint32_t BATT_GPR3; /* 0xC: Generic control */ + __RW uint32_t BATT_GPR4; /* 0x10: Generic control */ + __RW uint32_t BATT_GPR5; /* 0x14: Generic control */ + __RW uint32_t BATT_GPR6; /* 0x18: Generic control */ + __RW uint32_t BATT_GPR7; /* 0x1C: Generic control */ +} BGPR_Type; + + +/* Bitfield definition for register: BATT_GPR0 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR0_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR0_GPR_SHIFT (0U) +#define BGPR_BATT_GPR0_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR0_GPR_SHIFT) & BGPR_BATT_GPR0_GPR_MASK) +#define BGPR_BATT_GPR0_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR0_GPR_MASK) >> BGPR_BATT_GPR0_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR1 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR1_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR1_GPR_SHIFT (0U) +#define BGPR_BATT_GPR1_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR1_GPR_SHIFT) & BGPR_BATT_GPR1_GPR_MASK) +#define BGPR_BATT_GPR1_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR1_GPR_MASK) >> BGPR_BATT_GPR1_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR2 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR2_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR2_GPR_SHIFT (0U) +#define BGPR_BATT_GPR2_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR2_GPR_SHIFT) & BGPR_BATT_GPR2_GPR_MASK) +#define BGPR_BATT_GPR2_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR2_GPR_MASK) >> BGPR_BATT_GPR2_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR3 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR3_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR3_GPR_SHIFT (0U) +#define BGPR_BATT_GPR3_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR3_GPR_SHIFT) & BGPR_BATT_GPR3_GPR_MASK) +#define BGPR_BATT_GPR3_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR3_GPR_MASK) >> BGPR_BATT_GPR3_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR4 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR4_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR4_GPR_SHIFT (0U) +#define BGPR_BATT_GPR4_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR4_GPR_SHIFT) & BGPR_BATT_GPR4_GPR_MASK) +#define BGPR_BATT_GPR4_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR4_GPR_MASK) >> BGPR_BATT_GPR4_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR5 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR5_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR5_GPR_SHIFT (0U) +#define BGPR_BATT_GPR5_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR5_GPR_SHIFT) & BGPR_BATT_GPR5_GPR_MASK) +#define BGPR_BATT_GPR5_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR5_GPR_MASK) >> BGPR_BATT_GPR5_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR6 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR6_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR6_GPR_SHIFT (0U) +#define BGPR_BATT_GPR6_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR6_GPR_SHIFT) & BGPR_BATT_GPR6_GPR_MASK) +#define BGPR_BATT_GPR6_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR6_GPR_MASK) >> BGPR_BATT_GPR6_GPR_SHIFT) + +/* Bitfield definition for register: BATT_GPR7 */ +/* + * GPR (RW) + * + * Generic control + */ +#define BGPR_BATT_GPR7_GPR_MASK (0xFFFFFFFFUL) +#define BGPR_BATT_GPR7_GPR_SHIFT (0U) +#define BGPR_BATT_GPR7_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR7_GPR_SHIFT) & BGPR_BATT_GPR7_GPR_MASK) +#define BGPR_BATT_GPR7_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR7_GPR_MASK) >> BGPR_BATT_GPR7_GPR_SHIFT) + + + + +#endif /* HPM_BGPR_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_drv.h new file mode 100644 index 00000000..e37bac24 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_drv.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BPOR_DRV_H +#define HPM_BPOR_DRV_H + +#include "hpm_common.h" +#include "hpm_bpor_regs.h" + +/** + * + * @brief BPOR driver APIs + * @defgroup bpor_interface BPOR driver APIs + * @ingroup io_interfaces + * @{ + * + */ + +/** @brief Define BPOR power on cause */ +typedef enum { + bpor_power_on_cause_wbutn = 1 << 0, + bpor_power_on_cause_safety_violation = 1 << 1, + bpor_power_on_cause_rtc_0 = 1 << 2, + bpor_power_on_cause_rtc_1 = 1 << 3, + bpor_power_on_cause_gpio = 1 << 4 +} bpor_power_on_cause_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get power on cause + * + * @param[in] ptr BPOR base address + * @retval POR_CAUSE register value + */ +static inline uint32_t bpor_get_power_on_cause(BPOR_Type *ptr) +{ + return ptr->POR_CAUSE; +} + +/** + * @brief Clear power on cause + * + * @param[in] ptr BPOR base address + * @param[in] mask cause status to be cleared + */ +static inline void bpor_clear_power_on_cause(BPOR_Type *ptr, uint8_t mask) +{ + ptr->POR_CAUSE |= mask; +} + +/** + * @brief enable power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be enabled + */ +static inline void bpor_enable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) +{ + ptr->POR_SELECT |= cause; +} + +/** + * @brief disable power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be disabled + */ +static inline void bpor_disable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) +{ + ptr->POR_SELECT &= ~cause; +} + +/** + * @brief Set power on cause + * + * @param[in] ptr BPOR base address + * @param[in] cause wake up cause to be used + */ +static inline void bpor_set_power_on_cause(BPOR_Type *ptr, uint8_t cause) +{ + ptr->POR_SELECT = (ptr->POR_SELECT & ~BPOR_POR_SELECT_SELECT_MASK) | cause; +} + +/** + * @brief Enable register value retention when power down occurs + * + * @param[in] ptr BPOR base address + */ +static inline void bpor_enable_reg_value_retention(BPOR_Type *ptr) +{ + ptr->POR_CONFIG |= BPOR_POR_CONFIG_RETENTION_MASK; +} + +/** + * @brief Disable register value retention when power down occurs + * + * @param[in] ptr BPOR base address + */ +static inline void bpor_disable_reg_value_retention(BPOR_Type *ptr) +{ + ptr->POR_CONFIG &= ~BPOR_POR_CONFIG_RETENTION_MASK; +} + +/** + * @brief Set power down counter + * + * @param[in] ptr BPOR base address + * @param[in] counter counter value + */ +static inline void bpor_set_power_down_counter(BPOR_Type *ptr, uint16_t counter) +{ + ptr->POR_CONTROL = BPOR_POR_CONTROL_COUNTER_SET(counter); +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_BPOR_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_regs.h new file mode 100644 index 00000000..539c5840 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_bpor_regs.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_BPOR_H +#define HPM_BPOR_H + +typedef struct { + __RW uint32_t POR_CAUSE; /* 0x0: Power on cause */ + __RW uint32_t POR_SELECT; /* 0x4: Power on select */ + __RW uint32_t POR_CONFIG; /* 0x8: Power on reset config */ + __RW uint32_t POR_CONTROL; /* 0xC: Power down control */ +} BPOR_Type; + + +/* Bitfield definition for register: POR_CAUSE */ +/* + * CAUSE (RW) + * + * Power on cause, each bit represnts one cause, write 1 to clear each bit + * bit0: wakeup button + * bit1: security violation + * bit2: RTC alarm 0 + * bit3: RTC alarm 1 + * bit4: GPIO + */ +#define BPOR_POR_CAUSE_CAUSE_MASK (0x1FU) +#define BPOR_POR_CAUSE_CAUSE_SHIFT (0U) +#define BPOR_POR_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << BPOR_POR_CAUSE_CAUSE_SHIFT) & BPOR_POR_CAUSE_CAUSE_MASK) +#define BPOR_POR_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & BPOR_POR_CAUSE_CAUSE_MASK) >> BPOR_POR_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: POR_SELECT */ +/* + * SELECT (RW) + * + * Power on cause select, each bit represnts one cause, value 1 enables corresponding cause + * bit0: wakeup button + * bit1: security violation + * bit2: RTC alarm 0 + * bit3: RTC alarm 1 + * bit4: GPIO + */ +#define BPOR_POR_SELECT_SELECT_MASK (0x1FU) +#define BPOR_POR_SELECT_SELECT_SHIFT (0U) +#define BPOR_POR_SELECT_SELECT_SET(x) (((uint32_t)(x) << BPOR_POR_SELECT_SELECT_SHIFT) & BPOR_POR_SELECT_SELECT_MASK) +#define BPOR_POR_SELECT_SELECT_GET(x) (((uint32_t)(x) & BPOR_POR_SELECT_SELECT_MASK) >> BPOR_POR_SELECT_SELECT_SHIFT) + +/* Bitfield definition for register: POR_CONFIG */ +/* + * RETENTION (RW) + * + * retention battery domain setting + * 0: battery reset on reset pin reset happen + * 1: battery domain retention when reset pin reset happen + */ +#define BPOR_POR_CONFIG_RETENTION_MASK (0x1U) +#define BPOR_POR_CONFIG_RETENTION_SHIFT (0U) +#define BPOR_POR_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << BPOR_POR_CONFIG_RETENTION_SHIFT) & BPOR_POR_CONFIG_RETENTION_MASK) +#define BPOR_POR_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & BPOR_POR_CONFIG_RETENTION_MASK) >> BPOR_POR_CONFIG_RETENTION_SHIFT) + +/* Bitfield definition for register: POR_CONTROL */ +/* + * COUNTER (RW) + * + * Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 + */ +#define BPOR_POR_CONTROL_COUNTER_MASK (0xFFFFU) +#define BPOR_POR_CONTROL_COUNTER_SHIFT (0U) +#define BPOR_POR_CONTROL_COUNTER_SET(x) (((uint32_t)(x) << BPOR_POR_CONTROL_COUNTER_SHIFT) & BPOR_POR_CONTROL_COUNTER_MASK) +#define BPOR_POR_CONTROL_COUNTER_GET(x) (((uint32_t)(x) & BPOR_POR_CONTROL_COUNTER_MASK) >> BPOR_POR_CONTROL_COUNTER_SHIFT) + + + + +#endif /* HPM_BPOR_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c b/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c index d7b1e3b2..9e897fef 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,8 +9,7 @@ #include "hpm_clock_drv.h" #include "hpm_sysctl_drv.h" #include "hpm_pllctl_drv.h" -#include "hpm_csr_regs.h" -#include "riscv/riscv_core.h" + /*********************************************************************************************************************** * Definitions **********************************************************************************************************************/ @@ -64,7 +63,7 @@ static uint32_t get_frequency_for_wdg(uint32_t instance); */ static void switch_ip_clock(clock_name_t clock_name, bool on); -static uint64_t get_core_mcycle(void); +static uint64_t hpm_csr_get_core_cycle(void); /*********************************************************************************************************************** * Variables @@ -472,35 +471,19 @@ void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) } } - -static uint64_t get_core_mcycle(void) -{ - uint64_t result; - uint32_t resultl_first = read_csr(CSR_CYCLE); - uint32_t resulth = read_csr(CSR_CYCLEH); - uint32_t resultl_second = read_csr(CSR_CYCLE); - if (resultl_first < resultl_second) { - result = ((uint64_t)resulth << 32) | resultl_first; /* if MCYCLE didn't roll over, return the value directly */ - } else { - resulth = read_csr(CSR_CYCLEH); - result = ((uint64_t)resulth << 32) | resultl_second; /* if MCYCLE rolled over, need to get the MCYCLEH again */ - } - return result; - } - void clock_cpu_delay_us(uint32_t us) { uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = get_core_mcycle() + ticks_per_us * us; - while (get_core_mcycle() < expected_ticks) { + uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; + while (hpm_csr_get_core_cycle() < expected_ticks) { } } void clock_cpu_delay_ms(uint32_t ms) { uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = get_core_mcycle() + (uint64_t)ticks_per_us * 1000UL * ms; - while (get_core_mcycle() < expected_ticks) { + uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * ms; + while (hpm_csr_get_core_cycle() < expected_ticks) { } } @@ -509,4 +492,4 @@ void clock_update_core_clock(void) uint32_t hart_id = read_csr(CSR_MHARTID); clock_name_t cpu_clk_name = (hart_id == 1U) ? clock_cpu1 : clock_cpu0; hpm_core_clock = clock_get_frequency(cpu_clk_name); -} \ No newline at end of file +} diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h index d298b3df..23a46a75 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,6 +9,7 @@ #include "hpm_common.h" #include "hpm_sysctl_drv.h" +#include "hpm_csr_drv.h" /** * @brief CLOCK driver APIs diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h index da161186..88d1c2a5 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_csr_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h index 5261a769..74ba8c3f 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_dmamux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_enet_soc_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_enet_soc_drv.h index 9f85e8f8..18b35d6e 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_enet_soc_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_enet_soc_drv.h @@ -66,10 +66,10 @@ static inline hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_d if (ptr == HPM_ENET0) { HPM_CONCTL->CTRL0 &= ~(CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK | CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK); - HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(rx_delay); + HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(rx_delay); } else if (ptr == HPM_ENET1) { HPM_CONCTL->CTRL0 &= ~(CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK | CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK); - HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(rx_delay); + HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(rx_delay); } else { return status_invalid_argument; } @@ -126,4 +126,4 @@ static inline hpm_stat_t enet_rgmii_enable_clock(ENET_Type *ptr) } /* __cplusplus */ #endif -#endif /* HPM_ENET_SOC_DRV_H */ \ No newline at end of file +#endif /* HPM_ENET_SOC_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h index fc0eea5e..54f9f0ba 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h index 8b79a326..565f687b 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h @@ -304,7 +304,7 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) */ #define RESTORE_CSR(r) write_csr(r, __##r); -#if SUPPORT_PFT_ARCH +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH #define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) #define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) #else diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h index 3ed688c4..251ee8e6 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ioc_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h index 4bcbdc4a..37348a36 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -659,7 +659,6 @@ #define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) #define IOC_PC13_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PC13_FUNC_CTL_FEMC_BA0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC13_FUNC_CTL_ETH1_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PC14_FUNC_CTL function mux definitions */ #define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -695,7 +694,6 @@ #define IOC_PC18_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PC18_FUNC_CTL_FEMC_RAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PC18_FUNC_CTL_TRGM3_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC18_FUNC_CTL_ETH1_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PC19_FUNC_CTL function mux definitions */ #define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -796,7 +794,6 @@ #define IOC_PD00_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PD00_FUNC_CTL_FEMC_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD00_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD00_FUNC_CTL_ETH1_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PD01_FUNC_CTL function mux definitions */ #define IOC_PD01_FUNC_CTL_GPIO_D_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -836,7 +833,6 @@ #define IOC_PD05_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PD05_FUNC_CTL_FEMC_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) #define IOC_PD05_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD05_FUNC_CTL_ETH1_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PD06_FUNC_CTL function mux definitions */ #define IOC_PD06_FUNC_CTL_GPIO_D_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1185,7 +1181,6 @@ #define IOC_PE14_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) #define IOC_PE14_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) #define IOC_PE14_FUNC_CTL_ETH1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE14_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PE15_FUNC_CTL function mux definitions */ #define IOC_PE15_FUNC_CTL_GPIO_E_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1279,7 +1274,6 @@ #define IOC_PE24_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) #define IOC_PE24_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) #define IOC_PE24_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE24_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) #define IOC_PE24_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PE25_FUNC_CTL function mux definitions */ @@ -1377,7 +1371,6 @@ #define IOC_PF03_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) #define IOC_PF03_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) #define IOC_PF03_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF03_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) /* IOC_PF04_FUNC_CTL function mux definitions */ #define IOC_PF04_FUNC_CTL_GPIO_F_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) @@ -1420,7 +1413,6 @@ #define IOC_PF08_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) #define IOC_PF08_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) #define IOC_PF08_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF08_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) #define IOC_PF08_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) /* IOC_PF09_FUNC_CTL function mux definitions */ diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h new file mode 100644 index 00000000..e99e0837 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h @@ -0,0 +1,639 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PCFG_DRV_H +#define HPM_PCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_pcfg_regs.h" + +/** + * + * @brief PCFG driver APIs + * @defgroup pcfg_interface PCFG driver APIs + * @ingroup io_interfaces + * @{ + */ +#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW (0x1UL) + +#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) +#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) +#define PCFG_PERIPH_SET_CLOCK_AUTO(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW << (p)) + +/* @brief PCFG irc24m reference */ +typedef enum { + pcfg_irc24m_reference_32k = 0, + pcfg_irc24m_reference_24m_xtal = 1 +} pcfg_irc24m_reference_t; + +/* @brief PCFG dcdc current limit */ +typedef enum { + pcfg_dcdc_lp_current_limit_250ma = 0, + pcfg_dcdc_lp_current_limit_200ma = 1, +} pcfg_dcdc_lp_current_limit_t; + +/* @brief PCFG dcdc current hys */ +typedef enum { + pcfg_dcdc_current_hys_12_5mv = 0, + pcfg_dcdc_current_hys_25mv = 1, +} pcfg_dcdc_current_hys_t; + +/* @brief PCFG dcdc mode */ +typedef enum { + pcfg_dcdc_mode_off = 0, + pcfg_dcdc_mode_basic = 1, + pcfg_dcdc_mode_general = 3, + pcfg_dcdc_mode_expert = 7, +} pcfg_dcdc_mode_t; + +/* @brief PCFG pmc domain peripherals */ +typedef enum { + pcfg_pmc_periph_fuse = 0, + pcfg_pmc_periph_ram = 2, + pcfg_pmc_periph_vad = 4, + pcfg_pmc_periph_gpio = 6, + pcfg_pmc_periph_ioc = 8, + pcfg_pmc_periph_timer = 10, + pcfg_pmc_periph_wdog = 12, + pcfg_pmc_periph_uart = 14, + pcfg_pmc_periph_debug = 16, +} pcfg_pmc_periph_t; + +/* @brief PCFG status */ +enum { + status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), +}; + +/* @brief PCFG irc24m config */ +typedef struct { + uint32_t freq_in_hz; + pcfg_irc24m_reference_t reference; + bool return_to_default_on_xtal_loss; + bool free_run; +} pcfg_irc24m_config_t; + + +#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ + ((uint32_t) (mode) << ((module) << 1)) + +#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE0 (PCFG_DEBUG_STOP_CPU0_MASK) +#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE0 (0) +#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE1 (PCFG_DEBUG_STOP_CPU1_MASK) +#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE1 (0) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief bandgap disable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_POWER_SAVE_MASK; +} + +/** + * @brief bandgap enable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_enable_power_save_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP |= PCFG_BANDGAP_POWER_SAVE_MASK; +} + +/** + * @brief bandgap disable power save mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_LOWPOWER_MODE_MASK; +} + +/** + * @brief bandgap enable low power mode + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr) +{ + ptr->BANDGAP |= PCFG_BANDGAP_LOWPOWER_MODE_MASK; +} + +/** + * @brief check if bandgap is trimmed or not + * + * @param[in] ptr base address + * + * @retval true if bandgap is trimmed + */ +static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) +{ + return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief bandgap reload trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief turn off LDO 1V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo1p1_turn_off(PCFG_Type *ptr) +{ + ptr->LDO1P1 &= ~PCFG_LDO1P1_ENABLE_MASK; +} + +/** + * @brief turn of LDO 1V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo1p1_turn_on(PCFG_Type *ptr) +{ + ptr->LDO1P1 |= PCFG_LDO1P1_ENABLE_MASK; +} + +/** + * @brief turn off LDO2P5 + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) +{ + ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief turn on LDO 2.5V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) +{ + ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief check if LDO 2.5V is stable + * + * @param[in] ptr base address + * + * @retval true if LDO2P5 is stable + */ +static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) +{ + return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); +} + +/* + * @brief check if DCDC is stable or not + * @param[in] ptr base address + * @retval true if DCDC is stable + */ +static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) +{ + return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); +} + +/* + * @brief set DCDC work mode + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) +{ + ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); +} + +/** + * @brief set low power current limit + * + * @param[in] ptr base address + * @param[in] limit current limit at low power mode + * @param[in] over_limit set to true means current is greater than limit + */ +static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) +{ + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) + | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(over_limit); +} + +/** + * @brief disable power loss protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief enable power loss protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; +} + +/** + * @brief check if power loss flag is set + * + * @param[in] ptr base address + * + * @retval true if power loss is set + */ +static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); +} + +/** + * @brief disable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief enable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief checkover voltage flag + * + * @param[in] ptr base address + * @retval true if flag is set + */ +static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; +} + +/** + * @brief disable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief enable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief check if measured current is valid + * + * @param[in] ptr base address + * + * @retval true if measured current is valid + */ +static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) +{ + return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; +} + +/** + * @brief get DCDC start time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc start time in cycles + */ +static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); +} + +/** + * @brief get DCDC resume time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc resuem time in cycles + */ +static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); +} + +/** + * @brief set DCDC start time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles start time in cycles + */ +static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); +} + +/** + * @brief set DCDC resuem time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles resume time in cycles + */ +static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); +} + +/** + * @brief set dcdc current hysteres range + * + * @param[in] ptr base address + * @param[in] range current hysteres range + */ +static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) +{ + ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); +} + +/** + * @brief disable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief enable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief check if power trap is triggered + * + * @param[in] ptr base address + * + * @retval true if power trap is triggered + */ +static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) +{ + return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief clear power trap trigger flag + * + * @param[in] ptr base address + */ +static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief disable dcdc retention + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief enable dcdc retention to retain soc sram data + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief clear wakeup cause flag + * + * @param[in] ptr base address + * @param[in] mask mask of flags to be cleared + */ +static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_CAUSE |= mask; +} + +/** + * @brief get wakeup cause + * + * @param[in] ptr base address + * + * @retval mask of wake cause + */ +static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) +{ + return ptr->WAKE_CAUSE; +} + +/** + * @brief enable wakeup source + * + * @param[in] ptr base address + * @param[in] mask wakeup source mask + */ +static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK &= ~mask; +} + +/** + * @brief disable wakeup source + * + * @param[in] ptr base address + * @param[in] mask source to be disabled as wakeup source + */ +static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK |= mask; +} + +/** + * @brief set clock gate mode in vpmc domain + * + * @param[in] ptr base address + * @param[in] mode clock gate mode mask + */ +static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) +{ + ptr->SCG_CTRL = mode; +} + +/** + * @brief Disable CPU0 debug stop notficiation to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_disable_cpu0_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU0_MASK; +} + +/** + * @brief Enable CPU0 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_enable_cpu0_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU0_MASK; +} + +/** + * @brief Disable CPU1 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_disable_cpu1_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU1_MASK; +} + +/** + * @brief Enable CPU1 debug stop notification to peripherals + * + * @param[in] ptr + */ +static inline void pcfg_enable_cpu1_debug_stop_notfication(PCFG_Type *ptr) +{ + ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU1_MASK; +} + +/** + * @brief Configure CPU core debug stop notification to peripherals + * + * @param[in] ptr + * @param[in] mask + */ +static inline void pcfg_config_debug_stop_notification(PCFG_Type *ptr, uint8_t mask) +{ + ptr->DEBUG_STOP = mask; +} + +/** + * @brief check if irc24m is trimmed + * + * @param[in] ptr base address + * + * @retval true if it is trimmed + */ +static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) +{ + return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief reload irc24m trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) +{ + ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief config irc24m track + * + * @param[in] ptr base address + * @param[in] config config data + */ +void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); + +/* + * @brief set DCDC voltage at standby mode + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 2.5V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set DCDC voltage + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 1V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief get current DCDC current level in mA + * + * @param[in] ptr base address + * @retval Current level at mA + */ +uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_PCFG_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h new file mode 100644 index 00000000..1240a9cf --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h @@ -0,0 +1,927 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PCFG_H +#define HPM_PCFG_H + +typedef struct { + __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ + __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ + __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ + __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ + __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ + __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ + __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ + __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ + __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ + __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ + __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ + __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ + __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ + __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ + __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ + __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ + __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ + __RW uint32_t DEBUG_STOP; /* 0x50: Debug stop config */ + __R uint8_t RESERVED2[12]; /* 0x54 - 0x5F: Reserved */ + __RW uint32_t RC24M; /* 0x60: RC 24M config */ + __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ + __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ + __R uint32_t STATUS; /* 0x6C: RC 24M track status */ +} PCFG_Type; + + +/* Bitfield definition for register: BANDGAP */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) +#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) +#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) +#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) + +/* + * LOWPOWER_MODE (RW) + * + * Banggap work in low power mode, banggap function limited + * 0: banggap works in normal mode + * 1: banggap works in low power mode + */ +#define PCFG_BANDGAP_LOWPOWER_MODE_MASK (0x2000000UL) +#define PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25U) +#define PCFG_BANDGAP_LOWPOWER_MODE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) +#define PCFG_BANDGAP_LOWPOWER_MODE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) >> PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) + +/* + * POWER_SAVE (RW) + * + * Banggap work in power save mode, banggap function normally + * 0: banggap works in high performance mode + * 1: banggap works in power saving mode + */ +#define PCFG_BANDGAP_POWER_SAVE_MASK (0x1000000UL) +#define PCFG_BANDGAP_POWER_SAVE_SHIFT (24U) +#define PCFG_BANDGAP_POWER_SAVE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_POWER_SAVE_SHIFT) & PCFG_BANDGAP_POWER_SAVE_MASK) +#define PCFG_BANDGAP_POWER_SAVE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_POWER_SAVE_MASK) >> PCFG_BANDGAP_POWER_SAVE_SHIFT) + +/* + * VBG_1P0_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) +#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) + +/* + * VBG_P65_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) + +/* + * VBG_P50_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) +#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) +#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) + +/* Bitfield definition for register: LDO1P1 */ +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO1P1_ENABLE_MASK (0x10000UL) +#define PCFG_LDO1P1_ENABLE_SHIFT (16U) +#define PCFG_LDO1P1_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_ENABLE_SHIFT) & PCFG_LDO1P1_ENABLE_MASK) +#define PCFG_LDO1P1_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_ENABLE_MASK) >> PCFG_LDO1P1_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. + * 700: 700mV + * 720: 720mV + * . . . + * 1320:1320mV + */ +#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) +#define PCFG_LDO1P1_VOLT_SHIFT (0U) +#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) +#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) + +/* Bitfield definition for register: LDO2P5 */ +/* + * READY (RO) + * + * Ready flag, will set 1ms after enabled or voltage change + * 0: LDO is not ready for use + * 1: LDO is ready + */ +#define PCFG_LDO2P5_READY_MASK (0x10000000UL) +#define PCFG_LDO2P5_READY_SHIFT (28U) +#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) + +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) +#define PCFG_LDO2P5_ENABLE_SHIFT (16U) +#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) +#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. + * 2125: 2125mV + * 2150: 2150mV + * . . . + * 2900:2900mV + */ +#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) +#define PCFG_LDO2P5_VOLT_SHIFT (0U) +#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) +#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_MODE */ +/* + * READY (RO) + * + * Ready flag + * 0: DCDC is applying new change + * 1: DCDC is ready + */ +#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) +#define PCFG_DCDC_MODE_READY_SHIFT (28U) +#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) + +/* + * MODE (RW) + * + * DCDC work mode + * XX0: trun off + * 001: basic mode + * 011: generic mode + * 101: automatic mode + * 111: expert mode + */ +#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) +#define PCFG_DCDC_MODE_MODE_SHIFT (16U) +#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) +#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) + +/* + * VOLT (RW) + * + * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) +#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) +#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_LPMODE */ +/* + * STBY_VOLT (RW) + * + * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) +#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_PROT */ +/* + * ILIMIT_LP (RW) + * + * over current setting for low power mode + * 0:250mA + * 1:200mA + */ +#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) +#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) +#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) +#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) + +/* + * OVERLOAD_LP (RW) + * + * over current in low power mode + * 0: current is below setting + * 1: overcurrent happened in low power mode + */ +#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) +#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) + +/* + * DISABLE_POWER_LOSS (RW) + * + * disable power loss protection + * 0: power loss protection enabled, DCDC shuts down when power loss + * 1: power loss protection disabled, DCDC try working after power voltage drop + */ +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK (0x800000UL) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT (23U) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) +#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) >> PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) + +/* + * POWER_LOSS_FLAG (RO) + * + * power loss + * 0: input power is good + * 1: input power is too low + */ +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) + +/* + * DISABLE_OVERVOLTAGE (RW) + * + * ouput over voltage protection + * 0: protection enabled, DCDC will shut down is output voltage is unexpected high + * 1: protection disabled, DCDC continue to adjust output voltage + */ +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) + +/* + * OVERVOLT_FLAG (RO) + * + * output over voltage flag + * 0: output is normal + * 1: output is unexpected high + */ +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) + +/* + * DISABLE_SHORT (RW) + * + * disable output short circuit protection + * 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected + * 1: short circuit protection disabled + */ +#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) +#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) + +/* + * SHORT_CURRENT (RW) + * + * short circuit current setting + * 0: 2.0A, + * 1: 1.3A + */ +#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) +#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) + +/* + * SHORT_FLAG (RO) + * + * short circuit flag + * 0: current is within limit + * 1: short circuits detected + */ +#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) +#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) +#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) + +/* Bitfield definition for register: DCDC_CURRENT */ +/* + * ESTI_EN (RW) + * + * enable current measure + */ +#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) +#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) + +/* + * VALID (RO) + * + * Current level valid + * 0: data is invalid + * 1: data is valid + */ +#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) +#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) +#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) + +/* + * LEVEL (RO) + * + * DCDC current level, current level is num * 50mA + */ +#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) +#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) +#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) + +/* Bitfield definition for register: DCDC_ADVMODE */ +/* + * EN_RCSCALE (RW) + * + * Enable RC scale + */ +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) + +/* + * DC_C (RW) + * + * Loop C number + */ +#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) +#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) +#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) +#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) + +/* + * DC_R (RW) + * + * Loop R number + */ +#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) +#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) +#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) +#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) + +/* + * EN_FF_DET (RW) + * + * enable feed forward detect + * 0: feed forward detect is disabled + * 1: feed forward detect is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) + +/* + * EN_FF_LOOP (RW) + * + * enable feed forward loop + * 0: feed forward loop is disabled + * 1: feed forward loop is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) + +/* + * EN_AUTOLP (RW) + * + * enable auto enter low power mode + * 0: do not enter low power mode + * 1: enter low power mode if current is detected low + */ +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) + +/* + * EN_DCM_EXIT (RW) + * + * avoid over voltage + * 0: stay in DCM mode when voltage excess + * 1: change to CCM mode when voltage excess + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) + +/* + * EN_SKIP (RW) + * + * enable skip on narrow pulse + * 0: do not skip narrow pulse + * 1: skip narrow pulse + */ +#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) +#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) + +/* + * EN_IDLE (RW) + * + * enable skip when voltage is higher than threshold + * 0: do not skip + * 1: skip if voltage is excess + */ +#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) +#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) + +/* + * EN_DCM (RW) + * + * DCM mode + * 0: CCM mode + * 1: DCM mode + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) + +/* Bitfield definition for register: DCDC_ADVPARAM */ +/* + * MIN_DUT (RW) + * + * minimum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) + +/* + * MAX_DUT (RW) + * + * maximum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) + +/* Bitfield definition for register: DCDC_MISC */ +/* + * EN_HYST (RW) + * + * hysteres enable + */ +#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) +#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) +#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) +#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) + +/* + * HYST_SIGN (RW) + * + * hysteres sign + */ +#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) +#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) +#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) +#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) + +/* + * HYST_THRS (RW) + * + * hysteres threshold + */ +#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) +#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) +#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) +#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) + +/* + * RC_SCALE (RW) + * + * Loop RC scale threshold + */ +#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) +#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) +#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) +#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) + +/* + * DC_FF (RW) + * + * Loop feed forward number + */ +#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) +#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) +#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) +#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) + +/* + * OL_THRE (RW) + * + * overload for threshold for lod power mode + */ +#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) +#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) +#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) +#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) + +/* + * OL_HYST (RW) + * + * current hysteres range + * 0: 12.5mV + * 1: 25mV + */ +#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) +#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) +#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) +#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) + +/* + * DELAY (RW) + * + * enable delay + * 0: delay disabled, + * 1: delay enabled + */ +#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) +#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) +#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) +#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) + +/* + * CLK_SEL (RW) + * + * clock selection + * 0: select DCDC internal oscillator + * 1: select RC24M oscillator + */ +#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) +#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) +#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) +#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) + +/* + * EN_STEP (RW) + * + * enable stepping in voltage change + * 0: stepping disabled, + * 1: steping enabled + */ +#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) +#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) +#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) +#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) + +/* Bitfield definition for register: DCDC_DEBUG */ +/* + * UPDATE_TIME (RW) + * + * DCDC voltage change time in 24M clock cycles, default value is 1mS + */ +#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_START_TIME */ +/* + * START_TIME (RW) + * + * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + */ +#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) +#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) +#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_RESUME_TIME */ +/* + * RESUME_TIME (RW) + * + * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + */ +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) + +/* Bitfield definition for register: POWER_TRAP */ +/* + * TRIGGERED (RW) + * + * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. + * 0: low power trap is not triggered + * 1: low power trap triggered + */ +#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) +#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) +#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) +#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) + +/* + * RETENTION (RW) + * + * DCDC enter standby mode, which will reduce voltage for memory content retention + * 0: Shutdown DCDC + * 1: reduce DCDC voltage + */ +#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) +#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) +#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) +#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) + +/* + * TRAP (RW) + * + * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered + * 0: trap not enabled, pmic side low power function disabled + * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + */ +#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) +#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) +#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) +#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) + +/* Bitfield definition for register: WAKE_CAUSE */ +/* + * CAUSE (RW) + * + * wake up cause, each bit represents one wake up source, write 1 to clear the register bit + * 0: wake up source is not active during last wakeup + * 1: wake up source is active furing last wakeup + * bit 0: pmic_enable + * bit 1: debug wakeup + * bit 4: fuse interrupt + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit11: Security monitor interrupt + * bit12: Security in PMIC event + * bit16: Security violation in BATT + * bit17: GPIO in BATT interrupt + * bit18: BATT Button interrupt + * bit19: RTC alarm interrupt + */ +#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) +#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) +#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: WAKE_MASK */ +/* + * MASK (RW) + * + * mask for wake up sources, each bit represents one wakeup source + * 0: allow source to wake up system + * 1: disallow source to wakeup system + * bit 0: pmic_enable + * bit 1: debug wakeup + * bit 4: fuse interrupt + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit11: Security monitor interrupt + * bit12: Security in PMIC event + * bit16: Security violation in BATT + * bit17: GPIO in BATT interrupt + * bit18: BATT Button interrupt + * bit19: RTC alarm interrupt + */ +#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_MASK_MASK_SHIFT (0U) +#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) +#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) + +/* Bitfield definition for register: SCG_CTRL */ +/* + * SCG (RW) + * + * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral + * 00,01: reserved + * 10: clock is always off + * 11: clock is always on + * bit0-1: fuse + * bit2-3: sram + * bit4-5: vad + * bit6-7:gpio + * bit8-9:ioc + * bit10-11: timer + * bit12-13:wdog + * bit14-15:uart + * bit16-17:debug + */ +#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) +#define PCFG_SCG_CTRL_SCG_SHIFT (0U) +#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) +#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) + +/* Bitfield definition for register: DEBUG_STOP */ +/* + * CPU1 (RW) + * + * Stop peripheral when CPU1 enter debug mode + * 0: peripheral keep running when CPU1 in debug mode + * 1: peripheral enter debug mode when CPU1 enter debug + */ +#define PCFG_DEBUG_STOP_CPU1_MASK (0x2U) +#define PCFG_DEBUG_STOP_CPU1_SHIFT (1U) +#define PCFG_DEBUG_STOP_CPU1_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU1_SHIFT) & PCFG_DEBUG_STOP_CPU1_MASK) +#define PCFG_DEBUG_STOP_CPU1_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU1_MASK) >> PCFG_DEBUG_STOP_CPU1_SHIFT) + +/* + * CPU0 (RW) + * + * Stop peripheral when CPU0 enter debug mode + * 0: peripheral keep running when CPU0 in debug mode + * 1: peripheral enter debug mode when CPU0 enter debug + */ +#define PCFG_DEBUG_STOP_CPU0_MASK (0x1U) +#define PCFG_DEBUG_STOP_CPU0_SHIFT (0U) +#define PCFG_DEBUG_STOP_CPU0_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU0_SHIFT) & PCFG_DEBUG_STOP_CPU0_MASK) +#define PCFG_DEBUG_STOP_CPU0_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU0_MASK) >> PCFG_DEBUG_STOP_CPU0_SHIFT) + +/* Bitfield definition for register: RC24M */ +/* + * RC_TRIMMED (RW) + * + * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: RC is not trimmed + * 1: RC is trimmed + */ +#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) +#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) +#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) +#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) + +/* + * TRIM_C (RW) + * + * Coarse trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_C_MASK (0x700U) +#define PCFG_RC24M_TRIM_C_SHIFT (8U) +#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) +#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) + +/* + * TRIM_F (RW) + * + * Fine trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_F_MASK (0x1FU) +#define PCFG_RC24M_TRIM_F_SHIFT (0U) +#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) +#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) + +/* Bitfield definition for register: RC24M_TRACK */ +/* + * SEL24M (RW) + * + * Select track reference + * 0: select 32K as reference + * 1: select 24M XTAL as reference + */ +#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) +#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) +#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) +#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) + +/* + * RETURN (RW) + * + * Retrun default value when XTAL loss + * 0: remain last tracking value + * 1: switch to default value + */ +#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) +#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) +#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) +#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) + +/* + * TRACK (RW) + * + * track mode + * 0: RC24M free running + * 1: track RC24M to external XTAL + */ +#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) +#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) +#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) +#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) + +/* Bitfield definition for register: TRACK_TARGET */ +/* + * PRE_DIV (RW) + * + * Divider for reference source + */ +#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) +#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) +#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) +#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) + +/* + * TARGET (RW) + * + * Target frequency multiplier of divided source + */ +#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) +#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) +#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) +#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * SEL32K (RO) + * + * track is using XTAL32K + * 0: track is not using XTAL32K + * 1: track is using XTAL32K + */ +#define PCFG_STATUS_SEL32K_MASK (0x100000UL) +#define PCFG_STATUS_SEL32K_SHIFT (20U) +#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) + +/* + * SEL24M (RO) + * + * track is using XTAL24M + * 0: track is not using XTAL24M + * 1: track is using XTAL24M + */ +#define PCFG_STATUS_SEL24M_MASK (0x10000UL) +#define PCFG_STATUS_SEL24M_SHIFT (16U) +#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) + +/* + * EN_TRIM (RO) + * + * default value takes effect + * 0: default value is invalid + * 1: default value is valid + */ +#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) +#define PCFG_STATUS_EN_TRIM_SHIFT (15U) +#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) + +/* + * TRIM_C (RO) + * + * default coarse trim value + */ +#define PCFG_STATUS_TRIM_C_MASK (0x700U) +#define PCFG_STATUS_TRIM_C_SHIFT (8U) +#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) + +/* + * TRIM_F (RO) + * + * default fine trim value + */ +#define PCFG_STATUS_TRIM_F_MASK (0x1FU) +#define PCFG_STATUS_TRIM_F_SHIFT (0U) +#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) + + + + +#endif /* HPM_PCFG_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_pgpr_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_pgpr_regs.h new file mode 100644 index 00000000..36c19e7d --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_pgpr_regs.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PGPR_H +#define HPM_PGPR_H + +typedef struct { + __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ + __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ + __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ + __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ + __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ + __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ + __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ + __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ + __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ + __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ + __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ + __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ + __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ + __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ + __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ + __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ +} PGPR_Type; + + +/* Bitfield definition for register: PMIC_GPR00 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) +#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR01 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) +#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR02 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) +#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR03 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) +#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR04 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) +#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR05 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) +#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR06 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) +#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR07 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) +#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR08 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) +#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR09 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) +#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR10 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) +#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR11 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) +#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR12 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) +#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR13 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) +#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR14 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) +#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR15 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) +#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) + + + + +#endif /* HPM_PGPR_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h index 778cd9d4..92dceabf 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h new file mode 100644 index 00000000..b1eb6e6a --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PPOR_DRV_H +#define HPM_PPOR_DRV_H +#include "hpm_ppor_regs.h" + +typedef enum { + ppor_reset_brownout = 1 << 0, + ppor_reset_temperature = 1 << 1, + ppor_reset_pin = 1 << 2, + ppor_reset_debug = 1 << 4, + ppor_reset_security_violation = 1 << 5, + ppor_reset_jtag = 1 << 6, + ppor_reset_cpu0_lockup = 1 << 8, + ppor_reset_cpu1_lockup = 1 << 9, + ppor_reset_cpu0_request = 1 << 10, + ppor_reset_cpu1_request = 1 << 11, + ppor_reset_wdog0 = 1 << 16, + ppor_reset_wdog1 = 1 << 17, + ppor_reset_wdog2 = 1 << 18, + ppor_reset_wdog3 = 1 << 19, + ppor_reset_pmic_wdog = 1 << 20, + ppor_reset_software = 1 << 31, +} ppor_reset_source_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * perform software reset in counter * (1/24Mhz) seconds + */ +static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) +{ + ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } + +/* + * clear enable reset source according to the given mask + */ +static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE &= ~mask; +} + +/* + * set enable reset source according to the given mask + */ +static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE |= mask; +} + +/* + * set enable reset source + */ +static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) +{ + ptr->RESET_ENABLE = reset_sources; +} + +/* + * get enabled reset source + */ +static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) +{ + return ptr->RESET_ENABLE; +} + +/* + * get reset status + */ +static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) +{ + return ptr->RESET_STATUS; +} + +/* + * get reset flags + */ +static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) +{ + return ptr->RESET_FLAG; +} + +/* + * clear reset flags + */ +static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_FLAG |= mask; +} + +/* + * set cold reset + */ +static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_COLD = mask; +} + +/* + * clear cold reset + */ +static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_COLD &= ~mask; +} + +/* + * set hot reset + */ +static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOT = mask; +} + +/* + * clear hot reset + */ +static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_HOT &= ~mask; +} + +#ifdef __cplusplus +} +#endif +#endif diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_regs.h new file mode 100644 index 00000000..17d55b5a --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_regs.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PPOR_H +#define HPM_PPOR_H + +typedef struct { + __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ + __RW uint32_t RESET_STATUS; /* 0x4: reset source status */ + __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ + __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ + __RW uint32_t RESET_HOT; /* 0x10: reset type triggered by reset */ + __RW uint32_t RESET_COLD; /* 0x14: reset type attribute */ + __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */ + __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ +} PPOR_Type; + + +/* Bitfield definition for register: RESET_FLAG */ +/* + * FLAG (W1C) + * + * reset reason of last hard reset, write 1 to clear each bit + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) +#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) +#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) + +/* Bitfield definition for register: RESET_STATUS */ +/* + * STATUS (RW) + * + * current status of reset sources + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) +#define PPOR_RESET_STATUS_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_STATUS_STATUS_SHIFT) & PPOR_RESET_STATUS_STATUS_MASK) +#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_HOLD */ +/* + * STATUS (RW) + * + * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_HOLD_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOLD_STATUS_SHIFT (0U) +#define PPOR_RESET_HOLD_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_STATUS_SHIFT) & PPOR_RESET_HOLD_STATUS_MASK) +#define PPOR_RESET_HOLD_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_STATUS_MASK) >> PPOR_RESET_HOLD_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_ENABLE */ +/* + * ENABLE (RW) + * + * enable of reset sources + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) +#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) +#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) + +/* Bitfield definition for register: RESET_HOT */ +/* + * TYPE (RW) + * + * reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_HOT_TYPE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOT_TYPE_SHIFT (0U) +#define PPOR_RESET_HOT_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_HOT_TYPE_SHIFT) & PPOR_RESET_HOT_TYPE_MASK) +#define PPOR_RESET_HOT_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_HOT_TYPE_MASK) >> PPOR_RESET_HOT_TYPE_SHIFT) + +/* Bitfield definition for register: RESET_COLD */ +/* + * FLAG (RW) + * + * perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected + * 0: brownout + * 1: temperature(not available) + * 2: resetpin(not available) + * 4: debug reset + * 5: jtag reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2 + * 19: watch dog 3 + * 20: pmic watch dog + * 31: software + */ +#define PPOR_RESET_COLD_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_COLD_FLAG_SHIFT (0U) +#define PPOR_RESET_COLD_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_COLD_FLAG_SHIFT) & PPOR_RESET_COLD_FLAG_MASK) +#define PPOR_RESET_COLD_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_COLD_FLAG_MASK) >> PPOR_RESET_COLD_FLAG_SHIFT) + +/* Bitfield definition for register: SOFTWARE_RESET */ +/* + * COUNTER (RW) + * + * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + */ +#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) +#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) +#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) +#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) + + + + +#endif /* HPM_PPOR_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h index 8530f3f5..60174e42 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_romapi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -52,6 +52,14 @@ typedef union { }; } api_boot_arg_t; +/*EXiP Region Parameter */ +typedef struct { + uint32_t start; /**< Start address, must be 4KB aligned */ + uint32_t len; /**< Must be 4KB aligned */ + uint8_t key[16]; /**< AES Key */ + uint8_t ctr[8]; /**< Initial Vector/Counter */ +} exip_region_param_t; + #define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ #define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ #define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ @@ -65,7 +73,6 @@ typedef struct { uint32_t _internal[138]; } sm3_context_t; - #define SM4_ENCRYPT 1 #define SM4_DECRYPT 0 @@ -130,7 +137,8 @@ typedef struct { void (*update_dllcr)(XPI_Type *base, uint32_t serial_root_clk_freq, uint32_t data_valid_time, xpi_channel_t channel, uint32_t dly_target); /**< XPI driver interface: Get absolute address for APB transfer */ - hpm_stat_t (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); + hpm_stat_t (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, + uint32_t *out_addr); } xpi_driver_interface_t; /** @@ -144,38 +152,48 @@ typedef struct { /**< XPI NOR driver interface: initialize FLASH */ hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); /**< XPI NOR driver interface: Enable write access to FLASH */ - hpm_stat_t (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + hpm_stat_t (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t addr); /**< XPI NOR driver interface: Get FLASH status register */ - hpm_stat_t (*get_status)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr, + hpm_stat_t (*get_status)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t addr, uint16_t *out_status); /**< XPI NOR driver interface: Wait when FLASH is still busy */ - hpm_stat_t (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + hpm_stat_t (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t addr); /**< XPI NOR driver interface: erase a specified FLASH region */ hpm_stat_t (*erase)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t start, uint32_t length); /**< XPI NOR driver interface: Erase the whole FLASH */ hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); /**< XPI NOR driver interface: Erase specified FLASH sector */ - hpm_stat_t (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + hpm_stat_t (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t addr); /**< XPI NOR driver interface: Erase specified FLASH block */ - hpm_stat_t (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + hpm_stat_t (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + uint32_t addr); /**< XPI NOR driver interface: Program data to specified FLASH address */ - hpm_stat_t (*program)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, const uint32_t *src, + hpm_stat_t (*program)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + const uint32_t *src, uint32_t dst_addr, uint32_t length); /**< XPI NOR driver interface: read data from specified FLASH address */ hpm_stat_t (*read)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t *dst, uint32_t start, uint32_t length); /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ - hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, const uint32_t *src, uint32_t dst_addr, uint32_t length); /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ - hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, uint32_t addr); /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ - hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, + hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, uint32_t addr); /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ - hpm_stat_t (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + hpm_stat_t (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config); uint32_t reserved0[3]; @@ -277,7 +295,6 @@ typedef struct { uint8_t *output, const uint8_t *tag, uint32_t tag_len); } sm4_api_interface_t; - /** * @brief Bootloader API table */ @@ -306,7 +323,6 @@ typedef struct { /**< Bootloader API table Root */ #define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) - #ifdef __cplusplus extern "C" { #endif @@ -370,7 +386,8 @@ static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_ * @param[in] length Region size to be erased * @return API execution status */ -static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, +static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, uint32_t start, uint32_t length) { hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); @@ -442,7 +459,6 @@ static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, xpi return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); } - /** * @brief Erase the whole FLASH in blocking way * @param[in] base XPI base address @@ -471,7 +487,6 @@ static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, xpi_ return status; } - /** * @brief Program data to specified FLASH address in blocking way * @param[in] base XPI base address @@ -482,10 +497,12 @@ static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, xpi_ * @param[in] length length of data to be programmed * @return API execution status */ -static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, +static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, const uint32_t *src, uint32_t dst_addr, uint32_t length) { - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); + hpm_stat_t + status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); fencei(); return status; } @@ -518,7 +535,8 @@ static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, xp * @param [in] length length of data to be read out * @return API exection address */ -static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, +static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, uint32_t *dst, uint32_t start, uint32_t length) { return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); @@ -563,11 +581,163 @@ static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, xpi_nor_config */ static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr, - uint16_t *out_status) + uint16_t *out_status) { return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); } +/** + * @brief Configure the XPI Address Remapping Logic + * @param [in] base XPI base address + * @param [in] start Start Address (memory mapped address) + * @param [in] len Size for the remapping region + * @param [in] offset Relative address based on parameter "start" + * @retval true is all parameters are valid + * @retval false if any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) +{ + if (((base != HPM_XPI0) && (base != HPM_XPI1)) || ((start & 0xFFF) != 0) || ((len & 0xFFF) != 0) + || ((offset & 0xFFF) != 0)) { + return false; + } + static const uint8_t k_mc_xpi_remap_config[] = { + 0x2e, 0x96, 0x23, 0x22, 0xc5, 0x42, 0x23, 0x24, + 0xd5, 0x42, 0x93, 0xe5, 0x15, 0x00, 0x23, 0x20, + 0xb5, 0x42, 0x05, 0x45, 0x82, 0x80, + }; + typedef bool (*remap_config_cb_t)(XPI_Type *, uint32_t, uint32_t, uint32_t); + remap_config_cb_t cb = (remap_config_cb_t) &k_mc_xpi_remap_config; + bool result = cb(base, start, len, offset); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return result; +} + +/** + * @brief Disable XPI Remapping logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_remap_disable(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_disable[] = { + 0x83, 0x27, 0x05, 0x42, 0xf9, 0x9b, 0x23, 0x20, + 0xf5, 0x42, 0x82, 0x80, + }; + typedef void (*remap_disable_cb_t)(XPI_Type *); + remap_disable_cb_t cb = (remap_disable_cb_t) &k_mc_xpi_remap_disable; + cb(base); + fencei(); +} + +/** + * @brief Check whether XPI Remapping is enabled + * @param [in] base XPI base address + * + * @retval true Remapping logic is enabled + * @retval false Remapping logic is disabled + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_is_remap_enabled(XPI_Type *base) +{ + static const uint8_t k_mc_xpi_remap_enabled[] = { + 0x03, 0x25, 0x05, 0x42, 0x05, 0x89, 0x82, 0x80, + }; + typedef void (*remap_chk_cb_t)(XPI_Type *); + remap_chk_cb_t chk_cb = (remap_chk_cb_t) &k_mc_xpi_remap_enabled; + return chk_cb(base); +} + +/** + * @brief Configure Specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + * @param [in] param ExiP Region Parameter + * @retval true All parameters are valid + * @retval false Any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) +{ + if ((base != HPM_XPI0) && (base != HPM_XPI1)) { + return false; + } + static const uint8_t k_mc_exip_region_config[] = { + 0x18, 0x4a, 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, + 0xaa, 0x97, 0x23, 0xa4, 0xe7, 0xd0, 0x4c, 0x4a, + 0x14, 0x42, 0x58, 0x42, 0x23, 0xa6, 0xb7, 0xd0, + 0x4c, 0x46, 0x36, 0x97, 0x13, 0x77, 0x07, 0xc0, + 0x23, 0xa2, 0xb7, 0xd0, 0x0c, 0x46, 0x13, 0x67, + 0x37, 0x00, 0x05, 0x45, 0x23, 0xa0, 0xb7, 0xd0, + 0x0c, 0x4e, 0x23, 0xaa, 0xb7, 0xd0, 0x50, 0x4e, + 0x23, 0xa8, 0xc7, 0xd0, 0x23, 0xac, 0xd7, 0xd0, + 0x23, 0xae, 0xe7, 0xd0, 0x82, 0x80, + }; + typedef void (*exip_region_config_cb_t)(XPI_Type *, uint32_t, exip_region_param_t *); + exip_region_config_cb_t cb = (exip_region_config_cb_t) &k_mc_exip_region_config; + cb(base, index, param); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return true; +} + +/** + * @brief Disable EXiP Feature on specified EXiP Region + * @@param [in] base XPI base address + * @param [in] index EXiP Region index + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) +{ + static const uint8_t k_mc_exip_region_disable[] = { + 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, 0xaa, 0x97, + 0x03, 0xa7, 0xc7, 0xd1, 0x75, 0x9b, 0x23, 0xae, + 0xe7, 0xd0, 0x82, 0x80 + }; + typedef void (*exip_region_disable_cb_t)(XPI_Type *, uint32_t); + exip_region_disable_cb_t cb = (exip_region_disable_cb_t) &k_mc_exip_region_disable; + cb(base, index); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} + +/** + * @brief Enable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_enable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_enable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x37, 0x07, 0x00, 0x80, 0xd9, 0x8f, 0x23, 0x20, + 0xf5, 0xc0, 0x82, 0x80 + }; + typedef void (*exip_enable_cb_t)(XPI_Type *); + exip_enable_cb_t cb = (exip_enable_cb_t) &k_mc_exip_enable; + cb(base); +} + +/** + * @brief Disable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_disable(XPI_Type *base) +{ + static const uint8_t k_mc_exip_disable[] = { + 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, + 0x86, 0x07, 0x85, 0x83, 0x23, 0x20, 0xf5, 0xc0, + 0x82, 0x80 + }; + typedef void (*exip_disable_cb_t)(XPI_Type *); + exip_disable_cb_t cb = (exip_disable_cb_t) &k_mc_exip_disable; + cb(base); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); +} /*********************************************************************************************************************** * @@ -812,7 +982,8 @@ static inline void rom_sm4_setkey_dec(sm4_context_t *ctx, const uint8_t key[16]) * @param [out] output Output data * @return API execution status */ -static inline hpm_stat_t rom_sm4_crypt_ecb(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t *input, uint8_t *output) +static inline hpm_stat_t rom_sm4_crypt_ecb(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t *input, + uint8_t *output) { return ROM_API_TABLE_ROOT->sm4_api_if->crypt_ecb(ctx, mode, length, input, output); } @@ -826,13 +997,12 @@ static inline hpm_stat_t rom_sm4_crypt_ecb(sm4_context_t *ctx, uint32_t mode, ui * @param [out] output Output data * @return API execution status */ -static inline hpm_stat_t rom_sm4_crypt_cbc(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t iv[16], const uint8_t *input, uint8_t *output) +static inline hpm_stat_t rom_sm4_crypt_cbc(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t iv[16], + const uint8_t *input, uint8_t *output) { return ROM_API_TABLE_ROOT->sm4_api_if->crypt_cbc(ctx, mode, length, iv, input, output); } - - #ifdef __cplusplus } #endif diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml index ee924227..11deede0 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml @@ -8011,7 +8011,7 @@ - + @@ -19554,7 +19554,6 @@ - @@ -19603,7 +19602,6 @@ - @@ -20086,7 +20084,6 @@ - @@ -20094,6 +20091,7 @@ + @@ -20105,44 +20103,59 @@ + + + + + + + + + + + + + + + @@ -20151,7 +20164,9 @@ + + @@ -20164,6 +20179,7 @@ + @@ -20174,22 +20190,29 @@ + + + + + + + @@ -21219,6 +21242,7 @@ + @@ -21230,44 +21254,59 @@ + + + + + + + + + + + + + + + @@ -21276,7 +21315,9 @@ + + @@ -21289,6 +21330,7 @@ + @@ -21299,22 +21341,29 @@ + + + + + + + @@ -22377,10 +22426,7 @@ - - - @@ -22808,24 +22854,6 @@ - - - - - - - - - - - - - - - - - - @@ -22920,7 +22948,6 @@ - @@ -22931,12 +22958,6 @@ - - - - - - @@ -23087,132 +23108,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -23276,84 +23174,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -23384,20 +23204,6 @@ - - - - - - - - - - - - - - @@ -23414,20 +23220,6 @@ - - - - - - - - - - - - - - @@ -23444,20 +23236,6 @@ - - - - - - - - - - - - - - @@ -23474,30 +23252,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -23580,6 +23334,7 @@ + @@ -23768,46 +23523,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -23885,24 +23600,6 @@ - - - - - - - - - - - - - - - - - - @@ -23997,7 +23694,6 @@ - @@ -24008,12 +23704,6 @@ - - - - - - @@ -24164,132 +23854,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -24353,84 +23920,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -24461,20 +23950,6 @@ - - - - - - - - - - - - - - @@ -24491,20 +23966,6 @@ - - - - - - - - - - - - - - @@ -24521,20 +23982,6 @@ - - - - - - - - - - - - - - @@ -24551,30 +23998,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -24657,6 +24080,7 @@ + @@ -24845,51 +24269,11 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -24932,7 +24316,7 @@ - + @@ -24975,7 +24359,7 @@ - + @@ -25018,7 +24402,7 @@ - + @@ -25104,7 +24488,7 @@ - + @@ -25147,7 +24531,7 @@ - + @@ -25190,7 +24574,7 @@ - + @@ -25233,7 +24617,7 @@ - + @@ -25319,7 +24703,7 @@ - + @@ -25362,7 +24746,7 @@ - + @@ -25405,7 +24789,7 @@ - + @@ -25448,7 +24832,7 @@ - + @@ -25534,7 +24918,7 @@ - + @@ -25577,7 +24961,7 @@ - + @@ -25620,7 +25004,7 @@ - + @@ -25663,7 +25047,7 @@ - + @@ -25749,7 +25133,7 @@ - + @@ -25792,7 +25176,7 @@ - + @@ -25835,7 +25219,7 @@ - + @@ -25878,7 +25262,7 @@ - + @@ -25964,7 +25348,7 @@ - + @@ -26007,7 +25391,7 @@ - + @@ -26050,7 +25434,7 @@ - + @@ -26093,7 +25477,7 @@ - + @@ -26179,7 +25563,7 @@ - + @@ -26222,7 +25606,7 @@ - + @@ -26265,7 +25649,7 @@ - + @@ -26308,7 +25692,7 @@ - + @@ -26394,7 +25778,7 @@ - + @@ -26437,7 +25821,7 @@ - + @@ -26480,7 +25864,7 @@ - + @@ -26523,7 +25907,7 @@ - + @@ -26609,7 +25993,7 @@ - + @@ -26652,7 +26036,7 @@ - + @@ -26695,7 +26079,7 @@ - + @@ -26738,7 +26122,7 @@ - + @@ -26824,7 +26208,7 @@ - + @@ -26867,7 +26251,7 @@ - + @@ -26910,7 +26294,7 @@ - + @@ -26953,7 +26337,7 @@ - + @@ -27039,7 +26423,7 @@ - + @@ -27082,7 +26466,7 @@ - + @@ -27125,7 +26509,7 @@ - + @@ -27168,7 +26552,7 @@ - + @@ -28229,9 +27613,6 @@ - - - @@ -28675,9 +28056,6 @@ - - - @@ -28803,7 +28181,7 @@ - + @@ -28878,7 +28256,7 @@ - + @@ -28953,7 +28331,7 @@ - + @@ -29028,7 +28406,7 @@ - + @@ -29072,7 +28450,6 @@ - diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h index 845c946a..2361bf80 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -853,4 +853,10 @@ #include "hpm_gpiom_regs.h" #include "hpm_sysctl_regs.h" #include "hpm_trgm_regs.h" +#include "hpm_pcfg_regs.h" +#include "hpm_pgpr_regs.h" +#include "hpm_ppor_regs.h" +#include "hpm_bcfg_regs.h" +#include "hpm_bgpr_regs.h" +#include "hpm_bpor_regs.h" #endif /* HPM_SOC_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h index c071cfdf..9c24d8d6 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -31,6 +31,7 @@ */ #define I2S_SOC_MAX_CHANNEL_NUM (16U) #define I2S_SOC_MAX_TX_CHANNEL_NUM (8U) +#define I2S_SOC_MAX_TX_FIFO_DEPTH (8U) #define PDM_I2S HPM_I2S0 #define DAO_I2S HPM_I2S1 #define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U) @@ -105,12 +106,19 @@ * ENET Section */ #define ENET_SOC_RGMII_EN (1U) -#define ENET_SOC_DESC_ADDR_ALIGNMENT (16U) +#define ENET_SOC_DESC_ADDR_ALIGNMENT (32U) #define ENET_SOC_BUFF_ADDR_ALIGNMENT (4U) #define ENET_SOC_ADDR_MAX_COUNT (5U) #define ENET_SOC_ALT_EHD_DES_MIN_LEN (4U) #define ENET_SOC_ALT_EHD_DES_MAX_LEN (8U) #define ENET_SOC_ALT_EHD_DES_LEN (8U) +#define ENET_SOC_PPS_MAX_COUNT (4L) +#define ENET_SOC_PPS1_EN (0U) + +/* + * ACMP Section + */ +#define ACMP_SOC_BANDGAP (1U) /* * ADC Section @@ -129,7 +137,6 @@ #define ADC_SOC_TEMPSENS_REF25_VOL (3300U) #define ADC_SOC_VOUT25C_MAX_SAMPLE_VALUE (65535U) - #define ADC12_SOC_CLOCK_CLK_DIV (2U) #define ADC12_SOC_CALIBRATION_WAITING_LOOP_CNT (10) #define ADC12_SOC_MAX_CH_NUM (17U) @@ -138,7 +145,11 @@ #define ADC16_SOC_PARAMS_LEN (34U) #define ADC16_SOC_MAX_CH_NUM (7U) #define ADC16_SOC_TEMP_CH_NUM (14U) +#define ADC16_SOC_TEMP_CH_EN (1U) #define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) +#define ADC16_SOC_MAX_TRIG_CH_NUM (11U) +#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) + /* * SYSCTL Section */ @@ -154,6 +165,7 @@ * CAN Section */ #define CAN_SOC_MAX_COUNT (4U) +#define CAN_SOC_CANFD_TDC_REQUIRE_STUFF_EXCEPTION_WORKAROUND (1) /* Refer to E00016 in HPM6700/6400 Errata */ /* * UART Section @@ -182,10 +194,22 @@ * OTP Section */ #define OTP_SOC_UUID_IDX (88U) +#define OTP_SOC_UUID_LEN (16U) /* in bytes */ -/* - * OTP Section +/** + * PWM Section + * */ -#define OTP_SOC_UUID_IDX (88U) +#define PWM_SOC_HRPWM_SUPPORT (0U) +#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) +#define PWM_SOC_TIMER_RESET_SUPPORT (0U) + + +/** + * IOC Section + * + */ +#define IOC_SOC_PAD_MAX (491) + #endif /* HPM_SOC_FEATURE_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c b/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c index 0b66953e..203258cd 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c @@ -180,7 +180,7 @@ uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, return frequency; } -static hpm_stat_t _sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) +hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) { if (!sysctl_valid_cpu_index(cpu)) { return status_invalid_argument; @@ -192,12 +192,12 @@ static hpm_stat_t _sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry) { - return _sysctl_set_cpu_entry(ptr, 1, entry); + return sysctl_set_cpu_entry(ptr, 1, entry); } hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) { - return _sysctl_set_cpu_entry(ptr, 0, entry); + return sysctl_set_cpu_entry(ptr, 0, entry); } hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h index 2d02b800..04222745 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h @@ -1438,6 +1438,17 @@ static inline uint32_t sysctl_get_cpu1_flags(SYSCTL_Type *ptr) return sysctl_get_cpu_flags(ptr, 1); } +/** + * @brief Release cpu + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + */ +static inline void sysctl_release_cpu(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->CPU[cpu_index].LP &= ~SYSCTL_CPU_LP_HALT_MASK; +} + /** * @brief Release cpu1 * @@ -1445,7 +1456,20 @@ static inline uint32_t sysctl_get_cpu1_flags(SYSCTL_Type *ptr) */ static inline void sysctl_release_cpu1(SYSCTL_Type *ptr) { - ptr->CPU[1].LP &= ~SYSCTL_CPU_LP_HALT_MASK; + sysctl_release_cpu(ptr, 1); +} + +/** + * @brief Check whether CPU is released or not + * + * @param [in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @retval true CPU is released + * @retval false CPU is on-hold + */ +static inline bool sysctl_is_cpu_released(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + return ((ptr->CPU[cpu_index].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U); } /** @@ -1457,7 +1481,7 @@ static inline void sysctl_release_cpu1(SYSCTL_Type *ptr) */ static inline bool sysctl_is_cpu1_released(SYSCTL_Type *ptr) { - return ((ptr->CPU[1].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U); + return sysctl_is_cpu_released(ptr, 1); } /** @@ -1613,6 +1637,17 @@ hpm_stat_t sysctl_get_cpu1_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); + +/** + * @brief Set entry point on CPU boot or wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu CPU index + * @param[in] entry Entry address for CPU + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry); + /** * @brief Set entry point on CPU0 wakeup * diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h index bd8dcbd4..cd7ccfc0 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h index 3ebe6f7f..7532e4ad 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_trgm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h index 19d0e025..f233eb92 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/HPM6750/soc_modules.list b/common/libraries/hpm_sdk/soc/HPM6750/soc_modules.list index e422ffcc..01bdca78 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/soc_modules.list +++ b/common/libraries/hpm_sdk/soc/HPM6750/soc_modules.list @@ -1,10 +1,10 @@ -# Copyright 2022 hpmicro +# Copyright (c) 2022 HPMicro # SPDX-License-Identifier: BSD-3-Clause # # In this file, all modules available on this part are listed CONFIG_HAS_HPMSDK_UART=y -CONFIG_HAS_HPMSDK_DRAM=y +CONFIG_HAS_HPMSDK_FEMC=y CONFIG_HAS_HPMSDK_SDP=y CONFIG_HAS_HPMSDK_LCDC=y CONFIG_HAS_HPMSDK_I2C=y diff --git a/common/libraries/hpm_sdk/soc/HPM6750/system.c b/common/libraries/hpm_sdk/soc/HPM6750/system.c index ffe18703..2c0c81f6 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/system.c +++ b/common/libraries/hpm_sdk/soc/HPM6750/system.c @@ -10,6 +10,10 @@ #include "hpm_soc.h" #include "hpm_l1c_drv.h" +#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP +#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 +#endif + void enable_plic_feature(void) { uint32_t plic_feature = 0; @@ -17,7 +21,7 @@ void enable_plic_feature(void) /* enabled vector mode and preemptive priority interrupt */ plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; #endif -#ifndef DISABLE_IRQ_PREEMPTIVE +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) /* enabled preemptive priority interrupt */ plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; #endif @@ -30,7 +34,9 @@ __attribute__((weak)) void system_init(void) disable_irq_from_intc(); enable_plic_feature(); enable_irq_from_intc(); +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif #ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld index c5e0ac26..31af99c5 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld @@ -159,11 +159,16 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld index cec748d0..b190ca40 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld @@ -162,11 +162,16 @@ SECTIONS . = ALIGN(8); } > SDRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld index 85eec82a..c3c4455f 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld @@ -180,11 +180,16 @@ SECTIONS . = ALIGN(8); } > SDRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld index cfa7ea64..b43ac5c0 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld @@ -161,11 +161,16 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld index 3882e14d..9e0fea97 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld @@ -180,11 +180,16 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld index 1a5f50de..b03a8f04 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld @@ -154,11 +154,16 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld index 62254ec5..3187083e 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld @@ -152,11 +152,16 @@ SECTIONS . = ALIGN(8); } > AXI_SRAM - .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); KEEP(*(.noncacheable)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S index c55fd37a..44904f7c 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S @@ -46,6 +46,15 @@ _start: */ call c_startup +#if defined(__SES_RISCV) + /* Initialize the heap */ + la a0, __heap_start__ + la a1, __heap_end__ + sub a1, a1, a0 + la t1, __SEGGER_RTL_init_heap + jalr t1 +#endif + /* Do global constructors */ call __libc_init_array diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c index 3eb5b11c..4d7a057a 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c @@ -100,7 +100,7 @@ __attribute__((weak)) void reset_handler(void) * a call to __cxa_atexit() with __dso_handle as one of the arguments. * The dummy versions of these symbols should be provided. */ -void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) +__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) { } diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c index 34e0515f..dac29094 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c @@ -98,7 +98,7 @@ void irq_handler_trap(void) long mcause = read_csr(CSR_MCAUSE); long mepc = read_csr(CSR_MEPC); long mstatus = read_csr(CSR_MSTATUS); -#if SUPPORT_PFT_ARCH +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH long mxstatus = read_csr(CSR_MXSTATUS); #endif #ifdef __riscv_dsp @@ -129,7 +129,7 @@ void irq_handler_trap(void) uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); if (irq_index) { /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ -#ifndef DISABLE_IRQ_PREEMPTIVE +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) enable_global_irq(CSR_MSTATUS_MIE_MASK); #endif ((isr_func_t)__vector_table[irq_index])(); @@ -167,7 +167,7 @@ void irq_handler_trap(void) /* Restore CSR */ write_csr(CSR_MSTATUS, mstatus); write_csr(CSR_MEPC, mepc); -#if SUPPORT_PFT_ARCH +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH write_csr(CSR_MXSTATUS, mxstatus); #endif #ifdef __riscv_dsp diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h index 925cd44a..c1ab5646 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h index 4c8f19b7..0e757792 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -442,8 +442,12 @@ typedef struct { * CLOCK_DIVIDER (RW) * * clock_period, N half clock cycle per half adc cycle - * 0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. - * set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + * 0 for same adc_clk and bus_clk, + * 1 for 1:2, + * 2 for 1:3, + * ... + * 15 for 1:16 + * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk */ #define ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) #define ADC12_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h index 651178df..0d50037c 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -446,8 +446,12 @@ typedef struct { * CLOCK_DIVIDER (RW) * * clock_period, N half clock cycle per half adc cycle - * 0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3. - * set to 3 can genenerate 50MHz adc_clk at 200MHz bus_clk. + * 0 for same adc_clk and bus_clk, + * 1 for 1:2, + * 2 for 1:3, + * ... + * 15 for 1:16 + * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk */ #define ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) #define ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) @@ -843,7 +847,7 @@ typedef struct { * COV_END_CNT (RW) * * used for faster conversion, user can change it to get higher convert speed(but less accuracy). - * should set to (21-convert_clock_number). + * should set to (21-convert_clock_number+1). */ #define ADC16_ADC16_CONFIG1_COV_END_CNT_MASK (0x1F00U) #define ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT (8U) diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_crc_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_crc_regs.h new file mode 100644 index 00000000..8129805a --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_crc_regs.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CRC_H +#define HPM_CRC_H + +typedef struct { + struct { + __RW uint32_t PRE_SET; /* 0x0: pre set for crc setting */ + __RW uint32_t CLR; /* 0x4: chn clear crc result and setting */ + __RW uint32_t POLY; /* 0x8: chn poly */ + __RW uint32_t INIT_DATA; /* 0xC: chn init_data */ + __RW uint32_t XOROUT; /* 0x10: chn xorout */ + __RW uint32_t MISC_SETTING; /* 0x14: chn misc_setting */ + __RW uint32_t DATA; /* 0x18: chn data */ + __RW uint32_t RESULT; /* 0x1C: chn result */ + __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ + } CHN[8]; +} CRC_Type; + + +/* Bitfield definition for register of struct array CHN: PRE_SET */ +/* + * PRE_SET (RW) + * + * 0: no pre set + * 1: CRC32 + * 2: CRC32-AUTOSAR + * 3: CRC16-CCITT + * 4: CRC16-XMODEM + * 5: CRC16-MODBUS + * 1: CRC32 + * 2: CRC32-autosar + * 3: CRC16-ccitt + * 4: CRC16-xmodem + * 5: CRC16-modbus + * 6: crc16_dnp + * 7: crc16_x25 + * 8: crc16_usb + * 9: crc16_maxim + * 10: crc16_ibm + * 11: crc8_maxim + * 12: crc8_rohc + * 13: crc8_itu + * 14: crc8 + * 15: crc5_usb + */ +#define CRC_CHN_PRE_SET_PRE_SET_MASK (0xFFU) +#define CRC_CHN_PRE_SET_PRE_SET_SHIFT (0U) +#define CRC_CHN_PRE_SET_PRE_SET_SET(x) (((uint32_t)(x) << CRC_CHN_PRE_SET_PRE_SET_SHIFT) & CRC_CHN_PRE_SET_PRE_SET_MASK) +#define CRC_CHN_PRE_SET_PRE_SET_GET(x) (((uint32_t)(x) & CRC_CHN_PRE_SET_PRE_SET_MASK) >> CRC_CHN_PRE_SET_PRE_SET_SHIFT) + +/* Bitfield definition for register of struct array CHN: CLR */ +/* + * CLR (RW) + * + * write 1 to clr crc setting and result for its channel. + * always read 0. + */ +#define CRC_CHN_CLR_CLR_MASK (0x1U) +#define CRC_CHN_CLR_CLR_SHIFT (0U) +#define CRC_CHN_CLR_CLR_SET(x) (((uint32_t)(x) << CRC_CHN_CLR_CLR_SHIFT) & CRC_CHN_CLR_CLR_MASK) +#define CRC_CHN_CLR_CLR_GET(x) (((uint32_t)(x) & CRC_CHN_CLR_CLR_MASK) >> CRC_CHN_CLR_CLR_SHIFT) + +/* Bitfield definition for register of struct array CHN: POLY */ +/* + * POLY (RW) + * + * poly setting + */ +#define CRC_CHN_POLY_POLY_MASK (0xFFFFFFFFUL) +#define CRC_CHN_POLY_POLY_SHIFT (0U) +#define CRC_CHN_POLY_POLY_SET(x) (((uint32_t)(x) << CRC_CHN_POLY_POLY_SHIFT) & CRC_CHN_POLY_POLY_MASK) +#define CRC_CHN_POLY_POLY_GET(x) (((uint32_t)(x) & CRC_CHN_POLY_POLY_MASK) >> CRC_CHN_POLY_POLY_SHIFT) + +/* Bitfield definition for register of struct array CHN: INIT_DATA */ +/* + * INIT_DATA (RW) + * + * initial data of CRC + */ +#define CRC_CHN_INIT_DATA_INIT_DATA_MASK (0xFFFFFFFFUL) +#define CRC_CHN_INIT_DATA_INIT_DATA_SHIFT (0U) +#define CRC_CHN_INIT_DATA_INIT_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) +#define CRC_CHN_INIT_DATA_INIT_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) >> CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) + +/* Bitfield definition for register of struct array CHN: XOROUT */ +/* + * XOROUT (RW) + * + * XOR for CRC result + */ +#define CRC_CHN_XOROUT_XOROUT_MASK (0xFFFFFFFFUL) +#define CRC_CHN_XOROUT_XOROUT_SHIFT (0U) +#define CRC_CHN_XOROUT_XOROUT_SET(x) (((uint32_t)(x) << CRC_CHN_XOROUT_XOROUT_SHIFT) & CRC_CHN_XOROUT_XOROUT_MASK) +#define CRC_CHN_XOROUT_XOROUT_GET(x) (((uint32_t)(x) & CRC_CHN_XOROUT_XOROUT_MASK) >> CRC_CHN_XOROUT_XOROUT_SHIFT) + +/* Bitfield definition for register of struct array CHN: MISC_SETTING */ +/* + * BYTE_REV (RW) + * + * 0: no wrap input byte order + * 1: wrap input byte order + */ +#define CRC_CHN_MISC_SETTING_BYTE_REV_MASK (0x1000000UL) +#define CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT (24U) +#define CRC_CHN_MISC_SETTING_BYTE_REV_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) +#define CRC_CHN_MISC_SETTING_BYTE_REV_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) >> CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) + +/* + * REV_OUT (RW) + * + * 0: no wrap output bit order + * 1: wrap output bit order + */ +#define CRC_CHN_MISC_SETTING_REV_OUT_MASK (0x10000UL) +#define CRC_CHN_MISC_SETTING_REV_OUT_SHIFT (16U) +#define CRC_CHN_MISC_SETTING_REV_OUT_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) +#define CRC_CHN_MISC_SETTING_REV_OUT_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) >> CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) + +/* + * REV_IN (RW) + * + * 0: no wrap input bit order + * 1: wrap input bit order + */ +#define CRC_CHN_MISC_SETTING_REV_IN_MASK (0x100U) +#define CRC_CHN_MISC_SETTING_REV_IN_SHIFT (8U) +#define CRC_CHN_MISC_SETTING_REV_IN_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_IN_SHIFT) & CRC_CHN_MISC_SETTING_REV_IN_MASK) +#define CRC_CHN_MISC_SETTING_REV_IN_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_IN_MASK) >> CRC_CHN_MISC_SETTING_REV_IN_SHIFT) + +/* + * POLY_WIDTH (RW) + * + * crc data length + */ +#define CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK (0x3FU) +#define CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT (0U) +#define CRC_CHN_MISC_SETTING_POLY_WIDTH_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) +#define CRC_CHN_MISC_SETTING_POLY_WIDTH_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) >> CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) + +/* Bitfield definition for register of struct array CHN: DATA */ +/* + * DATA (RW) + * + * data for crc + */ +#define CRC_CHN_DATA_DATA_MASK (0xFFFFFFFFUL) +#define CRC_CHN_DATA_DATA_SHIFT (0U) +#define CRC_CHN_DATA_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_DATA_DATA_SHIFT) & CRC_CHN_DATA_DATA_MASK) +#define CRC_CHN_DATA_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_DATA_DATA_MASK) >> CRC_CHN_DATA_DATA_SHIFT) + +/* Bitfield definition for register of struct array CHN: RESULT */ +/* + * RESULT (RW) + * + * crc result + */ +#define CRC_CHN_RESULT_RESULT_MASK (0xFFFFFFFFUL) +#define CRC_CHN_RESULT_RESULT_SHIFT (0U) +#define CRC_CHN_RESULT_RESULT_SET(x) (((uint32_t)(x) << CRC_CHN_RESULT_RESULT_SHIFT) & CRC_CHN_RESULT_RESULT_MASK) +#define CRC_CHN_RESULT_RESULT_GET(x) (((uint32_t)(x) & CRC_CHN_RESULT_RESULT_MASK) >> CRC_CHN_RESULT_RESULT_SHIFT) + + + +/* CHN register group index macro definition */ +#define CRC_CHN_0 (0UL) +#define CRC_CHN_1 (1UL) +#define CRC_CHN_2 (2UL) +#define CRC_CHN_3 (3UL) +#define CRC_CHN_4 (4UL) +#define CRC_CHN_5 (5UL) +#define CRC_CHN_6 (6UL) +#define CRC_CHN_7 (7UL) + + +#endif /* HPM_CRC_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_dma_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_dma_regs.h index 196e9d3c..aeca5263 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_dma_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_dma_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,15 +10,17 @@ #define HPM_DMA_H typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ + __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ + __R uint32_t IDMISC; /* 0x4: ID Misc */ + __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ - __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ + __R uint8_t RESERVED2[12]; /* 0x14 - 0x1F: Reserved */ __W uint32_t DMACTRL; /* 0x20: DMAC Control Register */ __W uint32_t CHABORT; /* 0x24: Channel Abort Register */ - __R uint8_t RESERVED2[8]; /* 0x28 - 0x2F: Reserved */ + __R uint8_t RESERVED3[8]; /* 0x28 - 0x2F: Reserved */ __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */ __R uint32_t CHEN; /* 0x34: Channel Enable Register */ - __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ + __R uint8_t RESERVED4[8]; /* 0x38 - 0x3F: Reserved */ struct { __RW uint32_t CTRL; /* 0x40: Channel n Control Register */ __RW uint32_t TRANSIZE; /* 0x44: Channel n Transfer Size Register */ @@ -32,6 +34,18 @@ typedef struct { } DMA_Type; +/* Bitfield definition for register: IDMISC */ +/* + * IDLE_FLAG (RO) + * + * DMA Idle Flag + * 0 - DMA is busy + * 1 - DMA is dile + */ +#define DMA_IDMISC_IDLE_FLAG_MASK (0x8000U) +#define DMA_IDMISC_IDLE_FLAG_SHIFT (15U) +#define DMA_IDMISC_IDLE_FLAG_GET(x) (((uint32_t)(x) & DMA_IDMISC_IDLE_FLAG_MASK) >> DMA_IDMISC_IDLE_FLAG_SHIFT) + /* Bitfield definition for register: DMACFG */ /* * CHAINXFR (RO) @@ -273,7 +287,8 @@ typedef struct { * 0x8: 256 transfers * 0x9:512 transfers * 0xa: 1024 transfers - * 0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception + * 0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception + * for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 */ #define DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) #define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) @@ -290,7 +305,8 @@ typedef struct { * 0x3: Double word transfer * 0x4: Quad word transfer * 0x5: Eight word transfer - * 0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + * 0x6-x7: Reserved, setting this field with a reserved value triggers the error exception + * for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 */ #define DMA_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) #define DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) @@ -309,7 +325,8 @@ typedef struct { * 0x3: Double word transfer * 0x4: Quad word transfer * 0x5: Eight word transfer - * 0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception + * 0x6-x7: Reserved, setting this field with a reserved value triggers the error exception + * for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 */ #define DMA_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) #define DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_dram_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_dram_regs.h deleted file mode 100644 index 1adf5378..00000000 --- a/common/libraries/hpm_sdk/soc/ip/hpm_dram_regs.h +++ /dev/null @@ -1,834 +0,0 @@ -/* - * Copyright (c) 2021-2022 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DRAM_H -#define HPM_DRAM_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t BMW0; /* 0x8: Bus (AXI) Weight Control Register 0 */ - __RW uint32_t BMW1; /* 0xC: Bus (AXI) Weight Control Register 1 */ - __RW uint32_t BR[2]; /* 0x10 - 0x14: Base Register 0 (for SDRAM CS0 device) */ - __R uint8_t RESERVED1[32]; /* 0x18 - 0x37: Reserved */ - __RW uint32_t INTEN; /* 0x38: Interrupt Enable Register */ - __W uint32_t INTR; /* 0x3C: Interrupt Status Register */ - __RW uint32_t SDRCTRL0; /* 0x40: SDRAM Control Register 0 */ - __RW uint32_t SDRCTRL1; /* 0x44: SDRAM Control Register 1 */ - __RW uint32_t SDRCTRL2; /* 0x48: SDRAM Control Register 2 */ - __RW uint32_t SDRCTRL3; /* 0x4C: SDRAM Control Register 3 */ - __R uint8_t RESERVED2[64]; /* 0x50 - 0x8F: Reserved */ - __RW uint32_t SADDR; /* 0x90: IP Command Control Register 0 */ - __RW uint32_t DATSZ; /* 0x94: IP Command Control Register 1 */ - __RW uint32_t BYTEMSK; /* 0x98: IP Command Control Register 2 */ - __RW uint32_t IPCMD; /* 0x9C: IP Command Register */ - __RW uint32_t IPTX; /* 0xA0: TX DATA Register */ - __R uint8_t RESERVED3[12]; /* 0xA4 - 0xAF: Reserved */ - __RW uint32_t IPRX; /* 0xB0: RX DATA Register */ - __R uint8_t RESERVED4[12]; /* 0xB4 - 0xBF: Reserved */ - __R uint32_t STAT0; /* 0xC0: Status Register 0 */ - __R uint8_t RESERVED5[140]; /* 0xC4 - 0x14F: Reserved */ - __RW uint32_t DLYCFG; /* 0x150: Delay Line Config Register */ -} DRAM_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * BTO (RW) - * - * Bus timeout cycles - * AXI Bus timeout cycle is as following (255*(2^BTO)): - * 00000b - 255*1 - * 00001-11110b - 255*2 - 255*2^30 - * 11111b - 255*2^31 - */ -#define DRAM_CTRL_BTO_MASK (0x1F000000UL) -#define DRAM_CTRL_BTO_SHIFT (24U) -#define DRAM_CTRL_BTO_SET(x) (((uint32_t)(x) << DRAM_CTRL_BTO_SHIFT) & DRAM_CTRL_BTO_MASK) -#define DRAM_CTRL_BTO_GET(x) (((uint32_t)(x) & DRAM_CTRL_BTO_MASK) >> DRAM_CTRL_BTO_SHIFT) - -/* - * CTO (RW) - * - * Command Execution timeout cycles - * When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is - * generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is - * CTO*1024 cycle. - */ -#define DRAM_CTRL_CTO_MASK (0xFF0000UL) -#define DRAM_CTRL_CTO_SHIFT (16U) -#define DRAM_CTRL_CTO_SET(x) (((uint32_t)(x) << DRAM_CTRL_CTO_SHIFT) & DRAM_CTRL_CTO_MASK) -#define DRAM_CTRL_CTO_GET(x) (((uint32_t)(x) & DRAM_CTRL_CTO_MASK) >> DRAM_CTRL_CTO_SHIFT) - -/* - * DQS (RW) - * - * DQS (read strobe) mode - * 0b - Dummy read strobe loopbacked internally - * 1b - Dummy read strobe loopbacked from DQS pad - */ -#define DRAM_CTRL_DQS_MASK (0x4U) -#define DRAM_CTRL_DQS_SHIFT (2U) -#define DRAM_CTRL_DQS_SET(x) (((uint32_t)(x) << DRAM_CTRL_DQS_SHIFT) & DRAM_CTRL_DQS_MASK) -#define DRAM_CTRL_DQS_GET(x) (((uint32_t)(x) & DRAM_CTRL_DQS_MASK) >> DRAM_CTRL_DQS_SHIFT) - -/* - * DIS (RW) - * - * Module Disable - * 0b - Module enabled - * 1b - Module disabled - */ -#define DRAM_CTRL_DIS_MASK (0x2U) -#define DRAM_CTRL_DIS_SHIFT (1U) -#define DRAM_CTRL_DIS_SET(x) (((uint32_t)(x) << DRAM_CTRL_DIS_SHIFT) & DRAM_CTRL_DIS_MASK) -#define DRAM_CTRL_DIS_GET(x) (((uint32_t)(x) & DRAM_CTRL_DIS_MASK) >> DRAM_CTRL_DIS_SHIFT) - -/* - * RST (RW) - * - * Software Reset - * Reset all internal logic in SEMC except configuration register - */ -#define DRAM_CTRL_RST_MASK (0x1U) -#define DRAM_CTRL_RST_SHIFT (0U) -#define DRAM_CTRL_RST_SET(x) (((uint32_t)(x) << DRAM_CTRL_RST_SHIFT) & DRAM_CTRL_RST_MASK) -#define DRAM_CTRL_RST_GET(x) (((uint32_t)(x) & DRAM_CTRL_RST_MASK) >> DRAM_CTRL_RST_SHIFT) - -/* Bitfield definition for register: BMW0 */ -/* - * RWS (RW) - * - * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is - * same as current executing command with read/write operation switch. - */ -#define DRAM_BMW0_RWS_MASK (0xFF0000UL) -#define DRAM_BMW0_RWS_SHIFT (16U) -#define DRAM_BMW0_RWS_SET(x) (((uint32_t)(x) << DRAM_BMW0_RWS_SHIFT) & DRAM_BMW0_RWS_MASK) -#define DRAM_BMW0_RWS_GET(x) (((uint32_t)(x) & DRAM_BMW0_RWS_MASK) >> DRAM_BMW0_RWS_SHIFT) - -/* - * SH (RW) - * - * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is - * same as current executing command without read/write operation switch. - */ -#define DRAM_BMW0_SH_MASK (0xFF00U) -#define DRAM_BMW0_SH_SHIFT (8U) -#define DRAM_BMW0_SH_SET(x) (((uint32_t)(x) << DRAM_BMW0_SH_SHIFT) & DRAM_BMW0_SH_MASK) -#define DRAM_BMW0_SH_GET(x) (((uint32_t)(x) & DRAM_BMW0_SH_MASK) >> DRAM_BMW0_SH_SHIFT) - -/* - * AGE (RW) - * - * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is - * multiplied by WAGE to get weight score. - */ -#define DRAM_BMW0_AGE_MASK (0xF0U) -#define DRAM_BMW0_AGE_SHIFT (4U) -#define DRAM_BMW0_AGE_SET(x) (((uint32_t)(x) << DRAM_BMW0_AGE_SHIFT) & DRAM_BMW0_AGE_MASK) -#define DRAM_BMW0_AGE_GET(x) (((uint32_t)(x) & DRAM_BMW0_AGE_MASK) >> DRAM_BMW0_AGE_SHIFT) - -/* - * QOS (RW) - * - * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator - * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS - * is multiplied by WQOS to get weight score. - */ -#define DRAM_BMW0_QOS_MASK (0xFU) -#define DRAM_BMW0_QOS_SHIFT (0U) -#define DRAM_BMW0_QOS_SET(x) (((uint32_t)(x) << DRAM_BMW0_QOS_SHIFT) & DRAM_BMW0_QOS_MASK) -#define DRAM_BMW0_QOS_GET(x) (((uint32_t)(x) & DRAM_BMW0_QOS_MASK) >> DRAM_BMW0_QOS_SHIFT) - -/* Bitfield definition for register: BMW1 */ -/* - * BR (RW) - * - * Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current - * executing command. - */ -#define DRAM_BMW1_BR_MASK (0xFF000000UL) -#define DRAM_BMW1_BR_SHIFT (24U) -#define DRAM_BMW1_BR_SET(x) (((uint32_t)(x) << DRAM_BMW1_BR_SHIFT) & DRAM_BMW1_BR_MASK) -#define DRAM_BMW1_BR_GET(x) (((uint32_t)(x) & DRAM_BMW1_BR_MASK) >> DRAM_BMW1_BR_SHIFT) - -/* - * RWS (RW) - * - * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is - * same as current executing command with read/write operation switch. - */ -#define DRAM_BMW1_RWS_MASK (0xFF0000UL) -#define DRAM_BMW1_RWS_SHIFT (16U) -#define DRAM_BMW1_RWS_SET(x) (((uint32_t)(x) << DRAM_BMW1_RWS_SHIFT) & DRAM_BMW1_RWS_MASK) -#define DRAM_BMW1_RWS_GET(x) (((uint32_t)(x) & DRAM_BMW1_RWS_MASK) >> DRAM_BMW1_RWS_SHIFT) - -/* - * PH (RW) - * - * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is - * same as current executing command without read/write operation switch. - */ -#define DRAM_BMW1_PH_MASK (0xFF00U) -#define DRAM_BMW1_PH_SHIFT (8U) -#define DRAM_BMW1_PH_SET(x) (((uint32_t)(x) << DRAM_BMW1_PH_SHIFT) & DRAM_BMW1_PH_MASK) -#define DRAM_BMW1_PH_GET(x) (((uint32_t)(x) & DRAM_BMW1_PH_MASK) >> DRAM_BMW1_PH_SHIFT) - -/* - * AGE (RW) - * - * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is - * multiplied by WAGE to get weight score. - */ -#define DRAM_BMW1_AGE_MASK (0xF0U) -#define DRAM_BMW1_AGE_SHIFT (4U) -#define DRAM_BMW1_AGE_SET(x) (((uint32_t)(x) << DRAM_BMW1_AGE_SHIFT) & DRAM_BMW1_AGE_MASK) -#define DRAM_BMW1_AGE_GET(x) (((uint32_t)(x) & DRAM_BMW1_AGE_MASK) >> DRAM_BMW1_AGE_SHIFT) - -/* - * QOS (RW) - * - * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator - * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS - * is multiplied by WQOS to get weight score. - */ -#define DRAM_BMW1_QOS_MASK (0xFU) -#define DRAM_BMW1_QOS_SHIFT (0U) -#define DRAM_BMW1_QOS_SET(x) (((uint32_t)(x) << DRAM_BMW1_QOS_SHIFT) & DRAM_BMW1_QOS_MASK) -#define DRAM_BMW1_QOS_GET(x) (((uint32_t)(x) & DRAM_BMW1_QOS_MASK) >> DRAM_BMW1_QOS_SHIFT) - -/* Bitfield definition for register array: BR */ -/* - * BASE (RW) - * - * Base Address - * This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low - * position 12 bits are all zero. - */ -#define DRAM_BR_BASE_MASK (0xFFFFF000UL) -#define DRAM_BR_BASE_SHIFT (12U) -#define DRAM_BR_BASE_SET(x) (((uint32_t)(x) << DRAM_BR_BASE_SHIFT) & DRAM_BR_BASE_MASK) -#define DRAM_BR_BASE_GET(x) (((uint32_t)(x) & DRAM_BR_BASE_MASK) >> DRAM_BR_BASE_SHIFT) - -/* - * SIZE (RW) - * - * Memory size - * 00000b - 4KB - * 00001b - 8KB - * 00010b - 16KB - * 00011b - 32KB - * 00100b - 64KB - * 00101b - 128KB - * 00110b - 256KB - * 00111b - 512KB - * 01000b - 1MB - * 01001b - 2MB - * 01010b - 4MB - * 01011b - 8MB - * 01100b - 16MB - * 01101b - 32MB - * 01110b - 64MB - * 01111b - 128MB - * 10000b - 256MB - * 10001b - 512MB - * 10010b - 1GB - * 10011b - 2GB - * 10100-11111b - 4GB - */ -#define DRAM_BR_SIZE_MASK (0x3EU) -#define DRAM_BR_SIZE_SHIFT (1U) -#define DRAM_BR_SIZE_SET(x) (((uint32_t)(x) << DRAM_BR_SIZE_SHIFT) & DRAM_BR_SIZE_MASK) -#define DRAM_BR_SIZE_GET(x) (((uint32_t)(x) & DRAM_BR_SIZE_MASK) >> DRAM_BR_SIZE_SHIFT) - -/* - * VLD (RW) - * - * Valid - */ -#define DRAM_BR_VLD_MASK (0x1U) -#define DRAM_BR_VLD_SHIFT (0U) -#define DRAM_BR_VLD_SET(x) (((uint32_t)(x) << DRAM_BR_VLD_SHIFT) & DRAM_BR_VLD_MASK) -#define DRAM_BR_VLD_GET(x) (((uint32_t)(x) & DRAM_BR_VLD_MASK) >> DRAM_BR_VLD_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * AXIBUSERR (RW) - * - * AXI BUS error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define DRAM_INTEN_AXIBUSERR_MASK (0x8U) -#define DRAM_INTEN_AXIBUSERR_SHIFT (3U) -#define DRAM_INTEN_AXIBUSERR_SET(x) (((uint32_t)(x) << DRAM_INTEN_AXIBUSERR_SHIFT) & DRAM_INTEN_AXIBUSERR_MASK) -#define DRAM_INTEN_AXIBUSERR_GET(x) (((uint32_t)(x) & DRAM_INTEN_AXIBUSERR_MASK) >> DRAM_INTEN_AXIBUSERR_SHIFT) - -/* - * AXICMDERR (RW) - * - * AXI command error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define DRAM_INTEN_AXICMDERR_MASK (0x4U) -#define DRAM_INTEN_AXICMDERR_SHIFT (2U) -#define DRAM_INTEN_AXICMDERR_SET(x) (((uint32_t)(x) << DRAM_INTEN_AXICMDERR_SHIFT) & DRAM_INTEN_AXICMDERR_MASK) -#define DRAM_INTEN_AXICMDERR_GET(x) (((uint32_t)(x) & DRAM_INTEN_AXICMDERR_MASK) >> DRAM_INTEN_AXICMDERR_SHIFT) - -/* - * IPCMDERR (RW) - * - * IP command error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define DRAM_INTEN_IPCMDERR_MASK (0x2U) -#define DRAM_INTEN_IPCMDERR_SHIFT (1U) -#define DRAM_INTEN_IPCMDERR_SET(x) (((uint32_t)(x) << DRAM_INTEN_IPCMDERR_SHIFT) & DRAM_INTEN_IPCMDERR_MASK) -#define DRAM_INTEN_IPCMDERR_GET(x) (((uint32_t)(x) & DRAM_INTEN_IPCMDERR_MASK) >> DRAM_INTEN_IPCMDERR_SHIFT) - -/* - * IPCMDDONE (RW) - * - * IP command done interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define DRAM_INTEN_IPCMDDONE_MASK (0x1U) -#define DRAM_INTEN_IPCMDDONE_SHIFT (0U) -#define DRAM_INTEN_IPCMDDONE_SET(x) (((uint32_t)(x) << DRAM_INTEN_IPCMDDONE_SHIFT) & DRAM_INTEN_IPCMDDONE_MASK) -#define DRAM_INTEN_IPCMDDONE_GET(x) (((uint32_t)(x) & DRAM_INTEN_IPCMDDONE_MASK) >> DRAM_INTEN_IPCMDDONE_SHIFT) - -/* Bitfield definition for register: INTR */ -/* - * AXIBUSERR (W1C) - * - * AXI bus error interrupt - * AXI Bus error interrupt is generated in following cases: - * • AXI address is invalid - * • AXI 8-bit or 16-bit WRAP write/read - */ -#define DRAM_INTR_AXIBUSERR_MASK (0x8U) -#define DRAM_INTR_AXIBUSERR_SHIFT (3U) -#define DRAM_INTR_AXIBUSERR_SET(x) (((uint32_t)(x) << DRAM_INTR_AXIBUSERR_SHIFT) & DRAM_INTR_AXIBUSERR_MASK) -#define DRAM_INTR_AXIBUSERR_GET(x) (((uint32_t)(x) & DRAM_INTR_AXIBUSERR_MASK) >> DRAM_INTR_AXIBUSERR_SHIFT) - -/* - * AXICMDERR (W1C) - * - * AXI command error interrupt - * AXI command error interrupt is generated when AXI command execution timeout. - */ -#define DRAM_INTR_AXICMDERR_MASK (0x4U) -#define DRAM_INTR_AXICMDERR_SHIFT (2U) -#define DRAM_INTR_AXICMDERR_SET(x) (((uint32_t)(x) << DRAM_INTR_AXICMDERR_SHIFT) & DRAM_INTR_AXICMDERR_MASK) -#define DRAM_INTR_AXICMDERR_GET(x) (((uint32_t)(x) & DRAM_INTR_AXICMDERR_MASK) >> DRAM_INTR_AXICMDERR_SHIFT) - -/* - * IPCMDERR (W1C) - * - * IP command error done interrupt - * IP command error interrupt is generated in following case: - * • IP Command Address target invalid device space - * • IP Command Code unsupported - * • IP Command triggered when previous command - */ -#define DRAM_INTR_IPCMDERR_MASK (0x2U) -#define DRAM_INTR_IPCMDERR_SHIFT (1U) -#define DRAM_INTR_IPCMDERR_SET(x) (((uint32_t)(x) << DRAM_INTR_IPCMDERR_SHIFT) & DRAM_INTR_IPCMDERR_MASK) -#define DRAM_INTR_IPCMDERR_GET(x) (((uint32_t)(x) & DRAM_INTR_IPCMDERR_MASK) >> DRAM_INTR_IPCMDERR_SHIFT) - -/* - * IPCMDDONE (W1C) - * - * IP command normal done interrupt - */ -#define DRAM_INTR_IPCMDDONE_MASK (0x1U) -#define DRAM_INTR_IPCMDDONE_SHIFT (0U) -#define DRAM_INTR_IPCMDDONE_SET(x) (((uint32_t)(x) << DRAM_INTR_IPCMDDONE_SHIFT) & DRAM_INTR_IPCMDDONE_MASK) -#define DRAM_INTR_IPCMDDONE_GET(x) (((uint32_t)(x) & DRAM_INTR_IPCMDDONE_MASK) >> DRAM_INTR_IPCMDDONE_SHIFT) - -/* Bitfield definition for register: SDRCTRL0 */ -/* - * BANK2 (RW) - * - * 2 Bank selection bit - * 0b - SDRAM device has 4 banks. - * 1b - SDRAM device has 2 banks. - */ -#define DRAM_SDRCTRL0_BANK2_MASK (0x4000U) -#define DRAM_SDRCTRL0_BANK2_SHIFT (14U) -#define DRAM_SDRCTRL0_BANK2_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_BANK2_SHIFT) & DRAM_SDRCTRL0_BANK2_MASK) -#define DRAM_SDRCTRL0_BANK2_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_BANK2_MASK) >> DRAM_SDRCTRL0_BANK2_SHIFT) - -/* - * CAS (RW) - * - * CAS Latency - * 00b - 1 - * 01b - 1 - * 10b - 2 - * 11b - 3 - */ -#define DRAM_SDRCTRL0_CAS_MASK (0xC00U) -#define DRAM_SDRCTRL0_CAS_SHIFT (10U) -#define DRAM_SDRCTRL0_CAS_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_CAS_SHIFT) & DRAM_SDRCTRL0_CAS_MASK) -#define DRAM_SDRCTRL0_CAS_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_CAS_MASK) >> DRAM_SDRCTRL0_CAS_SHIFT) - -/* - * COL (RW) - * - * Column address bit number - * 00b - 12 bit - * 01b - 11 bit - * 10b - 10 bit - * 11b - 9 bit - */ -#define DRAM_SDRCTRL0_COL_MASK (0x300U) -#define DRAM_SDRCTRL0_COL_SHIFT (8U) -#define DRAM_SDRCTRL0_COL_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_COL_SHIFT) & DRAM_SDRCTRL0_COL_MASK) -#define DRAM_SDRCTRL0_COL_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_COL_MASK) >> DRAM_SDRCTRL0_COL_SHIFT) - -/* - * COL8 (RW) - * - * Column 8 selection bit - * 0b - Column address bit number is decided by COL field. - * 1b - Column address bit number is 8. COL field is ignored. - */ -#define DRAM_SDRCTRL0_COL8_MASK (0x80U) -#define DRAM_SDRCTRL0_COL8_SHIFT (7U) -#define DRAM_SDRCTRL0_COL8_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_COL8_SHIFT) & DRAM_SDRCTRL0_COL8_MASK) -#define DRAM_SDRCTRL0_COL8_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_COL8_MASK) >> DRAM_SDRCTRL0_COL8_SHIFT) - -/* - * BURSTLEN (RW) - * - * Burst Length - * 000b - 1 - * 001b - 2 - * 010b - 4 - * 011b - 8 - * 100b - 8 - * 101b - 8 - * 110b - 8 - * 111b - 8 - */ -#define DRAM_SDRCTRL0_BURSTLEN_MASK (0x70U) -#define DRAM_SDRCTRL0_BURSTLEN_SHIFT (4U) -#define DRAM_SDRCTRL0_BURSTLEN_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_BURSTLEN_SHIFT) & DRAM_SDRCTRL0_BURSTLEN_MASK) -#define DRAM_SDRCTRL0_BURSTLEN_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_BURSTLEN_MASK) >> DRAM_SDRCTRL0_BURSTLEN_SHIFT) - -/* - * HIGHBAND (RW) - * - * high band select - * 0: use data[15:0] for 16bit SDRAM; - * 1: use data[31:16] for 16bit SDRAM; - * only used when Port Size is 16bit(PORTSZ=01b) - */ -#define DRAM_SDRCTRL0_HIGHBAND_MASK (0x8U) -#define DRAM_SDRCTRL0_HIGHBAND_SHIFT (3U) -#define DRAM_SDRCTRL0_HIGHBAND_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_HIGHBAND_SHIFT) & DRAM_SDRCTRL0_HIGHBAND_MASK) -#define DRAM_SDRCTRL0_HIGHBAND_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_HIGHBAND_MASK) >> DRAM_SDRCTRL0_HIGHBAND_SHIFT) - -/* - * PORTSZ (RW) - * - * Port Size - * 00b - 8bit - * 01b - 16bit - * 10b - 32bit - */ -#define DRAM_SDRCTRL0_PORTSZ_MASK (0x3U) -#define DRAM_SDRCTRL0_PORTSZ_SHIFT (0U) -#define DRAM_SDRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL0_PORTSZ_SHIFT) & DRAM_SDRCTRL0_PORTSZ_MASK) -#define DRAM_SDRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL0_PORTSZ_MASK) >> DRAM_SDRCTRL0_PORTSZ_SHIFT) - -/* Bitfield definition for register: SDRCTRL1 */ -/* - * ACT2PRE (RW) - * - * ACT to Precharge minimum time - * It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - */ -#define DRAM_SDRCTRL1_ACT2PRE_MASK (0xF00000UL) -#define DRAM_SDRCTRL1_ACT2PRE_SHIFT (20U) -#define DRAM_SDRCTRL1_ACT2PRE_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_ACT2PRE_SHIFT) & DRAM_SDRCTRL1_ACT2PRE_MASK) -#define DRAM_SDRCTRL1_ACT2PRE_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_ACT2PRE_MASK) >> DRAM_SDRCTRL1_ACT2PRE_SHIFT) - -/* - * CKEOFF (RW) - * - * CKE OFF minimum time - * It is promised clock suspend last at leat CKEOFF+1 clock cycles. - */ -#define DRAM_SDRCTRL1_CKEOFF_MASK (0xF0000UL) -#define DRAM_SDRCTRL1_CKEOFF_SHIFT (16U) -#define DRAM_SDRCTRL1_CKEOFF_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_CKEOFF_SHIFT) & DRAM_SDRCTRL1_CKEOFF_MASK) -#define DRAM_SDRCTRL1_CKEOFF_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_CKEOFF_MASK) >> DRAM_SDRCTRL1_CKEOFF_SHIFT) - -/* - * WRC (RW) - * - * Write recovery time - * It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - */ -#define DRAM_SDRCTRL1_WRC_MASK (0xE000U) -#define DRAM_SDRCTRL1_WRC_SHIFT (13U) -#define DRAM_SDRCTRL1_WRC_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_WRC_SHIFT) & DRAM_SDRCTRL1_WRC_MASK) -#define DRAM_SDRCTRL1_WRC_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_WRC_MASK) >> DRAM_SDRCTRL1_WRC_SHIFT) - -/* - * RFRC (RW) - * - * Refresh recovery time - * It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - */ -#define DRAM_SDRCTRL1_RFRC_MASK (0x1F00U) -#define DRAM_SDRCTRL1_RFRC_SHIFT (8U) -#define DRAM_SDRCTRL1_RFRC_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_RFRC_SHIFT) & DRAM_SDRCTRL1_RFRC_MASK) -#define DRAM_SDRCTRL1_RFRC_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_RFRC_MASK) >> DRAM_SDRCTRL1_RFRC_SHIFT) - -/* - * ACT2RW (RW) - * - * ACT to Read/Write wait time - * It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - */ -#define DRAM_SDRCTRL1_ACT2RW_MASK (0xF0U) -#define DRAM_SDRCTRL1_ACT2RW_SHIFT (4U) -#define DRAM_SDRCTRL1_ACT2RW_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_ACT2RW_SHIFT) & DRAM_SDRCTRL1_ACT2RW_MASK) -#define DRAM_SDRCTRL1_ACT2RW_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_ACT2RW_MASK) >> DRAM_SDRCTRL1_ACT2RW_SHIFT) - -/* - * PRE2ACT (RW) - * - * PRECHARGE to ACT/Refresh wait time - * It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - */ -#define DRAM_SDRCTRL1_PRE2ACT_MASK (0xFU) -#define DRAM_SDRCTRL1_PRE2ACT_SHIFT (0U) -#define DRAM_SDRCTRL1_PRE2ACT_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL1_PRE2ACT_SHIFT) & DRAM_SDRCTRL1_PRE2ACT_MASK) -#define DRAM_SDRCTRL1_PRE2ACT_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL1_PRE2ACT_MASK) >> DRAM_SDRCTRL1_PRE2ACT_SHIFT) - -/* Bitfield definition for register: SDRCTRL2 */ -/* - * ITO (RW) - * - * SDRAM Idle timeout - * It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is - * considered idle when there is no AXI Bus transfer and no SDRAM command pending. - * 00000000b - IDLE timeout period is 256*Prescale period. - * 00000001-11111111b - IDLE timeout period is ITO*Prescale period. - */ -#define DRAM_SDRCTRL2_ITO_MASK (0xFF000000UL) -#define DRAM_SDRCTRL2_ITO_SHIFT (24U) -#define DRAM_SDRCTRL2_ITO_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL2_ITO_SHIFT) & DRAM_SDRCTRL2_ITO_MASK) -#define DRAM_SDRCTRL2_ITO_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL2_ITO_MASK) >> DRAM_SDRCTRL2_ITO_SHIFT) - -/* - * ACT2ACT (RW) - * - * ACT to ACT wait time - * It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This - * could help to meet tRRD timing requirement by SDRAM device. - */ -#define DRAM_SDRCTRL2_ACT2ACT_MASK (0xFF0000UL) -#define DRAM_SDRCTRL2_ACT2ACT_SHIFT (16U) -#define DRAM_SDRCTRL2_ACT2ACT_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL2_ACT2ACT_SHIFT) & DRAM_SDRCTRL2_ACT2ACT_MASK) -#define DRAM_SDRCTRL2_ACT2ACT_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL2_ACT2ACT_MASK) >> DRAM_SDRCTRL2_ACT2ACT_SHIFT) - -/* - * REF2REF (RW) - * - * Refresh to Refresh wait time - * It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. - * This could help to meet tRFC timing requirement by SDRAM device. - */ -#define DRAM_SDRCTRL2_REF2REF_MASK (0xFF00U) -#define DRAM_SDRCTRL2_REF2REF_SHIFT (8U) -#define DRAM_SDRCTRL2_REF2REF_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL2_REF2REF_SHIFT) & DRAM_SDRCTRL2_REF2REF_MASK) -#define DRAM_SDRCTRL2_REF2REF_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL2_REF2REF_MASK) >> DRAM_SDRCTRL2_REF2REF_SHIFT) - -/* - * SRRC (RW) - * - * Self Refresh Recovery time - * It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. - */ -#define DRAM_SDRCTRL2_SRRC_MASK (0xFFU) -#define DRAM_SDRCTRL2_SRRC_SHIFT (0U) -#define DRAM_SDRCTRL2_SRRC_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL2_SRRC_SHIFT) & DRAM_SDRCTRL2_SRRC_MASK) -#define DRAM_SDRCTRL2_SRRC_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL2_SRRC_MASK) >> DRAM_SDRCTRL2_SRRC_SHIFT) - -/* Bitfield definition for register: SDRCTRL3 */ -/* - * UT (RW) - * - * Refresh urgent threshold - * Internal refresh request is generated on every Refresh period. Before internal request timer count up to - * urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh - * request is handled in lower priority than any pending AXI command or IP command to SDRAM device. - * When internal request timer count up to this urgent threshold, refresh request is considered as urgent - * refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP - * command to SDRAM device. - * NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as - * urgent refresh request. - * Refresh urgent threshold is as follwoing: - * 00000000b - 256*Prescaler period - * 00000001-11111111b - UT*Prescaler period - */ -#define DRAM_SDRCTRL3_UT_MASK (0xFF000000UL) -#define DRAM_SDRCTRL3_UT_SHIFT (24U) -#define DRAM_SDRCTRL3_UT_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_UT_SHIFT) & DRAM_SDRCTRL3_UT_MASK) -#define DRAM_SDRCTRL3_UT_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_UT_MASK) >> DRAM_SDRCTRL3_UT_SHIFT) - -/* - * RT (RW) - * - * Refresh timer period - * Refresh timer period is as following: - * 00000000b - 256*Prescaler period - * 00000001-11111111b - RT*Prescaler period - */ -#define DRAM_SDRCTRL3_RT_MASK (0xFF0000UL) -#define DRAM_SDRCTRL3_RT_SHIFT (16U) -#define DRAM_SDRCTRL3_RT_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_RT_SHIFT) & DRAM_SDRCTRL3_RT_MASK) -#define DRAM_SDRCTRL3_RT_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_RT_MASK) >> DRAM_SDRCTRL3_RT_SHIFT) - -/* - * PRESCALE (RW) - * - * Prescaler timer period - * Prescaler timer period is as following: - * 00000000b - 256*16 clock cycles - * 00000001-11111111b - PRESCALE*16 clock cycles - */ -#define DRAM_SDRCTRL3_PRESCALE_MASK (0xFF00U) -#define DRAM_SDRCTRL3_PRESCALE_SHIFT (8U) -#define DRAM_SDRCTRL3_PRESCALE_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_PRESCALE_SHIFT) & DRAM_SDRCTRL3_PRESCALE_MASK) -#define DRAM_SDRCTRL3_PRESCALE_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_PRESCALE_MASK) >> DRAM_SDRCTRL3_PRESCALE_SHIFT) - -/* - * REBL (RW) - * - * Refresh burst length - * It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The - * number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. - * 000b - 1 - * 001b - 2 - * 010b - 3 - * 011b - 4 - * 100b - 5 - * 101b - 6 - * 110b - 7 - * 111b - 8 - */ -#define DRAM_SDRCTRL3_REBL_MASK (0xEU) -#define DRAM_SDRCTRL3_REBL_SHIFT (1U) -#define DRAM_SDRCTRL3_REBL_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_REBL_SHIFT) & DRAM_SDRCTRL3_REBL_MASK) -#define DRAM_SDRCTRL3_REBL_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_REBL_MASK) >> DRAM_SDRCTRL3_REBL_SHIFT) - -/* - * REN (RW) - * - * Refresh enable - */ -#define DRAM_SDRCTRL3_REN_MASK (0x1U) -#define DRAM_SDRCTRL3_REN_SHIFT (0U) -#define DRAM_SDRCTRL3_REN_SET(x) (((uint32_t)(x) << DRAM_SDRCTRL3_REN_SHIFT) & DRAM_SDRCTRL3_REN_MASK) -#define DRAM_SDRCTRL3_REN_GET(x) (((uint32_t)(x) & DRAM_SDRCTRL3_REN_MASK) >> DRAM_SDRCTRL3_REN_SHIFT) - -/* Bitfield definition for register: SADDR */ -/* - * SA (RW) - * - * Slave address - */ -#define DRAM_SADDR_SA_MASK (0xFFFFFFFFUL) -#define DRAM_SADDR_SA_SHIFT (0U) -#define DRAM_SADDR_SA_SET(x) (((uint32_t)(x) << DRAM_SADDR_SA_SHIFT) & DRAM_SADDR_SA_MASK) -#define DRAM_SADDR_SA_GET(x) (((uint32_t)(x) & DRAM_SADDR_SA_MASK) >> DRAM_SADDR_SA_SHIFT) - -/* Bitfield definition for register: DATSZ */ -/* - * DATSZ (RW) - * - * Data Size in Byte - * When IP command is not a write/read operation, DATSZ field would be ignored. - * 000b - 4 - * 001b - 1 - * 010b - 2 - * 011b - 3 - * 100b - 4 - * 101b - 4 - * 110b - 4 - * 111b - 4 - */ -#define DRAM_DATSZ_DATSZ_MASK (0x7U) -#define DRAM_DATSZ_DATSZ_SHIFT (0U) -#define DRAM_DATSZ_DATSZ_SET(x) (((uint32_t)(x) << DRAM_DATSZ_DATSZ_SHIFT) & DRAM_DATSZ_DATSZ_MASK) -#define DRAM_DATSZ_DATSZ_GET(x) (((uint32_t)(x) & DRAM_DATSZ_DATSZ_MASK) >> DRAM_DATSZ_DATSZ_SHIFT) - -/* Bitfield definition for register: BYTEMSK */ -/* - * BM3 (RW) - * - * Byte Mask for Byte 3 (IPTXD bit 31:24) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define DRAM_BYTEMSK_BM3_MASK (0x8U) -#define DRAM_BYTEMSK_BM3_SHIFT (3U) -#define DRAM_BYTEMSK_BM3_SET(x) (((uint32_t)(x) << DRAM_BYTEMSK_BM3_SHIFT) & DRAM_BYTEMSK_BM3_MASK) -#define DRAM_BYTEMSK_BM3_GET(x) (((uint32_t)(x) & DRAM_BYTEMSK_BM3_MASK) >> DRAM_BYTEMSK_BM3_SHIFT) - -/* - * BM2 (RW) - * - * Byte Mask for Byte 2 (IPTXD bit 23:16) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define DRAM_BYTEMSK_BM2_MASK (0x4U) -#define DRAM_BYTEMSK_BM2_SHIFT (2U) -#define DRAM_BYTEMSK_BM2_SET(x) (((uint32_t)(x) << DRAM_BYTEMSK_BM2_SHIFT) & DRAM_BYTEMSK_BM2_MASK) -#define DRAM_BYTEMSK_BM2_GET(x) (((uint32_t)(x) & DRAM_BYTEMSK_BM2_MASK) >> DRAM_BYTEMSK_BM2_SHIFT) - -/* - * BM1 (RW) - * - * Byte Mask for Byte 1 (IPTXD bit 15:8) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define DRAM_BYTEMSK_BM1_MASK (0x2U) -#define DRAM_BYTEMSK_BM1_SHIFT (1U) -#define DRAM_BYTEMSK_BM1_SET(x) (((uint32_t)(x) << DRAM_BYTEMSK_BM1_SHIFT) & DRAM_BYTEMSK_BM1_MASK) -#define DRAM_BYTEMSK_BM1_GET(x) (((uint32_t)(x) & DRAM_BYTEMSK_BM1_MASK) >> DRAM_BYTEMSK_BM1_SHIFT) - -/* - * BM0 (RW) - * - * Byte Mask for Byte 0 (IPTXD bit 7:0) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define DRAM_BYTEMSK_BM0_MASK (0x1U) -#define DRAM_BYTEMSK_BM0_SHIFT (0U) -#define DRAM_BYTEMSK_BM0_SET(x) (((uint32_t)(x) << DRAM_BYTEMSK_BM0_SHIFT) & DRAM_BYTEMSK_BM0_MASK) -#define DRAM_BYTEMSK_BM0_GET(x) (((uint32_t)(x) & DRAM_BYTEMSK_BM0_MASK) >> DRAM_BYTEMSK_BM0_SHIFT) - -/* Bitfield definition for register: IPCMD */ -/* - * KEY (WO) - * - * This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory - * device is selected by BRx settings and IPCR0 registers. - */ -#define DRAM_IPCMD_KEY_MASK (0xFFFF0000UL) -#define DRAM_IPCMD_KEY_SHIFT (16U) -#define DRAM_IPCMD_KEY_SET(x) (((uint32_t)(x) << DRAM_IPCMD_KEY_SHIFT) & DRAM_IPCMD_KEY_MASK) -#define DRAM_IPCMD_KEY_GET(x) (((uint32_t)(x) & DRAM_IPCMD_KEY_MASK) >> DRAM_IPCMD_KEY_SHIFT) - -/* - * CMD (RW) - * - * SDRAM Commands: - * • 0x8: READ - * • 0x9: WRITE - * • 0xA: MODESET - * • 0xB: ACTIVE - * • 0xC: AUTO REFRESH - * • 0xD: SELF REFRESH - * • 0xE: PRECHARGE - * • 0xF: PRECHARGE ALL - * • Others: RSVD - * NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - */ -#define DRAM_IPCMD_CMD_MASK (0xFFFFU) -#define DRAM_IPCMD_CMD_SHIFT (0U) -#define DRAM_IPCMD_CMD_SET(x) (((uint32_t)(x) << DRAM_IPCMD_CMD_SHIFT) & DRAM_IPCMD_CMD_MASK) -#define DRAM_IPCMD_CMD_GET(x) (((uint32_t)(x) & DRAM_IPCMD_CMD_MASK) >> DRAM_IPCMD_CMD_SHIFT) - -/* Bitfield definition for register: IPTX */ -/* - * DAT (RW) - * - * Data - */ -#define DRAM_IPTX_DAT_MASK (0xFFFFFFFFUL) -#define DRAM_IPTX_DAT_SHIFT (0U) -#define DRAM_IPTX_DAT_SET(x) (((uint32_t)(x) << DRAM_IPTX_DAT_SHIFT) & DRAM_IPTX_DAT_MASK) -#define DRAM_IPTX_DAT_GET(x) (((uint32_t)(x) & DRAM_IPTX_DAT_MASK) >> DRAM_IPTX_DAT_SHIFT) - -/* Bitfield definition for register: IPRX */ -/* - * DAT (RW) - * - * Data - */ -#define DRAM_IPRX_DAT_MASK (0xFFFFFFFFUL) -#define DRAM_IPRX_DAT_SHIFT (0U) -#define DRAM_IPRX_DAT_SET(x) (((uint32_t)(x) << DRAM_IPRX_DAT_SHIFT) & DRAM_IPRX_DAT_MASK) -#define DRAM_IPRX_DAT_GET(x) (((uint32_t)(x) & DRAM_IPRX_DAT_MASK) >> DRAM_IPRX_DAT_SHIFT) - -/* Bitfield definition for register: STAT0 */ -/* - * IDLE (RO) - * - * Indicating whether it is in IDLE state. - * When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no - * pending device access. - */ -#define DRAM_STAT0_IDLE_MASK (0x1U) -#define DRAM_STAT0_IDLE_SHIFT (0U) -#define DRAM_STAT0_IDLE_GET(x) (((uint32_t)(x) & DRAM_STAT0_IDLE_MASK) >> DRAM_STAT0_IDLE_SHIFT) - -/* Bitfield definition for register: DLYCFG */ -/* - * OE (RW) - * - * delay clock output enable, should be set after setting DLYEN and DLYSEL - */ -#define DRAM_DLYCFG_OE_MASK (0x2000U) -#define DRAM_DLYCFG_OE_SHIFT (13U) -#define DRAM_DLYCFG_OE_SET(x) (((uint32_t)(x) << DRAM_DLYCFG_OE_SHIFT) & DRAM_DLYCFG_OE_MASK) -#define DRAM_DLYCFG_OE_GET(x) (((uint32_t)(x) & DRAM_DLYCFG_OE_MASK) >> DRAM_DLYCFG_OE_SHIFT) - -/* - * DLYSEL (RW) - * - * delay line select, 0 for 1 cell, 31 for all 32 cells - */ -#define DRAM_DLYCFG_DLYSEL_MASK (0x3EU) -#define DRAM_DLYCFG_DLYSEL_SHIFT (1U) -#define DRAM_DLYCFG_DLYSEL_SET(x) (((uint32_t)(x) << DRAM_DLYCFG_DLYSEL_SHIFT) & DRAM_DLYCFG_DLYSEL_MASK) -#define DRAM_DLYCFG_DLYSEL_GET(x) (((uint32_t)(x) & DRAM_DLYCFG_DLYSEL_MASK) >> DRAM_DLYCFG_DLYSEL_SHIFT) - -/* - * DLYEN (RW) - * - * delay line enable - */ -#define DRAM_DLYCFG_DLYEN_MASK (0x1U) -#define DRAM_DLYCFG_DLYEN_SHIFT (0U) -#define DRAM_DLYCFG_DLYEN_SET(x) (((uint32_t)(x) << DRAM_DLYCFG_DLYEN_SHIFT) & DRAM_DLYCFG_DLYEN_MASK) -#define DRAM_DLYCFG_DLYEN_GET(x) (((uint32_t)(x) & DRAM_DLYCFG_DLYEN_MASK) >> DRAM_DLYCFG_DLYEN_SHIFT) - - - -/* BR register group index macro definition */ -#define DRAM_BR_BASE0 (0UL) -#define DRAM_BR_BASE1 (1UL) - - -#endif /* HPM_DRAM_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h index 9ed1b770..0f06227a 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_enet_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -18,8 +18,7 @@ typedef struct { __RW uint32_t GMII_DATA; /* 0x14: GMII Data Register */ __RW uint32_t FLOWCTRL; /* 0x18: Flow Control Register */ __RW uint32_t VLAN_TAG; /* 0x1C: VLAN Tag Register */ - __R uint32_t VERSION; /* 0x20: Version Register */ - __R uint32_t DEBUGGING; /* 0x24: Debug Register */ + __R uint8_t RESERVED0[8]; /* 0x20 - 0x27: Reserved */ __RW uint32_t RWKFRMFILT; /* 0x28: Remote Wake-Up Frame Filter Register */ __RW uint32_t PMT_CSR; /* 0x2C: PMT Control and Status Register */ __RW uint32_t LPI_CSR; /* 0x30: LPI Control and Status Regsiter */ @@ -32,11 +31,10 @@ typedef struct { __RW uint32_t HIGH; /* 0x48: MAC Address High Register */ __RW uint32_t LOW; /* 0x4C: MAC Address Low Register */ } MAC_ADDR[4]; - __R uint8_t RESERVED0[112]; /* 0x68 - 0xD7: Reserved */ + __R uint8_t RESERVED1[112]; /* 0x68 - 0xD7: Reserved */ __RW uint32_t XMII_CSR; /* 0xD8: SGMII/RGMII/SMII Control and Status Register */ __RW uint32_t WDOG_WTO; /* 0xDC: Watchdog Timeout Register */ - __RW uint32_t GPIO; /* 0xE0: General Purpose IO Register */ - __R uint8_t RESERVED1[28]; /* 0xE4 - 0xFF: Reserved */ + __R uint8_t RESERVED2[32]; /* 0xE0 - 0xFF: Reserved */ __RW uint32_t MMC_CNTRL; /* 0x100: MMC Control establishes the operating mode of MMC. */ __RW uint32_t MMC_INTR_RX; /* 0x104: MMC Receive Interrupt maintains the interrupt generated from all of the receive statistic counters. */ @@ -68,152 +66,20 @@ frames. */ __RW uint32_t TX1024TOMAXOCTETS_GB; /* 0x138: Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. */ - __RW uint32_t TXUNICASTFRAMES_GB; /* 0x13C: Number of good and bad unicast frames transmitted. */ - __RW uint32_t TXMULTICASTFRAMES_GB; /* 0x140: Number of good and bad multicast frames transmitted. */ - __RW uint32_t TXBROADCASTFRAMES_GB; /* 0x144: Number of good and bad broadcast frames transmitted. */ - __RW uint32_t TXUNDERFLOWERROR; /* 0x148: Number of frames aborted because of frame underflow error. */ - __RW uint32_t TXSINGLECOL_G; /* 0x14C: Number of successfully transmitted frames after a single collision -in the half-duplex mode. */ - __RW uint32_t TXMULTICOL_G; /* 0x150: Number of successfully transmitted frames after multiple collisions -in the half-duplex mode. */ - __RW uint32_t TXDEFERRED; /* 0x154: Number of successfully transmitted frames after a deferral in the -half-duplex mode. */ - __RW uint32_t TXLATECOL; /* 0x158: Number of frames aborted because of late collision error */ - __RW uint32_t TXEXESSCOL; /* 0x15C: Number of frames aborted because of excessive (16) collision -errors */ - __RW uint32_t TXCARRIERERROR; /* 0x160: Number of frames aborted because of carrier sense error (no -carrier or loss of carrier). */ - __RW uint32_t TXOCTETCOUNT_G; /* 0x164: Number of bytes transmitted, exclusive of preamble, only in good -frames. */ - __RW uint32_t TXFRAMECOUNT_G; /* 0x168: Number of good frames transmitted */ - __RW uint32_t TXEXCESSDEF; /* 0x16C: Number of frames aborted because of excessive deferral error -(deferred for more than two max-sized frame times). */ - __RW uint32_t TXPAUSEFRAMES; /* 0x170: Number of good Pause frames transmitted */ - __RW uint32_t TXVLANFRAMES_G; /* 0x174: Number of good VLAN frames transmitted, exclusive of retried -frames. */ - __RW uint32_t TXOVERSIZE_G; /* 0x178: Number of frames transmitted without errors and with length -greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged -frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC -Configuration Register)). */ - __R uint8_t RESERVED2[4]; /* 0x17C - 0x17F: Reserved */ + __R uint8_t RESERVED3[68]; /* 0x13C - 0x17F: Reserved */ __RW uint32_t RXFRAMECOUNT_GB; /* 0x180: Number of good and bad frames received */ - __RW uint32_t RXOCTETCOUNT_G; /* 0x184: Number of bytes received, exclusive of preamble, only in good -frames. */ - __RW uint32_t RXOCTETCOUNT_GB; /* 0x188: Number of bytes received, exclusive of preamble, in good and bad -frames. */ - __RW uint32_t RXBROADCASTFRAMES_G; /* 0x18C: Number of good broadcast frames received */ - __RW uint32_t RXMULTICASTFRAMES_G; /* 0x190: Number of good multicast frames received */ - __RW uint32_t RXCRCERROR; /* 0x194: Number of frames received with CRC error */ - __RW uint32_t RXALIGNMENTERROR; /* 0x198: Number of frames received with alignment (dribble) error. Valid -only in 10/100 mode */ - __RW uint32_t RXRUNTERROR; /* 0x19C: Number of frames received with runt (<64 bytes and CRC error) -error. */ - __RW uint32_t RXJABBERERROR; /* 0x1A0: Number of giant frames received with length (including CRC) -greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with -CRC error. If Jumbo Frame mode is enabled, then frames of -length greater than 9,018 bytes (9,022 for VLAN tagged) are -considered as giant frames. */ - __RW uint32_t RXUNDERSIZE_G; /* 0x1A4: Number of frames received with length less than 64 bytes, without -any errors. */ - __RW uint32_t RXOVERSIZE_G; /* 0x1A8: Number of frames received without errors, with length greater -than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 -bytes if enabled in Bit 27 of Register 0 (MAC Configuration -Register)) */ - __RW uint32_t RX64OCTETS_GB; /* 0x1AC: Number of good and bad frames received with length 64 bytes, -exclusive of preamble. */ - __RW uint32_t RX65TO127OCTETS_GB; /* 0x1B0: */ - __RW uint32_t RX128TO255OCTETS_GB; /* 0x1B4: */ - __RW uint32_t RX256TO511OCTETS_GB; /* 0x1B8: Number of good and bad frames received with length between -256 and 511 (inclusive) bytes, exclusive of preamble. */ - __RW uint32_t RX512TO1023OCTETS_GB; /* 0x1BC: Number of good and bad frames received with length between -512 and 1023 (inclusive) bytes, exclusive of preamble. */ - __RW uint32_t RX1024TOMAXOCTETS_GB; /* 0x1C0: Number of good and bad frames received with length between -1024 and maxsize (inclusive) bytes, exclusive of preamble. */ - __RW uint32_t RXUNICASTFRAMES_G; /* 0x1C4: Number of received good unicast frames. */ - __RW uint32_t RXLENGTHERROR; /* 0x1C8: Number of frames received with length error (Length type field ≠ -frame size), for all frames with valid length field. */ - __RW uint32_t RXOUTOFRANGETYPE; /* 0x1CC: Number of frames received with length field not equal to the valid -frame size (greater than 1,500 but less than 1,536). */ - __RW uint32_t RXPAUSEFRAMES; /* 0x1D0: Number of good and valid Pause frames received. */ - __RW uint32_t RXFIFOOVERFLOW; /* 0x1D4: Number of missed received frames because of FIFO overflow. -This counter is not present in the GMAC-CORE configuration. */ - __RW uint32_t RXVLANFRAMES_GB; /* 0x1D8: Number of good and bad VLAN frames received. */ - __RW uint32_t RXWATCHDOGERROR; /* 0x1DC: Number of frames received with error because of watchdog -timeout error (frames with a data load larger than 2,048 bytes or -the value programmed in Register 55 (Watchdog Timeout -Register)). */ - __RW uint32_t RXRCVERROR; /* 0x1E0: Number of frames received with Receive error or Frame Extension -error on the GMII or MII interface. */ - __RW uint32_t RXCTRLFRAMES_G; /* 0x1E4: Number of received good control frames */ - __R uint8_t RESERVED3[24]; /* 0x1E8 - 0x1FF: Reserved */ + __R uint8_t RESERVED4[124]; /* 0x184 - 0x1FF: Reserved */ __RW uint32_t MMC_IPC_INTR_MASK_RX; /* 0x200: MMC IPC Receive Checksum Offload Interrupt Mask maintains the mask for the interrupt generated from the receive IPC statistic counters. */ - __R uint8_t RESERVED4[4]; /* 0x204 - 0x207: Reserved */ + __R uint8_t RESERVED5[4]; /* 0x204 - 0x207: Reserved */ __RW uint32_t MMC_IPC_INTR_RX; /* 0x208: MMC Receive Checksum Offload Interrupt maintains the interrupt that the receive IPC statistic counters generate. See Table 4-25 for further detail. */ - __R uint8_t RESERVED5[4]; /* 0x20C - 0x20F: Reserved */ + __R uint8_t RESERVED6[4]; /* 0x20C - 0x20F: Reserved */ __RW uint32_t RXIPV4_GD_FMS; /* 0x210: Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload */ - __RW uint32_t RXIPV4_HDRERR_FRMS; /* 0x214: Number of IPv4 datagrams received with header (checksum, -length, or version mismatch) errors */ - __RW uint32_t RXIPV4_NOPAY_FRMS; /* 0x218: Number of IPv4 datagram frames received that did not have a -TCP, UDP, or ICMP payload processed by the Checksum engine */ - __RW uint32_t RXIPV4_FRAG_FRMS; /* 0x21C: Number of good IPv4 datagrams with fragmentation */ - __RW uint32_t RXIPV4_UDSBL_FRMS; /* 0x220: Number of good IPv4 datagrams received that had a UDP -payload with checksum disabled */ - __RW uint32_t RXIPV6_GD_FRMS; /* 0x224: Number of good IPv6 datagrams received with TCP, UDP, or -ICMP payloads */ - __RW uint32_t RXIPV6_HDRERR_FRMS; /* 0x228: Number of IPv6 datagrams received with header errors (length or -version mismatch) */ - __RW uint32_t RXIPV6_NOPAY_FRMS; /* 0x22C: Number of IPv6 datagram frames received that did not have a -TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with -fragmentation or security extension headers */ - __RW uint32_t RXUDP_GD_FRMS; /* 0x230: Number of good IP datagrams with a good UDP payload. This -counter is not updated when the rxipv4_udsbl_frms counter is -incremented. */ - __RW uint32_t RXUDP_ERR_FRMS; /* 0x234: Number of good IP datagrams whose UDP payload has a -checksum error */ - __RW uint32_t RXTCP_GD_FRMS; /* 0x238: Number of good IP datagrams with a good TCP payload */ - __RW uint32_t RXTCP_ERR_FRMS; /* 0x23C: Number of good IP datagrams whose TCP payload has a -checksum error */ - __RW uint32_t RXICMP_GD_FRMS; /* 0x240: Number of good IP datagrams with a good ICMP payload */ - __RW uint32_t RXICMP_ERR_FRMS; /* 0x244: Number of good IP datagrams whose ICMP payload has a -checksum error */ - __R uint8_t RESERVED6[8]; /* 0x248 - 0x24F: Reserved */ - __RW uint32_t RXIPV4_GD_OCTETS; /* 0x250: Number of bytes received in good IPv4 datagrams encapsulating -TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad -bytes are not included in this counter or in the octet counters listed -below). */ - __RW uint32_t RXIPV4_HDRERR_OCTETS; /* 0x254: Number of bytes received in IPv4 datagrams with header errors -(checksum, length, version mismatch). The value in the Length -field of IPv4 header is used to update this counter. */ - __RW uint32_t RXIPV4_NOPAY_OCTETS; /* 0x258: Number of bytes received in IPv4 datagrams that did not have a -TCP, UDP, or ICMP payload. The value in the IPv4 header’s -Length field is used to update this counter. */ - __RW uint32_t RXIPV4_FRAG_OCTETS; /* 0x25C: Number of bytes received in fragmented IPv4 datagrams. The -value in the IPv4 header’s Length field is used to update this -counter */ - __RW uint32_t RXIPV4_UDSBL_OCTETS; /* 0x260: Number of bytes received in a UDP segment that had the UDP -checksum disabled. This counter does not count IP Header bytes. */ - __RW uint32_t RXIPV6_GD_OCTETS; /* 0x264: Number of bytes received in good IPv6 datagrams encapsulating -TCP, UDP or ICMPv6 data */ - __RW uint32_t RXIPV6_HDRERR_OCTETS; /* 0x268: Number of bytes received in IPv6 datagrams with header errors -(length, version mismatch). The value in the IPv6 header’s Length -field is used to update this counter. */ - __RW uint32_t RXIPV6_NOPAY_OCTETS; /* 0x26C: Number of bytes received in IPv6 datagrams that did not have a -TCP, UDP, or ICMP payload. The value in the IPv6 header’s -Length field is used to update this counter. */ - __RW uint32_t RXUDP_GD_OCTETS; /* 0x270: Number of bytes received in a good UDP segment. This counter -(and the counters below) does not count IP header bytes. */ - __RW uint32_t RXUDP_ERR_OCTETS; /* 0x274: Number of bytes received in a UDP segment that had checksum -errors */ - __RW uint32_t RXTCP_GD_OCTETS; /* 0x278: Number of bytes received in a good TCP segment */ - __RW uint32_t RXTCP_ERR_OCTETS; /* 0x27C: Number of bytes received in a TCP segment with checksum -errors */ - __RW uint32_t RXICMP_GD_OCTETS; /* 0x280: Number of bytes received in a good ICMP segment */ - __R uint8_t RESERVED7[380]; /* 0x284 - 0x3FF: Reserved */ + __R uint8_t RESERVED7[492]; /* 0x214 - 0x3FF: Reserved */ struct { __RW uint32_t L3_L4_CTRL; /* 0x400: Layer 3 and Layer 4 Control Register */ __RW uint32_t L4_ADDR; /* 0x404: Layer 4 Address Register */ @@ -222,14 +88,11 @@ errors */ __RW uint32_t L3_ADDR_1; /* 0x414: Layer 3 Address 1 Register */ __RW uint32_t L3_ADDR_2; /* 0x418: Layer 3 Address 2 Register */ __RW uint32_t L3_ADDR_3; /* 0x41C: Layer 3 Address 3 Register */ - __R uint8_t RESERVED1[16]; /* 0x420 - 0x42F: Reserved */ - } L3_L4_CFG[4]; - __R uint8_t RESERVED8[64]; /* 0x4C0 - 0x4FF: Reserved */ - __RW uint32_t HASH_TABLE[8]; /* 0x500 - 0x51C: Hash Table Register 0 */ - __R uint8_t RESERVED9[100]; /* 0x520 - 0x583: Reserved */ + } L3_L4_CFG[1]; + __R uint8_t RESERVED8[356]; /* 0x420 - 0x583: Reserved */ __RW uint32_t VLAN_TAG_INC_RPL; /* 0x584: VLAN Tag Inclusion or Replacement Register */ __RW uint32_t VLAN_HASH; /* 0x588: VLAN Hash Table Register */ - __R uint8_t RESERVED10[372]; /* 0x58C - 0x6FF: Reserved */ + __R uint8_t RESERVED9[372]; /* 0x58C - 0x6FF: Reserved */ __RW uint32_t TS_CTRL; /* 0x700: Timestamp Control Register */ __RW uint32_t SUB_SEC_INCR; /* 0x704: Sub-Second Increment Register */ __R uint32_t SYST_SEC; /* 0x708: System Time - Seconds Register */ @@ -244,10 +107,10 @@ errors */ __RW uint32_t PPS_CTRL; /* 0x72C: PPS Control Register */ __R uint32_t AUX_TS_NSEC; /* 0x730: Auxiliary Timestamp - Nanoseconds Register */ __R uint32_t AUX_TS_SEC; /* 0x734: Auxiliary Timestamp - Seconds Register */ - __R uint8_t RESERVED11[40]; /* 0x738 - 0x75F: Reserved */ + __R uint8_t RESERVED10[40]; /* 0x738 - 0x75F: Reserved */ __RW uint32_t PPS0_INTERVAL; /* 0x760: PPS0 Interval Register */ __RW uint32_t PPS0_WIDTH; /* 0x764: PPS0 Width Register */ - __R uint8_t RESERVED12[24]; /* 0x768 - 0x77F: Reserved */ + __R uint8_t RESERVED11[24]; /* 0x768 - 0x77F: Reserved */ struct { __RW uint32_t TGTTM_SEC; /* 0x780: PPS Target Time Seconds Register */ __RW uint32_t TGTTM_NSEC; /* 0x784: PPS Target Time Nanoseconds Register */ @@ -255,7 +118,7 @@ errors */ __RW uint32_t WIDTH; /* 0x78C: PPS Width Register */ __R uint8_t RESERVED0[16]; /* 0x790 - 0x79F: Reserved */ } PPS[3]; - __R uint8_t RESERVED13[2080]; /* 0x7E0 - 0xFFF: Reserved */ + __R uint8_t RESERVED12[2080]; /* 0x7E0 - 0xFFF: Reserved */ __RW uint32_t DMA_BUS_MODE; /* 0x1000: Bus Mode Register */ __RW uint32_t DMA_TX_POLL_DEMAND; /* 0x1004: Transmit Poll Demand Register */ __RW uint32_t DMA_RX_POLL_DEMAND; /* 0x1008: Receive Poll Demand Register */ @@ -268,17 +131,16 @@ errors */ __RW uint32_t DMA_RX_INTR_WDOG; /* 0x1024: Receive Interrupt Watchdog Timer Register */ __RW uint32_t DMA_AXI_MODE; /* 0x1028: AXI Bus Mode Register */ __RW uint32_t DMA_BUS_STATUS; /* 0x102C: AHB or AXI Status Register */ - __R uint8_t RESERVED14[24]; /* 0x1030 - 0x1047: Reserved */ + __R uint8_t RESERVED13[24]; /* 0x1030 - 0x1047: Reserved */ __RW uint32_t DMA_CURR_HOST_TX_DESC; /* 0x1048: Current Host Transmit Descriptor Register */ __RW uint32_t DMA_CURR_HOST_RX_DESC; /* 0x104C: Current Host Receive Descriptor Register */ __RW uint32_t DMA_CURR_HOST_TX_BUF; /* 0x1050: Current Host Transmit Buffer Address Register */ __RW uint32_t DMA_CURR_HOST_RX_BUF; /* 0x1054: Current Host Receive Buffer Address Register */ - __RW uint32_t DMA_HW_FEATURE; /* 0x1058: HW Feature Register */ - __R uint8_t RESERVED15[8100]; /* 0x105C - 0x2FFF: Reserved */ + __R uint8_t RESERVED14[8104]; /* 0x1058 - 0x2FFF: Reserved */ __RW uint32_t CTRL0; /* 0x3000: Control Register 0 */ - __R uint8_t RESERVED16[4]; /* 0x3004 - 0x3007: Reserved */ + __R uint8_t RESERVED15[4]; /* 0x3004 - 0x3007: Reserved */ __RW uint32_t CTRL2; /* 0x3008: Control Register 1 */ - __R uint8_t RESERVED17[28]; /* 0x300C - 0x3027: Reserved */ + __R uint8_t RESERVED16[28]; /* 0x300C - 0x3027: Reserved */ } ENET_Type; @@ -982,162 +844,6 @@ errors */ #define ENET_VLAN_TAG_VL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VL_SHIFT) & ENET_VLAN_TAG_VL_MASK) #define ENET_VLAN_TAG_VL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VL_MASK) >> ENET_VLAN_TAG_VL_SHIFT) -/* Bitfield definition for register: VERSION */ -/* - * USERVER (RO) - * - * User-defined Version - */ -#define ENET_VERSION_USERVER_MASK (0xFF00U) -#define ENET_VERSION_USERVER_SHIFT (8U) -#define ENET_VERSION_USERVER_GET(x) (((uint32_t)(x) & ENET_VERSION_USERVER_MASK) >> ENET_VERSION_USERVER_SHIFT) - -/* - * SNPSVER (RO) - * - * Synopsys-defined Version (3.7) - */ -#define ENET_VERSION_SNPSVER_MASK (0xFFU) -#define ENET_VERSION_SNPSVER_SHIFT (0U) -#define ENET_VERSION_SNPSVER_GET(x) (((uint32_t)(x) & ENET_VERSION_SNPSVER_MASK) >> ENET_VERSION_SNPSVER_SHIFT) - -/* Bitfield definition for register: DEBUGGING */ -/* - * TXSTSFSTS (RO) - * - * MTL TxStatus FIFO Full Status - * When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot accept any more frames for transmission. This bit is reserved in the GMAC-AHB and GMAC-DMA configurations. - */ -#define ENET_DEBUGGING_TXSTSFSTS_MASK (0x2000000UL) -#define ENET_DEBUGGING_TXSTSFSTS_SHIFT (25U) -#define ENET_DEBUGGING_TXSTSFSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TXSTSFSTS_MASK) >> ENET_DEBUGGING_TXSTSFSTS_SHIFT) - -/* - * TXFSTS (RO) - * - * MTL Tx FIFO Not Empty Status - * When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission. - */ -#define ENET_DEBUGGING_TXFSTS_MASK (0x1000000UL) -#define ENET_DEBUGGING_TXFSTS_SHIFT (24U) -#define ENET_DEBUGGING_TXFSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TXFSTS_MASK) >> ENET_DEBUGGING_TXFSTS_SHIFT) - -/* - * TWCSTS (RO) - * - * MTL Tx FIFO Write Controller Status - * When high, this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO. - */ -#define ENET_DEBUGGING_TWCSTS_MASK (0x400000UL) -#define ENET_DEBUGGING_TWCSTS_SHIFT (22U) -#define ENET_DEBUGGING_TWCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TWCSTS_MASK) >> ENET_DEBUGGING_TWCSTS_SHIFT) - -/* - * TRCSTS (RO) - * - * MTL Tx FIFO Read Controller Status - * This field indicates the state of the Tx FIFO Read Controller: - * - 00: IDLE state - * - 01: READ state (transferring data to the MAC transmitter) - * - 10: Waiting for TxStatus from the MAC transmitter - * - 11: Writing the received TxStatus or flushing the Tx FIFO - */ -#define ENET_DEBUGGING_TRCSTS_MASK (0x300000UL) -#define ENET_DEBUGGING_TRCSTS_SHIFT (20U) -#define ENET_DEBUGGING_TRCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TRCSTS_MASK) >> ENET_DEBUGGING_TRCSTS_SHIFT) - -/* - * TXPAUSED (RO) - * - * MAC Transmitter in Pause - * When high, this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-only mode) and hence does not schedule any frame for transmission. - */ -#define ENET_DEBUGGING_TXPAUSED_MASK (0x80000UL) -#define ENET_DEBUGGING_TXPAUSED_SHIFT (19U) -#define ENET_DEBUGGING_TXPAUSED_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TXPAUSED_MASK) >> ENET_DEBUGGING_TXPAUSED_SHIFT) - -/* - * TFCSTS (RO) - * - * MAC Transmit Frame Controller Status - * This field indicates the state of the MAC Transmit Frame Controller module: - * - 00: IDLE state - * - 01: Waiting for status of previous frame or IFG or backoff period to be over - * - 10: Generating and transmitting a Pause frame (in the full-duplex mode) - * - 11: Transferring input frame for transmission - */ -#define ENET_DEBUGGING_TFCSTS_MASK (0x60000UL) -#define ENET_DEBUGGING_TFCSTS_SHIFT (17U) -#define ENET_DEBUGGING_TFCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TFCSTS_MASK) >> ENET_DEBUGGING_TFCSTS_SHIFT) - -/* - * TPESTS (RO) - * - * MAC GMII or MII Transmit Protocol Engine Status - * When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state. - */ -#define ENET_DEBUGGING_TPESTS_MASK (0x10000UL) -#define ENET_DEBUGGING_TPESTS_SHIFT (16U) -#define ENET_DEBUGGING_TPESTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_TPESTS_MASK) >> ENET_DEBUGGING_TPESTS_SHIFT) - -/* - * RXFSTS (RO) - * - * MTL RxFIFO Fill-Level Status - * This field gives the status of the fill-level of the Rx FIFO: - * - 00: Rx FIFO Empty - * - 01: Rx FIFO fill-level below flow-control deactivate threshold - * - 10: Rx FIFO fill-level above flow-control activate threshold - * - 11: Rx FIFO Full - */ -#define ENET_DEBUGGING_RXFSTS_MASK (0x300U) -#define ENET_DEBUGGING_RXFSTS_SHIFT (8U) -#define ENET_DEBUGGING_RXFSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RXFSTS_MASK) >> ENET_DEBUGGING_RXFSTS_SHIFT) - -/* - * RRCSTS (RO) - * - * MTL RxFIFO Read Controller State - * This field gives the state of the Rx FIFO read Controller: - * - 00: IDLE state - * - 01: Reading frame data - * - 10: Reading frame status (or timestamp) - * - 11: Flushing the frame data and status - */ -#define ENET_DEBUGGING_RRCSTS_MASK (0x60U) -#define ENET_DEBUGGING_RRCSTS_SHIFT (5U) -#define ENET_DEBUGGING_RRCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RRCSTS_MASK) >> ENET_DEBUGGING_RRCSTS_SHIFT) - -/* - * RWCSTS (RO) - * - * MTL Rx FIFO Write Controller Active Status - * When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. - */ -#define ENET_DEBUGGING_RWCSTS_MASK (0x10U) -#define ENET_DEBUGGING_RWCSTS_SHIFT (4U) -#define ENET_DEBUGGING_RWCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RWCSTS_MASK) >> ENET_DEBUGGING_RWCSTS_SHIFT) - -/* - * RFCFCSTS (RO) - * - * MAC Receive Frame FIFO Controller Status - * When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module. - RFCFCSTS[1] represents the status of small FIFO Read controller. - RFCFCSTS[0] represents the status of small FIFO Write controller. - */ -#define ENET_DEBUGGING_RFCFCSTS_MASK (0x6U) -#define ENET_DEBUGGING_RFCFCSTS_SHIFT (1U) -#define ENET_DEBUGGING_RFCFCSTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RFCFCSTS_MASK) >> ENET_DEBUGGING_RFCFCSTS_SHIFT) - -/* - * RPESTS (RO) - * - * MAC GMII or MII Receive Protocol Engine Status - * When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state. - */ -#define ENET_DEBUGGING_RPESTS_MASK (0x1U) -#define ENET_DEBUGGING_RPESTS_SHIFT (0U) -#define ENET_DEBUGGING_RPESTS_GET(x) (((uint32_t)(x) & ENET_DEBUGGING_RPESTS_MASK) >> ENET_DEBUGGING_RPESTS_SHIFT) - /* Bitfield definition for register: RWKFRMFILT */ /* * WKUPFRMFILT (RW) @@ -1555,7 +1261,7 @@ errors */ * AE (RO) * * Address Enable - * This bit is always set to 1. + * This bit is RO. The bit value is fixed at 1. */ #define ENET_MAC_ADDR_0_HIGH_AE_MASK (0x80000000UL) #define ENET_MAC_ADDR_0_HIGH_AE_SHIFT (31U) @@ -1642,15 +1348,6 @@ errors */ #define ENET_MAC_ADDR_LOW_ADDRLO_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_LOW_ADDRLO_MASK) >> ENET_MAC_ADDR_LOW_ADDRLO_SHIFT) /* Bitfield definition for register: XMII_CSR */ -/* - * SMIDRXS (RO) - * - * Delay SMII RX Data Sampling with respect to the SMII SYNC Signal When set, the first bit of the SMII RX data is sampled one cycle after the SMII SYNC signal. When reset, the first bit of the SMII RX data is sampled along with the SMII SYNC signal. If the SMII PHY Interface with source synchronous mode is selected during core configuration, this bit is reserved (RO with default value). - */ -#define ENET_XMII_CSR_SMIDRXS_MASK (0x10000UL) -#define ENET_XMII_CSR_SMIDRXS_SHIFT (16U) -#define ENET_XMII_CSR_SMIDRXS_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_SMIDRXS_MASK) >> ENET_XMII_CSR_SMIDRXS_SHIFT) - /* * FALSCARDET (RW) * @@ -1734,43 +1431,6 @@ errors */ #define ENET_WDOG_WTO_WTO_SET(x) (((uint32_t)(x) << ENET_WDOG_WTO_WTO_SHIFT) & ENET_WDOG_WTO_WTO_MASK) #define ENET_WDOG_WTO_WTO_GET(x) (((uint32_t)(x) & ENET_WDOG_WTO_WTO_MASK) >> ENET_WDOG_WTO_WTO_SHIFT) -/* Bitfield definition for register: GPIO */ -/* - * GPIT (RW) - * - */ -#define ENET_GPIO_GPIT_MASK (0xF000000UL) -#define ENET_GPIO_GPIT_SHIFT (24U) -#define ENET_GPIO_GPIT_SET(x) (((uint32_t)(x) << ENET_GPIO_GPIT_SHIFT) & ENET_GPIO_GPIT_MASK) -#define ENET_GPIO_GPIT_GET(x) (((uint32_t)(x) & ENET_GPIO_GPIT_MASK) >> ENET_GPIO_GPIT_SHIFT) - -/* - * GPIE (RW) - * - */ -#define ENET_GPIO_GPIE_MASK (0xF0000UL) -#define ENET_GPIO_GPIE_SHIFT (16U) -#define ENET_GPIO_GPIE_SET(x) (((uint32_t)(x) << ENET_GPIO_GPIE_SHIFT) & ENET_GPIO_GPIE_MASK) -#define ENET_GPIO_GPIE_GET(x) (((uint32_t)(x) & ENET_GPIO_GPIE_MASK) >> ENET_GPIO_GPIE_SHIFT) - -/* - * GPO (RW) - * - */ -#define ENET_GPIO_GPO_MASK (0xF00U) -#define ENET_GPIO_GPO_SHIFT (8U) -#define ENET_GPIO_GPO_SET(x) (((uint32_t)(x) << ENET_GPIO_GPO_SHIFT) & ENET_GPIO_GPO_MASK) -#define ENET_GPIO_GPO_GET(x) (((uint32_t)(x) & ENET_GPIO_GPO_MASK) >> ENET_GPIO_GPO_SHIFT) - -/* - * GPIS (RW) - * - */ -#define ENET_GPIO_GPIS_MASK (0xFU) -#define ENET_GPIO_GPIS_SHIFT (0U) -#define ENET_GPIO_GPIS_SET(x) (((uint32_t)(x) << ENET_GPIO_GPIS_SHIFT) & ENET_GPIO_GPIS_MASK) -#define ENET_GPIO_GPIS_GET(x) (((uint32_t)(x) & ENET_GPIO_GPIS_MASK) >> ENET_GPIO_GPIS_SHIFT) - /* Bitfield definition for register: MMC_CNTRL */ /* * UCDBC (RW) @@ -3095,472 +2755,21 @@ errors */ * * Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. */ -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) >> ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXUNICASTFRAMES_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad unicast frames transmitted. - */ -#define ENET_TXUNICASTFRAMES_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXUNICASTFRAMES_GB_FRMCNT_SHIFT (0U) -#define ENET_TXUNICASTFRAMES_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXUNICASTFRAMES_GB_FRMCNT_SHIFT) & ENET_TXUNICASTFRAMES_GB_FRMCNT_MASK) -#define ENET_TXUNICASTFRAMES_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXUNICASTFRAMES_GB_FRMCNT_MASK) >> ENET_TXUNICASTFRAMES_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXMULTICASTFRAMES_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad multicast frames transmitted. - */ -#define ENET_TXMULTICASTFRAMES_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXMULTICASTFRAMES_GB_FRMCNT_SHIFT (0U) -#define ENET_TXMULTICASTFRAMES_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXMULTICASTFRAMES_GB_FRMCNT_SHIFT) & ENET_TXMULTICASTFRAMES_GB_FRMCNT_MASK) -#define ENET_TXMULTICASTFRAMES_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXMULTICASTFRAMES_GB_FRMCNT_MASK) >> ENET_TXMULTICASTFRAMES_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXBROADCASTFRAMES_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad broadcast frames transmitted. - */ -#define ENET_TXBROADCASTFRAMES_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXBROADCASTFRAMES_GB_FRMCNT_SHIFT (0U) -#define ENET_TXBROADCASTFRAMES_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXBROADCASTFRAMES_GB_FRMCNT_SHIFT) & ENET_TXBROADCASTFRAMES_GB_FRMCNT_MASK) -#define ENET_TXBROADCASTFRAMES_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXBROADCASTFRAMES_GB_FRMCNT_MASK) >> ENET_TXBROADCASTFRAMES_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXUNDERFLOWERROR */ -/* - * FRMCNT (RW) - * - * Number of frames aborted because of frame underflow error. - */ -#define ENET_TXUNDERFLOWERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXUNDERFLOWERROR_FRMCNT_SHIFT (0U) -#define ENET_TXUNDERFLOWERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXUNDERFLOWERROR_FRMCNT_SHIFT) & ENET_TXUNDERFLOWERROR_FRMCNT_MASK) -#define ENET_TXUNDERFLOWERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXUNDERFLOWERROR_FRMCNT_MASK) >> ENET_TXUNDERFLOWERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXSINGLECOL_G */ -/* - * FRMCNT (RW) - * - * Number of successfully transmitted frames after a single collision in the half-duplex mode. - */ -#define ENET_TXSINGLECOL_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXSINGLECOL_G_FRMCNT_SHIFT (0U) -#define ENET_TXSINGLECOL_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXSINGLECOL_G_FRMCNT_SHIFT) & ENET_TXSINGLECOL_G_FRMCNT_MASK) -#define ENET_TXSINGLECOL_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXSINGLECOL_G_FRMCNT_MASK) >> ENET_TXSINGLECOL_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXMULTICOL_G */ -/* - * FRMCNT (RW) - * - * Number of successfully transmitted frames after multiple collisions in the half-duplex mode. - */ -#define ENET_TXMULTICOL_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXMULTICOL_G_FRMCNT_SHIFT (0U) -#define ENET_TXMULTICOL_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXMULTICOL_G_FRMCNT_SHIFT) & ENET_TXMULTICOL_G_FRMCNT_MASK) -#define ENET_TXMULTICOL_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXMULTICOL_G_FRMCNT_MASK) >> ENET_TXMULTICOL_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXDEFERRED */ -/* - * FRMCNT (RW) - * - * Number of successfully transmitted frames after a deferral in the half-duplex mode. - */ -#define ENET_TXDEFERRED_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXDEFERRED_FRMCNT_SHIFT (0U) -#define ENET_TXDEFERRED_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXDEFERRED_FRMCNT_SHIFT) & ENET_TXDEFERRED_FRMCNT_MASK) -#define ENET_TXDEFERRED_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXDEFERRED_FRMCNT_MASK) >> ENET_TXDEFERRED_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXLATECOL */ -/* - * FRMCNT (RW) - * - * Number of frames aborted because of late collision error. - */ -#define ENET_TXLATECOL_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXLATECOL_FRMCNT_SHIFT (0U) -#define ENET_TXLATECOL_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXLATECOL_FRMCNT_SHIFT) & ENET_TXLATECOL_FRMCNT_MASK) -#define ENET_TXLATECOL_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXLATECOL_FRMCNT_MASK) >> ENET_TXLATECOL_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXEXESSCOL */ -/* - * FRMCNT (RW) - * - * Number of frames aborted because of excessive (16) collision errors. - */ -#define ENET_TXEXESSCOL_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXEXESSCOL_FRMCNT_SHIFT (0U) -#define ENET_TXEXESSCOL_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXEXESSCOL_FRMCNT_SHIFT) & ENET_TXEXESSCOL_FRMCNT_MASK) -#define ENET_TXEXESSCOL_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXEXESSCOL_FRMCNT_MASK) >> ENET_TXEXESSCOL_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXCARRIERERROR */ -/* - * FRMCNT (RW) - * - * Number of frames aborted because of carrier sense error (no carrier or loss of carrier). - */ -#define ENET_TXCARRIERERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXCARRIERERROR_FRMCNT_SHIFT (0U) -#define ENET_TXCARRIERERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXCARRIERERROR_FRMCNT_SHIFT) & ENET_TXCARRIERERROR_FRMCNT_MASK) -#define ENET_TXCARRIERERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXCARRIERERROR_FRMCNT_MASK) >> ENET_TXCARRIERERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXOCTETCOUNT_G */ -/* - * BYTECNT (RW) - * - * Number of bytes transmitted, exclusive of preamble, only in good frames. - */ -#define ENET_TXOCTETCOUNT_G_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_TXOCTETCOUNT_G_BYTECNT_SHIFT (0U) -#define ENET_TXOCTETCOUNT_G_BYTECNT_SET(x) (((uint32_t)(x) << ENET_TXOCTETCOUNT_G_BYTECNT_SHIFT) & ENET_TXOCTETCOUNT_G_BYTECNT_MASK) -#define ENET_TXOCTETCOUNT_G_BYTECNT_GET(x) (((uint32_t)(x) & ENET_TXOCTETCOUNT_G_BYTECNT_MASK) >> ENET_TXOCTETCOUNT_G_BYTECNT_SHIFT) - -/* Bitfield definition for register: TXFRAMECOUNT_G */ -/* - * FRMCNT (RW) - * - * Number of good frames transmitted. - */ -#define ENET_TXFRAMECOUNT_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXFRAMECOUNT_G_FRMCNT_SHIFT (0U) -#define ENET_TXFRAMECOUNT_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXFRAMECOUNT_G_FRMCNT_SHIFT) & ENET_TXFRAMECOUNT_G_FRMCNT_MASK) -#define ENET_TXFRAMECOUNT_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXFRAMECOUNT_G_FRMCNT_MASK) >> ENET_TXFRAMECOUNT_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXEXCESSDEF */ -/* - * FRMCNT (RW) - * - * Number of frames aborted because of excessive deferral error (deferred for more than two max-sized frame times). - */ -#define ENET_TXEXCESSDEF_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXEXCESSDEF_FRMCNT_SHIFT (0U) -#define ENET_TXEXCESSDEF_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXEXCESSDEF_FRMCNT_SHIFT) & ENET_TXEXCESSDEF_FRMCNT_MASK) -#define ENET_TXEXCESSDEF_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXEXCESSDEF_FRMCNT_MASK) >> ENET_TXEXCESSDEF_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXPAUSEFRAMES */ -/* - * FRMCNT (RW) - * - * Number of good Pause frames transmitted. - */ -#define ENET_TXPAUSEFRAMES_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXPAUSEFRAMES_FRMCNT_SHIFT (0U) -#define ENET_TXPAUSEFRAMES_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXPAUSEFRAMES_FRMCNT_SHIFT) & ENET_TXPAUSEFRAMES_FRMCNT_MASK) -#define ENET_TXPAUSEFRAMES_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXPAUSEFRAMES_FRMCNT_MASK) >> ENET_TXPAUSEFRAMES_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXVLANFRAMES_G */ -/* - * FRMCNT (RW) - * - * Number of good VLAN frames transmitted, exclusive of retried frames. - */ -#define ENET_TXVLANFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXVLANFRAMES_G_FRMCNT_SHIFT (0U) -#define ENET_TXVLANFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXVLANFRAMES_G_FRMCNT_SHIFT) & ENET_TXVLANFRAMES_G_FRMCNT_MASK) -#define ENET_TXVLANFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXVLANFRAMES_G_FRMCNT_MASK) >> ENET_TXVLANFRAMES_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: TXOVERSIZE_G */ -/* - * FRMCNT (RW) - * - * Number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). - */ -#define ENET_TXOVERSIZE_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TXOVERSIZE_G_FRMCNT_SHIFT (0U) -#define ENET_TXOVERSIZE_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TXOVERSIZE_G_FRMCNT_SHIFT) & ENET_TXOVERSIZE_G_FRMCNT_MASK) -#define ENET_TXOVERSIZE_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TXOVERSIZE_G_FRMCNT_MASK) >> ENET_TXOVERSIZE_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXFRAMECOUNT_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received. - */ -#define ENET_RXFRAMECOUNT_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT (0U) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) >> ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXOCTETCOUNT_G */ -/* - * BYTECNT (RW) - * - * Number of bytes received, exclusive of preamble, in good and bad frames. - */ -#define ENET_RXOCTETCOUNT_G_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXOCTETCOUNT_G_BYTECNT_SHIFT (0U) -#define ENET_RXOCTETCOUNT_G_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXOCTETCOUNT_G_BYTECNT_SHIFT) & ENET_RXOCTETCOUNT_G_BYTECNT_MASK) -#define ENET_RXOCTETCOUNT_G_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXOCTETCOUNT_G_BYTECNT_MASK) >> ENET_RXOCTETCOUNT_G_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXOCTETCOUNT_GB */ -/* - * BYTECNT (RW) - * - * Number of bytes received, exclusive of preamble, only in good frames. - */ -#define ENET_RXOCTETCOUNT_GB_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXOCTETCOUNT_GB_BYTECNT_SHIFT (0U) -#define ENET_RXOCTETCOUNT_GB_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXOCTETCOUNT_GB_BYTECNT_SHIFT) & ENET_RXOCTETCOUNT_GB_BYTECNT_MASK) -#define ENET_RXOCTETCOUNT_GB_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXOCTETCOUNT_GB_BYTECNT_MASK) >> ENET_RXOCTETCOUNT_GB_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXBROADCASTFRAMES_G */ -/* - * FRMCNT (RW) - * - * Number of good broadcast frames received. - */ -#define ENET_RXBROADCASTFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXBROADCASTFRAMES_G_FRMCNT_SHIFT (0U) -#define ENET_RXBROADCASTFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXBROADCASTFRAMES_G_FRMCNT_SHIFT) & ENET_RXBROADCASTFRAMES_G_FRMCNT_MASK) -#define ENET_RXBROADCASTFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXBROADCASTFRAMES_G_FRMCNT_MASK) >> ENET_RXBROADCASTFRAMES_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXMULTICASTFRAMES_G */ -/* - * FRMCNT (RW) - * - * Number of good multicast frames received. - */ -#define ENET_RXMULTICASTFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXMULTICASTFRAMES_G_FRMCNT_SHIFT (0U) -#define ENET_RXMULTICASTFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXMULTICASTFRAMES_G_FRMCNT_SHIFT) & ENET_RXMULTICASTFRAMES_G_FRMCNT_MASK) -#define ENET_RXMULTICASTFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXMULTICASTFRAMES_G_FRMCNT_MASK) >> ENET_RXMULTICASTFRAMES_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXCRCERROR */ -/* - * FRMCNT (RW) - * - * Number of frames received with CRC error. - */ -#define ENET_RXCRCERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXCRCERROR_FRMCNT_SHIFT (0U) -#define ENET_RXCRCERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXCRCERROR_FRMCNT_SHIFT) & ENET_RXCRCERROR_FRMCNT_MASK) -#define ENET_RXCRCERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXCRCERROR_FRMCNT_MASK) >> ENET_RXCRCERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXALIGNMENTERROR */ -/* - * FRMCNT (RW) - * - * Number of frames received with alignment (dribble) error. Valid only in 10/100 mode. - */ -#define ENET_RXALIGNMENTERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXALIGNMENTERROR_FRMCNT_SHIFT (0U) -#define ENET_RXALIGNMENTERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXALIGNMENTERROR_FRMCNT_SHIFT) & ENET_RXALIGNMENTERROR_FRMCNT_MASK) -#define ENET_RXALIGNMENTERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXALIGNMENTERROR_FRMCNT_MASK) >> ENET_RXALIGNMENTERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXRUNTERROR */ -/* - * FRMCNT (RW) - * - * Number of frames received with runt (<64 bytes and CRC error) error. - */ -#define ENET_RXRUNTERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXRUNTERROR_FRMCNT_SHIFT (0U) -#define ENET_RXRUNTERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXRUNTERROR_FRMCNT_SHIFT) & ENET_RXRUNTERROR_FRMCNT_MASK) -#define ENET_RXRUNTERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXRUNTERROR_FRMCNT_MASK) >> ENET_RXRUNTERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXJABBERERROR */ -/* - * FRMCNT (RW) - * - * Number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames. - */ -#define ENET_RXJABBERERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXJABBERERROR_FRMCNT_SHIFT (0U) -#define ENET_RXJABBERERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXJABBERERROR_FRMCNT_SHIFT) & ENET_RXJABBERERROR_FRMCNT_MASK) -#define ENET_RXJABBERERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXJABBERERROR_FRMCNT_MASK) >> ENET_RXJABBERERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXUNDERSIZE_G */ -/* - * FRMCNT (RW) - * - * Number of frames received with length less than 64 bytes, without any errors. - */ -#define ENET_RXUNDERSIZE_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXUNDERSIZE_G_FRMCNT_SHIFT (0U) -#define ENET_RXUNDERSIZE_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXUNDERSIZE_G_FRMCNT_SHIFT) & ENET_RXUNDERSIZE_G_FRMCNT_MASK) -#define ENET_RXUNDERSIZE_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXUNDERSIZE_G_FRMCNT_MASK) >> ENET_RXUNDERSIZE_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXOVERSIZE_G */ -/* - * FRMCNT (RW) - * - * Number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled in Bit 27 of Register 0 (MAC Configuration Register)). - */ -#define ENET_RXOVERSIZE_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXOVERSIZE_G_FRMCNT_SHIFT (0U) -#define ENET_RXOVERSIZE_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXOVERSIZE_G_FRMCNT_SHIFT) & ENET_RXOVERSIZE_G_FRMCNT_MASK) -#define ENET_RXOVERSIZE_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXOVERSIZE_G_FRMCNT_MASK) >> ENET_RXOVERSIZE_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: RX64OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received with length 64 bytes, exclusive of preamble. - */ -#define ENET_RX64OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RX64OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_RX64OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX64OCTETS_GB_FRMCNT_SHIFT) & ENET_RX64OCTETS_GB_FRMCNT_MASK) -#define ENET_RX64OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX64OCTETS_GB_FRMCNT_MASK) >> ENET_RX64OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RX65TO127OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble. - */ -#define ENET_RX65TO127OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RX65TO127OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_RX65TO127OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX65TO127OCTETS_GB_FRMCNT_SHIFT) & ENET_RX65TO127OCTETS_GB_FRMCNT_MASK) -#define ENET_RX65TO127OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX65TO127OCTETS_GB_FRMCNT_MASK) >> ENET_RX65TO127OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RX128TO255OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. - */ -#define ENET_RX128TO255OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RX128TO255OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_RX128TO255OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX128TO255OCTETS_GB_FRMCNT_SHIFT) & ENET_RX128TO255OCTETS_GB_FRMCNT_MASK) -#define ENET_RX128TO255OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX128TO255OCTETS_GB_FRMCNT_MASK) >> ENET_RX128TO255OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RX256TO511OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received with length between 256 and 511 (inclusive) bytes, exclusive of preamble. - */ -#define ENET_RX256TO511OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RX256TO511OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_RX256TO511OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX256TO511OCTETS_GB_FRMCNT_SHIFT) & ENET_RX256TO511OCTETS_GB_FRMCNT_MASK) -#define ENET_RX256TO511OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX256TO511OCTETS_GB_FRMCNT_MASK) >> ENET_RX256TO511OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RX512TO1023OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble. - */ -#define ENET_RX512TO1023OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RX512TO1023OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_RX512TO1023OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX512TO1023OCTETS_GB_FRMCNT_SHIFT) & ENET_RX512TO1023OCTETS_GB_FRMCNT_MASK) -#define ENET_RX512TO1023OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX512TO1023OCTETS_GB_FRMCNT_MASK) >> ENET_RX512TO1023OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RX1024TOMAXOCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_RX1024TOMAXOCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RX1024TOMAXOCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_RX1024TOMAXOCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) & ENET_RX1024TOMAXOCTETS_GB_FRMCNT_MASK) -#define ENET_RX1024TOMAXOCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RX1024TOMAXOCTETS_GB_FRMCNT_MASK) >> ENET_RX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXUNICASTFRAMES_G */ -/* - * FRMCNT (RW) - * - * Number of received good unicast frames. - */ -#define ENET_RXUNICASTFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXUNICASTFRAMES_G_FRMCNT_SHIFT (0U) -#define ENET_RXUNICASTFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXUNICASTFRAMES_G_FRMCNT_SHIFT) & ENET_RXUNICASTFRAMES_G_FRMCNT_MASK) -#define ENET_RXUNICASTFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXUNICASTFRAMES_G_FRMCNT_MASK) >> ENET_RXUNICASTFRAMES_G_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXLENGTHERROR */ -/* - * FRMCNT (RW) - * - * Number of frames received with length error (Length type field ≠ frame size), for all frames with valid length field. - */ -#define ENET_RXLENGTHERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXLENGTHERROR_FRMCNT_SHIFT (0U) -#define ENET_RXLENGTHERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXLENGTHERROR_FRMCNT_SHIFT) & ENET_RXLENGTHERROR_FRMCNT_MASK) -#define ENET_RXLENGTHERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXLENGTHERROR_FRMCNT_MASK) >> ENET_RXLENGTHERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXOUTOFRANGETYPE */ -/* - * FRMCNT (RW) - * - * Number of frames received with length field not equal to the valid frame size (greater than 1,500 but less than 1,536). - */ -#define ENET_RXOUTOFRANGETYPE_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXOUTOFRANGETYPE_FRMCNT_SHIFT (0U) -#define ENET_RXOUTOFRANGETYPE_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXOUTOFRANGETYPE_FRMCNT_SHIFT) & ENET_RXOUTOFRANGETYPE_FRMCNT_MASK) -#define ENET_RXOUTOFRANGETYPE_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXOUTOFRANGETYPE_FRMCNT_MASK) >> ENET_RXOUTOFRANGETYPE_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXPAUSEFRAMES */ -/* - * FRMCNT (RW) - * - * Number of good and valid Pause frames received. - */ -#define ENET_RXPAUSEFRAMES_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXPAUSEFRAMES_FRMCNT_SHIFT (0U) -#define ENET_RXPAUSEFRAMES_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXPAUSEFRAMES_FRMCNT_SHIFT) & ENET_RXPAUSEFRAMES_FRMCNT_MASK) -#define ENET_RXPAUSEFRAMES_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXPAUSEFRAMES_FRMCNT_MASK) >> ENET_RXPAUSEFRAMES_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXFIFOOVERFLOW */ -/* - * FRMCNT (RW) - * - * Number of missed received frames because of FIFO overflow. This counter is not present in the GMAC-CORE configuration. - */ -#define ENET_RXFIFOOVERFLOW_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXFIFOOVERFLOW_FRMCNT_SHIFT (0U) -#define ENET_RXFIFOOVERFLOW_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXFIFOOVERFLOW_FRMCNT_SHIFT) & ENET_RXFIFOOVERFLOW_FRMCNT_MASK) -#define ENET_RXFIFOOVERFLOW_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXFIFOOVERFLOW_FRMCNT_MASK) >> ENET_RXFIFOOVERFLOW_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXVLANFRAMES_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad VLAN frames received. - */ -#define ENET_RXVLANFRAMES_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXVLANFRAMES_GB_FRMCNT_SHIFT (0U) -#define ENET_RXVLANFRAMES_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXVLANFRAMES_GB_FRMCNT_SHIFT) & ENET_RXVLANFRAMES_GB_FRMCNT_MASK) -#define ENET_RXVLANFRAMES_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXVLANFRAMES_GB_FRMCNT_MASK) >> ENET_RXVLANFRAMES_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXWATCHDOGERROR */ -/* - * FRMCNT (RW) - * - * Number of frames received with error because of watchdog timeout error (frames with a data load larger than 2,048 bytes or the value programmed in Register 55 (Watchdog Timeout Register)). - */ -#define ENET_RXWATCHDOGERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXWATCHDOGERROR_FRMCNT_SHIFT (0U) -#define ENET_RXWATCHDOGERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXWATCHDOGERROR_FRMCNT_SHIFT) & ENET_RXWATCHDOGERROR_FRMCNT_MASK) -#define ENET_RXWATCHDOGERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXWATCHDOGERROR_FRMCNT_MASK) >> ENET_RXWATCHDOGERROR_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXRCVERROR */ -/* - * FRMCNT (RW) - * - * Number of frames received with Receive error or Frame Extension error on the GMII or MII interface. - */ -#define ENET_RXRCVERROR_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXRCVERROR_FRMCNT_SHIFT (0U) -#define ENET_RXRCVERROR_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXRCVERROR_FRMCNT_SHIFT) & ENET_RXRCVERROR_FRMCNT_MASK) -#define ENET_RXRCVERROR_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXRCVERROR_FRMCNT_MASK) >> ENET_RXRCVERROR_FRMCNT_SHIFT) +#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT (0U) +#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) +#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) >> ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) -/* Bitfield definition for register: RXCTRLFRAMES_G */ +/* Bitfield definition for register: RXFRAMECOUNT_GB */ /* * FRMCNT (RW) * - * Number of received good control frames. + * Number of good and bad frames received. */ -#define ENET_RXCTRLFRAMES_G_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXCTRLFRAMES_G_FRMCNT_SHIFT (0U) -#define ENET_RXCTRLFRAMES_G_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXCTRLFRAMES_G_FRMCNT_SHIFT) & ENET_RXCTRLFRAMES_G_FRMCNT_MASK) -#define ENET_RXCTRLFRAMES_G_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXCTRLFRAMES_G_FRMCNT_MASK) >> ENET_RXCTRLFRAMES_G_FRMCNT_SHIFT) +#define ENET_RXFRAMECOUNT_GB_FRMCNT_MASK (0xFFFFFFFFUL) +#define ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT (0U) +#define ENET_RXFRAMECOUNT_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) +#define ENET_RXFRAMECOUNT_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) >> ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) /* Bitfield definition for register: MMC_IPC_INTR_MASK_RX */ /* @@ -4191,292 +3400,6 @@ errors */ #define ENET_RXIPV4_GD_FMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) #define ENET_RXIPV4_GD_FMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) >> ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) -/* Bitfield definition for register: RXIPV4_HDRERR_FRMS */ -/* - * FRMCNT (RW) - * - * Number of IPv4 datagrams received with header (checksum, length, or version mismatch) errors - */ -#define ENET_RXIPV4_HDRERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_HDRERR_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV4_HDRERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_HDRERR_FRMS_FRMCNT_SHIFT) & ENET_RXIPV4_HDRERR_FRMS_FRMCNT_MASK) -#define ENET_RXIPV4_HDRERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_HDRERR_FRMS_FRMCNT_MASK) >> ENET_RXIPV4_HDRERR_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_NOPAY_FRMS */ -/* - * FRMCNT (RW) - * - * Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine - */ -#define ENET_RXIPV4_NOPAY_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_NOPAY_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV4_NOPAY_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_NOPAY_FRMS_FRMCNT_SHIFT) & ENET_RXIPV4_NOPAY_FRMS_FRMCNT_MASK) -#define ENET_RXIPV4_NOPAY_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_NOPAY_FRMS_FRMCNT_MASK) >> ENET_RXIPV4_NOPAY_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_FRAG_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IPv4 datagrams with fragmentation - */ -#define ENET_RXIPV4_FRAG_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_FRAG_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV4_FRAG_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_FRAG_FRMS_FRMCNT_SHIFT) & ENET_RXIPV4_FRAG_FRMS_FRMCNT_MASK) -#define ENET_RXIPV4_FRAG_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_FRAG_FRMS_FRMCNT_MASK) >> ENET_RXIPV4_FRAG_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_UDSBL_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IPv4 datagrams received that had a UDP payload with checksum disabled - */ -#define ENET_RXIPV4_UDSBL_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_UDSBL_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV4_UDSBL_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_UDSBL_FRMS_FRMCNT_SHIFT) & ENET_RXIPV4_UDSBL_FRMS_FRMCNT_MASK) -#define ENET_RXIPV4_UDSBL_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_UDSBL_FRMS_FRMCNT_MASK) >> ENET_RXIPV4_UDSBL_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV6_GD_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads - */ -#define ENET_RXIPV6_GD_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV6_GD_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV6_GD_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_GD_FRMS_FRMCNT_SHIFT) & ENET_RXIPV6_GD_FRMS_FRMCNT_MASK) -#define ENET_RXIPV6_GD_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_GD_FRMS_FRMCNT_MASK) >> ENET_RXIPV6_GD_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV6_HDRERR_FRMS */ -/* - * FRMCNT (RW) - * - * Number of IPv6 datagrams received with header errors (length or version mismatch) - */ -#define ENET_RXIPV6_HDRERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV6_HDRERR_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV6_HDRERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_HDRERR_FRMS_FRMCNT_SHIFT) & ENET_RXIPV6_HDRERR_FRMS_FRMCNT_MASK) -#define ENET_RXIPV6_HDRERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_HDRERR_FRMS_FRMCNT_MASK) >> ENET_RXIPV6_HDRERR_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV6_NOPAY_FRMS */ -/* - * FRMCNT (RW) - * - * Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers - */ -#define ENET_RXIPV6_NOPAY_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV6_NOPAY_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV6_NOPAY_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_NOPAY_FRMS_FRMCNT_SHIFT) & ENET_RXIPV6_NOPAY_FRMS_FRMCNT_MASK) -#define ENET_RXIPV6_NOPAY_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_NOPAY_FRMS_FRMCNT_MASK) >> ENET_RXIPV6_NOPAY_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXUDP_GD_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IP datagrams with a good UDP payload. This counter is not updated when the rxipv4_udsbl_frms counter is incremented. - */ -#define ENET_RXUDP_GD_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXUDP_GD_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXUDP_GD_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXUDP_GD_FRMS_FRMCNT_SHIFT) & ENET_RXUDP_GD_FRMS_FRMCNT_MASK) -#define ENET_RXUDP_GD_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXUDP_GD_FRMS_FRMCNT_MASK) >> ENET_RXUDP_GD_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXUDP_ERR_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IP datagrams whose UDP payload has a checksum error - */ -#define ENET_RXUDP_ERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXUDP_ERR_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXUDP_ERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXUDP_ERR_FRMS_FRMCNT_SHIFT) & ENET_RXUDP_ERR_FRMS_FRMCNT_MASK) -#define ENET_RXUDP_ERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXUDP_ERR_FRMS_FRMCNT_MASK) >> ENET_RXUDP_ERR_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXTCP_GD_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IP datagrams with a good TCP payload - */ -#define ENET_RXTCP_GD_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXTCP_GD_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXTCP_GD_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXTCP_GD_FRMS_FRMCNT_SHIFT) & ENET_RXTCP_GD_FRMS_FRMCNT_MASK) -#define ENET_RXTCP_GD_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXTCP_GD_FRMS_FRMCNT_MASK) >> ENET_RXTCP_GD_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXTCP_ERR_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IP datagrams whose TCP payload has a checksum error - */ -#define ENET_RXTCP_ERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXTCP_ERR_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXTCP_ERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXTCP_ERR_FRMS_FRMCNT_SHIFT) & ENET_RXTCP_ERR_FRMS_FRMCNT_MASK) -#define ENET_RXTCP_ERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXTCP_ERR_FRMS_FRMCNT_MASK) >> ENET_RXTCP_ERR_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXICMP_GD_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IP datagrams with a good ICMP payload - */ -#define ENET_RXICMP_GD_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXICMP_GD_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXICMP_GD_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXICMP_GD_FRMS_FRMCNT_SHIFT) & ENET_RXICMP_GD_FRMS_FRMCNT_MASK) -#define ENET_RXICMP_GD_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXICMP_GD_FRMS_FRMCNT_MASK) >> ENET_RXICMP_GD_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXICMP_ERR_FRMS */ -/* - * FRMCNT (RW) - * - * Number of good IP datagrams whose ICMP payload has a checksum error - */ -#define ENET_RXICMP_ERR_FRMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXICMP_ERR_FRMS_FRMCNT_SHIFT (0U) -#define ENET_RXICMP_ERR_FRMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXICMP_ERR_FRMS_FRMCNT_SHIFT) & ENET_RXICMP_ERR_FRMS_FRMCNT_MASK) -#define ENET_RXICMP_ERR_FRMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXICMP_ERR_FRMS_FRMCNT_MASK) >> ENET_RXICMP_ERR_FRMS_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_GD_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are not included in this counter or in the octet counters listed below). - */ -#define ENET_RXIPV4_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_GD_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV4_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_GD_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV4_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_GD_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_GD_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_HDRERR_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in IPv4 datagrams with header errors (checksum, length, version mismatch). The value in the Length field of IPv4 header is used to update this counter. - */ -#define ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_HDRERR_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_NOPAY_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 header’s Length field is used to update this counter. - */ -#define ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_NOPAY_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_FRAG_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 header’s Length field is used to update this counter. - */ -#define ENET_RXIPV4_FRAG_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_FRAG_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV4_FRAG_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_FRAG_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_FRAG_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV4_FRAG_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_FRAG_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_FRAG_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV4_UDSBL_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. - */ -#define ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_MASK) >> ENET_RXIPV4_UDSBL_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV6_GD_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data - */ -#define ENET_RXIPV6_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV6_GD_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV6_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV6_GD_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV6_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_GD_OCTETS_BYTECNT_MASK) >> ENET_RXIPV6_GD_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV6_HDRERR_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in IPv6 datagrams with header errors (length, version mismatch). The value in the IPv6 header’s Length field is used to update this counter. - */ -#define ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_MASK) >> ENET_RXIPV6_HDRERR_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXIPV6_NOPAY_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 header’s Length field is used to update this counter. - */ -#define ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_SHIFT) & ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_MASK) -#define ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_MASK) >> ENET_RXIPV6_NOPAY_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXUDP_GD_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in a good UDP segment. This counter (and the counters below) does not count IP header bytes. - */ -#define ENET_RXUDP_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXUDP_GD_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXUDP_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXUDP_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXUDP_GD_OCTETS_BYTECNT_MASK) -#define ENET_RXUDP_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXUDP_GD_OCTETS_BYTECNT_MASK) >> ENET_RXUDP_GD_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXUDP_ERR_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in a UDP segment that had checksum errors - */ -#define ENET_RXUDP_ERR_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXUDP_ERR_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXUDP_ERR_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXUDP_ERR_OCTETS_BYTECNT_SHIFT) & ENET_RXUDP_ERR_OCTETS_BYTECNT_MASK) -#define ENET_RXUDP_ERR_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXUDP_ERR_OCTETS_BYTECNT_MASK) >> ENET_RXUDP_ERR_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXTCP_GD_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in a good TCP segment - */ -#define ENET_RXTCP_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXTCP_GD_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXTCP_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXTCP_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXTCP_GD_OCTETS_BYTECNT_MASK) -#define ENET_RXTCP_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXTCP_GD_OCTETS_BYTECNT_MASK) >> ENET_RXTCP_GD_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXTCP_ERR_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in a TCP segment with checksum errors - */ -#define ENET_RXTCP_ERR_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXTCP_ERR_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXTCP_ERR_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXTCP_ERR_OCTETS_BYTECNT_SHIFT) & ENET_RXTCP_ERR_OCTETS_BYTECNT_MASK) -#define ENET_RXTCP_ERR_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXTCP_ERR_OCTETS_BYTECNT_MASK) >> ENET_RXTCP_ERR_OCTETS_BYTECNT_SHIFT) - -/* Bitfield definition for register: RXICMP_GD_OCTETS */ -/* - * BYTECNT (RW) - * - * Number of bytes received in a good ICMP segment - */ -#define ENET_RXICMP_GD_OCTETS_BYTECNT_MASK (0xFFFFFFFFUL) -#define ENET_RXICMP_GD_OCTETS_BYTECNT_SHIFT (0U) -#define ENET_RXICMP_GD_OCTETS_BYTECNT_SET(x) (((uint32_t)(x) << ENET_RXICMP_GD_OCTETS_BYTECNT_SHIFT) & ENET_RXICMP_GD_OCTETS_BYTECNT_MASK) -#define ENET_RXICMP_GD_OCTETS_BYTECNT_GET(x) (((uint32_t)(x) & ENET_RXICMP_GD_OCTETS_BYTECNT_MASK) >> ENET_RXICMP_GD_OCTETS_BYTECNT_SHIFT) - /* Bitfield definition for register of struct array L3_L4_CFG: L3_L4_CTRL */ /* * L4DPIM0 (RW) @@ -4692,18 +3615,6 @@ errors */ #define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) #define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) >> ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) -/* Bitfield definition for register array: HASH_TABLE */ -/* - * HT31T0 (RW) - * - * First 32 bits of Hash Table - * This field contains the first 32 Bits (31:0) of the Hash table. - */ -#define ENET_HASH_TABLE_HT31T0_MASK (0xFFFFFFFFUL) -#define ENET_HASH_TABLE_HT31T0_SHIFT (0U) -#define ENET_HASH_TABLE_HT31T0_SET(x) (((uint32_t)(x) << ENET_HASH_TABLE_HT31T0_SHIFT) & ENET_HASH_TABLE_HT31T0_MASK) -#define ENET_HASH_TABLE_HT31T0_GET(x) (((uint32_t)(x) & ENET_HASH_TABLE_HT31T0_MASK) >> ENET_HASH_TABLE_HT31T0_SHIFT) - /* Bitfield definition for register: VLAN_TAG_INC_RPL */ /* * CSVL (RW) @@ -5295,6 +4206,17 @@ errors */ #define ENET_PPS_CTRL_TRGTMODSEL1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) #define ENET_PPS_CTRL_TRGTMODSEL1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) >> ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) +/* + * PPSEN1 (RW) + * + * Flexible PPS1 Output Mode Enable + * When set high, Bits[10:8] function as PPSCMD. + */ +#define ENET_PPS_CTRL_PPSEN1_MASK (0x1000U) +#define ENET_PPS_CTRL_PPSEN1_SHIFT (12U) +#define ENET_PPS_CTRL_PPSEN1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSEN1_SHIFT) & ENET_PPS_CTRL_PPSEN1_MASK) +#define ENET_PPS_CTRL_PPSEN1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSEN1_MASK) >> ENET_PPS_CTRL_PPSEN1_SHIFT) + /* * PPSCMD1 (RW) * @@ -6655,293 +5577,13 @@ errors */ #define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) #define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) >> ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) -/* Bitfield definition for register: DMA_HW_FEATURE */ -/* - * ACTPHYIF (RW) - * - * Active or selected PHY interface - * When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. - * - 000: GMII or MII - * - 001: RGMII - * - 010: SGMII - * - 011: TBI - * - 100: RMII - * - 101: RTBI - * - 110: SMII - * - 111: RevMII - All Others: Reserved - */ -#define ENET_DMA_HW_FEATURE_ACTPHYIF_MASK (0x70000000UL) -#define ENET_DMA_HW_FEATURE_ACTPHYIF_SHIFT (28U) -#define ENET_DMA_HW_FEATURE_ACTPHYIF_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_ACTPHYIF_SHIFT) & ENET_DMA_HW_FEATURE_ACTPHYIF_MASK) -#define ENET_DMA_HW_FEATURE_ACTPHYIF_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_ACTPHYIF_MASK) >> ENET_DMA_HW_FEATURE_ACTPHYIF_SHIFT) - -/* - * SAVLANINS (RW) - * - * Source Address or VLAN Insertion - */ -#define ENET_DMA_HW_FEATURE_SAVLANINS_MASK (0x8000000UL) -#define ENET_DMA_HW_FEATURE_SAVLANINS_SHIFT (27U) -#define ENET_DMA_HW_FEATURE_SAVLANINS_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_SAVLANINS_SHIFT) & ENET_DMA_HW_FEATURE_SAVLANINS_MASK) -#define ENET_DMA_HW_FEATURE_SAVLANINS_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_SAVLANINS_MASK) >> ENET_DMA_HW_FEATURE_SAVLANINS_SHIFT) - -/* - * FLEXIPPSEN (RW) - * - * Flexible Pulse-Per-Second Output - */ -#define ENET_DMA_HW_FEATURE_FLEXIPPSEN_MASK (0x4000000UL) -#define ENET_DMA_HW_FEATURE_FLEXIPPSEN_SHIFT (26U) -#define ENET_DMA_HW_FEATURE_FLEXIPPSEN_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_FLEXIPPSEN_SHIFT) & ENET_DMA_HW_FEATURE_FLEXIPPSEN_MASK) -#define ENET_DMA_HW_FEATURE_FLEXIPPSEN_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_FLEXIPPSEN_MASK) >> ENET_DMA_HW_FEATURE_FLEXIPPSEN_SHIFT) - -/* - * INTTSEN (RW) - * - * Timestamping with Internal System Time - */ -#define ENET_DMA_HW_FEATURE_INTTSEN_MASK (0x2000000UL) -#define ENET_DMA_HW_FEATURE_INTTSEN_SHIFT (25U) -#define ENET_DMA_HW_FEATURE_INTTSEN_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_INTTSEN_SHIFT) & ENET_DMA_HW_FEATURE_INTTSEN_MASK) -#define ENET_DMA_HW_FEATURE_INTTSEN_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_INTTSEN_MASK) >> ENET_DMA_HW_FEATURE_INTTSEN_SHIFT) - -/* - * ENHDESSEL (RW) - * - * Alternate (Enhanced Descriptor) - */ -#define ENET_DMA_HW_FEATURE_ENHDESSEL_MASK (0x1000000UL) -#define ENET_DMA_HW_FEATURE_ENHDESSEL_SHIFT (24U) -#define ENET_DMA_HW_FEATURE_ENHDESSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_ENHDESSEL_SHIFT) & ENET_DMA_HW_FEATURE_ENHDESSEL_MASK) -#define ENET_DMA_HW_FEATURE_ENHDESSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_ENHDESSEL_MASK) >> ENET_DMA_HW_FEATURE_ENHDESSEL_SHIFT) - -/* - * TXCHCNT (RW) - * - * Number of additional Tx Channels - */ -#define ENET_DMA_HW_FEATURE_TXCHCNT_MASK (0xC00000UL) -#define ENET_DMA_HW_FEATURE_TXCHCNT_SHIFT (22U) -#define ENET_DMA_HW_FEATURE_TXCHCNT_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_TXCHCNT_SHIFT) & ENET_DMA_HW_FEATURE_TXCHCNT_MASK) -#define ENET_DMA_HW_FEATURE_TXCHCNT_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_TXCHCNT_MASK) >> ENET_DMA_HW_FEATURE_TXCHCNT_SHIFT) - -/* - * RXCHCNT (RW) - * - * Number of additional Rx Channels - */ -#define ENET_DMA_HW_FEATURE_RXCHCNT_MASK (0x300000UL) -#define ENET_DMA_HW_FEATURE_RXCHCNT_SHIFT (20U) -#define ENET_DMA_HW_FEATURE_RXCHCNT_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RXCHCNT_SHIFT) & ENET_DMA_HW_FEATURE_RXCHCNT_MASK) -#define ENET_DMA_HW_FEATURE_RXCHCNT_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RXCHCNT_MASK) >> ENET_DMA_HW_FEATURE_RXCHCNT_SHIFT) - -/* - * RXFIFOSIZE (RW) - * - * Rx FIFO > 2,048 Bytes - */ -#define ENET_DMA_HW_FEATURE_RXFIFOSIZE_MASK (0x80000UL) -#define ENET_DMA_HW_FEATURE_RXFIFOSIZE_SHIFT (19U) -#define ENET_DMA_HW_FEATURE_RXFIFOSIZE_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RXFIFOSIZE_SHIFT) & ENET_DMA_HW_FEATURE_RXFIFOSIZE_MASK) -#define ENET_DMA_HW_FEATURE_RXFIFOSIZE_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RXFIFOSIZE_MASK) >> ENET_DMA_HW_FEATURE_RXFIFOSIZE_SHIFT) - -/* - * RXTYP2COE (RW) - * - * IP Checksum Offload (Type 2) in Rx - */ -#define ENET_DMA_HW_FEATURE_RXTYP2COE_MASK (0x40000UL) -#define ENET_DMA_HW_FEATURE_RXTYP2COE_SHIFT (18U) -#define ENET_DMA_HW_FEATURE_RXTYP2COE_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RXTYP2COE_SHIFT) & ENET_DMA_HW_FEATURE_RXTYP2COE_MASK) -#define ENET_DMA_HW_FEATURE_RXTYP2COE_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RXTYP2COE_MASK) >> ENET_DMA_HW_FEATURE_RXTYP2COE_SHIFT) - -/* - * RXTYP1COE (RW) - * - * IP Checksum Offload (Type 1) in Rx Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE = 1. - */ -#define ENET_DMA_HW_FEATURE_RXTYP1COE_MASK (0x20000UL) -#define ENET_DMA_HW_FEATURE_RXTYP1COE_SHIFT (17U) -#define ENET_DMA_HW_FEATURE_RXTYP1COE_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RXTYP1COE_SHIFT) & ENET_DMA_HW_FEATURE_RXTYP1COE_MASK) -#define ENET_DMA_HW_FEATURE_RXTYP1COE_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RXTYP1COE_MASK) >> ENET_DMA_HW_FEATURE_RXTYP1COE_SHIFT) - -/* - * TXCOESEL (RW) - * - * Checksum Offload in Tx - */ -#define ENET_DMA_HW_FEATURE_TXCOESEL_MASK (0x10000UL) -#define ENET_DMA_HW_FEATURE_TXCOESEL_SHIFT (16U) -#define ENET_DMA_HW_FEATURE_TXCOESEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_TXCOESEL_SHIFT) & ENET_DMA_HW_FEATURE_TXCOESEL_MASK) -#define ENET_DMA_HW_FEATURE_TXCOESEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_TXCOESEL_MASK) >> ENET_DMA_HW_FEATURE_TXCOESEL_SHIFT) - -/* - * AVSEL (RW) - * - * AV feature - */ -#define ENET_DMA_HW_FEATURE_AVSEL_MASK (0x8000U) -#define ENET_DMA_HW_FEATURE_AVSEL_SHIFT (15U) -#define ENET_DMA_HW_FEATURE_AVSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_AVSEL_SHIFT) & ENET_DMA_HW_FEATURE_AVSEL_MASK) -#define ENET_DMA_HW_FEATURE_AVSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_AVSEL_MASK) >> ENET_DMA_HW_FEATURE_AVSEL_SHIFT) - -/* - * EEESEL (RW) - * - * Energy Efficient Ethernet - */ -#define ENET_DMA_HW_FEATURE_EEESEL_MASK (0x4000U) -#define ENET_DMA_HW_FEATURE_EEESEL_SHIFT (14U) -#define ENET_DMA_HW_FEATURE_EEESEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_EEESEL_SHIFT) & ENET_DMA_HW_FEATURE_EEESEL_MASK) -#define ENET_DMA_HW_FEATURE_EEESEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_EEESEL_MASK) >> ENET_DMA_HW_FEATURE_EEESEL_SHIFT) - -/* - * TSVER2SEL (RW) - * - * IEEE 1588-2008 Advanced timestamp - */ -#define ENET_DMA_HW_FEATURE_TSVER2SEL_MASK (0x2000U) -#define ENET_DMA_HW_FEATURE_TSVER2SEL_SHIFT (13U) -#define ENET_DMA_HW_FEATURE_TSVER2SEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_TSVER2SEL_SHIFT) & ENET_DMA_HW_FEATURE_TSVER2SEL_MASK) -#define ENET_DMA_HW_FEATURE_TSVER2SEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_TSVER2SEL_MASK) >> ENET_DMA_HW_FEATURE_TSVER2SEL_SHIFT) - -/* - * TSVER1SEL (RW) - * - * Only IEEE 1588-2002 timestamp - */ -#define ENET_DMA_HW_FEATURE_TSVER1SEL_MASK (0x1000U) -#define ENET_DMA_HW_FEATURE_TSVER1SEL_SHIFT (12U) -#define ENET_DMA_HW_FEATURE_TSVER1SEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_TSVER1SEL_SHIFT) & ENET_DMA_HW_FEATURE_TSVER1SEL_MASK) -#define ENET_DMA_HW_FEATURE_TSVER1SEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_TSVER1SEL_MASK) >> ENET_DMA_HW_FEATURE_TSVER1SEL_SHIFT) - -/* - * MMCSEL (RW) - * - * RMON module - */ -#define ENET_DMA_HW_FEATURE_MMCSEL_MASK (0x800U) -#define ENET_DMA_HW_FEATURE_MMCSEL_SHIFT (11U) -#define ENET_DMA_HW_FEATURE_MMCSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_MMCSEL_SHIFT) & ENET_DMA_HW_FEATURE_MMCSEL_MASK) -#define ENET_DMA_HW_FEATURE_MMCSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_MMCSEL_MASK) >> ENET_DMA_HW_FEATURE_MMCSEL_SHIFT) - -/* - * MGKSEL (RW) - * - * PMT magic packet - */ -#define ENET_DMA_HW_FEATURE_MGKSEL_MASK (0x400U) -#define ENET_DMA_HW_FEATURE_MGKSEL_SHIFT (10U) -#define ENET_DMA_HW_FEATURE_MGKSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_MGKSEL_SHIFT) & ENET_DMA_HW_FEATURE_MGKSEL_MASK) -#define ENET_DMA_HW_FEATURE_MGKSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_MGKSEL_MASK) >> ENET_DMA_HW_FEATURE_MGKSEL_SHIFT) - -/* - * RWKSEL (RW) - * - * PMT remote wake-up frame - */ -#define ENET_DMA_HW_FEATURE_RWKSEL_MASK (0x200U) -#define ENET_DMA_HW_FEATURE_RWKSEL_SHIFT (9U) -#define ENET_DMA_HW_FEATURE_RWKSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_RWKSEL_SHIFT) & ENET_DMA_HW_FEATURE_RWKSEL_MASK) -#define ENET_DMA_HW_FEATURE_RWKSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_RWKSEL_MASK) >> ENET_DMA_HW_FEATURE_RWKSEL_SHIFT) - -/* - * SMASEL (RW) - * - * SMA (MDIO) Interface - */ -#define ENET_DMA_HW_FEATURE_SMASEL_MASK (0x100U) -#define ENET_DMA_HW_FEATURE_SMASEL_SHIFT (8U) -#define ENET_DMA_HW_FEATURE_SMASEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_SMASEL_SHIFT) & ENET_DMA_HW_FEATURE_SMASEL_MASK) -#define ENET_DMA_HW_FEATURE_SMASEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_SMASEL_MASK) >> ENET_DMA_HW_FEATURE_SMASEL_SHIFT) - -/* - * L3L4FLTREN (RW) - * - * Layer 3 and Layer 4 feature - */ -#define ENET_DMA_HW_FEATURE_L3L4FLTREN_MASK (0x80U) -#define ENET_DMA_HW_FEATURE_L3L4FLTREN_SHIFT (7U) -#define ENET_DMA_HW_FEATURE_L3L4FLTREN_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_L3L4FLTREN_SHIFT) & ENET_DMA_HW_FEATURE_L3L4FLTREN_MASK) -#define ENET_DMA_HW_FEATURE_L3L4FLTREN_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_L3L4FLTREN_MASK) >> ENET_DMA_HW_FEATURE_L3L4FLTREN_SHIFT) - -/* - * PCSSEL (RW) - * - * PCS registers (TBI, SGMII, or RTBI PHY interface) - */ -#define ENET_DMA_HW_FEATURE_PCSSEL_MASK (0x40U) -#define ENET_DMA_HW_FEATURE_PCSSEL_SHIFT (6U) -#define ENET_DMA_HW_FEATURE_PCSSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_PCSSEL_SHIFT) & ENET_DMA_HW_FEATURE_PCSSEL_MASK) -#define ENET_DMA_HW_FEATURE_PCSSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_PCSSEL_MASK) >> ENET_DMA_HW_FEATURE_PCSSEL_SHIFT) - -/* - * ADDMACADRSEL (RW) - * - * Multiple MAC Address registers - */ -#define ENET_DMA_HW_FEATURE_ADDMACADRSEL_MASK (0x20U) -#define ENET_DMA_HW_FEATURE_ADDMACADRSEL_SHIFT (5U) -#define ENET_DMA_HW_FEATURE_ADDMACADRSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_ADDMACADRSEL_SHIFT) & ENET_DMA_HW_FEATURE_ADDMACADRSEL_MASK) -#define ENET_DMA_HW_FEATURE_ADDMACADRSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_ADDMACADRSEL_MASK) >> ENET_DMA_HW_FEATURE_ADDMACADRSEL_SHIFT) - -/* - * HASHSEL (RW) - * - * HASH filter - */ -#define ENET_DMA_HW_FEATURE_HASHSEL_MASK (0x10U) -#define ENET_DMA_HW_FEATURE_HASHSEL_SHIFT (4U) -#define ENET_DMA_HW_FEATURE_HASHSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_HASHSEL_SHIFT) & ENET_DMA_HW_FEATURE_HASHSEL_MASK) -#define ENET_DMA_HW_FEATURE_HASHSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_HASHSEL_MASK) >> ENET_DMA_HW_FEATURE_HASHSEL_SHIFT) - -/* - * EXTHASHEN (RW) - * - * Expanded DA Hash filter - */ -#define ENET_DMA_HW_FEATURE_EXTHASHEN_MASK (0x8U) -#define ENET_DMA_HW_FEATURE_EXTHASHEN_SHIFT (3U) -#define ENET_DMA_HW_FEATURE_EXTHASHEN_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_EXTHASHEN_SHIFT) & ENET_DMA_HW_FEATURE_EXTHASHEN_MASK) -#define ENET_DMA_HW_FEATURE_EXTHASHEN_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_EXTHASHEN_MASK) >> ENET_DMA_HW_FEATURE_EXTHASHEN_SHIFT) - -/* - * HDSEL (RW) - * - * Half-duplex support - */ -#define ENET_DMA_HW_FEATURE_HDSEL_MASK (0x4U) -#define ENET_DMA_HW_FEATURE_HDSEL_SHIFT (2U) -#define ENET_DMA_HW_FEATURE_HDSEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_HDSEL_SHIFT) & ENET_DMA_HW_FEATURE_HDSEL_MASK) -#define ENET_DMA_HW_FEATURE_HDSEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_HDSEL_MASK) >> ENET_DMA_HW_FEATURE_HDSEL_SHIFT) - -/* - * GMIISEL (RW) - * - * 1000 Mbps support - */ -#define ENET_DMA_HW_FEATURE_GMIISEL_MASK (0x2U) -#define ENET_DMA_HW_FEATURE_GMIISEL_SHIFT (1U) -#define ENET_DMA_HW_FEATURE_GMIISEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_GMIISEL_SHIFT) & ENET_DMA_HW_FEATURE_GMIISEL_MASK) -#define ENET_DMA_HW_FEATURE_GMIISEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_GMIISEL_MASK) >> ENET_DMA_HW_FEATURE_GMIISEL_SHIFT) - -/* - * MIISEL (RW) - * - * 10 or 100 Mbps support - */ -#define ENET_DMA_HW_FEATURE_MIISEL_MASK (0x1U) -#define ENET_DMA_HW_FEATURE_MIISEL_SHIFT (0U) -#define ENET_DMA_HW_FEATURE_MIISEL_SET(x) (((uint32_t)(x) << ENET_DMA_HW_FEATURE_MIISEL_SHIFT) & ENET_DMA_HW_FEATURE_MIISEL_MASK) -#define ENET_DMA_HW_FEATURE_MIISEL_GET(x) (((uint32_t)(x) & ENET_DMA_HW_FEATURE_MIISEL_MASK) >> ENET_DMA_HW_FEATURE_MIISEL_SHIFT) - /* Bitfield definition for register: CTRL0 */ /* * ENET0_RXCLK_DLY_SEL (RW) * */ -#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK (0x3E0U) -#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT (5U) +#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK (0x3F00U) +#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT (8U) #define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) & ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) #define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) >> ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) @@ -6949,7 +5591,7 @@ errors */ * ENET0_TXCLK_DLY_SEL (RW) * */ -#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK (0x1FU) +#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK (0x3FU) #define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT (0U) #define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) & ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) #define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) >> ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) @@ -6958,6 +5600,7 @@ errors */ /* * ENET0_LPI_IRQ_EN (RW) * + * lowpower interrupt enable, for internal use only, user should use core registers for enable/disable interrupt */ #define ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK (0x20000000UL) #define ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT (29U) @@ -6967,6 +5610,8 @@ errors */ /* * ENET0_REFCLK_OE (RW) * + * set to enable output 50MHz clock to rmii phy. + * User should set it if use soc internal clock as refclk */ #define ENET_CTRL2_ENET0_REFCLK_OE_MASK (0x80000UL) #define ENET_CTRL2_ENET0_REFCLK_OE_SHIFT (19U) @@ -6976,6 +5621,9 @@ errors */ /* * ENET0_PHY_INF_SEL (RW) * + * PHY mode select + * 000MII; 001RGMII; 100RMII; + * should be set before config IOMUX, otherwise may cause glitch for RGMII */ #define ENET_CTRL2_ENET0_PHY_INF_SEL_MASK (0xE000U) #define ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT (13U) @@ -6985,6 +5633,7 @@ errors */ /* * ENET0_FLOWCTRL (RW) * + * flow control request */ #define ENET_CTRL2_ENET0_FLOWCTRL_MASK (0x1000U) #define ENET_CTRL2_ENET0_FLOWCTRL_SHIFT (12U) @@ -6994,6 +5643,10 @@ errors */ /* * ENET0_RMII_TXCLK_SEL (RW) * + * RMII mode output clock pad select + * set to use txck as RMII refclk; + * clr to use rxck as RMII refclk; default 0(rxck) + * refclk is always from pad, can use external clock from pad, or use internal clock output to pad then loopback. */ #define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK (0x400U) #define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT (10U) @@ -7010,19 +5663,6 @@ errors */ /* L3_L4_CFG register group index macro definition */ #define ENET_L3_L4_CFG_0 (0UL) -#define ENET_L3_L4_CFG_1 (1UL) -#define ENET_L3_L4_CFG_2 (2UL) -#define ENET_L3_L4_CFG_3 (3UL) - -/* HASH_TABLE register group index macro definition */ -#define ENET_HASH_TABLE_REGISTER0 (0UL) -#define ENET_HASH_TABLE_REGISTER1 (1UL) -#define ENET_HASH_TABLE_REGISTER2 (2UL) -#define ENET_HASH_TABLE_REGISTER3 (3UL) -#define ENET_HASH_TABLE_REGISTER4 (4UL) -#define ENET_HASH_TABLE_REGISTER5 (5UL) -#define ENET_HASH_TABLE_REGISTER6 (6UL) -#define ENET_HASH_TABLE_REGISTER7 (7UL) /* PPS register group index macro definition */ #define ENET_PPS_1 (0UL) diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_lin_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_lin_regs.h new file mode 100644 index 00000000..b798c820 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_lin_regs.h @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_LIN_H +#define HPM_LIN_H + +typedef struct { + __RW uint32_t DATABYTE[8]; /* 0x0 - 0x1C: data byte */ + __RW uint32_t CONTROL; /* 0x20: control register */ + __R uint32_t STATE; /* 0x24: state register */ + __R uint32_t ERROR; /* 0x28: error register */ + __RW uint32_t DATA_LEN; /* 0x2C: data lenth register */ + __RW uint32_t BAUDRATE_CTL_LOW; /* 0x30: baudrate control low register */ + __RW uint32_t BARDRATE_CTL_HIGH; /* 0x34: baudrate control high register */ + __RW uint32_t ID; /* 0x38: id register */ + __RW uint32_t TV; /* 0x3C: timeout control register */ +} LIN_Type; + + +/* Bitfield definition for register array: DATABYTE */ +/* + * DATA_BYTE (RW) + * + * data byte + */ +#define LIN_DATABYTE_DATA_BYTE_MASK (0xFFU) +#define LIN_DATABYTE_DATA_BYTE_SHIFT (0U) +#define LIN_DATABYTE_DATA_BYTE_SET(x) (((uint32_t)(x) << LIN_DATABYTE_DATA_BYTE_SHIFT) & LIN_DATABYTE_DATA_BYTE_MASK) +#define LIN_DATABYTE_DATA_BYTE_GET(x) (((uint32_t)(x) & LIN_DATABYTE_DATA_BYTE_MASK) >> LIN_DATABYTE_DATA_BYTE_SHIFT) + +/* Bitfield definition for register: CONTROL */ +/* + * STOP (WO) + * + * slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID + */ +#define LIN_CONTROL_STOP_MASK (0x80U) +#define LIN_CONTROL_STOP_SHIFT (7U) +#define LIN_CONTROL_STOP_SET(x) (((uint32_t)(x) << LIN_CONTROL_STOP_SHIFT) & LIN_CONTROL_STOP_MASK) +#define LIN_CONTROL_STOP_GET(x) (((uint32_t)(x) & LIN_CONTROL_STOP_MASK) >> LIN_CONTROL_STOP_SHIFT) + +/* + * SLEEP (RW) + * + * The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core. + */ +#define LIN_CONTROL_SLEEP_MASK (0x40U) +#define LIN_CONTROL_SLEEP_SHIFT (6U) +#define LIN_CONTROL_SLEEP_SET(x) (((uint32_t)(x) << LIN_CONTROL_SLEEP_SHIFT) & LIN_CONTROL_SLEEP_MASK) +#define LIN_CONTROL_SLEEP_GET(x) (((uint32_t)(x) & LIN_CONTROL_SLEEP_MASK) >> LIN_CONTROL_SLEEP_SHIFT) + +/* + * TRANSMIT (RW) + * + * 1: transmit operation 0: receive operation + */ +#define LIN_CONTROL_TRANSMIT_MASK (0x20U) +#define LIN_CONTROL_TRANSMIT_SHIFT (5U) +#define LIN_CONTROL_TRANSMIT_SET(x) (((uint32_t)(x) << LIN_CONTROL_TRANSMIT_SHIFT) & LIN_CONTROL_TRANSMIT_MASK) +#define LIN_CONTROL_TRANSMIT_GET(x) (((uint32_t)(x) & LIN_CONTROL_TRANSMIT_MASK) >> LIN_CONTROL_TRANSMIT_SHIFT) + +/* + * DATA_ACK (RW) + * + * slave only. Write 1 after handling a data request interrupt + */ +#define LIN_CONTROL_DATA_ACK_MASK (0x10U) +#define LIN_CONTROL_DATA_ACK_SHIFT (4U) +#define LIN_CONTROL_DATA_ACK_SET(x) (((uint32_t)(x) << LIN_CONTROL_DATA_ACK_SHIFT) & LIN_CONTROL_DATA_ACK_MASK) +#define LIN_CONTROL_DATA_ACK_GET(x) (((uint32_t)(x) & LIN_CONTROL_DATA_ACK_MASK) >> LIN_CONTROL_DATA_ACK_SHIFT) + +/* + * RESET_INT (WO) + * + * write 1 to reset the int bit in the status register and the interrupt request output of LIN + */ +#define LIN_CONTROL_RESET_INT_MASK (0x8U) +#define LIN_CONTROL_RESET_INT_SHIFT (3U) +#define LIN_CONTROL_RESET_INT_SET(x) (((uint32_t)(x) << LIN_CONTROL_RESET_INT_SHIFT) & LIN_CONTROL_RESET_INT_MASK) +#define LIN_CONTROL_RESET_INT_GET(x) (((uint32_t)(x) & LIN_CONTROL_RESET_INT_MASK) >> LIN_CONTROL_RESET_INT_SHIFT) + +/* + * RESET_ERROR (WO) + * + * assert 1 to reset the error bits in status register and error register. A read access to this bit delivers always the value 0 + */ +#define LIN_CONTROL_RESET_ERROR_MASK (0x4U) +#define LIN_CONTROL_RESET_ERROR_SHIFT (2U) +#define LIN_CONTROL_RESET_ERROR_SET(x) (((uint32_t)(x) << LIN_CONTROL_RESET_ERROR_SHIFT) & LIN_CONTROL_RESET_ERROR_MASK) +#define LIN_CONTROL_RESET_ERROR_GET(x) (((uint32_t)(x) & LIN_CONTROL_RESET_ERROR_MASK) >> LIN_CONTROL_RESET_ERROR_SHIFT) + +/* + * WAKEUP_REQ (RW) + * + * wakeup request. Assert to terminate the Sleep mode of the LIN bus. The bit will be reset by core + */ +#define LIN_CONTROL_WAKEUP_REQ_MASK (0x2U) +#define LIN_CONTROL_WAKEUP_REQ_SHIFT (1U) +#define LIN_CONTROL_WAKEUP_REQ_SET(x) (((uint32_t)(x) << LIN_CONTROL_WAKEUP_REQ_SHIFT) & LIN_CONTROL_WAKEUP_REQ_MASK) +#define LIN_CONTROL_WAKEUP_REQ_GET(x) (((uint32_t)(x) & LIN_CONTROL_WAKEUP_REQ_MASK) >> LIN_CONTROL_WAKEUP_REQ_SHIFT) + +/* + * START_REQ (RW) + * + * master only. Set by host controller of a LIN master to start the LIN transmission. The core will reset the bit after the transmission is finished or an error is occurred + */ +#define LIN_CONTROL_START_REQ_MASK (0x1U) +#define LIN_CONTROL_START_REQ_SHIFT (0U) +#define LIN_CONTROL_START_REQ_SET(x) (((uint32_t)(x) << LIN_CONTROL_START_REQ_SHIFT) & LIN_CONTROL_START_REQ_MASK) +#define LIN_CONTROL_START_REQ_GET(x) (((uint32_t)(x) & LIN_CONTROL_START_REQ_MASK) >> LIN_CONTROL_START_REQ_SHIFT) + +/* Bitfield definition for register: STATE */ +/* + * LIN_ACTIVE (RO) + * + * The bit indicates whether the LIN bus is active or not + */ +#define LIN_STATE_LIN_ACTIVE_MASK (0x80U) +#define LIN_STATE_LIN_ACTIVE_SHIFT (7U) +#define LIN_STATE_LIN_ACTIVE_GET(x) (((uint32_t)(x) & LIN_STATE_LIN_ACTIVE_MASK) >> LIN_STATE_LIN_ACTIVE_SHIFT) + +/* + * BUS_IDLE_TV (RO) + * + * slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s + */ +#define LIN_STATE_BUS_IDLE_TV_MASK (0x40U) +#define LIN_STATE_BUS_IDLE_TV_SHIFT (6U) +#define LIN_STATE_BUS_IDLE_TV_GET(x) (((uint32_t)(x) & LIN_STATE_BUS_IDLE_TV_MASK) >> LIN_STATE_BUS_IDLE_TV_SHIFT) + +/* + * ABORTED (RO) + * + * slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error. + */ +#define LIN_STATE_ABORTED_MASK (0x20U) +#define LIN_STATE_ABORTED_SHIFT (5U) +#define LIN_STATE_ABORTED_GET(x) (((uint32_t)(x) & LIN_STATE_ABORTED_MASK) >> LIN_STATE_ABORTED_SHIFT) + +/* + * DATA_REQ (RO) + * + * slave only. Sets after receiving the identifier and requests an interrupt to the host controller. + */ +#define LIN_STATE_DATA_REQ_MASK (0x10U) +#define LIN_STATE_DATA_REQ_SHIFT (4U) +#define LIN_STATE_DATA_REQ_GET(x) (((uint32_t)(x) & LIN_STATE_DATA_REQ_MASK) >> LIN_STATE_DATA_REQ_SHIFT) + +/* + * INT (RO) + * + * set when request an interrupt. Reset by reset_int + */ +#define LIN_STATE_INT_MASK (0x8U) +#define LIN_STATE_INT_SHIFT (3U) +#define LIN_STATE_INT_GET(x) (((uint32_t)(x) & LIN_STATE_INT_MASK) >> LIN_STATE_INT_SHIFT) + +/* + * ERROR (RO) + * + * set when detecte an error, clear by reset_error + */ +#define LIN_STATE_ERROR_MASK (0x4U) +#define LIN_STATE_ERROR_SHIFT (2U) +#define LIN_STATE_ERROR_GET(x) (((uint32_t)(x) & LIN_STATE_ERROR_MASK) >> LIN_STATE_ERROR_SHIFT) + +/* + * WAKEUP (RO) + * + * set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1 + */ +#define LIN_STATE_WAKEUP_MASK (0x2U) +#define LIN_STATE_WAKEUP_SHIFT (1U) +#define LIN_STATE_WAKEUP_GET(x) (((uint32_t)(x) & LIN_STATE_WAKEUP_MASK) >> LIN_STATE_WAKEUP_SHIFT) + +/* + * COMPLETE (RO) + * + * set after a transmission has been successful finished and it will reset at the start of a transmission. + */ +#define LIN_STATE_COMPLETE_MASK (0x1U) +#define LIN_STATE_COMPLETE_SHIFT (0U) +#define LIN_STATE_COMPLETE_GET(x) (((uint32_t)(x) & LIN_STATE_COMPLETE_MASK) >> LIN_STATE_COMPLETE_SHIFT) + +/* Bitfield definition for register: ERROR */ +/* + * PARITY_ERROR (RO) + * + * slave only. identifier parity error + */ +#define LIN_ERROR_PARITY_ERROR_MASK (0x8U) +#define LIN_ERROR_PARITY_ERROR_SHIFT (3U) +#define LIN_ERROR_PARITY_ERROR_GET(x) (((uint32_t)(x) & LIN_ERROR_PARITY_ERROR_MASK) >> LIN_ERROR_PARITY_ERROR_SHIFT) + +/* + * TIMEOUT (RO) + * + * timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms + */ +#define LIN_ERROR_TIMEOUT_MASK (0x4U) +#define LIN_ERROR_TIMEOUT_SHIFT (2U) +#define LIN_ERROR_TIMEOUT_GET(x) (((uint32_t)(x) & LIN_ERROR_TIMEOUT_MASK) >> LIN_ERROR_TIMEOUT_SHIFT) + +/* + * CHK_ERROR (RO) + * + * checksum error + */ +#define LIN_ERROR_CHK_ERROR_MASK (0x2U) +#define LIN_ERROR_CHK_ERROR_SHIFT (1U) +#define LIN_ERROR_CHK_ERROR_GET(x) (((uint32_t)(x) & LIN_ERROR_CHK_ERROR_MASK) >> LIN_ERROR_CHK_ERROR_SHIFT) + +/* + * BIT_ERROR (RO) + * + * bit error + */ +#define LIN_ERROR_BIT_ERROR_MASK (0x1U) +#define LIN_ERROR_BIT_ERROR_SHIFT (0U) +#define LIN_ERROR_BIT_ERROR_GET(x) (((uint32_t)(x) & LIN_ERROR_BIT_ERROR_MASK) >> LIN_ERROR_BIT_ERROR_SHIFT) + +/* Bitfield definition for register: DATA_LEN */ +/* + * ENH_CHECK (RW) + * + * 1:enhence check mode + */ +#define LIN_DATA_LEN_ENH_CHECK_MASK (0x80U) +#define LIN_DATA_LEN_ENH_CHECK_SHIFT (7U) +#define LIN_DATA_LEN_ENH_CHECK_SET(x) (((uint32_t)(x) << LIN_DATA_LEN_ENH_CHECK_SHIFT) & LIN_DATA_LEN_ENH_CHECK_MASK) +#define LIN_DATA_LEN_ENH_CHECK_GET(x) (((uint32_t)(x) & LIN_DATA_LEN_ENH_CHECK_MASK) >> LIN_DATA_LEN_ENH_CHECK_SHIFT) + +/* + * DATA_LENGTH (RW) + * + * data length + */ +#define LIN_DATA_LEN_DATA_LENGTH_MASK (0xFU) +#define LIN_DATA_LEN_DATA_LENGTH_SHIFT (0U) +#define LIN_DATA_LEN_DATA_LENGTH_SET(x) (((uint32_t)(x) << LIN_DATA_LEN_DATA_LENGTH_SHIFT) & LIN_DATA_LEN_DATA_LENGTH_MASK) +#define LIN_DATA_LEN_DATA_LENGTH_GET(x) (((uint32_t)(x) & LIN_DATA_LEN_DATA_LENGTH_MASK) >> LIN_DATA_LEN_DATA_LENGTH_SHIFT) + +/* Bitfield definition for register: BAUDRATE_CTL_LOW */ +/* + * BT_DIV_LOW (RW) + * + * bit div register 7:0 + */ +#define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_MASK (0xFFU) +#define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SHIFT (0U) +#define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SET(x) (((uint32_t)(x) << LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SHIFT) & LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_MASK) +#define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_GET(x) (((uint32_t)(x) & LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_MASK) >> LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SHIFT) + +/* Bitfield definition for register: BARDRATE_CTL_HIGH */ +/* + * PRESCL (RW) + * + * prescl register + */ +#define LIN_BARDRATE_CTL_HIGH_PRESCL_MASK (0xC0U) +#define LIN_BARDRATE_CTL_HIGH_PRESCL_SHIFT (6U) +#define LIN_BARDRATE_CTL_HIGH_PRESCL_SET(x) (((uint32_t)(x) << LIN_BARDRATE_CTL_HIGH_PRESCL_SHIFT) & LIN_BARDRATE_CTL_HIGH_PRESCL_MASK) +#define LIN_BARDRATE_CTL_HIGH_PRESCL_GET(x) (((uint32_t)(x) & LIN_BARDRATE_CTL_HIGH_PRESCL_MASK) >> LIN_BARDRATE_CTL_HIGH_PRESCL_SHIFT) + +/* + * BT_MUL (RW) + * + * bt_mul register + */ +#define LIN_BARDRATE_CTL_HIGH_BT_MUL_MASK (0x3EU) +#define LIN_BARDRATE_CTL_HIGH_BT_MUL_SHIFT (1U) +#define LIN_BARDRATE_CTL_HIGH_BT_MUL_SET(x) (((uint32_t)(x) << LIN_BARDRATE_CTL_HIGH_BT_MUL_SHIFT) & LIN_BARDRATE_CTL_HIGH_BT_MUL_MASK) +#define LIN_BARDRATE_CTL_HIGH_BT_MUL_GET(x) (((uint32_t)(x) & LIN_BARDRATE_CTL_HIGH_BT_MUL_MASK) >> LIN_BARDRATE_CTL_HIGH_BT_MUL_SHIFT) + +/* + * BT_DIV_HIGH (RW) + * + * bit div register 8 + */ +#define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_MASK (0x1U) +#define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SHIFT (0U) +#define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SET(x) (((uint32_t)(x) << LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SHIFT) & LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_MASK) +#define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_GET(x) (((uint32_t)(x) & LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_MASK) >> LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SHIFT) + +/* Bitfield definition for register: ID */ +/* + * ID (RW) + * + * id register + */ +#define LIN_ID_ID_MASK (0x3FU) +#define LIN_ID_ID_SHIFT (0U) +#define LIN_ID_ID_SET(x) (((uint32_t)(x) << LIN_ID_ID_SHIFT) & LIN_ID_ID_MASK) +#define LIN_ID_ID_GET(x) (((uint32_t)(x) & LIN_ID_ID_MASK) >> LIN_ID_ID_SHIFT) + +/* Bitfield definition for register: TV */ +/* + * INITIAL_MODE (RW) + * + * initial_mode + */ +#define LIN_TV_INITIAL_MODE_MASK (0x80U) +#define LIN_TV_INITIAL_MODE_SHIFT (7U) +#define LIN_TV_INITIAL_MODE_SET(x) (((uint32_t)(x) << LIN_TV_INITIAL_MODE_SHIFT) & LIN_TV_INITIAL_MODE_MASK) +#define LIN_TV_INITIAL_MODE_GET(x) (((uint32_t)(x) & LIN_TV_INITIAL_MODE_MASK) >> LIN_TV_INITIAL_MODE_SHIFT) + +/* + * MASTER_MODE (RW) + * + * master_mode + */ +#define LIN_TV_MASTER_MODE_MASK (0x40U) +#define LIN_TV_MASTER_MODE_SHIFT (6U) +#define LIN_TV_MASTER_MODE_SET(x) (((uint32_t)(x) << LIN_TV_MASTER_MODE_SHIFT) & LIN_TV_MASTER_MODE_MASK) +#define LIN_TV_MASTER_MODE_GET(x) (((uint32_t)(x) & LIN_TV_MASTER_MODE_MASK) >> LIN_TV_MASTER_MODE_SHIFT) + +/* + * BUS_INACTIVITY_TIME (RW) + * + * slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s + */ +#define LIN_TV_BUS_INACTIVITY_TIME_MASK (0xCU) +#define LIN_TV_BUS_INACTIVITY_TIME_SHIFT (2U) +#define LIN_TV_BUS_INACTIVITY_TIME_SET(x) (((uint32_t)(x) << LIN_TV_BUS_INACTIVITY_TIME_SHIFT) & LIN_TV_BUS_INACTIVITY_TIME_MASK) +#define LIN_TV_BUS_INACTIVITY_TIME_GET(x) (((uint32_t)(x) & LIN_TV_BUS_INACTIVITY_TIME_MASK) >> LIN_TV_BUS_INACTIVITY_TIME_SHIFT) + +/* + * WUP_REPEAT_TIME (RW) + * + * slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms + */ +#define LIN_TV_WUP_REPEAT_TIME_MASK (0x3U) +#define LIN_TV_WUP_REPEAT_TIME_SHIFT (0U) +#define LIN_TV_WUP_REPEAT_TIME_SET(x) (((uint32_t)(x) << LIN_TV_WUP_REPEAT_TIME_SHIFT) & LIN_TV_WUP_REPEAT_TIME_MASK) +#define LIN_TV_WUP_REPEAT_TIME_GET(x) (((uint32_t)(x) & LIN_TV_WUP_REPEAT_TIME_MASK) >> LIN_TV_WUP_REPEAT_TIME_SHIFT) + + + +/* DATABYTE register group index macro definition */ +#define LIN_DATABYTE_DATA_BYTE0 (0UL) +#define LIN_DATABYTE_DATA_BYTE1 (1UL) +#define LIN_DATABYTE_DATA_BYTE2 (2UL) +#define LIN_DATABYTE_DATA_BYTE3 (3UL) +#define LIN_DATABYTE_DATA_BYTE4 (4UL) +#define LIN_DATABYTE_DATA_BYTE5 (5UL) +#define LIN_DATABYTE_DATA_BYTE6 (6UL) +#define LIN_DATABYTE_DATA_BYTE7 (7UL) + + +#endif /* HPM_LIN_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h new file mode 100644 index 00000000..8e3c48a2 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h @@ -0,0 +1,3583 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MCAN_H +#define HPM_MCAN_H + +typedef struct { + __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ + __R uint32_t ENDN; /* 0x4: endian register */ + __R uint8_t RESERVED1[4]; /* 0x8 - 0xB: Reserved */ + __RW uint32_t DBTP; /* 0xC: data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set */ + __RW uint32_t TEST; /* 0x10: test register */ + __RW uint32_t RWD; /* 0x14: ram watchdog */ + __RW uint32_t CCCR; /* 0x18: CC control register */ + __RW uint32_t NBTP; /* 0x1C: nominal bit timing and prescaler register */ + __RW uint32_t TSCC; /* 0x20: timestamp counter configuration */ + __R uint32_t TSCV; /* 0x24: timestamp counter value */ + __RW uint32_t TOCC; /* 0x28: timeout counter configuration */ + __R uint32_t TOCV; /* 0x2C: timeout counter value */ + __R uint8_t RESERVED2[16]; /* 0x30 - 0x3F: Reserved */ + __R uint32_t ECR; /* 0x40: error counter register */ + __R uint32_t PSR; /* 0x44: protocol status register */ + __RW uint32_t TDCR; /* 0x48: transmitter delay compensation */ + __R uint8_t RESERVED3[4]; /* 0x4C - 0x4F: Reserved */ + __RW uint32_t IR; /* 0x50: interrupt register */ + __RW uint32_t IE; /* 0x54: interrupt enable */ + __RW uint32_t ILS; /* 0x58: interrupt line select */ + __RW uint32_t ILE; /* 0x5C: interrupt line enable */ + __R uint8_t RESERVED4[32]; /* 0x60 - 0x7F: Reserved */ + __RW uint32_t GFC; /* 0x80: global filter configuration */ + __RW uint32_t SIDFC; /* 0x84: standard ID filter configuration */ + __RW uint32_t XIDFC; /* 0x88: extended ID filter configuration */ + __R uint8_t RESERVED5[4]; /* 0x8C - 0x8F: Reserved */ + __RW uint32_t XIDAM; /* 0x90: extended id and mask */ + __R uint32_t HPMS; /* 0x94: high priority message status */ + __RW uint32_t NDAT1; /* 0x98: new data1 */ + __RW uint32_t NDAT2; /* 0x9C: new data2 */ + __RW uint32_t RXF0C; /* 0xA0: rx fifo 0 configuration */ + __R uint32_t RXF0S; /* 0xA4: rx fifo 0 status */ + __RW uint32_t RXF0A; /* 0xA8: rx fifo0 acknowledge */ + __RW uint32_t RXBC; /* 0xAC: rx buffer configuration */ + __RW uint32_t RXF1C; /* 0xB0: rx fifo1 configuration */ + __R uint32_t RXF1S; /* 0xB4: rx fifo1 status */ + __RW uint32_t RXF1A; /* 0xB8: rx fifo 1 acknowledge */ + __RW uint32_t RXESC; /* 0xBC: rx buffer/fifo element size configuration */ + __RW uint32_t TXBC; /* 0xC0: tx buffer configuration */ + __R uint32_t TXFQS; /* 0xC4: tx fifo/queue status */ + __RW uint32_t TXESC; /* 0xC8: tx buffer element size configuration */ + __R uint32_t TXBRP; /* 0xCC: tx buffer request pending */ + __RW uint32_t TXBAR; /* 0xD0: tx buffer add request */ + __RW uint32_t TXBCR; /* 0xD4: tx buffer cancellation request */ + __R uint32_t TXBTO; /* 0xD8: tx buffer transmission occurred */ + __R uint32_t TXBCF; /* 0xDC: tx buffer cancellation finished */ + __RW uint32_t TXBTIE; /* 0xE0: tx buffer transmission interrupt enable */ + __RW uint32_t TXBCIE; /* 0xE4: tx buffer cancellation finished interrupt enable */ + __R uint8_t RESERVED6[8]; /* 0xE8 - 0xEF: Reserved */ + __RW uint32_t TXEFC; /* 0xF0: tx event fifo configuration */ + __R uint32_t TXEFS; /* 0xF4: tx event fifo status */ + __RW uint32_t TXEFA; /* 0xF8: tx event fifo acknowledge */ + __R uint8_t RESERVED7[260]; /* 0xFC - 0x1FF: Reserved */ + __R uint32_t TS_SEL[16]; /* 0x200 - 0x23C: timestamp 0-15 */ + __R uint32_t CREL; /* 0x240: core release register */ + __RW uint32_t TSCFG; /* 0x244: timestamp configuration */ + __R uint32_t TSS1; /* 0x248: timestamp status1 */ + __R uint32_t TSS2; /* 0x24C: timestamp status2 */ + __R uint32_t ATB; /* 0x250: actual timebase */ + __R uint32_t ATBH; /* 0x254: actual timebase high */ + __R uint8_t RESERVED8[424]; /* 0x258 - 0x3FF: Reserved */ + __RW uint32_t GLB_CTL; /* 0x400: global control */ + __R uint32_t GLB_STATUS; /* 0x404: global status */ + __R uint8_t RESERVED9[7160]; /* 0x408 - 0x1FFF: Reserved */ + __RW uint32_t MESSAGE_BUFF[640]; /* 0x2000 - 0x29FC: message buff */ +} MCAN_Type; + + +/* Bitfield definition for register: ENDN */ +/* + * EVT (R) + * + * Endianness Test Value + * The endianness test value is 0x87654321. + */ +#define MCAN_ENDN_EVT_MASK (0xFFFFFFFFUL) +#define MCAN_ENDN_EVT_SHIFT (0U) +#define MCAN_ENDN_EVT_GET(x) (((uint32_t)(x) & MCAN_ENDN_EVT_MASK) >> MCAN_ENDN_EVT_SHIFT) + +/* Bitfield definition for register: DBTP */ +/* + * TDC (RW) + * + * transmitter delay compensation enable + * 0= Transmitter Delay Compensation disabled + * 1= Transmitter Delay Compensation enabled + */ +#define MCAN_DBTP_TDC_MASK (0x800000UL) +#define MCAN_DBTP_TDC_SHIFT (23U) +#define MCAN_DBTP_TDC_SET(x) (((uint32_t)(x) << MCAN_DBTP_TDC_SHIFT) & MCAN_DBTP_TDC_MASK) +#define MCAN_DBTP_TDC_GET(x) (((uint32_t)(x) & MCAN_DBTP_TDC_MASK) >> MCAN_DBTP_TDC_SHIFT) + +/* + * DBRP (RW) + * + * Data Bit Rate Prescaler + * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + */ +#define MCAN_DBTP_DBRP_MASK (0x1F0000UL) +#define MCAN_DBTP_DBRP_SHIFT (16U) +#define MCAN_DBTP_DBRP_SET(x) (((uint32_t)(x) << MCAN_DBTP_DBRP_SHIFT) & MCAN_DBTP_DBRP_MASK) +#define MCAN_DBTP_DBRP_GET(x) (((uint32_t)(x) & MCAN_DBTP_DBRP_MASK) >> MCAN_DBTP_DBRP_SHIFT) + +/* + * DTSEG1 (RW) + * + * Data time segment before sample point + * Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + */ +#define MCAN_DBTP_DTSEG1_MASK (0x1F00U) +#define MCAN_DBTP_DTSEG1_SHIFT (8U) +#define MCAN_DBTP_DTSEG1_SET(x) (((uint32_t)(x) << MCAN_DBTP_DTSEG1_SHIFT) & MCAN_DBTP_DTSEG1_MASK) +#define MCAN_DBTP_DTSEG1_GET(x) (((uint32_t)(x) & MCAN_DBTP_DTSEG1_MASK) >> MCAN_DBTP_DTSEG1_SHIFT) + +/* + * DTSEG2 (RW) + * + * Data time segment after sample point + * Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + */ +#define MCAN_DBTP_DTSEG2_MASK (0xF0U) +#define MCAN_DBTP_DTSEG2_SHIFT (4U) +#define MCAN_DBTP_DTSEG2_SET(x) (((uint32_t)(x) << MCAN_DBTP_DTSEG2_SHIFT) & MCAN_DBTP_DTSEG2_MASK) +#define MCAN_DBTP_DTSEG2_GET(x) (((uint32_t)(x) & MCAN_DBTP_DTSEG2_MASK) >> MCAN_DBTP_DTSEG2_SHIFT) + +/* + * DSJW (RW) + * + * Data (Re)Synchronization Jump Width + * Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + */ +#define MCAN_DBTP_DSJW_MASK (0xFU) +#define MCAN_DBTP_DSJW_SHIFT (0U) +#define MCAN_DBTP_DSJW_SET(x) (((uint32_t)(x) << MCAN_DBTP_DSJW_SHIFT) & MCAN_DBTP_DSJW_MASK) +#define MCAN_DBTP_DSJW_GET(x) (((uint32_t)(x) & MCAN_DBTP_DSJW_MASK) >> MCAN_DBTP_DSJW_SHIFT) + +/* Bitfield definition for register: TEST */ +/* + * SVAL (R) + * + * Started Valid + * 0= Value of TXBNS not valid + * 1= Value of TXBNS valid + */ +#define MCAN_TEST_SVAL_MASK (0x200000UL) +#define MCAN_TEST_SVAL_SHIFT (21U) +#define MCAN_TEST_SVAL_GET(x) (((uint32_t)(x) & MCAN_TEST_SVAL_MASK) >> MCAN_TEST_SVAL_SHIFT) + +/* + * TXBNS (R) + * + * Tx Buffer Number Started + * Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. + */ +#define MCAN_TEST_TXBNS_MASK (0x1F0000UL) +#define MCAN_TEST_TXBNS_SHIFT (16U) +#define MCAN_TEST_TXBNS_GET(x) (((uint32_t)(x) & MCAN_TEST_TXBNS_MASK) >> MCAN_TEST_TXBNS_SHIFT) + +/* + * PVAL (R) + * + * Prepared Valid + * 0= Value of TXBNP not valid + * 1= Value of TXBNP valid + */ +#define MCAN_TEST_PVAL_MASK (0x2000U) +#define MCAN_TEST_PVAL_SHIFT (13U) +#define MCAN_TEST_PVAL_GET(x) (((uint32_t)(x) & MCAN_TEST_PVAL_MASK) >> MCAN_TEST_PVAL_SHIFT) + +/* + * TXBNP (R) + * + * Tx Buffer Number Prepared + * Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. + */ +#define MCAN_TEST_TXBNP_MASK (0x1F00U) +#define MCAN_TEST_TXBNP_SHIFT (8U) +#define MCAN_TEST_TXBNP_GET(x) (((uint32_t)(x) & MCAN_TEST_TXBNP_MASK) >> MCAN_TEST_TXBNP_SHIFT) + +/* + * RX (R) + * + * Receive Pin + * Monitors the actual value of pin m_can_rx + * 0= The CAN bus is dominant (m_can_rx = ‘0’) + * 1= The CAN bus is recessive (m_can_rx = ‘1’) + */ +#define MCAN_TEST_RX_MASK (0x80U) +#define MCAN_TEST_RX_SHIFT (7U) +#define MCAN_TEST_RX_GET(x) (((uint32_t)(x) & MCAN_TEST_RX_MASK) >> MCAN_TEST_RX_SHIFT) + +/* + * TX (RW) + * + * Control of Transmit Pin + * 00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time + * 01 Sample Point can be monitored at pin m_can_tx + * 10 Dominant (‘0’) level at pin m_can_tx + * 11 Recessive (‘1’) at pin m_can_tx + */ +#define MCAN_TEST_TX_MASK (0x60U) +#define MCAN_TEST_TX_SHIFT (5U) +#define MCAN_TEST_TX_SET(x) (((uint32_t)(x) << MCAN_TEST_TX_SHIFT) & MCAN_TEST_TX_MASK) +#define MCAN_TEST_TX_GET(x) (((uint32_t)(x) & MCAN_TEST_TX_MASK) >> MCAN_TEST_TX_SHIFT) + +/* + * LBCK (RW) + * + * Loop Back Mode + * 0= Reset value, Loop Back Mode is disabled + * 1= Loop Back Mode is enabled + */ +#define MCAN_TEST_LBCK_MASK (0x10U) +#define MCAN_TEST_LBCK_SHIFT (4U) +#define MCAN_TEST_LBCK_SET(x) (((uint32_t)(x) << MCAN_TEST_LBCK_SHIFT) & MCAN_TEST_LBCK_MASK) +#define MCAN_TEST_LBCK_GET(x) (((uint32_t)(x) & MCAN_TEST_LBCK_MASK) >> MCAN_TEST_LBCK_SHIFT) + +/* Bitfield definition for register: RWD */ +/* + * WDV (R) + * + * Watchdog Value + * Actual Message RAM Watchdog Counter Value. + */ +#define MCAN_RWD_WDV_MASK (0xFF00U) +#define MCAN_RWD_WDV_SHIFT (8U) +#define MCAN_RWD_WDV_GET(x) (((uint32_t)(x) & MCAN_RWD_WDV_MASK) >> MCAN_RWD_WDV_SHIFT) + +/* + * WDC (RW) + * + * Watchdog Configuration + * Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. + */ +#define MCAN_RWD_WDC_MASK (0xFFU) +#define MCAN_RWD_WDC_SHIFT (0U) +#define MCAN_RWD_WDC_SET(x) (((uint32_t)(x) << MCAN_RWD_WDC_SHIFT) & MCAN_RWD_WDC_MASK) +#define MCAN_RWD_WDC_GET(x) (((uint32_t)(x) & MCAN_RWD_WDC_MASK) >> MCAN_RWD_WDC_SHIFT) + +/* Bitfield definition for register: CCCR */ +/* + * NISO (RW) + * + * Non ISO Operation + * If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD + * Specification V1.0. + * 0= CAN FD frame format according to ISO 11898-1:2015 + * 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 + * Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. + */ +#define MCAN_CCCR_NISO_MASK (0x8000U) +#define MCAN_CCCR_NISO_SHIFT (15U) +#define MCAN_CCCR_NISO_SET(x) (((uint32_t)(x) << MCAN_CCCR_NISO_SHIFT) & MCAN_CCCR_NISO_MASK) +#define MCAN_CCCR_NISO_GET(x) (((uint32_t)(x) & MCAN_CCCR_NISO_MASK) >> MCAN_CCCR_NISO_SHIFT) + +/* + * TXP (RW) + * + * Transmit Pause + * If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after + * itself has successfully transmitted a frame (see Section 3.5). + * 0= Transmit pause disabled + * 1= Transmit pause enabled + */ +#define MCAN_CCCR_TXP_MASK (0x4000U) +#define MCAN_CCCR_TXP_SHIFT (14U) +#define MCAN_CCCR_TXP_SET(x) (((uint32_t)(x) << MCAN_CCCR_TXP_SHIFT) & MCAN_CCCR_TXP_MASK) +#define MCAN_CCCR_TXP_GET(x) (((uint32_t)(x) & MCAN_CCCR_TXP_MASK) >> MCAN_CCCR_TXP_SHIFT) + +/* + * EFBI (RW) + * + * Edge Filtering during Bus Integration + * 0= Edge filtering disabled + * 1= Two consecutive dominant tq required to detect an edge for hard synchronization + */ +#define MCAN_CCCR_EFBI_MASK (0x2000U) +#define MCAN_CCCR_EFBI_SHIFT (13U) +#define MCAN_CCCR_EFBI_SET(x) (((uint32_t)(x) << MCAN_CCCR_EFBI_SHIFT) & MCAN_CCCR_EFBI_MASK) +#define MCAN_CCCR_EFBI_GET(x) (((uint32_t)(x) & MCAN_CCCR_EFBI_MASK) >> MCAN_CCCR_EFBI_SHIFT) + +/* + * PXHD (RW) + * + * Protocol Exception Handling Disable + * 0= Protocol exception handling enabled + * 1= Protocol exception handling disabled + * Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. + */ +#define MCAN_CCCR_PXHD_MASK (0x1000U) +#define MCAN_CCCR_PXHD_SHIFT (12U) +#define MCAN_CCCR_PXHD_SET(x) (((uint32_t)(x) << MCAN_CCCR_PXHD_SHIFT) & MCAN_CCCR_PXHD_MASK) +#define MCAN_CCCR_PXHD_GET(x) (((uint32_t)(x) & MCAN_CCCR_PXHD_MASK) >> MCAN_CCCR_PXHD_SHIFT) + +/* + * WMM (RW) + * + * Wide Message Marker + * Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. + * 0= 8-bit Message Marker used + * 1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO + */ +#define MCAN_CCCR_WMM_MASK (0x800U) +#define MCAN_CCCR_WMM_SHIFT (11U) +#define MCAN_CCCR_WMM_SET(x) (((uint32_t)(x) << MCAN_CCCR_WMM_SHIFT) & MCAN_CCCR_WMM_MASK) +#define MCAN_CCCR_WMM_GET(x) (((uint32_t)(x) & MCAN_CCCR_WMM_MASK) >> MCAN_CCCR_WMM_SHIFT) + +/* + * UTSU (RW) + * + * Use Timestamping Unit + * When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. + * 0= Internal time stamping + * 1= External time stamping by TSU + * Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. + * In this case bit UTSU is fixed to zero by synthesis. + */ +#define MCAN_CCCR_UTSU_MASK (0x400U) +#define MCAN_CCCR_UTSU_SHIFT (10U) +#define MCAN_CCCR_UTSU_SET(x) (((uint32_t)(x) << MCAN_CCCR_UTSU_SHIFT) & MCAN_CCCR_UTSU_MASK) +#define MCAN_CCCR_UTSU_GET(x) (((uint32_t)(x) & MCAN_CCCR_UTSU_MASK) >> MCAN_CCCR_UTSU_SHIFT) + +/* + * BRSE (RW) + * + * Bit Rate Switch Enable + * 0= Bit rate switching for transmissions disabled + * 1= Bit rate switching for transmissions enabled + * Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. + */ +#define MCAN_CCCR_BRSE_MASK (0x200U) +#define MCAN_CCCR_BRSE_SHIFT (9U) +#define MCAN_CCCR_BRSE_SET(x) (((uint32_t)(x) << MCAN_CCCR_BRSE_SHIFT) & MCAN_CCCR_BRSE_MASK) +#define MCAN_CCCR_BRSE_GET(x) (((uint32_t)(x) & MCAN_CCCR_BRSE_MASK) >> MCAN_CCCR_BRSE_SHIFT) + +/* + * FDOE (RW) + * + * FD Operation Enable + * 0= FD operation disabled + * 1= FD operation enabled + */ +#define MCAN_CCCR_FDOE_MASK (0x100U) +#define MCAN_CCCR_FDOE_SHIFT (8U) +#define MCAN_CCCR_FDOE_SET(x) (((uint32_t)(x) << MCAN_CCCR_FDOE_SHIFT) & MCAN_CCCR_FDOE_MASK) +#define MCAN_CCCR_FDOE_GET(x) (((uint32_t)(x) & MCAN_CCCR_FDOE_MASK) >> MCAN_CCCR_FDOE_SHIFT) + +/* + * TEST (RW) + * + * Test Mode Enable + * 0= Normal operation, register TEST holds reset values + * 1= Test Mode, write access to register TEST enabled + */ +#define MCAN_CCCR_TEST_MASK (0x80U) +#define MCAN_CCCR_TEST_SHIFT (7U) +#define MCAN_CCCR_TEST_SET(x) (((uint32_t)(x) << MCAN_CCCR_TEST_SHIFT) & MCAN_CCCR_TEST_MASK) +#define MCAN_CCCR_TEST_GET(x) (((uint32_t)(x) & MCAN_CCCR_TEST_MASK) >> MCAN_CCCR_TEST_SHIFT) + +/* + * DAR (RW) + * + * Disable Automatic Retransmission + * 0= Automatic retransmission of messages not transmitted successfully enabled + * 1= Automatic retransmission disabled + */ +#define MCAN_CCCR_DAR_MASK (0x40U) +#define MCAN_CCCR_DAR_SHIFT (6U) +#define MCAN_CCCR_DAR_SET(x) (((uint32_t)(x) << MCAN_CCCR_DAR_SHIFT) & MCAN_CCCR_DAR_MASK) +#define MCAN_CCCR_DAR_GET(x) (((uint32_t)(x) & MCAN_CCCR_DAR_MASK) >> MCAN_CCCR_DAR_SHIFT) + +/* + * MON (RW) + * + * Bus Monitoring Mode + * Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. + * 0= Bus Monitoring Mode is disabled + * 1= Bus Monitoring Mode is enabled + */ +#define MCAN_CCCR_MON_MASK (0x20U) +#define MCAN_CCCR_MON_SHIFT (5U) +#define MCAN_CCCR_MON_SET(x) (((uint32_t)(x) << MCAN_CCCR_MON_SHIFT) & MCAN_CCCR_MON_MASK) +#define MCAN_CCCR_MON_GET(x) (((uint32_t)(x) & MCAN_CCCR_MON_MASK) >> MCAN_CCCR_MON_SHIFT) + +/* + * CSR (RW) + * + * Clock Stop Request + * 0= No clock stop is requested + * 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. + */ +#define MCAN_CCCR_CSR_MASK (0x10U) +#define MCAN_CCCR_CSR_SHIFT (4U) +#define MCAN_CCCR_CSR_SET(x) (((uint32_t)(x) << MCAN_CCCR_CSR_SHIFT) & MCAN_CCCR_CSR_MASK) +#define MCAN_CCCR_CSR_GET(x) (((uint32_t)(x) & MCAN_CCCR_CSR_MASK) >> MCAN_CCCR_CSR_SHIFT) + +/* + * CSA (R) + * + * Clock Stop Acknowledge + * 0= No clock stop acknowledged + * 1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk + */ +#define MCAN_CCCR_CSA_MASK (0x8U) +#define MCAN_CCCR_CSA_SHIFT (3U) +#define MCAN_CCCR_CSA_GET(x) (((uint32_t)(x) & MCAN_CCCR_CSA_MASK) >> MCAN_CCCR_CSA_SHIFT) + +/* + * ASM (RW) + * + * Restricted Operation Mode + * Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. + * 0= Normal CAN operation + * 1= Restricted Operation Mode active + */ +#define MCAN_CCCR_ASM_MASK (0x4U) +#define MCAN_CCCR_ASM_SHIFT (2U) +#define MCAN_CCCR_ASM_SET(x) (((uint32_t)(x) << MCAN_CCCR_ASM_SHIFT) & MCAN_CCCR_ASM_MASK) +#define MCAN_CCCR_ASM_GET(x) (((uint32_t)(x) & MCAN_CCCR_ASM_MASK) >> MCAN_CCCR_ASM_SHIFT) + +/* + * CCE (RW) + * + * Configuration Change Enable + * 0= The CPU has no write access to the protected configuration registers + * 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) + */ +#define MCAN_CCCR_CCE_MASK (0x2U) +#define MCAN_CCCR_CCE_SHIFT (1U) +#define MCAN_CCCR_CCE_SET(x) (((uint32_t)(x) << MCAN_CCCR_CCE_SHIFT) & MCAN_CCCR_CCE_MASK) +#define MCAN_CCCR_CCE_GET(x) (((uint32_t)(x) & MCAN_CCCR_CCE_MASK) >> MCAN_CCCR_CCE_SHIFT) + +/* + * INIT (RW) + * + * Initialization + * 0= Normal Operation + * 1= Initialization is started + */ +#define MCAN_CCCR_INIT_MASK (0x1U) +#define MCAN_CCCR_INIT_SHIFT (0U) +#define MCAN_CCCR_INIT_SET(x) (((uint32_t)(x) << MCAN_CCCR_INIT_SHIFT) & MCAN_CCCR_INIT_MASK) +#define MCAN_CCCR_INIT_GET(x) (((uint32_t)(x) & MCAN_CCCR_INIT_MASK) >> MCAN_CCCR_INIT_SHIFT) + +/* Bitfield definition for register: NBTP */ +/* + * NSJW (RW) + * + * Nominal (Re)Synchronization Jump Width + * Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + */ +#define MCAN_NBTP_NSJW_MASK (0xFE000000UL) +#define MCAN_NBTP_NSJW_SHIFT (25U) +#define MCAN_NBTP_NSJW_SET(x) (((uint32_t)(x) << MCAN_NBTP_NSJW_SHIFT) & MCAN_NBTP_NSJW_MASK) +#define MCAN_NBTP_NSJW_GET(x) (((uint32_t)(x) & MCAN_NBTP_NSJW_MASK) >> MCAN_NBTP_NSJW_SHIFT) + +/* + * NBRP (RW) + * + * Nominal Bit Rate Prescaler + * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is + * such that one more than the value programmed here is used. + */ +#define MCAN_NBTP_NBRP_MASK (0x1FF0000UL) +#define MCAN_NBTP_NBRP_SHIFT (16U) +#define MCAN_NBTP_NBRP_SET(x) (((uint32_t)(x) << MCAN_NBTP_NBRP_SHIFT) & MCAN_NBTP_NBRP_MASK) +#define MCAN_NBTP_NBRP_GET(x) (((uint32_t)(x) & MCAN_NBTP_NBRP_MASK) >> MCAN_NBTP_NBRP_SHIFT) + +/* + * NTSEG1 (RW) + * + * Nominal Time segment before sample point + * Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + */ +#define MCAN_NBTP_NTSEG1_MASK (0xFF00U) +#define MCAN_NBTP_NTSEG1_SHIFT (8U) +#define MCAN_NBTP_NTSEG1_SET(x) (((uint32_t)(x) << MCAN_NBTP_NTSEG1_SHIFT) & MCAN_NBTP_NTSEG1_MASK) +#define MCAN_NBTP_NTSEG1_GET(x) (((uint32_t)(x) & MCAN_NBTP_NTSEG1_MASK) >> MCAN_NBTP_NTSEG1_SHIFT) + +/* + * NTSEG2 (RW) + * + * Nominal Time segment after sample point + * Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + */ +#define MCAN_NBTP_NTSEG2_MASK (0x7FU) +#define MCAN_NBTP_NTSEG2_SHIFT (0U) +#define MCAN_NBTP_NTSEG2_SET(x) (((uint32_t)(x) << MCAN_NBTP_NTSEG2_SHIFT) & MCAN_NBTP_NTSEG2_MASK) +#define MCAN_NBTP_NTSEG2_GET(x) (((uint32_t)(x) & MCAN_NBTP_NTSEG2_MASK) >> MCAN_NBTP_NTSEG2_SHIFT) + +/* Bitfield definition for register: TSCC */ +/* + * TCP (RW) + * + * Timestamp Counter Prescaler + * Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + */ +#define MCAN_TSCC_TCP_MASK (0xF0000UL) +#define MCAN_TSCC_TCP_SHIFT (16U) +#define MCAN_TSCC_TCP_SET(x) (((uint32_t)(x) << MCAN_TSCC_TCP_SHIFT) & MCAN_TSCC_TCP_MASK) +#define MCAN_TSCC_TCP_GET(x) (((uint32_t)(x) & MCAN_TSCC_TCP_MASK) >> MCAN_TSCC_TCP_SHIFT) + +/* + * TSS (RW) + * + * timestamp Select + * 00= Timestamp counter value always 0x0000 + * 01= Timestamp counter value incremented according to TCP + * 10= External timestamp counter value used + * 11= Same as “00” + */ +#define MCAN_TSCC_TSS_MASK (0x3U) +#define MCAN_TSCC_TSS_SHIFT (0U) +#define MCAN_TSCC_TSS_SET(x) (((uint32_t)(x) << MCAN_TSCC_TSS_SHIFT) & MCAN_TSCC_TSS_MASK) +#define MCAN_TSCC_TSS_GET(x) (((uint32_t)(x) & MCAN_TSCC_TSS_MASK) >> MCAN_TSCC_TSS_SHIFT) + +/* Bitfield definition for register: TSCV */ +/* + * TSC (RC) + * + * Timestamp Counter + * The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. + */ +#define MCAN_TSCV_TSC_MASK (0xFFFFU) +#define MCAN_TSCV_TSC_SHIFT (0U) +#define MCAN_TSCV_TSC_GET(x) (((uint32_t)(x) & MCAN_TSCV_TSC_MASK) >> MCAN_TSCV_TSC_SHIFT) + +/* Bitfield definition for register: TOCC */ +/* + * TOP (RW) + * + * Timeout Period + * Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + */ +#define MCAN_TOCC_TOP_MASK (0xFFFF0000UL) +#define MCAN_TOCC_TOP_SHIFT (16U) +#define MCAN_TOCC_TOP_SET(x) (((uint32_t)(x) << MCAN_TOCC_TOP_SHIFT) & MCAN_TOCC_TOP_MASK) +#define MCAN_TOCC_TOP_GET(x) (((uint32_t)(x) & MCAN_TOCC_TOP_MASK) >> MCAN_TOCC_TOP_SHIFT) + +/* + * TOS (RW) + * + * Timeout Select + * When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. + * 00= Continuous operation + * 01= Timeout controlled by Tx Event FIFO + * 10= Timeout controlled by Rx FIFO 0 + * 11= Timeout controlled by Rx FIFO 1 + */ +#define MCAN_TOCC_TOS_MASK (0x6U) +#define MCAN_TOCC_TOS_SHIFT (1U) +#define MCAN_TOCC_TOS_SET(x) (((uint32_t)(x) << MCAN_TOCC_TOS_SHIFT) & MCAN_TOCC_TOS_MASK) +#define MCAN_TOCC_TOS_GET(x) (((uint32_t)(x) & MCAN_TOCC_TOS_MASK) >> MCAN_TOCC_TOS_SHIFT) + +/* + * RP (RW) + * + * Enable Timeout Counter + * 0= Timeout Counter disabled + * 1= Timeout Counter enabled + */ +#define MCAN_TOCC_RP_MASK (0x1U) +#define MCAN_TOCC_RP_SHIFT (0U) +#define MCAN_TOCC_RP_SET(x) (((uint32_t)(x) << MCAN_TOCC_RP_SHIFT) & MCAN_TOCC_RP_MASK) +#define MCAN_TOCC_RP_GET(x) (((uint32_t)(x) & MCAN_TOCC_RP_MASK) >> MCAN_TOCC_RP_SHIFT) + +/* Bitfield definition for register: TOCV */ +/* + * TOC (RC) + * + * Timeout Counter + * The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. + * Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. + */ +#define MCAN_TOCV_TOC_MASK (0xFFFFU) +#define MCAN_TOCV_TOC_SHIFT (0U) +#define MCAN_TOCV_TOC_GET(x) (((uint32_t)(x) & MCAN_TOCV_TOC_MASK) >> MCAN_TOCV_TOC_SHIFT) + +/* Bitfield definition for register: ECR */ +/* + * CEL (X) + * + * CAN Error Logging + * The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. + * The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. + * Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. + */ +#define MCAN_ECR_CEL_MASK (0xFF0000UL) +#define MCAN_ECR_CEL_SHIFT (16U) +#define MCAN_ECR_CEL_GET(x) (((uint32_t)(x) & MCAN_ECR_CEL_MASK) >> MCAN_ECR_CEL_SHIFT) + +/* + * RP (R) + * + * Receive Error Passive + * 0= The Receive Error Counter is below the error passive level of 128 + * 1= The Receive Error Counter has reached the error passive level of 128 + */ +#define MCAN_ECR_RP_MASK (0x8000U) +#define MCAN_ECR_RP_SHIFT (15U) +#define MCAN_ECR_RP_GET(x) (((uint32_t)(x) & MCAN_ECR_RP_MASK) >> MCAN_ECR_RP_SHIFT) + +/* + * REC (R) + * + * Receive Error Counter + * Actual state of the Receive Error Counter, values between 0 and 127 + */ +#define MCAN_ECR_REC_MASK (0x7F00U) +#define MCAN_ECR_REC_SHIFT (8U) +#define MCAN_ECR_REC_GET(x) (((uint32_t)(x) & MCAN_ECR_REC_MASK) >> MCAN_ECR_REC_SHIFT) + +/* + * TEC (R) + * + * Transmit Error Counter + * Actual state of the Transmit Error Counter, values between 0 and 255 + * Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. + */ +#define MCAN_ECR_TEC_MASK (0xFFU) +#define MCAN_ECR_TEC_SHIFT (0U) +#define MCAN_ECR_TEC_GET(x) (((uint32_t)(x) & MCAN_ECR_TEC_MASK) >> MCAN_ECR_TEC_SHIFT) + +/* Bitfield definition for register: PSR */ +/* + * TDCV (R) + * + * Transmitter Delay Compensation Value + * Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + */ +#define MCAN_PSR_TDCV_MASK (0x7F0000UL) +#define MCAN_PSR_TDCV_SHIFT (16U) +#define MCAN_PSR_TDCV_GET(x) (((uint32_t)(x) & MCAN_PSR_TDCV_MASK) >> MCAN_PSR_TDCV_SHIFT) + +/* + * PXE (X) + * + * Protocol Exception Event + * 0= No protocol exception event occurred since last read access + * 1= Protocol exception event occurred + * Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. + */ +#define MCAN_PSR_PXE_MASK (0x4000U) +#define MCAN_PSR_PXE_SHIFT (14U) +#define MCAN_PSR_PXE_GET(x) (((uint32_t)(x) & MCAN_PSR_PXE_MASK) >> MCAN_PSR_PXE_SHIFT) + +/* + * RFDF (X) + * + * Received a CAN FD Message + * This bit is set independent of acceptance filtering. + * 0= Since this bit was reset by the CPU, no CAN FD message has been received + * 1= Message in CAN FD format with FDF flag set has been received + * Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. + */ +#define MCAN_PSR_RFDF_MASK (0x2000U) +#define MCAN_PSR_RFDF_SHIFT (13U) +#define MCAN_PSR_RFDF_GET(x) (((uint32_t)(x) & MCAN_PSR_RFDF_MASK) >> MCAN_PSR_RFDF_SHIFT) + +/* + * RBRS (X) + * + * BRS flag of last received CAN FD Message + * This bit is set together with RFDF, independent of acceptance filtering. + * 0= Last received CAN FD message did not have its BRS flag set + * 1= Last received CAN FD message had its BRS flag set + * Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. + */ +#define MCAN_PSR_RBRS_MASK (0x1000U) +#define MCAN_PSR_RBRS_SHIFT (12U) +#define MCAN_PSR_RBRS_GET(x) (((uint32_t)(x) & MCAN_PSR_RBRS_MASK) >> MCAN_PSR_RBRS_SHIFT) + +/* + * RESI (X) + * + * ESI flag of last received CAN FD Message + * This bit is set together with RFDF, independent of acceptance filtering. + * 0= Last received CAN FD message did not have its ESI flag set + * 1= Last received CAN FD message had its ESI flag set + * Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. + */ +#define MCAN_PSR_RESI_MASK (0x800U) +#define MCAN_PSR_RESI_SHIFT (11U) +#define MCAN_PSR_RESI_GET(x) (((uint32_t)(x) & MCAN_PSR_RESI_MASK) >> MCAN_PSR_RESI_SHIFT) + +/* + * DLEC (S) + * + * Data Phase Last Error Code + * Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with + * its BRS flag set has been transferred (reception or transmission) without error. + * Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. + */ +#define MCAN_PSR_DLEC_MASK (0x700U) +#define MCAN_PSR_DLEC_SHIFT (8U) +#define MCAN_PSR_DLEC_GET(x) (((uint32_t)(x) & MCAN_PSR_DLEC_MASK) >> MCAN_PSR_DLEC_SHIFT) + +/* + * BO (R) + * + * Bus_Off Status + * 0= The M_CAN is not Bus_Off + * 1= The M_CAN is in Bus_Off state + */ +#define MCAN_PSR_BO_MASK (0x80U) +#define MCAN_PSR_BO_SHIFT (7U) +#define MCAN_PSR_BO_GET(x) (((uint32_t)(x) & MCAN_PSR_BO_MASK) >> MCAN_PSR_BO_SHIFT) + +/* + * EW (R) + * + * Warning Status + * 0= Both error counters are below the Error_Warning limit of 96 + * 1= At least one of error counter has reached the Error_Warning limit of 96 + */ +#define MCAN_PSR_EW_MASK (0x40U) +#define MCAN_PSR_EW_SHIFT (6U) +#define MCAN_PSR_EW_GET(x) (((uint32_t)(x) & MCAN_PSR_EW_MASK) >> MCAN_PSR_EW_SHIFT) + +/* + * EP (R) + * + * Error Passive + * 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected + * 1= The M_CAN is in the Error_Passive state + */ +#define MCAN_PSR_EP_MASK (0x20U) +#define MCAN_PSR_EP_SHIFT (5U) +#define MCAN_PSR_EP_GET(x) (((uint32_t)(x) & MCAN_PSR_EP_MASK) >> MCAN_PSR_EP_SHIFT) + +/* + * ACT (R) + * + * Activity + * Monitors the module’s CAN communication state. + * 00= Synchronizing - node is synchronizing on CAN communication + * 01= Idle - node is neither receiver nor transmitter + * 10= Receiver - node is operating as receiver + * 11= Transmitter - node is operating as transmitter + * Note: ACT is set to “00” by a Protocol Exception Event. + */ +#define MCAN_PSR_ACT_MASK (0x18U) +#define MCAN_PSR_ACT_SHIFT (3U) +#define MCAN_PSR_ACT_GET(x) (((uint32_t)(x) & MCAN_PSR_ACT_MASK) >> MCAN_PSR_ACT_SHIFT) + +/* + * LEC (S) + * + * Last Error Code + * The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. + * 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. + * 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. + * 2= Form Error: A fixed format part of a received frame has the wrong format. + * 3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. + * 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), + * the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus + * value was dominant. + * 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at + * dominant or continuously disturbed). + * 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. + * 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. + * Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. + * Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. + * Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. + */ +#define MCAN_PSR_LEC_MASK (0x7U) +#define MCAN_PSR_LEC_SHIFT (0U) +#define MCAN_PSR_LEC_GET(x) (((uint32_t)(x) & MCAN_PSR_LEC_MASK) >> MCAN_PSR_LEC_SHIFT) + +/* Bitfield definition for register: TDCR */ +/* + * TDCO (RW) + * + * Transmitter Delay Compensation SSP Offset + * Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. + */ +#define MCAN_TDCR_TDCO_MASK (0x7F00U) +#define MCAN_TDCR_TDCO_SHIFT (8U) +#define MCAN_TDCR_TDCO_SET(x) (((uint32_t)(x) << MCAN_TDCR_TDCO_SHIFT) & MCAN_TDCR_TDCO_MASK) +#define MCAN_TDCR_TDCO_GET(x) (((uint32_t)(x) & MCAN_TDCR_TDCO_MASK) >> MCAN_TDCR_TDCO_SHIFT) + +/* + * TDCF (RW) + * + * Transmitter Delay Compensation Filter Window Length + * Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. + */ +#define MCAN_TDCR_TDCF_MASK (0x7FU) +#define MCAN_TDCR_TDCF_SHIFT (0U) +#define MCAN_TDCR_TDCF_SET(x) (((uint32_t)(x) << MCAN_TDCR_TDCF_SHIFT) & MCAN_TDCR_TDCF_MASK) +#define MCAN_TDCR_TDCF_GET(x) (((uint32_t)(x) & MCAN_TDCR_TDCF_MASK) >> MCAN_TDCR_TDCF_SHIFT) + +/* Bitfield definition for register: IR */ +/* + * ARA (RW) + * + * Access to Reserved Address + * 0= No access to reserved address occurred + * 1= Access to reserved address occurred + */ +#define MCAN_IR_ARA_MASK (0x20000000UL) +#define MCAN_IR_ARA_SHIFT (29U) +#define MCAN_IR_ARA_SET(x) (((uint32_t)(x) << MCAN_IR_ARA_SHIFT) & MCAN_IR_ARA_MASK) +#define MCAN_IR_ARA_GET(x) (((uint32_t)(x) & MCAN_IR_ARA_MASK) >> MCAN_IR_ARA_SHIFT) + +/* + * PED (RW) + * + * Protocol Error in Data Phase (Data Bit Time is used) + * 0= No protocol error in data phase + * 1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) + */ +#define MCAN_IR_PED_MASK (0x10000000UL) +#define MCAN_IR_PED_SHIFT (28U) +#define MCAN_IR_PED_SET(x) (((uint32_t)(x) << MCAN_IR_PED_SHIFT) & MCAN_IR_PED_MASK) +#define MCAN_IR_PED_GET(x) (((uint32_t)(x) & MCAN_IR_PED_MASK) >> MCAN_IR_PED_SHIFT) + +/* + * PEA (RW) + * + * Protocol Error in Arbitration Phase (Nominal Bit Time is used) + * 0= No protocol error in arbitration phase + * 1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) + */ +#define MCAN_IR_PEA_MASK (0x8000000UL) +#define MCAN_IR_PEA_SHIFT (27U) +#define MCAN_IR_PEA_SET(x) (((uint32_t)(x) << MCAN_IR_PEA_SHIFT) & MCAN_IR_PEA_MASK) +#define MCAN_IR_PEA_GET(x) (((uint32_t)(x) & MCAN_IR_PEA_MASK) >> MCAN_IR_PEA_SHIFT) + +/* + * WDI (RW) + * + * Watchdog Interrupt + * 0= No Message RAM Watchdog event occurred + * 1= Message RAM Watchdog event due to missing READY + */ +#define MCAN_IR_WDI_MASK (0x4000000UL) +#define MCAN_IR_WDI_SHIFT (26U) +#define MCAN_IR_WDI_SET(x) (((uint32_t)(x) << MCAN_IR_WDI_SHIFT) & MCAN_IR_WDI_MASK) +#define MCAN_IR_WDI_GET(x) (((uint32_t)(x) & MCAN_IR_WDI_MASK) >> MCAN_IR_WDI_SHIFT) + +/* + * BO (RW) + * + * Bus_Off Status + * 0= Bus_Off status unchanged + * 1= Bus_Off status changed + */ +#define MCAN_IR_BO_MASK (0x2000000UL) +#define MCAN_IR_BO_SHIFT (25U) +#define MCAN_IR_BO_SET(x) (((uint32_t)(x) << MCAN_IR_BO_SHIFT) & MCAN_IR_BO_MASK) +#define MCAN_IR_BO_GET(x) (((uint32_t)(x) & MCAN_IR_BO_MASK) >> MCAN_IR_BO_SHIFT) + +/* + * EW (RW) + * + * Warning Status + * 0= Error_Warning status unchanged + * 1= Error_Warning status changed + */ +#define MCAN_IR_EW_MASK (0x1000000UL) +#define MCAN_IR_EW_SHIFT (24U) +#define MCAN_IR_EW_SET(x) (((uint32_t)(x) << MCAN_IR_EW_SHIFT) & MCAN_IR_EW_MASK) +#define MCAN_IR_EW_GET(x) (((uint32_t)(x) & MCAN_IR_EW_MASK) >> MCAN_IR_EW_SHIFT) + +/* + * EP (RW) + * + * Error Passive + * 0= Error_Passive status unchanged + * 1= Error_Passive status changed + */ +#define MCAN_IR_EP_MASK (0x800000UL) +#define MCAN_IR_EP_SHIFT (23U) +#define MCAN_IR_EP_SET(x) (((uint32_t)(x) << MCAN_IR_EP_SHIFT) & MCAN_IR_EP_MASK) +#define MCAN_IR_EP_GET(x) (((uint32_t)(x) & MCAN_IR_EP_MASK) >> MCAN_IR_EP_SHIFT) + +/* + * ELO (RW) + * + * Error Logging Overflow + * 0= CAN Error Logging Counter did not overflow + * 1= Overflow of CAN Error Logging Counter occurred + */ +#define MCAN_IR_ELO_MASK (0x400000UL) +#define MCAN_IR_ELO_SHIFT (22U) +#define MCAN_IR_ELO_SET(x) (((uint32_t)(x) << MCAN_IR_ELO_SHIFT) & MCAN_IR_ELO_MASK) +#define MCAN_IR_ELO_GET(x) (((uint32_t)(x) & MCAN_IR_ELO_MASK) >> MCAN_IR_ELO_SHIFT) + +/* + * BEU (RW) + * + * Bit Error Uncorrected + * Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. + * 0= No bit error detected when reading from Message RAM + * 1= Bit error detected, uncorrected (e.g. parity logic) + */ +#define MCAN_IR_BEU_MASK (0x200000UL) +#define MCAN_IR_BEU_SHIFT (21U) +#define MCAN_IR_BEU_SET(x) (((uint32_t)(x) << MCAN_IR_BEU_SHIFT) & MCAN_IR_BEU_MASK) +#define MCAN_IR_BEU_GET(x) (((uint32_t)(x) & MCAN_IR_BEU_MASK) >> MCAN_IR_BEU_SHIFT) + +/* + * BEC (RW) + * + * Bit Error Corrected + * Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. + * 0= No bit error detected when reading from Message RAM + * 1= Bit error detected and corrected (e.g. ECC) + */ +#define MCAN_IR_BEC_MASK (0x100000UL) +#define MCAN_IR_BEC_SHIFT (20U) +#define MCAN_IR_BEC_SET(x) (((uint32_t)(x) << MCAN_IR_BEC_SHIFT) & MCAN_IR_BEC_MASK) +#define MCAN_IR_BEC_GET(x) (((uint32_t)(x) & MCAN_IR_BEC_MASK) >> MCAN_IR_BEC_SHIFT) + +/* + * DRX (RW) + * + * Message stored to Dedicated Rx Buffer + * The flag is set whenever a received message has been stored into a dedicated Rx Buffer. + * 0= No Rx Buffer updated + * 1= At least one received message stored into an Rx Buffer + */ +#define MCAN_IR_DRX_MASK (0x80000UL) +#define MCAN_IR_DRX_SHIFT (19U) +#define MCAN_IR_DRX_SET(x) (((uint32_t)(x) << MCAN_IR_DRX_SHIFT) & MCAN_IR_DRX_MASK) +#define MCAN_IR_DRX_GET(x) (((uint32_t)(x) & MCAN_IR_DRX_MASK) >> MCAN_IR_DRX_SHIFT) + +/* + * TOO (RW) + * + * Timeout Occurred + * 0= No timeout + * 1= Timeout reached + */ +#define MCAN_IR_TOO_MASK (0x40000UL) +#define MCAN_IR_TOO_SHIFT (18U) +#define MCAN_IR_TOO_SET(x) (((uint32_t)(x) << MCAN_IR_TOO_SHIFT) & MCAN_IR_TOO_MASK) +#define MCAN_IR_TOO_GET(x) (((uint32_t)(x) & MCAN_IR_TOO_MASK) >> MCAN_IR_TOO_SHIFT) + +/* + * MRAF (RW) + * + * Message RAM Access Failure + * The flag is set, when the Rx Handler + * .has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message + * storage is aborted and the Rx Handler starts processing of the following message. + * .was not able to write a message to the Message RAM. In this case message storage is aborted. + * In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. + * The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the + * M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. + * 0= No Message RAM access failure occurred + * 1= Message RAM access failure occurred + */ +#define MCAN_IR_MRAF_MASK (0x20000UL) +#define MCAN_IR_MRAF_SHIFT (17U) +#define MCAN_IR_MRAF_SET(x) (((uint32_t)(x) << MCAN_IR_MRAF_SHIFT) & MCAN_IR_MRAF_MASK) +#define MCAN_IR_MRAF_GET(x) (((uint32_t)(x) & MCAN_IR_MRAF_MASK) >> MCAN_IR_MRAF_SHIFT) + +/* + * TSW (RW) + * + * Timestamp Wraparound + * 0= No timestamp counter wrap-around + * 1= Timestamp counter wrapped around + */ +#define MCAN_IR_TSW_MASK (0x10000UL) +#define MCAN_IR_TSW_SHIFT (16U) +#define MCAN_IR_TSW_SET(x) (((uint32_t)(x) << MCAN_IR_TSW_SHIFT) & MCAN_IR_TSW_MASK) +#define MCAN_IR_TSW_GET(x) (((uint32_t)(x) & MCAN_IR_TSW_MASK) >> MCAN_IR_TSW_SHIFT) + +/* + * TEFL (RW) + * + * Tx Event FIFO Element Lost + * 0= No Tx Event FIFO element lost + * 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero + */ +#define MCAN_IR_TEFL_MASK (0x8000U) +#define MCAN_IR_TEFL_SHIFT (15U) +#define MCAN_IR_TEFL_SET(x) (((uint32_t)(x) << MCAN_IR_TEFL_SHIFT) & MCAN_IR_TEFL_MASK) +#define MCAN_IR_TEFL_GET(x) (((uint32_t)(x) & MCAN_IR_TEFL_MASK) >> MCAN_IR_TEFL_SHIFT) + +/* + * TEFF (RW) + * + * Tx Event FIFO Full + * 0= Tx Event FIFO not full + * 1= Tx Event FIFO full + */ +#define MCAN_IR_TEFF_MASK (0x4000U) +#define MCAN_IR_TEFF_SHIFT (14U) +#define MCAN_IR_TEFF_SET(x) (((uint32_t)(x) << MCAN_IR_TEFF_SHIFT) & MCAN_IR_TEFF_MASK) +#define MCAN_IR_TEFF_GET(x) (((uint32_t)(x) & MCAN_IR_TEFF_MASK) >> MCAN_IR_TEFF_SHIFT) + +/* + * TEFW (RW) + * + * Tx Event FIFO Watermark Reached + * 0= Tx Event FIFO fill level below watermark + * 1= Tx Event FIFO fill level reached watermark + */ +#define MCAN_IR_TEFW_MASK (0x2000U) +#define MCAN_IR_TEFW_SHIFT (13U) +#define MCAN_IR_TEFW_SET(x) (((uint32_t)(x) << MCAN_IR_TEFW_SHIFT) & MCAN_IR_TEFW_MASK) +#define MCAN_IR_TEFW_GET(x) (((uint32_t)(x) & MCAN_IR_TEFW_MASK) >> MCAN_IR_TEFW_SHIFT) + +/* + * TEFN (RW) + * + * Tx Event FIFO New Entry + * 0= Tx Event FIFO unchanged + * 1= Tx Handler wrote Tx Event FIFO element + */ +#define MCAN_IR_TEFN_MASK (0x1000U) +#define MCAN_IR_TEFN_SHIFT (12U) +#define MCAN_IR_TEFN_SET(x) (((uint32_t)(x) << MCAN_IR_TEFN_SHIFT) & MCAN_IR_TEFN_MASK) +#define MCAN_IR_TEFN_GET(x) (((uint32_t)(x) & MCAN_IR_TEFN_MASK) >> MCAN_IR_TEFN_SHIFT) + +/* + * TFE (RW) + * + * Tx FIFO Empty + * 0= Tx FIFO non-empty + * 1= Tx FIFO empty + */ +#define MCAN_IR_TFE_MASK (0x800U) +#define MCAN_IR_TFE_SHIFT (11U) +#define MCAN_IR_TFE_SET(x) (((uint32_t)(x) << MCAN_IR_TFE_SHIFT) & MCAN_IR_TFE_MASK) +#define MCAN_IR_TFE_GET(x) (((uint32_t)(x) & MCAN_IR_TFE_MASK) >> MCAN_IR_TFE_SHIFT) + +/* + * TCF (RW) + * + * Transmission Cancellation Finished + * 0= No transmission cancellation finished + * 1= Transmission cancellation finished + */ +#define MCAN_IR_TCF_MASK (0x400U) +#define MCAN_IR_TCF_SHIFT (10U) +#define MCAN_IR_TCF_SET(x) (((uint32_t)(x) << MCAN_IR_TCF_SHIFT) & MCAN_IR_TCF_MASK) +#define MCAN_IR_TCF_GET(x) (((uint32_t)(x) & MCAN_IR_TCF_MASK) >> MCAN_IR_TCF_SHIFT) + +/* + * TC (RW) + * + * Transmission Completed + * 0= No transmission completed + * 1= Transmission completed + */ +#define MCAN_IR_TC_MASK (0x200U) +#define MCAN_IR_TC_SHIFT (9U) +#define MCAN_IR_TC_SET(x) (((uint32_t)(x) << MCAN_IR_TC_SHIFT) & MCAN_IR_TC_MASK) +#define MCAN_IR_TC_GET(x) (((uint32_t)(x) & MCAN_IR_TC_MASK) >> MCAN_IR_TC_SHIFT) + +/* + * HPM (RW) + * + * High Priority Message + * 0= No high priority message received + * 1= High priority message received + */ +#define MCAN_IR_HPM_MASK (0x100U) +#define MCAN_IR_HPM_SHIFT (8U) +#define MCAN_IR_HPM_SET(x) (((uint32_t)(x) << MCAN_IR_HPM_SHIFT) & MCAN_IR_HPM_MASK) +#define MCAN_IR_HPM_GET(x) (((uint32_t)(x) & MCAN_IR_HPM_MASK) >> MCAN_IR_HPM_SHIFT) + +/* + * RF1L (RW) + * + * Rx FIFO 1 Message Lost + * 0= No Rx FIFO 1 message lost + * 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + */ +#define MCAN_IR_RF1L_MASK (0x80U) +#define MCAN_IR_RF1L_SHIFT (7U) +#define MCAN_IR_RF1L_SET(x) (((uint32_t)(x) << MCAN_IR_RF1L_SHIFT) & MCAN_IR_RF1L_MASK) +#define MCAN_IR_RF1L_GET(x) (((uint32_t)(x) & MCAN_IR_RF1L_MASK) >> MCAN_IR_RF1L_SHIFT) + +/* + * RF1F (RW) + * + * Rx FIFO 1 Full + * 0= Rx FIFO 1 not full + * 1= Rx FIFO 1 full + */ +#define MCAN_IR_RF1F_MASK (0x40U) +#define MCAN_IR_RF1F_SHIFT (6U) +#define MCAN_IR_RF1F_SET(x) (((uint32_t)(x) << MCAN_IR_RF1F_SHIFT) & MCAN_IR_RF1F_MASK) +#define MCAN_IR_RF1F_GET(x) (((uint32_t)(x) & MCAN_IR_RF1F_MASK) >> MCAN_IR_RF1F_SHIFT) + +/* + * RF1W (RW) + * + * Rx FIFO 1 Watermark Reached + * 0= Rx FIFO 1 fill level below watermark + * 1= Rx FIFO 1 fill level reached watermark + */ +#define MCAN_IR_RF1W_MASK (0x20U) +#define MCAN_IR_RF1W_SHIFT (5U) +#define MCAN_IR_RF1W_SET(x) (((uint32_t)(x) << MCAN_IR_RF1W_SHIFT) & MCAN_IR_RF1W_MASK) +#define MCAN_IR_RF1W_GET(x) (((uint32_t)(x) & MCAN_IR_RF1W_MASK) >> MCAN_IR_RF1W_SHIFT) + +/* + * RF1N (RW) + * + * Rx FIFO 1 New Message + * 0= No new message written to Rx FIFO 1 + * 1= New message written to Rx FIFO 1 + */ +#define MCAN_IR_RF1N_MASK (0x10U) +#define MCAN_IR_RF1N_SHIFT (4U) +#define MCAN_IR_RF1N_SET(x) (((uint32_t)(x) << MCAN_IR_RF1N_SHIFT) & MCAN_IR_RF1N_MASK) +#define MCAN_IR_RF1N_GET(x) (((uint32_t)(x) & MCAN_IR_RF1N_MASK) >> MCAN_IR_RF1N_SHIFT) + +/* + * RF0L (RW) + * + * Rx FIFO 0 Message Lost + * 0= No Rx FIFO 0 message lost + * 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + */ +#define MCAN_IR_RF0L_MASK (0x8U) +#define MCAN_IR_RF0L_SHIFT (3U) +#define MCAN_IR_RF0L_SET(x) (((uint32_t)(x) << MCAN_IR_RF0L_SHIFT) & MCAN_IR_RF0L_MASK) +#define MCAN_IR_RF0L_GET(x) (((uint32_t)(x) & MCAN_IR_RF0L_MASK) >> MCAN_IR_RF0L_SHIFT) + +/* + * RF0F (RW) + * + * Rx FIFO 0 Full + * 0= Rx FIFO 0 not full + * 1= Rx FIFO 0 full + */ +#define MCAN_IR_RF0F_MASK (0x4U) +#define MCAN_IR_RF0F_SHIFT (2U) +#define MCAN_IR_RF0F_SET(x) (((uint32_t)(x) << MCAN_IR_RF0F_SHIFT) & MCAN_IR_RF0F_MASK) +#define MCAN_IR_RF0F_GET(x) (((uint32_t)(x) & MCAN_IR_RF0F_MASK) >> MCAN_IR_RF0F_SHIFT) + +/* + * RF0W (RW) + * + * Rx FIFO 0 Watermark Reached + * 0= Rx FIFO 0 fill level below watermark + * 1= Rx FIFO 0 fill level reached watermark + */ +#define MCAN_IR_RF0W_MASK (0x2U) +#define MCAN_IR_RF0W_SHIFT (1U) +#define MCAN_IR_RF0W_SET(x) (((uint32_t)(x) << MCAN_IR_RF0W_SHIFT) & MCAN_IR_RF0W_MASK) +#define MCAN_IR_RF0W_GET(x) (((uint32_t)(x) & MCAN_IR_RF0W_MASK) >> MCAN_IR_RF0W_SHIFT) + +/* + * RF0N (RW) + * + * Rx FIFO 0 New Message + * 0= No new message written to Rx FIFO 0 + * 1= New message written to Rx FIFO 0 + */ +#define MCAN_IR_RF0N_MASK (0x1U) +#define MCAN_IR_RF0N_SHIFT (0U) +#define MCAN_IR_RF0N_SET(x) (((uint32_t)(x) << MCAN_IR_RF0N_SHIFT) & MCAN_IR_RF0N_MASK) +#define MCAN_IR_RF0N_GET(x) (((uint32_t)(x) & MCAN_IR_RF0N_MASK) >> MCAN_IR_RF0N_SHIFT) + +/* Bitfield definition for register: IE */ +/* + * ARAE (RW) + * + * Access to Reserved Address Enable + */ +#define MCAN_IE_ARAE_MASK (0x20000000UL) +#define MCAN_IE_ARAE_SHIFT (29U) +#define MCAN_IE_ARAE_SET(x) (((uint32_t)(x) << MCAN_IE_ARAE_SHIFT) & MCAN_IE_ARAE_MASK) +#define MCAN_IE_ARAE_GET(x) (((uint32_t)(x) & MCAN_IE_ARAE_MASK) >> MCAN_IE_ARAE_SHIFT) + +/* + * PEDE (RW) + * + * Protocol Error in Data Phase Enable + */ +#define MCAN_IE_PEDE_MASK (0x10000000UL) +#define MCAN_IE_PEDE_SHIFT (28U) +#define MCAN_IE_PEDE_SET(x) (((uint32_t)(x) << MCAN_IE_PEDE_SHIFT) & MCAN_IE_PEDE_MASK) +#define MCAN_IE_PEDE_GET(x) (((uint32_t)(x) & MCAN_IE_PEDE_MASK) >> MCAN_IE_PEDE_SHIFT) + +/* + * PEAE (RW) + * + * Protocol Error in Arbitration Phase Enable + */ +#define MCAN_IE_PEAE_MASK (0x8000000UL) +#define MCAN_IE_PEAE_SHIFT (27U) +#define MCAN_IE_PEAE_SET(x) (((uint32_t)(x) << MCAN_IE_PEAE_SHIFT) & MCAN_IE_PEAE_MASK) +#define MCAN_IE_PEAE_GET(x) (((uint32_t)(x) & MCAN_IE_PEAE_MASK) >> MCAN_IE_PEAE_SHIFT) + +/* + * WDIE (RW) + * + * Watchdog Interrupt Enable + */ +#define MCAN_IE_WDIE_MASK (0x4000000UL) +#define MCAN_IE_WDIE_SHIFT (26U) +#define MCAN_IE_WDIE_SET(x) (((uint32_t)(x) << MCAN_IE_WDIE_SHIFT) & MCAN_IE_WDIE_MASK) +#define MCAN_IE_WDIE_GET(x) (((uint32_t)(x) & MCAN_IE_WDIE_MASK) >> MCAN_IE_WDIE_SHIFT) + +/* + * BOE (RW) + * + * Bus_Off Status Interrupt Enable + */ +#define MCAN_IE_BOE_MASK (0x2000000UL) +#define MCAN_IE_BOE_SHIFT (25U) +#define MCAN_IE_BOE_SET(x) (((uint32_t)(x) << MCAN_IE_BOE_SHIFT) & MCAN_IE_BOE_MASK) +#define MCAN_IE_BOE_GET(x) (((uint32_t)(x) & MCAN_IE_BOE_MASK) >> MCAN_IE_BOE_SHIFT) + +/* + * EWE (RW) + * + * Warning Status Interrupt Enable + */ +#define MCAN_IE_EWE_MASK (0x1000000UL) +#define MCAN_IE_EWE_SHIFT (24U) +#define MCAN_IE_EWE_SET(x) (((uint32_t)(x) << MCAN_IE_EWE_SHIFT) & MCAN_IE_EWE_MASK) +#define MCAN_IE_EWE_GET(x) (((uint32_t)(x) & MCAN_IE_EWE_MASK) >> MCAN_IE_EWE_SHIFT) + +/* + * EPE (RW) + * + * Error Passive Interrupt Enable + */ +#define MCAN_IE_EPE_MASK (0x800000UL) +#define MCAN_IE_EPE_SHIFT (23U) +#define MCAN_IE_EPE_SET(x) (((uint32_t)(x) << MCAN_IE_EPE_SHIFT) & MCAN_IE_EPE_MASK) +#define MCAN_IE_EPE_GET(x) (((uint32_t)(x) & MCAN_IE_EPE_MASK) >> MCAN_IE_EPE_SHIFT) + +/* + * ELOE (RW) + * + * Error Logging Overflow Interrupt Enable + */ +#define MCAN_IE_ELOE_MASK (0x400000UL) +#define MCAN_IE_ELOE_SHIFT (22U) +#define MCAN_IE_ELOE_SET(x) (((uint32_t)(x) << MCAN_IE_ELOE_SHIFT) & MCAN_IE_ELOE_MASK) +#define MCAN_IE_ELOE_GET(x) (((uint32_t)(x) & MCAN_IE_ELOE_MASK) >> MCAN_IE_ELOE_SHIFT) + +/* + * BEUE (RW) + * + * Bit Error Uncorrected Interrupt Enable + */ +#define MCAN_IE_BEUE_MASK (0x200000UL) +#define MCAN_IE_BEUE_SHIFT (21U) +#define MCAN_IE_BEUE_SET(x) (((uint32_t)(x) << MCAN_IE_BEUE_SHIFT) & MCAN_IE_BEUE_MASK) +#define MCAN_IE_BEUE_GET(x) (((uint32_t)(x) & MCAN_IE_BEUE_MASK) >> MCAN_IE_BEUE_SHIFT) + +/* + * BECE (RW) + * + * Bit Error Corrected Interrupt Enable + */ +#define MCAN_IE_BECE_MASK (0x100000UL) +#define MCAN_IE_BECE_SHIFT (20U) +#define MCAN_IE_BECE_SET(x) (((uint32_t)(x) << MCAN_IE_BECE_SHIFT) & MCAN_IE_BECE_MASK) +#define MCAN_IE_BECE_GET(x) (((uint32_t)(x) & MCAN_IE_BECE_MASK) >> MCAN_IE_BECE_SHIFT) + +/* + * DRXE (RW) + * + * Message stored to Dedicated Rx Buffer Interrupt Enable + */ +#define MCAN_IE_DRXE_MASK (0x80000UL) +#define MCAN_IE_DRXE_SHIFT (19U) +#define MCAN_IE_DRXE_SET(x) (((uint32_t)(x) << MCAN_IE_DRXE_SHIFT) & MCAN_IE_DRXE_MASK) +#define MCAN_IE_DRXE_GET(x) (((uint32_t)(x) & MCAN_IE_DRXE_MASK) >> MCAN_IE_DRXE_SHIFT) + +/* + * TOOE (RW) + * + * Timeout Occurred Interrupt Enable + */ +#define MCAN_IE_TOOE_MASK (0x40000UL) +#define MCAN_IE_TOOE_SHIFT (18U) +#define MCAN_IE_TOOE_SET(x) (((uint32_t)(x) << MCAN_IE_TOOE_SHIFT) & MCAN_IE_TOOE_MASK) +#define MCAN_IE_TOOE_GET(x) (((uint32_t)(x) & MCAN_IE_TOOE_MASK) >> MCAN_IE_TOOE_SHIFT) + +/* + * MRAFE (RW) + * + * Message RAM Access Failure Interrupt Enable + */ +#define MCAN_IE_MRAFE_MASK (0x20000UL) +#define MCAN_IE_MRAFE_SHIFT (17U) +#define MCAN_IE_MRAFE_SET(x) (((uint32_t)(x) << MCAN_IE_MRAFE_SHIFT) & MCAN_IE_MRAFE_MASK) +#define MCAN_IE_MRAFE_GET(x) (((uint32_t)(x) & MCAN_IE_MRAFE_MASK) >> MCAN_IE_MRAFE_SHIFT) + +/* + * TSWE (RW) + * + * Timestamp Wraparound Interrupt Enable + */ +#define MCAN_IE_TSWE_MASK (0x10000UL) +#define MCAN_IE_TSWE_SHIFT (16U) +#define MCAN_IE_TSWE_SET(x) (((uint32_t)(x) << MCAN_IE_TSWE_SHIFT) & MCAN_IE_TSWE_MASK) +#define MCAN_IE_TSWE_GET(x) (((uint32_t)(x) & MCAN_IE_TSWE_MASK) >> MCAN_IE_TSWE_SHIFT) + +/* + * TEFLE (RW) + * + * Tx Event FIFO Event Lost Interrupt Enable + */ +#define MCAN_IE_TEFLE_MASK (0x8000U) +#define MCAN_IE_TEFLE_SHIFT (15U) +#define MCAN_IE_TEFLE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFLE_SHIFT) & MCAN_IE_TEFLE_MASK) +#define MCAN_IE_TEFLE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFLE_MASK) >> MCAN_IE_TEFLE_SHIFT) + +/* + * TEFFE (RW) + * + * Tx Event FIFO Full Interrupt Enable + */ +#define MCAN_IE_TEFFE_MASK (0x4000U) +#define MCAN_IE_TEFFE_SHIFT (14U) +#define MCAN_IE_TEFFE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFFE_SHIFT) & MCAN_IE_TEFFE_MASK) +#define MCAN_IE_TEFFE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFFE_MASK) >> MCAN_IE_TEFFE_SHIFT) + +/* + * TEFWE (RW) + * + * Tx Event FIFO Watermark Reached Interrupt Enable + */ +#define MCAN_IE_TEFWE_MASK (0x2000U) +#define MCAN_IE_TEFWE_SHIFT (13U) +#define MCAN_IE_TEFWE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFWE_SHIFT) & MCAN_IE_TEFWE_MASK) +#define MCAN_IE_TEFWE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFWE_MASK) >> MCAN_IE_TEFWE_SHIFT) + +/* + * TEFNE (RW) + * + * Tx Event FIFO New Entry Interrupt Enable + */ +#define MCAN_IE_TEFNE_MASK (0x1000U) +#define MCAN_IE_TEFNE_SHIFT (12U) +#define MCAN_IE_TEFNE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFNE_SHIFT) & MCAN_IE_TEFNE_MASK) +#define MCAN_IE_TEFNE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFNE_MASK) >> MCAN_IE_TEFNE_SHIFT) + +/* + * TFEE (RW) + * + * Tx FIFO Empty Interrupt Enable + */ +#define MCAN_IE_TFEE_MASK (0x800U) +#define MCAN_IE_TFEE_SHIFT (11U) +#define MCAN_IE_TFEE_SET(x) (((uint32_t)(x) << MCAN_IE_TFEE_SHIFT) & MCAN_IE_TFEE_MASK) +#define MCAN_IE_TFEE_GET(x) (((uint32_t)(x) & MCAN_IE_TFEE_MASK) >> MCAN_IE_TFEE_SHIFT) + +/* + * TCFE (RW) + * + * Transmission Cancellation Finished Interrupt Enable + */ +#define MCAN_IE_TCFE_MASK (0x400U) +#define MCAN_IE_TCFE_SHIFT (10U) +#define MCAN_IE_TCFE_SET(x) (((uint32_t)(x) << MCAN_IE_TCFE_SHIFT) & MCAN_IE_TCFE_MASK) +#define MCAN_IE_TCFE_GET(x) (((uint32_t)(x) & MCAN_IE_TCFE_MASK) >> MCAN_IE_TCFE_SHIFT) + +/* + * TCE (RW) + * + * Transmission Completed Interrupt Enable + */ +#define MCAN_IE_TCE_MASK (0x200U) +#define MCAN_IE_TCE_SHIFT (9U) +#define MCAN_IE_TCE_SET(x) (((uint32_t)(x) << MCAN_IE_TCE_SHIFT) & MCAN_IE_TCE_MASK) +#define MCAN_IE_TCE_GET(x) (((uint32_t)(x) & MCAN_IE_TCE_MASK) >> MCAN_IE_TCE_SHIFT) + +/* + * HPME (RW) + * + * High Priority Message Interrupt Enable + */ +#define MCAN_IE_HPME_MASK (0x100U) +#define MCAN_IE_HPME_SHIFT (8U) +#define MCAN_IE_HPME_SET(x) (((uint32_t)(x) << MCAN_IE_HPME_SHIFT) & MCAN_IE_HPME_MASK) +#define MCAN_IE_HPME_GET(x) (((uint32_t)(x) & MCAN_IE_HPME_MASK) >> MCAN_IE_HPME_SHIFT) + +/* + * RF1LE (RW) + * + * Rx FIFO 1 Message Lost Interrupt Enable + */ +#define MCAN_IE_RF1LE_MASK (0x80U) +#define MCAN_IE_RF1LE_SHIFT (7U) +#define MCAN_IE_RF1LE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1LE_SHIFT) & MCAN_IE_RF1LE_MASK) +#define MCAN_IE_RF1LE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1LE_MASK) >> MCAN_IE_RF1LE_SHIFT) + +/* + * RF1FE (RW) + * + * Rx FIFO 1 Full Interrupt Enable + */ +#define MCAN_IE_RF1FE_MASK (0x40U) +#define MCAN_IE_RF1FE_SHIFT (6U) +#define MCAN_IE_RF1FE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1FE_SHIFT) & MCAN_IE_RF1FE_MASK) +#define MCAN_IE_RF1FE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1FE_MASK) >> MCAN_IE_RF1FE_SHIFT) + +/* + * RF1WE (RW) + * + * Rx FIFO 1 Watermark Reached Interrupt Enable + */ +#define MCAN_IE_RF1WE_MASK (0x20U) +#define MCAN_IE_RF1WE_SHIFT (5U) +#define MCAN_IE_RF1WE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1WE_SHIFT) & MCAN_IE_RF1WE_MASK) +#define MCAN_IE_RF1WE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1WE_MASK) >> MCAN_IE_RF1WE_SHIFT) + +/* + * RF1NE (RW) + * + * Rx FIFO 1 New Message Interrupt Enable + */ +#define MCAN_IE_RF1NE_MASK (0x10U) +#define MCAN_IE_RF1NE_SHIFT (4U) +#define MCAN_IE_RF1NE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1NE_SHIFT) & MCAN_IE_RF1NE_MASK) +#define MCAN_IE_RF1NE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1NE_MASK) >> MCAN_IE_RF1NE_SHIFT) + +/* + * RF0LE (RW) + * + * Rx FIFO 0 Message Lost Interrupt Enable + */ +#define MCAN_IE_RF0LE_MASK (0x8U) +#define MCAN_IE_RF0LE_SHIFT (3U) +#define MCAN_IE_RF0LE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0LE_SHIFT) & MCAN_IE_RF0LE_MASK) +#define MCAN_IE_RF0LE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0LE_MASK) >> MCAN_IE_RF0LE_SHIFT) + +/* + * RF0FE (RW) + * + * Rx FIFO 0 Full Interrupt Enable + */ +#define MCAN_IE_RF0FE_MASK (0x4U) +#define MCAN_IE_RF0FE_SHIFT (2U) +#define MCAN_IE_RF0FE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0FE_SHIFT) & MCAN_IE_RF0FE_MASK) +#define MCAN_IE_RF0FE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0FE_MASK) >> MCAN_IE_RF0FE_SHIFT) + +/* + * RF0WE (RW) + * + * Rx FIFO 0 Watermark Reached Interrupt Enable + */ +#define MCAN_IE_RF0WE_MASK (0x2U) +#define MCAN_IE_RF0WE_SHIFT (1U) +#define MCAN_IE_RF0WE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0WE_SHIFT) & MCAN_IE_RF0WE_MASK) +#define MCAN_IE_RF0WE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0WE_MASK) >> MCAN_IE_RF0WE_SHIFT) + +/* + * RF0NE (RW) + * + * Rx FIFO 0 New Message Interrupt Enable + */ +#define MCAN_IE_RF0NE_MASK (0x1U) +#define MCAN_IE_RF0NE_SHIFT (0U) +#define MCAN_IE_RF0NE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0NE_SHIFT) & MCAN_IE_RF0NE_MASK) +#define MCAN_IE_RF0NE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0NE_MASK) >> MCAN_IE_RF0NE_SHIFT) + +/* Bitfield definition for register: ILS */ +/* + * ARAL (RW) + * + * Access to Reserved Address Line + */ +#define MCAN_ILS_ARAL_MASK (0x20000000UL) +#define MCAN_ILS_ARAL_SHIFT (29U) +#define MCAN_ILS_ARAL_SET(x) (((uint32_t)(x) << MCAN_ILS_ARAL_SHIFT) & MCAN_ILS_ARAL_MASK) +#define MCAN_ILS_ARAL_GET(x) (((uint32_t)(x) & MCAN_ILS_ARAL_MASK) >> MCAN_ILS_ARAL_SHIFT) + +/* + * PEDL (RW) + * + * Protocol Error in Data Phase Line + */ +#define MCAN_ILS_PEDL_MASK (0x10000000UL) +#define MCAN_ILS_PEDL_SHIFT (28U) +#define MCAN_ILS_PEDL_SET(x) (((uint32_t)(x) << MCAN_ILS_PEDL_SHIFT) & MCAN_ILS_PEDL_MASK) +#define MCAN_ILS_PEDL_GET(x) (((uint32_t)(x) & MCAN_ILS_PEDL_MASK) >> MCAN_ILS_PEDL_SHIFT) + +/* + * PEAL (RW) + * + * Protocol Error in Arbitration Phase Line + */ +#define MCAN_ILS_PEAL_MASK (0x8000000UL) +#define MCAN_ILS_PEAL_SHIFT (27U) +#define MCAN_ILS_PEAL_SET(x) (((uint32_t)(x) << MCAN_ILS_PEAL_SHIFT) & MCAN_ILS_PEAL_MASK) +#define MCAN_ILS_PEAL_GET(x) (((uint32_t)(x) & MCAN_ILS_PEAL_MASK) >> MCAN_ILS_PEAL_SHIFT) + +/* + * WDIL (RW) + * + * Watchdog Interrupt Line + */ +#define MCAN_ILS_WDIL_MASK (0x4000000UL) +#define MCAN_ILS_WDIL_SHIFT (26U) +#define MCAN_ILS_WDIL_SET(x) (((uint32_t)(x) << MCAN_ILS_WDIL_SHIFT) & MCAN_ILS_WDIL_MASK) +#define MCAN_ILS_WDIL_GET(x) (((uint32_t)(x) & MCAN_ILS_WDIL_MASK) >> MCAN_ILS_WDIL_SHIFT) + +/* + * BOL (RW) + * + * Bus_Off Status Interrupt Line + */ +#define MCAN_ILS_BOL_MASK (0x2000000UL) +#define MCAN_ILS_BOL_SHIFT (25U) +#define MCAN_ILS_BOL_SET(x) (((uint32_t)(x) << MCAN_ILS_BOL_SHIFT) & MCAN_ILS_BOL_MASK) +#define MCAN_ILS_BOL_GET(x) (((uint32_t)(x) & MCAN_ILS_BOL_MASK) >> MCAN_ILS_BOL_SHIFT) + +/* + * EWL (RW) + * + * Warning Status Interrupt Line + */ +#define MCAN_ILS_EWL_MASK (0x1000000UL) +#define MCAN_ILS_EWL_SHIFT (24U) +#define MCAN_ILS_EWL_SET(x) (((uint32_t)(x) << MCAN_ILS_EWL_SHIFT) & MCAN_ILS_EWL_MASK) +#define MCAN_ILS_EWL_GET(x) (((uint32_t)(x) & MCAN_ILS_EWL_MASK) >> MCAN_ILS_EWL_SHIFT) + +/* + * EPL (RW) + * + * Error Passive Interrupt Line + */ +#define MCAN_ILS_EPL_MASK (0x800000UL) +#define MCAN_ILS_EPL_SHIFT (23U) +#define MCAN_ILS_EPL_SET(x) (((uint32_t)(x) << MCAN_ILS_EPL_SHIFT) & MCAN_ILS_EPL_MASK) +#define MCAN_ILS_EPL_GET(x) (((uint32_t)(x) & MCAN_ILS_EPL_MASK) >> MCAN_ILS_EPL_SHIFT) + +/* + * ELOL (RW) + * + * Error Logging Overflow Interrupt Line + */ +#define MCAN_ILS_ELOL_MASK (0x400000UL) +#define MCAN_ILS_ELOL_SHIFT (22U) +#define MCAN_ILS_ELOL_SET(x) (((uint32_t)(x) << MCAN_ILS_ELOL_SHIFT) & MCAN_ILS_ELOL_MASK) +#define MCAN_ILS_ELOL_GET(x) (((uint32_t)(x) & MCAN_ILS_ELOL_MASK) >> MCAN_ILS_ELOL_SHIFT) + +/* + * BEUL (RW) + * + * Bit Error Uncorrected Interrupt Line + */ +#define MCAN_ILS_BEUL_MASK (0x200000UL) +#define MCAN_ILS_BEUL_SHIFT (21U) +#define MCAN_ILS_BEUL_SET(x) (((uint32_t)(x) << MCAN_ILS_BEUL_SHIFT) & MCAN_ILS_BEUL_MASK) +#define MCAN_ILS_BEUL_GET(x) (((uint32_t)(x) & MCAN_ILS_BEUL_MASK) >> MCAN_ILS_BEUL_SHIFT) + +/* + * BECL (RW) + * + * Bit Error Corrected Interrupt Line + */ +#define MCAN_ILS_BECL_MASK (0x100000UL) +#define MCAN_ILS_BECL_SHIFT (20U) +#define MCAN_ILS_BECL_SET(x) (((uint32_t)(x) << MCAN_ILS_BECL_SHIFT) & MCAN_ILS_BECL_MASK) +#define MCAN_ILS_BECL_GET(x) (((uint32_t)(x) & MCAN_ILS_BECL_MASK) >> MCAN_ILS_BECL_SHIFT) + +/* + * DRXL (RW) + * + * Message stored to Dedicated Rx Buffer Interrupt Line + */ +#define MCAN_ILS_DRXL_MASK (0x80000UL) +#define MCAN_ILS_DRXL_SHIFT (19U) +#define MCAN_ILS_DRXL_SET(x) (((uint32_t)(x) << MCAN_ILS_DRXL_SHIFT) & MCAN_ILS_DRXL_MASK) +#define MCAN_ILS_DRXL_GET(x) (((uint32_t)(x) & MCAN_ILS_DRXL_MASK) >> MCAN_ILS_DRXL_SHIFT) + +/* + * TOOL (RW) + * + * Timeout Occurred Interrupt Line + */ +#define MCAN_ILS_TOOL_MASK (0x40000UL) +#define MCAN_ILS_TOOL_SHIFT (18U) +#define MCAN_ILS_TOOL_SET(x) (((uint32_t)(x) << MCAN_ILS_TOOL_SHIFT) & MCAN_ILS_TOOL_MASK) +#define MCAN_ILS_TOOL_GET(x) (((uint32_t)(x) & MCAN_ILS_TOOL_MASK) >> MCAN_ILS_TOOL_SHIFT) + +/* + * MRAFL (RW) + * + * Message RAM Access Failure Interrupt Line + */ +#define MCAN_ILS_MRAFL_MASK (0x20000UL) +#define MCAN_ILS_MRAFL_SHIFT (17U) +#define MCAN_ILS_MRAFL_SET(x) (((uint32_t)(x) << MCAN_ILS_MRAFL_SHIFT) & MCAN_ILS_MRAFL_MASK) +#define MCAN_ILS_MRAFL_GET(x) (((uint32_t)(x) & MCAN_ILS_MRAFL_MASK) >> MCAN_ILS_MRAFL_SHIFT) + +/* + * TSWL (RW) + * + * Timestamp Wraparound Interrupt Line + */ +#define MCAN_ILS_TSWL_MASK (0x10000UL) +#define MCAN_ILS_TSWL_SHIFT (16U) +#define MCAN_ILS_TSWL_SET(x) (((uint32_t)(x) << MCAN_ILS_TSWL_SHIFT) & MCAN_ILS_TSWL_MASK) +#define MCAN_ILS_TSWL_GET(x) (((uint32_t)(x) & MCAN_ILS_TSWL_MASK) >> MCAN_ILS_TSWL_SHIFT) + +/* + * TEFLL (RW) + * + * Tx Event FIFO Event Lost Interrupt Line + */ +#define MCAN_ILS_TEFLL_MASK (0x8000U) +#define MCAN_ILS_TEFLL_SHIFT (15U) +#define MCAN_ILS_TEFLL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFLL_SHIFT) & MCAN_ILS_TEFLL_MASK) +#define MCAN_ILS_TEFLL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFLL_MASK) >> MCAN_ILS_TEFLL_SHIFT) + +/* + * TEFFL (RW) + * + * Tx Event FIFO Full Interrupt Line + */ +#define MCAN_ILS_TEFFL_MASK (0x4000U) +#define MCAN_ILS_TEFFL_SHIFT (14U) +#define MCAN_ILS_TEFFL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFFL_SHIFT) & MCAN_ILS_TEFFL_MASK) +#define MCAN_ILS_TEFFL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFFL_MASK) >> MCAN_ILS_TEFFL_SHIFT) + +/* + * TEFWL (RW) + * + * Tx Event FIFO Watermark Reached Interrupt Line + */ +#define MCAN_ILS_TEFWL_MASK (0x2000U) +#define MCAN_ILS_TEFWL_SHIFT (13U) +#define MCAN_ILS_TEFWL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFWL_SHIFT) & MCAN_ILS_TEFWL_MASK) +#define MCAN_ILS_TEFWL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFWL_MASK) >> MCAN_ILS_TEFWL_SHIFT) + +/* + * TEFNL (RW) + * + * Tx Event FIFO New Entry Interrupt Line + */ +#define MCAN_ILS_TEFNL_MASK (0x1000U) +#define MCAN_ILS_TEFNL_SHIFT (12U) +#define MCAN_ILS_TEFNL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFNL_SHIFT) & MCAN_ILS_TEFNL_MASK) +#define MCAN_ILS_TEFNL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFNL_MASK) >> MCAN_ILS_TEFNL_SHIFT) + +/* + * TFEL (RW) + * + * Tx FIFO Empty Interrupt Line + */ +#define MCAN_ILS_TFEL_MASK (0x800U) +#define MCAN_ILS_TFEL_SHIFT (11U) +#define MCAN_ILS_TFEL_SET(x) (((uint32_t)(x) << MCAN_ILS_TFEL_SHIFT) & MCAN_ILS_TFEL_MASK) +#define MCAN_ILS_TFEL_GET(x) (((uint32_t)(x) & MCAN_ILS_TFEL_MASK) >> MCAN_ILS_TFEL_SHIFT) + +/* + * TCFL (RW) + * + * Transmission Cancellation Finished Interrupt Line + */ +#define MCAN_ILS_TCFL_MASK (0x400U) +#define MCAN_ILS_TCFL_SHIFT (10U) +#define MCAN_ILS_TCFL_SET(x) (((uint32_t)(x) << MCAN_ILS_TCFL_SHIFT) & MCAN_ILS_TCFL_MASK) +#define MCAN_ILS_TCFL_GET(x) (((uint32_t)(x) & MCAN_ILS_TCFL_MASK) >> MCAN_ILS_TCFL_SHIFT) + +/* + * TCL (RW) + * + * Transmission Completed Interrupt Line + */ +#define MCAN_ILS_TCL_MASK (0x200U) +#define MCAN_ILS_TCL_SHIFT (9U) +#define MCAN_ILS_TCL_SET(x) (((uint32_t)(x) << MCAN_ILS_TCL_SHIFT) & MCAN_ILS_TCL_MASK) +#define MCAN_ILS_TCL_GET(x) (((uint32_t)(x) & MCAN_ILS_TCL_MASK) >> MCAN_ILS_TCL_SHIFT) + +/* + * HPML (RW) + * + * High Priority Message Interrupt Line + */ +#define MCAN_ILS_HPML_MASK (0x100U) +#define MCAN_ILS_HPML_SHIFT (8U) +#define MCAN_ILS_HPML_SET(x) (((uint32_t)(x) << MCAN_ILS_HPML_SHIFT) & MCAN_ILS_HPML_MASK) +#define MCAN_ILS_HPML_GET(x) (((uint32_t)(x) & MCAN_ILS_HPML_MASK) >> MCAN_ILS_HPML_SHIFT) + +/* + * RF1LL (RW) + * + * Rx FIFO 1 Message Lost Interrupt Line + */ +#define MCAN_ILS_RF1LL_MASK (0x80U) +#define MCAN_ILS_RF1LL_SHIFT (7U) +#define MCAN_ILS_RF1LL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1LL_SHIFT) & MCAN_ILS_RF1LL_MASK) +#define MCAN_ILS_RF1LL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1LL_MASK) >> MCAN_ILS_RF1LL_SHIFT) + +/* + * RF1FL (RW) + * + * Rx FIFO 1 Full Interrupt Line + */ +#define MCAN_ILS_RF1FL_MASK (0x40U) +#define MCAN_ILS_RF1FL_SHIFT (6U) +#define MCAN_ILS_RF1FL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1FL_SHIFT) & MCAN_ILS_RF1FL_MASK) +#define MCAN_ILS_RF1FL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1FL_MASK) >> MCAN_ILS_RF1FL_SHIFT) + +/* + * RF1WL (RW) + * + * Rx FIFO 1 Watermark Reached Interrupt Line + */ +#define MCAN_ILS_RF1WL_MASK (0x20U) +#define MCAN_ILS_RF1WL_SHIFT (5U) +#define MCAN_ILS_RF1WL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1WL_SHIFT) & MCAN_ILS_RF1WL_MASK) +#define MCAN_ILS_RF1WL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1WL_MASK) >> MCAN_ILS_RF1WL_SHIFT) + +/* + * RF1NL (RW) + * + * Rx FIFO 1 New Message Interrupt Line + */ +#define MCAN_ILS_RF1NL_MASK (0x10U) +#define MCAN_ILS_RF1NL_SHIFT (4U) +#define MCAN_ILS_RF1NL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1NL_SHIFT) & MCAN_ILS_RF1NL_MASK) +#define MCAN_ILS_RF1NL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1NL_MASK) >> MCAN_ILS_RF1NL_SHIFT) + +/* + * RF0LL (RW) + * + * Rx FIFO 0 Message Lost Interrupt Line + */ +#define MCAN_ILS_RF0LL_MASK (0x8U) +#define MCAN_ILS_RF0LL_SHIFT (3U) +#define MCAN_ILS_RF0LL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0LL_SHIFT) & MCAN_ILS_RF0LL_MASK) +#define MCAN_ILS_RF0LL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0LL_MASK) >> MCAN_ILS_RF0LL_SHIFT) + +/* + * RF0FL (RW) + * + * Rx FIFO 0 Full Interrupt Line + */ +#define MCAN_ILS_RF0FL_MASK (0x4U) +#define MCAN_ILS_RF0FL_SHIFT (2U) +#define MCAN_ILS_RF0FL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0FL_SHIFT) & MCAN_ILS_RF0FL_MASK) +#define MCAN_ILS_RF0FL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0FL_MASK) >> MCAN_ILS_RF0FL_SHIFT) + +/* + * RF0WL (RW) + * + * Rx FIFO 0 Watermark Reached Interrupt Line + */ +#define MCAN_ILS_RF0WL_MASK (0x2U) +#define MCAN_ILS_RF0WL_SHIFT (1U) +#define MCAN_ILS_RF0WL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0WL_SHIFT) & MCAN_ILS_RF0WL_MASK) +#define MCAN_ILS_RF0WL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0WL_MASK) >> MCAN_ILS_RF0WL_SHIFT) + +/* + * RF0NL (RW) + * + * Rx FIFO 0 New Message Interrupt Line + */ +#define MCAN_ILS_RF0NL_MASK (0x1U) +#define MCAN_ILS_RF0NL_SHIFT (0U) +#define MCAN_ILS_RF0NL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0NL_SHIFT) & MCAN_ILS_RF0NL_MASK) +#define MCAN_ILS_RF0NL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0NL_MASK) >> MCAN_ILS_RF0NL_SHIFT) + +/* Bitfield definition for register: ILE */ +/* + * EINT1 (RW) + * + * Enable Interrupt Line 1 + * 0= Interrupt line m_can_int1 disabled + * 1= Interrupt line m_can_int1 enabled + */ +#define MCAN_ILE_EINT1_MASK (0x2U) +#define MCAN_ILE_EINT1_SHIFT (1U) +#define MCAN_ILE_EINT1_SET(x) (((uint32_t)(x) << MCAN_ILE_EINT1_SHIFT) & MCAN_ILE_EINT1_MASK) +#define MCAN_ILE_EINT1_GET(x) (((uint32_t)(x) & MCAN_ILE_EINT1_MASK) >> MCAN_ILE_EINT1_SHIFT) + +/* + * EINT0 (RW) + * + * Enable Interrupt Line 0 + * 0= Interrupt line m_can_int0 disabled + * 1= Interrupt line m_can_int0 enabled + */ +#define MCAN_ILE_EINT0_MASK (0x1U) +#define MCAN_ILE_EINT0_SHIFT (0U) +#define MCAN_ILE_EINT0_SET(x) (((uint32_t)(x) << MCAN_ILE_EINT0_SHIFT) & MCAN_ILE_EINT0_MASK) +#define MCAN_ILE_EINT0_GET(x) (((uint32_t)(x) & MCAN_ILE_EINT0_MASK) >> MCAN_ILE_EINT0_SHIFT) + +/* Bitfield definition for register: GFC */ +/* + * ANFS (RW) + * + * Accept Non-matching Frames Standard + * Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. + * 00= Accept in Rx FIFO 0 + * 01= Accept in Rx FIFO 1 + * 10= Reject + * 11= Reject + */ +#define MCAN_GFC_ANFS_MASK (0x30U) +#define MCAN_GFC_ANFS_SHIFT (4U) +#define MCAN_GFC_ANFS_SET(x) (((uint32_t)(x) << MCAN_GFC_ANFS_SHIFT) & MCAN_GFC_ANFS_MASK) +#define MCAN_GFC_ANFS_GET(x) (((uint32_t)(x) & MCAN_GFC_ANFS_MASK) >> MCAN_GFC_ANFS_SHIFT) + +/* + * ANFE (RW) + * + * Accept Non-matching Frames Extended + * Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. + * 00= Accept in Rx FIFO 0 + * 01= Accept in Rx FIFO 1 + * 10= Reject + * 11= Reject + */ +#define MCAN_GFC_ANFE_MASK (0xCU) +#define MCAN_GFC_ANFE_SHIFT (2U) +#define MCAN_GFC_ANFE_SET(x) (((uint32_t)(x) << MCAN_GFC_ANFE_SHIFT) & MCAN_GFC_ANFE_MASK) +#define MCAN_GFC_ANFE_GET(x) (((uint32_t)(x) & MCAN_GFC_ANFE_MASK) >> MCAN_GFC_ANFE_SHIFT) + +/* + * RRFS (RW) + * + * Reject Remote Frames Standard + * 0= Filter remote frames with 11-bit standard IDs + * 1= Reject all remote frames with 11-bit standard IDs + */ +#define MCAN_GFC_RRFS_MASK (0x2U) +#define MCAN_GFC_RRFS_SHIFT (1U) +#define MCAN_GFC_RRFS_SET(x) (((uint32_t)(x) << MCAN_GFC_RRFS_SHIFT) & MCAN_GFC_RRFS_MASK) +#define MCAN_GFC_RRFS_GET(x) (((uint32_t)(x) & MCAN_GFC_RRFS_MASK) >> MCAN_GFC_RRFS_SHIFT) + +/* + * RRFE (RW) + * + * Reject Remote Frames Extended + * 0= Filter remote frames with 29-bit extended IDs + * 1= Reject all remote frames with 29-bit extended IDs + */ +#define MCAN_GFC_RRFE_MASK (0x1U) +#define MCAN_GFC_RRFE_SHIFT (0U) +#define MCAN_GFC_RRFE_SET(x) (((uint32_t)(x) << MCAN_GFC_RRFE_SHIFT) & MCAN_GFC_RRFE_MASK) +#define MCAN_GFC_RRFE_GET(x) (((uint32_t)(x) & MCAN_GFC_RRFE_MASK) >> MCAN_GFC_RRFE_SHIFT) + +/* Bitfield definition for register: SIDFC */ +/* + * LSS (RW) + * + * List Size Standard + * 0= No standard Message ID filter + * 1-128= Number of standard Message ID filter elements + * >128= Values greater than 128 are interpreted as 128 + */ +#define MCAN_SIDFC_LSS_MASK (0xFF0000UL) +#define MCAN_SIDFC_LSS_SHIFT (16U) +#define MCAN_SIDFC_LSS_SET(x) (((uint32_t)(x) << MCAN_SIDFC_LSS_SHIFT) & MCAN_SIDFC_LSS_MASK) +#define MCAN_SIDFC_LSS_GET(x) (((uint32_t)(x) & MCAN_SIDFC_LSS_MASK) >> MCAN_SIDFC_LSS_SHIFT) + +/* + * FLSSA (RW) + * + * Filter List Standard Start Address + * Start address of standard Message ID filter list (32-bit word address) + */ +#define MCAN_SIDFC_FLSSA_MASK (0xFFFCU) +#define MCAN_SIDFC_FLSSA_SHIFT (2U) +#define MCAN_SIDFC_FLSSA_SET(x) (((uint32_t)(x) << MCAN_SIDFC_FLSSA_SHIFT) & MCAN_SIDFC_FLSSA_MASK) +#define MCAN_SIDFC_FLSSA_GET(x) (((uint32_t)(x) & MCAN_SIDFC_FLSSA_MASK) >> MCAN_SIDFC_FLSSA_SHIFT) + +/* Bitfield definition for register: XIDFC */ +/* + * LSE (RW) + * + * List Size Extended + * 0= No extended Message ID filter + * 1-64= Number of extended Message ID filter elements + * >64= Values greater than 64 are interpreted as 64 + */ +#define MCAN_XIDFC_LSE_MASK (0x7F0000UL) +#define MCAN_XIDFC_LSE_SHIFT (16U) +#define MCAN_XIDFC_LSE_SET(x) (((uint32_t)(x) << MCAN_XIDFC_LSE_SHIFT) & MCAN_XIDFC_LSE_MASK) +#define MCAN_XIDFC_LSE_GET(x) (((uint32_t)(x) & MCAN_XIDFC_LSE_MASK) >> MCAN_XIDFC_LSE_SHIFT) + +/* + * FLESA (RW) + * + * Filter List Extended Start Address + * Start address of extended Message ID filter list (32-bit word address). + */ +#define MCAN_XIDFC_FLESA_MASK (0xFFFCU) +#define MCAN_XIDFC_FLESA_SHIFT (2U) +#define MCAN_XIDFC_FLESA_SET(x) (((uint32_t)(x) << MCAN_XIDFC_FLESA_SHIFT) & MCAN_XIDFC_FLESA_MASK) +#define MCAN_XIDFC_FLESA_GET(x) (((uint32_t)(x) & MCAN_XIDFC_FLESA_MASK) >> MCAN_XIDFC_FLESA_SHIFT) + +/* Bitfield definition for register: XIDAM */ +/* + * EIDM (RW) + * + * Extended ID Mask + * For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. + */ +#define MCAN_XIDAM_EIDM_MASK (0x1FFFFFFFUL) +#define MCAN_XIDAM_EIDM_SHIFT (0U) +#define MCAN_XIDAM_EIDM_SET(x) (((uint32_t)(x) << MCAN_XIDAM_EIDM_SHIFT) & MCAN_XIDAM_EIDM_MASK) +#define MCAN_XIDAM_EIDM_GET(x) (((uint32_t)(x) & MCAN_XIDAM_EIDM_MASK) >> MCAN_XIDAM_EIDM_SHIFT) + +/* Bitfield definition for register: HPMS */ +/* + * FLST (R) + * + * Filter List + * Indicates the filter list of the matching filter element. + * 0= Standard Filter List + * 1= Extended Filter List + */ +#define MCAN_HPMS_FLST_MASK (0x8000U) +#define MCAN_HPMS_FLST_SHIFT (15U) +#define MCAN_HPMS_FLST_GET(x) (((uint32_t)(x) & MCAN_HPMS_FLST_MASK) >> MCAN_HPMS_FLST_SHIFT) + +/* + * FIDX (R) + * + * Filter Index + * Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. + */ +#define MCAN_HPMS_FIDX_MASK (0x7F00U) +#define MCAN_HPMS_FIDX_SHIFT (8U) +#define MCAN_HPMS_FIDX_GET(x) (((uint32_t)(x) & MCAN_HPMS_FIDX_MASK) >> MCAN_HPMS_FIDX_SHIFT) + +/* + * MSI (R) + * + * Message Storage Indicator + * 00= No FIFO selected + * 01= FIFO message lost + * 10= Message stored in FIFO 0 + * 11= Message stored in FIFO 1 + */ +#define MCAN_HPMS_MSI_MASK (0xC0U) +#define MCAN_HPMS_MSI_SHIFT (6U) +#define MCAN_HPMS_MSI_GET(x) (((uint32_t)(x) & MCAN_HPMS_MSI_MASK) >> MCAN_HPMS_MSI_SHIFT) + +/* + * BIDX (R) + * + * Buffer Index + * Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. + */ +#define MCAN_HPMS_BIDX_MASK (0x3FU) +#define MCAN_HPMS_BIDX_SHIFT (0U) +#define MCAN_HPMS_BIDX_GET(x) (((uint32_t)(x) & MCAN_HPMS_BIDX_MASK) >> MCAN_HPMS_BIDX_SHIFT) + +/* Bitfield definition for register: NDAT1 */ +/* + * ND1 (RW) + * + * New Data[31:0] + * The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. + * 0= Rx Buffer not updated + * 1= Rx Buffer updated from new message + */ +#define MCAN_NDAT1_ND1_MASK (0xFFFFFFFFUL) +#define MCAN_NDAT1_ND1_SHIFT (0U) +#define MCAN_NDAT1_ND1_SET(x) (((uint32_t)(x) << MCAN_NDAT1_ND1_SHIFT) & MCAN_NDAT1_ND1_MASK) +#define MCAN_NDAT1_ND1_GET(x) (((uint32_t)(x) & MCAN_NDAT1_ND1_MASK) >> MCAN_NDAT1_ND1_SHIFT) + +/* Bitfield definition for register: NDAT2 */ +/* + * ND2 (RW) + * + * New Data[63:32] + * The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. + * 0= Rx Buffer not updated + * 1= Rx Buffer updated from new message + */ +#define MCAN_NDAT2_ND2_MASK (0xFFFFFFFFUL) +#define MCAN_NDAT2_ND2_SHIFT (0U) +#define MCAN_NDAT2_ND2_SET(x) (((uint32_t)(x) << MCAN_NDAT2_ND2_SHIFT) & MCAN_NDAT2_ND2_MASK) +#define MCAN_NDAT2_ND2_GET(x) (((uint32_t)(x) & MCAN_NDAT2_ND2_MASK) >> MCAN_NDAT2_ND2_SHIFT) + +/* Bitfield definition for register: RXF0C */ +/* + * F0OM (RW) + * + * FIFO 0 Operation Mode + * FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). + * 0= FIFO 0 blocking mode + * 1= FIFO 0 overwrite mode + */ +#define MCAN_RXF0C_F0OM_MASK (0x80000000UL) +#define MCAN_RXF0C_F0OM_SHIFT (31U) +#define MCAN_RXF0C_F0OM_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0OM_SHIFT) & MCAN_RXF0C_F0OM_MASK) +#define MCAN_RXF0C_F0OM_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0OM_MASK) >> MCAN_RXF0C_F0OM_SHIFT) + +/* + * F0WM (RW) + * + * Rx FIFO 0 Watermark + * 0= Watermark interrupt disabled + * 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) + * >64= Watermark interrupt disabled + */ +#define MCAN_RXF0C_F0WM_MASK (0x7F000000UL) +#define MCAN_RXF0C_F0WM_SHIFT (24U) +#define MCAN_RXF0C_F0WM_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0WM_SHIFT) & MCAN_RXF0C_F0WM_MASK) +#define MCAN_RXF0C_F0WM_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0WM_MASK) >> MCAN_RXF0C_F0WM_SHIFT) + +/* + * F0S (RW) + * + * Rx FIFO 0 Size + * 0= No Rx FIFO 0 + * 1-64= Number of Rx FIFO 0 elements + * >64= Values greater than 64 are interpreted as 64 + * The Rx FIFO 0 elements are indexed from 0 to F0S-1 + */ +#define MCAN_RXF0C_F0S_MASK (0x7F0000UL) +#define MCAN_RXF0C_F0S_SHIFT (16U) +#define MCAN_RXF0C_F0S_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0S_SHIFT) & MCAN_RXF0C_F0S_MASK) +#define MCAN_RXF0C_F0S_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0S_MASK) >> MCAN_RXF0C_F0S_SHIFT) + +/* + * F0SA (RW) + * + * Rx FIFO 0 Start Address + * Start address of Rx FIFO 0 in Message RAM (32-bit word address) + */ +#define MCAN_RXF0C_F0SA_MASK (0xFFFCU) +#define MCAN_RXF0C_F0SA_SHIFT (2U) +#define MCAN_RXF0C_F0SA_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0SA_SHIFT) & MCAN_RXF0C_F0SA_MASK) +#define MCAN_RXF0C_F0SA_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0SA_MASK) >> MCAN_RXF0C_F0SA_SHIFT) + +/* Bitfield definition for register: RXF0S */ +/* + * RF0L (R) + * + * Rx FIFO 0 Message Lost + * This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. + * 0= No Rx FIFO 0 message lost + * 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + * Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. + */ +#define MCAN_RXF0S_RF0L_MASK (0x2000000UL) +#define MCAN_RXF0S_RF0L_SHIFT (25U) +#define MCAN_RXF0S_RF0L_GET(x) (((uint32_t)(x) & MCAN_RXF0S_RF0L_MASK) >> MCAN_RXF0S_RF0L_SHIFT) + +/* + * F0F (R) + * + * Rx FIFO 0 Full + * 0= Rx FIFO 0 not full + * 1= Rx FIFO 0 full + */ +#define MCAN_RXF0S_F0F_MASK (0x1000000UL) +#define MCAN_RXF0S_F0F_SHIFT (24U) +#define MCAN_RXF0S_F0F_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0F_MASK) >> MCAN_RXF0S_F0F_SHIFT) + +/* + * F0PI (R) + * + * Rx FIFO 0 Put Index + * Rx FIFO 0 write index pointer, range 0 to 63. + */ +#define MCAN_RXF0S_F0PI_MASK (0x3F0000UL) +#define MCAN_RXF0S_F0PI_SHIFT (16U) +#define MCAN_RXF0S_F0PI_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0PI_MASK) >> MCAN_RXF0S_F0PI_SHIFT) + +/* + * F0GI (R) + * + * Rx FIFO 0 Get Index + * Rx FIFO 0 read index pointer, range 0 to 63. + */ +#define MCAN_RXF0S_F0GI_MASK (0x3F00U) +#define MCAN_RXF0S_F0GI_SHIFT (8U) +#define MCAN_RXF0S_F0GI_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0GI_MASK) >> MCAN_RXF0S_F0GI_SHIFT) + +/* + * F0FL (R) + * + * Rx FIFO 0 Fill Level + * Number of elements stored in Rx FIFO 0, range 0 to 64. + */ +#define MCAN_RXF0S_F0FL_MASK (0x7FU) +#define MCAN_RXF0S_F0FL_SHIFT (0U) +#define MCAN_RXF0S_F0FL_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0FL_MASK) >> MCAN_RXF0S_F0FL_SHIFT) + +/* Bitfield definition for register: RXF0A */ +/* + * F0AI (RW) + * + * Rx FIFO 0 Acknowledge Index + * After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + */ +#define MCAN_RXF0A_F0AI_MASK (0x3FU) +#define MCAN_RXF0A_F0AI_SHIFT (0U) +#define MCAN_RXF0A_F0AI_SET(x) (((uint32_t)(x) << MCAN_RXF0A_F0AI_SHIFT) & MCAN_RXF0A_F0AI_MASK) +#define MCAN_RXF0A_F0AI_GET(x) (((uint32_t)(x) & MCAN_RXF0A_F0AI_MASK) >> MCAN_RXF0A_F0AI_SHIFT) + +/* Bitfield definition for register: RXBC */ +/* + * RBSA (RW) + * + * Rx Buffer Start Address + * Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. + */ +#define MCAN_RXBC_RBSA_MASK (0xFFFCU) +#define MCAN_RXBC_RBSA_SHIFT (2U) +#define MCAN_RXBC_RBSA_SET(x) (((uint32_t)(x) << MCAN_RXBC_RBSA_SHIFT) & MCAN_RXBC_RBSA_MASK) +#define MCAN_RXBC_RBSA_GET(x) (((uint32_t)(x) & MCAN_RXBC_RBSA_MASK) >> MCAN_RXBC_RBSA_SHIFT) + +/* Bitfield definition for register: RXF1C */ +/* + * F1OM (RW) + * + * FIFO 1 Operation Mode + * FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). + * 0= FIFO 1 blocking mode + * 1= FIFO 1 overwrite mode + */ +#define MCAN_RXF1C_F1OM_MASK (0x80000000UL) +#define MCAN_RXF1C_F1OM_SHIFT (31U) +#define MCAN_RXF1C_F1OM_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1OM_SHIFT) & MCAN_RXF1C_F1OM_MASK) +#define MCAN_RXF1C_F1OM_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1OM_MASK) >> MCAN_RXF1C_F1OM_SHIFT) + +/* + * F1WM (RW) + * + * Rx FIFO 1 Watermark + * 0= Watermark interrupt disabled + * 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) + * >64= Watermark interrupt disabled + */ +#define MCAN_RXF1C_F1WM_MASK (0x7F000000UL) +#define MCAN_RXF1C_F1WM_SHIFT (24U) +#define MCAN_RXF1C_F1WM_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1WM_SHIFT) & MCAN_RXF1C_F1WM_MASK) +#define MCAN_RXF1C_F1WM_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1WM_MASK) >> MCAN_RXF1C_F1WM_SHIFT) + +/* + * F1S (RW) + * + * Rx FIFO 1 Size + * 0= No Rx FIFO 1 + * 1-64= Number of Rx FIFO 1 elements + * >64= Values greater than 64 are interpreted as 64 + * The Rx FIFO 1 elements are indexed from 0 to F1S - 1 + */ +#define MCAN_RXF1C_F1S_MASK (0x7F0000UL) +#define MCAN_RXF1C_F1S_SHIFT (16U) +#define MCAN_RXF1C_F1S_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1S_SHIFT) & MCAN_RXF1C_F1S_MASK) +#define MCAN_RXF1C_F1S_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1S_MASK) >> MCAN_RXF1C_F1S_SHIFT) + +/* + * F1SA (RW) + * + * Rx FIFO 1 Start Address + * Start address of Rx FIFO 1 in Message RAM (32-bit word address) + */ +#define MCAN_RXF1C_F1SA_MASK (0xFFFCU) +#define MCAN_RXF1C_F1SA_SHIFT (2U) +#define MCAN_RXF1C_F1SA_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1SA_SHIFT) & MCAN_RXF1C_F1SA_MASK) +#define MCAN_RXF1C_F1SA_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1SA_MASK) >> MCAN_RXF1C_F1SA_SHIFT) + +/* Bitfield definition for register: RXF1S */ +/* + * DMS (R) + * + * Debug Message Status + * 00= Idle state, wait for reception of debug messages, DMA request is cleared + * 01= Debug message A received + * 10= Debug messages A, B received + * 11= Debug messages A, B, C received, DMA request is set + */ +#define MCAN_RXF1S_DMS_MASK (0xC0000000UL) +#define MCAN_RXF1S_DMS_SHIFT (30U) +#define MCAN_RXF1S_DMS_GET(x) (((uint32_t)(x) & MCAN_RXF1S_DMS_MASK) >> MCAN_RXF1S_DMS_SHIFT) + +/* + * RF1L (R) + * + * Rx FIFO 1 Message Lost + * This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. + * 0= No Rx FIFO 1 message lost + * 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + * Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. + */ +#define MCAN_RXF1S_RF1L_MASK (0x2000000UL) +#define MCAN_RXF1S_RF1L_SHIFT (25U) +#define MCAN_RXF1S_RF1L_GET(x) (((uint32_t)(x) & MCAN_RXF1S_RF1L_MASK) >> MCAN_RXF1S_RF1L_SHIFT) + +/* + * F1F (R) + * + * Rx FIFO 1 Full + * 0= Rx FIFO 1 not full + * 1= Rx FIFO 1 full + */ +#define MCAN_RXF1S_F1F_MASK (0x1000000UL) +#define MCAN_RXF1S_F1F_SHIFT (24U) +#define MCAN_RXF1S_F1F_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1F_MASK) >> MCAN_RXF1S_F1F_SHIFT) + +/* + * F1PI (R) + * + * Rx FIFO 1 Put Index + * Rx FIFO 1 write index pointer, range 0 to 63. + */ +#define MCAN_RXF1S_F1PI_MASK (0x3F0000UL) +#define MCAN_RXF1S_F1PI_SHIFT (16U) +#define MCAN_RXF1S_F1PI_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1PI_MASK) >> MCAN_RXF1S_F1PI_SHIFT) + +/* + * F1GI (R) + * + * Rx FIFO 1 Get Index + * Rx FIFO 1 read index pointer, range 0 to 63. + */ +#define MCAN_RXF1S_F1GI_MASK (0x3F00U) +#define MCAN_RXF1S_F1GI_SHIFT (8U) +#define MCAN_RXF1S_F1GI_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1GI_MASK) >> MCAN_RXF1S_F1GI_SHIFT) + +/* + * F1FL (R) + * + * Rx FIFO 1 Fill Level + * Number of elements stored in Rx FIFO 1, range 0 to 64. + */ +#define MCAN_RXF1S_F1FL_MASK (0x7FU) +#define MCAN_RXF1S_F1FL_SHIFT (0U) +#define MCAN_RXF1S_F1FL_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1FL_MASK) >> MCAN_RXF1S_F1FL_SHIFT) + +/* Bitfield definition for register: RXF1A */ +/* + * F1AI (RW) + * + * Rx FIFO 1 Acknowledge Index + * After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + */ +#define MCAN_RXF1A_F1AI_MASK (0x3FU) +#define MCAN_RXF1A_F1AI_SHIFT (0U) +#define MCAN_RXF1A_F1AI_SET(x) (((uint32_t)(x) << MCAN_RXF1A_F1AI_SHIFT) & MCAN_RXF1A_F1AI_MASK) +#define MCAN_RXF1A_F1AI_GET(x) (((uint32_t)(x) & MCAN_RXF1A_F1AI_MASK) >> MCAN_RXF1A_F1AI_SHIFT) + +/* Bitfield definition for register: RXESC */ +/* + * RBDS (RW) + * + * Rx Buffer Data Field Size + * 000= 8 byte data field + * 001= 12 byte data field + * 010= 16 byte data field + * 011= 20 byte data field + * 100= 24 byte data field + * 101= 32 byte data field + * 110= 48 byte data field + * 111= 64 byte data field + */ +#define MCAN_RXESC_RBDS_MASK (0x700U) +#define MCAN_RXESC_RBDS_SHIFT (8U) +#define MCAN_RXESC_RBDS_SET(x) (((uint32_t)(x) << MCAN_RXESC_RBDS_SHIFT) & MCAN_RXESC_RBDS_MASK) +#define MCAN_RXESC_RBDS_GET(x) (((uint32_t)(x) & MCAN_RXESC_RBDS_MASK) >> MCAN_RXESC_RBDS_SHIFT) + +/* + * F1DS (RW) + * + * Rx FIFO 1 Data Field Size + * 000= 8 byte data field + * 001= 12 byte data field + * 010= 16 byte data field + * 011= 20 byte data field + * 100= 24 byte data field + * 101= 32 byte data field + * 110= 48 byte data field + * 111= 64 byte data field + */ +#define MCAN_RXESC_F1DS_MASK (0x70U) +#define MCAN_RXESC_F1DS_SHIFT (4U) +#define MCAN_RXESC_F1DS_SET(x) (((uint32_t)(x) << MCAN_RXESC_F1DS_SHIFT) & MCAN_RXESC_F1DS_MASK) +#define MCAN_RXESC_F1DS_GET(x) (((uint32_t)(x) & MCAN_RXESC_F1DS_MASK) >> MCAN_RXESC_F1DS_SHIFT) + +/* + * F0DS (RW) + * + * Rx FIFO 0 Data Field Size + * 000= 8 byte data field + * 001= 12 byte data field + * 010= 16 byte data field + * 011= 20 byte data field + * 100= 24 byte data field + * 101= 32 byte data field + * 110= 48 byte data field + * 111= 64 byte data field + * Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. + */ +#define MCAN_RXESC_F0DS_MASK (0x7U) +#define MCAN_RXESC_F0DS_SHIFT (0U) +#define MCAN_RXESC_F0DS_SET(x) (((uint32_t)(x) << MCAN_RXESC_F0DS_SHIFT) & MCAN_RXESC_F0DS_MASK) +#define MCAN_RXESC_F0DS_GET(x) (((uint32_t)(x) & MCAN_RXESC_F0DS_MASK) >> MCAN_RXESC_F0DS_SHIFT) + +/* Bitfield definition for register: TXBC */ +/* + * TFQM (RW) + * + * Tx FIFO/Queue Mode + * 0= Tx FIFO operation + * 1= Tx Queue operation + */ +#define MCAN_TXBC_TFQM_MASK (0x40000000UL) +#define MCAN_TXBC_TFQM_SHIFT (30U) +#define MCAN_TXBC_TFQM_SET(x) (((uint32_t)(x) << MCAN_TXBC_TFQM_SHIFT) & MCAN_TXBC_TFQM_MASK) +#define MCAN_TXBC_TFQM_GET(x) (((uint32_t)(x) & MCAN_TXBC_TFQM_MASK) >> MCAN_TXBC_TFQM_SHIFT) + +/* + * TFQS (RW) + * + * Transmit FIFO/Queue Size + * 0= No Tx FIFO/Queue + * 1-32= Number of Tx Buffers used for Tx FIFO/Queue + * >32= Values greater than 32 are interpreted as 32 + */ +#define MCAN_TXBC_TFQS_MASK (0x3F000000UL) +#define MCAN_TXBC_TFQS_SHIFT (24U) +#define MCAN_TXBC_TFQS_SET(x) (((uint32_t)(x) << MCAN_TXBC_TFQS_SHIFT) & MCAN_TXBC_TFQS_MASK) +#define MCAN_TXBC_TFQS_GET(x) (((uint32_t)(x) & MCAN_TXBC_TFQS_MASK) >> MCAN_TXBC_TFQS_SHIFT) + +/* + * NDTB (RW) + * + * Number of Dedicated Transmit Buffers + * 0= No Dedicated Tx Buffers + * 1-32= Number of Dedicated Tx Buffers + * >32= Values greater than 32 are interpreted as 32 + */ +#define MCAN_TXBC_NDTB_MASK (0x3F0000UL) +#define MCAN_TXBC_NDTB_SHIFT (16U) +#define MCAN_TXBC_NDTB_SET(x) (((uint32_t)(x) << MCAN_TXBC_NDTB_SHIFT) & MCAN_TXBC_NDTB_MASK) +#define MCAN_TXBC_NDTB_GET(x) (((uint32_t)(x) & MCAN_TXBC_NDTB_MASK) >> MCAN_TXBC_NDTB_SHIFT) + +/* + * TBSA (RW) + * + * Tx Buffers Start Address + * Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). + * Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. + */ +#define MCAN_TXBC_TBSA_MASK (0xFFFCU) +#define MCAN_TXBC_TBSA_SHIFT (2U) +#define MCAN_TXBC_TBSA_SET(x) (((uint32_t)(x) << MCAN_TXBC_TBSA_SHIFT) & MCAN_TXBC_TBSA_MASK) +#define MCAN_TXBC_TBSA_GET(x) (((uint32_t)(x) & MCAN_TXBC_TBSA_MASK) >> MCAN_TXBC_TBSA_SHIFT) + +/* Bitfield definition for register: TXFQS */ +/* + * TFQF (R) + * + * Tx FIFO/Queue Full + * 0= Tx FIFO/Queue not full + * 1= Tx FIFO/Queue full + */ +#define MCAN_TXFQS_TFQF_MASK (0x200000UL) +#define MCAN_TXFQS_TFQF_SHIFT (21U) +#define MCAN_TXFQS_TFQF_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFQF_MASK) >> MCAN_TXFQS_TFQF_SHIFT) + +/* + * TFQPI (R) + * + * Tx FIFO/Queue Put Index + * Tx FIFO/Queue write index pointer, range 0 to 31. + */ +#define MCAN_TXFQS_TFQPI_MASK (0x1F0000UL) +#define MCAN_TXFQS_TFQPI_SHIFT (16U) +#define MCAN_TXFQS_TFQPI_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFQPI_MASK) >> MCAN_TXFQS_TFQPI_SHIFT) + +/* + * TFGI (R) + * + * Tx FIFO Get Index + * Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured + * (TXBC.TFQM = ‘1’). + */ +#define MCAN_TXFQS_TFGI_MASK (0x1F00U) +#define MCAN_TXFQS_TFGI_SHIFT (8U) +#define MCAN_TXFQS_TFGI_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFGI_MASK) >> MCAN_TXFQS_TFGI_SHIFT) + +/* + * TFFL (R) + * + * Tx FIFO Free Level + * Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) + * Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with + * the first dedicated Tx Buffers. + * Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. + */ +#define MCAN_TXFQS_TFFL_MASK (0x3FU) +#define MCAN_TXFQS_TFFL_SHIFT (0U) +#define MCAN_TXFQS_TFFL_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFFL_MASK) >> MCAN_TXFQS_TFFL_SHIFT) + +/* Bitfield definition for register: TXESC */ +/* + * TBDS (RW) + * + * Tx Buffer Data Field Size + * 000= 8 byte data field + * 001= 12 byte data field + * 010= 16 byte data field + * 011= 20 byte data field + * 100= 24 byte data field + * 101= 32 byte data field + * 110= 48 byte data field + * 111= 64 byte data field + * Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). + */ +#define MCAN_TXESC_TBDS_MASK (0x7U) +#define MCAN_TXESC_TBDS_SHIFT (0U) +#define MCAN_TXESC_TBDS_SET(x) (((uint32_t)(x) << MCAN_TXESC_TBDS_SHIFT) & MCAN_TXESC_TBDS_MASK) +#define MCAN_TXESC_TBDS_GET(x) (((uint32_t)(x) & MCAN_TXESC_TBDS_MASK) >> MCAN_TXESC_TBDS_SHIFT) + +/* Bitfield definition for register: TXBRP */ +/* + * TRP (R) + * + * Transmission Request Pending + * Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register + * TXBCR. + * TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the + * highest priority (Tx Buffer with lowest Message ID). + * A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. + * After a cancellation has been requested, a finished cancellation is signalled via TXBCF + * ? after successful transmission together with the corresponding TXBTO bit + * ? when the transmission has not yet been started at the point of cancellation + * ? when the transmission has been aborted due to lost arbitration + * ? when an error occurred during frame transmission + * In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. + * 0= No transmission request pending + * 1= Transmission request pending + * Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. + */ +#define MCAN_TXBRP_TRP_MASK (0xFFFFFFFFUL) +#define MCAN_TXBRP_TRP_SHIFT (0U) +#define MCAN_TXBRP_TRP_GET(x) (((uint32_t)(x) & MCAN_TXBRP_TRP_MASK) >> MCAN_TXBRP_TRP_SHIFT) + +/* Bitfield definition for register: TXBAR */ +/* + * AR (RW) + * + * Add Request + * Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx + * Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. + * When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. + * 0= No transmission request added + * 1= Transmission requested added + * Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. + */ +#define MCAN_TXBAR_AR_MASK (0xFFFFFFFFUL) +#define MCAN_TXBAR_AR_SHIFT (0U) +#define MCAN_TXBAR_AR_SET(x) (((uint32_t)(x) << MCAN_TXBAR_AR_SHIFT) & MCAN_TXBAR_AR_MASK) +#define MCAN_TXBAR_AR_GET(x) (((uint32_t)(x) & MCAN_TXBAR_AR_MASK) >> MCAN_TXBAR_AR_SHIFT) + +/* Bitfield definition for register: TXBCR */ +/* + * CR (RW) + * + * Cancellation Request + * Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. + * 0= No cancellation pending + * 1= Cancellation pending + */ +#define MCAN_TXBCR_CR_MASK (0xFFFFFFFFUL) +#define MCAN_TXBCR_CR_SHIFT (0U) +#define MCAN_TXBCR_CR_SET(x) (((uint32_t)(x) << MCAN_TXBCR_CR_SHIFT) & MCAN_TXBCR_CR_MASK) +#define MCAN_TXBCR_CR_GET(x) (((uint32_t)(x) & MCAN_TXBCR_CR_MASK) >> MCAN_TXBCR_CR_SHIFT) + +/* Bitfield definition for register: TXBTO */ +/* + * TO (R) + * + * Transmission Occurred + * Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. + * 0= No transmission occurred + * 1= Transmission occurred + */ +#define MCAN_TXBTO_TO_MASK (0xFFFFFFFFUL) +#define MCAN_TXBTO_TO_SHIFT (0U) +#define MCAN_TXBTO_TO_GET(x) (((uint32_t)(x) & MCAN_TXBTO_TO_MASK) >> MCAN_TXBTO_TO_SHIFT) + +/* Bitfield definition for register: TXBCF */ +/* + * CF (R) + * + * Cancellation Finished + * Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. + * 0= No transmit buffer cancellation + * 1= Transmit buffer cancellation finished + */ +#define MCAN_TXBCF_CF_MASK (0xFFFFFFFFUL) +#define MCAN_TXBCF_CF_SHIFT (0U) +#define MCAN_TXBCF_CF_GET(x) (((uint32_t)(x) & MCAN_TXBCF_CF_MASK) >> MCAN_TXBCF_CF_SHIFT) + +/* Bitfield definition for register: TXBTIE */ +/* + * TIE (RW) + * + * Transmission Interrupt Enable + * Each Tx Buffer has its own Transmission Interrupt Enable bit. + * 0= Transmission interrupt disabled + * 1= Transmission interrupt enable + */ +#define MCAN_TXBTIE_TIE_MASK (0xFFFFFFFFUL) +#define MCAN_TXBTIE_TIE_SHIFT (0U) +#define MCAN_TXBTIE_TIE_SET(x) (((uint32_t)(x) << MCAN_TXBTIE_TIE_SHIFT) & MCAN_TXBTIE_TIE_MASK) +#define MCAN_TXBTIE_TIE_GET(x) (((uint32_t)(x) & MCAN_TXBTIE_TIE_MASK) >> MCAN_TXBTIE_TIE_SHIFT) + +/* Bitfield definition for register: TXBCIE */ +/* + * CFIE (RW) + * + * Cancellation Finished Interrupt Enable + * Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. + * 0= Cancellation finished interrupt disabled + * 1= Cancellation finished interrupt enabled + */ +#define MCAN_TXBCIE_CFIE_MASK (0xFFFFFFFFUL) +#define MCAN_TXBCIE_CFIE_SHIFT (0U) +#define MCAN_TXBCIE_CFIE_SET(x) (((uint32_t)(x) << MCAN_TXBCIE_CFIE_SHIFT) & MCAN_TXBCIE_CFIE_MASK) +#define MCAN_TXBCIE_CFIE_GET(x) (((uint32_t)(x) & MCAN_TXBCIE_CFIE_MASK) >> MCAN_TXBCIE_CFIE_SHIFT) + +/* Bitfield definition for register: TXEFC */ +/* + * EFWM (RW) + * + * Event FIFO Watermark + * 0= Watermark interrupt disabled + * 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) + * >32= Watermark interrupt disabled + */ +#define MCAN_TXEFC_EFWM_MASK (0x3F000000UL) +#define MCAN_TXEFC_EFWM_SHIFT (24U) +#define MCAN_TXEFC_EFWM_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFWM_SHIFT) & MCAN_TXEFC_EFWM_MASK) +#define MCAN_TXEFC_EFWM_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFWM_MASK) >> MCAN_TXEFC_EFWM_SHIFT) + +/* + * EFS (RW) + * + * Event FIFO Size + * 0= Tx Event FIFO disabled + * 1-32= Number of Tx Event FIFO elements + * >32= Values greater than 32 are interpreted as 32 + * The Tx Event FIFO elements are indexed from 0 to EFS - 1 + */ +#define MCAN_TXEFC_EFS_MASK (0x3F0000UL) +#define MCAN_TXEFC_EFS_SHIFT (16U) +#define MCAN_TXEFC_EFS_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFS_SHIFT) & MCAN_TXEFC_EFS_MASK) +#define MCAN_TXEFC_EFS_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFS_MASK) >> MCAN_TXEFC_EFS_SHIFT) + +/* + * EFSA (RW) + * + * Event FIFO Start Address + * Start address of Tx Event FIFO in Message RAM (32-bit word address) + */ +#define MCAN_TXEFC_EFSA_MASK (0xFFFCU) +#define MCAN_TXEFC_EFSA_SHIFT (2U) +#define MCAN_TXEFC_EFSA_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFSA_SHIFT) & MCAN_TXEFC_EFSA_MASK) +#define MCAN_TXEFC_EFSA_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFSA_MASK) >> MCAN_TXEFC_EFSA_SHIFT) + +/* Bitfield definition for register: TXEFS */ +/* + * TEFL (R) + * + * Tx Event FIFO Element Lost + * This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. + * 0= No Tx Event FIFO element lost + * 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + */ +#define MCAN_TXEFS_TEFL_MASK (0x2000000UL) +#define MCAN_TXEFS_TEFL_SHIFT (25U) +#define MCAN_TXEFS_TEFL_GET(x) (((uint32_t)(x) & MCAN_TXEFS_TEFL_MASK) >> MCAN_TXEFS_TEFL_SHIFT) + +/* + * EFF (R) + * + * Event FIFO Full + * 0= Tx Event FIFO not full + * 1= Tx Event FIFO full + */ +#define MCAN_TXEFS_EFF_MASK (0x1000000UL) +#define MCAN_TXEFS_EFF_SHIFT (24U) +#define MCAN_TXEFS_EFF_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFF_MASK) >> MCAN_TXEFS_EFF_SHIFT) + +/* + * EFPI (R) + * + * Event FIFO Put Index + * Tx Event FIFO write index pointer, range 0 to 31. + */ +#define MCAN_TXEFS_EFPI_MASK (0x1F0000UL) +#define MCAN_TXEFS_EFPI_SHIFT (16U) +#define MCAN_TXEFS_EFPI_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFPI_MASK) >> MCAN_TXEFS_EFPI_SHIFT) + +/* + * EFGI (R) + * + * Event FIFO Get Index + * Tx Event FIFO read index pointer, range 0 to 31. + */ +#define MCAN_TXEFS_EFGI_MASK (0x1F00U) +#define MCAN_TXEFS_EFGI_SHIFT (8U) +#define MCAN_TXEFS_EFGI_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFGI_MASK) >> MCAN_TXEFS_EFGI_SHIFT) + +/* + * EFFL (R) + * + * Event FIFO Fill Level + * Number of elements stored in Tx Event FIFO, range 0 to 32. + */ +#define MCAN_TXEFS_EFFL_MASK (0x3FU) +#define MCAN_TXEFS_EFFL_SHIFT (0U) +#define MCAN_TXEFS_EFFL_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFFL_MASK) >> MCAN_TXEFS_EFFL_SHIFT) + +/* Bitfield definition for register: TXEFA */ +/* + * EFAI (RW) + * + * Event FIFO Acknowledge Index + * After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get + * Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. + */ +#define MCAN_TXEFA_EFAI_MASK (0x1FU) +#define MCAN_TXEFA_EFAI_SHIFT (0U) +#define MCAN_TXEFA_EFAI_SET(x) (((uint32_t)(x) << MCAN_TXEFA_EFAI_SHIFT) & MCAN_TXEFA_EFAI_MASK) +#define MCAN_TXEFA_EFAI_GET(x) (((uint32_t)(x) & MCAN_TXEFA_EFAI_MASK) >> MCAN_TXEFA_EFAI_SHIFT) + +/* Bitfield definition for register array: TS_SEL */ +/* + * TS (R) + * + * Timestamp Word TS + * default can save 16 timestamps with 32bit; + * if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + */ +#define MCAN_TS_SEL_TS_MASK (0xFFFFFFFFUL) +#define MCAN_TS_SEL_TS_SHIFT (0U) +#define MCAN_TS_SEL_TS_GET(x) (((uint32_t)(x) & MCAN_TS_SEL_TS_MASK) >> MCAN_TS_SEL_TS_SHIFT) + +/* Bitfield definition for register: CREL */ +/* + * REL (R) + * + * Core Release + * One digit, BCD-coded + */ +#define MCAN_CREL_REL_MASK (0xF0000000UL) +#define MCAN_CREL_REL_SHIFT (28U) +#define MCAN_CREL_REL_GET(x) (((uint32_t)(x) & MCAN_CREL_REL_MASK) >> MCAN_CREL_REL_SHIFT) + +/* + * STEP (R) + * + * Step of Core Release + * One digit, BCD-coded. + */ +#define MCAN_CREL_STEP_MASK (0xF000000UL) +#define MCAN_CREL_STEP_SHIFT (24U) +#define MCAN_CREL_STEP_GET(x) (((uint32_t)(x) & MCAN_CREL_STEP_MASK) >> MCAN_CREL_STEP_SHIFT) + +/* + * SUBSTEP (R) + * + * Sub-step of Core Release + * One digit, BCD-coded + */ +#define MCAN_CREL_SUBSTEP_MASK (0xF00000UL) +#define MCAN_CREL_SUBSTEP_SHIFT (20U) +#define MCAN_CREL_SUBSTEP_GET(x) (((uint32_t)(x) & MCAN_CREL_SUBSTEP_MASK) >> MCAN_CREL_SUBSTEP_SHIFT) + +/* + * YEAR (R) + * + * Timestamp Year + * One digit, BCD-coded. This field is set by generic parameter on + * synthesis. + */ +#define MCAN_CREL_YEAR_MASK (0xF0000UL) +#define MCAN_CREL_YEAR_SHIFT (16U) +#define MCAN_CREL_YEAR_GET(x) (((uint32_t)(x) & MCAN_CREL_YEAR_MASK) >> MCAN_CREL_YEAR_SHIFT) + +/* + * MON (R) + * + * Timestamp Month + * Two digits, BCD-coded. This field is set by generic parameter + * on synthesis. + */ +#define MCAN_CREL_MON_MASK (0xFF00U) +#define MCAN_CREL_MON_SHIFT (8U) +#define MCAN_CREL_MON_GET(x) (((uint32_t)(x) & MCAN_CREL_MON_MASK) >> MCAN_CREL_MON_SHIFT) + +/* + * DAY (R) + * + * Timestamp Day + * Two digits, BCD-coded. This field is set by generic parameter + * on synthesis. + */ +#define MCAN_CREL_DAY_MASK (0xFFU) +#define MCAN_CREL_DAY_SHIFT (0U) +#define MCAN_CREL_DAY_GET(x) (((uint32_t)(x) & MCAN_CREL_DAY_MASK) >> MCAN_CREL_DAY_SHIFT) + +/* Bitfield definition for register: TSCFG */ +/* + * TBPRE (RW) + * + * Timebase Prescaler + * 0x00 to 0xFF + * The value by which the oscillator frequency is divided for + * generating the timebase counter clock. Valid values for the + * Timebase Prescaler are 0 to 255. The actual interpretation by + * the hardware of this value is such that one more than the value + * programmed here is used. Affects only the TSU internal + * timebase. When the internal timebase is excluded by synthesis, + * TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not + * used. + */ +#define MCAN_TSCFG_TBPRE_MASK (0xFF00U) +#define MCAN_TSCFG_TBPRE_SHIFT (8U) +#define MCAN_TSCFG_TBPRE_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TBPRE_SHIFT) & MCAN_TSCFG_TBPRE_MASK) +#define MCAN_TSCFG_TBPRE_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TBPRE_MASK) >> MCAN_TSCFG_TBPRE_SHIFT) + +/* + * EN64 (RW) + * + * set to use 64bit timestamp. + * when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. + * TSP can be used to select different one + */ +#define MCAN_TSCFG_EN64_MASK (0x8U) +#define MCAN_TSCFG_EN64_SHIFT (3U) +#define MCAN_TSCFG_EN64_SET(x) (((uint32_t)(x) << MCAN_TSCFG_EN64_SHIFT) & MCAN_TSCFG_EN64_MASK) +#define MCAN_TSCFG_EN64_GET(x) (((uint32_t)(x) & MCAN_TSCFG_EN64_MASK) >> MCAN_TSCFG_EN64_SHIFT) + +/* + * SCP (RW) + * + * Select Capturing Position + * 0: Capture Timestamp at EOF + * 1: Capture Timestamp at SOF + */ +#define MCAN_TSCFG_SCP_MASK (0x4U) +#define MCAN_TSCFG_SCP_SHIFT (2U) +#define MCAN_TSCFG_SCP_SET(x) (((uint32_t)(x) << MCAN_TSCFG_SCP_SHIFT) & MCAN_TSCFG_SCP_MASK) +#define MCAN_TSCFG_SCP_GET(x) (((uint32_t)(x) & MCAN_TSCFG_SCP_MASK) >> MCAN_TSCFG_SCP_SHIFT) + +/* + * TBCS (RW) + * + * Timebase Counter Select + * When the internal timebase is excluded by synthesis, TBCS is + * fixed to ‘1’. + * 0: Timestamp value captured from internal timebase counter, + * ATB.TB[31:0] is the internal timbase counter + * 1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] + */ +#define MCAN_TSCFG_TBCS_MASK (0x2U) +#define MCAN_TSCFG_TBCS_SHIFT (1U) +#define MCAN_TSCFG_TBCS_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TBCS_SHIFT) & MCAN_TSCFG_TBCS_MASK) +#define MCAN_TSCFG_TBCS_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TBCS_MASK) >> MCAN_TSCFG_TBCS_SHIFT) + +/* + * TSUE (RW) + * + * Timestamp Unit Enable + * 0: TSU disabled + * 1: TSU enabled + */ +#define MCAN_TSCFG_TSUE_MASK (0x1U) +#define MCAN_TSCFG_TSUE_SHIFT (0U) +#define MCAN_TSCFG_TSUE_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TSUE_SHIFT) & MCAN_TSCFG_TSUE_MASK) +#define MCAN_TSCFG_TSUE_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TSUE_MASK) >> MCAN_TSCFG_TSUE_SHIFT) + +/* Bitfield definition for register: TSS1 */ +/* + * TSL (R) + * + * Timestamp Lost + * Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. + * Reading a Timestamp register resets the related bit. + */ +#define MCAN_TSS1_TSL_MASK (0xFFFF0000UL) +#define MCAN_TSS1_TSL_SHIFT (16U) +#define MCAN_TSS1_TSL_GET(x) (((uint32_t)(x) & MCAN_TSS1_TSL_MASK) >> MCAN_TSS1_TSL_SHIFT) + +/* + * TSN (R) + * + * Timestamp New + * Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related + * Timestamp register. Reading a Timestamp register resets the related bit. + */ +#define MCAN_TSS1_TSN_MASK (0xFFFFU) +#define MCAN_TSS1_TSN_SHIFT (0U) +#define MCAN_TSS1_TSN_GET(x) (((uint32_t)(x) & MCAN_TSS1_TSN_MASK) >> MCAN_TSS1_TSN_SHIFT) + +/* Bitfield definition for register: TSS2 */ +/* + * TSP (R) + * + * Timestamp Pointer + * The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 + * depending on number_ts_g), it is incremented to 0. + * Value also signalled on output m_can_tsp[3:0]. + */ +#define MCAN_TSS2_TSP_MASK (0xFU) +#define MCAN_TSS2_TSP_SHIFT (0U) +#define MCAN_TSS2_TSP_GET(x) (((uint32_t)(x) & MCAN_TSS2_TSP_MASK) >> MCAN_TSS2_TSP_SHIFT) + +/* Bitfield definition for register: ATB */ +/* + * TB (RC) + * + * timebase for timestamp generation 31-0 + */ +#define MCAN_ATB_TB_MASK (0xFFFFFFFFUL) +#define MCAN_ATB_TB_SHIFT (0U) +#define MCAN_ATB_TB_GET(x) (((uint32_t)(x) & MCAN_ATB_TB_MASK) >> MCAN_ATB_TB_SHIFT) + +/* Bitfield definition for register: ATBH */ +/* + * TBH (RC) + * + * timebase for timestamp generation 63-32 + */ +#define MCAN_ATBH_TBH_MASK (0xFFFFFFFFUL) +#define MCAN_ATBH_TBH_SHIFT (0U) +#define MCAN_ATBH_TBH_GET(x) (((uint32_t)(x) & MCAN_ATBH_TBH_MASK) >> MCAN_ATBH_TBH_SHIFT) + +/* Bitfield definition for register: GLB_CTL */ +/* + * M_CAN_STBY (RW) + * + * m_can standby control + */ +#define MCAN_GLB_CTL_M_CAN_STBY_MASK (0x80000000UL) +#define MCAN_GLB_CTL_M_CAN_STBY_SHIFT (31U) +#define MCAN_GLB_CTL_M_CAN_STBY_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_M_CAN_STBY_SHIFT) & MCAN_GLB_CTL_M_CAN_STBY_MASK) +#define MCAN_GLB_CTL_M_CAN_STBY_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_M_CAN_STBY_MASK) >> MCAN_GLB_CTL_M_CAN_STBY_SHIFT) + +/* + * STBY_CLR_EN (RW) + * + * m_can standby clear control + * 0:controlled by software by standby bit[bit31] + * 1:auto clear standby by hardware when rx data is 0 + */ +#define MCAN_GLB_CTL_STBY_CLR_EN_MASK (0x40000000UL) +#define MCAN_GLB_CTL_STBY_CLR_EN_SHIFT (30U) +#define MCAN_GLB_CTL_STBY_CLR_EN_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_STBY_CLR_EN_SHIFT) & MCAN_GLB_CTL_STBY_CLR_EN_MASK) +#define MCAN_GLB_CTL_STBY_CLR_EN_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_STBY_CLR_EN_MASK) >> MCAN_GLB_CTL_STBY_CLR_EN_SHIFT) + +/* + * STBY_POL (RW) + * + * standby polarity selection + */ +#define MCAN_GLB_CTL_STBY_POL_MASK (0x20000000UL) +#define MCAN_GLB_CTL_STBY_POL_SHIFT (29U) +#define MCAN_GLB_CTL_STBY_POL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_STBY_POL_SHIFT) & MCAN_GLB_CTL_STBY_POL_MASK) +#define MCAN_GLB_CTL_STBY_POL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_STBY_POL_MASK) >> MCAN_GLB_CTL_STBY_POL_SHIFT) + +/* + * TSU_TBIN_SEL (RW) + * + */ +#define MCAN_GLB_CTL_TSU_TBIN_SEL_MASK (0x7U) +#define MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT (0U) +#define MCAN_GLB_CTL_TSU_TBIN_SEL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) +#define MCAN_GLB_CTL_TSU_TBIN_SEL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) >> MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) + +/* Bitfield definition for register: GLB_STATUS */ +/* + * M_CAN_INT1 (R) + * + * m_can interrupt status1 + */ +#define MCAN_GLB_STATUS_M_CAN_INT1_MASK (0x8U) +#define MCAN_GLB_STATUS_M_CAN_INT1_SHIFT (3U) +#define MCAN_GLB_STATUS_M_CAN_INT1_GET(x) (((uint32_t)(x) & MCAN_GLB_STATUS_M_CAN_INT1_MASK) >> MCAN_GLB_STATUS_M_CAN_INT1_SHIFT) + +/* + * M_CAN_INT0 (R) + * + * m_can interrupt status0 + */ +#define MCAN_GLB_STATUS_M_CAN_INT0_MASK (0x4U) +#define MCAN_GLB_STATUS_M_CAN_INT0_SHIFT (2U) +#define MCAN_GLB_STATUS_M_CAN_INT0_GET(x) (((uint32_t)(x) & MCAN_GLB_STATUS_M_CAN_INT0_MASK) >> MCAN_GLB_STATUS_M_CAN_INT0_SHIFT) + +/* Bitfield definition for register array: MESSAGE_BUFF */ +/* + * DATA (RW) + * + * m_can message buffer + */ +#define MCAN_MESSAGE_BUFF_DATA_MASK (0xFFFFFFFFUL) +#define MCAN_MESSAGE_BUFF_DATA_SHIFT (0U) +#define MCAN_MESSAGE_BUFF_DATA_SET(x) (((uint32_t)(x) << MCAN_MESSAGE_BUFF_DATA_SHIFT) & MCAN_MESSAGE_BUFF_DATA_MASK) +#define MCAN_MESSAGE_BUFF_DATA_GET(x) (((uint32_t)(x) & MCAN_MESSAGE_BUFF_DATA_MASK) >> MCAN_MESSAGE_BUFF_DATA_SHIFT) + + + +/* TS_SEL register group index macro definition */ +#define MCAN_TS_SEL_TS_SEL0 (0UL) +#define MCAN_TS_SEL_TS_SEL1 (1UL) +#define MCAN_TS_SEL_TS_SEL2 (2UL) +#define MCAN_TS_SEL_TS_SEL3 (3UL) +#define MCAN_TS_SEL_TS_SEL4 (4UL) +#define MCAN_TS_SEL_TS_SEL5 (5UL) +#define MCAN_TS_SEL_TS_SEL6 (6UL) +#define MCAN_TS_SEL_TS_SEL7 (7UL) +#define MCAN_TS_SEL_TS_SEL8 (8UL) +#define MCAN_TS_SEL_TS_SEL9 (9UL) +#define MCAN_TS_SEL_TS_SEL10 (10UL) +#define MCAN_TS_SEL_TS_SEL11 (11UL) +#define MCAN_TS_SEL_TS_SEL12 (12UL) +#define MCAN_TS_SEL_TS_SEL13 (13UL) +#define MCAN_TS_SEL_TS_SEL14 (14UL) +#define MCAN_TS_SEL_TS_SEL15 (15UL) + +/* MESSAGE_BUFF register group index macro definition */ +#define MCAN_MESSAGE_BUFF_0 (0UL) +#define MCAN_MESSAGE_BUFF_1 (1UL) +#define MCAN_MESSAGE_BUFF_2 (2UL) +#define MCAN_MESSAGE_BUFF_3 (3UL) +#define MCAN_MESSAGE_BUFF_4 (4UL) +#define MCAN_MESSAGE_BUFF_5 (5UL) +#define MCAN_MESSAGE_BUFF_6 (6UL) +#define MCAN_MESSAGE_BUFF_7 (7UL) +#define MCAN_MESSAGE_BUFF_8 (8UL) +#define MCAN_MESSAGE_BUFF_9 (9UL) +#define MCAN_MESSAGE_BUFF_10 (10UL) +#define MCAN_MESSAGE_BUFF_11 (11UL) +#define MCAN_MESSAGE_BUFF_12 (12UL) +#define MCAN_MESSAGE_BUFF_13 (13UL) +#define MCAN_MESSAGE_BUFF_14 (14UL) +#define MCAN_MESSAGE_BUFF_15 (15UL) +#define MCAN_MESSAGE_BUFF_16 (16UL) +#define MCAN_MESSAGE_BUFF_17 (17UL) +#define MCAN_MESSAGE_BUFF_18 (18UL) +#define MCAN_MESSAGE_BUFF_19 (19UL) +#define MCAN_MESSAGE_BUFF_20 (20UL) +#define MCAN_MESSAGE_BUFF_21 (21UL) +#define MCAN_MESSAGE_BUFF_22 (22UL) +#define MCAN_MESSAGE_BUFF_23 (23UL) +#define MCAN_MESSAGE_BUFF_24 (24UL) +#define MCAN_MESSAGE_BUFF_25 (25UL) +#define MCAN_MESSAGE_BUFF_26 (26UL) +#define MCAN_MESSAGE_BUFF_27 (27UL) +#define MCAN_MESSAGE_BUFF_28 (28UL) +#define MCAN_MESSAGE_BUFF_29 (29UL) +#define MCAN_MESSAGE_BUFF_30 (30UL) +#define MCAN_MESSAGE_BUFF_31 (31UL) +#define MCAN_MESSAGE_BUFF_32 (32UL) +#define MCAN_MESSAGE_BUFF_33 (33UL) +#define MCAN_MESSAGE_BUFF_34 (34UL) +#define MCAN_MESSAGE_BUFF_35 (35UL) +#define MCAN_MESSAGE_BUFF_36 (36UL) +#define MCAN_MESSAGE_BUFF_37 (37UL) +#define MCAN_MESSAGE_BUFF_38 (38UL) +#define MCAN_MESSAGE_BUFF_39 (39UL) +#define MCAN_MESSAGE_BUFF_40 (40UL) +#define MCAN_MESSAGE_BUFF_41 (41UL) +#define MCAN_MESSAGE_BUFF_42 (42UL) +#define MCAN_MESSAGE_BUFF_43 (43UL) +#define MCAN_MESSAGE_BUFF_44 (44UL) +#define MCAN_MESSAGE_BUFF_45 (45UL) +#define MCAN_MESSAGE_BUFF_46 (46UL) +#define MCAN_MESSAGE_BUFF_47 (47UL) +#define MCAN_MESSAGE_BUFF_48 (48UL) +#define MCAN_MESSAGE_BUFF_49 (49UL) +#define MCAN_MESSAGE_BUFF_50 (50UL) +#define MCAN_MESSAGE_BUFF_51 (51UL) +#define MCAN_MESSAGE_BUFF_52 (52UL) +#define MCAN_MESSAGE_BUFF_53 (53UL) +#define MCAN_MESSAGE_BUFF_54 (54UL) +#define MCAN_MESSAGE_BUFF_55 (55UL) +#define MCAN_MESSAGE_BUFF_56 (56UL) +#define MCAN_MESSAGE_BUFF_57 (57UL) +#define MCAN_MESSAGE_BUFF_58 (58UL) +#define MCAN_MESSAGE_BUFF_59 (59UL) +#define MCAN_MESSAGE_BUFF_60 (60UL) +#define MCAN_MESSAGE_BUFF_61 (61UL) +#define MCAN_MESSAGE_BUFF_62 (62UL) +#define MCAN_MESSAGE_BUFF_63 (63UL) +#define MCAN_MESSAGE_BUFF_64 (64UL) +#define MCAN_MESSAGE_BUFF_65 (65UL) +#define MCAN_MESSAGE_BUFF_66 (66UL) +#define MCAN_MESSAGE_BUFF_67 (67UL) +#define MCAN_MESSAGE_BUFF_68 (68UL) +#define MCAN_MESSAGE_BUFF_69 (69UL) +#define MCAN_MESSAGE_BUFF_70 (70UL) +#define MCAN_MESSAGE_BUFF_71 (71UL) +#define MCAN_MESSAGE_BUFF_72 (72UL) +#define MCAN_MESSAGE_BUFF_73 (73UL) +#define MCAN_MESSAGE_BUFF_74 (74UL) +#define MCAN_MESSAGE_BUFF_75 (75UL) +#define MCAN_MESSAGE_BUFF_76 (76UL) +#define MCAN_MESSAGE_BUFF_77 (77UL) +#define MCAN_MESSAGE_BUFF_78 (78UL) +#define MCAN_MESSAGE_BUFF_79 (79UL) +#define MCAN_MESSAGE_BUFF_80 (80UL) +#define MCAN_MESSAGE_BUFF_81 (81UL) +#define MCAN_MESSAGE_BUFF_82 (82UL) +#define MCAN_MESSAGE_BUFF_83 (83UL) +#define MCAN_MESSAGE_BUFF_84 (84UL) +#define MCAN_MESSAGE_BUFF_85 (85UL) +#define MCAN_MESSAGE_BUFF_86 (86UL) +#define MCAN_MESSAGE_BUFF_87 (87UL) +#define MCAN_MESSAGE_BUFF_88 (88UL) +#define MCAN_MESSAGE_BUFF_89 (89UL) +#define MCAN_MESSAGE_BUFF_90 (90UL) +#define MCAN_MESSAGE_BUFF_91 (91UL) +#define MCAN_MESSAGE_BUFF_92 (92UL) +#define MCAN_MESSAGE_BUFF_93 (93UL) +#define MCAN_MESSAGE_BUFF_94 (94UL) +#define MCAN_MESSAGE_BUFF_95 (95UL) +#define MCAN_MESSAGE_BUFF_96 (96UL) +#define MCAN_MESSAGE_BUFF_97 (97UL) +#define MCAN_MESSAGE_BUFF_98 (98UL) +#define MCAN_MESSAGE_BUFF_99 (99UL) +#define MCAN_MESSAGE_BUFF_100 (100UL) +#define MCAN_MESSAGE_BUFF_101 (101UL) +#define MCAN_MESSAGE_BUFF_102 (102UL) +#define MCAN_MESSAGE_BUFF_103 (103UL) +#define MCAN_MESSAGE_BUFF_104 (104UL) +#define MCAN_MESSAGE_BUFF_105 (105UL) +#define MCAN_MESSAGE_BUFF_106 (106UL) +#define MCAN_MESSAGE_BUFF_107 (107UL) +#define MCAN_MESSAGE_BUFF_108 (108UL) +#define MCAN_MESSAGE_BUFF_109 (109UL) +#define MCAN_MESSAGE_BUFF_110 (110UL) +#define MCAN_MESSAGE_BUFF_111 (111UL) +#define MCAN_MESSAGE_BUFF_112 (112UL) +#define MCAN_MESSAGE_BUFF_113 (113UL) +#define MCAN_MESSAGE_BUFF_114 (114UL) +#define MCAN_MESSAGE_BUFF_115 (115UL) +#define MCAN_MESSAGE_BUFF_116 (116UL) +#define MCAN_MESSAGE_BUFF_117 (117UL) +#define MCAN_MESSAGE_BUFF_118 (118UL) +#define MCAN_MESSAGE_BUFF_119 (119UL) +#define MCAN_MESSAGE_BUFF_120 (120UL) +#define MCAN_MESSAGE_BUFF_121 (121UL) +#define MCAN_MESSAGE_BUFF_122 (122UL) +#define MCAN_MESSAGE_BUFF_123 (123UL) +#define MCAN_MESSAGE_BUFF_124 (124UL) +#define MCAN_MESSAGE_BUFF_125 (125UL) +#define MCAN_MESSAGE_BUFF_126 (126UL) +#define MCAN_MESSAGE_BUFF_127 (127UL) +#define MCAN_MESSAGE_BUFF_128 (128UL) +#define MCAN_MESSAGE_BUFF_129 (129UL) +#define MCAN_MESSAGE_BUFF_130 (130UL) +#define MCAN_MESSAGE_BUFF_131 (131UL) +#define MCAN_MESSAGE_BUFF_132 (132UL) +#define MCAN_MESSAGE_BUFF_133 (133UL) +#define MCAN_MESSAGE_BUFF_134 (134UL) +#define MCAN_MESSAGE_BUFF_135 (135UL) +#define MCAN_MESSAGE_BUFF_136 (136UL) +#define MCAN_MESSAGE_BUFF_137 (137UL) +#define MCAN_MESSAGE_BUFF_138 (138UL) +#define MCAN_MESSAGE_BUFF_139 (139UL) +#define MCAN_MESSAGE_BUFF_140 (140UL) +#define MCAN_MESSAGE_BUFF_141 (141UL) +#define MCAN_MESSAGE_BUFF_142 (142UL) +#define MCAN_MESSAGE_BUFF_143 (143UL) +#define MCAN_MESSAGE_BUFF_144 (144UL) +#define MCAN_MESSAGE_BUFF_145 (145UL) +#define MCAN_MESSAGE_BUFF_146 (146UL) +#define MCAN_MESSAGE_BUFF_147 (147UL) +#define MCAN_MESSAGE_BUFF_148 (148UL) +#define MCAN_MESSAGE_BUFF_149 (149UL) +#define MCAN_MESSAGE_BUFF_150 (150UL) +#define MCAN_MESSAGE_BUFF_151 (151UL) +#define MCAN_MESSAGE_BUFF_152 (152UL) +#define MCAN_MESSAGE_BUFF_153 (153UL) +#define MCAN_MESSAGE_BUFF_154 (154UL) +#define MCAN_MESSAGE_BUFF_155 (155UL) +#define MCAN_MESSAGE_BUFF_156 (156UL) +#define MCAN_MESSAGE_BUFF_157 (157UL) +#define MCAN_MESSAGE_BUFF_158 (158UL) +#define MCAN_MESSAGE_BUFF_159 (159UL) +#define MCAN_MESSAGE_BUFF_160 (160UL) +#define MCAN_MESSAGE_BUFF_161 (161UL) +#define MCAN_MESSAGE_BUFF_162 (162UL) +#define MCAN_MESSAGE_BUFF_163 (163UL) +#define MCAN_MESSAGE_BUFF_164 (164UL) +#define MCAN_MESSAGE_BUFF_165 (165UL) +#define MCAN_MESSAGE_BUFF_166 (166UL) +#define MCAN_MESSAGE_BUFF_167 (167UL) +#define MCAN_MESSAGE_BUFF_168 (168UL) +#define MCAN_MESSAGE_BUFF_169 (169UL) +#define MCAN_MESSAGE_BUFF_170 (170UL) +#define MCAN_MESSAGE_BUFF_171 (171UL) +#define MCAN_MESSAGE_BUFF_172 (172UL) +#define MCAN_MESSAGE_BUFF_173 (173UL) +#define MCAN_MESSAGE_BUFF_174 (174UL) +#define MCAN_MESSAGE_BUFF_175 (175UL) +#define MCAN_MESSAGE_BUFF_176 (176UL) +#define MCAN_MESSAGE_BUFF_177 (177UL) +#define MCAN_MESSAGE_BUFF_178 (178UL) +#define MCAN_MESSAGE_BUFF_179 (179UL) +#define MCAN_MESSAGE_BUFF_180 (180UL) +#define MCAN_MESSAGE_BUFF_181 (181UL) +#define MCAN_MESSAGE_BUFF_182 (182UL) +#define MCAN_MESSAGE_BUFF_183 (183UL) +#define MCAN_MESSAGE_BUFF_184 (184UL) +#define MCAN_MESSAGE_BUFF_185 (185UL) +#define MCAN_MESSAGE_BUFF_186 (186UL) +#define MCAN_MESSAGE_BUFF_187 (187UL) +#define MCAN_MESSAGE_BUFF_188 (188UL) +#define MCAN_MESSAGE_BUFF_189 (189UL) +#define MCAN_MESSAGE_BUFF_190 (190UL) +#define MCAN_MESSAGE_BUFF_191 (191UL) +#define MCAN_MESSAGE_BUFF_192 (192UL) +#define MCAN_MESSAGE_BUFF_193 (193UL) +#define MCAN_MESSAGE_BUFF_194 (194UL) +#define MCAN_MESSAGE_BUFF_195 (195UL) +#define MCAN_MESSAGE_BUFF_196 (196UL) +#define MCAN_MESSAGE_BUFF_197 (197UL) +#define MCAN_MESSAGE_BUFF_198 (198UL) +#define MCAN_MESSAGE_BUFF_199 (199UL) +#define MCAN_MESSAGE_BUFF_200 (200UL) +#define MCAN_MESSAGE_BUFF_201 (201UL) +#define MCAN_MESSAGE_BUFF_202 (202UL) +#define MCAN_MESSAGE_BUFF_203 (203UL) +#define MCAN_MESSAGE_BUFF_204 (204UL) +#define MCAN_MESSAGE_BUFF_205 (205UL) +#define MCAN_MESSAGE_BUFF_206 (206UL) +#define MCAN_MESSAGE_BUFF_207 (207UL) +#define MCAN_MESSAGE_BUFF_208 (208UL) +#define MCAN_MESSAGE_BUFF_209 (209UL) +#define MCAN_MESSAGE_BUFF_210 (210UL) +#define MCAN_MESSAGE_BUFF_211 (211UL) +#define MCAN_MESSAGE_BUFF_212 (212UL) +#define MCAN_MESSAGE_BUFF_213 (213UL) +#define MCAN_MESSAGE_BUFF_214 (214UL) +#define MCAN_MESSAGE_BUFF_215 (215UL) +#define MCAN_MESSAGE_BUFF_216 (216UL) +#define MCAN_MESSAGE_BUFF_217 (217UL) +#define MCAN_MESSAGE_BUFF_218 (218UL) +#define MCAN_MESSAGE_BUFF_219 (219UL) +#define MCAN_MESSAGE_BUFF_220 (220UL) +#define MCAN_MESSAGE_BUFF_221 (221UL) +#define MCAN_MESSAGE_BUFF_222 (222UL) +#define MCAN_MESSAGE_BUFF_223 (223UL) +#define MCAN_MESSAGE_BUFF_224 (224UL) +#define MCAN_MESSAGE_BUFF_225 (225UL) +#define MCAN_MESSAGE_BUFF_226 (226UL) +#define MCAN_MESSAGE_BUFF_227 (227UL) +#define MCAN_MESSAGE_BUFF_228 (228UL) +#define MCAN_MESSAGE_BUFF_229 (229UL) +#define MCAN_MESSAGE_BUFF_230 (230UL) +#define MCAN_MESSAGE_BUFF_231 (231UL) +#define MCAN_MESSAGE_BUFF_232 (232UL) +#define MCAN_MESSAGE_BUFF_233 (233UL) +#define MCAN_MESSAGE_BUFF_234 (234UL) +#define MCAN_MESSAGE_BUFF_235 (235UL) +#define MCAN_MESSAGE_BUFF_236 (236UL) +#define MCAN_MESSAGE_BUFF_237 (237UL) +#define MCAN_MESSAGE_BUFF_238 (238UL) +#define MCAN_MESSAGE_BUFF_239 (239UL) +#define MCAN_MESSAGE_BUFF_240 (240UL) +#define MCAN_MESSAGE_BUFF_241 (241UL) +#define MCAN_MESSAGE_BUFF_242 (242UL) +#define MCAN_MESSAGE_BUFF_243 (243UL) +#define MCAN_MESSAGE_BUFF_244 (244UL) +#define MCAN_MESSAGE_BUFF_245 (245UL) +#define MCAN_MESSAGE_BUFF_246 (246UL) +#define MCAN_MESSAGE_BUFF_247 (247UL) +#define MCAN_MESSAGE_BUFF_248 (248UL) +#define MCAN_MESSAGE_BUFF_249 (249UL) +#define MCAN_MESSAGE_BUFF_250 (250UL) +#define MCAN_MESSAGE_BUFF_251 (251UL) +#define MCAN_MESSAGE_BUFF_252 (252UL) +#define MCAN_MESSAGE_BUFF_253 (253UL) +#define MCAN_MESSAGE_BUFF_254 (254UL) +#define MCAN_MESSAGE_BUFF_255 (255UL) +#define MCAN_MESSAGE_BUFF_256 (256UL) +#define MCAN_MESSAGE_BUFF_257 (257UL) +#define MCAN_MESSAGE_BUFF_258 (258UL) +#define MCAN_MESSAGE_BUFF_259 (259UL) +#define MCAN_MESSAGE_BUFF_260 (260UL) +#define MCAN_MESSAGE_BUFF_261 (261UL) +#define MCAN_MESSAGE_BUFF_262 (262UL) +#define MCAN_MESSAGE_BUFF_263 (263UL) +#define MCAN_MESSAGE_BUFF_264 (264UL) +#define MCAN_MESSAGE_BUFF_265 (265UL) +#define MCAN_MESSAGE_BUFF_266 (266UL) +#define MCAN_MESSAGE_BUFF_267 (267UL) +#define MCAN_MESSAGE_BUFF_268 (268UL) +#define MCAN_MESSAGE_BUFF_269 (269UL) +#define MCAN_MESSAGE_BUFF_270 (270UL) +#define MCAN_MESSAGE_BUFF_271 (271UL) +#define MCAN_MESSAGE_BUFF_272 (272UL) +#define MCAN_MESSAGE_BUFF_273 (273UL) +#define MCAN_MESSAGE_BUFF_274 (274UL) +#define MCAN_MESSAGE_BUFF_275 (275UL) +#define MCAN_MESSAGE_BUFF_276 (276UL) +#define MCAN_MESSAGE_BUFF_277 (277UL) +#define MCAN_MESSAGE_BUFF_278 (278UL) +#define MCAN_MESSAGE_BUFF_279 (279UL) +#define MCAN_MESSAGE_BUFF_280 (280UL) +#define MCAN_MESSAGE_BUFF_281 (281UL) +#define MCAN_MESSAGE_BUFF_282 (282UL) +#define MCAN_MESSAGE_BUFF_283 (283UL) +#define MCAN_MESSAGE_BUFF_284 (284UL) +#define MCAN_MESSAGE_BUFF_285 (285UL) +#define MCAN_MESSAGE_BUFF_286 (286UL) +#define MCAN_MESSAGE_BUFF_287 (287UL) +#define MCAN_MESSAGE_BUFF_288 (288UL) +#define MCAN_MESSAGE_BUFF_289 (289UL) +#define MCAN_MESSAGE_BUFF_290 (290UL) +#define MCAN_MESSAGE_BUFF_291 (291UL) +#define MCAN_MESSAGE_BUFF_292 (292UL) +#define MCAN_MESSAGE_BUFF_293 (293UL) +#define MCAN_MESSAGE_BUFF_294 (294UL) +#define MCAN_MESSAGE_BUFF_295 (295UL) +#define MCAN_MESSAGE_BUFF_296 (296UL) +#define MCAN_MESSAGE_BUFF_297 (297UL) +#define MCAN_MESSAGE_BUFF_298 (298UL) +#define MCAN_MESSAGE_BUFF_299 (299UL) +#define MCAN_MESSAGE_BUFF_300 (300UL) +#define MCAN_MESSAGE_BUFF_301 (301UL) +#define MCAN_MESSAGE_BUFF_302 (302UL) +#define MCAN_MESSAGE_BUFF_303 (303UL) +#define MCAN_MESSAGE_BUFF_304 (304UL) +#define MCAN_MESSAGE_BUFF_305 (305UL) +#define MCAN_MESSAGE_BUFF_306 (306UL) +#define MCAN_MESSAGE_BUFF_307 (307UL) +#define MCAN_MESSAGE_BUFF_308 (308UL) +#define MCAN_MESSAGE_BUFF_309 (309UL) +#define MCAN_MESSAGE_BUFF_310 (310UL) +#define MCAN_MESSAGE_BUFF_311 (311UL) +#define MCAN_MESSAGE_BUFF_312 (312UL) +#define MCAN_MESSAGE_BUFF_313 (313UL) +#define MCAN_MESSAGE_BUFF_314 (314UL) +#define MCAN_MESSAGE_BUFF_315 (315UL) +#define MCAN_MESSAGE_BUFF_316 (316UL) +#define MCAN_MESSAGE_BUFF_317 (317UL) +#define MCAN_MESSAGE_BUFF_318 (318UL) +#define MCAN_MESSAGE_BUFF_319 (319UL) +#define MCAN_MESSAGE_BUFF_320 (320UL) +#define MCAN_MESSAGE_BUFF_321 (321UL) +#define MCAN_MESSAGE_BUFF_322 (322UL) +#define MCAN_MESSAGE_BUFF_323 (323UL) +#define MCAN_MESSAGE_BUFF_324 (324UL) +#define MCAN_MESSAGE_BUFF_325 (325UL) +#define MCAN_MESSAGE_BUFF_326 (326UL) +#define MCAN_MESSAGE_BUFF_327 (327UL) +#define MCAN_MESSAGE_BUFF_328 (328UL) +#define MCAN_MESSAGE_BUFF_329 (329UL) +#define MCAN_MESSAGE_BUFF_330 (330UL) +#define MCAN_MESSAGE_BUFF_331 (331UL) +#define MCAN_MESSAGE_BUFF_332 (332UL) +#define MCAN_MESSAGE_BUFF_333 (333UL) +#define MCAN_MESSAGE_BUFF_334 (334UL) +#define MCAN_MESSAGE_BUFF_335 (335UL) +#define MCAN_MESSAGE_BUFF_336 (336UL) +#define MCAN_MESSAGE_BUFF_337 (337UL) +#define MCAN_MESSAGE_BUFF_338 (338UL) +#define MCAN_MESSAGE_BUFF_339 (339UL) +#define MCAN_MESSAGE_BUFF_340 (340UL) +#define MCAN_MESSAGE_BUFF_341 (341UL) +#define MCAN_MESSAGE_BUFF_342 (342UL) +#define MCAN_MESSAGE_BUFF_343 (343UL) +#define MCAN_MESSAGE_BUFF_344 (344UL) +#define MCAN_MESSAGE_BUFF_345 (345UL) +#define MCAN_MESSAGE_BUFF_346 (346UL) +#define MCAN_MESSAGE_BUFF_347 (347UL) +#define MCAN_MESSAGE_BUFF_348 (348UL) +#define MCAN_MESSAGE_BUFF_349 (349UL) +#define MCAN_MESSAGE_BUFF_350 (350UL) +#define MCAN_MESSAGE_BUFF_351 (351UL) +#define MCAN_MESSAGE_BUFF_352 (352UL) +#define MCAN_MESSAGE_BUFF_353 (353UL) +#define MCAN_MESSAGE_BUFF_354 (354UL) +#define MCAN_MESSAGE_BUFF_355 (355UL) +#define MCAN_MESSAGE_BUFF_356 (356UL) +#define MCAN_MESSAGE_BUFF_357 (357UL) +#define MCAN_MESSAGE_BUFF_358 (358UL) +#define MCAN_MESSAGE_BUFF_359 (359UL) +#define MCAN_MESSAGE_BUFF_360 (360UL) +#define MCAN_MESSAGE_BUFF_361 (361UL) +#define MCAN_MESSAGE_BUFF_362 (362UL) +#define MCAN_MESSAGE_BUFF_363 (363UL) +#define MCAN_MESSAGE_BUFF_364 (364UL) +#define MCAN_MESSAGE_BUFF_365 (365UL) +#define MCAN_MESSAGE_BUFF_366 (366UL) +#define MCAN_MESSAGE_BUFF_367 (367UL) +#define MCAN_MESSAGE_BUFF_368 (368UL) +#define MCAN_MESSAGE_BUFF_369 (369UL) +#define MCAN_MESSAGE_BUFF_370 (370UL) +#define MCAN_MESSAGE_BUFF_371 (371UL) +#define MCAN_MESSAGE_BUFF_372 (372UL) +#define MCAN_MESSAGE_BUFF_373 (373UL) +#define MCAN_MESSAGE_BUFF_374 (374UL) +#define MCAN_MESSAGE_BUFF_375 (375UL) +#define MCAN_MESSAGE_BUFF_376 (376UL) +#define MCAN_MESSAGE_BUFF_377 (377UL) +#define MCAN_MESSAGE_BUFF_378 (378UL) +#define MCAN_MESSAGE_BUFF_379 (379UL) +#define MCAN_MESSAGE_BUFF_380 (380UL) +#define MCAN_MESSAGE_BUFF_381 (381UL) +#define MCAN_MESSAGE_BUFF_382 (382UL) +#define MCAN_MESSAGE_BUFF_383 (383UL) +#define MCAN_MESSAGE_BUFF_384 (384UL) +#define MCAN_MESSAGE_BUFF_385 (385UL) +#define MCAN_MESSAGE_BUFF_386 (386UL) +#define MCAN_MESSAGE_BUFF_387 (387UL) +#define MCAN_MESSAGE_BUFF_388 (388UL) +#define MCAN_MESSAGE_BUFF_389 (389UL) +#define MCAN_MESSAGE_BUFF_390 (390UL) +#define MCAN_MESSAGE_BUFF_391 (391UL) +#define MCAN_MESSAGE_BUFF_392 (392UL) +#define MCAN_MESSAGE_BUFF_393 (393UL) +#define MCAN_MESSAGE_BUFF_394 (394UL) +#define MCAN_MESSAGE_BUFF_395 (395UL) +#define MCAN_MESSAGE_BUFF_396 (396UL) +#define MCAN_MESSAGE_BUFF_397 (397UL) +#define MCAN_MESSAGE_BUFF_398 (398UL) +#define MCAN_MESSAGE_BUFF_399 (399UL) +#define MCAN_MESSAGE_BUFF_400 (400UL) +#define MCAN_MESSAGE_BUFF_401 (401UL) +#define MCAN_MESSAGE_BUFF_402 (402UL) +#define MCAN_MESSAGE_BUFF_403 (403UL) +#define MCAN_MESSAGE_BUFF_404 (404UL) +#define MCAN_MESSAGE_BUFF_405 (405UL) +#define MCAN_MESSAGE_BUFF_406 (406UL) +#define MCAN_MESSAGE_BUFF_407 (407UL) +#define MCAN_MESSAGE_BUFF_408 (408UL) +#define MCAN_MESSAGE_BUFF_409 (409UL) +#define MCAN_MESSAGE_BUFF_410 (410UL) +#define MCAN_MESSAGE_BUFF_411 (411UL) +#define MCAN_MESSAGE_BUFF_412 (412UL) +#define MCAN_MESSAGE_BUFF_413 (413UL) +#define MCAN_MESSAGE_BUFF_414 (414UL) +#define MCAN_MESSAGE_BUFF_415 (415UL) +#define MCAN_MESSAGE_BUFF_416 (416UL) +#define MCAN_MESSAGE_BUFF_417 (417UL) +#define MCAN_MESSAGE_BUFF_418 (418UL) +#define MCAN_MESSAGE_BUFF_419 (419UL) +#define MCAN_MESSAGE_BUFF_420 (420UL) +#define MCAN_MESSAGE_BUFF_421 (421UL) +#define MCAN_MESSAGE_BUFF_422 (422UL) +#define MCAN_MESSAGE_BUFF_423 (423UL) +#define MCAN_MESSAGE_BUFF_424 (424UL) +#define MCAN_MESSAGE_BUFF_425 (425UL) +#define MCAN_MESSAGE_BUFF_426 (426UL) +#define MCAN_MESSAGE_BUFF_427 (427UL) +#define MCAN_MESSAGE_BUFF_428 (428UL) +#define MCAN_MESSAGE_BUFF_429 (429UL) +#define MCAN_MESSAGE_BUFF_430 (430UL) +#define MCAN_MESSAGE_BUFF_431 (431UL) +#define MCAN_MESSAGE_BUFF_432 (432UL) +#define MCAN_MESSAGE_BUFF_433 (433UL) +#define MCAN_MESSAGE_BUFF_434 (434UL) +#define MCAN_MESSAGE_BUFF_435 (435UL) +#define MCAN_MESSAGE_BUFF_436 (436UL) +#define MCAN_MESSAGE_BUFF_437 (437UL) +#define MCAN_MESSAGE_BUFF_438 (438UL) +#define MCAN_MESSAGE_BUFF_439 (439UL) +#define MCAN_MESSAGE_BUFF_440 (440UL) +#define MCAN_MESSAGE_BUFF_441 (441UL) +#define MCAN_MESSAGE_BUFF_442 (442UL) +#define MCAN_MESSAGE_BUFF_443 (443UL) +#define MCAN_MESSAGE_BUFF_444 (444UL) +#define MCAN_MESSAGE_BUFF_445 (445UL) +#define MCAN_MESSAGE_BUFF_446 (446UL) +#define MCAN_MESSAGE_BUFF_447 (447UL) +#define MCAN_MESSAGE_BUFF_448 (448UL) +#define MCAN_MESSAGE_BUFF_449 (449UL) +#define MCAN_MESSAGE_BUFF_450 (450UL) +#define MCAN_MESSAGE_BUFF_451 (451UL) +#define MCAN_MESSAGE_BUFF_452 (452UL) +#define MCAN_MESSAGE_BUFF_453 (453UL) +#define MCAN_MESSAGE_BUFF_454 (454UL) +#define MCAN_MESSAGE_BUFF_455 (455UL) +#define MCAN_MESSAGE_BUFF_456 (456UL) +#define MCAN_MESSAGE_BUFF_457 (457UL) +#define MCAN_MESSAGE_BUFF_458 (458UL) +#define MCAN_MESSAGE_BUFF_459 (459UL) +#define MCAN_MESSAGE_BUFF_460 (460UL) +#define MCAN_MESSAGE_BUFF_461 (461UL) +#define MCAN_MESSAGE_BUFF_462 (462UL) +#define MCAN_MESSAGE_BUFF_463 (463UL) +#define MCAN_MESSAGE_BUFF_464 (464UL) +#define MCAN_MESSAGE_BUFF_465 (465UL) +#define MCAN_MESSAGE_BUFF_466 (466UL) +#define MCAN_MESSAGE_BUFF_467 (467UL) +#define MCAN_MESSAGE_BUFF_468 (468UL) +#define MCAN_MESSAGE_BUFF_469 (469UL) +#define MCAN_MESSAGE_BUFF_470 (470UL) +#define MCAN_MESSAGE_BUFF_471 (471UL) +#define MCAN_MESSAGE_BUFF_472 (472UL) +#define MCAN_MESSAGE_BUFF_473 (473UL) +#define MCAN_MESSAGE_BUFF_474 (474UL) +#define MCAN_MESSAGE_BUFF_475 (475UL) +#define MCAN_MESSAGE_BUFF_476 (476UL) +#define MCAN_MESSAGE_BUFF_477 (477UL) +#define MCAN_MESSAGE_BUFF_478 (478UL) +#define MCAN_MESSAGE_BUFF_479 (479UL) +#define MCAN_MESSAGE_BUFF_480 (480UL) +#define MCAN_MESSAGE_BUFF_481 (481UL) +#define MCAN_MESSAGE_BUFF_482 (482UL) +#define MCAN_MESSAGE_BUFF_483 (483UL) +#define MCAN_MESSAGE_BUFF_484 (484UL) +#define MCAN_MESSAGE_BUFF_485 (485UL) +#define MCAN_MESSAGE_BUFF_486 (486UL) +#define MCAN_MESSAGE_BUFF_487 (487UL) +#define MCAN_MESSAGE_BUFF_488 (488UL) +#define MCAN_MESSAGE_BUFF_489 (489UL) +#define MCAN_MESSAGE_BUFF_490 (490UL) +#define MCAN_MESSAGE_BUFF_491 (491UL) +#define MCAN_MESSAGE_BUFF_492 (492UL) +#define MCAN_MESSAGE_BUFF_493 (493UL) +#define MCAN_MESSAGE_BUFF_494 (494UL) +#define MCAN_MESSAGE_BUFF_495 (495UL) +#define MCAN_MESSAGE_BUFF_496 (496UL) +#define MCAN_MESSAGE_BUFF_497 (497UL) +#define MCAN_MESSAGE_BUFF_498 (498UL) +#define MCAN_MESSAGE_BUFF_499 (499UL) +#define MCAN_MESSAGE_BUFF_500 (500UL) +#define MCAN_MESSAGE_BUFF_501 (501UL) +#define MCAN_MESSAGE_BUFF_502 (502UL) +#define MCAN_MESSAGE_BUFF_503 (503UL) +#define MCAN_MESSAGE_BUFF_504 (504UL) +#define MCAN_MESSAGE_BUFF_505 (505UL) +#define MCAN_MESSAGE_BUFF_506 (506UL) +#define MCAN_MESSAGE_BUFF_507 (507UL) +#define MCAN_MESSAGE_BUFF_508 (508UL) +#define MCAN_MESSAGE_BUFF_509 (509UL) +#define MCAN_MESSAGE_BUFF_510 (510UL) +#define MCAN_MESSAGE_BUFF_511 (511UL) +#define MCAN_MESSAGE_BUFF_512 (512UL) +#define MCAN_MESSAGE_BUFF_513 (513UL) +#define MCAN_MESSAGE_BUFF_514 (514UL) +#define MCAN_MESSAGE_BUFF_515 (515UL) +#define MCAN_MESSAGE_BUFF_516 (516UL) +#define MCAN_MESSAGE_BUFF_517 (517UL) +#define MCAN_MESSAGE_BUFF_518 (518UL) +#define MCAN_MESSAGE_BUFF_519 (519UL) +#define MCAN_MESSAGE_BUFF_520 (520UL) +#define MCAN_MESSAGE_BUFF_521 (521UL) +#define MCAN_MESSAGE_BUFF_522 (522UL) +#define MCAN_MESSAGE_BUFF_523 (523UL) +#define MCAN_MESSAGE_BUFF_524 (524UL) +#define MCAN_MESSAGE_BUFF_525 (525UL) +#define MCAN_MESSAGE_BUFF_526 (526UL) +#define MCAN_MESSAGE_BUFF_527 (527UL) +#define MCAN_MESSAGE_BUFF_528 (528UL) +#define MCAN_MESSAGE_BUFF_529 (529UL) +#define MCAN_MESSAGE_BUFF_530 (530UL) +#define MCAN_MESSAGE_BUFF_531 (531UL) +#define MCAN_MESSAGE_BUFF_532 (532UL) +#define MCAN_MESSAGE_BUFF_533 (533UL) +#define MCAN_MESSAGE_BUFF_534 (534UL) +#define MCAN_MESSAGE_BUFF_535 (535UL) +#define MCAN_MESSAGE_BUFF_536 (536UL) +#define MCAN_MESSAGE_BUFF_537 (537UL) +#define MCAN_MESSAGE_BUFF_538 (538UL) +#define MCAN_MESSAGE_BUFF_539 (539UL) +#define MCAN_MESSAGE_BUFF_540 (540UL) +#define MCAN_MESSAGE_BUFF_541 (541UL) +#define MCAN_MESSAGE_BUFF_542 (542UL) +#define MCAN_MESSAGE_BUFF_543 (543UL) +#define MCAN_MESSAGE_BUFF_544 (544UL) +#define MCAN_MESSAGE_BUFF_545 (545UL) +#define MCAN_MESSAGE_BUFF_546 (546UL) +#define MCAN_MESSAGE_BUFF_547 (547UL) +#define MCAN_MESSAGE_BUFF_548 (548UL) +#define MCAN_MESSAGE_BUFF_549 (549UL) +#define MCAN_MESSAGE_BUFF_550 (550UL) +#define MCAN_MESSAGE_BUFF_551 (551UL) +#define MCAN_MESSAGE_BUFF_552 (552UL) +#define MCAN_MESSAGE_BUFF_553 (553UL) +#define MCAN_MESSAGE_BUFF_554 (554UL) +#define MCAN_MESSAGE_BUFF_555 (555UL) +#define MCAN_MESSAGE_BUFF_556 (556UL) +#define MCAN_MESSAGE_BUFF_557 (557UL) +#define MCAN_MESSAGE_BUFF_558 (558UL) +#define MCAN_MESSAGE_BUFF_559 (559UL) +#define MCAN_MESSAGE_BUFF_560 (560UL) +#define MCAN_MESSAGE_BUFF_561 (561UL) +#define MCAN_MESSAGE_BUFF_562 (562UL) +#define MCAN_MESSAGE_BUFF_563 (563UL) +#define MCAN_MESSAGE_BUFF_564 (564UL) +#define MCAN_MESSAGE_BUFF_565 (565UL) +#define MCAN_MESSAGE_BUFF_566 (566UL) +#define MCAN_MESSAGE_BUFF_567 (567UL) +#define MCAN_MESSAGE_BUFF_568 (568UL) +#define MCAN_MESSAGE_BUFF_569 (569UL) +#define MCAN_MESSAGE_BUFF_570 (570UL) +#define MCAN_MESSAGE_BUFF_571 (571UL) +#define MCAN_MESSAGE_BUFF_572 (572UL) +#define MCAN_MESSAGE_BUFF_573 (573UL) +#define MCAN_MESSAGE_BUFF_574 (574UL) +#define MCAN_MESSAGE_BUFF_575 (575UL) +#define MCAN_MESSAGE_BUFF_576 (576UL) +#define MCAN_MESSAGE_BUFF_577 (577UL) +#define MCAN_MESSAGE_BUFF_578 (578UL) +#define MCAN_MESSAGE_BUFF_579 (579UL) +#define MCAN_MESSAGE_BUFF_580 (580UL) +#define MCAN_MESSAGE_BUFF_581 (581UL) +#define MCAN_MESSAGE_BUFF_582 (582UL) +#define MCAN_MESSAGE_BUFF_583 (583UL) +#define MCAN_MESSAGE_BUFF_584 (584UL) +#define MCAN_MESSAGE_BUFF_585 (585UL) +#define MCAN_MESSAGE_BUFF_586 (586UL) +#define MCAN_MESSAGE_BUFF_587 (587UL) +#define MCAN_MESSAGE_BUFF_588 (588UL) +#define MCAN_MESSAGE_BUFF_589 (589UL) +#define MCAN_MESSAGE_BUFF_590 (590UL) +#define MCAN_MESSAGE_BUFF_591 (591UL) +#define MCAN_MESSAGE_BUFF_592 (592UL) +#define MCAN_MESSAGE_BUFF_593 (593UL) +#define MCAN_MESSAGE_BUFF_594 (594UL) +#define MCAN_MESSAGE_BUFF_595 (595UL) +#define MCAN_MESSAGE_BUFF_596 (596UL) +#define MCAN_MESSAGE_BUFF_597 (597UL) +#define MCAN_MESSAGE_BUFF_598 (598UL) +#define MCAN_MESSAGE_BUFF_599 (599UL) +#define MCAN_MESSAGE_BUFF_600 (600UL) +#define MCAN_MESSAGE_BUFF_601 (601UL) +#define MCAN_MESSAGE_BUFF_602 (602UL) +#define MCAN_MESSAGE_BUFF_603 (603UL) +#define MCAN_MESSAGE_BUFF_604 (604UL) +#define MCAN_MESSAGE_BUFF_605 (605UL) +#define MCAN_MESSAGE_BUFF_606 (606UL) +#define MCAN_MESSAGE_BUFF_607 (607UL) +#define MCAN_MESSAGE_BUFF_608 (608UL) +#define MCAN_MESSAGE_BUFF_609 (609UL) +#define MCAN_MESSAGE_BUFF_610 (610UL) +#define MCAN_MESSAGE_BUFF_611 (611UL) +#define MCAN_MESSAGE_BUFF_612 (612UL) +#define MCAN_MESSAGE_BUFF_613 (613UL) +#define MCAN_MESSAGE_BUFF_614 (614UL) +#define MCAN_MESSAGE_BUFF_615 (615UL) +#define MCAN_MESSAGE_BUFF_616 (616UL) +#define MCAN_MESSAGE_BUFF_617 (617UL) +#define MCAN_MESSAGE_BUFF_618 (618UL) +#define MCAN_MESSAGE_BUFF_619 (619UL) +#define MCAN_MESSAGE_BUFF_620 (620UL) +#define MCAN_MESSAGE_BUFF_621 (621UL) +#define MCAN_MESSAGE_BUFF_622 (622UL) +#define MCAN_MESSAGE_BUFF_623 (623UL) +#define MCAN_MESSAGE_BUFF_624 (624UL) +#define MCAN_MESSAGE_BUFF_625 (625UL) +#define MCAN_MESSAGE_BUFF_626 (626UL) +#define MCAN_MESSAGE_BUFF_627 (627UL) +#define MCAN_MESSAGE_BUFF_628 (628UL) +#define MCAN_MESSAGE_BUFF_629 (629UL) +#define MCAN_MESSAGE_BUFF_630 (630UL) +#define MCAN_MESSAGE_BUFF_631 (631UL) +#define MCAN_MESSAGE_BUFF_632 (632UL) +#define MCAN_MESSAGE_BUFF_633 (633UL) +#define MCAN_MESSAGE_BUFF_634 (634UL) +#define MCAN_MESSAGE_BUFF_635 (635UL) +#define MCAN_MESSAGE_BUFF_636 (636UL) +#define MCAN_MESSAGE_BUFF_637 (637UL) +#define MCAN_MESSAGE_BUFF_638 (638UL) +#define MCAN_MESSAGE_BUFF_639 (639UL) + + +#endif /* HPM_MCAN_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_pla_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_pla_regs.h new file mode 100644 index 00000000..1723aeac --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_pla_regs.h @@ -0,0 +1,1708 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PLA_H +#define HPM_PLA_H + +typedef struct { + struct { + __RW uint32_t AOI_16TO8[8]; /* 0x0 - 0x1C: CHN AOI_16to8 AND logic cfg */ + __RW uint32_t AOI_8TO7_00_01; /* 0x20: CHN AOI_16to8_00_01 OR logic cfg */ + __RW uint32_t AOI_8TO7_02_03; /* 0x24: CHN AOI_16to8_02_03 OR logic cfg */ + __RW uint32_t AOI_8TO7_04_05; /* 0x28: CHN AOI_16to8_04_05 OR logic cfg */ + __RW uint32_t AOI_8TO7_06; /* 0x2C: CHN AOI_16to8_06 OR logic cfg */ + __RW uint32_t FILTER_2ND[8]; /* 0x30 - 0x4C: CHN SECOND_FILTER cfg */ + __RW uint32_t FILTER_3RD[7]; /* 0x50 - 0x68: CHN THIRD_FILTER cfg */ + __RW uint32_t CFG_FF; /* 0x6C: CHN cfg ff */ + } CHN[8]; + __R uint8_t RESERVED0[64]; /* 0x380 - 0x3BF: Reserved */ + __RW uint32_t FILTER_1ST_PLA_IN[8]; /* 0x3C0 - 0x3DC: FRIST_FILTER_PLA_IN setting */ + __RW uint32_t FILTER_1ST_PLA_OUT[8]; /* 0x3E0 - 0x3FC: FRIST_FILTER_PLA_OUT setting */ + __RW uint32_t CHN_CFG_ACTIVE[8]; /* 0x400 - 0x41C: CHN cfg active */ +} PLA_Type; + + +/* Bitfield definition for register of struct array CHN: AOI_16TO8_00 */ +/* + * AOI_16TO8_15 (RW) + * + * select value for AOI_16to8_15. + * 0: 0. + * 1: 1st_filter_out[15]. + * 2: ~1st_filter_out[15]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK (0xC0000000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT (30U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT) + +/* + * AOI_16TO8_14 (RW) + * + * select value for AOI_16to8_14. + * 0: 0. + * 1: 1st_filter_out[14]. + * 2: ~1st_filter_out[14]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK (0x30000000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT (28U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT) + +/* + * AOI_16TO8_13 (RW) + * + * select value for AOI_16to8_13. + * 0: 0. + * 1: 1st_filter_out[13]. + * 2: ~1st_filter_out[13]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK (0xC000000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT (26U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT) + +/* + * AOI_16TO8_12 (RW) + * + * select value for AOI_16to8_12. + * 0: 0. + * 1: 1st_filter_out[12]. + * 2: ~1st_filter_out[12]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK (0x3000000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT (24U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT) + +/* + * AOI_16TO8_11 (RW) + * + * select value for AOI_16to8_11. + * 0: 0. + * 1: 1st_filter_out[11]. + * 2: ~1st_filter_out[11]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK (0xC00000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT (22U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT) + +/* + * AOI_16TO8_10 (RW) + * + * select value for AOI_16to8_10. + * 0: 0. + * 1: 1st_filter_out[10]. + * 2: ~1st_filter_out[10]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK (0x300000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT (20U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT) + +/* + * AOI_16TO8_9 (RW) + * + * select value for AOI_16to8_9. + * 0: 0. + * 1: 1st_filter_out[9]. + * 2: ~1st_filter_out[9]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK (0xC0000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT (18U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT) + +/* + * AOI_16TO8_8 (RW) + * + * select value for AOI_16to8_8. + * 0: 0. + * 1: 1st_filter_out[8]. + * 2: ~1st_filter_out[8]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK (0x30000UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT (16U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT) + +/* + * AOI_16TO8_7 (RW) + * + * select value for AOI_16to8_7. + * 0: 0. + * 1: 1st_filter_out[7]. + * 2: ~1st_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK (0xC000U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT (14U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT) + +/* + * AOI_16TO8_6 (RW) + * + * select value for AOI_16to8_6. + * 0: 0. + * 1: 1st_filter_out[6]. + * 2: ~1st_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK (0x3000U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT (12U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT) + +/* + * AOI_16TO8_5 (RW) + * + * select value for AOI_16to8_5. + * 0: 0. + * 1: 1st_filter_out[5]. + * 2: ~1st_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK (0xC00U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT (10U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT) + +/* + * AOI_16TO8_4 (RW) + * + * select value for AOI_16to8_4. + * 0: 0. + * 1: 1st_filter_out[4]. + * 2: ~1st_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK (0x300U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT (8U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT) + +/* + * AOI_16TO8_3 (RW) + * + * select value for AOI_16to8_3. + * 0: 0. + * 1: 1st_filter_out[3]. + * 2: ~1st_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK (0xC0U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT (6U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT) + +/* + * AOI_16TO8_2 (RW) + * + * select value for AOI_16to8_2. + * 0: 0. + * 1: 1st_filter_out[2]. + * 2: ~1st_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK (0x30U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT (4U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT) + +/* + * AOI_16TO8_1 (RW) + * + * select value for AOI_16to8_1. + * 0: 0. + * 1: 1st_filter_out[1]. + * 2: ~1st_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK (0xCU) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT (2U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT) + +/* + * AOI_16TO8_0 (RW) + * + * select value for AOI_16to8_0. + * 0: 0. + * 1: 1st_filter_out[0]. + * 2: ~1st_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK (0x3U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT (0U) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT) + +/* Bitfield definition for register of struct array CHN: AOI_8TO7_00_01 */ +/* + * AOI_8TO7_01_7 (RW) + * + * select value for AOI_8to7_01_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK (0xC0000000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT (30U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT) + +/* + * AOI_8TO7_01_6 (RW) + * + * select value for AOI_8to7_01_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK (0x30000000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT (28U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT) + +/* + * AOI_8TO7_01_5 (RW) + * + * select value for AOI_8to7_01_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK (0xC000000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT (26U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT) + +/* + * AOI_8TO7_01_4 (RW) + * + * select value for AOI_8to7_01_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK (0x3000000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT (24U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT) + +/* + * AOI_8TO7_01_3 (RW) + * + * select value for AOI_8to7_01_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK (0xC00000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT (22U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT) + +/* + * AOI_8TO7_01_2 (RW) + * + * select value for AOI_8to7_01_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK (0x300000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT (20U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT) + +/* + * AOI_8TO7_01_1 (RW) + * + * select value for AOI_8to7_01_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK (0xC0000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT (18U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT) + +/* + * AOI_8TO7_01_0 (RW) + * + * select value for AOI_8to7_01_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK (0x30000UL) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT (16U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT) + +/* + * AOI_8TO7_00_7 (RW) + * + * select value for AOI_8to7_00_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK (0xC000U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT (14U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT) + +/* + * AOI_8TO7_00_6 (RW) + * + * select value for AOI_8to7_00_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK (0x3000U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT (12U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT) + +/* + * AOI_8TO7_00_5 (RW) + * + * select value for AOI_8to7_00_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK (0xC00U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT (10U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT) + +/* + * AOI_8TO7_00_4 (RW) + * + * select value for AOI_8to7_00_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK (0x300U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT (8U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT) + +/* + * AOI_8TO7_00_3 (RW) + * + * select value for AOI_8to7_00_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK (0xC0U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT (6U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT) + +/* + * AOI_8TO7_00_2 (RW) + * + * select value for AOI_8to7_00_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK (0x30U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT (4U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT) + +/* + * AOI_8TO7_00_1 (RW) + * + * select value for AOI_8to7_00_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK (0xCU) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT (2U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT) + +/* + * AOI_8TO7_00_0 (RW) + * + * select value for AOI_8to7_00_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK (0x3U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT (0U) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK) +#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT) + +/* Bitfield definition for register of struct array CHN: AOI_8TO7_02_03 */ +/* + * AOI_8TO7_03_7 (RW) + * + * select value for AOI_8to7_03_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK (0xC0000000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT (30U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT) + +/* + * AOI_8TO7_03_6 (RW) + * + * select value for AOI_8to7_03_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK (0x30000000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT (28U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT) + +/* + * AOI_8TO7_03_5 (RW) + * + * select value for AOI_8to7_03_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK (0xC000000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT (26U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT) + +/* + * AOI_8TO7_03_4 (RW) + * + * select value for AOI_8to7_03_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK (0x3000000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT (24U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT) + +/* + * AOI_8TO7_03_3 (RW) + * + * select value for AOI_8to7_03_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK (0xC00000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT (22U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT) + +/* + * AOI_8TO7_03_2 (RW) + * + * select value for AOI_8to7_03_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK (0x300000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT (20U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT) + +/* + * AOI_8TO7_03_1 (RW) + * + * select value for AOI_8to7_03_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK (0xC0000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT (18U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT) + +/* + * AOI_8TO7_03_0 (RW) + * + * select value for AOI_8to7_03_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK (0x30000UL) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT (16U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT) + +/* + * AOI_8TO7_02_7 (RW) + * + * select value for AOI_8to7_02_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK (0xC000U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT (14U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT) + +/* + * AOI_8TO7_02_6 (RW) + * + * select value for AOI_8to7_02_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK (0x3000U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT (12U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT) + +/* + * AOI_8TO7_02_5 (RW) + * + * select value for AOI_8to7_02_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK (0xC00U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT (10U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT) + +/* + * AOI_8TO7_02_4 (RW) + * + * select value for AOI_8to7_02_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK (0x300U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT (8U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT) + +/* + * AOI_8TO7_02_3 (RW) + * + * select value for AOI_8to7_02_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK (0xC0U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT (6U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT) + +/* + * AOI_8TO7_02_2 (RW) + * + * select value for AOI_8to7_02_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK (0x30U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT (4U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT) + +/* + * AOI_8TO7_02_1 (RW) + * + * select value for AOI_8to7_02_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK (0xCU) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT (2U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT) + +/* + * AOI_8TO7_02_0 (RW) + * + * select value for AOI_8to7_02_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK (0x3U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT (0U) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK) +#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT) + +/* Bitfield definition for register of struct array CHN: AOI_8TO7_04_05 */ +/* + * AOI_8TO7_05_7 (RW) + * + * select value for AOI_8to7_05_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK (0xC0000000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT (30U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT) + +/* + * AOI_8TO7_05_6 (RW) + * + * select value for AOI_8to7_05_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK (0x30000000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT (28U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT) + +/* + * AOI_8TO7_05_5 (RW) + * + * select value for AOI_8to7_05_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK (0xC000000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT (26U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT) + +/* + * AOI_8TO7_05_4 (RW) + * + * select value for AOI_8to7_05_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK (0x3000000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT (24U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT) + +/* + * AOI_8TO7_05_3 (RW) + * + * select value for AOI_8to7_05_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK (0xC00000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT (22U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT) + +/* + * AOI_8TO7_05_2 (RW) + * + * select value for AOI_8to7_05_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK (0x300000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT (20U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT) + +/* + * AOI_8TO7_05_1 (RW) + * + * select value for AOI_8to7_05_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK (0xC0000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT (18U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT) + +/* + * AOI_8TO7_05_0 (RW) + * + * select value for AOI_8to7_05_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK (0x30000UL) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT (16U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT) + +/* + * AOI_8TO7_04_7 (RW) + * + * select value for AOI_8to7_04_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK (0xC000U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT (14U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT) + +/* + * AOI_8TO7_04_6 (RW) + * + * select value for AOI_8to7_04_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK (0x3000U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT (12U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT) + +/* + * AOI_8TO7_04_5 (RW) + * + * select value for AOI_8to7_04_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK (0xC00U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT (10U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT) + +/* + * AOI_8TO7_04_4 (RW) + * + * select value for AOI_8to7_04_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK (0x300U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT (8U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT) + +/* + * AOI_8TO7_04_3 (RW) + * + * select value for AOI_8to7_04_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK (0xC0U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT (6U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT) + +/* + * AOI_8TO7_04_2 (RW) + * + * select value for AOI_8to7_04_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK (0x30U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT (4U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT) + +/* + * AOI_8TO7_04_1 (RW) + * + * select value for AOI_8to7_04_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK (0xCU) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT (2U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT) + +/* + * AOI_8TO7_04_0 (RW) + * + * select value for AOI_8to7_04_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK (0x3U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT (0U) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK) +#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT) + +/* Bitfield definition for register of struct array CHN: AOI_8TO7_06 */ +/* + * AOI_8TO7_06_7 (RW) + * + * select value for AOI_8to7_06_7. + * 0: 0. + * 1: 2nd_filter_out[7]. + * 2: ~2nd_filter_out[7]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK (0xC000U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT (14U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT) + +/* + * AOI_8TO7_06_6 (RW) + * + * select value for AOI_8to7_06_6. + * 0: 0. + * 1: 2nd_filter_out[6]. + * 2: ~2nd_filter_out[6]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK (0x3000U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT (12U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT) + +/* + * AOI_8TO7_06_5 (RW) + * + * select value for AOI_8to7_06_5. + * 0: 0. + * 1: 2nd_filter_out[5]. + * 2: ~2nd_filter_out[5]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK (0xC00U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT (10U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT) + +/* + * AOI_8TO7_06_4 (RW) + * + * select value for AOI_8to7_06_4. + * 0: 0. + * 1: 2nd_filter_out[4]. + * 2: ~2nd_filter_out[4]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK (0x300U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT (8U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT) + +/* + * AOI_8TO7_06_3 (RW) + * + * select value for AOI_8to7_06_3. + * 0: 0. + * 1: 2nd_filter_out[3]. + * 2: ~2nd_filter_out[3]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK (0xC0U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT (6U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT) + +/* + * AOI_8TO7_06_2 (RW) + * + * select value for AOI_8to7_06_2. + * 0: 0. + * 1: 2nd_filter_out[2]. + * 2: ~2nd_filter_out[2]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK (0x30U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT (4U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT) + +/* + * AOI_8TO7_06_1 (RW) + * + * select value for AOI_8to7_06_1. + * 0: 0. + * 1: 2nd_filter_out[1]. + * 2: ~2nd_filter_out[1]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK (0xCU) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT (2U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT) + +/* + * AOI_8TO7_06_0 (RW) + * + * select value for AOI_8to7_06_0. + * 0: 0. + * 1: 2nd_filter_out[0]. + * 2: ~2nd_filter_out[0]. + * 3: 1 + */ +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK (0x3U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT (0U) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK) +#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT) + +/* Bitfield definition for register of struct array CHN: SECOND_FILTER_0 */ +/* + * FILTER_EXT_COUNTER (RW) + * + * filter_ext counter value, cycles for filter or extent by system clock。 + * 0：0*apb_clk_period + * 1：1*apb_clk_period + * 2: 2*apb_clk_period + * … + * 65535: 65535*apb_clk_period + */ +#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT (16U) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT) + +/* + * FILTER_EXT_TYPE (RW) + * + * filter extend type. + * 0-3：nothing to do. + * 4： input high level extend. + * 5： input low level extend. + * 6： output extend. + * 7： input pulse extend. + */ +#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK (0x7000U) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT (12U) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT) + +/* + * FILTER_EXT_ENABLE (RW) + * + * filter extend enable. + * 0. bypass filter extend. all setting in bit31:12 are inactive + * 1. enable filter extend, all setting in bit31:12 are active. + */ +#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK (0x100U) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT (8U) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK) +#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT) + +/* + * FILTER_SYNC_LEVEL (RW) + * + * synchroniser level. + * 0: 2 level sync. + * 1: 3 level sync + */ +#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK (0x80U) +#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT (7U) +#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK) +#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK) >> PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT) + +/* + * POSE_EDGE_DECT_ENABLE (RW) + * + * pose edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK (0x40U) +#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT (6U) +#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK) +#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT) + +/* + * NEGE_EDGE_DECT_ENABLE (RW) + * + * nege edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK (0x20U) +#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT (5U) +#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK) +#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT) + +/* + * EDGE_DECT_ENABLE (RW) + * + * edge detector enable. + * 0: disable. bit6/bit5 setting inactive. + * 1: enable. bit6/bit5 setting active. + */ +#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK (0x10U) +#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT (4U) +#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK) +#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT) + +/* + * FILTER_REVERSE (RW) + * + * reverse sync and edge detector filter's output. + * 0: not reverse. + * 1: reverse. + */ +#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK (0x8U) +#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT (3U) +#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK) +#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT) + +/* + * SOFTWARE_INJECT (RW) + * + * software inject value for sync and edge detector filter. + * 0: inject low level. + * 1: inject high level. + * 2: not inject. + * 3. inject high level. + */ +#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK (0x6U) +#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT (1U) +#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT) & PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK) +#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK) >> PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT) + +/* + * SYNC_EDGE_FILTER_ENABLE (RW) + * + * sync and edge detector filter. + * 0: disable. + * 1: enable. + */ +#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U) +#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U) +#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK) +#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array CHN: THIRD_FILTER_0 */ +/* + * FILTER_EXT_COUNTER (RW) + * + * filter_ext counter value, cycles for filter or extent by system clock。 + * 0：0*apb_clk_period + * 1：1*apb_clk_period + * 2: 2*apb_clk_period + * … + * 65535: 65535*apb_clk_period + */ +#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT (16U) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT) + +/* + * FILTER_EXT_TYPE (RW) + * + * filter extend type. + * 0-3：nothing to do. + * 4： input high level extend. + * 5： input low level extend. + * 6： output extend. + * 7： input pulse extend. + */ +#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK (0x7000U) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT (12U) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT) + +/* + * FILTER_EXT_ENABLE (RW) + * + * filter extend enable. + * 0. bypass filter extend. all setting in bit31:12 are inactive + * 1. enable filter extend, all setting in bit31:12 are active. + */ +#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK (0x100U) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT (8U) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK) +#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT) + +/* + * FILTER_SYNC_LEVEL (RW) + * + * synchroniser level. + * 0: 2 level sync. + * 1: 3 level sync + */ +#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK (0x80U) +#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT (7U) +#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK) +#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK) >> PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT) + +/* + * POSE_EDGE_DECT_ENABLE (RW) + * + * pose edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK (0x40U) +#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT (6U) +#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK) +#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT) + +/* + * NEGE_EDGE_DECT_ENABLE (RW) + * + * nege edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK (0x20U) +#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT (5U) +#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK) +#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT) + +/* + * EDGE_DECT_ENABLE (RW) + * + * edge detector enable. + * 0: disable. bit6/bit5 setting inactive. + * 1: enable. bit6/bit5 setting active. + */ +#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK (0x10U) +#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT (4U) +#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK) +#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT) + +/* + * FILTER_REVERSE (RW) + * + * reverse sync and edge detector filter's output. + * 0: not reverse. + * 1: reverse. + */ +#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK (0x8U) +#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT (3U) +#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK) +#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT) + +/* + * SOFTWARE_INJECT (RW) + * + * software inject value for sync and edge detector filter. + * 0: inject low level. + * 1: inject high level. + * 2: not inject. + * 3. inject high level. + */ +#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK (0x6U) +#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT (1U) +#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT) & PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK) +#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK) >> PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT) + +/* + * SYNC_EDGE_FILTER_ENABLE (RW) + * + * sync and edge detector filter. + * 0: disable. + * 1: enable. + */ +#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U) +#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U) +#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK) +#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array CHN: CFG_FF */ +/* + * OSC_LOOP_CLAMP_VALUE (RW) + * + * osc loop clamp value when osc ring active. + * 0: clamp 0. + * 1: clamp 1. + */ +#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK (0x20000UL) +#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT (17U) +#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT) & PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK) +#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK) >> PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT) + +/* + * DIS_OSC_LOOP_CLAMP (RW) + * + * disable osc loop clamp. + * 0: enable osc loop clamp when osc ring active. + * 1: disable or clean current osc loop clamp. + */ +#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK (0x10000UL) +#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT (16U) +#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT) & PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK) +#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK) >> PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT) + +/* + * SEL_ADDER_MINUS (RW) + * + * 0: select adder when cfg_adder_minus active. + * 1: select minus when cfg_adder_minus active. + */ +#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK (0x10U) +#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT (4U) +#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT) & PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK) +#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK) >> PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT) + +/* + * SEL_CLK_SOURCE (RW) + * + * cfg_ff clock source. + * 0: system clock. + * 1: use 3rd_filter_2 as clock. + */ +#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK (0x8U) +#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT (3U) +#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT) & PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK) +#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK) >> PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT) + +/* + * SEL_CFG_FF_TYPE (RW) + * + * cfg_ff type. + * 0: DFF. + * 1: 3rd_filter_0. + * 2: dual-edge DFF. + * 3: Trigger FF. + * 4: JK FF. + * 5. latch. + * 6: full adder/minus. + */ +#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK (0x7U) +#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT (0U) +#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT) & PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK) +#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK) >> PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT) + +/* Bitfield definition for register array: FILTER_1ST_PLA_IN */ +/* + * FILTER_EXT_COUNTER (RW) + * + * filter_ext counter value, cycles for filter or extent by system clock。 + * 0：0*apb_clk_period + * 1：1*apb_clk_period + * 2: 2*apb_clk_period + * … + * 65535: 65535*apb_clk_period + */ +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT (16U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT) + +/* + * FILTER_EXT_TYPE (RW) + * + * filter extend type. + * 0-3：nothing to do. + * 4： input high level extend. + * 5： input low level extend. + * 6： output extend. + * 7： input pulse extend. + */ +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK (0x7000U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT (12U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT) + +/* + * FILTER_EXT_ENABLE (RW) + * + * filter extend enable. + * 0. bypass filter extend. all setting in bit31:12 are inactive + * 1. enable filter extend, all setting in bit31:12 are active. + */ +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK (0x100U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT (8U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT) + +/* + * FILTER_SYNC_LEVEL (RW) + * + * synchroniser level. + * 0: 2 level sync. + * 1: 3 level sync + */ +#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK (0x80U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT (7U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK) +#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT) + +/* + * POSE_EDGE_DECT_ENABLE (RW) + * + * pose edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK (0x40U) +#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT (6U) +#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT) + +/* + * NEGE_EDGE_DECT_ENABLE (RW) + * + * nege edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK (0x20U) +#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT (5U) +#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT) + +/* + * EDGE_DECT_ENABLE (RW) + * + * edge detector enable. + * 0: disable. bit6/bit5 setting inactive. + * 1: enable. bit6/bit5 setting active. + */ +#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK (0x10U) +#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT (4U) +#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT) + +/* + * FILTER_REVERSE (RW) + * + * reverse sync and edge detector filter's output. + * 0: not reverse. + * 1: reverse. + */ +#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK (0x8U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT (3U) +#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK) +#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT) + +/* + * SOFTWARE_INJECT (RW) + * + * software inject value for sync and edge detector filter. + * 0: inject low level. + * 1: inject high level. + * 2: not inject. + * 3. inject high level. + */ +#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK (0x6U) +#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT (1U) +#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT) & PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK) +#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK) >> PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT) + +/* + * SYNC_EDGE_FILTER_ENABLE (RW) + * + * sync and edge detector filter. + * 0: disable. + * 1: enable. + */ +#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U) +#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U) +#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT) + +/* Bitfield definition for register array: FILTER_1ST_PLA_OUT */ +/* + * FILTER_EXT_COUNTER (RW) + * + * filter_ext counter value, cycles for filter or extent by system clock。 + * 0：0*apb_clk_period + * 1：1*apb_clk_period + * 2: 2*apb_clk_period + * … + * 65535: 65535*apb_clk_period + */ +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT (16U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT) + +/* + * FILTER_EXT_TYPE (RW) + * + * filter extend type. + * 0-3：nothing to do. + * 4： input high level extend. + * 5： input low level extend. + * 6： output extend. + * 7： input pulse extend. + */ +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK (0x7000U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT (12U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT) + +/* + * FILTER_EXT_ENABLE (RW) + * + * filter extend enable. + * 0. bypass filter extend. all setting in bit31:12 are inactive + * 1. enable filter extend, all setting in bit31:12 are active. + */ +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK (0x100U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT (8U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT) + +/* + * FILTER_SYNC_LEVEL (RW) + * + * synchroniser level. + * 0: 2 level sync. + * 1: 3 level sync + */ +#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK (0x80U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT (7U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT) + +/* + * POSE_EDGE_DECT_ENABLE (RW) + * + * pose edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK (0x40U) +#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT (6U) +#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT) + +/* + * NEGE_EDGE_DECT_ENABLE (RW) + * + * nege edge detector enable. + * 0: disable. + * 1: enable. + */ +#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK (0x20U) +#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT (5U) +#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT) + +/* + * EDGE_DECT_ENABLE (RW) + * + * edge detector enable. + * 0: disable. bit6/bit5 setting inactive. + * 1: enable. bit6/bit5 setting active. + */ +#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK (0x10U) +#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT (4U) +#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT) + +/* + * FILTER_REVERSE (RW) + * + * reverse sync and edge detector filter's output. + * 0: not reverse. + * 1: reverse. + */ +#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK (0x8U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT (3U) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT) + +/* + * SOFTWARE_INJECT (RW) + * + * software inject value for sync and edge detector filter. + * 0: inject low level. + * 1: inject high level. + * 2: not inject. + * 3. inject high level. + */ +#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK (0x6U) +#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT (1U) +#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT) & PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK) +#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK) >> PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT) + +/* + * SYNC_EDGE_FILTER_ENABLE (RW) + * + * sync and edge detector filter. + * 0: disable. + * 1: enable. + */ +#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U) +#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U) +#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK) +#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT) + +/* Bitfield definition for register array: CHN_CFG_ACTIVE */ +/* + * CFG_ACTIVE (RW) + * + * write 0xF00D to enable all setting. Otherwire, all setting inactive. + */ +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK (0xFFFFU) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT (0U) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT) & PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK) >> PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT) + + + +/* AOI_16TO8 register group index macro definition */ +#define PLA_CHN_AOI_16TO8_AOI_16TO8_00 (0UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_01 (1UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_02 (2UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_03 (3UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_04 (4UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_05 (5UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_06 (6UL) +#define PLA_CHN_AOI_16TO8_AOI_16TO8_07 (7UL) + +/* FILTER_2ND register group index macro definition */ +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_0 (0UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_1 (1UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_2 (2UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_3 (3UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_4 (4UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_5 (5UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_6 (6UL) +#define PLA_CHN_FILTER_2ND_SECOND_FILTER_7 (7UL) + +/* FILTER_3RD register group index macro definition */ +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_0 (0UL) +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_1 (1UL) +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_2 (2UL) +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_3 (3UL) +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_4 (4UL) +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_5 (5UL) +#define PLA_CHN_FILTER_3RD_THIRD_FILTER_6 (6UL) + +/* CHN register group index macro definition */ +#define PLA_CHN_0 (0UL) +#define PLA_CHN_1 (1UL) +#define PLA_CHN_2 (2UL) +#define PLA_CHN_3 (3UL) +#define PLA_CHN_4 (4UL) +#define PLA_CHN_5 (5UL) +#define PLA_CHN_6 (6UL) +#define PLA_CHN_7 (7UL) + +/* FILTER_1ST_PLA_IN register group index macro definition */ +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_0 (0UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_1 (1UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_2 (2UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_3 (3UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_4 (4UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_5 (5UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_6 (6UL) +#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_7 (7UL) + +/* FILTER_1ST_PLA_OUT register group index macro definition */ +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_IN_0 (0UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_0 (0UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_1 (1UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_2 (2UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_3 (3UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_4 (4UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_5 (5UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_6 (6UL) +#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_7 (7UL) + +/* CHN_CFG_ACTIVE register group index macro definition */ +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN0 (0UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN1 (1UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN2 (2UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN3 (3UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN4 (4UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN5 (5UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN6 (6UL) +#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN7 (7UL) + + +#endif /* HPM_PLA_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h index 14ea40e5..fcb06d58 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_pwm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,9 +11,18 @@ typedef struct { __RW uint32_t UNLK; /* 0x0: Shadow registers unlock register */ - __RW uint32_t STA; /* 0x4: Counter start register */ - __RW uint32_t RLD; /* 0x8: Counter reload register */ - __RW uint32_t CMP[24]; /* 0xC - 0x68: Comparator register */ + union { + __RW uint32_t STA; /* 0x4: Counter start register */ + __RW uint32_t STA_HRPWM; /* 0x4: Counter start register */ + }; + union { + __RW uint32_t RLD; /* 0x8: Counter reload register */ + __RW uint32_t RLD_HRPWM; /* 0x8: Counter reload register */ + }; + union { + __RW uint32_t CMP[24]; /* 0xC - 0x68: Comparator register */ + __RW uint32_t CMP_HRPWM[24]; /* 0xC - 0x68: Comparator register */ + }; __R uint8_t RESERVED0[12]; /* 0x6C - 0x77: Reserved */ __RW uint32_t FRCMD; /* 0x78: Force output mode register */ __RW uint32_t SHLK; /* 0x7C: Shadow registers lock register */ @@ -36,6 +45,9 @@ typedef struct { __R uint8_t RESERVED7[4]; /* 0x228 - 0x22B: Reserved */ __RW uint32_t DMAEN; /* 0x22C: DMA request enable register */ __RW uint32_t CMPCFG[24]; /* 0x230 - 0x28C: Comparator configure register */ + __R uint8_t RESERVED8[368]; /* 0x290 - 0x3FF: Reserved */ + __R uint32_t ANASTS[8]; /* 0x400 - 0x41C: analog status register */ + __W uint32_t HRPWM_CFG; /* 0x420: hrpwm config register */ } PWM_Type; @@ -73,6 +85,16 @@ typedef struct { #define PWM_STA_STA_SET(x) (((uint32_t)(x) << PWM_STA_STA_SHIFT) & PWM_STA_STA_MASK) #define PWM_STA_STA_GET(x) (((uint32_t)(x) & PWM_STA_STA_MASK) >> PWM_STA_STA_SHIFT) +/* Bitfield definition for register: STA_HRPWM */ +/* + * STA (RW) + * + */ +#define PWM_STA_HRPWM_STA_MASK (0xFFFFFF00UL) +#define PWM_STA_HRPWM_STA_SHIFT (8U) +#define PWM_STA_HRPWM_STA_SET(x) (((uint32_t)(x) << PWM_STA_HRPWM_STA_SHIFT) & PWM_STA_HRPWM_STA_MASK) +#define PWM_STA_HRPWM_STA_GET(x) (((uint32_t)(x) & PWM_STA_HRPWM_STA_MASK) >> PWM_STA_HRPWM_STA_SHIFT) + /* Bitfield definition for register: RLD */ /* * XRLD (RW) @@ -94,7 +116,27 @@ typedef struct { #define PWM_RLD_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_RLD_SHIFT) & PWM_RLD_RLD_MASK) #define PWM_RLD_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_RLD_MASK) >> PWM_RLD_RLD_SHIFT) -/* Bitfield definition for register array: CMP */ +/* Bitfield definition for register: RLD_HRPWM */ +/* + * RLD (RW) + * + */ +#define PWM_RLD_HRPWM_RLD_MASK (0xFFFFFF00UL) +#define PWM_RLD_HRPWM_RLD_SHIFT (8U) +#define PWM_RLD_HRPWM_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_HRPWM_RLD_SHIFT) & PWM_RLD_HRPWM_RLD_MASK) +#define PWM_RLD_HRPWM_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_HRPWM_RLD_MASK) >> PWM_RLD_HRPWM_RLD_SHIFT) + +/* + * RLD_HR (RW) + * + * pwm timer counter reload value at high resolution, only exist if hwpwm is enabled. + */ +#define PWM_RLD_HRPWM_RLD_HR_MASK (0xFFU) +#define PWM_RLD_HRPWM_RLD_HR_SHIFT (0U) +#define PWM_RLD_HRPWM_RLD_HR_SET(x) (((uint32_t)(x) << PWM_RLD_HRPWM_RLD_HR_SHIFT) & PWM_RLD_HRPWM_RLD_HR_MASK) +#define PWM_RLD_HRPWM_RLD_HR_GET(x) (((uint32_t)(x) & PWM_RLD_HRPWM_RLD_HR_MASK) >> PWM_RLD_HRPWM_RLD_HR_SHIFT) + +/* Bitfield definition for register: 0 */ /* * XCMP (RW) * @@ -136,6 +178,26 @@ typedef struct { #define PWM_CMP_CMPJIT_SET(x) (((uint32_t)(x) << PWM_CMP_CMPJIT_SHIFT) & PWM_CMP_CMPJIT_MASK) #define PWM_CMP_CMPJIT_GET(x) (((uint32_t)(x) & PWM_CMP_CMPJIT_MASK) >> PWM_CMP_CMPJIT_SHIFT) +/* Bitfield definition for register: 0 */ +/* + * CMP (RW) + * + */ +#define PWM_CMP_HRPWM_CMP_MASK (0xFFFFFF00UL) +#define PWM_CMP_HRPWM_CMP_SHIFT (8U) +#define PWM_CMP_HRPWM_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_HRPWM_CMP_SHIFT) & PWM_CMP_HRPWM_CMP_MASK) +#define PWM_CMP_HRPWM_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_HRPWM_CMP_MASK) >> PWM_CMP_HRPWM_CMP_SHIFT) + +/* + * CMP_HR (RW) + * + * high resolution compare value + */ +#define PWM_CMP_HRPWM_CMP_HR_MASK (0xFFU) +#define PWM_CMP_HRPWM_CMP_HR_SHIFT (0U) +#define PWM_CMP_HRPWM_CMP_HR_SET(x) (((uint32_t)(x) << PWM_CMP_HRPWM_CMP_HR_SHIFT) & PWM_CMP_HRPWM_CMP_HR_MASK) +#define PWM_CMP_HRPWM_CMP_HR_GET(x) (((uint32_t)(x) & PWM_CMP_HRPWM_CMP_HR_MASK) >> PWM_CMP_HRPWM_CMP_HR_SHIFT) + /* Bitfield definition for register: FRCMD */ /* * FRCMD (RW) @@ -260,7 +322,7 @@ typedef struct { * HWSHDWEDG (RW) * * When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. - * This bit assign its which edge is used as shadow register hardware load event. + * This bit assign its which edge is used as compare shadow register hardware load event. * 1- Falling edge * 0- Rising edge */ @@ -377,7 +439,27 @@ typedef struct { #define PWM_GCR_XRLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_XRLDSYNCEN_MASK) >> PWM_GCR_XRLDSYNCEN_SHIFT) /* - * FRCTIME (RW) + * HR_PWM_EN (RW) + * + * set to enable high resolution pwm, trig_cmp, start/reload register will have different definition. + */ +#define PWM_GCR_HR_PWM_EN_MASK (0x10U) +#define PWM_GCR_HR_PWM_EN_SHIFT (4U) +#define PWM_GCR_HR_PWM_EN_SET(x) (((uint32_t)(x) << PWM_GCR_HR_PWM_EN_SHIFT) & PWM_GCR_HR_PWM_EN_MASK) +#define PWM_GCR_HR_PWM_EN_GET(x) (((uint32_t)(x) & PWM_GCR_HR_PWM_EN_MASK) >> PWM_GCR_HR_PWM_EN_SHIFT) + +/* + * TIMERRESET (RW) + * + * set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear + */ +#define PWM_GCR_TIMERRESET_MASK (0x8U) +#define PWM_GCR_TIMERRESET_SHIFT (3U) +#define PWM_GCR_TIMERRESET_SET(x) (((uint32_t)(x) << PWM_GCR_TIMERRESET_SHIFT) & PWM_GCR_TIMERRESET_MASK) +#define PWM_GCR_TIMERRESET_GET(x) (((uint32_t)(x) & PWM_GCR_TIMERRESET_MASK) >> PWM_GCR_TIMERRESET_SHIFT) + +/* + * FRCTIME (WO) * * This bit field select the force effective time * 00: force immediately @@ -401,6 +483,36 @@ typedef struct { #define PWM_GCR_SWFRC_GET(x) (((uint32_t)(x) & PWM_GCR_SWFRC_MASK) >> PWM_GCR_SWFRC_SHIFT) /* Bitfield definition for register: SHCR */ +/* + * CNT_UPDATE_RELOAD (RW) + * + * set to update counter working register at reload point, clear to use cnt_update_time as old version. + */ +#define PWM_SHCR_CNT_UPDATE_RELOAD_MASK (0x8000U) +#define PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT (15U) +#define PWM_SHCR_CNT_UPDATE_RELOAD_SET(x) (((uint32_t)(x) << PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT) & PWM_SHCR_CNT_UPDATE_RELOAD_MASK) +#define PWM_SHCR_CNT_UPDATE_RELOAD_GET(x) (((uint32_t)(x) & PWM_SHCR_CNT_UPDATE_RELOAD_MASK) >> PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT) + +/* + * CNT_UPDATE_EDGE (RW) + * + * 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for counter shadow registers + */ +#define PWM_SHCR_CNT_UPDATE_EDGE_MASK (0x4000U) +#define PWM_SHCR_CNT_UPDATE_EDGE_SHIFT (14U) +#define PWM_SHCR_CNT_UPDATE_EDGE_SET(x) (((uint32_t)(x) << PWM_SHCR_CNT_UPDATE_EDGE_SHIFT) & PWM_SHCR_CNT_UPDATE_EDGE_MASK) +#define PWM_SHCR_CNT_UPDATE_EDGE_GET(x) (((uint32_t)(x) & PWM_SHCR_CNT_UPDATE_EDGE_MASK) >> PWM_SHCR_CNT_UPDATE_EDGE_SHIFT) + +/* + * FORCE_UPDATE_EDGE (RW) + * + * 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for FRCMD shadow registers + */ +#define PWM_SHCR_FORCE_UPDATE_EDGE_MASK (0x2000U) +#define PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT (13U) +#define PWM_SHCR_FORCE_UPDATE_EDGE_SET(x) (((uint32_t)(x) << PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT) & PWM_SHCR_FORCE_UPDATE_EDGE_MASK) +#define PWM_SHCR_FORCE_UPDATE_EDGE_GET(x) (((uint32_t)(x) & PWM_SHCR_FORCE_UPDATE_EDGE_MASK) >> PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT) + /* * FRCSHDWSEL (RW) * @@ -506,6 +618,19 @@ typedef struct { #define PWM_CNTCOPY_CNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_CNT_MASK) >> PWM_CNTCOPY_CNT_SHIFT) /* Bitfield definition for register array: PWMCFG */ +/* + * HR_UPDATE_MODE (RW) + * + * 0: update the hr value for the first edge at reload point; + * 1: update the hr value for the first edge at the last edge; + * all others will be updated at previous edge + * for pair mode, only pwm_cfg 0/2/4/6 are used + */ +#define PWM_PWMCFG_HR_UPDATE_MODE_MASK (0x20000000UL) +#define PWM_PWMCFG_HR_UPDATE_MODE_SHIFT (29U) +#define PWM_PWMCFG_HR_UPDATE_MODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_HR_UPDATE_MODE_SHIFT) & PWM_PWMCFG_HR_UPDATE_MODE_MASK) +#define PWM_PWMCFG_HR_UPDATE_MODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_HR_UPDATE_MODE_MASK) >> PWM_PWMCFG_HR_UPDATE_MODE_SHIFT) + /* * OEN (RW) * @@ -786,6 +911,31 @@ typedef struct { #define PWM_CMPCFG_CMPMODE_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPMODE_SHIFT) & PWM_CMPCFG_CMPMODE_MASK) #define PWM_CMPCFG_CMPMODE_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPMODE_MASK) >> PWM_CMPCFG_CMPMODE_SHIFT) +/* Bitfield definition for register array: ANASTS */ +/* + * CALON (RO) + * + * calibration status. + * will be set by hardware after setting cal_start. + * cleared after calibration finished + */ +#define PWM_ANASTS_CALON_MASK (0x80000000UL) +#define PWM_ANASTS_CALON_SHIFT (31U) +#define PWM_ANASTS_CALON_GET(x) (((uint32_t)(x) & PWM_ANASTS_CALON_MASK) >> PWM_ANASTS_CALON_SHIFT) + +/* Bitfield definition for register: HRPWM_CFG */ +/* + * CAL_START (WO) + * + * calibration start. + * software setting this bit to start calibration process. + * each bit for one channel. + */ +#define PWM_HRPWM_CFG_CAL_START_MASK (0xFFU) +#define PWM_HRPWM_CFG_CAL_START_SHIFT (0U) +#define PWM_HRPWM_CFG_CAL_START_SET(x) (((uint32_t)(x) << PWM_HRPWM_CFG_CAL_START_SHIFT) & PWM_HRPWM_CFG_CAL_START_MASK) +#define PWM_HRPWM_CFG_CAL_START_GET(x) (((uint32_t)(x) & PWM_HRPWM_CFG_CAL_START_MASK) >> PWM_HRPWM_CFG_CAL_START_SHIFT) + /* CMP register group index macro definition */ @@ -814,6 +964,32 @@ typedef struct { #define PWM_CMP_22 (22UL) #define PWM_CMP_23 (23UL) +/* CMP_HRPWM register group index macro definition */ +#define PWM_CMP_HRPWM_0 (0UL) +#define PWM_CMP_HRPWM_1 (1UL) +#define PWM_CMP_HRPWM_2 (2UL) +#define PWM_CMP_HRPWM_3 (3UL) +#define PWM_CMP_HRPWM_4 (4UL) +#define PWM_CMP_HRPWM_5 (5UL) +#define PWM_CMP_HRPWM_6 (6UL) +#define PWM_CMP_HRPWM_7 (7UL) +#define PWM_CMP_HRPWM_8 (8UL) +#define PWM_CMP_HRPWM_9 (9UL) +#define PWM_CMP_HRPWM_10 (10UL) +#define PWM_CMP_HRPWM_11 (11UL) +#define PWM_CMP_HRPWM_12 (12UL) +#define PWM_CMP_HRPWM_13 (13UL) +#define PWM_CMP_HRPWM_14 (14UL) +#define PWM_CMP_HRPWM_15 (15UL) +#define PWM_CMP_HRPWM_16 (16UL) +#define PWM_CMP_HRPWM_17 (17UL) +#define PWM_CMP_HRPWM_18 (18UL) +#define PWM_CMP_HRPWM_19 (19UL) +#define PWM_CMP_HRPWM_20 (20UL) +#define PWM_CMP_HRPWM_21 (21UL) +#define PWM_CMP_HRPWM_22 (22UL) +#define PWM_CMP_HRPWM_23 (23UL) + /* CHCFG register group index macro definition */ #define PWM_CHCFG_0 (0UL) #define PWM_CHCFG_1 (1UL) @@ -928,5 +1104,15 @@ typedef struct { #define PWM_CMPCFG_22 (22UL) #define PWM_CMPCFG_23 (23UL) +/* ANASTS register group index macro definition */ +#define PWM_ANASTS_0 (0UL) +#define PWM_ANASTS_1 (1UL) +#define PWM_ANASTS_2 (2UL) +#define PWM_ANASTS_3 (3UL) +#define PWM_ANASTS_4 (4UL) +#define PWM_ANASTS_5 (5UL) +#define PWM_ANASTS_6 (6UL) +#define PWM_ANASTS_7 (7UL) + #endif /* HPM_PWM_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_sdm_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_sdm_regs.h new file mode 100644 index 00000000..a2be18d7 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_sdm_regs.h @@ -0,0 +1,753 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SDM_H +#define HPM_SDM_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: SDM control register */ + __RW uint32_t INT_EN; /* 0x4: Interrupt enable register. */ + __R uint32_t STATUS; /* 0x8: Status Registers */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + struct { + __RW uint32_t SDFIFOCTRL; /* 0x10: Data FIFO Path Control Register */ + __RW uint32_t SDCTRLP; /* 0x14: Data Path Control Primary Register */ + __RW uint32_t SDCTRLE; /* 0x18: Data Path Control Extra Register */ + __RW uint32_t SDST; /* 0x1C: Data Path Status */ + __R uint32_t SDATA; /* 0x20: Data */ + __R uint32_t SDFIFO; /* 0x24: FIFO Data */ + __R uint32_t SCAMP; /* 0x28: instant Amplitude Results */ + __RW uint32_t SCHTL; /* 0x2C: Amplitude Threshold for High Limit */ + __RW uint32_t SCHTLZ; /* 0x30: Amplitude Threshold for zero crossing */ + __RW uint32_t SCLLT; /* 0x34: Amplitude Threshold for low limit */ + __RW uint32_t SCCTRL; /* 0x38: Amplitude Path Control */ + __RW uint32_t SCST; /* 0x3C: Amplitude Path Status */ + __R uint8_t RESERVED0[16]; /* 0x40 - 0x4F: Reserved */ + } CH[4]; +} SDM_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * SFTRST (RW) + * + * software reset the module if asserted to be1’b1. + */ +#define SDM_CTRL_SFTRST_MASK (0x80000000UL) +#define SDM_CTRL_SFTRST_SHIFT (31U) +#define SDM_CTRL_SFTRST_SET(x) (((uint32_t)(x) << SDM_CTRL_SFTRST_SHIFT) & SDM_CTRL_SFTRST_MASK) +#define SDM_CTRL_SFTRST_GET(x) (((uint32_t)(x) & SDM_CTRL_SFTRST_MASK) >> SDM_CTRL_SFTRST_SHIFT) + +/* + * CHMD (RW) + * + * Channel Rcv mode + * Bits[2:0] for Ch0. + * Bits[5:3] for Ch1 + * Bits[8:6] for Ch2 + * Bits[11:9] for Ch3 + * 3'b000: Capture at posedge of MCLK + * 3'b001: Capture at both posedge and negedge of MCLK + * 3'b010: Manchestor Mode + * 3'b011: Capture at negedge of MCLK + * 3'b100: Capture at every other posedge of MCLK + * 3'b101: Capture at every other negedge of MCLK + * Others: Undefined + */ +#define SDM_CTRL_CHMD_MASK (0x3FFC000UL) +#define SDM_CTRL_CHMD_SHIFT (14U) +#define SDM_CTRL_CHMD_SET(x) (((uint32_t)(x) << SDM_CTRL_CHMD_SHIFT) & SDM_CTRL_CHMD_MASK) +#define SDM_CTRL_CHMD_GET(x) (((uint32_t)(x) & SDM_CTRL_CHMD_MASK) >> SDM_CTRL_CHMD_SHIFT) + +/* + * SYNC_MCLK (RW) + * + * Asserted to double sync the mclk input pin before its usage inside the module + */ +#define SDM_CTRL_SYNC_MCLK_MASK (0x3C00U) +#define SDM_CTRL_SYNC_MCLK_SHIFT (10U) +#define SDM_CTRL_SYNC_MCLK_SET(x) (((uint32_t)(x) << SDM_CTRL_SYNC_MCLK_SHIFT) & SDM_CTRL_SYNC_MCLK_MASK) +#define SDM_CTRL_SYNC_MCLK_GET(x) (((uint32_t)(x) & SDM_CTRL_SYNC_MCLK_MASK) >> SDM_CTRL_SYNC_MCLK_SHIFT) + +/* + * SYNC_MDAT (RW) + * + * Asserted to double sync the mdat input pin before its usage inside the module + */ +#define SDM_CTRL_SYNC_MDAT_MASK (0x3C0U) +#define SDM_CTRL_SYNC_MDAT_SHIFT (6U) +#define SDM_CTRL_SYNC_MDAT_SET(x) (((uint32_t)(x) << SDM_CTRL_SYNC_MDAT_SHIFT) & SDM_CTRL_SYNC_MDAT_MASK) +#define SDM_CTRL_SYNC_MDAT_GET(x) (((uint32_t)(x) & SDM_CTRL_SYNC_MDAT_MASK) >> SDM_CTRL_SYNC_MDAT_SHIFT) + +/* + * CH_EN (RW) + * + * Channel Enable + */ +#define SDM_CTRL_CH_EN_MASK (0x3CU) +#define SDM_CTRL_CH_EN_SHIFT (2U) +#define SDM_CTRL_CH_EN_SET(x) (((uint32_t)(x) << SDM_CTRL_CH_EN_SHIFT) & SDM_CTRL_CH_EN_MASK) +#define SDM_CTRL_CH_EN_GET(x) (((uint32_t)(x) & SDM_CTRL_CH_EN_MASK) >> SDM_CTRL_CH_EN_SHIFT) + +/* + * IE (RW) + * + * Interrupt Enable + */ +#define SDM_CTRL_IE_MASK (0x2U) +#define SDM_CTRL_IE_SHIFT (1U) +#define SDM_CTRL_IE_SET(x) (((uint32_t)(x) << SDM_CTRL_IE_SHIFT) & SDM_CTRL_IE_MASK) +#define SDM_CTRL_IE_GET(x) (((uint32_t)(x) & SDM_CTRL_IE_MASK) >> SDM_CTRL_IE_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * CH3DRY (RW) + * + * Ch3 Data Ready interrupt enable. + */ +#define SDM_INT_EN_CH3DRY_MASK (0x80U) +#define SDM_INT_EN_CH3DRY_SHIFT (7U) +#define SDM_INT_EN_CH3DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH3DRY_SHIFT) & SDM_INT_EN_CH3DRY_MASK) +#define SDM_INT_EN_CH3DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH3DRY_MASK) >> SDM_INT_EN_CH3DRY_SHIFT) + +/* + * CH2DRY (RW) + * + * Ch2 Data Ready interrupt enable + */ +#define SDM_INT_EN_CH2DRY_MASK (0x40U) +#define SDM_INT_EN_CH2DRY_SHIFT (6U) +#define SDM_INT_EN_CH2DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH2DRY_SHIFT) & SDM_INT_EN_CH2DRY_MASK) +#define SDM_INT_EN_CH2DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH2DRY_MASK) >> SDM_INT_EN_CH2DRY_SHIFT) + +/* + * CH1DRY (RW) + * + * Ch1 Data Ready interrupt enable + */ +#define SDM_INT_EN_CH1DRY_MASK (0x20U) +#define SDM_INT_EN_CH1DRY_SHIFT (5U) +#define SDM_INT_EN_CH1DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH1DRY_SHIFT) & SDM_INT_EN_CH1DRY_MASK) +#define SDM_INT_EN_CH1DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH1DRY_MASK) >> SDM_INT_EN_CH1DRY_SHIFT) + +/* + * CH0DRY (RW) + * + * Ch0 Data Ready interrupt enable + */ +#define SDM_INT_EN_CH0DRY_MASK (0x10U) +#define SDM_INT_EN_CH0DRY_SHIFT (4U) +#define SDM_INT_EN_CH0DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH0DRY_SHIFT) & SDM_INT_EN_CH0DRY_MASK) +#define SDM_INT_EN_CH0DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH0DRY_MASK) >> SDM_INT_EN_CH0DRY_SHIFT) + +/* + * CH3ERR (RW) + * + * Ch3 Error interrupt enable. + */ +#define SDM_INT_EN_CH3ERR_MASK (0x8U) +#define SDM_INT_EN_CH3ERR_SHIFT (3U) +#define SDM_INT_EN_CH3ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH3ERR_SHIFT) & SDM_INT_EN_CH3ERR_MASK) +#define SDM_INT_EN_CH3ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH3ERR_MASK) >> SDM_INT_EN_CH3ERR_SHIFT) + +/* + * CH2ERR (RW) + * + * Ch2 Error interrupt enable + */ +#define SDM_INT_EN_CH2ERR_MASK (0x4U) +#define SDM_INT_EN_CH2ERR_SHIFT (2U) +#define SDM_INT_EN_CH2ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH2ERR_SHIFT) & SDM_INT_EN_CH2ERR_MASK) +#define SDM_INT_EN_CH2ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH2ERR_MASK) >> SDM_INT_EN_CH2ERR_SHIFT) + +/* + * CH1ERR (RW) + * + * Ch1 Error interrupt enable + */ +#define SDM_INT_EN_CH1ERR_MASK (0x2U) +#define SDM_INT_EN_CH1ERR_SHIFT (1U) +#define SDM_INT_EN_CH1ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH1ERR_SHIFT) & SDM_INT_EN_CH1ERR_MASK) +#define SDM_INT_EN_CH1ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH1ERR_MASK) >> SDM_INT_EN_CH1ERR_SHIFT) + +/* + * CH0ERR (RW) + * + * Ch0 Error interrupt enable + */ +#define SDM_INT_EN_CH0ERR_MASK (0x1U) +#define SDM_INT_EN_CH0ERR_SHIFT (0U) +#define SDM_INT_EN_CH0ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH0ERR_SHIFT) & SDM_INT_EN_CH0ERR_MASK) +#define SDM_INT_EN_CH0ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH0ERR_MASK) >> SDM_INT_EN_CH0ERR_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * CH3DRY (RO) + * + * Ch3 Data Ready. + * De-assert this bit by reading the data (or data fifo) registers. + */ +#define SDM_STATUS_CH3DRY_MASK (0x80U) +#define SDM_STATUS_CH3DRY_SHIFT (7U) +#define SDM_STATUS_CH3DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH3DRY_MASK) >> SDM_STATUS_CH3DRY_SHIFT) + +/* + * CH2DRY (RO) + * + * Ch2 Data Ready + */ +#define SDM_STATUS_CH2DRY_MASK (0x40U) +#define SDM_STATUS_CH2DRY_SHIFT (6U) +#define SDM_STATUS_CH2DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH2DRY_MASK) >> SDM_STATUS_CH2DRY_SHIFT) + +/* + * CH1DRY (RO) + * + * Ch1 Data Ready + */ +#define SDM_STATUS_CH1DRY_MASK (0x20U) +#define SDM_STATUS_CH1DRY_SHIFT (5U) +#define SDM_STATUS_CH1DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH1DRY_MASK) >> SDM_STATUS_CH1DRY_SHIFT) + +/* + * CH0DRY (RO) + * + * Ch0 Data Ready + */ +#define SDM_STATUS_CH0DRY_MASK (0x10U) +#define SDM_STATUS_CH0DRY_SHIFT (4U) +#define SDM_STATUS_CH0DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH0DRY_MASK) >> SDM_STATUS_CH0DRY_SHIFT) + +/* + * CH3ERR (RO) + * + * Ch3 Error. + * ORed together by channel related error signals and corresponding error interrupt enable signals. + * De-assert this bit by write-1-clear the corresponding error status bits in the channel status registers. + */ +#define SDM_STATUS_CH3ERR_MASK (0x8U) +#define SDM_STATUS_CH3ERR_SHIFT (3U) +#define SDM_STATUS_CH3ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH3ERR_MASK) >> SDM_STATUS_CH3ERR_SHIFT) + +/* + * CH2ERR (RO) + * + * Ch2 Error + */ +#define SDM_STATUS_CH2ERR_MASK (0x4U) +#define SDM_STATUS_CH2ERR_SHIFT (2U) +#define SDM_STATUS_CH2ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH2ERR_MASK) >> SDM_STATUS_CH2ERR_SHIFT) + +/* + * CH1ERR (RO) + * + * Ch1 Error + */ +#define SDM_STATUS_CH1ERR_MASK (0x2U) +#define SDM_STATUS_CH1ERR_SHIFT (1U) +#define SDM_STATUS_CH1ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH1ERR_MASK) >> SDM_STATUS_CH1ERR_SHIFT) + +/* + * CH0ERR (RO) + * + * Ch0 Error + */ +#define SDM_STATUS_CH0ERR_MASK (0x1U) +#define SDM_STATUS_CH0ERR_SHIFT (0U) +#define SDM_STATUS_CH0ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH0ERR_MASK) >> SDM_STATUS_CH0ERR_SHIFT) + +/* Bitfield definition for register of struct array CH: SDFIFOCTRL */ +/* + * THRSH (RW) + * + * FIFO threshold (0,..,16) (fillings > threshold, then gen int) + */ +#define SDM_CH_SDFIFOCTRL_THRSH_MASK (0x1F0U) +#define SDM_CH_SDFIFOCTRL_THRSH_SHIFT (4U) +#define SDM_CH_SDFIFOCTRL_THRSH_SET(x) (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_THRSH_SHIFT) & SDM_CH_SDFIFOCTRL_THRSH_MASK) +#define SDM_CH_SDFIFOCTRL_THRSH_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_THRSH_MASK) >> SDM_CH_SDFIFOCTRL_THRSH_SHIFT) + +/* + * D_RDY_INT_EN (RW) + * + * FIFO data ready interrupt enable + */ +#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK (0x4U) +#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT (2U) +#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SET(x) (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) & SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) +#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) >> SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) + +/* Bitfield definition for register of struct array CH: SDCTRLP */ +/* + * MANCH_THR (RW) + * + * Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] + */ +#define SDM_CH_SDCTRLP_MANCH_THR_MASK (0xFE000000UL) +#define SDM_CH_SDCTRLP_MANCH_THR_SHIFT (25U) +#define SDM_CH_SDCTRLP_MANCH_THR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_MANCH_THR_SHIFT) & SDM_CH_SDCTRLP_MANCH_THR_MASK) +#define SDM_CH_SDCTRLP_MANCH_THR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_MANCH_THR_MASK) >> SDM_CH_SDCTRLP_MANCH_THR_SHIFT) + +/* + * WDOG_THR (RW) + * + * Watch dog threshold for channel failure of CLK halting + */ +#define SDM_CH_SDCTRLP_WDOG_THR_MASK (0x1FE0000UL) +#define SDM_CH_SDCTRLP_WDOG_THR_SHIFT (17U) +#define SDM_CH_SDCTRLP_WDOG_THR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WDOG_THR_SHIFT) & SDM_CH_SDCTRLP_WDOG_THR_MASK) +#define SDM_CH_SDCTRLP_WDOG_THR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WDOG_THR_MASK) >> SDM_CH_SDCTRLP_WDOG_THR_SHIFT) + +/* + * AF_IE (RW) + * + * Acknowledge feedback interrupt enable + */ +#define SDM_CH_SDCTRLP_AF_IE_MASK (0x10000UL) +#define SDM_CH_SDCTRLP_AF_IE_SHIFT (16U) +#define SDM_CH_SDCTRLP_AF_IE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_AF_IE_SHIFT) & SDM_CH_SDCTRLP_AF_IE_MASK) +#define SDM_CH_SDCTRLP_AF_IE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_AF_IE_MASK) >> SDM_CH_SDCTRLP_AF_IE_SHIFT) + +/* + * DFFOVIE (RW) + * + * Ch Data FIFO overflow interrupt enable + */ +#define SDM_CH_SDCTRLP_DFFOVIE_MASK (0x8000U) +#define SDM_CH_SDCTRLP_DFFOVIE_SHIFT (15U) +#define SDM_CH_SDCTRLP_DFFOVIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DFFOVIE_SHIFT) & SDM_CH_SDCTRLP_DFFOVIE_MASK) +#define SDM_CH_SDCTRLP_DFFOVIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DFFOVIE_MASK) >> SDM_CH_SDCTRLP_DFFOVIE_SHIFT) + +/* + * DSATIE (RW) + * + * Ch CIC Data Saturation Interrupt Enable + */ +#define SDM_CH_SDCTRLP_DSATIE_MASK (0x4000U) +#define SDM_CH_SDCTRLP_DSATIE_SHIFT (14U) +#define SDM_CH_SDCTRLP_DSATIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DSATIE_SHIFT) & SDM_CH_SDCTRLP_DSATIE_MASK) +#define SDM_CH_SDCTRLP_DSATIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DSATIE_MASK) >> SDM_CH_SDCTRLP_DSATIE_SHIFT) + +/* + * DRIE (RW) + * + * Ch Data Ready Interrupt Enable + */ +#define SDM_CH_SDCTRLP_DRIE_MASK (0x2000U) +#define SDM_CH_SDCTRLP_DRIE_SHIFT (13U) +#define SDM_CH_SDCTRLP_DRIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DRIE_SHIFT) & SDM_CH_SDCTRLP_DRIE_MASK) +#define SDM_CH_SDCTRLP_DRIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DRIE_MASK) >> SDM_CH_SDCTRLP_DRIE_SHIFT) + +/* + * SYNCSEL (RW) + * + * Select the PWM SYNC Source + */ +#define SDM_CH_SDCTRLP_SYNCSEL_MASK (0x1F80U) +#define SDM_CH_SDCTRLP_SYNCSEL_SHIFT (7U) +#define SDM_CH_SDCTRLP_SYNCSEL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_SYNCSEL_SHIFT) & SDM_CH_SDCTRLP_SYNCSEL_MASK) +#define SDM_CH_SDCTRLP_SYNCSEL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_SYNCSEL_MASK) >> SDM_CH_SDCTRLP_SYNCSEL_SHIFT) + +/* + * FFSYNCCLREN (RW) + * + * Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 + */ +#define SDM_CH_SDCTRLP_FFSYNCCLREN_MASK (0x40U) +#define SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT (6U) +#define SDM_CH_SDCTRLP_FFSYNCCLREN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK) +#define SDM_CH_SDCTRLP_FFSYNCCLREN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK) >> SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT) + +/* + * WTSYNACLR (RW) + * + * 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen + * 0: WTSYNFLG should be cleared manually by WTSYNMCLR + */ +#define SDM_CH_SDCTRLP_WTSYNACLR_MASK (0x20U) +#define SDM_CH_SDCTRLP_WTSYNACLR_SHIFT (5U) +#define SDM_CH_SDCTRLP_WTSYNACLR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNACLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNACLR_MASK) +#define SDM_CH_SDCTRLP_WTSYNACLR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNACLR_MASK) >> SDM_CH_SDCTRLP_WTSYNACLR_SHIFT) + +/* + * WTSYNMCLR (RW) + * + * 1: Manually clear WTSYNFLG. Auto-clear. + */ +#define SDM_CH_SDCTRLP_WTSYNMCLR_MASK (0x10U) +#define SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT (4U) +#define SDM_CH_SDCTRLP_WTSYNMCLR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK) +#define SDM_CH_SDCTRLP_WTSYNMCLR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK) >> SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT) + +/* + * WTSYNCEN (RW) + * + * 1: Start to store data only after PWM SYNC event + * 0: Start to store data whenever enabled + */ +#define SDM_CH_SDCTRLP_WTSYNCEN_MASK (0x8U) +#define SDM_CH_SDCTRLP_WTSYNCEN_SHIFT (3U) +#define SDM_CH_SDCTRLP_WTSYNCEN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNCEN_SHIFT) & SDM_CH_SDCTRLP_WTSYNCEN_MASK) +#define SDM_CH_SDCTRLP_WTSYNCEN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNCEN_MASK) >> SDM_CH_SDCTRLP_WTSYNCEN_SHIFT) + +/* + * D32 (RW) + * + * 1:32 bit data + * 0:16 bit data + */ +#define SDM_CH_SDCTRLP_D32_MASK (0x4U) +#define SDM_CH_SDCTRLP_D32_SHIFT (2U) +#define SDM_CH_SDCTRLP_D32_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_D32_SHIFT) & SDM_CH_SDCTRLP_D32_MASK) +#define SDM_CH_SDCTRLP_D32_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_D32_MASK) >> SDM_CH_SDCTRLP_D32_SHIFT) + +/* + * DR_OPT (RW) + * + * 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold + * 0: Use Data Reg Ready as data ready + */ +#define SDM_CH_SDCTRLP_DR_OPT_MASK (0x2U) +#define SDM_CH_SDCTRLP_DR_OPT_SHIFT (1U) +#define SDM_CH_SDCTRLP_DR_OPT_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DR_OPT_SHIFT) & SDM_CH_SDCTRLP_DR_OPT_MASK) +#define SDM_CH_SDCTRLP_DR_OPT_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DR_OPT_MASK) >> SDM_CH_SDCTRLP_DR_OPT_SHIFT) + +/* + * EN (RW) + * + * Data Path Enable + */ +#define SDM_CH_SDCTRLP_EN_MASK (0x1U) +#define SDM_CH_SDCTRLP_EN_SHIFT (0U) +#define SDM_CH_SDCTRLP_EN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_EN_SHIFT) & SDM_CH_SDCTRLP_EN_MASK) +#define SDM_CH_SDCTRLP_EN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_EN_MASK) >> SDM_CH_SDCTRLP_EN_SHIFT) + +/* Bitfield definition for register of struct array CH: SDCTRLE */ +/* + * SGD_ORDR (RW) + * + * CIC order + * 0: SYNC1 + * 1: SYNC2 + * 2: SYNC3 + * 3: FAST_SYNC + */ +#define SDM_CH_SDCTRLE_SGD_ORDR_MASK (0x60000UL) +#define SDM_CH_SDCTRLE_SGD_ORDR_SHIFT (17U) +#define SDM_CH_SDCTRLE_SGD_ORDR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_SGD_ORDR_SHIFT) & SDM_CH_SDCTRLE_SGD_ORDR_MASK) +#define SDM_CH_SDCTRLE_SGD_ORDR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_SGD_ORDR_MASK) >> SDM_CH_SDCTRLE_SGD_ORDR_SHIFT) + +/* + * PWMSYNC (RW) + * + * Asserted to double sync the PWM trigger signal + */ +#define SDM_CH_SDCTRLE_PWMSYNC_MASK (0x10000UL) +#define SDM_CH_SDCTRLE_PWMSYNC_SHIFT (16U) +#define SDM_CH_SDCTRLE_PWMSYNC_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_PWMSYNC_SHIFT) & SDM_CH_SDCTRLE_PWMSYNC_MASK) +#define SDM_CH_SDCTRLE_PWMSYNC_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_PWMSYNC_MASK) >> SDM_CH_SDCTRLE_PWMSYNC_SHIFT) + +/* + * CIC_SCL (RW) + * + * CIC shift control + */ +#define SDM_CH_SDCTRLE_CIC_SCL_MASK (0x7800U) +#define SDM_CH_SDCTRLE_CIC_SCL_SHIFT (11U) +#define SDM_CH_SDCTRLE_CIC_SCL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_SCL_SHIFT) & SDM_CH_SDCTRLE_CIC_SCL_MASK) +#define SDM_CH_SDCTRLE_CIC_SCL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_SCL_MASK) >> SDM_CH_SDCTRLE_CIC_SCL_SHIFT) + +/* + * CIC_DEC_RATIO (RW) + * + * CIC decimation ratio. 0 means div-by-256 + */ +#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK (0x7F8U) +#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT (3U) +#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK) +#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK) >> SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) + +/* + * IGN_INI_SAMPLES (RW) + * + * NotZero: Don't store the first samples that are not accurate + * Zero: Store all samples + */ +#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK (0x7U) +#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT (0U) +#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) +#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) >> SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) + +/* Bitfield definition for register of struct array CH: SDST */ +/* + * PERIOD_MCLK (RO) + * + * maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. + */ +#define SDM_CH_SDST_PERIOD_MCLK_MASK (0x7F800000UL) +#define SDM_CH_SDST_PERIOD_MCLK_SHIFT (23U) +#define SDM_CH_SDST_PERIOD_MCLK_GET(x) (((uint32_t)(x) & SDM_CH_SDST_PERIOD_MCLK_MASK) >> SDM_CH_SDST_PERIOD_MCLK_SHIFT) + +/* + * FIFO_DR (W1C) + * + * FIFO data ready + */ +#define SDM_CH_SDST_FIFO_DR_MASK (0x200U) +#define SDM_CH_SDST_FIFO_DR_SHIFT (9U) +#define SDM_CH_SDST_FIFO_DR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_FIFO_DR_SHIFT) & SDM_CH_SDST_FIFO_DR_MASK) +#define SDM_CH_SDST_FIFO_DR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_FIFO_DR_MASK) >> SDM_CH_SDST_FIFO_DR_SHIFT) + +/* + * AF (W1C) + * + * Achnowledge flag + */ +#define SDM_CH_SDST_AF_MASK (0x100U) +#define SDM_CH_SDST_AF_SHIFT (8U) +#define SDM_CH_SDST_AF_SET(x) (((uint32_t)(x) << SDM_CH_SDST_AF_SHIFT) & SDM_CH_SDST_AF_MASK) +#define SDM_CH_SDST_AF_GET(x) (((uint32_t)(x) & SDM_CH_SDST_AF_MASK) >> SDM_CH_SDST_AF_SHIFT) + +/* + * DOV_ERR (W1C) + * + * Data FIFO Overflow Error. Error flag. + */ +#define SDM_CH_SDST_DOV_ERR_MASK (0x80U) +#define SDM_CH_SDST_DOV_ERR_SHIFT (7U) +#define SDM_CH_SDST_DOV_ERR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_DOV_ERR_SHIFT) & SDM_CH_SDST_DOV_ERR_MASK) +#define SDM_CH_SDST_DOV_ERR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_DOV_ERR_MASK) >> SDM_CH_SDST_DOV_ERR_SHIFT) + +/* + * DSAT_ERR (W1C) + * + * CIC out Data saturation err. Error flag. + */ +#define SDM_CH_SDST_DSAT_ERR_MASK (0x40U) +#define SDM_CH_SDST_DSAT_ERR_SHIFT (6U) +#define SDM_CH_SDST_DSAT_ERR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_DSAT_ERR_SHIFT) & SDM_CH_SDST_DSAT_ERR_MASK) +#define SDM_CH_SDST_DSAT_ERR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_DSAT_ERR_MASK) >> SDM_CH_SDST_DSAT_ERR_SHIFT) + +/* + * WTSYNFLG (RO) + * + * Wait-for-sync event found + */ +#define SDM_CH_SDST_WTSYNFLG_MASK (0x20U) +#define SDM_CH_SDST_WTSYNFLG_SHIFT (5U) +#define SDM_CH_SDST_WTSYNFLG_GET(x) (((uint32_t)(x) & SDM_CH_SDST_WTSYNFLG_MASK) >> SDM_CH_SDST_WTSYNFLG_SHIFT) + +/* + * FILL (RO) + * + * Data FIFO Fillings + */ +#define SDM_CH_SDST_FILL_MASK (0x1FU) +#define SDM_CH_SDST_FILL_SHIFT (0U) +#define SDM_CH_SDST_FILL_GET(x) (((uint32_t)(x) & SDM_CH_SDST_FILL_MASK) >> SDM_CH_SDST_FILL_SHIFT) + +/* Bitfield definition for register of struct array CH: SDATA */ +/* + * VAL (RO) + * + * Data + */ +#define SDM_CH_SDATA_VAL_MASK (0xFFFFFFFFUL) +#define SDM_CH_SDATA_VAL_SHIFT (0U) +#define SDM_CH_SDATA_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SDATA_VAL_MASK) >> SDM_CH_SDATA_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SDFIFO */ +/* + * VAL (RO) + * + * FIFO Data + */ +#define SDM_CH_SDFIFO_VAL_MASK (0xFFFFFFFFUL) +#define SDM_CH_SDFIFO_VAL_SHIFT (0U) +#define SDM_CH_SDFIFO_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFO_VAL_MASK) >> SDM_CH_SDFIFO_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCAMP */ +/* + * VAL (RO) + * + * instant Amplitude Results + */ +#define SDM_CH_SCAMP_VAL_MASK (0xFFFFU) +#define SDM_CH_SCAMP_VAL_SHIFT (0U) +#define SDM_CH_SCAMP_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCAMP_VAL_MASK) >> SDM_CH_SCAMP_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCHTL */ +/* + * VAL (RW) + * + * Amplitude Threshold for High Limit + */ +#define SDM_CH_SCHTL_VAL_MASK (0xFFFFU) +#define SDM_CH_SCHTL_VAL_SHIFT (0U) +#define SDM_CH_SCHTL_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCHTL_VAL_SHIFT) & SDM_CH_SCHTL_VAL_MASK) +#define SDM_CH_SCHTL_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCHTL_VAL_MASK) >> SDM_CH_SCHTL_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCHTLZ */ +/* + * VAL (RW) + * + * Amplitude Threshold for zero crossing + */ +#define SDM_CH_SCHTLZ_VAL_MASK (0xFFFFU) +#define SDM_CH_SCHTLZ_VAL_SHIFT (0U) +#define SDM_CH_SCHTLZ_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCHTLZ_VAL_SHIFT) & SDM_CH_SCHTLZ_VAL_MASK) +#define SDM_CH_SCHTLZ_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCHTLZ_VAL_MASK) >> SDM_CH_SCHTLZ_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCLLT */ +/* + * VAL (RW) + * + * Amplitude Threshold for low limit + */ +#define SDM_CH_SCLLT_VAL_MASK (0xFFFFU) +#define SDM_CH_SCLLT_VAL_SHIFT (0U) +#define SDM_CH_SCLLT_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCLLT_VAL_SHIFT) & SDM_CH_SCLLT_VAL_MASK) +#define SDM_CH_SCLLT_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCLLT_VAL_MASK) >> SDM_CH_SCLLT_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCCTRL */ +/* + * HZ_EN (RW) + * + * Zero Crossing Enable + */ +#define SDM_CH_SCCTRL_HZ_EN_MASK (0x800000UL) +#define SDM_CH_SCCTRL_HZ_EN_SHIFT (23U) +#define SDM_CH_SCCTRL_HZ_EN_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_HZ_EN_SHIFT) & SDM_CH_SCCTRL_HZ_EN_MASK) +#define SDM_CH_SCCTRL_HZ_EN_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_HZ_EN_MASK) >> SDM_CH_SCCTRL_HZ_EN_SHIFT) + +/* + * MF_IE (RW) + * + * Module failure Interrupt enable + */ +#define SDM_CH_SCCTRL_MF_IE_MASK (0x400000UL) +#define SDM_CH_SCCTRL_MF_IE_SHIFT (22U) +#define SDM_CH_SCCTRL_MF_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_MF_IE_SHIFT) & SDM_CH_SCCTRL_MF_IE_MASK) +#define SDM_CH_SCCTRL_MF_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_MF_IE_MASK) >> SDM_CH_SCCTRL_MF_IE_SHIFT) + +/* + * HL_IE (RW) + * + * HLT Interrupt Enable + */ +#define SDM_CH_SCCTRL_HL_IE_MASK (0x200000UL) +#define SDM_CH_SCCTRL_HL_IE_SHIFT (21U) +#define SDM_CH_SCCTRL_HL_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_HL_IE_SHIFT) & SDM_CH_SCCTRL_HL_IE_MASK) +#define SDM_CH_SCCTRL_HL_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_HL_IE_MASK) >> SDM_CH_SCCTRL_HL_IE_SHIFT) + +/* + * LL_IE (RW) + * + * LLT interrupt Enable + */ +#define SDM_CH_SCCTRL_LL_IE_MASK (0x100000UL) +#define SDM_CH_SCCTRL_LL_IE_SHIFT (20U) +#define SDM_CH_SCCTRL_LL_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_LL_IE_SHIFT) & SDM_CH_SCCTRL_LL_IE_MASK) +#define SDM_CH_SCCTRL_LL_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_LL_IE_MASK) >> SDM_CH_SCCTRL_LL_IE_SHIFT) + +/* + * SGD_ORDR (RW) + * + * CIC order + * 0: SYNC1 + * 1: SYNC2 + * 2: SYNC3 + * 3: FAST_SYNC + */ +#define SDM_CH_SCCTRL_SGD_ORDR_MASK (0xC0000UL) +#define SDM_CH_SCCTRL_SGD_ORDR_SHIFT (18U) +#define SDM_CH_SCCTRL_SGD_ORDR_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_SGD_ORDR_SHIFT) & SDM_CH_SCCTRL_SGD_ORDR_MASK) +#define SDM_CH_SCCTRL_SGD_ORDR_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_SGD_ORDR_MASK) >> SDM_CH_SCCTRL_SGD_ORDR_SHIFT) + +/* + * CIC_DEC_RATIO (RW) + * + * CIC decimation ratio. 0 means div-by-32 + */ +#define SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK (0x1F0U) +#define SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT (4U) +#define SDM_CH_SCCTRL_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK) +#define SDM_CH_SCCTRL_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK) >> SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) + +/* + * IGN_INI_SAMPLES (RW) + * + * NotZero: Ignore the first samples that are not accurate + * Zero: Use all samples + */ +#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK (0xEU) +#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT (1U) +#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK) +#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK) >> SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) + +/* + * EN (RW) + * + * Amplitude Path Enable + */ +#define SDM_CH_SCCTRL_EN_MASK (0x1U) +#define SDM_CH_SCCTRL_EN_SHIFT (0U) +#define SDM_CH_SCCTRL_EN_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_EN_SHIFT) & SDM_CH_SCCTRL_EN_MASK) +#define SDM_CH_SCCTRL_EN_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_EN_MASK) >> SDM_CH_SCCTRL_EN_SHIFT) + +/* Bitfield definition for register of struct array CH: SCST */ +/* + * HZ (W1C) + * + * Amplitude rising above HZ event found. + */ +#define SDM_CH_SCST_HZ_MASK (0x8U) +#define SDM_CH_SCST_HZ_SHIFT (3U) +#define SDM_CH_SCST_HZ_SET(x) (((uint32_t)(x) << SDM_CH_SCST_HZ_SHIFT) & SDM_CH_SCST_HZ_MASK) +#define SDM_CH_SCST_HZ_GET(x) (((uint32_t)(x) & SDM_CH_SCST_HZ_MASK) >> SDM_CH_SCST_HZ_SHIFT) + +/* + * MF (W1C) + * + * power modulator Failure found. MCLK not found. Error flag. + */ +#define SDM_CH_SCST_MF_MASK (0x4U) +#define SDM_CH_SCST_MF_SHIFT (2U) +#define SDM_CH_SCST_MF_SET(x) (((uint32_t)(x) << SDM_CH_SCST_MF_SHIFT) & SDM_CH_SCST_MF_MASK) +#define SDM_CH_SCST_MF_GET(x) (((uint32_t)(x) & SDM_CH_SCST_MF_MASK) >> SDM_CH_SCST_MF_SHIFT) + +/* + * CMPH (W1C) + * + * HLT out of range. Error flag. + */ +#define SDM_CH_SCST_CMPH_MASK (0x2U) +#define SDM_CH_SCST_CMPH_SHIFT (1U) +#define SDM_CH_SCST_CMPH_SET(x) (((uint32_t)(x) << SDM_CH_SCST_CMPH_SHIFT) & SDM_CH_SCST_CMPH_MASK) +#define SDM_CH_SCST_CMPH_GET(x) (((uint32_t)(x) & SDM_CH_SCST_CMPH_MASK) >> SDM_CH_SCST_CMPH_SHIFT) + +/* + * CMPL (W1C) + * + * LLT out of range. Error flag. + */ +#define SDM_CH_SCST_CMPL_MASK (0x1U) +#define SDM_CH_SCST_CMPL_SHIFT (0U) +#define SDM_CH_SCST_CMPL_SET(x) (((uint32_t)(x) << SDM_CH_SCST_CMPL_SHIFT) & SDM_CH_SCST_CMPL_MASK) +#define SDM_CH_SCST_CMPL_GET(x) (((uint32_t)(x) & SDM_CH_SCST_CMPL_MASK) >> SDM_CH_SCST_CMPL_SHIFT) + + + +/* CH register group index macro definition */ +#define SDM_CH_0 (0UL) +#define SDM_CH_1 (1UL) +#define SDM_CH_2 (2UL) +#define SDM_CH_3 (3UL) + + +#endif /* HPM_SDM_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h index 6af8b773..5ac04df1 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_sdp_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -170,6 +170,7 @@ typedef struct { * AES algorithem selection. * 0x0 = AES 128; * 0x1 = AES 256; + * 0x8 = SM4； * Others, reserved. */ #define SDP_MODCTRL_AESALG_MASK (0xF0000000UL) diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h index c2033c65..bf7294b0 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h @@ -10,10 +10,12 @@ #define HPM_UART_H typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ + __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ + __RW uint32_t RXIDLE_CFG; /* 0x4: Receive Idle Configuration Register */ + __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ __RW uint32_t CFG; /* 0x10: Configuration Register */ __RW uint32_t OSCR; /* 0x14: Over Sample Control Register */ - __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ + __R uint8_t RESERVED2[8]; /* 0x18 - 0x1F: Reserved */ union { __R uint32_t RBR; /* 0x20: Receiver Buffer Register (when DLAB = 0) */ __W uint32_t THR; /* 0x20: Transmitter Holding Register (when DLAB = 0) */ @@ -24,7 +26,7 @@ typedef struct { __RW uint32_t DLM; /* 0x24: Divisor Latch MSB (when DLAB = 1) */ }; union { - __R uint32_t IIR; /* 0x28: Interrupt Identification Register */ + __RW uint32_t IIR; /* 0x28: Interrupt Identification Register */ __W uint32_t FCR; /* 0x28: FIFO Control Register */ }; __RW uint32_t LCR; /* 0x2C: Line Control Register */ @@ -34,6 +36,41 @@ typedef struct { } UART_Type; +/* Bitfield definition for register: RXIDLE_CFG */ +/* + * DETECT_COND (RW) + * + * IDLE Detection Condition + * 0 - Treat as idle if RX pin is logic one + * 1 - Treat as idle if UART state machine state is idle + */ +#define UART_RXIDLE_CFG_DETECT_COND_MASK (0x200U) +#define UART_RXIDLE_CFG_DETECT_COND_SHIFT (9U) +#define UART_RXIDLE_CFG_DETECT_COND_SET(x) (((uint32_t)(x) << UART_RXIDLE_CFG_DETECT_COND_SHIFT) & UART_RXIDLE_CFG_DETECT_COND_MASK) +#define UART_RXIDLE_CFG_DETECT_COND_GET(x) (((uint32_t)(x) & UART_RXIDLE_CFG_DETECT_COND_MASK) >> UART_RXIDLE_CFG_DETECT_COND_SHIFT) + +/* + * DETECT_EN (RW) + * + * UART Idle Detect Enable + * 0 - Disable + * 1 - Enable + */ +#define UART_RXIDLE_CFG_DETECT_EN_MASK (0x100U) +#define UART_RXIDLE_CFG_DETECT_EN_SHIFT (8U) +#define UART_RXIDLE_CFG_DETECT_EN_SET(x) (((uint32_t)(x) << UART_RXIDLE_CFG_DETECT_EN_SHIFT) & UART_RXIDLE_CFG_DETECT_EN_MASK) +#define UART_RXIDLE_CFG_DETECT_EN_GET(x) (((uint32_t)(x) & UART_RXIDLE_CFG_DETECT_EN_MASK) >> UART_RXIDLE_CFG_DETECT_EN_SHIFT) + +/* + * THR (RW) + * + * Threshold for UART Receive Idle detection (in terms of bits) + */ +#define UART_RXIDLE_CFG_THR_MASK (0xFFU) +#define UART_RXIDLE_CFG_THR_SHIFT (0U) +#define UART_RXIDLE_CFG_THR_SET(x) (((uint32_t)(x) << UART_RXIDLE_CFG_THR_SHIFT) & UART_RXIDLE_CFG_THR_MASK) +#define UART_RXIDLE_CFG_THR_GET(x) (((uint32_t)(x) & UART_RXIDLE_CFG_THR_MASK) >> UART_RXIDLE_CFG_THR_SHIFT) + /* Bitfield definition for register: CFG */ /* * FIFOSIZE (RO) @@ -97,6 +134,18 @@ typedef struct { #define UART_DLL_DLL_GET(x) (((uint32_t)(x) & UART_DLL_DLL_MASK) >> UART_DLL_DLL_SHIFT) /* Bitfield definition for register: IER */ +/* + * ERXIDLE (RW) + * + * Enable Receive Idle interrupt + * 0 - Disable Idle interrupt + * 1 - Enable Idle interrupt + */ +#define UART_IER_ERXIDLE_MASK (0x80000000UL) +#define UART_IER_ERXIDLE_SHIFT (31U) +#define UART_IER_ERXIDLE_SET(x) (((uint32_t)(x) << UART_IER_ERXIDLE_SHIFT) & UART_IER_ERXIDLE_MASK) +#define UART_IER_ERXIDLE_GET(x) (((uint32_t)(x) & UART_IER_ERXIDLE_MASK) >> UART_IER_ERXIDLE_SHIFT) + /* * EMSI (RW) * @@ -159,6 +208,18 @@ typedef struct { #define UART_DLM_DLM_GET(x) (((uint32_t)(x) & UART_DLM_DLM_MASK) >> UART_DLM_DLM_SHIFT) /* Bitfield definition for register: IIR */ +/* + * RXIDLE_FLAG (RW) + * + * UART IDLE Flag + * 0 - UART is busy + * 1 - UART is idle + */ +#define UART_IIR_RXIDLE_FLAG_MASK (0x80000000UL) +#define UART_IIR_RXIDLE_FLAG_SHIFT (31U) +#define UART_IIR_RXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR_RXIDLE_FLAG_SHIFT) & UART_IIR_RXIDLE_FLAG_MASK) +#define UART_IIR_RXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR_RXIDLE_FLAG_MASK) >> UART_IIR_RXIDLE_FLAG_SHIFT) + /* * FIFOED (RO) * diff --git a/common/libraries/hpm_sdk/utils/CMakeLists.txt b/common/libraries/hpm_sdk/utils/CMakeLists.txt index b3ee1569..e731f683 100644 --- a/common/libraries/hpm_sdk/utils/CMakeLists.txt +++ b/common/libraries/hpm_sdk/utils/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause sdk_inc(.) diff --git a/common/libraries/hpm_sdk/utils/hpm_ffssi.c b/common/libraries/hpm_sdk/utils/hpm_ffssi.c index 3db7cd36..75ca411f 100644 --- a/common/libraries/hpm_sdk/utils/hpm_ffssi.c +++ b/common/libraries/hpm_sdk/utils/hpm_ffssi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/utils/hpm_sbrk.c b/common/libraries/hpm_sdk/utils/hpm_sbrk.c index 8c4a9590..027d8c66 100644 --- a/common/libraries/hpm_sdk/utils/hpm_sbrk.c +++ b/common/libraries/hpm_sdk/utils/hpm_sbrk.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/libraries/hpm_sdk/utils/hpm_swap.c b/common/libraries/hpm_sdk/utils/hpm_swap.c index b728f257..36d90c1c 100644 --- a/common/libraries/hpm_sdk/utils/hpm_swap.c +++ b/common/libraries/hpm_sdk/utils/hpm_swap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * diff --git a/common/rt-thread/components/drivers/sdio/block_dev.c b/common/rt-thread/components/drivers/sdio/block_dev.c index 40675660..8aabb6d5 100644 --- a/common/rt-thread/components/drivers/sdio/block_dev.c +++ b/common/rt-thread/components/drivers/sdio/block_dev.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2011-07-25 weety first version + * 2011-07-25 weety first version + * 2023-05-06 hpmicro avoid null dereference issue in rt_mmcsd_blk_remove */ #include @@ -505,22 +506,25 @@ void rt_mmcsd_blk_remove(struct rt_mmcsd_card *card) rt_list_t *l, *n; struct mmcsd_blk_device *blk_dev; - for (l = (&card->blk_devices)->next, n = l->next; l != &card->blk_devices; l = n, n=n->next) + if (card->blk_devices.next != RT_NULL) { - blk_dev = (struct mmcsd_blk_device *)rt_list_entry(l, struct mmcsd_blk_device, list); - if (blk_dev->card == card) + for (l = (&card->blk_devices)->next, n = l->next; l != &card->blk_devices; l = n, n=n->next) { - /* unmount file system */ - const char * mounted_path = dfs_filesystem_get_mounted_path(&(blk_dev->dev)); - if (mounted_path) + blk_dev = (struct mmcsd_blk_device *)rt_list_entry(l, struct mmcsd_blk_device, list); + if (blk_dev->card == card) { - dfs_unmount(mounted_path); - LOG_D("unmount file system %s for device %s.\r\n", mounted_path, blk_dev->dev.parent.name); + /* unmount file system */ + const char * mounted_path = dfs_filesystem_get_mounted_path(&(blk_dev->dev)); + if (mounted_path) + { + dfs_unmount(mounted_path); + LOG_D("unmount file system %s for device %s.\r\n", mounted_path, blk_dev->dev.parent.name); + } + rt_sem_delete(blk_dev->part.lock); + rt_device_unregister(&blk_dev->dev); + rt_list_remove(&blk_dev->list); + rt_free(blk_dev); } - rt_sem_delete(blk_dev->part.lock); - rt_device_unregister(&blk_dev->dev); - rt_list_remove(&blk_dev->list); - rt_free(blk_dev); } } } diff --git a/common/rt-thread/components/drivers/sdio/mmc.c b/common/rt-thread/components/drivers/sdio/mmc.c index ac017265..1c730894 100644 --- a/common/rt-thread/components/drivers/sdio/mmc.c +++ b/common/rt-thread/components/drivers/sdio/mmc.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2015-06-15 hichard first version + * 2023-05-23 hpmicro Correct the bus_width setting issue */ #include @@ -294,6 +295,13 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) EXT_CSD_BUS_WIDTH_4, EXT_CSD_BUS_WIDTH_1 }; + + rt_uint32_t bus_widths[] = { + MMCSD_BUS_WIDTH_8, + MMCSD_BUS_WIDTH_4, + MMCSD_BUS_WIDTH_1 + }; + struct rt_mmcsd_host *host = card->host; unsigned idx, trys, bus_width = 0; int err = 0; @@ -330,6 +338,7 @@ static int mmc_select_bus_width(struct rt_mmcsd_card *card, rt_uint8_t *ext_csd) if (err) continue; + bus_width = bus_widths[idx]; for(trys = 0; trys < 5; trys++){ mmcsd_set_bus_width(host, bus_width); mmcsd_delay_ms(10); diff --git a/common/rt-thread/components/drivers/sdio/mmcsd_core.c b/common/rt-thread/components/drivers/sdio/mmcsd_core.c index b4e08e55..5cd2ea81 100644 --- a/common/rt-thread/components/drivers/sdio/mmcsd_core.c +++ b/common/rt-thread/components/drivers/sdio/mmcsd_core.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-07-25 weety first version + * 2023-05-06 hpmicro Correct the logic of SPI CS control in mmcsd_go_idle */ #include @@ -107,7 +108,7 @@ rt_int32_t mmcsd_go_idle(struct rt_mmcsd_host *host) rt_int32_t err; struct rt_mmcsd_cmd cmd; - if (!controller_is_spi(host)) + if (controller_is_spi(host)) { mmcsd_set_chip_select(host, MMCSD_CS_HIGH); mmcsd_delay_ms(1); @@ -123,7 +124,7 @@ rt_int32_t mmcsd_go_idle(struct rt_mmcsd_host *host) mmcsd_delay_ms(1); - if (!controller_is_spi(host)) + if (controller_is_spi(host)) { mmcsd_set_chip_select(host, MMCSD_CS_IGNORE); mmcsd_delay_ms(1); @@ -751,4 +752,3 @@ int rt_mmcsd_core_init(void) return 0; } INIT_PREV_EXPORT(rt_mmcsd_core_init); - diff --git a/common/rt-thread/components/net/lwip/port/lwipopts.h b/common/rt-thread/components/net/lwip/port/lwipopts.h index 8c6c9cfc..3d327f3f 100644 --- a/common/rt-thread/components/net/lwip/port/lwipopts.h +++ b/common/rt-thread/components/net/lwip/port/lwipopts.h @@ -276,7 +276,7 @@ #define MEM_ALIGNMENT 4 #endif -#define MEMP_OVERFLOW_CHECK 1 +#define MEMP_OVERFLOW_CHECK 0 #define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 1 //#define MEM_LIBC_MALLOC 1 diff --git a/common/startup/HPM6280/SConscript b/common/startup/HPM6280/SConscript new file mode 100644 index 00000000..18c366ba --- /dev/null +++ b/common/startup/HPM6280/SConscript @@ -0,0 +1,21 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Split(''' + startup.c + trap.c +''') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D45', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/common/startup/HPM6280/startup.c b/common/startup/HPM6280/startup.c new file mode 100644 index 00000000..5d6123bd --- /dev/null +++ b/common/startup/HPM6280/startup.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Do global constructors */ + __libc_init_array(); + + + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init() +{ +} diff --git a/common/startup/HPM6280/toolchains/gcc/start.S b/common/startup/HPM6280/toolchains/gcc/start.S new file mode 100644 index 00000000..3b56dc0a --- /dev/null +++ b/common/startup/HPM6280/toolchains/gcc/start.S @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + .option pop + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + /* Disable Vector mode */ + csrci CSR_MMISC_CTL, 2 + + /* Initialize trap_entry base */ + la t0, irq_handler_trap + csrw mtvec, t0 + + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .global default_irq_handler + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/common/startup/HPM6280/toolchains/gcc/vectors.S b/common/startup/HPM6280/toolchains/gcc/vectors.S new file mode 100644 index 00000000..dbe155fd --- /dev/null +++ b/common/startup/HPM6280/toolchains/gcc/vectors.S @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2021-2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_HANDLER 18 /* SDFM IRQ handler */ + IRQ_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* UART0 IRQ handler */ + IRQ_HANDLER 30 /* UART1 IRQ handler */ + IRQ_HANDLER 31 /* UART2 IRQ handler */ + IRQ_HANDLER 32 /* UART3 IRQ handler */ + IRQ_HANDLER 33 /* UART4 IRQ handler */ + IRQ_HANDLER 34 /* UART5 IRQ handler */ + IRQ_HANDLER 35 /* UART6 IRQ handler */ + IRQ_HANDLER 36 /* UART7 IRQ handler */ + IRQ_HANDLER 37 /* CAN0 IRQ handler */ + IRQ_HANDLER 38 /* CAN1 IRQ handler */ + IRQ_HANDLER 39 /* CAN2 IRQ handler */ + IRQ_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_HANDLER 41 /* PTPC IRQ handler */ + IRQ_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_HANDLER 44 /* TSNS IRQ handler */ + IRQ_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_HANDLER 69 /* SDP IRQ handler */ + IRQ_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_HANDLER 71 /* XDMA IRQ handler */ + IRQ_HANDLER 72 /* HDMA IRQ handler */ + IRQ_HANDLER 73 /* RNG IRQ handler */ + IRQ_HANDLER 74 /* USB0 IRQ handler */ + IRQ_HANDLER 75 /* PSEC IRQ handler */ + IRQ_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_HANDLER 77 /* PWDG IRQ handler */ + IRQ_HANDLER 78 /* PTMR IRQ handler */ + IRQ_HANDLER 79 /* PUART IRQ handler */ + IRQ_HANDLER 80 /* FUSE IRQ handler */ + IRQ_HANDLER 81 /* SECMON IRQ handler */ + IRQ_HANDLER 82 /* RTC IRQ handler */ + IRQ_HANDLER 83 /* BUTN IRQ handler */ + IRQ_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_HANDLER 85 /* BVIO IRQ handler */ + IRQ_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_HANDLER 93 /* LIN3 IRQ handler */ + \ No newline at end of file diff --git a/common/startup/HPM6280/trap.c b/common/startup/HPM6280/trap.c new file mode 100644 index 00000000..68ce432b --- /dev/null +++ b/common/startup/HPM6280/trap.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2021 - 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "riscv-stackframe.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +static void rt_show_stack_frame(void); + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + rt_kprintf("mdcause: FP disabled exception \r\n"); + break; + case 2: + rt_kprintf("mdcause: ACE disabled exception \r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: Misaligned access \r\n"); + break; + case 5: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + case 6: + rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + rt_kprintf("mdcause: ECC/Parity error\r\n"); + break; + case 2: + rt_kprintf("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + rt_kprintf("mdcause: BUS error\r\n"); + break; + case 4: + rt_kprintf("mdcause: Misaligned access \r\n"); + break; + case 5: + rt_kprintf("mdcause: PMP empty hole access \r\n"); + break; + case 6: + rt_kprintf("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + rt_kprintf("mdcause: PMA NAMO exception \r\n"); + default: + rt_kprintf("mdcause: reserved \r\n"); + break; + } + break; + default: + rt_kprintf("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_show_stack_frame(); + while (1) + { + } +} + +void trap_entry(rt_hw_stack_frame_t *stack_frame); + +void trap_entry(rt_hw_stack_frame_t *stack_frame) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + + s_stack_frame = stack_frame; + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +static void rt_show_stack_frame(void) +{ + rt_kprintf("Stack frame:\r\n----------------------------------------\r\n"); + rt_kprintf("ra : 0x%08x\r\n", s_stack_frame->ra); + rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS)); + rt_kprintf("t0 : 0x%08x\r\n", s_stack_frame->t0); + rt_kprintf("t1 : 0x%08x\r\n", s_stack_frame->t1); + rt_kprintf("t2 : 0x%08x\r\n", s_stack_frame->t2); + rt_kprintf("a0 : 0x%08x\r\n", s_stack_frame->a0); + rt_kprintf("a1 : 0x%08x\r\n", s_stack_frame->a1); + rt_kprintf("a2 : 0x%08x\r\n", s_stack_frame->a2); + rt_kprintf("a3 : 0x%08x\r\n", s_stack_frame->a3); + rt_kprintf("a4 : 0x%08x\r\n", s_stack_frame->a4); + rt_kprintf("a5 : 0x%08x\r\n", s_stack_frame->a5); + rt_kprintf("a6 : 0x%08x\r\n", s_stack_frame->a6); + rt_kprintf("a7 : 0x%08x\r\n", s_stack_frame->a7); + rt_kprintf("t3 : 0x%08x\r\n", s_stack_frame->t3); + rt_kprintf("t4 : 0x%08x\r\n", s_stack_frame->t4); + rt_kprintf("t5 : 0x%08x\r\n", s_stack_frame->t5); + rt_kprintf("t6 : 0x%08x\r\n", s_stack_frame->t6); +} diff --git a/projects/adc_example/.cproject b/projects/adc_example/.cproject index 41c4fd41..f7dcb25b 100644 --- a/projects/adc_example/.cproject +++ b/projects/adc_example/.cproject @@ -109,7 +109,7 @@