diff --git a/.gitignore b/.gitignore index 4cb89876..fba98c21 100644 --- a/.gitignore +++ b/.gitignore @@ -56,3 +56,5 @@ dkms.conf # Scons cache *.dbsqlite + +.vscode \ No newline at end of file diff --git a/ChangeLog.md b/ChangeLog.md index a4d4d6df..e2a8a660 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,5 +1,21 @@ # Change Log +## v1.3.0 +- Integrated hpm_sdk v1.3.0 + - Note: + - the docs, middleware, scripts, samples folder in SDK root directory were removed +- Updated: + - Added SVD support + - Added hardare filter support to `CAN` driver + - Disable PWM invert output by default + - Fixed: + - elf file generated by RT-Thread Studio cannot be recognized by Ozone properly + - online package `i2c tools` cannot work + - ethernet may fail to work when network storm happened + - audio channel control may be unexepcted if i2s overflow/underflow happened + - compiling error if `ADC12` is enabled + - GPIO cannot read back pin level correctly if it is configured as Open-Drain Pull-up mode + ## v1.2.0 - Integrated hpm_sdk v1.2.0 - Note: diff --git a/ChangeLog_zh.md b/ChangeLog_zh.md index ac954f28..69440c3e 100644 --- a/ChangeLog_zh.md +++ b/ChangeLog_zh.md @@ -1,5 +1,21 @@ # 更新 +## v1.3.0 +- 整合了hpm_sdk v1.3.0 + - 注： + - SDK根目录下的docs,middleware,samples, scripts等目录被移除 +- 更新 + - 增加了SVD文件的支持 + - CAN: 增加了硬件过滤器支持 + - 默认禁用了PWM输出反向 +- 修复： + - RT-Thread Studio生成的elf文件无法被`Ozone`正确的识别 + - 在线包`i2c tools`不工作 + - 以太网在网络风暴产生后工作不正常 + - 音频声道控制在产生上溢/下溢后产生异常 + - 当开启`ADC12`后编译失败 + - GPIO在配置为开漏极并上拉模式后无法正确的读出引脚的电平 + ## v1.2.0 - 整合了hpm_sdk v1.2.0 - 注： diff --git a/HPMicro-HPM6300EVK.yaml b/HPMicro-HPM6300EVK.yaml index 2db634ed..4fa1dcd1 100644 --- a/HPMicro-HPM6300EVK.yaml +++ b/HPMicro-HPM6300EVK.yaml @@ -49,7 +49,7 @@ features_zh: - '调试接口: 板载FT2232' pkg_type: Board_Support_Packages pkg_vendor: HPMicro -pkg_version: 1.2.0 +pkg_version: 1.3.0 template_projects: - project_name: blink_led @@ -92,7 +92,7 @@ template_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] @@ -145,7 +145,7 @@ example_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] @@ -190,7 +190,7 @@ example_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] @@ -235,7 +235,7 @@ example_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] @@ -280,7 +280,7 @@ example_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] @@ -325,7 +325,7 @@ example_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] @@ -370,7 +370,7 @@ example_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] @@ -415,7 +415,7 @@ example_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] @@ -461,7 +461,7 @@ example_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] @@ -507,7 +507,7 @@ example_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] @@ -553,7 +553,7 @@ example_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] @@ -600,7 +600,7 @@ example_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] @@ -646,7 +646,7 @@ example_projects: - package_name: OpenOCD-HPMicro package_type: Debugger_Support_Packages package_vendor: 'HPMicro' - package_version: 0.3.0 + package_version: 0.4.0 source_path_offset: '' target_path_offset: '' files_and_folders: [] diff --git a/board/board.c b/board/board.c index f176e26b..68d4be2a 100644 --- a/board/board.c +++ b/board/board.c @@ -415,31 +415,43 @@ void board_init_clock(void) clock_set_source_divider(clock_aud1, clk_src_pll2_clk0, 46); /* config clock_aud1 for 44100*n sample rate */ } -uint32_t board_init_adc16_clock(ADC16_Type *ptr) +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) { uint32_t freq = 0; - switch ((uint32_t) ptr) { - case HPM_ADC0_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@160MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk1 divided by 2 (@166MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk1, 2U); + } + freq = clock_get_frequency(clock_adc0); - break; - case HPM_ADC1_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@160MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@166MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll0_clk1, 2U); + } + freq = clock_get_frequency(clock_adc1); - break; - case HPM_ADC2_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@160MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@166MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll0_clk1, 2U); + } + freq = clock_get_frequency(clock_adc2); - break; - default: - /* Invalid ADC instance */ - break; } return freq; @@ -468,10 +480,10 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) if (ptr == HPM_DAC) { if (clk_src_ahb == true) { /* Configure the DAC clock to 160MHz */ - clock_set_dac_source(clock_dac0, clk_dac_src_ahb); + clock_set_dac_source(clock_dac0, clk_dac_src_ahb0); } else { /* Configure the DAC clock to 166MHz */ - clock_set_dac_source(clock_dac0, clk_dac_src_ana); + clock_set_dac_source(clock_dac0, clk_dac_src_ana3); clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2); } diff --git a/board/board.h b/board/board.h index 7410b1b2..dfb8a17a 100644 --- a/board/board.h +++ b/board/board.h @@ -352,7 +352,7 @@ void board_init_clock(void); uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc16_clock(ADC16_Type *ptr); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); diff --git a/board/rtt_board.c b/board/rtt_board.c index 0e44227c..e27391bc 100644 --- a/board/rtt_board.c +++ b/board/rtt_board.c @@ -15,7 +15,7 @@ #include "hpm_sysctl_drv.h" #include #include -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" void os_tick_config(void); @@ -27,7 +27,7 @@ void rtt_board_init(void) board_init_console(); board_init_pmp(); - dma_manager_init(); + dma_mgr_init(); /* initialize memory system */ rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); diff --git a/common/.gitattributes b/common/.gitattributes new file mode 100644 index 00000000..d1564d72 --- /dev/null +++ b/common/.gitattributes @@ -0,0 +1,2 @@ +.gitattributes export-ignore +.gitignore export-ignore \ No newline at end of file diff --git a/common/.gitignore b/common/.gitignore new file mode 100644 index 00000000..2287b288 --- /dev/null +++ b/common/.gitignore @@ -0,0 +1,67 @@ +# Prerequisites +*.d + +# Object files +*.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.conf + +# Paython cache +*.pyc + +# Scons cache +*.dbsqlite + +# hpm_sdk docs +libraries/hpm_sdk/**/doc +libraries/hpm_sdk/**/docs +libraries/hpm_sdk/**/test +*.yaml + +#dir +.vscode diff --git a/common/libraries/Kconfig b/common/libraries/Kconfig index faf5bc5b..54164220 100644 --- a/common/libraries/Kconfig +++ b/common/libraries/Kconfig @@ -1,4 +1,4 @@ -config SOC_HPM6000_SERIES +config SOC_SERIES_HPM5000 bool select ARCH_RISCV32 select ARCH_RISCV_DPU diff --git a/common/libraries/drivers/SConscript b/common/libraries/drivers/SConscript index 36fa0242..992ef4f5 100644 --- a/common/libraries/drivers/SConscript +++ b/common/libraries/drivers/SConscript @@ -19,6 +19,9 @@ if GetDepend('BSP_USING_RTC'): if GetDepend('BSP_USING_WDG'): src += ['drv_wdt.c'] +if GetDepend('BSP_USING_EWDG'): + src += ['drv_ewdt.c'] + if GetDepend('BSP_USING_ETH'): src += ['drv_enet.c'] diff --git a/common/libraries/drivers/drv_adc.c b/common/libraries/drivers/drv_adc.c index 48e3ab56..c22f0fa9 100644 --- a/common/libraries/drivers/drv_adc.c +++ b/common/libraries/drivers/drv_adc.c @@ -112,11 +112,11 @@ static uint32_t hpm_adc_init_clock(struct rt_adc_device *device) #if defined(ADC12_SOC_MAX_CH_NUM) if (hpm_adc->is_adc12) { - clock_freq = board_init_adc12_clock((ADC12_Type*)hpm_adc->adc_base); + clock_freq = board_init_adc12_clock((ADC12_Type*)hpm_adc->adc_base,true); } else #endif { - clock_freq = board_init_adc16_clock((ADC16_Type*)hpm_adc->adc_base); + clock_freq = board_init_adc16_clock((ADC16_Type*)hpm_adc->adc_base,true); } return clock_freq; } @@ -153,6 +153,10 @@ static rt_err_t init_adc_config(hpm_rtt_adc *adc) if (ret != status_success) { return RT_ERROR; } +#endif +#if defined(ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT) && ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT + /* enable oneshot mode */ + adc16_enable_oneshot_mode((ADC16_Type *)adc->adc_base); #endif } return RT_EOK; @@ -167,7 +171,7 @@ static rt_err_t init_channel_config(hpm_rtt_adc *adc, uint16_t channel) adc12_channel_config_t ch_cfg; adc12_get_channel_default_config(&ch_cfg); - ch_cfg.ch = adc->channel; + ch_cfg.ch = channel; ch_cfg.diff_sel = adc12_sample_signal_single_ended; ch_cfg.sample_cycle = 20; diff --git a/common/libraries/drivers/drv_can.c b/common/libraries/drivers/drv_can.c index b91401e2..9d1ecc21 100644 --- a/common/libraries/drivers/drv_can.c +++ b/common/libraries/drivers/drv_can.c @@ -411,6 +411,12 @@ static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg) drv_can->filter_num = 0; } err = hpm_can_configure(can, &drv_can->can_dev.config); +#ifdef RT_CAN_USING_HDR + if (filter == RT_NULL) { + /*if use RT_CAN_USING_HDR, but if want to receive everything without filtering, use default filter, need to return NO-RT-OK status*/ + err = -RT_ETRAP; + } +#endif } break; case RT_CAN_CMD_SET_MODE: @@ -505,6 +511,7 @@ static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg) rt_memcpy(arg, &drv_can->can_dev.status, sizeof(drv_can->can_dev.status)); break; } + return err; } static int hpm_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) @@ -633,6 +640,11 @@ static int hpm_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t box for(uint32_t i = 0; i < msg_len; i++) { can_msg->data[i] = rx_buf.data[i]; } +#ifdef RT_CAN_USING_HDR + /* Hardware filter messages are valid */ + can_msg->hdr_index = boxno; + can->hdr[can_msg->hdr_index].connected = 1; +#endif } else { return -RT_EEMPTY; @@ -686,7 +698,9 @@ int rt_hw_can_init(void) config.privmode = RT_CAN_MODE_NOPRIV; config.sndboxnumber = CAN_SENDBOX_NUM; config.ticks = 50; - +#ifdef RT_CAN_USING_HDR + config.maxhdr = 16; +#endif for (uint32_t i = 0; i < ARRAY_SIZE(hpm_cans); i++) { hpm_cans[i]->can_dev.config = config; diff --git a/common/libraries/drivers/drv_dao.c b/common/libraries/drivers/drv_dao.c index 786f2e79..a0dfb114 100644 --- a/common/libraries/drivers/drv_dao.c +++ b/common/libraries/drivers/drv_dao.c @@ -18,11 +18,15 @@ #include "hpm_dao_drv.h" #include "board.h" #include "drv_dao.h" +#ifdef CONFIG_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else #include "hpm_dma_drv.h" +#endif #include "hpm_dmamux_drv.h" #include "hpm_l1c_drv.h" #include "hpm_clock_drv.h" -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" /* DAO connect to I2S1 TX*/ #define DAO_DMA_REQ HPM_DMA_SRC_I2S1_TX @@ -36,13 +40,11 @@ struct hpm_dao }; struct hpm_dao hpm_dao_dev = { 0 }; -static hpm_dma_resource_t dma_resource = { 0 }; +static dma_resource_t dma_resource = { 0 }; -void dao_dma_callback(DMA_Type *ptr, uint32_t channel, void *user_data, uint32_t int_stat) +void dao_dma_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) { - if (int_stat == DMA_CHANNEL_STATUS_TC) { - rt_audio_tx_complete(&hpm_dao_dev.audio); - } + rt_audio_tx_complete(&hpm_dao_dev.audio); } static rt_err_t hpm_dao_getcaps(struct rt_audio_device* audio, struct rt_audio_caps* caps) @@ -92,6 +94,11 @@ static rt_err_t hpm_dao_getcaps(struct rt_audio_device* audio, struct rt_audio_c return result; } +static bool i2s_is_enabled(I2S_Type *ptr) +{ + return ((ptr->CTRL & I2S_CTRL_I2S_EN_MASK) != 0); +} + static rt_err_t hpm_dao_set_samplerate(uint32_t samplerate) { uint32_t mclk_hz; @@ -100,11 +107,17 @@ static rt_err_t hpm_dao_set_samplerate(uint32_t samplerate) mclk_hz = clock_get_frequency(clock_i2s1); i2s_get_default_transfer_config_for_dao(&transfer); transfer.sample_rate = samplerate; + bool is_enabled = i2s_is_enabled(DAO_I2S); + dma_abort_channel(dma_resource.base, dma_resource.channel); if (status_success != i2s_config_tx(DAO_I2S, mclk_hz, &transfer)) { LOG_E("dao_i2s configure transfer failed\n"); return -RT_ERROR; } + if (is_enabled) + { + i2s_enable(DAO_I2S); + } return RT_EOK; } @@ -185,12 +198,13 @@ static rt_err_t hpm_dao_start(struct rt_audio_device* audio, int stream) { RT_ASSERT(audio != RT_NULL); - dao_start(HPM_DAO); + i2s_reset_tx_rx(DAO_I2S); + dao_software_reset(HPM_DAO); - if (dma_manager_request_resource(&dma_resource) == status_success) { + if (dma_mgr_request_resource(&dma_resource) == status_success) { uint8_t dmamux_ch; - dma_manager_install_interrupt_callback(&dma_resource, dao_dma_callback, NULL); - dma_manager_enable_dma_interrupt(&dma_resource, 1); + dma_mgr_install_chn_tc_callback(&dma_resource, dao_dma_tc_callback, NULL); + dma_mgr_enable_dma_irq_with_priority(&dma_resource, 1); dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource.base, dma_resource.channel); dmamux_config(HPM_DMAMUX, dmamux_ch, DAO_DMA_REQ, true); } else { @@ -200,6 +214,9 @@ static rt_err_t hpm_dao_start(struct rt_audio_device* audio, int stream) rt_audio_tx_complete(audio); + i2s_start(DAO_I2S); + dao_start(HPM_DAO); + return RT_EOK; } @@ -208,8 +225,9 @@ static rt_err_t hpm_dao_stop(struct rt_audio_device* audio, int stream) RT_ASSERT(audio != RT_NULL); dao_stop(HPM_DAO); + i2s_stop(DAO_I2S); - dma_manager_release_resource(&dma_resource); + dma_mgr_release_resource(&dma_resource); return RT_EOK; } diff --git a/common/libraries/drivers/drv_enet.c b/common/libraries/drivers/drv_enet.c index 538c5662..1db87187 100644 --- a/common/libraries/drivers/drv_enet.c +++ b/common/libraries/drivers/drv_enet.c @@ -174,7 +174,6 @@ static rt_err_t hpm_enet_init(enet_device *init) { /* Initialize reference clock */ board_init_enet_rmii_reference_clock(init->instance, init->int_refclk); - enet_rmii_enable_clock(init->instance, init->int_refclk); } #if ENET_SOC_RGMII_EN @@ -406,54 +405,57 @@ static struct pbuf *rt_hpm_eth_rx(rt_device_t dev) { /* allocate a pbuf chain of pbufs from the Lwip buffer pool */ p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - } - if (p != NULL) - { - dma_rx_desc = frame.rx_desc; - buffer_offset = 0; - for (q = p; q != NULL; q = q->next) + if (p != NULL) { - bytes_left_to_copy = q->len; - payload_offset = 0; - - /* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/ - while ((bytes_left_to_copy + buffer_offset) > rx_buff_size) + dma_rx_desc = frame.rx_desc; + buffer_offset = 0; + for (q = p; q != NULL; q = q->next) { - /* Copy data to pbuf */ - SMEMCPY((uint8_t *)((uint8_t *)q->payload + payload_offset), (uint8_t *)((uint8_t *)buffer + buffer_offset), (rx_buff_size - buffer_offset)); + bytes_left_to_copy = q->len; + payload_offset = 0; - /* Point to next descriptor */ - dma_rx_desc = (enet_rx_desc_t *)(dma_rx_desc->rdes3_bm.next_desc); - buffer = (uint8_t *)(dma_rx_desc->rdes2_bm.buffer1); + /* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/ + while ((bytes_left_to_copy + buffer_offset) > rx_buff_size) + { + /* Copy data to pbuf */ + SMEMCPY((uint8_t *)((uint8_t *)q->payload + payload_offset), (uint8_t *)((uint8_t *)buffer + buffer_offset), (rx_buff_size - buffer_offset)); + + /* Point to next descriptor */ + dma_rx_desc = (enet_rx_desc_t *)(dma_rx_desc->rdes3_bm.next_desc); + buffer = (uint8_t *)(dma_rx_desc->rdes2_bm.buffer1); - bytes_left_to_copy = bytes_left_to_copy - (rx_buff_size - buffer_offset); - payload_offset = payload_offset + (rx_buff_size - buffer_offset); - buffer_offset = 0; + bytes_left_to_copy = bytes_left_to_copy - (rx_buff_size - buffer_offset); + payload_offset = payload_offset + (rx_buff_size - buffer_offset); + buffer_offset = 0; + } + /* Copy remaining data in pbuf */ + q->payload = (void *)sys_address_to_core_local_mem(0, (uint32_t)buffer); + buffer_offset = buffer_offset + bytes_left_to_copy; } - /* Copy remaining data in pbuf */ - q->payload = (void *)sys_address_to_core_local_mem(0, (uint32_t)buffer); - buffer_offset = buffer_offset + bytes_left_to_copy; } - } - else - { - return NULL; - } - /* Release descriptors to DMA */ - /* Point to first descriptor */ - dma_rx_desc = frame.rx_desc; + /* Release descriptors to DMA */ + /* Point to first descriptor */ + dma_rx_desc = frame.rx_desc; - /* Set Own bit in Rx descriptors: gives the buffers back to DMA */ - for (i = 0; i < enet_dev->desc.rx_frame_info.seg_count; i++) - { - dma_rx_desc->rdes0_bm.own = 1; - dma_rx_desc = (enet_rx_desc_t*)(dma_rx_desc->rdes3_bm.next_desc); + /* Set Own bit in Rx descriptors: gives the buffers back to DMA */ + for (i = 0; i < enet_dev->desc.rx_frame_info.seg_count; i++) + { + dma_rx_desc->rdes0_bm.own = 1; + dma_rx_desc = (enet_rx_desc_t*)(dma_rx_desc->rdes3_bm.next_desc); + } + + /* Clear Segment_Count */ + enet_dev->desc.rx_frame_info.seg_count = 0; } - /* Clear Segment_Count */ - enet_dev->desc.rx_frame_info.seg_count = 0; + /* Resume Rx Process */ + if (ENET_DMA_STATUS_RU_GET(enet_dev->instance->DMA_STATUS)) + { + enet_dev->instance->DMA_STATUS = ENET_DMA_STATUS_RU_MASK; + enet_dev->instance->DMA_RX_POLL_DEMAND = 1; + } return p; } diff --git a/common/libraries/drivers/drv_ewdt.c b/common/libraries/drivers/drv_ewdt.c new file mode 100644 index 00000000..f39bc8c9 --- /dev/null +++ b/common/libraries/drivers/drv_ewdt.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#include +#include "board.h" +#include "drv_ewdt.h" +#include "hpm_ewdg_drv.h" +#include "hpm_sysctl_drv.h" + + +#ifdef BSP_USING_EWDG + +#define EWDG_CNT_CLK_FREQ 32768UL + + +typedef struct hpm_wdog +{ + EWDG_Type *wdog_base; + char *device_name; + clock_name_t clock_name; + uint32_t irq_num; + rt_watchdog_t *wdog; +}hpm_wdog_t; + +static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt); +static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag); +static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt); +static rt_err_t hpm_wdog_refresh(rt_watchdog_t *wdt); +static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args); + +static void hpm_wdog_isr(rt_watchdog_t *wdt); + +#if defined(BSP_USING_EWDG0) +rt_watchdog_t wdog0; +void wdog0_isr(void) +{ + hpm_wdog_isr(&wdog0); +} +SDK_DECLARE_EXT_ISR_M(IRQn_WDOG0, wdog0_isr) +#endif + +#if defined(BSP_USING_EWDG1) +rt_watchdog_t wdog1; +void wdog1_isr(void) +{ + hpm_wdog_isr(&wdog1); +} +SDK_DECLARE_EXT_ISR_M(IRQn_WDOG1, wdog1_isr) +#endif + +#if defined(BSP_USING_EWDG2) +rt_watchdog_t wdog2; +void wdog2_isr(void) +{ + hpm_wdog_isr(&wdog2); +} +SDK_DECLARE_EXT_ISR_M(IRQn_WDOG2, wdog2_isr) +#endif + +#if defined(BSP_USING_EWDG3) +rt_watchdog_t wdog3; +void wdog3_isr(void) +{ + hpm_wdog_isr(&wdog3); +} +SDK_DECLARE_EXT_ISR_M(IRQn_WDOG3, wdog3_isr) +#endif + +static hpm_wdog_t wdogs[] = { +#ifdef BSP_USING_EWDG0 + { + .wdog_base = HPM_WDG0, + .device_name = "wdt0", + .clock_name = clock_watchdog0, + .irq_num = IRQn_WDG0, + .wdog = &wdog0, + }, +#endif + +#ifdef BSP_USING_EWDG1 + { + .wdog_base = HPM_WDG1, + .device_name = "wdt1", + .clock_name = clock_watchdog1, + .irq_num = IRQn_WDG1, + .wdog = &wdog1, + }, +#endif + +#ifdef BSP_USING_EWDG2 + { + .wdog_base = HPM_WDG2, + .device_name = "wdt2", + .clock_name = clock_watchdog2, + .irq_num = IRQn_WDG2, + .wdog = &wdog2, + }, +#endif + +#ifdef BSP_USING_EWDG3 + { + .wdog_name = HPM_WDG3, + .device_name = "wdt3", + .clock_name = clock_watchdog3, + .irq_num = IRQn_WDG3, + .wdog = &wdog3, + }, +#endif +}; + +static struct rt_watchdog_ops hpm_wdog_ops = { + .init = hpm_wdog_init, + .control = hpm_wdog_control, +}; + +static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + EWDG_Type *base = hpm_wdog->wdog_base; + + ewdg_config_t config; + + printf("Init Watchdog\n"); + ewdg_get_default_config(base, &config); + /* Enable EWDG */ + config.enable_watchdog = true; + config.ctrl_config.use_lowlevel_timeout = false; + /* Enable EWDG Timeout Reset */ + config.int_rst_config.enable_timeout_reset = true; + /* Set EWDG Count clock source to OSC32 */ + config.ctrl_config.cnt_clk_sel = ewdg_cnt_clk_src_ext_osc_clk; + + /* Set the EWDG reset timeout to 101ms */ + config.cnt_src_freq = EWDG_CNT_CLK_FREQ; + config.ctrl_config.timeout_reset_us = 101UL * 1000UL; + + ewdg_init(base, &config); + + return RT_EOK; +} + +static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + EWDG_Type *base = hpm_wdog->wdog_base; + + rt_enter_critical(); + ewdg_enable(base); + rt_exit_critical(); +} + +static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + EWDG_Type *base = hpm_wdog->wdog_base; + + rt_enter_critical(); + ewdg_disable(base); + rt_exit_critical(); + + return RT_EOK; +} + +static rt_err_t hpm_wdog_refresh(rt_watchdog_t *wdt) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + EWDG_Type *base = hpm_wdog->wdog_base; + + rt_enter_critical(); + ewdg_refresh(base); + rt_exit_critical(); + + return RT_EOK; +} + +static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) +{ + rt_err_t ret = RT_EOK; + + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + EWDG_Type *base = hpm_wdog->wdog_base; + + ewdg_config_t config; + + uint32_t temp; + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + RT_ASSERT(*(uint32_t *)args != 0); + temp = *(uint32_t *)args; + temp *= 1000000U; /* Convert to microseconds */ + + ewdg_get_default_config(base, &config); + config.enable_watchdog = true; + config.int_rst_config.enable_timeout_reset = true; + config.ctrl_config.use_lowlevel_timeout = false; + uint32_t ewdg_src_clk_freq = EWDG_CNT_CLK_FREQ; + config.ctrl_config.cnt_clk_sel = ewdg_cnt_clk_src_ext_osc_clk; + + /* Set the EWDG reset timeout to 1 second */ + config.cnt_src_freq = ewdg_src_clk_freq; + config.ctrl_config.timeout_reset_us = temp; + + /* Initialize the EWDG */ + hpm_stat_t status = ewdg_init(base, &config); + if (status != status_success) { + printf(" EWDG initialization failed, error_code=%d\n", status); + } + /* delay 1ms to ensure above configure take effective*/ + rt_thread_mdelay(1); + break; + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + hpm_wdog_refresh(wdt); + break; + case RT_DEVICE_CTRL_WDT_START: + hpm_wdog_open(wdt, *(uint16_t*)args); + break; + case RT_DEVICE_CTRL_WDT_STOP: + hpm_wdog_close(wdt); + break; + default: + ret = RT_EINVAL; + break; + } + + return RT_EOK; +} + +void hpm_wdog_isr(rt_watchdog_t *wdt) +{ + hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; + EWDG_Type *base = hpm_wdog->wdog_base; + + uint32_t ewdg_stat = ewdg_get_status_flags(base); + + if ((ewdg_stat & EWDG_INT_TIMEOUT) != 0) { + ewdg_refresh(base); + } + ewdg_clear_status_flags(base, ewdg_stat); +} + +int rt_hw_wdt_init(void) +{ + rt_err_t err = RT_EOK; + +#if defined(BSP_USING_EWDG) + for (uint32_t i = 0; i < sizeof(wdogs) / sizeof(wdogs[0]); i++) + { + wdogs[i].wdog->ops = &hpm_wdog_ops; + clock_add_to_group(wdogs[i].clock_name, 0); + err = rt_hw_watchdog_register(wdogs[i].wdog, wdogs[i].device_name, RT_DEVICE_FLAG_RDWR, (void *)&wdogs[i]); + if (err != RT_EOK) + { + LOG_E("rt device %s failed, status=%d\n", wdogs[i].device_name, err); + } + } +#endif + return err; +} + +INIT_BOARD_EXPORT(rt_hw_wdt_init); +#endif /* RT_USING_WDT */ \ No newline at end of file diff --git a/common/libraries/drivers/drv_ewdt.h b/common/libraries/drivers/drv_ewdt.h new file mode 100644 index 00000000..4c69255a --- /dev/null +++ b/common/libraries/drivers/drv_ewdt.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DRV_WDT_H +#define DRV_WDT_H + + +int rt_hw_wdt_init(void); + +#endif \ No newline at end of file diff --git a/common/libraries/drivers/drv_gpio.c b/common/libraries/drivers/drv_gpio.c index 4a002dde..643fe819 100644 --- a/common/libraries/drivers/drv_gpio.c +++ b/common/libraries/drivers/drv_gpio.c @@ -8,6 +8,7 @@ * 2022-01-11 HPMicro First version * 2022-07-28 HPMicro Fixed compiling warnings * 2023-05-08 HPMicro Adapt RT-Thread V5.0.0 + * 2023-08-15 HPMicro Enable pad loopback feature */ #include @@ -22,6 +23,10 @@ #include "hpm_clock_drv.h" #include "hpm_soc_feature.h" +#ifndef IOC_SOC_PAD_MAX +#define IOC_SOC_PAD_MAX (56U) +#endif + typedef struct { uint32_t gpio_idx; @@ -38,7 +43,7 @@ static const gpio_irq_map_t hpm_gpio_irq_map[] = { #ifdef IRQn_GPIO0_C { GPIO_IE_GPIOC, IRQn_GPIO0_C }, #endif -#ifdef GPIO_IE_GPIOD +#ifdef IRQn_GPIO0_D { GPIO_IE_GPIOD, IRQn_GPIO0_D }, #endif #ifdef IRQn_GPIO0_E @@ -181,7 +186,9 @@ static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) HPM_PIOC->PAD[pin].FUNC_CTL = 3; break; case GPIO_DI_GPIOZ : +#ifdef HPM_BIOC HPM_BIOC->PAD[pin].FUNC_CTL = 3; +#endif break; default : break; @@ -213,6 +220,7 @@ static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) /* Invalid mode */ break; } + HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; } static rt_int8_t hpm_pin_read(rt_device_t dev, rt_base_t pin) diff --git a/common/libraries/drivers/drv_hwtimer.c b/common/libraries/drivers/drv_hwtimer.c index 2ef9c18e..636b5add 100644 --- a/common/libraries/drivers/drv_hwtimer.c +++ b/common/libraries/drivers/drv_hwtimer.c @@ -168,10 +168,10 @@ SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR7, gptmr7_isr); static void hpm_hwtmr_isr(hpm_gptimer_t *timer) { uint32_t hwtmr_stat = gptmr_get_status(timer->base); - if ((hwtmr_stat & GPTMR_CH_CMP_STAT_MASK(0, 0)) != 0U) + if ((hwtmr_stat & GPTMR_CH_RLD_STAT_MASK(timer->channel)) != 0U) { rt_device_hwtimer_isr(&timer->timer); - gptmr_clear_status(timer->base, GPTMR_CH_CMP_STAT_MASK(0, 0)); + gptmr_clear_status(timer->base, GPTMR_CH_RLD_STAT_MASK(timer->channel)); } } diff --git a/common/libraries/drivers/drv_i2c.c b/common/libraries/drivers/drv_i2c.c index b983509d..99d05afc 100644 --- a/common/libraries/drivers/drv_i2c.c +++ b/common/libraries/drivers/drv_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 HPMicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -15,6 +15,8 @@ #ifdef RT_USING_I2C +#define HPM_RTT_DRV_RETRY_TIMEOUT (1000000) + struct hpm_i2c { struct rt_i2c_bus_device bus; @@ -65,6 +67,48 @@ struct rt_i2c_bus_device_ops hpm_i2c_ops = RT_NULL }; +static hpm_stat_t hpm_i2c_probe(I2C_Type *ptr, uint16_t addr) +{ + hpm_stat_t stat = status_success; + uint32_t retry; + + /* W1C, clear CMPL bit to avoid blocking the transmission */ + ptr->STATUS = I2C_STATUS_CMPL_MASK; + + ptr->CMD = I2C_CMD_CLEAR_FIFO; + ptr->ADDR = I2C_ADDR_ADDR_SET(addr); + ptr->CTRL = I2C_CTRL_PHASE_START_MASK | I2C_CTRL_PHASE_STOP_MASK | I2C_CTRL_PHASE_ADDR_MASK + | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE); + + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; + + retry = 0; + while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) + { + if (retry > HPM_RTT_DRV_RETRY_TIMEOUT) + { + break; + } + retry++; + } + if (retry > HPM_RTT_DRV_RETRY_TIMEOUT) + { + return status_timeout; + } + + /* Check whether ACK was received*/ + if ((ptr->STATUS & I2C_STATUS_ACK_MASK) != 0) + { + stat = status_success; + } + else + { + stat = status_i2c_no_ack; + } + + return stat; +} + static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) { RT_ASSERT(bus != RT_NULL); @@ -96,7 +140,14 @@ static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct } else { - i2c_stat = i2c_master_write(i2c_info->base, msg->addr, msg->buf, msg->len); + if (msg->len > 0) + { + i2c_stat = i2c_master_write(i2c_info->base, msg->addr, msg->buf, msg->len); + } + else + { + i2c_stat = hpm_i2c_probe(i2c_info->base, msg->addr); + } } if (i2c_stat != status_success) diff --git a/common/libraries/drivers/drv_i2s.c b/common/libraries/drivers/drv_i2s.c index ce2088f2..b63f1b6b 100644 --- a/common/libraries/drivers/drv_i2s.c +++ b/common/libraries/drivers/drv_i2s.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 HPMicro + * Copyright (c) 2022-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -15,23 +15,36 @@ #ifdef BSP_USING_I2S #include "hpm_i2s_drv.h" #include "board.h" +#ifdef CONFIG_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else #include "hpm_dma_drv.h" +#endif #include "hpm_dmamux_drv.h" #include "hpm_l1c_drv.h" #include "hpm_clock_drv.h" -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" #include "drv_i2s.h" #include "drivers/audio.h" static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* writeBuf, void* readBuf, rt_size_t size); +/** + * I2S state + */ +typedef enum { + hpm_i2s_state_stop, + hpm_i2s_state_read, + hpm_i2s_state_write, +} hpm_i2s_state_t; + struct hpm_i2s { struct rt_audio_device audio; struct rt_audio_configure audio_config; - hpm_dma_resource_t rx_dma_resource; - hpm_dma_resource_t tx_dma_resource; + dma_resource_t rx_dma_resource; + dma_resource_t tx_dma_resource; char *dev_name; I2S_Type *base; clock_name_t clk_name; @@ -40,6 +53,7 @@ struct hpm_i2s uint8_t tx_dma_req; rt_uint8_t* tx_buff; rt_uint8_t* rx_buff; + hpm_i2s_state_t i2s_state; }; #if defined(BSP_USING_I2S0) @@ -61,7 +75,7 @@ ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s3_rx_buff[I2S_FIFO_SIZE]; static struct hpm_i2s hpm_i2s_set[] = { -#if defined(BSP_USING_I2S0) +#if defined(BSP_USING_I2S0) && defined(HPM_I2S0) { .dev_name = "i2s0", .base = HPM_I2S0, @@ -72,7 +86,7 @@ static struct hpm_i2s hpm_i2s_set[] = .rx_buff = i2s0_rx_buff, }, #endif -#if defined(BSP_USING_I2S1) +#if defined(BSP_USING_I2S1) && defined(HPM_I2S1) { .dev_name = "i2s1", .base = HPM_I2S1; @@ -83,7 +97,7 @@ static struct hpm_i2s hpm_i2s_set[] = .rx_buff = i2s1_rx_buff, }, #endif -#if defined(BSP_USING_I2S2) +#if defined(BSP_USING_I2S2) && defined(HPM_I2S2) { .dev_name = "i2s2", .base = HPM_I2S2, @@ -94,7 +108,7 @@ static struct hpm_i2s hpm_i2s_set[] = .rx_buff = i2s2_rx_buff, }, #endif -#if defined(BSP_USING_I2S3) +#if defined(BSP_USING_I2S3) && defined(HPM_I2S3) { .dev_name = "i2s3", .base = HPM_I2S3, @@ -108,22 +122,18 @@ static struct hpm_i2s hpm_i2s_set[] = }; /* I2S TX DMA callback function: trigger next transfer */ -void i2s_tx_dma_callback(DMA_Type *ptr, uint32_t channel, void *user_data, uint32_t int_stat) +void i2s_tx_dma_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) { - if (int_stat == DMA_CHANNEL_STATUS_TC) { - struct hpm_i2s* hpm_audio = (struct hpm_i2s*) user_data; - rt_audio_tx_complete(&hpm_audio->audio); - } + struct hpm_i2s* hpm_audio = (struct hpm_i2s*) user_data; + rt_audio_tx_complete(&hpm_audio->audio); } /* I2S RX DMA callback function: write data into record->pipe and trigger next transfer */ -void i2s_rx_dma_callback(DMA_Type *ptr, uint32_t channel, void *user_data, uint32_t int_stat) +void i2s_rx_dma_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) { - if (int_stat == DMA_CHANNEL_STATUS_TC) { - struct hpm_i2s* hpm_audio = (struct hpm_i2s*) user_data; - rt_audio_rx_done(&hpm_audio->audio, hpm_audio->rx_buff, I2S_FIFO_SIZE); - hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE); - } + struct hpm_i2s* hpm_audio = (struct hpm_i2s*) user_data; + rt_audio_rx_done(&hpm_audio->audio, hpm_audio->rx_buff, I2S_FIFO_SIZE); + hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE); } @@ -145,7 +155,10 @@ static rt_err_t hpm_i2s_init(struct rt_audio_device* audio) i2s_get_default_config(hpm_audio->base, &i2s_config); i2s_config.enable_mclk_out = true; - i2s_config.frame_start_at_rising_edge = true; //左对齐与右对齐方式， 对应上升沿 +#if BOARD_USE_AUDIO_CODEC_WM8960 + i2s_config.invert_fclk_out = true; + i2s_config.invert_fclk_in = true; +#endif i2s_init(hpm_audio->base, &i2s_config); mclk_hz = clock_get_frequency(hpm_audio->clk_name); @@ -167,6 +180,8 @@ static rt_err_t hpm_i2s_init(struct rt_audio_device* audio) return -RT_ERROR; } + hpm_audio->i2s_state = hpm_i2s_state_stop; + return RT_EOK; } @@ -277,9 +292,13 @@ static rt_err_t hpm_i2s_getcaps(struct rt_audio_device* audio, struct rt_audio_c return result; } -static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio_caps* caps) +static bool i2s_is_enabled(I2S_Type *ptr) { + return ((ptr->CTRL & I2S_CTRL_I2S_EN_MASK) != 0); +} +static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio_caps* caps) +{ rt_err_t result = RT_EOK; RT_ASSERT(audio != RT_NULL); struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; @@ -393,10 +412,30 @@ static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio assert(hpm_audio->audio_config.samplebits == 16 || hpm_audio->audio_config.samplebits == 32); hpm_audio->transfer.audio_depth = hpm_audio->audio_config.samplebits; + /* Stop I2S transfer if the I2S needs to be re-configured */ + bool is_enabled = i2s_is_enabled(hpm_audio->base); + if (is_enabled) + { + if (hpm_audio->i2s_state == hpm_i2s_state_read) + { + dma_abort_channel(hpm_audio->rx_dma_resource.base, hpm_audio->rx_dma_resource.channel); + } + if (hpm_audio->i2s_state == hpm_i2s_state_write) + { + dma_abort_channel(hpm_audio->tx_dma_resource.base, hpm_audio->tx_dma_resource.channel); + } + } if (status_success != i2s_config_transfer(hpm_audio->base, clock_get_frequency(hpm_audio->clk_name), &hpm_audio->transfer)) { LOG_E("%s configure transfer failed.\n", hpm_audio->dev_name); + return -RT_ERROR; + } + /* Restore I2S to previous state */ + if (is_enabled) + { + i2s_enable(hpm_audio->base); } + return result; } @@ -408,24 +447,27 @@ static rt_err_t hpm_i2s_start(struct rt_audio_device* audio, int stream) /* 申请DMA resource用于I2S transfer */ if (stream == AUDIO_STREAM_REPLAY) { - hpm_dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; - if (dma_manager_request_resource(dma_resource) == status_success) { + dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; + if (dma_mgr_request_resource(dma_resource) == status_success) { uint8_t dmamux_ch; - dma_manager_install_interrupt_callback(dma_resource, i2s_tx_dma_callback, hpm_audio); - dma_manager_enable_dma_interrupt(dma_resource, 1); + dma_mgr_install_chn_tc_callback(dma_resource, i2s_tx_dma_tc_callback, hpm_audio); + dma_mgr_enable_dma_irq_with_priority(dma_resource, 1); dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource->base, dma_resource->channel); dmamux_config(HPM_DMAMUX, dmamux_ch, hpm_audio->tx_dma_req, true); } else { LOG_E("no dma resource available for I2S TX transfer.\n"); return -RT_ERROR; } + i2s_disable(hpm_audio->base); + i2s_reset_tx_rx(hpm_audio->base); rt_audio_tx_complete(audio); + i2s_enable(hpm_audio->base); } else if (stream == AUDIO_STREAM_RECORD) { - hpm_dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; - if (dma_manager_request_resource(dma_resource) == status_success) { + dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; + if (dma_mgr_request_resource(dma_resource) == status_success) { uint8_t dmamux_ch; - dma_manager_install_interrupt_callback(dma_resource, i2s_rx_dma_callback, hpm_audio); - dma_manager_enable_dma_interrupt(dma_resource, 1); + dma_mgr_install_chn_tc_callback(dma_resource, i2s_rx_dma_tc_callback, hpm_audio); + dma_mgr_enable_dma_irq_with_priority(dma_resource, 1); dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource->base, dma_resource->channel); dmamux_config(HPM_DMAMUX, dmamux_ch, hpm_audio->rx_dma_req, true); } else { @@ -433,9 +475,12 @@ static rt_err_t hpm_i2s_start(struct rt_audio_device* audio, int stream) return -RT_ERROR; } - if (RT_EOK != hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE)) { + i2s_disable(hpm_audio->base); + i2s_reset_tx_rx(hpm_audio->base); + if (I2S_FIFO_SIZE != hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE)) { return RT_ERROR; } + i2s_enable(hpm_audio->base); } else { return -RT_ERROR; } @@ -448,17 +493,21 @@ static rt_err_t hpm_i2s_stop(struct rt_audio_device* audio, int stream) RT_ASSERT(audio != RT_NULL); struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; + i2s_disable(hpm_audio->base); + if (stream == AUDIO_STREAM_REPLAY) { - hpm_dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; - dma_manager_release_resource(dma_resource); + dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; + dma_mgr_release_resource(dma_resource); } else if (stream == AUDIO_STREAM_RECORD) { - hpm_dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; - dma_manager_release_resource(dma_resource); + dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; + dma_mgr_release_resource(dma_resource); } else { return -RT_ERROR; } + hpm_audio->i2s_state = hpm_i2s_state_stop; + return RT_EOK; } @@ -480,7 +529,7 @@ static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* wr if(writeBuf != RT_NULL) { - hpm_dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; + dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; dma_channel_config_t ch_config = {0}; dma_default_channel_config(dma_resource->base, &ch_config); ch_config.src_addr = core_local_mem_to_sys_address(HPM_CORE0, (uint32_t)writeBuf); @@ -498,12 +547,13 @@ static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* wr l1c_dc_writeback((uint32_t)writeBuf, size); } + hpm_audio->i2s_state = hpm_i2s_state_write; if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config, true)) { LOG_E("dma setup channel failed\n"); return -RT_ERROR; } } else if (readBuf != RT_NULL){ - hpm_dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; + dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; dma_channel_config_t ch_config = {0}; dma_default_channel_config(dma_resource->base, &ch_config); ch_config.src_addr = (uint32_t)&hpm_audio->base->RXD[hpm_audio->transfer.data_line] + data_shift_byte; @@ -516,6 +566,7 @@ static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* wr ch_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + hpm_audio->i2s_state = hpm_i2s_state_read; if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config, true)) { LOG_E("dma setup channel failed\n"); return -RT_ERROR; diff --git a/common/libraries/drivers/drv_mcan.c b/common/libraries/drivers/drv_mcan.c index 3b075d4b..70dedb65 100644 --- a/common/libraries/drivers/drv_mcan.c +++ b/common/libraries/drivers/drv_mcan.c @@ -339,6 +339,7 @@ static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configu drv_can->can_config.all_filters_config.ext_id_filter_list.filter_elem_list = &drv_can->ext_can_filters[0]; drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = drv_can->ext_filter_num; drv_can->can_config.all_filters_config.ext_id_mask = (1UL << 30) - 1UL; + drv_can->can_config.txbuf_trans_interrupt_mask = ~0UL; hpm_stat_t status = mcan_init(drv_can->can_base, &drv_can->can_config, can_clk); if (status != status_success) @@ -360,6 +361,7 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) rt_err_t err = RT_EOK; uint32_t temp; + uint32_t irq_txrx_mask; switch (cmd) { @@ -368,19 +370,22 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) intc_m_disable_irq(drv_can->irq_num); if (arg_val == RT_DEVICE_FLAG_INT_RX) { - uint32_t irq_txrx_mask = MCAN_EVENT_RECEIVE; + irq_txrx_mask = MCAN_EVENT_RECEIVE; drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; + drv_can->can_config.interrupt_mask &= ~irq_txrx_mask; mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); } else if (arg_val == RT_DEVICE_FLAG_INT_TX) { - uint32_t irq_txrx_mask = MCAN_EVENT_TRANSMIT; + irq_txrx_mask = MCAN_EVENT_TRANSMIT; drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; + drv_can->can_config.interrupt_mask &= ~irq_txrx_mask; mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); mcan_disable_txbuf_interrupt(drv_can->can_base, ~0UL); } else if (arg_val == RT_DEVICE_CAN_INT_ERR) { - uint32_t irq_txrx_mask = MCAN_EVENT_ERROR; + irq_txrx_mask = MCAN_EVENT_ERROR; drv_can->irq_txrx_err_enable_mask &= ~irq_txrx_mask; + drv_can->can_config.interrupt_mask &= ~irq_txrx_mask; mcan_disable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); } else { err = -RT_ERROR; @@ -390,23 +395,26 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) arg_val = (uint32_t) arg; if (arg_val == RT_DEVICE_FLAG_INT_RX) { - uint32_t irq_txrx_mask = MCAN_EVENT_RECEIVE; + irq_txrx_mask = MCAN_EVENT_RECEIVE; drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; + drv_can->can_config.interrupt_mask |= irq_txrx_mask; mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); intc_m_enable_irq_with_priority(drv_can->irq_num, 1); } else if (arg_val == RT_DEVICE_FLAG_INT_TX) { - uint32_t irq_txrx_mask = MCAN_EVENT_TRANSMIT; + irq_txrx_mask = MCAN_EVENT_TRANSMIT; drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; + drv_can->can_config.interrupt_mask |= irq_txrx_mask; mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); mcan_enable_txbuf_interrupt(drv_can->can_base, ~0UL); intc_m_enable_irq_with_priority(drv_can->irq_num, 1); } else if (arg_val == RT_DEVICE_CAN_INT_ERR) { - uint32_t irq_txrx_mask = MCAN_EVENT_ERROR; + irq_txrx_mask = MCAN_EVENT_ERROR; drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; + drv_can->can_config.interrupt_mask |= irq_txrx_mask; mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); intc_m_enable_irq_with_priority(drv_can->irq_num, 1); } @@ -491,6 +499,12 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) drv_can->can_config.all_filters_config.ext_id_filter_list.mcan_filter_elem_count = 1; } err = hpm_mcan_configure(can, &drv_can->can_dev.config); +#ifdef RT_CAN_USING_HDR + if (filter == RT_NULL) { + /*if use RT_CAN_USING_HDR, but if want to receive everything without filtering, use default filter, need to return NO-RT-OK status*/ + err = -RT_ETRAP; + } +#endif } break; case RT_CAN_CMD_SET_MODE: @@ -587,6 +601,7 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) rt_memcpy(arg, &drv_can->can_dev.status, sizeof(drv_can->can_dev.status)); break; } + return err; } static int hpm_mcan_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) @@ -694,7 +709,11 @@ static int hpm_mcan_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t bo for(uint32_t i = 0; i < msg_len; i++) { can_msg->data[i] = rx_buf.data_8[i]; } - +#ifdef RT_CAN_USING_HDR + /* Hardware filter messages are valid */ + can_msg->hdr_index = boxno; + can->hdr[can_msg->hdr_index].connected = 1; +#endif } else { @@ -710,7 +729,9 @@ int rt_hw_mcan_init(void) config.privmode = RT_CAN_MODE_NOPRIV; config.sndboxnumber = CAN_SENDBOX_NUM; config.ticks = 50; - +#ifdef RT_CAN_USING_HDR + config.maxhdr = 32; +#endif for (uint32_t i = 0; i < ARRAY_SIZE(hpm_cans); i++) { hpm_cans[i]->can_dev.config = config; diff --git a/common/libraries/drivers/drv_pdm.c b/common/libraries/drivers/drv_pdm.c index e15185de..a2401afd 100644 --- a/common/libraries/drivers/drv_pdm.c +++ b/common/libraries/drivers/drv_pdm.c @@ -18,10 +18,14 @@ #include "hpm_i2s_drv.h" #include "hpm_pdm_drv.h" #include "drv_pdm.h" +#ifdef CONFIG_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else #include "hpm_dma_drv.h" +#endif #include "hpm_dmamux_drv.h" #include "hpm_l1c_drv.h" -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" /* PDM connect to I2S0 RX */ @@ -36,16 +40,14 @@ struct hpm_pdm }; struct hpm_pdm hpm_pdm_dev = { 0 }; -static hpm_dma_resource_t dma_resource = { 0 }; +static dma_resource_t dma_resource = { 0 }; static rt_err_t hpm_pdm_dma_transmit(); -void pdm_dma_callback(DMA_Type *ptr, uint32_t channel, void *user_data, uint32_t int_stat) +void pdm_dma_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) { - if (int_stat == DMA_CHANNEL_STATUS_TC) { - rt_audio_rx_done(&hpm_pdm_dev.audio, hpm_pdm_dev.rx_fifo, PDM_FIFO_SIZE); - hpm_pdm_dma_transmit(); - } + rt_audio_rx_done(&hpm_pdm_dev.audio, hpm_pdm_dev.rx_fifo, PDM_FIFO_SIZE); + hpm_pdm_dma_transmit(); } static rt_err_t hpm_pdm_getcaps(struct rt_audio_device* audio, struct rt_audio_caps* caps) @@ -95,6 +97,11 @@ static rt_err_t hpm_pdm_getcaps(struct rt_audio_device* audio, struct rt_audio_c return result; } +static bool i2s_is_enabled(I2S_Type *ptr) +{ + return ((ptr->CTRL & I2S_CTRL_I2S_EN_MASK) != 0); +} + static rt_err_t hpm_pdm_set_channels(uint32_t channel) { uint32_t mclk_hz; @@ -112,11 +119,17 @@ static rt_err_t hpm_pdm_set_channels(uint32_t channel) return -RT_ERROR; } + bool is_enabled = i2s_is_enabled(PDM_I2S); + dma_abort_channel(dma_resource.base, dma_resource.channel); if (status_success != i2s_config_rx(PDM_I2S, mclk_hz, &transfer)) { - LOG_E("dao_i2s configure transfer failed\n"); + LOG_E("pdm_i2s configure transfer failed\n"); return -RT_ERROR; } + if (is_enabled) + { + i2s_enable(PDM_I2S); + } return RT_EOK; } @@ -201,12 +214,13 @@ static rt_err_t hpm_pdm_start(struct rt_audio_device* audio, int stream) if (stream == AUDIO_STREAM_RECORD) { - pdm_start(HPM_PDM); + i2s_reset_tx_rx(PDM_I2S); + pdm_software_reset(HPM_PDM); - if (dma_manager_request_resource(&dma_resource) == status_success) { + if (dma_mgr_request_resource(&dma_resource) == status_success) { uint8_t dmamux_ch; - dma_manager_install_interrupt_callback(&dma_resource, pdm_dma_callback, NULL); - dma_manager_enable_dma_interrupt(&dma_resource, 1); + dma_mgr_install_chn_tc_callback(&dma_resource, pdm_dma_tc_callback, NULL); + dma_mgr_enable_dma_irq_with_priority(&dma_resource, 1); dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource.base, dma_resource.channel); dmamux_config(HPM_DMAMUX, dmamux_ch, PDM_DMA_REQ, true); } else { @@ -217,6 +231,9 @@ static rt_err_t hpm_pdm_start(struct rt_audio_device* audio, int stream) if (RT_EOK != hpm_pdm_dma_transmit()) { return RT_ERROR; } + + pdm_start(HPM_PDM); + i2s_start(PDM_I2S); } return RT_EOK; @@ -230,8 +247,9 @@ static rt_err_t hpm_pdm_stop(struct rt_audio_device* audio, int stream) { pdm_stop(HPM_PDM); } + i2s_stop(PDM_I2S); - dma_manager_release_resource(&dma_resource); + dma_mgr_release_resource(&dma_resource); return RT_EOK; } diff --git a/common/libraries/drivers/drv_pwm.c b/common/libraries/drivers/drv_pwm.c index 80136ce2..0407032e 100644 --- a/common/libraries/drivers/drv_pwm.c +++ b/common/libraries/drivers/drv_pwm.c @@ -100,7 +100,7 @@ rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channe pwm_config.enable_output = true; pwm_config.dead_zone_in_half_cycle = 0; - pwm_config.invert_output = true; + pwm_config.invert_output = false; /* * config pwm */ diff --git a/common/libraries/drivers/drv_spi.c b/common/libraries/drivers/drv_spi.c index cf033e34..6ec7c144 100644 --- a/common/libraries/drivers/drv_spi.c +++ b/common/libraries/drivers/drv_spi.c @@ -17,7 +17,7 @@ #include "drv_spi.h" #include "hpm_spi_drv.h" #include "hpm_sysctl_drv.h" -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" #include "hpm_dmamux_drv.h" #include "hpm_l1c_drv.h" @@ -34,8 +34,8 @@ struct hpm_spi rt_bool_t enable_dma; rt_uint8_t tx_dmamux; rt_uint8_t rx_dmamux; - hpm_dma_resource_t tx_dma; - hpm_dma_resource_t rx_dma; + dma_resource_t tx_dma; + dma_resource_t rx_dma; }; static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg); @@ -474,13 +474,13 @@ int rt_hw_spi_init(void) spi->spi_bus.parent.user_data = spi; if (spi->enable_dma) { - stat = dma_manager_request_resource(&spi->tx_dma); + stat = dma_mgr_request_resource(&spi->tx_dma); if (stat != status_success) { return -RT_ERROR; } - stat = dma_manager_request_resource(&spi->rx_dma); + stat = dma_mgr_request_resource(&spi->rx_dma); if (stat != status_success) { return -RT_ERROR; diff --git a/common/libraries/drivers/drv_uart_v2.c b/common/libraries/drivers/drv_uart_v2.c index 57ea89c7..3c98e585 100644 --- a/common/libraries/drivers/drv_uart_v2.c +++ b/common/libraries/drivers/drv_uart_v2.c @@ -18,9 +18,13 @@ #include "hpm_uart_drv.h" #include "hpm_sysctl_drv.h" #include "hpm_l1c_drv.h" +#ifdef CONFIG_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else #include "hpm_dma_drv.h" +#endif #include "hpm_dmamux_drv.h" -#include "hpm_dma_manager.h" +#include "hpm_dma_mgr.h" #include "hpm_soc.h" #ifdef RT_USING_SERIAL_V2 @@ -31,7 +35,7 @@ typedef struct dma_channel { struct rt_serial_device *serial; - hpm_dma_resource_t resource; + dma_resource_t resource; void (*tranfer_done)(struct rt_serial_device *serial); void (*tranfer_abort)(struct rt_serial_device *serial); void (*tranfer_error)(struct rt_serial_device *serial); @@ -546,32 +550,36 @@ enum #if defined(RT_SERIAL_USING_DMA) -static void uart_dma_callback(DMA_Type *base, uint32_t channel, void *user_data, uint32_t int_stat) +static void uart_dma_tc_callback(DMA_Type *base, uint32_t channel, void *user_data) { hpm_dma_channel_handle_t *dma_handle = (hpm_dma_channel_handle_t*)user_data; if ((dma_handle->resource.base != base) || (dma_handle->resource.channel != channel)) { return; } + dma_handle->tranfer_done(dma_handle->serial); +} - if (IS_HPM_BITMASK_SET(int_stat, DMA_CHANNEL_STATUS_TC) && (dma_handle->tranfer_done != NULL)) - { - dma_handle->tranfer_done(dma_handle->serial); - } - - if (IS_HPM_BITMASK_SET(int_stat, DMA_CHANNEL_STATUS_ABORT) && (dma_handle->tranfer_abort != NULL)) +static void uart_dma_abort_callback(DMA_Type *base, uint32_t channel, void *user_data) +{ + hpm_dma_channel_handle_t *dma_handle = (hpm_dma_channel_handle_t*)user_data; + if ((dma_handle->resource.base != base) || (dma_handle->resource.channel != channel)) { - dma_handle->tranfer_abort(dma_handle->serial); + return; } + dma_handle->tranfer_abort(dma_handle->serial); +} - if (IS_HPM_BITMASK_SET(int_stat, DMA_CHANNEL_STATUS_ERROR) && (dma_handle->tranfer_error != NULL)) +static void uart_dma_error_callback(DMA_Type *base, uint32_t channel, void *user_data) +{ + hpm_dma_channel_handle_t *dma_handle = (hpm_dma_channel_handle_t*)user_data; + if ((dma_handle->resource.base != base) || (dma_handle->resource.channel != channel)) { - dma_handle->tranfer_error(dma_handle->serial); + return; } + dma_handle->tranfer_error(dma_handle->serial); } - - static void uart_tx_done(struct rt_serial_device *serial) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); @@ -585,7 +593,7 @@ static void uart_rx_done(struct rt_serial_device *serial) uint32_t uart_recv_data_count = 0; struct hpm_uart *uart = (struct hpm_uart *)serial->parent.user_data; uint32_t rx_idle_tmp_buffer_size = sizeof(uart->rx_idle_tmp_buffer); - uart_recv_data_count = rx_idle_tmp_buffer_size - dma_get_residue_transfer_size(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel); + uart_recv_data_count = rx_idle_tmp_buffer_size - dma_get_remaining_transfer_size(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel); if (l1c_dc_is_enabled()) { uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)uart->rx_idle_tmp_buffer); uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)uart->rx_idle_tmp_buffer + rx_idle_tmp_buffer_size); @@ -631,7 +639,6 @@ static void hpm_uart_isr(struct rt_serial_device *serial) /* enter interrupt */ rt_interrupt_enter(); stat = uart_get_status(uart->uart_base); - enabled_irq = uart_get_enabled_irq(uart->uart_base); irq_id = uart_get_irq_id(uart->uart_base); if (irq_id == uart_intr_id_rx_data_avail) { @@ -654,7 +661,7 @@ static void hpm_uart_isr(struct rt_serial_device *serial) rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } - if ((enabled_irq & uart_intr_tx_slot_avail) && (stat & uart_stat_tx_slot_avail)) { + if ((irq_id & uart_intr_tx_slot_avail) && (stat & uart_stat_tx_slot_avail)) { /* UART in mode Transmitter */ struct rt_serial_tx_fifo *tx_fifo; tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx; @@ -664,16 +671,15 @@ static void hpm_uart_isr(struct rt_serial_device *serial) uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail); fifo_size = uart_get_fifo_size(uart->uart_base); ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb); - tx_size = (ringbuffer_data_len > fifo_size) ? fifo_size : ringbuffer_data_len; - for (uint32_t i = 0; i < tx_size; i++) { - rt_ringbuffer_getchar(&tx_fifo->rb, &put_char); - uart_write_byte(uart->uart_base, put_char); - } - ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb);; - if (ringbuffer_data_len) { - uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); - } else { + if (ringbuffer_data_len <= 0) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + } else { + tx_size = (ringbuffer_data_len > fifo_size) ? fifo_size : ringbuffer_data_len; + for (uint32_t i = 0; i < tx_size; i++) { + rt_ringbuffer_getchar(&tx_fifo->rb, &put_char); + uart_write_byte(uart->uart_base, put_char); + } + uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); } } #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) && defined(RT_SERIAL_USING_DMA) @@ -719,7 +725,7 @@ static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct seria uart_config.rxidle_config.detect_enable = true; uart_config.rxidle_config.detect_irq_enable = true; uart_config.rxidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one; - uart_config.rxidle_config.threshold = 10U; /* 10bit */ + uart_config.rxidle_config.threshold = 16U; /* 10bit */ #endif } @@ -737,12 +743,14 @@ hpm_stat_t hpm_uart_dma_rx_init(struct hpm_uart *uart_ctx) hpm_stat_t status = status_fail; if (!uart_ctx->rx_resource_allocated) { - status = dma_manager_request_resource(&uart_ctx->rx_chn_ctx.resource); + status = dma_mgr_request_resource(&uart_ctx->rx_chn_ctx.resource); if (status == status_success) { uart_ctx->dma_flags |= RT_DEVICE_FLAG_DMA_RX; uart_ctx->rx_resource_allocated = true; - dma_manager_install_interrupt_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_callback, &uart_ctx->rx_chn_ctx); + dma_mgr_install_chn_tc_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_tc_callback, &uart_ctx->rx_chn_ctx); + dma_mgr_install_chn_abort_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_abort_callback, &uart_ctx->rx_chn_ctx); + dma_mgr_install_chn_error_callback(&uart_ctx->rx_chn_ctx.resource, uart_dma_error_callback, &uart_ctx->rx_chn_ctx); } } return status; @@ -753,12 +761,14 @@ hpm_stat_t hpm_uart_dma_tx_init(struct hpm_uart *uart_ctx) hpm_stat_t status = status_fail; if (!uart_ctx->tx_resource_allocated) { - status = dma_manager_request_resource(&uart_ctx->tx_chn_ctx.resource); + status = dma_mgr_request_resource(&uart_ctx->tx_chn_ctx.resource); if (status == status_success) { uart_ctx->dma_flags |= RT_DEVICE_FLAG_DMA_TX; uart_ctx->tx_resource_allocated = true; - dma_manager_install_interrupt_callback(&uart_ctx->tx_chn_ctx.resource, uart_dma_callback, &uart_ctx->tx_chn_ctx); + dma_mgr_install_chn_tc_callback(&uart_ctx->tx_chn_ctx.resource, uart_dma_tc_callback, &uart_ctx->tx_chn_ctx); + dma_mgr_install_chn_abort_callback(&uart_ctx->tx_chn_ctx.resource, uart_dma_abort_callback, &uart_ctx->tx_chn_ctx); + dma_mgr_install_chn_error_callback(&uart_ctx->tx_chn_ctx.resource, uart_dma_error_callback, &uart_ctx->tx_chn_ctx); } } return status; @@ -876,10 +886,10 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void } #ifdef RT_SERIAL_USING_DMA else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { - dma_manager_disable_channel_interrupt(&uart->tx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL); + dma_mgr_disable_chn_irq(&uart->tx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL); dma_abort_channel(uart->tx_chn_ctx.resource.base, uart->tx_chn_ctx.resource.channel); } else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) { - dma_manager_disable_channel_interrupt(&uart->rx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL); + dma_mgr_disable_chn_irq(&uart->rx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL); dma_abort_channel(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel); } #endif @@ -1007,7 +1017,7 @@ static rt_ssize_t hpm_uart_transmit(struct rt_serial_device *serial, #endif if (size > 0) { - if (uart_check_status(uart->uart_base, uart_stat_transmitter_empty)) { + if (uart_check_status(uart->uart_base, uart_stat_tx_slot_avail)) { uart_disable_irq(uart->uart_base, uart_intr_tx_slot_avail); fifo_size = uart_get_fifo_size(uart->uart_base); ringbuffer_data_len = rt_ringbuffer_data_len(&tx_fifo->rb); @@ -1016,11 +1026,7 @@ static rt_ssize_t hpm_uart_transmit(struct rt_serial_device *serial, rt_ringbuffer_getchar(&tx_fifo->rb, &ch); uart_write_byte(uart->uart_base, ch); } - if (rt_ringbuffer_data_len(&tx_fifo->rb)) { - uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); - } else { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); - } + uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); } } } diff --git a/common/libraries/hpm_sdk/CHANGELOG.md b/common/libraries/hpm_sdk/CHANGELOG.md index b454a99b..0f41f27c 100644 --- a/common/libraries/hpm_sdk/CHANGELOG.md +++ b/common/libraries/hpm_sdk/CHANGELOG.md @@ -1,5 +1,182 @@ # Change Log +## [1.3.0] - 2023-09-30: + +Main changes since 1.2.0 + +Tested Segger Embedded Studio Version: 7.32 + +### Changed: + - boards: hpm6200evk/hpm6300evk: delete unwanted clock_ahb div set + - boards: hpm6750xxx: switch dcdc work mode to dcm mode + - docs: sdk: boards: hpm6750evk2: add pps pin information + - component: wm8960: support sysclk pre-divider + - components: serial_nor: add serial nor flash. + - openocd: probes: ft2232: remove trst and srst config. + - ip: cam：remove 0x5c MAX_WN_CYCLE register in regs.h + - driver: cam: remove invalid register + - drivers: i2s: update API + - drivers: adc: adc12/adc16: rename adc16_get_busywait to adc16_is_nonblocking_mode + - drivers: adc: adc12/adc16: update adcx_init API + - drivers: pllctrl: update pllctrl drivers + - drivers: spi : add spi enable and disable datamerge + - drivers: spi : add spi_set_address_len API + - drivers: pdgo Add missing APIs + - drivers: uart: update uart rx idle flag process and fifo control + - soc: delete_unnecessary_ppor_reset_bit_field + - soc: hpm_gpiom_soc_drv.h: delete gpiom_gpio_t soc name + - soc: delete DMA_SOC_BUS_NUM Macro + - soc: pcfg: update pcfg SCG_CTRL related drivers + - soc: hpm6750:startup Enable LMM1 clock before access to LMM1 + - soc: gcc ld: add memory used size check + - middleware: cherryusb: update to v0.10.1 + - middleware: guix: demo adapts to 800 * 480 resolution + - middleware: guix: improve demo display performance + - middleware: cherryusb: update for midi descriptor define + - middleware: cherryusb: update for midi + - samples: drivers: adc: adc12/adc16: speed optimization for oneshot reading + - samples: drivers: adc: adc12/adc16： update API call used for nonblocking judgement + - samples: drivers: adc: adc12/adc16: update API call related to blocking setting in oneshot mode + - samples: drivers: adc: adc12/adc16: reduce the input parameters of init_trigger_target function + - samples: drivers: adc: adc12/adc16: update init_oneshot_config + - samples: drivers: adc: adc12/adc16: optimization for clearing interrupt status + - samples: drivers: pwm: Add pwm clock jitter demo + - samples: cherryusb: hid host: separate mouse and keyboard urb + - samples: hrpwm: Add demo for updating hrpwm frequency + - samples: drivers:mcan Add CAN error handling and refined logic. + - samples: mbx: move dualcore mbx sample to multicore folder + - samples: cherryusb: update for v0.10.1 + - samples: motor_ctrl: bldc smc: gcc toolcahin enable fpu. + - samples: lwip: lwip_tcpecho_freertos: optimization in a thread-safety way + - samples: qeo: update qeo abz frequency configuration + - samples: gptmr: add sent_signal sample. + - samples: lwip: lwip_ptp: remove the dependency on pps0 pinout + - samples: dma_manager: update for use dma_mgr_setup_channel() + - samples: drivers: gptmr: pwm_measure: support use dma + - samples: lwip: lwip_httpsrv/lwip_https_server: rename project names for uniform naming + - samples: multicore: lvgl_coremark: delete custom linker files and using andes toolchain + - samples: flash_algo: update device size. + - samples: cherryusb: host: hid: use ep_mps to fill urb + +### Added: + - cmake: ses: support specify custom openocd board cfg file. + - cmake: support specifying minimum sdk version in app.yaml. + - boards: add hpm5300evk + - components: eeprom_emulation: add hpm nor-flash support + - components: eeprom_emulation: add eeprom emulation component + - soc: add APIs for get or set sysctl resource status + - drivers: common: add HPM_ALIGN_DOWN and HPM_ALIGN_UP define + - drivers: adc: ad12/adc16: add adcx_set_blocking_read/adcx_set_nonblocking_read + - drivers: add encoder position driver + - drivers: lcdc: add enable/disable background in alpha blender. + - drivers: usb: add api to set dp/dm pin pulldown resistance + - drivers: spi: add spi_get_rx_fifo_valid_data_size and spi_get_tx_fifo_valid_data_size APIs + - drivers: spi: add directIO function APIs + - drivers: enet: add rx resume API + - drivers: adc16: add resolution setting in adc16_get_default_config API + - drivers:rtc Add rtc_get_timeval API. + - drivers:mcan Add mcan_transmit_via_txfifo_nonblocking API. + - drivers: usb: add usb_hcd_set_power_ctrl_polarity() API + - drivers: plb: add plb drivers + - drivers: linv2: add linv2 driver + - drivers: sei: add sei driver + - drivers: dmav2: add dmav2 driver + - drivers: qeo: add qeo driver + - drivers: qeiv2: add qeiv2 driver + - drivers: mmc: add mmc driver + - drivers: rdc: add rdc driver + - drivers: add opamp driver + - drivers: bgpr: add related APIs for bgpr + - middleware: FreeRTOS: add xPortIsInsideInterrupt() API + - middleware: threadx: add definition automatically when enable traceX + - middleware: freeRTOS: add use gptmr to generate interrupt + - middleware: hpm_mcl: add hfi + - samples: drivers: adc: adc12/adc16: add wdog feature + - samples: add opamp demo + - samples: cherryusb: rndis: host: add iperf sample. + - samples: cherryusb: rndis: host: add ping sample. + - samples: drivers: adc: adc12/adc16: add hw trigger configuration in sequence mode + - samples: eeprom_emulation: add eeprom emulation perf test sample + - samples: eeprom_emulation: add base api demo + - samples: tracex: add demo for traceX usage + - samples: cherryusb: add audio_v1_mic_speaker_midi sample + - samples: cherryusb: add midi device sample + - samples: drivers: sei: add sei samples + - samples: drivers: plb: add plb demo + - samples: drivers: mmc: add mmc demo + - samples: drivers: qeiv2: add qeiv2 demo + - samples: drivers: qeo: add qeo demo + - samples: drivers: dmav2: add dmav2 demo + - samples: drivers: linv2: add linv2 demo + - samples: drivers: rdc: add rdc demo + - samples: drivers: pdgo Add PDGO samples + - samples: drivers: ewdg Add EWDG sample + - samples: lwip: add a lwip_tcpecho_multi_ports sample + - samples: motor_ctrl: add hfi + +### Fixed: + - cmake: fix segger default heap and stack size config + - cmake: fix add_subdirectory_ifdef arg processing. + - doc: boards: hpm6300evk: fix acmp pin info. + - boards: hpm6750evkmini: fix board_init_rgb_pwm_pins() problem + - boards: hpm6200evk: fix BOARD_G_GPIO_CTRL defined in wrong position + - openocd: hpm6750-dual-core: fix expression warning. + - component: wm8960: fix clock tolerance process + - soc: toolchains: segger: block tls add with fixed order + - soc: toolchain: gcc: fix Thread-Local Storage problem + - soc: segger linker files: fix heap and ctors initialize + - soc: fix interrupt complete operation + - soc: pcfg: fix DCDC_PROT[OVERLOAD_LP] bit access + - soc: ip: adc12: fix ADC12 threshold setting + - soc: HPM6750: fix clock setting and frequency obatining error + - soc: HPM6360: fix clock source definitions for ADC16 + - soc: HPM6280: fix clock source definitions for ADC16 + - soc: HPM6360: fix obtaining clock source error for DAC + - soc: HPM6280: fix obtaining clock source for DAC + - drivers: adc16: add bus mode enable control APIs + - drivers: adc16: fix ahb setting + - drivers: cam: clear the status of CAM should not affect other bits + - drivers: trgmux: filter function can't work. + - drivers: src: adc16: fix end count setting + - drivers: adc/dac: fix interrupt status clearing + - drivers: adc16: fix DMA access format + - drivers: sdm: fix over sample rate and signal sync problem + - drivers: pwm: fix pwm xcmp enable setting + - drivers: pwm: correct external fault polarity setting. + - drivers: pwm: add update hrpwm reload shadow api + - drivers: spi: fix can't set change data_bits use spi_set_data_bits API + - drivers: ptpc: fix ptpc_clear_irq_status API issue. + - drivers: i2c: fix i2c_clear_status API issue. + - drivers: gptmr: fix gptmr_clear_status API issue. + - middleware: erpc: rpmsg_lite: fix platform_in_isr() error + - middleware:hpm_sdmmc Fix the issue sdsc cards are not supported. + - middleware: threadx: fix D extend asm code error + - samples: usbx: add multi devices and hot plug support + - samples: motor_ctrl: fix adc trig invalidate. + - samples: lwip: fix TCP reception error when size over 2KB + - samples: lwip: DHCP failure in lwip_tcpecho_freertos + - samples: drivers: adc: adc12: fix the status flag judgement in isr process + - samples: rgb_led: fix cmp shadow error + - samples: gptmr: pwm_generate: fix inaccurate duty in high frequency + - samples: lwip: low_level_input: fix the network storm issue + - samples: timer_basic: fix inconsistent use of defines + - samples: drivers: adc: adc16: fix the bit of interrupt status clearing in sequence mode + - samples: power_mode_switch: trigger system lowpower for standby mode + - samples: touch_panel: fix error data when 5 fingers touch screen at same time. + - samples: jpeg: jpeg_decode: fixed lcd display is tore when decoder is running + - samples: jpeg: jpeg_decode: malloc out of memory on gcc + - samples: drivers:can Fix abnormal behavior on can error sample. + - samples: segger_rtt: call board_init_clock. + - samples: drivers: acmp: fix one toggle value but multi toggle pulses + - samples: lwip_tcpecho_freerstos: fix code stuck with gcc toolchain + - samples: jpeg: fix JPEG_USE_UDISK compile error + - samples: bldc_foc: fix input value range. + - samples: cherryusb: rndis: udp_echo: fix echo extra char + - samples: usbx: fix global var placement + - samples: power_mode_switch: set to preset_1 after exiting wait mode. + - samples: pla: fix pla first pulse abnormal. + - samples: plb: fix the first pulse is abnormal. + ## [1.2.0] - 2023-06-30: Main changes since 1.1.0 diff --git a/common/libraries/hpm_sdk/CMakeLists.txt b/common/libraries/hpm_sdk/CMakeLists.txt index be360846..de8361a4 100644 --- a/common/libraries/hpm_sdk/CMakeLists.txt +++ b/common/libraries/hpm_sdk/CMakeLists.txt @@ -15,9 +15,6 @@ if(extram_size) sdk_linker_global_symbols("_extram_size=${extram_size}") endif() -sdk_linker_global_symbols("_heap_size=${HEAP_SIZE}") -sdk_linker_global_symbols("_stack_size=${STACK_SIZE}") - if(NOT ${CMAKE_BUILD_TYPE} STREQUAL "") string(TOLOWER ${CMAKE_BUILD_TYPE} build_type) string(FIND ${build_type} "release" found) @@ -81,7 +78,7 @@ if(NOT ${CMAKE_BUILD_TYPE} STREQUAL "") string(FIND ${build_type} "sec_core_img" found) if(${found} GREATER_EQUAL 0) - set(GEN_SEC_CORE_IMG_C_ARRAY true) + set(GEN_SEC_CORE_IMG_C_ARRAY true PARENT_SCOPE) endif() else() @@ -155,16 +152,17 @@ endif() sdk_ld_options("-T ${LINKER_SCRIPT}") set(generated_file_path "${PROJECT_BINARY_DIR}/generated") -# prepare dummy file -set(EMPTY_FILE ${generated_file_path}/misc/empty.c) -file(WRITE ${EMPTY_FILE} "") - -add_executable(${APP_ELF_NAME} ${EMPTY_FILE}) # generate SDK version file execute_process( COMMAND ${CMAKE_COMMAND} -DHPM_SDK_BASE=${HPM_SDK_BASE} -DOUT_FILE=${generated_file_path}/include/hpm_sdk_version.h + -DSDKVERSION=${SDKVERSION} + -DSDK_VERSION_NUMBER=${SDK_VERSION_NUMBER} + -DSDK_VERSION_MAJOR=${SDK_VERSION_MAJOR} + -DSDK_VERSION_MINOR=${SDK_VERSION_MINOR} + -DSDK_PATCHLEVEL=${SDK_PATCHLEVEL} + -DSDK_VERSION_STRING=${SDK_VERSION_STRING} -P ${HPM_SDK_BASE}/cmake/gen_version_h.cmake WORKING_DIRECTORY ${PROJECT_BINARY_DIR} ) @@ -197,21 +195,3 @@ else() ${HPM_SDK_LIB} ${HPM_SDK_LIB_ITF} app "-Wl,--no-whole-archive") endif() - -add_custom_command( - TARGET ${APP_ELF_NAME} - COMMAND "${CROSS_COMPILE}objcopy" -O binary -S ${EXECUTABLE_OUTPUT_PATH}/${APP_ELF_NAME} ${EXECUTABLE_OUTPUT_PATH}/${APP_BIN_NAME} -) - -add_custom_command( - TARGET ${APP_ELF_NAME} - COMMAND "${CROSS_COMPILE}objdump" -S -d ${EXECUTABLE_OUTPUT_PATH}/${APP_ELF_NAME} > ${EXECUTABLE_OUTPUT_PATH}/${APP_ASM_NAME} -) - - -if (DEFINED GEN_SEC_CORE_IMG_C_ARRAY) - if(NOT DEFINED SEC_CORE_IMG_C_ARRAY_OUTPUT) - set(SEC_CORE_IMG_C_ARRAY_OUTPUT "sec_core_img.c") - endif() - generate_bin2c_array(${SEC_CORE_IMG_C_ARRAY_OUTPUT}) -endif() diff --git a/common/libraries/hpm_sdk/README_zh.md b/common/libraries/hpm_sdk/README_zh.md index 1b66378f..cc1abb5f 100644 --- a/common/libraries/hpm_sdk/README_zh.md +++ b/common/libraries/hpm_sdk/README_zh.md @@ -167,7 +167,7 @@ HPM SDK项目是基于HPMicro 公司的MCU编写的软件开发包，支持多 ``` - 使用GNU GCC工具链编译示例应用: - 做完尚书步骤之后, 就可以构建编译SDK示例工程. 以下步骤描述了如何编译hello_world: + 做完上述步骤之后, 就可以构建编译SDK示例工程. 以下步骤描述了如何编译hello_world: 1. 切换到示例应用目录: ```shell diff --git a/common/libraries/hpm_sdk/SConscript b/common/libraries/hpm_sdk/SConscript index 425073a3..5ac13fbd 100644 --- a/common/libraries/hpm_sdk/SConscript +++ b/common/libraries/hpm_sdk/SConscript @@ -13,9 +13,12 @@ src = [] src += ['drivers/src/hpm_pmp_drv.c'] src += ['drivers/src/hpm_pllctl_drv.c'] src += ['drivers/src/hpm_pllctlv2_drv.c'] -src += ['drivers/src/hpm_dma_drv.c'] src += ['drivers/src/hpm_pcfg_drv.c'] +if rtconfig.CHIP_NAME == "HPM6750" or rtconfig.CHIP_NAME == "HPM6360" or rtconfig.CHIP_NAME == "HPM6280": + src += ['drivers/src/hpm_dma_drv.c'] +else: + src += ['drivers/src/hpm_dmav2_drv.c'] if GetDepend(['BSP_USING_GPIO']): src += ['drivers/src/hpm_gpio_drv.c'] @@ -35,6 +38,9 @@ if GetDepend(['BSP_USING_RTC']): if GetDepend(['BSP_USING_WDG']): src += ['drivers/src/hpm_wdg_drv.c'] +if GetDepend(['BSP_USING_EWDG']): + src += ['drivers/src/hpm_ewdg_drv.c'] + if GetDepend(['BSP_USING_ADC']): if GetDepend(['BSP_USING_ADC12']): src += ['drivers/src/hpm_adc12_drv.c'] diff --git a/common/libraries/hpm_sdk/VERSION b/common/libraries/hpm_sdk/VERSION index 5e41d154..c82a3186 100644 --- a/common/libraries/hpm_sdk/VERSION +++ b/common/libraries/hpm_sdk/VERSION @@ -1,5 +1,5 @@ VERSION_MAJOR = 1 -VERSION_MINOR = 2 +VERSION_MINOR = 3 PATCHLEVEL = 0 VERSION_TWEAK = 0 EXTRAVERSION = 0 diff --git a/common/libraries/hpm_sdk/boards/hpm5300evk/CMakeLists.txt b/common/libraries/hpm_sdk/boards/hpm5300evk/CMakeLists.txt new file mode 100644 index 00000000..1c7bc734 --- /dev/null +++ b/common/libraries/hpm_sdk/boards/hpm5300evk/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + + +sdk_inc(.) +sdk_src(pinmux.c) +sdk_src(board.c) diff --git a/common/libraries/hpm_sdk/boards/hpm5300evk/board.c b/common/libraries/hpm_sdk/boards/hpm5300evk/board.c new file mode 100644 index 00000000..6688112f --- /dev/null +++ b/common/libraries/hpm_sdk/boards/hpm5300evk/board.c @@ -0,0 +1,615 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_sdk_version.h" +#include "hpm_gptmr_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_usb_drv.h" +#include "hpm_clock_drv.h" +#include "hpm_pllctlv2_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_pcfg_drv.h" + +static board_timer_cb timer_cb; + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0}; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART + console_config_t cfg; + + /* uart needs to configure pin function before enabling clock, otherwise the level change of + * uart rx pin when configuring pin function will cause a wrong data to be received. + * And a uart rx dma request will be generated by default uart fifo dma trigger level. + */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_BASE); + + /* Configure the UART clock to 24MHz */ + clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_CLK_NAME, 0); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t)BOARD_CONSOLE_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_BAUDRATE; + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while (1) + ; +#endif +#endif +} + +void board_print_banner(void) +{ + const uint8_t banner[] = "\n" +"----------------------------------------------------------------------\n" +"$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n" +"$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n" +"$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n" +"$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n" +"$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n" +"$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n" +"$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n" +"\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n" +"----------------------------------------------------------------------\n"; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif + printf("%s", banner); +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); + printf("==============================\n"); +} + +void board_init(void) +{ + init_xtal_pins(); + init_py_pins_as_pgpio(); + board_init_usb_dp_dm_pins(); + + board_init_clock(); + board_init_console(); + board_init_pmp(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_usb_dp_dm_pins(void) +{ + /* Disconnect usb dp/dm pins pull down 45ohm resistance */ + + while (sysctl_resource_any_is_busy(HPM_SYSCTL)) { + ; + } + if (pllctlv2_xtal_is_stable(HPM_PLLCTLV2) && pllctlv2_xtal_is_enabled(HPM_PLLCTLV2)) { + if (clock_check_in_group(clock_usb0, 0)) { + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + } else { + clock_add_to_group(clock_usb0, 0); + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + clock_remove_from_group(clock_usb0, 0); + } + } else { + uint8_t tmp; + tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal); + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03); + clock_add_to_group(clock_usb0, 0); + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + clock_remove_from_group(clock_usb0, 0); + while (sysctl_resource_target_is_busy(HPM_SYSCTL, sysctl_resource_usb0)) { + ; + } + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, tmp); + } +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, 2); + } + + /* group0[0] */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_ahb, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_rom, 0); + clock_add_to_group(clock_can0, 0); + clock_add_to_group(clock_can1, 0); + clock_add_to_group(clock_can2, 0); + clock_add_to_group(clock_can3, 0); + clock_add_to_group(clock_ptpc, 0); + clock_add_to_group(clock_lin0, 0); + clock_add_to_group(clock_lin1, 0); + clock_add_to_group(clock_lin2, 0); + clock_add_to_group(clock_lin3, 0); + clock_add_to_group(clock_gptmr0, 0); + clock_add_to_group(clock_gptmr1, 0); + clock_add_to_group(clock_gptmr2, 0); + clock_add_to_group(clock_gptmr3, 0); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + clock_add_to_group(clock_spi0, 0); + clock_add_to_group(clock_spi1, 0); + clock_add_to_group(clock_spi2, 0); + clock_add_to_group(clock_spi3, 0); + clock_add_to_group(clock_uart0, 0); + clock_add_to_group(clock_uart1, 0); + clock_add_to_group(clock_uart2, 0); + clock_add_to_group(clock_uart3, 0); + clock_add_to_group(clock_uart4, 0); + clock_add_to_group(clock_uart5, 0); + clock_add_to_group(clock_uart6, 0); + /* group0[1] */ + clock_add_to_group(clock_uart7, 0); + clock_add_to_group(clock_watchdog0, 0); + clock_add_to_group(clock_watchdog1, 0); + clock_add_to_group(clock_mbx0, 0); + clock_add_to_group(clock_tsns, 0); + clock_add_to_group(clock_crc0, 0); + clock_add_to_group(clock_adc0, 0); + clock_add_to_group(clock_adc1, 0); + clock_add_to_group(clock_dac0, 0); + clock_add_to_group(clock_dac1, 0); + clock_add_to_group(clock_acmp, 0); + clock_add_to_group(clock_opa0, 0); + clock_add_to_group(clock_opa1, 0); + clock_add_to_group(clock_mot0, 0); + clock_add_to_group(clock_rng, 0); + clock_add_to_group(clock_sdp, 0); + clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_usb0, 0); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + /* Bump up DCDC voltage to 1175mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1175); + + /* Configure CPU to 480MHz, AXI/AHB to 160MHz */ + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3); + /* Configure PLL0 Post Divider */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); /* PLL0CLK0: 960MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3); /* PLL0CLK1: 600MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7); /* PLL0CLK2: 400MHz */ + /* Configure PLL0 Frequency to 960MHz */ + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 960000000); + + clock_update_core_clock(); + + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); +} + +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); + gpio_set_pin_input(BOARD_APP_GPIO_CTRL, BOARD_APP_GPIO_INDEX, BOARD_APP_GPIO_PIN); +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level()); +} + +void board_init_usb_pins(void) +{ + init_usb_pins(); + usb_hcd_set_power_ctrl_polarity(BOARD_USB, true); + + /* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */ + /* usb_phy_using_internal_vbus(BOARD_USB); */ +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_led_toggle(void) +{ + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +} + +void board_init_uart(UART_Type *ptr) +{ + /* configure uart's pin before opening uart's clock */ + init_uart_pins(ptr); + board_init_uart_clock(ptr); +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + clock_add_to_group(clock_spi1, 0); + return clock_get_frequency(clock_spi1); + } + return 0; +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_init_lin_pins(LINV2_Type *ptr) +{ + init_lin_pins(ptr); + gpio_set_pin_output_with_initial(BOARD_12V_EN_GPIO_CTRL, BOARD_12V_EN_GPIO_INDEX, BOARD_12V_EN_GPIO_PIN, 1); /* enable 12v output */ +} + +uint32_t board_init_lin_clock(LINV2_Type *ptr) +{ + if (ptr == HPM_LIN2) { + clock_add_to_group(clock_lin2, 0); + clock_set_source_divider(clock_lin2, clk_src_pll1_clk0, 40U); /* 20MHz */ + return clock_get_frequency(clock_lin2); + } else if (ptr == HPM_LIN3) { + clock_add_to_group(clock_lin3, 0); + clock_set_source_divider(clock_lin3, clk_src_pll1_clk0, 40U); /* 20MHz */ + return clock_get_frequency(clock_lin3); + } + return 0; +} + +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +{ +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U); + } + + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll0_clk2, 2U); + } + + freq = clock_get_frequency(clock_adc1); + } + + return freq; +} + +void board_init_adc16_pins(void) +{ + init_adc_pins(); +} + +uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_DAC0) { + if (clk_src_ahb == true) { + /* Configure the DAC clock to 180MHz */ + clock_set_dac_source(clock_dac0, clk_dac_src_ahb0); + } else { + /* Configure the DAC clock to 166MHz */ + clock_set_dac_source(clock_dac0, clk_dac_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll0_clk1, 2); + } + + freq = clock_get_frequency(clock_dac0); + } else if (ptr == HPM_DAC1) { + if (clk_src_ahb == true) { + /* Configure the DAC clock to 180MHz */ + clock_set_dac_source(clock_dac1, clk_dac_src_ahb0); + } else { + /* Configure the DAC clock to 166MHz */ + clock_set_dac_source(clock_dac1, clk_dac_src_ana3); + clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2); + } + + freq = clock_get_frequency(clock_dac1); + } + + return freq; +} + +void board_init_can(MCAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(MCAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_MCAN0) { + clock_add_to_group(clock_can0, 0); + clock_set_source_divider(clock_can0, clock_source_pll1_clk0, 10); + freq = clock_get_frequency(clock_can0); + } + if (ptr == HPM_MCAN1) { + clock_add_to_group(clock_can1, 0); + clock_set_source_divider(clock_can1, clock_source_pll1_clk0, 10); + freq = clock_get_frequency(clock_can1); + } + if (ptr == HPM_MCAN2) { + clock_add_to_group(clock_can2, 0); + clock_set_source_divider(clock_can2, clock_source_pll1_clk0, 10); + freq = clock_get_frequency(clock_can2); + } + if (ptr == HPM_MCAN3) { + clock_add_to_group(clock_can3, 0); + clock_set_source_divider(clock_can3, clock_source_pll1_clk0, 10); + freq = clock_get_frequency(clock_can3); + } + return freq; +} + +void board_init_rgb_pwm_pins(void) +{ + init_led_pins_as_pwm(); +} + +void board_disable_output_rgb_led(uint8_t color) +{ +} + +void board_enable_output_rgb_led(uint8_t color) +{ +} + +void board_init_dac_pins(DAC_Type *ptr) +{ + init_dac_pins(ptr); +} + +uint8_t board_get_led_pwm_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +void board_init_pmp(void) +{ +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART1) { + clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); + clock_add_to_group(clock_uart1, 0); + freq = clock_get_frequency(clock_uart1); + } else if (ptr == HPM_UART2) { + clock_set_source_divider(clock_uart2, clk_src_pll0_clk2, 8); + clock_add_to_group(clock_uart2, 0); + freq = clock_get_frequency(clock_uart2); + } + + return freq; +} + +void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx) +{ + init_sei_pins(ptr, sei_ctrl_idx); +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + if (i2c_get_line_scl_status(ptr) == false) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (i2c_get_line_sda_status(ptr) == false) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + i2s_gen_reset_signal(ptr, 9); + board_delay_ms(100); + printf("I2C bus is cleared\n"); +} + +void board_init_i2c(I2C_Type *ptr) +{ + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + if (ptr == NULL) { + return; + } + init_i2c_pins(ptr); + board_i2c_bus_clear(ptr); + + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + /* Configure the I2C clock to 24MHz */ + clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); + while (1) { + } + } + +} + diff --git a/common/libraries/hpm_sdk/boards/hpm5300evk/board.h b/common/libraries/hpm_sdk/boards/hpm5300evk/board.h new file mode 100644 index 00000000..afa06dfa --- /dev/null +++ b/common/libraries/hpm_sdk/boards/hpm5300evk/board.h @@ -0,0 +1,354 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include +#include "hpm_common.h" +#include "hpm_clock_drv.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "pinmux.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif + +#define BOARD_NAME "hpm5300evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_4 /* align with used pin */ + +/* dma section */ +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_HDMA +#define TEST_DMA_IRQ IRQn_HDMA + +/* uart section */ +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART0 +#define BOARD_APP_UART_IRQ IRQn_UART0 +#else +#ifndef BOARD_APP_UART_IRQ +#warning no IRQ specified for application uart +#endif +#endif + +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart0 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX + +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART +#endif + +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART +#ifndef BOARD_CONSOLE_BASE +#define BOARD_CONSOLE_BASE HPM_UART0 +#define BOARD_CONSOLE_CLK_NAME clock_uart0 +#endif +#define BOARD_CONSOLE_BAUDRATE (115200UL) +#endif + +#define BOARD_FREEMASTER_UART_BASE HPM_UART2 +#define BOARD_FREEMASTER_UART_IRQ IRQn_UART2 +#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart2 + +/* nor flash section */ +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) /* Check */ +#define BOARD_FLASH_SIZE (SIZE_1MB) + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 +#define BOARD_APP_I2C_CLK_NAME clock_i2c0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR0 +#define BOARD_GPTMR_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM HPM_GPTMR0 +#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0 + +/* User LED */ +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 +#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_LED_GPIO_PIN 23 + +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 + +/* 12V Power Enable*/ +#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0 +#define BOARD_12V_EN_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_12V_EN_GPIO_PIN 24 + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* User button */ +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_APP_GPIO_PIN 9 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI1 +#define BOARD_APP_SPI_CLK_NAME clock_spi1 +#define BOARD_APP_SPI_IRQ IRQn_SPI1 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PA26 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* ADC section */ +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (11U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A + +/* DAC section */ +#define BOARD_DAC_BASE HPM_DAC0 +#define BOARD_DAC_IRQn IRQn_DAC0 +#define BOARD_APP_DAC_CLOCK_NAME clock_dac0 + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* SDXC section */ +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC0) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) + +/* MCAN section */ +#define BOARD_APP_CAN_BASE HPM_MCAN3 +#define BOARD_APP_CAN_IRQn IRQn_CAN3 + +/* CALLBACK TIMER section */ +#define BOARD_CALLBACK_TIMER (HPM_GPTMR3) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) + +/* APP PWM */ +#define BOARD_APP_PWM HPM_PWM0 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 +#define BOARD_APP_PWM_OUT1 2 +#define BOARD_APP_PWM_OUT2 3 +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM0 +#define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM0_SYNCI + +/*BLDC pwm*/ +/*PWM define*/ +#define BOARD_BLDCPWM HPM_PWM0 +#define BOARD_BLDC_UH_PWM_OUTPIN (6U) +#define BOARD_BLDC_UL_PWM_OUTPIN (7U) +#define BOARD_BLDC_VH_PWM_OUTPIN (4U) +#define BOARD_BLDC_VL_PWM_OUTPIN (5U) +#define BOARD_BLDC_WH_PWM_OUTPIN (2U) +#define BOARD_BLDC_WL_PWM_OUTPIN (3U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM0 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM0 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) + +/*HALL define*/ + +/*RDC*/ +#define BOARD_RDC_TRGM HPM_TRGM0 +#define BOARD_RDC_TRGIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_RDC_TRGO_0 +#define BOARD_RDC_TRG_NUM TRGM_TRGOCFG_MOT_GPIO0 +#define BOARD_RDC_TRG_ADC_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_RDC_ADC_I_BASE HPM_ADC0 +#define BOARD_RDC_ADC_Q_BASE HPM_ADC1 +#define BOARD_RDC_ADC_I_CHN (5U) +#define BOARD_RDC_ADC_Q_CHN (6U) +#define BOARD_RDC_ADC_IRQn IRQn_ADC0 +#define BOARD_RDC_ADC_TRIG_FLAG adc16_event_trig_complete +#define BOARD_RDC_ADC_TRG ADC16_CONFIG_TRG0A + +/*QEI*/ +#define BOARD_BLDC_QEI_TRGM HPM_TRGM0 +#define BOARD_BLDC_QEIV2_BASE HPM_QEI1 +#define BOARD_BLDC_QEIV2_IRQ IRQn_QEI1 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) +#define BOARD_BLDC_QEI_ADC_MATRIX_ADCX trgm_adc_matrix_output_to_qei1_adcx +#define BOARD_BLDC_QEI_ADC_MATRIX_ADCY trgm_adc_matrix_output_to_qei1_adcy + +/*Timer define*/ +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_RELOAD (100000U) + +/*adc*/ +#define BOARD_BLDC_ADC_MODULE (ADCX_MODULE_ADC16) +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (5U) +#define BOARD_BLDC_ADC_CH_V (6U) +#define BOARD_BLDC_ADC_CH_W (6U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES (40U) +#define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_PLB_COUNTER HPM_PLB +#define BOARD_PLB_PWM_BASE HPM_PWM0 +#define BOARD_PLB_PWM_CLOCK_NAME clock_mot0 +#define BOARD_PLB_TRGM HPM_TRGM0 +#define BOARD_PLB_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_CH8REF) +#define BOARD_PLB_IN_PWM_TRG_NUM (TRGM_TRGOCFG_PLB_IN_00) +#define BOARD_PLB_IN_PWM_PULSE_TRG_NUM (TRGM_TRGOCFG_PLB_IN_02) +#define BOARD_PLB_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLB_OUT00) +#define BOARD_PLB_IO_TRG_NUM (TRGM_TRGOCFG_MOT_GPIO2) +#define BOARD_PLB_IO_TRG_SHIFT (2) +#define BOARD_PLB_PWM_CMP (8U) +#define BOARD_PLB_PWM_CHN (8U) +#define BOARD_PLB_CHN plb_chn0 + +/* lin section */ +#define BOARD_LIN HPM_LIN3 +#define BOARD_LIN_CLK_NAME clock_lin3 +#define BOARD_LIN_IRQ IRQn_LIN3 +#define BOARD_LIN_BAUDRATE (19200U) + +/* QEO */ +#define BOARD_QEO HPM_QEO0 +#define BOARD_QEO_TRGM_POS trgm_pos_matrix_output_to_qeo0 + +/* moto */ +#define BOARD_MOTOR_CLK_NAME clock_mot0 + +/* SEI */ +#define BOARD_SEI HPM_SEI +#define BOARD_SEI_CTRL SEI_CTRL_1 +#define BOARD_SEI_IRQn IRQn_SEI1 + +/* USB */ +#define BOARD_USB HPM_USB0 + +/* OPAMP */ +#define BOARD_APP_OPAMP HPM_OPAMP0 + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR2 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr2 + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init_gpio_pins(void); +void board_init_led_pins(void); +void board_init_usb_pins(void); +void board_led_write(uint8_t state); +void board_led_toggle(void); +void board_init_uart(UART_Type *ptr); +uint32_t board_init_spi_clock(SPI_Type *ptr); +void board_init_spi_pins(SPI_Type *ptr); +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); +void board_init_adc16_pins(void); +uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); +void board_init_can(MCAN_Type *ptr); +uint32_t board_init_can_clock(MCAN_Type *ptr); +void board_init_rgb_pwm_pins(void); +void board_disable_output_rgb_led(uint8_t color); +void board_enable_output_rgb_led(uint8_t color); +void board_init_dac_pins(DAC_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_init_lin_pins(LINV2_Type *ptr); +uint32_t board_init_lin_clock(LINV2_Type *ptr); + +void board_init(void); +void board_init_usb_dp_dm_pins(void); +void board_init_clock(void); +void board_delay_us(uint32_t us); +void board_delay_ms(uint32_t ms); +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_ungate_mchtmr_at_lp_mode(void); + +uint8_t board_get_led_gpio_off_level(void); +uint8_t board_get_led_pwm_off_level(void); + +void board_init_pmp(void); + +uint32_t board_init_uart_clock(UART_Type *ptr); +void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); + +void board_init_i2c(I2C_Type *ptr); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/common/libraries/hpm_sdk/boards/hpm5300evk/pinmux.c b/common/libraries/hpm_sdk/boards/hpm5300evk/pinmux.c new file mode 100644 index 00000000..1af1ef9f --- /dev/null +++ b/common/libraries/hpm_sdk/boards/hpm5300evk/pinmux.c @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ +#include "board.h" +#include "pinmux.h" + +void init_xtal_pins(void) +{ + /* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */ + /* + * HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + * HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + */ +} + +void init_py_pins_as_pgpio(void) +{ + /* Set PY00-PY05 default function to PGPIO */ + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_PGPIO_Y_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_PGPIO_Y_01; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_PGPIO_Y_02; + HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = IOC_PY03_FUNC_CTL_PGPIO_Y_03; + HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = IOC_PY04_FUNC_CTL_PGPIO_Y_04; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_PGPIO_Y_05; +} + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD; + } else if (ptr == HPM_UART2) { + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_UART2_TXD; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_UART2_RXD; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART2_DE; + } else { + ; + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB02].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB03].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else if (ptr == HPM_I2C1) { + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB06].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB07].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else { + ; + } +} + +void init_gpio_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_SPI1_CS_1; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_SPI1_CS_0; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_GPIO_A_25; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; + } +} + + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + if (ptr == HPM_GPTMR0) { + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR0_COMP_0; + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1; + } +} + +void init_hall_trgm_pins(void) +{ + init_qeiv2_uvw_pins(HPM_QEI1); +} + +void init_qei_trgm_pins(void) +{ + init_qeiv2_ab_pins(HPM_QEI1); +} + +void init_butn_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; +} + +void init_acmp_pins(void) +{ + /* configure to ACMP_COMP_1(ALT16) function */ + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_ACMP_COMP_1; + /* configure to CMP1_INN4 function */ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_pwm_pins(PWM_Type *ptr) +{ + if (ptr == HPM_PWM0) { + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_PWM0_P_2; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_PWM0_P_3; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_PWM0_P_4; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_PWM0_P_5; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_PWM0_P_6; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_PWM0_P_7; + } +} + +void init_adc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC Test: ADC0.15/ADC1.15 */ + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_BUS: ADC0.14/ADC1.14 */ + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_A: ADC0.11/ADC1.11 */ + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_B: ADC0.1 /ADC1.1 */ + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_C: ADC0.2 /ADC1.2 */ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_D: ADC0.3 /ADC1.3 */ + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC0.4 /ADC1.4 */ + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */ + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.6 /ADC1.6 */ + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* Board ID: ADC0.7 /ADC1.7 */ +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */ + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.6 /ADC1.6 */ +} + +void init_usb_pins(void) +{ + /* Package QFN48 and LQFP64 should be set PA24 and PA25 pins as analog type to enable USB_P and USB_N. */ + /* + * HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + * HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + */ + + /* Package QFN32 should be set PA26 and PA27 pins as analog type to enable USB_P and USB_N. */ + /* + * HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + * HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + */ + + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID; + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC; + /* USB0_PWR */ + HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR; + + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_SOC_GPIO_Y_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_SOC_GPIO_Y_01; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_SOC_GPIO_Y_02; +} + +void init_can_pins(MCAN_Type *ptr) +{ + if (ptr == HPM_MCAN3) { + HPM_IOC->PAD[IOC_PAD_PY04].FUNC_CTL = IOC_PY04_FUNC_CTL_CAN3_RXD; + HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_CAN3_TXD; + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = IOC_PY04_FUNC_CTL_SOC_GPIO_Y_04; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_SOC_GPIO_Y_05; + } +} + +void init_led_pins_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_GPIO_A_23; +} + +void init_led_pins_as_pwm(void) +{ + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_TRGM0_P_03; +} + +void init_dac_pins(DAC_Type *ptr) +{ + if (ptr == HPM_DAC0) { + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC0.OUT */ + } else if (ptr == HPM_DAC1) { + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC1.OUT */ + } +} + +void init_lin_pins(LINV2_Type *ptr) +{ + /** enable open drain and pull up */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); + if (ptr == HPM_LIN3) { + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_LIN3_TREN; + HPM_IOC->PAD[IOC_PAD_PA13].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_LIN3_RXD; + HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_LIN3_TXD; + HPM_IOC->PAD[IOC_PAD_PA15].PAD_CTL = pad_ctl; + } + /* Enable 12V */ + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_GPIO_A_24; +} + +void init_plb_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TRGM0_P_02; +} + +void init_qeo_pins(QEO_Type *ptr) +{ + if (ptr == HPM_QEO0) { + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_QEO0_A; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_QEO0_B; + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_QEO0_Z; + } +} + +void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx) +{ + if (ptr == HPM_SEI) { + if (sei_ctrl_idx == SEI_CTRL_1) { + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_SEI1_DE; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_SEI1_CK; + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_SEI1_TX; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_SEI1_RX; + } + } +} + +void init_rdc_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_RDC0_EXC_P; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + +/*The GPIO is designed for debug */ +#ifdef RDC_SAMPLE_TEST_GPIO_OUTPUT + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_TRGM0_P_00; +#endif +} + +void init_qeiv2_uvw_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI1) { + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_QEI1_Z; + } +} + +void init_qeiv2_ab_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI1) { + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B; + } +} + +void init_qeiv2_abz_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI1) { + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_QEI1_Z; + } +} + +void init_opamp_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} diff --git a/common/libraries/hpm_sdk/boards/hpm5300evk/pinmux.h b/common/libraries/hpm_sdk/boards/hpm5300evk/pinmux.h new file mode 100644 index 00000000..e95f57bd --- /dev/null +++ b/common/libraries/hpm_sdk/boards/hpm5300evk/pinmux.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif +void init_xtal_pins(void); +void init_py_pins_as_pgpio(void); +void init_uart_pins(UART_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_hall_trgm_pins(void); +void init_qei_trgm_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_pwm_pins(PWM_Type *ptr); +void init_adc_pins(void); +void init_adc_bldc_pins(void); +void init_usb_pins(void); +void init_can_pins(MCAN_Type *ptr); +void init_dac_pins(DAC_Type *ptr); +void init_led_pins_as_gpio(void); +void init_led_pins_as_pwm(void); +void init_plb_pins(void); +void init_lin_pins(LINV2_Type *ptr); +void init_qeo_pins(QEO_Type *ptr); +void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); +void init_rdc_pin(void); +void init_qeiv2_uvw_pins(QEIV2_Type *ptr); +void init_qeiv2_ab_pins(QEIV2_Type *ptr); +void init_qeiv2_abz_pins(QEIV2_Type *ptr); +void init_opamp_pins(void); +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/common/libraries/hpm_sdk/boards/hpm6200evk/board.c b/common/libraries/hpm_sdk/boards/hpm6200evk/board.c index 86cfb9bc..18dd0991 100644 --- a/common/libraries/hpm_sdk/boards/hpm6200evk/board.c +++ b/common/libraries/hpm_sdk/boards/hpm6200evk/board.c @@ -120,13 +120,13 @@ void board_print_clock_freq(void) printf("==============================\n"); printf(" %s clock summary\n", BOARD_NAME); printf("==============================\n"); - printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0)); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1)); - printf("axi:\t\t %dHz\n", clock_get_frequency(clock_axi)); - printf("ahb:\t\t %dHz\n", clock_get_frequency(clock_ahb)); - printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0)); + printf("axi:\t\t %luHz\n", clock_get_frequency(clock_axi)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); - printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); printf("==============================\n"); } @@ -226,10 +226,62 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) void board_i2c_bus_clear(I2C_Type *ptr) { init_i2c_pins_as_gpio(ptr); + if (ptr == BOARD_APP_I2C_BASE) { + gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN); + gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN); + if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN)) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN)) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + + gpio_set_pin_output(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN); + while (1) { + for (uint32_t i = 0; i < 9; i++) { + gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 1); + board_delay_ms(10); + gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 0); + board_delay_ms(10); + } + board_delay_ms(100); + } + printf("I2C bus is cleared\n"); + } } void board_init_i2c(I2C_Type *ptr) { + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + if (ptr == NULL) { + return; + } + + board_i2c_bus_clear(ptr); + init_i2c_pins(ptr); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + /* Configure the I2C clock to 24MHz */ + clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); + while (1) { + } + } } uint32_t board_init_spi_clock(SPI_Type *ptr) @@ -256,6 +308,11 @@ uint32_t board_init_spi_clock(SPI_Type *ptr) return 0; } +void board_init_lin_pins(LIN_Type *ptr) +{ + init_lin_pins(ptr); +} + uint32_t board_init_lin_clock(LIN_Type *ptr) { if (ptr == HPM_LIN0) { @@ -480,67 +537,71 @@ void board_init_clock(void) /* Bump up DCDC voltage to 1275mv */ pcfg_dcdc_set_voltage(HPM_PCFG, 1275); - /* Configure CPU to 600MHz, AXI/AHB to 200MHz */ - sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clk_src_pll1_clk0, 1, 3, 3); /* Connect CAN2/CAN3 to pll0clk0*/ clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 1); clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 1); + /* Configure CPU to 600MHz, AXI/AHB to 200MHz */ + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk0, 1, 3, 3); /* Configure PLL1_CLK0 Post Divider to 1 */ pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 0); pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 600000000); clock_update_core_clock(); - /* Configure AHB to 200MHz */ - clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); - /* Configure mchtmr to 24MHz */ clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); } -uint32_t board_init_adc12_clock(ADC16_Type *ptr) +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) { uint32_t freq = 0; - switch ((uint32_t)ptr) { - case HPM_ADC0_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk0, 2U); + } + freq = clock_get_frequency(clock_adc0); - break; - case HPM_ADC1_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll0_clk0, 2U); + } + freq = clock_get_frequency(clock_adc1); - break; - case HPM_ADC2_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll0_clk0, 2U); + } + freq = clock_get_frequency(clock_adc2); - break; - default: - /* Invalid ADC instance */ - break; } return freq; } -uint32_t board_init_adc16_clock(ADC16_Type *ptr) -{ - return 0; -} - uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) { uint32_t freq = 0; if (ptr == HPM_DAC0) { if (clk_src_ahb == true) { - /* Configure the DAC clock to 133MHz */ + /* Configure the DAC clock to 200MHz */ clock_set_dac_source(clock_dac0, clk_dac_src_ahb0); } else { /* Configure the DAC clock to 166MHz */ @@ -549,6 +610,17 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) } freq = clock_get_frequency(clock_dac0); + } else if (ptr == HPM_DAC1) { + if (clk_src_ahb == true) { + /* Configure the DAC clock to 200MHz */ + clock_set_dac_source(clock_dac1, clk_dac_src_ahb0); + } else { + /* Configure the DAC clock to 166MHz */ + clock_set_dac_source(clock_dac1, clk_dac_src_ana4); + clock_set_source_divider(clock_ana4, clk_src_pll0_clk1, 2); + } + + freq = clock_get_frequency(clock_dac1); } return freq; diff --git a/common/libraries/hpm_sdk/boards/hpm6200evk/board.h b/common/libraries/hpm_sdk/boards/hpm6200evk/board.h index 2156b245..d9421cf4 100644 --- a/common/libraries/hpm_sdk/boards/hpm6200evk/board.h +++ b/common/libraries/hpm_sdk/boards/hpm6200evk/board.h @@ -38,7 +38,7 @@ #define BOARD_APP_UART_IRQ IRQn_UART0 #else #ifndef BOARD_APP_UART_IRQ -#warning no IRQ specified for applicaiton uart +#warning no IRQ specified for application uart #endif #endif @@ -101,6 +101,11 @@ #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX #define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 #define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_I2C_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2C_SCL_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_I2C_SCL_GPIO_PIN 22 +#define BOARD_I2C_SDA_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_I2C_SDA_GPIO_PIN 23 /* ACMP desction */ #define BOARD_ACMP HPM_ACMP @@ -131,18 +136,6 @@ #define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 #define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr2 - -#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL -#define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX -#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN - -#define BOARD_LED_OFF_LEVEL 0 -#define BOARD_LED_ON_LEVEL !BOARD_LED_OFF_LEVEL -#define BOARD_LED_TOGGLE_RGB 1 - -#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ -#define BOARD_APP_GPIO_PIN 2 - /* pinmux section */ #define USING_GPIO0_FOR_GPIOZ #ifndef USING_GPIO0_FOR_GPIOZ @@ -166,9 +159,7 @@ #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) #define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX -#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX -#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1 #define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 #define BOARD_SPI_CS_PIN IOC_PAD_PB02 #define BOARD_SPI_CS_ACTIVE_LEVEL (0U) @@ -183,15 +174,24 @@ #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) /* ADC section */ -#define BOARD_APP_ADC16_NAME "ADC0" -#define BOARD_APP_ADC16_BASE HPM_ADC0 -#define BOARD_APP_ADC16_IRQn IRQn_ADC0 -#define BOARD_APP_ADC16_CH_1 (1U) +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (1U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A /* DAC section */ -#define BOARD_DAC_BASE HPM_DAC0 -#define BOARD_DAC_IRQn IRQn_DAC0 -#define BOARD_DAC_CLOCK_NAME clock_dac0 +#define BOARD_DAC_BASE HPM_DAC0 +#define BOARD_DAC_IRQn IRQn_DAC0 +#define BOARD_APP_DAC_CLOCK_NAME clock_dac0 /* CAN section */ #define BOARD_APP_CAN_BASE HPM_MCAN0 @@ -324,6 +324,18 @@ #define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB #define BOARD_B_GPIO_PIN 19 +#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL +#define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX +#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN + +#define BOARD_LED_OFF_LEVEL 0 +#define BOARD_LED_ON_LEVEL !BOARD_LED_OFF_LEVEL +#define BOARD_LED_TOGGLE_RGB 1 + +/* Key Section */ +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ +#define BOARD_APP_GPIO_PIN 2 + /* RGB LED Section */ #define BOARD_RED_PWM_IRQ IRQn_PWM3 #define BOARD_RED_PWM HPM_PWM3 @@ -460,6 +472,12 @@ #define BOARD_SHOW_BANNER 1 #endif +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR1 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr1 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -493,9 +511,10 @@ void board_init_clock(void); uint32_t board_init_spi_clock(SPI_Type *ptr); +void board_init_lin_pins(LIN_Type *ptr); uint32_t board_init_lin_clock(LIN_Type *ptr); -uint32_t board_init_adc16_clock(ADC16_Type *ptr); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); diff --git a/common/libraries/hpm_sdk/boards/hpm6300evk/board.c b/common/libraries/hpm_sdk/boards/hpm6300evk/board.c index 471b2232..927158ba 100644 --- a/common/libraries/hpm_sdk/boards/hpm6300evk/board.c +++ b/common/libraries/hpm_sdk/boards/hpm6300evk/board.c @@ -234,10 +234,62 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) void board_i2c_bus_clear(I2C_Type *ptr) { init_i2c_pins_as_gpio(ptr); + if (ptr == BOARD_APP_I2C_BASE) { + gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN); + gpio_set_pin_input(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN); + if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN)) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (!gpio_read_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SDA_GPIO_INDEX, BOARD_I2C_SDA_GPIO_PIN)) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + + gpio_set_pin_output(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN); + while (1) { + for (uint32_t i = 0; i < 9; i++) { + gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 1); + board_delay_ms(10); + gpio_write_pin(BOARD_I2C_GPIO_CTRL, BOARD_I2C_SCL_GPIO_INDEX, BOARD_I2C_SCL_GPIO_PIN, 0); + board_delay_ms(10); + } + board_delay_ms(100); + } + printf("I2C bus is cleared\n"); + } } void board_init_i2c(I2C_Type *ptr) { + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + if (ptr == NULL) { + return; + } + + board_i2c_bus_clear(ptr); + init_i2c_pins(ptr); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + /* Configure the I2C clock to 24MHz */ + clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); + while (1) { + } + } } uint32_t board_init_spi_clock(SPI_Type *ptr) @@ -419,55 +471,17 @@ void board_init_clock(void) /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); - /* - * Configure CPU0 to 480MHz - * - * NOTE: The PLL2 is disabled by default, and it will be enabled automatically if - * it is required by any nodes. - * Here the PLl2 clock is enabled after switching CPU clock source to it - */ - clock_set_source_divider(clock_cpu0, clk_src_pll1_clk0, 1); + + /* Configure CPU to 480MHz, AXI/AHB to 160MHz */ + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk0, 1, 3, 3); /* Configure PLL1_CLK0 Post Divider to 1.2 */ pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 1); - /* Configure PLL1 clock frequencey to 576MHz, the PLL1_CLK0 frequency =- 576MHz / 1.2 = 480MHz */ + /* Configure PLL1 clock frequencey to 576MHz, the PLL1_CLK0 frequency = 576MHz / 1.2 = 480MHz */ pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 576000000); - clock_update_core_clock(); - /* Configure AHB to 200MHz */ - clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); - - clock_set_source_divider(clock_aud1, clk_src_pll2_clk0, 46); /* config clock_aud1 for 44100*n sample rate */ -} - -uint32_t board_init_adc12_clock(ADC16_Type *ptr) -{ - uint32_t freq = 0; - switch ((uint32_t) ptr) { - case HPM_ADC0_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc0); - break; - case HPM_ADC1_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc1); - break; - case HPM_ADC2_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc2); - break; - default: - /* Invalid ADC instance */ - break; - } - - return freq; + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); } uint32_t board_init_dao_clock(void) @@ -490,9 +504,46 @@ uint32_t board_init_i2s_clock(I2S_Type *ptr) return 0; } -uint32_t board_init_adc16_clock(ADC16_Type *ptr) +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) { - return 0; + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@160MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk1 divided by 2 (@166MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk1, 2U); + } + + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@160MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@166MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll0_clk1, 2U); + } + + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@160MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@166MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll0_clk1, 2U); + } + + freq = clock_get_frequency(clock_adc2); + } + + return freq; } uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) @@ -502,10 +553,10 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) if (ptr == HPM_DAC) { if (clk_src_ahb == true) { /* Configure the DAC clock to 160MHz */ - clock_set_dac_source(clock_dac0, clk_dac_src_ahb); + clock_set_dac_source(clock_dac0, clk_dac_src_ahb0); } else { /* Configure the DAC clock to 166MHz */ - clock_set_dac_source(clock_dac0, clk_dac_src_ana); + clock_set_dac_source(clock_dac0, clk_dac_src_ana3); clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2); } diff --git a/common/libraries/hpm_sdk/boards/hpm6300evk/board.h b/common/libraries/hpm_sdk/boards/hpm6300evk/board.h index 34768fb4..46ad149a 100644 --- a/common/libraries/hpm_sdk/boards/hpm6300evk/board.h +++ b/common/libraries/hpm_sdk/boards/hpm6300evk/board.h @@ -36,7 +36,7 @@ #define BOARD_APP_UART_IRQ IRQn_UART0 #else #ifndef BOARD_APP_UART_IRQ -#warning no IRQ specified for applicaiton uart +#warning no IRQ specified for application uart #endif #endif @@ -118,6 +118,11 @@ #define BOARD_APP_I2C_DMA HPM_HDMA #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX #define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 +#define BOARD_I2C_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2C_SCL_GPIO_INDEX GPIO_DO_GPIOC +#define BOARD_I2C_SCL_GPIO_PIN 13 +#define BOARD_I2C_SDA_GPIO_INDEX GPIO_DO_GPIOC +#define BOARD_I2C_SDA_GPIO_PIN 14 /* ACMP desction */ #define BOARD_ACMP HPM_ACMP @@ -205,17 +210,27 @@ #define BOARD_ENET_RMII HPM_ENET0 #define BOARD_ENET_RMII_INT_REF_CLK (1U) #define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp0) +#define BOARD_ENET_RMII_PPS0_PINOUT (1) /* ADC section */ -#define BOARD_APP_ADC16_NAME "ADC0" -#define BOARD_APP_ADC16_BASE HPM_ADC0 -#define BOARD_APP_ADC16_IRQn IRQn_ADC0 -#define BOARD_APP_ADC16_CH_1 (13U) +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (13U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A /* DAC section */ -#define BOARD_DAC_BASE HPM_DAC -#define BOARD_DAC_IRQn IRQn_DAC -#define BOARD_DAC_CLOCK_NAME clock_dac0 +#define BOARD_DAC_BASE HPM_DAC +#define BOARD_DAC_IRQn IRQn_DAC +#define BOARD_APP_DAC_CLOCK_NAME clock_dac0 /* CAN section */ #define BOARD_APP_CAN_BASE HPM_CAN1 @@ -343,6 +358,12 @@ #define BOARD_SHOW_BANNER 1 #endif +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR1 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr1 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -374,7 +395,7 @@ void board_init_clock(void); uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc16_clock(ADC16_Type *ptr); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk/board.c b/common/libraries/hpm_sdk/boards/hpm6750evk/board.c index 0bf702d2..22df7b83 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evk/board.c +++ b/common/libraries/hpm_sdk/boards/hpm6750evk/board.c @@ -20,6 +20,7 @@ #include "hpm_trgm_drv.h" #include "hpm_pllctl_drv.h" #include "hpm_enet_drv.h" +#include "hpm_enet_phy_common.h" #include "hpm_pcfg_drv.h" #include "hpm_sdk_version.h" @@ -253,6 +254,11 @@ void board_power_cycle_lcd(void) } +void board_lcd_backlight(bool is_on) +{ + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, is_on); +} + void board_init_lcd(void) { board_init_lcd_clock(); @@ -479,6 +485,7 @@ uint8_t board_get_led_gpio_off_level(void) void board_init_led_pins(void) { + board_turnoff_rgb_led(); init_led_pins_as_gpio(); gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level()); gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level()); @@ -675,6 +682,7 @@ void board_init_clock(void) /* Bump up DCDC voltage to 1200mv */ pcfg_dcdc_set_voltage(HPM_PCFG, 1200); + pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); @@ -687,8 +695,6 @@ void board_init_clock(void) clock_update_core_clock(); clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/ - - clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 44100*n sample rate */ clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); } @@ -714,48 +720,18 @@ uint32_t board_init_lcd_clock(void) { uint32_t freq; clock_add_to_group(clock_display, 0); - /* Configure LCDC clock to 29.7MHz */ - clock_set_source_divider(clock_display, clock_source_pll4_clk0, 20U); + /* Configure LCDC clock to 59.4MHz */ + clock_set_source_divider(clock_display, clock_source_pll4_clk0, 10U); freq = clock_get_frequency(clock_display); return freq; } -uint32_t board_init_adc12_clock(ADC12_Type *ptr) -{ - uint32_t freq = 0; - switch ((uint32_t) ptr) { - case HPM_ADC0_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc0); - break; - case HPM_ADC1_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc1); - break; - case HPM_ADC2_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc2); - break; - default: - /* Invalid ADC instance */ - break; - } - - return freq; -} - uint32_t board_init_dao_clock(void) { clock_add_to_group(clock_dao, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk); + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); return clock_get_frequency(clock_dao); } @@ -782,42 +758,112 @@ void board_init_i2s_pins(I2S_Type *ptr) uint32_t board_init_i2s_clock(I2S_Type *ptr) { + uint32_t freq = 0; + if (ptr == HPM_I2S0) { clock_add_to_group(clock_i2s0, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, BOARD_APP_AUDIO_CLK_SRC, 25); + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); - return clock_get_frequency(clock_i2s0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); + + freq = clock_get_frequency(clock_i2s1); + } else { + ; } - return 0; + + return freq; } /* adjust I2S source clock base on sample rate */ uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) { + uint32_t freq = 0; + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); if ((sample_rate % 22050) == 0) { - clock_add_to_group(clock_i2s0, 0); - clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ - clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud1); + clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ } else { - clock_add_to_group(clock_i2s0, 0); clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */ - clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); } - return clock_get_frequency(clock_i2s0); + clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */ + } + clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1); + freq = clock_get_frequency(clock_i2s1); + } else { + ; } - return 0; + + return freq; +} + +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc2); + } + + return freq; } -uint32_t board_init_adc16_clock(ADC16_Type *ptr) +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) { uint32_t freq = 0; + if (ptr == HPM_ADC3) { - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc3, clk_adc_src_ana1); - clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc3); } @@ -1074,7 +1120,7 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { /* Configure Enet clock to output reference clock */ - if (ptr == HPM_ENET0 || ptr == HPM_ENET1) { + if (ptr == HPM_ENET1) { if (internal) { /* set pll output frequency at 1GHz */ if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) { @@ -1097,7 +1143,11 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) { - return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); + if (ptr == HPM_ENET0) { + return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); + } + + return status_invalid_argument; } void board_init_adc12_pins(void) @@ -1178,6 +1228,95 @@ void board_init_enet_pps_pins(ENET_Type *ptr) init_enet_pps_pins(); } +#if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT + +hpm_stat_t board_init_multiple_enet_pins(void) +{ + board_init_enet_pins(HPM_ENET0); + board_init_enet_pins(HPM_ENET1); + + return status_success; +} + +hpm_stat_t board_init_multiple_enet_clock(void) +{ + /* Set RGMII clock delay */ + board_init_enet_rgmii_clock_delay(HPM_ENET0); + + /* Set RMII reference clock */ + board_init_enet_rmii_reference_clock(HPM_ENET1, BOARD_ENET_RMII_INT_REF_CLK); + printf("Enet1 Reference Clock: %s\n", BOARD_ENET_RMII_INT_REF_CLK ? "Internal Clock" : "External Clock"); + + return status_success; +} + +hpm_stat_t board_reset_multiple_enet_phy(void) +{ + board_reset_enet_phy(HPM_ENET0); + board_reset_enet_phy(HPM_ENET1); + + return status_success; +} + +hpm_stat_t board_init_enet_phy(ENET_Type *ptr) +{ + dp83867_config_t phy_config0; + dp83848_config_t phy_config1; + + if (ptr == HPM_ENET0) { + dp83867_reset(HPM_ENET0); + #if __DISABLE_AUTO_NEGO + dp83867_set_mdi_crossover_mode(HPM_ENET0, enet_phy_mdi_crossover_manual_mdix); + #endif + dp83867_basic_mode_default_config(HPM_ENET0, &phy_config0); + if (dp83867_basic_mode_init(HPM_ENET0, &phy_config0) == true) { + return status_success; + } else { + printf("Enet0 phy init failed!\n"); + return status_fail; + } + } else if (ptr == HPM_ENET1) { + dp83848_reset(HPM_ENET1); + dp83848_basic_mode_default_config(HPM_ENET1, &phy_config1); + if (dp83848_basic_mode_init(HPM_ENET1, &phy_config1) == true) { + return status_success; + } else { + printf("Enet1 phy init failed!\n"); + return status_fail; + } + } else { + return status_invalid_argument; + } +} + +ENET_Type *board_get_enet_base(uint8_t idx) +{ + if (idx == 0) { + return HPM_ENET0; + } else { + return HPM_ENET1; + } +} + +uint8_t board_get_enet_phy_itf(uint8_t idx) +{ + if (idx == 0) { + return BOARD_ENET_RGMII_PHY_ITF; + } else { + return BOARD_ENET_RMII_PHY_ITF; + } +} + +void board_get_enet_phy_status(uint8_t idx, void *status) +{ + if (idx == 0) { + dp83867_get_phy_status(HPM_ENET0, status); + } else { + dp83848_get_phy_status(HPM_ENET1, status); + } +} +#endif + void board_init_dao_pins(void) { init_dao_pins(); diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk/board.h b/common/libraries/hpm_sdk/boards/hpm6750evk/board.h index af0c92da..a42f2e59 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evk/board.h +++ b/common/libraries/hpm_sdk/boards/hpm6750evk/board.h @@ -33,7 +33,7 @@ #define BOARD_APP_UART_IRQ IRQn_UART0 #else #ifndef BOARD_APP_UART_IRQ -#warning no IRQ specified for applicaiton uart +#warning no IRQ specified for application uart #endif #endif @@ -301,10 +301,12 @@ #define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 /* enet section */ +#define BOARD_ENET_COUNT (2U) #define BOARD_ENET_PPS HPM_ENET0 #define BOARD_ENET_PPS_IDX enet_pps_0 #define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 +#define BOARD_ENET_RGMII_PHY_ITF enet_inf_rgmii #define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 #define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF #define BOARD_ENET_RGMII_RST_GPIO_PIN (0U) @@ -312,26 +314,46 @@ #define BOARD_ENET_RGMII_TX_DLY (0U) #define BOARD_ENET_RGMII_RX_DLY (23U) #define BOARD_ENET_RGMII_PTP_CLOCK clock_ptp0 +#define BOARD_ENET_RGMII_PPS0_PINOUT (1) +#define BOARD_ENET_RMII_PHY_ITF enet_inf_rmii #define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 #define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOE #define BOARD_ENET_RMII_RST_GPIO_PIN (26U) #define BOARD_ENET_RMII HPM_ENET1 #define BOARD_ENET_RMII_INT_REF_CLK (1U) #define BOARD_ENET_RMII_PTP_CLOCK clock_ptp1 +#define BOARD_ENET_RMII_PPS0_PINOUT (0) /* ADC section */ -#define BOARD_APP_ADC12_NAME "ADC0" -#define BOARD_APP_ADC12_BASE HPM_ADC0 -#define BOARD_APP_ADC12_IRQn IRQn_ADC0 -#define BOARD_APP_ADC12_CH_1 (11U) -#define BOARD_APP_ADC12_CH_2 (10U) -#define BOARD_APP_ADC12_CH_3 (7U) - -#define BOARD_APP_ADC16_NAME "ADC3" -#define BOARD_APP_ADC16_BASE HPM_ADC3 -#define BOARD_APP_ADC16_IRQn IRQn_ADC3 -#define BOARD_APP_ADC16_CH_1 (2U) +#define BOARD_APP_ADC12_NAME "ADC0" +#define BOARD_APP_ADC12_BASE HPM_ADC0 +#define BOARD_APP_ADC12_IRQn IRQn_ADC0 +#define BOARD_APP_ADC12_CH_1 (11U) +#define BOARD_APP_ADC12_CH_2 (10U) +#define BOARD_APP_ADC12_CH_3 (7U) +#define BOARD_APP_ADC12_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_NAME "ADC3" +#define BOARD_APP_ADC16_BASE HPM_ADC3 +#define BOARD_APP_ADC16_IRQn IRQn_ADC3 +#define BOARD_APP_ADC16_CH_1 (2U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc3) + +#define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A /* CAN section */ #define BOARD_APP_CAN_BASE HPM_CAN0 @@ -501,6 +523,12 @@ #define BOARD_SHOW_BANNER 1 #endif +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR4 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR4 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr4 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -513,6 +541,7 @@ void board_init_console(void); void board_init_uart(UART_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); +void board_lcd_backlight(bool is_on); void board_panel_para_to_lcdc(lcdc_config_t *config); void board_init_can(CAN_Type *ptr); @@ -550,9 +579,9 @@ uint32_t board_init_lcd_clock(void); uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc12_clock(ADC12_Type *ptr); +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); -uint32_t board_init_adc16_clock(ADC16_Type *ptr); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); uint32_t board_init_can_clock(CAN_Type *ptr); @@ -587,6 +616,16 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); +#if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT +hpm_stat_t board_init_multiple_enet_pins(void); +hpm_stat_t board_init_multiple_enet_clock(void); +hpm_stat_t board_reset_multiple_enet_phy(void); +hpm_stat_t board_init_enet_phy(ENET_Type *ptr); +ENET_Type *board_get_enet_base(uint8_t idx); +uint8_t board_get_enet_phy_itf(uint8_t idx); +void board_get_enet_phy_status(uint8_t idx, void *status); +#endif + /* * @brief Initialize PMP and PMA for but not limited to the following purposes: * -- non-cacheable memory initialization diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk2/board.c b/common/libraries/hpm_sdk/boards/hpm6750evk2/board.c index cb9907be..14f09e7e 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evk2/board.c +++ b/common/libraries/hpm_sdk/boards/hpm6750evk2/board.c @@ -20,6 +20,7 @@ #include "hpm_trgm_drv.h" #include "hpm_pllctl_drv.h" #include "hpm_enet_drv.h" +#include "hpm_enet_phy_common.h" #include "hpm_pcfg_drv.h" #include "hpm_sdk_version.h" @@ -123,22 +124,22 @@ void board_print_clock_freq(void) printf("==============================\n"); printf(" %s clock summary\n", BOARD_NAME); printf("==============================\n"); - printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0)); - printf("cpu1:\t\t %dHz\n", clock_get_frequency(clock_cpu1)); - printf("axi0:\t\t %dHz\n", clock_get_frequency(clock_axi0)); - printf("axi1:\t\t %dHz\n", clock_get_frequency(clock_axi1)); - printf("axi2:\t\t %dHz\n", clock_get_frequency(clock_axi2)); - printf("ahb:\t\t %dHz\n", clock_get_frequency(clock_ahb)); - printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0)); - printf("mchtmr1:\t %dHz\n", clock_get_frequency(clock_mchtmr1)); - printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0)); - printf("xpi1:\t\t %dHz\n", clock_get_frequency(clock_xpi1)); - printf("femc:\t\t %dHz\n", clock_get_frequency(clock_femc)); - printf("display:\t %dHz\n", clock_get_frequency(clock_display)); - printf("cam0:\t\t %dHz\n", clock_get_frequency(clock_camera0)); - printf("cam1:\t\t %dHz\n", clock_get_frequency(clock_camera1)); - printf("jpeg:\t\t %dHz\n", clock_get_frequency(clock_jpeg)); - printf("pdma:\t\t %dHz\n", clock_get_frequency(clock_pdma)); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); + printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1)); + printf("axi0:\t\t %luHz\n", clock_get_frequency(clock_axi0)); + printf("axi1:\t\t %luHz\n", clock_get_frequency(clock_axi1)); + printf("axi2:\t\t %luHz\n", clock_get_frequency(clock_axi2)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); + printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); + printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); + printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); + printf("display:\t %luHz\n", clock_get_frequency(clock_display)); + printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); + printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); + printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg)); + printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma)); printf("==============================\n"); } @@ -235,6 +236,11 @@ void board_power_cycle_lcd(void) } +void board_lcd_backlight(bool is_on) +{ + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, is_on); +} + void board_init_lcd(void) { board_init_lcd_clock(); @@ -356,7 +362,7 @@ void board_init_i2c(I2C_Type *ptr) freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME); stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); if (stat != status_success) { - printf("failed to initialize i2c 0x%x\n", (uint32_t)BOARD_CAP_I2C_BASE); + printf("failed to initialize i2c 0x%lx\n", (uint32_t)BOARD_CAP_I2C_BASE); while (1) { } } @@ -449,6 +455,7 @@ uint8_t board_get_led_gpio_off_level(void) void board_init_led_pins(void) { + board_turnoff_rgb_led(); init_led_pins_as_gpio(); gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level()); gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level()); @@ -645,6 +652,7 @@ void board_init_clock(void) /* Bump up DCDC voltage to 1200mv */ pcfg_dcdc_set_voltage(HPM_PCFG, 1200); + pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); @@ -657,8 +665,6 @@ void board_init_clock(void) clock_update_core_clock(); clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/ - - clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 44100*n sample rate */ clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); } @@ -690,42 +696,12 @@ uint32_t board_init_lcd_clock(void) return freq; } -uint32_t board_init_adc12_clock(ADC12_Type *ptr) -{ - uint32_t freq = 0; - switch ((uint32_t) ptr) { - case HPM_ADC0_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc0); - break; - case HPM_ADC1_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc1); - break; - case HPM_ADC2_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc2); - break; - default: - /* Invalid ADC instance */ - break; - } - - return freq; -} - uint32_t board_init_dao_clock(void) { clock_add_to_group(clock_dao, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk); + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); return clock_get_frequency(clock_dao); } @@ -752,42 +728,112 @@ void board_init_i2s_pins(I2S_Type *ptr) uint32_t board_init_i2s_clock(I2S_Type *ptr) { + uint32_t freq = 0; + if (ptr == HPM_I2S0) { clock_add_to_group(clock_i2s0, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, BOARD_APP_AUDIO_CLK_SRC, 25); + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); - return clock_get_frequency(clock_i2s0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); + + freq = clock_get_frequency(clock_i2s1); + } else { + ; } - return 0; + + return freq; } /* adjust I2S source clock base on sample rate */ uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) { + uint32_t freq = 0; + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); if ((sample_rate % 22050) == 0) { - clock_add_to_group(clock_i2s0, 0); - clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ - clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud1); + clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ } else { - clock_add_to_group(clock_i2s0, 0); clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */ - clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); } - return clock_get_frequency(clock_i2s0); + clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */ + } + clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1); + freq = clock_get_frequency(clock_i2s1); + } else { + ; } - return 0; + + return freq; +} + +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc2); + } + + return freq; } -uint32_t board_init_adc16_clock(ADC16_Type *ptr) +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) { uint32_t freq = 0; + if (ptr == HPM_ADC3) { - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc3, clk_adc_src_ana1); - clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc3); } @@ -1055,7 +1101,7 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { /* Configure Enet clock to output reference clock */ - if (ptr == HPM_ENET0 || ptr == HPM_ENET1) { + if (ptr == HPM_ENET1) { if (internal) { /* set pll output frequency at 1GHz */ if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) { @@ -1078,7 +1124,11 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) { - return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); + if (ptr == HPM_ENET0) { + return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); + } + + return status_invalid_argument; } void board_init_adc12_pins(void) @@ -1159,6 +1209,92 @@ void board_init_enet_pps_pins(ENET_Type *ptr) init_enet_pps_pins(); } +#if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT + +hpm_stat_t board_init_multiple_enet_pins(void) +{ + board_init_enet_pins(HPM_ENET0); + board_init_enet_pins(HPM_ENET1); + + return status_success; +} + +hpm_stat_t board_init_multiple_enet_clock(void) +{ + /* Set RGMII clock delay */ + board_init_enet_rgmii_clock_delay(HPM_ENET0); + + /* Set RMII reference clock */ + board_init_enet_rmii_reference_clock(HPM_ENET1, BOARD_ENET_RMII_INT_REF_CLK); + printf("Enet1 Reference Clock: %s\n", BOARD_ENET_RMII_INT_REF_CLK ? "Internal Clock" : "External Clock"); + + return status_success; +} + +hpm_stat_t board_reset_multiple_enet_phy(void) +{ + board_reset_enet_phy(HPM_ENET0); + board_reset_enet_phy(HPM_ENET1); + + return status_success; +} + +hpm_stat_t board_init_enet_phy(ENET_Type *ptr) +{ + rtl8211_config_t phy_config0; + rtl8201_config_t phy_config1; + + if (ptr == HPM_ENET0) { + rtl8211_reset(ptr); + rtl8211_basic_mode_default_config(HPM_ENET0, &phy_config0); + if (rtl8211_basic_mode_init(HPM_ENET0, &phy_config0) == true) { + return status_success; + } else { + printf("Enet0 phy init failed!\n"); + return status_fail; + } + } else if (ptr == HPM_ENET1) { + rtl8201_reset(HPM_ENET1); + rtl8201_basic_mode_default_config(HPM_ENET1, &phy_config1); + if (rtl8201_basic_mode_init(HPM_ENET1, &phy_config1) == true) { + return status_success; + } else { + printf("Enet1 phy init failed!\n"); + return status_fail; + } + } else { + return status_invalid_argument; + } +} + +ENET_Type *board_get_enet_base(uint8_t idx) +{ + if (idx == 0) { + return HPM_ENET0; + } else { + return HPM_ENET1; + } +} + +uint8_t board_get_enet_phy_itf(uint8_t idx) +{ + if (idx == 0) { + return BOARD_ENET_RGMII_PHY_ITF; + } else { + return BOARD_ENET_RMII_PHY_ITF; + } +} + +void board_get_enet_phy_status(uint8_t idx, void *status) +{ + if (idx == 0) { + rtl8211_get_phy_status(HPM_ENET0, status); + } else { + rtl8201_get_phy_status(HPM_ENET1, status); + } +} +#endif + void board_init_dao_pins(void) { init_dao_pins(); diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk2/board.h b/common/libraries/hpm_sdk/boards/hpm6750evk2/board.h index aefc269d..f1823bbf 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evk2/board.h +++ b/common/libraries/hpm_sdk/boards/hpm6750evk2/board.h @@ -33,7 +33,7 @@ #define BOARD_APP_UART_IRQ IRQn_UART0 #else #ifndef BOARD_APP_UART_IRQ -#warning no IRQ specified for applicaiton uart +#warning no IRQ specified for application uart #endif #endif @@ -304,36 +304,59 @@ #define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 /* enet section */ +#define BOARD_ENET_COUNT (2U) +#define BOARD_ENET_PPS HPM_ENET0 +#define BOARD_ENET_PPS_IDX enet_pps_0 +#define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 + +#define BOARD_ENET_RGMII_PHY_ITF enet_inf_rgmii #define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 #define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF #define BOARD_ENET_RGMII_RST_GPIO_PIN (0U) #define BOARD_ENET_RGMII HPM_ENET0 #define BOARD_ENET_RGMII_TX_DLY (0U) #define BOARD_ENET_RGMII_RX_DLY (7U) - #define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0) +#define BOARD_ENET_RGMII_PPS0_PINOUT (1) - +#define BOARD_ENET_RMII_PHY_ITF enet_inf_rmii #define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 #define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOE #define BOARD_ENET_RMII_RST_GPIO_PIN (26U) #define BOARD_ENET_RMII HPM_ENET1 #define BOARD_ENET_RMII_INT_REF_CLK (1U) - #define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp1) +#define BOARD_ENET_RMII_PPS0_PINOUT (0) /* ADC section */ -#define BOARD_APP_ADC12_NAME "ADC0" -#define BOARD_APP_ADC12_BASE HPM_ADC0 -#define BOARD_APP_ADC12_IRQn IRQn_ADC0 -#define BOARD_APP_ADC12_CH_1 (11U) -#define BOARD_APP_ADC12_CH_2 (10U) -#define BOARD_APP_ADC12_CH_3 (7U) - -#define BOARD_APP_ADC16_NAME "ADC3" -#define BOARD_APP_ADC16_BASE HPM_ADC3 -#define BOARD_APP_ADC16_IRQn IRQn_ADC3 -#define BOARD_APP_ADC16_CH_1 (2U) +#define BOARD_APP_ADC12_NAME "ADC0" +#define BOARD_APP_ADC12_BASE HPM_ADC0 +#define BOARD_APP_ADC12_IRQn IRQn_ADC0 +#define BOARD_APP_ADC12_CH_1 (11U) +#define BOARD_APP_ADC12_CH_2 (10U) +#define BOARD_APP_ADC12_CH_3 (7U) +#define BOARD_APP_ADC12_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_NAME "ADC3" +#define BOARD_APP_ADC16_BASE HPM_ADC3 +#define BOARD_APP_ADC16_IRQn IRQn_ADC3 +#define BOARD_APP_ADC16_CH_1 (2U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc3) + +#define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A /* CAN section */ #define BOARD_APP_CAN_BASE HPM_CAN0 @@ -506,6 +529,12 @@ #define BOARD_SHOW_BANNER 1 #endif +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR6 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR6 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr6 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -518,6 +547,7 @@ void board_init_console(void); void board_init_uart(UART_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); +void board_lcd_backlight(bool is_on); void board_panel_para_to_lcdc(lcdc_config_t *config); void board_init_can(CAN_Type *ptr); @@ -555,9 +585,9 @@ uint32_t board_init_lcd_clock(void); uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc12_clock(ADC12_Type *ptr); +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); -uint32_t board_init_adc16_clock(ADC16_Type *ptr); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); uint32_t board_init_can_clock(CAN_Type *ptr); @@ -592,6 +622,16 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); +#if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT +hpm_stat_t board_init_multiple_enet_pins(void); +hpm_stat_t board_init_multiple_enet_clock(void); +hpm_stat_t board_reset_multiple_enet_phy(void); +hpm_stat_t board_init_enet_phy(ENET_Type *ptr); +ENET_Type *board_get_enet_base(uint8_t idx); +uint8_t board_get_enet_phy_itf(uint8_t idx); +void board_get_enet_phy_status(uint8_t idx, void *status); +#endif + /* * @brief Initialize PMP and PMA for but not limited to the following purposes: * -- non-cacheable memory initialization diff --git a/common/libraries/hpm_sdk/boards/hpm6750evk2/pinmux.c b/common/libraries/hpm_sdk/boards/hpm6750evk2/pinmux.c index 9882f1e4..9cc28fae 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evk2/pinmux.c +++ b/common/libraries/hpm_sdk/boards/hpm6750evk2/pinmux.c @@ -21,8 +21,8 @@ void init_uart_pins(UART_Type *ptr) HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; /* PY port IO needs to configure PIOC as well */ - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; } else if (ptr == HPM_UART2) { HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_UART2_TXD; HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_UART2_RXD; diff --git a/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.c b/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.c index 42228c5d..ffb5cde4 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.c +++ b/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.c @@ -203,7 +203,11 @@ static void board_turnoff_rgb_led(void) uint8_t board_get_led_pwm_off_level(void) { - return BOARD_LED_OFF_LEVEL; + if (invert_led_level) { + return BOARD_LED_ON_LEVEL; + } else { + return BOARD_LED_OFF_LEVEL; + } } uint8_t board_get_led_gpio_off_level(void) @@ -264,6 +268,10 @@ void board_power_cycle_lcd(void) gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, 1); } +void board_lcd_backlight(bool is_on) +{ + gpio_write_pin(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN, is_on); +} void board_init_lcd(void) { @@ -473,6 +481,7 @@ void board_write_spi_cs(uint32_t pin, uint8_t state) void board_init_led_pins(void) { + board_turnoff_rgb_led(); init_led_pins_as_gpio(); gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level()); gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level()); @@ -482,7 +491,7 @@ void board_init_led_pins(void) void board_led_toggle(void) { static uint8_t i; - if (BOARD_LED_PULL_STATUS) { + if (!invert_led_level) { /* hpm6750 Mini Rev A led configure*/ gpio_write_port(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, (7 & ~(1 << i)) << BOARD_G_GPIO_PIN); } else { @@ -661,6 +670,7 @@ void board_init_clock(void) /* Bump up DCDC voltage to 1200mv */ pcfg_dcdc_set_voltage(HPM_PCFG, 1200); + pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); @@ -673,8 +683,6 @@ void board_init_clock(void) clock_update_core_clock(); clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2); /*200m hz*/ - - clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 44100*n sample rate */ clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); } @@ -706,42 +714,12 @@ uint32_t board_init_lcd_clock(void) return freq; } -uint32_t board_init_adc12_clock(ADC12_Type *ptr) -{ - uint32_t freq = 0; - switch ((uint32_t) ptr) { - case HPM_ADC0_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc0); - break; - case HPM_ADC1_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc1); - break; - case HPM_ADC2_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc2); - break; - default: - /* Invalid ADC instance */ - break; - } - - return freq; -} - uint32_t board_init_dao_clock(void) { clock_add_to_group(clock_dao, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud0_clk); + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); return clock_get_frequency(clock_dao); } @@ -768,43 +746,112 @@ void board_init_i2s_pins(I2S_Type *ptr) uint32_t board_init_i2s_clock(I2S_Type *ptr) { + uint32_t freq = 0; + if (ptr == HPM_I2S0) { clock_add_to_group(clock_i2s0, 0); sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); - return clock_get_frequency(clock_i2s0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); + + freq = clock_get_frequency(clock_i2s1); } else { - return 0; + ; } + + return freq; } /* adjust I2S source clock base on sample rate */ uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) { + uint32_t freq = 0; + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); if ((sample_rate % 22050) == 0) { - clock_add_to_group(clock_i2s0, 0); - clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ - clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud1); + clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ } else { - clock_add_to_group(clock_i2s0, 0); clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */ - clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); } - return clock_get_frequency(clock_i2s0); + clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 25); /* config clock_aud0 for 8000*n sample rate */ + } + clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1); + freq = clock_get_frequency(clock_i2s1); + } else { + ; + } + + return freq; +} + +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc2); } - return 0; + + return freq; } -uint32_t board_init_adc16_clock(ADC16_Type *ptr) +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) { uint32_t freq = 0; + if (ptr == HPM_ADC3) { - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc3, clk_adc_src_ana1); - clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + freq = clock_get_frequency(clock_adc3); } @@ -956,8 +1003,38 @@ bool board_sd_detect_card(SDXC_Type *ptr) return sdxc_is_card_inserted(ptr); } +static void set_rgb_output_off(PWM_Type *ptr, uint8_t pin, uint8_t cmp_index) +{ + pwm_cmp_config_t cmp_config = {0}; + pwm_output_channel_t ch_config = {0}; + + pwm_stop_counter(ptr); + pwm_get_default_cmp_config(ptr, &cmp_config); + pwm_get_default_output_channel_config(ptr, &ch_config); + + pwm_set_reload(ptr, 0, 0xF); + pwm_set_start_count(ptr, 0, 0); + + cmp_config.mode = pwm_cmp_mode_output_compare; + cmp_config.cmp = 0x10; + cmp_config.update_trigger = pwm_shadow_register_update_on_modify; + pwm_config_cmp(ptr, cmp_index, &cmp_config); + + ch_config.cmp_start_index = cmp_index; + ch_config.cmp_end_index = cmp_index; + ch_config.invert_output = !board_get_led_pwm_off_level(); + + pwm_config_output_channel(ptr, pin, &ch_config); +} + void board_init_rgb_pwm_pins(void) { + board_turnoff_rgb_led(); + + set_rgb_output_off(BOARD_RED_PWM, BOARD_RED_PWM_OUT, BOARD_RED_PWM_CMP); + set_rgb_output_off(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT, BOARD_GREEN_PWM_CMP); + set_rgb_output_off(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT, BOARD_BLUE_PWM_CMP); + init_led_pins_as_pwm(); } @@ -1100,4 +1177,4 @@ void board_init_enet_pps_pins(ENET_Type *ptr) void board_init_dao_pins(void) { init_dao_pins(); -} \ No newline at end of file +} diff --git a/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.h b/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.h index c344cb91..b7d94bd1 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.h +++ b/common/libraries/hpm_sdk/boards/hpm6750evkmini/board.h @@ -32,7 +32,7 @@ #define BOARD_APP_UART_IRQ IRQn_UART0 #else #ifndef BOARD_APP_UART_IRQ -#warning no IRQ specified for applicaiton uart +#warning no IRQ specified for application uart #endif #endif @@ -187,9 +187,8 @@ *led Internal pull-up and pull-down resistance direction *The configurations of Rev-A / B boards are different */ -#define BOARD_LED_PULL_STATUS IOC_PAD_PAD_CTL_PS_GET(HPM_IOC->PAD[IOC_PAD_PB18].PAD_CTL) -#define BOARD_LED_OFF_LEVEL BOARD_LED_PULL_STATUS -#define BOARD_LED_ON_LEVEL !BOARD_LED_PULL_STATUS +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ #define BOARD_APP_GPIO_PIN 2 @@ -307,16 +306,33 @@ #define BOARD_ENET_RMII_INT_REF_CLK (0U) #define BOARD_ENET_RMII_PTP_CLOCK clock_ptp1 -/* adc section */ -#define BOARD_APP_ADC12_NAME "ADC0" -#define BOARD_APP_ADC12_BASE HPM_ADC0 -#define BOARD_APP_ADC12_IRQn IRQn_ADC0 -#define BOARD_APP_ADC12_CH_1 (7U) - -#define BOARD_APP_ADC16_NAME "ADC3" -#define BOARD_APP_ADC16_IRQn IRQn_ADC3 -#define BOARD_APP_ADC16_BASE HPM_ADC3 -#define BOARD_APP_ADC16_CH_1 (2U) +/* ADC section */ +#define BOARD_APP_ADC12_NAME "ADC0" +#define BOARD_APP_ADC12_BASE HPM_ADC0 +#define BOARD_APP_ADC12_IRQn IRQn_ADC0 +#define BOARD_APP_ADC12_CH_1 (7U) +#define BOARD_APP_ADC12_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_NAME "ADC3" +#define BOARD_APP_ADC16_IRQn IRQn_ADC3 +#define BOARD_APP_ADC16_BASE HPM_ADC3 +#define BOARD_APP_ADC16_CH_1 (2U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc3) + +#define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A /* CAN section */ #define BOARD_APP_CAN_BASE HPM_CAN1 @@ -388,7 +404,7 @@ #define BOARD_BLUE_PWM_IRQ IRQn_PWM0 #define BOARD_BLUE_PWM HPM_PWM0 #define BOARD_BLUE_PWM_OUT 7 -#define BOARD_BLUE_PWM_CMP 0 +#define BOARD_BLUE_PWM_CMP 7 #define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true #define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0 @@ -489,6 +505,12 @@ #define BOARD_SHOW_BANNER 1 #endif +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR4 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR4 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr4 + #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE 0 #endif @@ -505,6 +527,7 @@ void board_init_console(void); void board_init_uart(UART_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); +void board_lcd_backlight(bool is_on); void board_panel_para_to_lcdc(lcdc_config_t *config); void board_init_can(CAN_Type *ptr); @@ -541,9 +564,9 @@ uint32_t board_init_lcd_clock(void); uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc12_clock(ADC12_Type *ptr); +uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); -uint32_t board_init_adc16_clock(ADC16_Type *ptr); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); uint32_t board_init_can_clock(CAN_Type *ptr); diff --git a/common/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c b/common/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c index faab550e..8f4d8560 100644 --- a/common/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c +++ b/common/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.c @@ -21,8 +21,8 @@ void init_uart_pins(UART_Type *ptr) HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD; HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD; /* PY port IO needs to configure PIOC as well */ - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06; } else if (ptr == HPM_UART6) { HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_UART6_RXD; HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_UART6_TXD; diff --git a/common/libraries/hpm_sdk/boards/openocd/boards/hpm5300evk.cfg b/common/libraries/hpm_sdk/boards/openocd/boards/hpm5300evk.cfg new file mode 100644 index 00000000..7d495f5b --- /dev/null +++ b/common/libraries/hpm_sdk/boards/openocd/boards/hpm5300evk.cfg @@ -0,0 +1,79 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit 6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3000000 +# - base address: 0x80000000 +# - flash size: 0x2000000 +# - flash option0: 0x7 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x6 0x1000 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +$_TARGET0 configure -event reset-init { + init_clock +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/common/libraries/hpm_sdk/boards/openocd/hpm5300_all_in_one.cfg b/common/libraries/hpm_sdk/boards/openocd/hpm5300_all_in_one.cfg new file mode 100644 index 00000000..d9ede39f --- /dev/null +++ b/common/libraries/hpm_sdk/boards/openocd/hpm5300_all_in_one.cfg @@ -0,0 +1,33 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause +# +# assumptions: +# - HPM_SDK_BASE has been defined as environment variable pointing to correct hpm_sdk path +# - current directory is ${HPM_SDK_BASE}/boards/openocd +# +# usage: +# # connect hpm5300evk via ft2232, debugging single core +# $ openocd -c "set HPM_SDK_BASE ${HPM_SDK_BASE}; set BOARD hpm5300vk; set PROBE ft2232;" -f hpm5300_all_in_one.cfg +# +# # supported board to be set to BOARD: +# - hpm5300evk +# # supported probes to be set to PROBE: +# - ft2232 +# - ft232 +# - jlink +# - cmsis_dap +# - nds_aice_micro + +set HPM_OPENOCD_CONFIG ${HPM_SDK_BASE}/boards/openocd + +if { ![info exists PROBE ] } { + set PROBE ft2232 +} + +if { ![info exists BOARD] } { + set BOARD hpm5300evk +} + +source ${HPM_OPENOCD_CONFIG}/probes/${PROBE}.cfg +source ${HPM_OPENOCD_CONFIG}/soc/hpm5361.cfg +source ${HPM_OPENOCD_CONFIG}/boards/${BOARD}.cfg diff --git a/common/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg b/common/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg index 2d918fd5..ee1b76f7 100644 --- a/common/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/probes/ft2232.cfg @@ -3,8 +3,6 @@ bindto 0.0.0.0 adapter speed 10000 -reset_config trst_and_srst -adapter srst delay 50 adapter driver ftdi ftdi_vid_pid 0x0403 0x6010 diff --git a/common/libraries/hpm_sdk/boards/openocd/soc/hpm5361.cfg b/common/libraries/hpm_sdk/boards/openocd/soc/hpm5361.cfg new file mode 100644 index 00000000..ad949dcb --- /dev/null +++ b/common/libraries/hpm_sdk/boards/openocd/soc/hpm5361.cfg @@ -0,0 +1,13 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm5361 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 diff --git a/common/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg b/common/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg index 14019e5d..ad83b6a1 100644 --- a/common/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg +++ b/common/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg @@ -28,7 +28,7 @@ proc dmi_write_memory {addr value} { } proc dmi_read_memory {addr} { - set sbcs [expr 0x100000 | [dmi_read 0x38]] + set sbcs [expr { 0x100000 | [dmi_read 0x38] }] dmi_write 0x38 ${sbcs} dmi_write 0x39 ${addr} set value [dmi_read 0x3C] diff --git a/common/libraries/hpm_sdk/components/CMakeLists.txt b/common/libraries/hpm_sdk/components/CMakeLists.txt index ab6aa6ef..7c621d34 100644 --- a/common/libraries/hpm_sdk/components/CMakeLists.txt +++ b/common/libraries/hpm_sdk/components/CMakeLists.txt @@ -13,8 +13,9 @@ add_subdirectory_ifdef(CONFIG_USB_DEVICE usb/device) add_subdirectory_ifdef(CONFIG_TOUCH touch) add_subdirectory_ifdef(CONFIG_HPM_ADC adc) add_subdirectory_ifdef(CONFIG_HPM_SPI spi) -add_subdirectory_ifdef(CONFIG_DMA_MANAGER dma_manager) +add_subdirectory_ifdef(CONFIG_DMA_MGR dma_mgr) add_subdirectory_ifdef(CONFIG_IPC_EVENT_MGR ipc_event_mgr) add_subdirectory_ifdef(CONFIG_HPM_SCCB sccb) add_subdirectory_ifdef(CONFIG_HPM_SMBUS smbus) add_subdirectory_ifdef(CONFIG_HPM_UART_LIN uart_lin) +add_subdirectory_ifdef(CONFIG_EEPROM_EMULATION eeprom_emulation) diff --git a/common/libraries/hpm_sdk/components/SConscript b/common/libraries/hpm_sdk/components/SConscript index 8044364e..02305efd 100644 --- a/common/libraries/hpm_sdk/components/SConscript +++ b/common/libraries/hpm_sdk/components/SConscript @@ -8,13 +8,13 @@ cwd = GetCurrentDir() CPPDEFINES=[] # Update include path -path = [ os.path.join(cwd, 'debug_console'), os.path.join(cwd, 'touch'), os.path.join(cwd, 'usb'), os.path.join(cwd, 'dma_manager')] +path = [ os.path.join(cwd, 'debug_console'), os.path.join(cwd, 'touch'), os.path.join(cwd, 'usb'), os.path.join(cwd, 'dma_mgr')] # The set of source files associated with this SConscript file. src = [] src += [ os.path.join(cwd, 'debug_console', 'hpm_debug_console.c') ] -src += [ os.path.join(cwd, 'dma_manager', 'hpm_dma_manager.c') ] +src += [ os.path.join(cwd, 'dma_mgr', 'hpm_dma_mgr.c') ] if GetDepend(['BSP_USING_TOUCH_GT911']): src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_touch_gt911.c') ] diff --git a/common/libraries/hpm_sdk/components/camera/ov5640/CMakeLists.txt b/common/libraries/hpm_sdk/components/camera/ov5640/CMakeLists.txt index 259423be..a09231ee 100644 --- a/common/libraries/hpm_sdk/components/camera/ov5640/CMakeLists.txt +++ b/common/libraries/hpm_sdk/components/camera/ov5640/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2021 HPMicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause sdk_inc(.) diff --git a/common/libraries/hpm_sdk/components/camera/ov7725/CMakeLists.txt b/common/libraries/hpm_sdk/components/camera/ov7725/CMakeLists.txt index 3197ffd2..baca1241 100644 --- a/common/libraries/hpm_sdk/components/camera/ov7725/CMakeLists.txt +++ b/common/libraries/hpm_sdk/components/camera/ov7725/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2021 HPMicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause sdk_inc(.) diff --git a/common/libraries/hpm_sdk/components/codec/sgtl5000/CMakeLists.txt b/common/libraries/hpm_sdk/components/codec/sgtl5000/CMakeLists.txt index 2ed48f33..9335c665 100644 --- a/common/libraries/hpm_sdk/components/codec/sgtl5000/CMakeLists.txt +++ b/common/libraries/hpm_sdk/components/codec/sgtl5000/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2021 HPMicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause sdk_inc(.) diff --git a/common/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c b/common/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c index af4e739b..e981c8e8 100644 --- a/common/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c +++ b/common/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c @@ -401,41 +401,35 @@ hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, return stat; } +static bool wm8960_check_clock_tolerance(uint32_t source, uint32_t target) +{ + if (abs(source - target) * 100 / target < HPM_WM8960_MCLK_TOLERANCE) { + return true; + } + return false; +} + hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits) { hpm_stat_t stat = status_success; - uint32_t divider = 0; - uint16_t val = 0; + uint16_t val = 0; + uint32_t ratio[7] = {256, 256 * 1.5, 256 * 2, 256 * 3, 256 * 4, 256 * 5.5, 256 * 6}; + bool clock_meet_requirement = false; - /* Compute sample rate divider and SYSCLK Pre-divider, dac and adc are the same sample rate */ - divider = sysclk / sample_rate; + if (sysclk / sample_rate > 256 * 6) { + sysclk = sysclk / 2; + val = WM8960_CLOCK1_SYSCLKDIV_SET(2U); /* SYSCLK Pre-divider */ + } - if (divider > 6 * 512 * HPM_WM8960_MCLK_TOLERANCE / 100 + 6 * 512) { - divider = divider / 2; /* SYSCLK Pre-divider */ - val |= WM8960_CLOCK1_SYSCLKDIV_SET(2U); + for (uint8_t i = 0; i < 7; i++) { + if (wm8960_check_clock_tolerance(sysclk, sample_rate * ratio[i])) { + val |= ((i << WM8960_CLOCK1_ADCDIV_SHIFT) | (i << WM8960_CLOCK1_DACDIV_SHIFT)); + clock_meet_requirement = true; + break; + } } - if (abs(divider - 256) <= 256 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256; - } else if (abs(divider - 256 * 1.5) <= 256 * 1.5 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256 * 1.5; - val |= ((1 << WM8960_CLOCK1_ADCDIV_SHIFT) | (1 << WM8960_CLOCK1_DACDIV_SHIFT)); - } else if (abs(divider - 256 * 2) <= 256 * 2 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256 * 2; - val |= ((2 << WM8960_CLOCK1_ADCDIV_SHIFT) | (2 << WM8960_CLOCK1_DACDIV_SHIFT)); - } else if (abs(divider - 256 * 3) <= 256 * 3 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256 * 3; - val |= ((3 << WM8960_CLOCK1_ADCDIV_SHIFT) | (3 << WM8960_CLOCK1_DACDIV_SHIFT)); - } else if (abs(divider - 256 * 4) <= 256 * 4 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256 * 4; - val |= ((4 << WM8960_CLOCK1_ADCDIV_SHIFT) | (4 << WM8960_CLOCK1_DACDIV_SHIFT)); - } else if (abs(divider - 256 * 5.5) <= 256 * 5.5 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256 * 5.5; - val |= ((5 << WM8960_CLOCK1_ADCDIV_SHIFT) | (5 << WM8960_CLOCK1_DACDIV_SHIFT)); - } else if (abs(divider - 256 * 6) <= 256 * 6 * HPM_WM8960_MCLK_TOLERANCE) { - divider = 256 * 6; - val |= ((6 << WM8960_CLOCK1_ADCDIV_SHIFT) | (6 << WM8960_CLOCK1_DACDIV_SHIFT)); - } else { + if (!clock_meet_requirement) { return status_invalid_argument; } HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val)); diff --git a/common/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c b/common/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c deleted file mode 100644 index 7529e5af..00000000 --- a/common/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include -#include "hpm_dma_manager.h" -#include "hpm_soc.h" - -/***************************************************************************************************************** - * - * Definitions - * - *****************************************************************************************************************/ - -typedef struct _dma_instance_info { - DMA_Type *base; - int32_t irq_num; -} dma_channel_info_t; - -/** - * @brief DMA Manager Context Structure - * - */ -typedef struct _dma_manager_context { - dma_channel_info_t dma_instance[DMA_SOC_MAX_COUNT]; /**< DMA instances */ - hpm_dma_channel_context_t channels[DMA_SOC_MAX_COUNT][DMA_SOC_CHANNEL_NUM]; /**< Array of DMA channels */ -} hpm_dma_manager_context_t; - -#define DMA_DISABLE_ALL_CHN_INT (DMA_INTERRUPT_MASK_ERROR | DMA_INTERRUPT_MASK_ABORT | DMA_INTERRUPT_MASK_TERMINAL_COUNT) - - -/***************************************************************************************************************** - * - * Prototypes - * - *****************************************************************************************************************/ - -/** - * @brief Search DMA channel context for specified DMA channel resource - * - * @param [in] resource DMA Channel resource - * @return The request DMA channel context if resource is valid or NULL if resource in invalid - */ -static hpm_dma_channel_context_t *dma_manager_search_channel_context(const hpm_dma_resource_t *resource); - -static uint32_t dma_manager_enter_critical(void); -static void dma_manager_exit_critical(uint32_t level); - -static void dma0_isr(void); -SDK_DECLARE_EXT_ISR_M(IRQn_HDMA, dma0_isr); - -#if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) -static void dma1_isr(void); -SDK_DECLARE_EXT_ISR_M(IRQn_XDMA, dma1_isr); -#endif - -/***************************************************************************************************************** - * - * Variables - * - *****************************************************************************************************************/ -static hpm_dma_manager_context_t s_dma_mngr_ctx; -#define HPM_DMA_MGR (&s_dma_mngr_ctx) - - - -/***************************************************************************************************************** - * - * Codes - * - *****************************************************************************************************************/ -static inline void handle_dma_isr(DMA_Type *ptr, uint32_t instance) -{ - for (uint8_t channel = 0; channel < DMA_SOC_CHANNEL_NUM; channel++) { - uint32_t int_disable_mask = dma_check_channel_interrupt_mask(ptr, channel); - /* If Channel interrupt is enabled */ - if (int_disable_mask != DMA_DISABLE_ALL_CHN_INT) { - uint32_t chn_int_stat = dma_check_transfer_status(ptr, channel); - if (chn_int_stat != DMA_CHANNEL_STATUS_ONGOING) { - hpm_dma_channel_context_t *chn_ctx = &HPM_DMA_MGR->channels[instance][channel]; - if (chn_ctx->callback != NULL) { - chn_ctx->callback(ptr, channel, chn_ctx->user_data, chn_int_stat); - } - } /* end if (chn_int_stat != DMA_CHANNEL_STATUS_ONGOING) */ - } /* end if (int_disable_mask != DMA_DISABLE_ALL_CHN_INT) */ - } /* end for (uint8_t channel = 0; channel < DMA_SOC_MAX_COUNT; channel++) */ -} - -void dma0_isr(void) -{ - handle_dma_isr(HPM_HDMA, 0); -} - -#if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) -void dma1_isr(void) -{ - handle_dma_isr(HPM_XDMA, 1); -} -#endif - -static uint32_t dma_manager_enter_critical(void) -{ - uint32_t level = read_csr(CSR_MSTATUS); - disable_global_irq(CSR_MSTATUS_MIE_MASK); - return level; -} - -static void dma_manager_exit_critical(uint32_t level) -{ - write_csr(CSR_MSTATUS, level); -} - -/* See hpm_dma_manager.h for more details */ -void dma_manager_init(void) -{ - (void) memset(HPM_DMA_MGR, 0, sizeof(*HPM_DMA_MGR)); - HPM_DMA_MGR->dma_instance[0].base = HPM_HDMA, - HPM_DMA_MGR->dma_instance[0].irq_num = IRQn_HDMA; - #if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) - HPM_DMA_MGR->dma_instance[1].base = HPM_XDMA; - HPM_DMA_MGR->dma_instance[1].irq_num = IRQn_XDMA; - #endif -} - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_request_resource(hpm_dma_resource_t *resource) -{ - hpm_stat_t status; - - if (resource == NULL) { - status = status_invalid_argument; - } else { - uint32_t instance; - uint32_t channel; - bool has_found = false; - uint32_t level = dma_manager_enter_critical(); - for (instance = 0; instance < DMA_SOC_MAX_COUNT; instance++) { - for (channel = 0; channel < DMA_SOC_CHANNEL_NUM; channel++) { - if (!HPM_DMA_MGR->channels[instance][channel].is_allocated) { - has_found = true; - break; - } - } - if (has_found) { - break; - } - } - - if (has_found) { - HPM_DMA_MGR->channels[instance][channel].is_allocated = true; - resource->base = HPM_DMA_MGR->dma_instance[instance].base; - resource->channel = channel; - resource->irq_num = HPM_DMA_MGR->dma_instance[instance].irq_num; - status = status_success; - } else { - status = status_dma_manager_no_resource; - } - - dma_manager_exit_critical(level); - } - - return status; -} - -static hpm_dma_channel_context_t *dma_manager_search_channel_context(const hpm_dma_resource_t *resource) -{ - hpm_dma_channel_context_t *channel_ctx = NULL; - - if ((resource != NULL) && (resource->channel < DMA_SOC_CHANNEL_NUM)) { - uint32_t instance; - uint32_t channel; - bool has_found = false; - for (instance = 0; instance < DMA_SOC_MAX_COUNT; instance++) { - if (resource->base == HPM_DMA_MGR->dma_instance[instance].base) { - has_found = true; - break; - } - } - - channel = resource->channel; - if (has_found) { - channel_ctx = &HPM_DMA_MGR->channels[instance][channel]; - } - } - - return channel_ctx; -} - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_release_resource(const hpm_dma_resource_t *resource) -{ - hpm_stat_t status; - - hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); - - if (channel_ctx == NULL) { - status = status_invalid_argument; - } else { - - uint32_t level = dma_manager_enter_critical(); - channel_ctx->is_allocated = false; - channel_ctx->user_data = NULL; - channel_ctx->callback = NULL; - status = status_success; - dma_manager_exit_critical(level); - } - return status; -} - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_enable_channel_interrupt(const hpm_dma_resource_t *resource, uint32_t irq_mask) -{ - hpm_stat_t status; - - hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); - - if (channel_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_enable_channel_interrupt(resource->base, resource->channel, irq_mask); - status = status_success; - } - return status; -} - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_disable_channel_interrupt(const hpm_dma_resource_t *resource, uint32_t irq_mask) -{ - hpm_stat_t status; - - hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); - - if (channel_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_disable_channel_interrupt(resource->base, resource->channel, irq_mask); - status = status_success; - } - return status; -} - - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_enable_dma_interrupt(const hpm_dma_resource_t *resource, uint32_t priority) -{ - hpm_stat_t status; - - hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); - - if (channel_ctx == NULL) { - status = status_invalid_argument; - } else { - intc_m_enable_irq_with_priority(resource->irq_num, priority); - status = status_success; - } - return status; -} - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_disable_dma_interrupt(const hpm_dma_resource_t *resource) -{ - hpm_stat_t status; - - hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); - - if (channel_ctx == NULL) { - status = status_invalid_argument; - } else { - intc_m_disable_irq(resource->irq_num); - status = status_success; - } - return status; -} - - -/* See hpm_dma_manager.h for more details */ -hpm_stat_t dma_manager_install_interrupt_callback(const hpm_dma_resource_t *resource, hpm_dma_channel_callback_t callback, void *user_data) -{ - hpm_stat_t status; - - hpm_dma_channel_context_t *channel_ctx = dma_manager_search_channel_context(resource); - - if (channel_ctx == NULL) { - status = status_invalid_argument; - } else { - channel_ctx->user_data = user_data; - channel_ctx->callback = callback; - status = status_success; - } - return status; -} diff --git a/common/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h b/common/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h deleted file mode 100644 index b04bd806..00000000 --- a/common/libraries/hpm_sdk/components/dma_manager/hpm_dma_manager.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_DMA_MANAGER_H -#define HPM_DMA_MANAGER_H - -#include "hpm_common.h" -#ifdef CONFIG_HAS_HPMSDK_DMAV2 -#include "hpm_dmav2_drv.h" -#else -#include "hpm_dma_drv.h" -#endif -#include "hpm_soc_feature.h" - - -#ifdef __cplusplus - -extern "C" { -#endif - - -/** - * @brief DMA Manager status codes - */ -enum { - status_dma_manager_no_resource = MAKE_STATUS(status_group_dma_manager, 0), /**< No DMA resource available */ -}; - -/** - * @brief DMA Channel Interrupt callback - * - * @param [in] DMA base address - * @param [in] channel DMA channel index - * @param [in/out] user_data User Data context - * @param [in] int_stat DMA interrupt status - * bit0 - DMA_CHANNEL_STATUS_ONGOING - * bit1 - DMA_CHANNEL_STATUS_ERROR - * bit2 - DMA_CHANNEL_STATUS_ABORT - * bit3 - DMA_CHANNEL_STATUS_TC - */ -typedef void (*hpm_dma_channel_callback_t)(DMA_Type *base, uint32_t channel, void *user_data, uint32_t int_stat); - -/** - * @brief DMA Resource Structure - */ -typedef struct _dma_resource { - DMA_Type *base; /**< The DMA intance that the allocated channel belongs to */ - uint32_t channel; /**< Channel index */ - int32_t irq_num; /**< DMA IRQ number */ -} hpm_dma_resource_t; - -/** - * @brief DMA Channel Context Structure - */ -typedef struct _dma_channel_context { - bool is_allocated; /**< Whether DMA channel was allocated */ - void *user_data; /**< User data required by DMA channel callback */ - hpm_dma_channel_callback_t callback;/**< DMA channel callback */ -} hpm_dma_channel_context_t; - - -/** - * @brief Initialize DMA Manager Context - */ -void dma_manager_init(void); - -/** - * @brief Request DMA resource from DMA Manager - * - * @param [out] resource DMA resource - * @retval status_success if no error occurred - * @retval status_invalid_argument if the parameter is invalid - * @retval status_dma_manager_no_resource if all DMA channels are occupied; - */ -hpm_stat_t dma_manager_request_resource(hpm_dma_resource_t *resource); - -/** - * @brief Release DMA resource - * - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if the parameter is invalid - */ -hpm_stat_t dma_manager_release_resource(const hpm_dma_resource_t *resource); - - -/** - * @brief Enable Resource interrupt - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_manager_enable_channel_interrupt(const hpm_dma_resource_t *resource, uint32_t irq_mask); - - -/** - * @brief Disable Resource interrupt - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_manager_disable_channel_interrupt(const hpm_dma_resource_t *resource, uint32_t irq_mask); - - -/** - * @brief Enable DMa interrupt - * @param [in] resource DMA resource - * @param [in] priority Interrupt Priority - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_manager_enable_dma_interrupt(const hpm_dma_resource_t *resource, uint32_t priority); - -/** - * @brief Disable DMA interrupt - * NOTE: Each DMA instance consists of several DMA channels, disabling the DMA interrupt - * will disable the global DMA interrupt for all DMA channels. Please be aware of the - * impact - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_manager_disable_dma_interrupt(const hpm_dma_resource_t *resource); - - -/** - * @brief Install Interrupt Callback for the DMA resource - * - * @param [in] resource DMA resource - * @param [in] callback Interrupt callback for DMA resource - * @param [in] user_data User data used in the callback - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_manager_install_interrupt_callback(const hpm_dma_resource_t *resource, hpm_dma_channel_callback_t callback, void *user_data); - - - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_DMA_MANAGER_H */ diff --git a/common/libraries/hpm_sdk/components/dma_manager/CMakeLists.txt b/common/libraries/hpm_sdk/components/dma_mgr/CMakeLists.txt similarity index 71% rename from common/libraries/hpm_sdk/components/dma_manager/CMakeLists.txt rename to common/libraries/hpm_sdk/components/dma_mgr/CMakeLists.txt index 9cc8514f..a2e3932e 100644 --- a/common/libraries/hpm_sdk/components/dma_manager/CMakeLists.txt +++ b/common/libraries/hpm_sdk/components/dma_mgr/CMakeLists.txt @@ -1,5 +1,5 @@ -# Copyright (c) 2022 HPMicro -# SPDX-License-Identifier: BSD-3-Clause - -sdk_inc(.) -sdk_src(hpm_dma_manager.c) +# Copyright (c) 2022 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +sdk_inc(.) +sdk_src(hpm_dma_mgr.c) diff --git a/common/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.c b/common/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.c new file mode 100644 index 00000000..9ab97ec7 --- /dev/null +++ b/common/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.c @@ -0,0 +1,775 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "hpm_dma_mgr.h" +#include "hpm_soc.h" + +/***************************************************************************************************************** + * + * Definitions + * + *****************************************************************************************************************/ + +typedef struct _dma_instance_info { + DMA_Type *base; + int32_t irq_num; +} dma_chn_info_t; + +/** + * @brief DMA Channel Context Structure + */ +typedef struct _dma_channel_context { + bool is_allocated; /**< Whether DMA channel was allocated */ + void *tc_cb_data_ptr; /**< User data required by transfer complete callback */ + void *half_tc_cb_data_ptr; /**< User data required by half transfer complete callback */ + void *error_cb_data_ptr; /**< User data required by error callback */ + void *abort_cb_data_ptr; /**< User data required by abort callback */ + dma_mgr_chn_cb_t tc_cb; /**< DMA channel transfer complete callback */ + dma_mgr_chn_cb_t half_tc_cb; /**< DMA channel half transfer complete callback */ + dma_mgr_chn_cb_t error_cb; /**< DMA channel error callback */ + dma_mgr_chn_cb_t abort_cb; /**< DMA channel abort callback */ +} dma_chn_context_t; + +/** + * @brief DMA Manager Context Structure + * + */ +typedef struct _dma_mgr_context { + dma_chn_info_t dma_instance[DMA_SOC_MAX_COUNT]; /**< DMA instances */ + dma_chn_context_t channels[DMA_SOC_MAX_COUNT][DMA_SOC_CHANNEL_NUM]; /**< Array of DMA channels */ +} dma_mgr_context_t; + + +/***************************************************************************************************************** + * + * Prototypes + * + *****************************************************************************************************************/ + +/** + * @brief Search DMA channel context for specified DMA channel resource + * + * @param [in] resource DMA Channel resource + * @return The request DMA channel context if resource is valid or NULL if resource in invalid + */ +static dma_chn_context_t *dma_mgr_search_chn_context(const dma_resource_t *resource); + +static uint32_t dma_mgr_enter_critical(void); +static void dma_mgr_exit_critical(uint32_t level); + +static void dma0_isr(void); +SDK_DECLARE_EXT_ISR_M(IRQn_HDMA, dma0_isr); + +#if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) +static void dma1_isr(void); +SDK_DECLARE_EXT_ISR_M(IRQn_XDMA, dma1_isr); +#endif + +/***************************************************************************************************************** + * + * Variables + * + *****************************************************************************************************************/ +static dma_mgr_context_t s_dma_mngr_ctx; +#define HPM_DMA_MGR (&s_dma_mngr_ctx) + +/***************************************************************************************************************** + * + * Codes + * + *****************************************************************************************************************/ +static inline void handle_dma_isr(DMA_Type *ptr, uint32_t instance) +{ + uint32_t int_disable_mask; + uint32_t chn_int_stat; + dma_chn_context_t *chn_ctx; + + for (uint8_t channel = 0; channel < DMA_SOC_CHANNEL_NUM; channel++) { + int_disable_mask = dma_check_channel_interrupt_mask(ptr, channel); + chn_int_stat = dma_check_transfer_status(ptr, channel); + chn_ctx = &HPM_DMA_MGR->channels[instance][channel]; + + if (((int_disable_mask & DMA_MGR_INTERRUPT_MASK_TC) == 0) && ((chn_int_stat & DMA_MGR_CHANNEL_STATUS_TC) != 0)) { + if (chn_ctx->tc_cb != NULL) { + chn_ctx->tc_cb(ptr, channel, chn_ctx->tc_cb_data_ptr); + } + } + if (((int_disable_mask & DMA_MGR_INTERRUPT_MASK_HALF_TC) == 0) && ((chn_int_stat & DMA_MGR_CHANNEL_STATUS_HALF_TC) != 0)) { + if (chn_ctx->half_tc_cb != NULL) { + chn_ctx->half_tc_cb(ptr, channel, chn_ctx->half_tc_cb_data_ptr); + } + } + if (((int_disable_mask & DMA_MGR_INTERRUPT_MASK_ERROR) == 0) && ((chn_int_stat & DMA_MGR_CHANNEL_STATUS_ERROR) != 0)) { + if (chn_ctx->error_cb != NULL) { + chn_ctx->error_cb(ptr, channel, chn_ctx->error_cb_data_ptr); + } + } + if (((int_disable_mask & DMA_MGR_INTERRUPT_MASK_ABORT) == 0) && ((chn_int_stat & DMA_MGR_CHANNEL_STATUS_ABORT) != 0)) { + if (chn_ctx->abort_cb != NULL) { + chn_ctx->abort_cb(ptr, channel, chn_ctx->abort_cb_data_ptr); + } + } + } +} + +void dma0_isr(void) +{ + handle_dma_isr(HPM_HDMA, 0); +} + +#if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) +void dma1_isr(void) +{ + handle_dma_isr(HPM_XDMA, 1); +} +#endif + +static uint32_t dma_mgr_enter_critical(void) +{ + return disable_global_irq(CSR_MSTATUS_MIE_MASK); +} + +static void dma_mgr_exit_critical(uint32_t level) +{ + restore_global_irq(level); +} + +void dma_mgr_init(void) +{ + (void) memset(HPM_DMA_MGR, 0, sizeof(*HPM_DMA_MGR)); + HPM_DMA_MGR->dma_instance[0].base = HPM_HDMA, + HPM_DMA_MGR->dma_instance[0].irq_num = IRQn_HDMA; + #if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) + HPM_DMA_MGR->dma_instance[1].base = HPM_XDMA; + HPM_DMA_MGR->dma_instance[1].irq_num = IRQn_XDMA; + #endif +} + +hpm_stat_t dma_mgr_request_resource(dma_resource_t *resource) +{ + hpm_stat_t status; + + if (resource == NULL) { + status = status_invalid_argument; + } else { + uint32_t instance; + uint32_t channel; + bool has_found = false; + uint32_t level = dma_mgr_enter_critical(); + for (instance = 0; instance < DMA_SOC_MAX_COUNT; instance++) { + for (channel = 0; channel < DMA_SOC_CHANNEL_NUM; channel++) { + if (!HPM_DMA_MGR->channels[instance][channel].is_allocated) { + has_found = true; + break; + } + } + if (has_found) { + break; + } + } + + if (has_found) { + HPM_DMA_MGR->channels[instance][channel].is_allocated = true; + resource->base = HPM_DMA_MGR->dma_instance[instance].base; + resource->channel = channel; + resource->irq_num = HPM_DMA_MGR->dma_instance[instance].irq_num; + status = status_success; + } else { + status = status_dma_mgr_no_resource; + } + + dma_mgr_exit_critical(level); + } + + return status; +} + +static dma_chn_context_t *dma_mgr_search_chn_context(const dma_resource_t *resource) +{ + dma_chn_context_t *chn_ctx = NULL; + + if ((resource != NULL) && (resource->channel < DMA_SOC_CHANNEL_NUM)) { + uint32_t instance; + uint32_t channel; + bool has_found = false; + for (instance = 0; instance < DMA_SOC_MAX_COUNT; instance++) { + if (resource->base == HPM_DMA_MGR->dma_instance[instance].base) { + has_found = true; + break; + } + } + + channel = resource->channel; + if (has_found) { + if (HPM_DMA_MGR->channels[instance][channel].is_allocated) { + chn_ctx = &HPM_DMA_MGR->channels[instance][channel]; + } + } + } + + return chn_ctx; +} + +hpm_stat_t dma_mgr_release_resource(const dma_resource_t *resource) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + uint32_t level = dma_mgr_enter_critical(); + chn_ctx->is_allocated = false; + chn_ctx->tc_cb_data_ptr = NULL; + chn_ctx->half_tc_cb_data_ptr = NULL; + chn_ctx->error_cb_data_ptr = NULL; + chn_ctx->abort_cb_data_ptr = NULL; + chn_ctx->tc_cb = NULL; + chn_ctx->half_tc_cb = NULL; + chn_ctx->error_cb = NULL; + chn_ctx->abort_cb = NULL; + status = status_success; + dma_mgr_exit_critical(level); + } + return status; +} + +hpm_stat_t dma_mgr_enable_dma_irq_with_priority(const dma_resource_t *resource, uint32_t priority) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + intc_m_enable_irq_with_priority(resource->irq_num, priority); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_disable_dma_irq(const dma_resource_t *resource) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + intc_m_disable_irq(resource->irq_num); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_install_chn_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + chn_ctx->tc_cb_data_ptr = user_data; + chn_ctx->tc_cb = callback; + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_install_chn_half_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + chn_ctx->half_tc_cb_data_ptr = user_data; + chn_ctx->half_tc_cb = callback; + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_install_chn_error_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + chn_ctx->error_cb_data_ptr = user_data; + chn_ctx->error_cb = callback; + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_install_chn_abort_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + chn_ctx->abort_cb_data_ptr = user_data; + chn_ctx->abort_cb = callback; + status = status_success; + } + return status; +} + +void dma_mgr_get_default_chn_config(dma_mgr_chn_conf_t *config) +{ + config->en_dmamux = false; + config->dmamux_src = 0; + config->priority = DMA_MGR_CHANNEL_PRIORITY_LOW; + config->src_burst_size = DMA_MGR_NUM_TRANSFER_PER_BURST_1T; + config->src_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; + config->dst_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; + config->src_width = DMA_MGR_TRANSFER_WIDTH_BYTE; + config->dst_width = DMA_MGR_TRANSFER_WIDTH_BYTE; + config->src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; + config->dst_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; + config->src_addr = 0; + config->dst_addr = 0; + config->size_in_byte = 0; + config->linked_ptr = 0; + config->interrupt_mask = DMA_MGR_INTERRUPT_MASK_ALL; + config->en_infiniteloop = false; + config->handshake_opt = DMA_MGR_HANDSHAKE_OPT_ONE_BURST; + config->burst_opt = DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE; +} + +hpm_stat_t dma_mgr_setup_channel(const dma_resource_t *resource, dma_mgr_chn_conf_t *config) +{ + hpm_stat_t status; + uint32_t dmamux_ch; + dma_channel_config_t dma_config; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(resource->base, resource->channel); + dmamux_config(HPM_DMAMUX, dmamux_ch, config->dmamux_src, config->en_dmamux); + dma_config.priority = config->priority; + dma_config.src_burst_size = config->src_burst_size; + dma_config.src_mode = config->src_mode; + dma_config.dst_mode = config->dst_mode; + dma_config.src_width = config->src_width; + dma_config.dst_width = config->dst_width; + dma_config.src_addr_ctrl = config->src_addr_ctrl; + dma_config.dst_addr_ctrl = config->dst_addr_ctrl; + dma_config.src_addr = config->src_addr; + dma_config.dst_addr = config->dst_addr; + dma_config.size_in_byte = config->size_in_byte; + dma_config.linked_ptr = config->linked_ptr; + dma_config.interrupt_mask = config->interrupt_mask; +#ifdef DMA_MGR_HAS_INFINITE_LOOP + dma_config.en_infiniteloop = config->en_infiniteloop; +#endif +#ifdef DMA_MGR_HAS_HANDSHAKE_OPT + dma_config.handshake_opt = config->handshake_opt; +#endif +#ifdef DMA_MGR_HAS_BURST_OPT + dma_config.burst_opt = config->burst_opt; +#endif + status = dma_setup_channel(resource->base, resource->channel, &dma_config, false); + } + return status; +} + +hpm_stat_t dma_mgr_config_linked_descriptor(const dma_resource_t *resource, dma_mgr_chn_conf_t *config, dma_mgr_linked_descriptor_t *descriptor) +{ + hpm_stat_t status; + dma_channel_config_t dma_config; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_config.priority = config->priority; + dma_config.src_burst_size = config->src_burst_size; + dma_config.src_mode = config->src_mode; + dma_config.dst_mode = config->dst_mode; + dma_config.src_width = config->src_width; + dma_config.dst_width = config->dst_width; + dma_config.src_addr_ctrl = config->src_addr_ctrl; + dma_config.dst_addr_ctrl = config->dst_addr_ctrl; + dma_config.src_addr = config->src_addr; + dma_config.dst_addr = config->dst_addr; + dma_config.size_in_byte = config->size_in_byte; + dma_config.linked_ptr = config->linked_ptr; + dma_config.interrupt_mask = config->interrupt_mask; +#ifdef DMA_MGR_HAS_INFINITE_LOOP + dma_config.en_infiniteloop = config->en_infiniteloop; +#endif +#ifdef DMA_MGR_HAS_HANDSHAKE_OPT + dma_config.handshake_opt = config->handshake_opt; +#endif +#ifdef DMA_MGR_HAS_BURST_OPT + dma_config.burst_opt = config->burst_opt; +#endif + status = dma_config_linked_descriptor(resource->base, (dma_linked_descriptor_t *)descriptor, resource->channel, &dma_config); + } + return status; +} + +hpm_stat_t dma_mgr_enable_channel(const dma_resource_t *resource) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + status = dma_enable_channel(resource->base, resource->channel); + } + return status; +} + +hpm_stat_t dma_mgr_disable_channel(const dma_resource_t *resource) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_disable_channel(resource->base, resource->channel); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_check_chn_enable(const dma_resource_t *resource, bool *enable) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + *enable = dma_channel_is_enable(resource->base, resource->channel); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_enable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_enable_channel_interrupt(resource->base, resource->channel, irq_mask); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_disable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_disable_channel_interrupt(resource->base, resource->channel, irq_mask); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_priority(const dma_resource_t *resource, uint8_t priority) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_priority(resource->base, resource->channel, priority); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_src_work_mode(const dma_resource_t *resource, uint8_t mode) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_source_work_mode(resource->base, resource->channel, mode); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_dst_work_mode(const dma_resource_t *resource, uint8_t mode) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_destination_work_mode(resource->base, resource->channel, mode); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_src_burst_size(const dma_resource_t *resource, uint8_t burstsize) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_source_burst_size(resource->base, resource->channel, burstsize); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_get_chn_remaining_transize(const dma_resource_t *resource, uint32_t *size) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + *size = dma_get_remaining_transfer_size(resource->base, resource->channel); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_transize(const dma_resource_t *resource, uint32_t size) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_transfer_size(resource->base, resource->channel, size); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_src_width(const dma_resource_t *resource, uint8_t width) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_source_width(resource->base, resource->channel, width); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_dst_width(const dma_resource_t *resource, uint8_t width) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_destination_width(resource->base, resource->channel, width); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_src_addr(const dma_resource_t *resource, uint32_t addr) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_source_address(resource->base, resource->channel, addr); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_dst_addr(const dma_resource_t *resource, uint32_t addr) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_destination_address(resource->base, resource->channel, addr); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_src_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_source_address_ctrl(resource->base, resource->channel, addr_ctrl); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_dst_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_set_destination_address_ctrl(resource->base, resource->channel, addr_ctrl); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_infinite_loop_mode(const dma_resource_t *resource, bool infinite_loop) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { +#ifdef DMA_MGR_HAS_INFINITE_LOOP + dma_set_infinite_loop_mode(resource->base, resource->channel, infinite_loop); + status = status_success; +#else + status = status_fail; +#endif + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_src_busrt_option(const dma_resource_t *resource, uint8_t burst_opt) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { +#ifdef DMA_MGR_HAS_BURST_OPT + dma_set_src_busrt_option(resource->base, resource->channel, burst_opt); + status = status_success; +#else + status = status_fail; +#endif + } + return status; +} + +hpm_stat_t dma_mgr_set_chn_handshake_option(const dma_resource_t *resource, uint8_t handshake_opt) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { +#ifdef DMA_MGR_HAS_HANDSHAKE_OPT + dma_set_handshake_option(resource->base, resource->channel, handshake_opt); + status = status_success; +#else + status = status_fail; +#endif + } + return status; +} + +hpm_stat_t dma_mgr_abort_chn_transfer(const dma_resource_t *resource) +{ + hpm_stat_t status; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + status = status_invalid_argument; + } else { + dma_abort_channel(resource->base, 1u << resource->channel); + status = status_success; + } + return status; +} + +hpm_stat_t dma_mgr_check_chn_transfer_status(const dma_resource_t *resource, uint32_t *status) +{ + hpm_stat_t stat; + + dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); + + if (chn_ctx == NULL) { + stat = status_invalid_argument; + } else { + *status = dma_check_transfer_status(resource->base, resource->channel); + stat = status_success; + } + return stat; +} diff --git a/common/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.h b/common/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.h new file mode 100644 index 00000000..d7d16679 --- /dev/null +++ b/common/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.h @@ -0,0 +1,552 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_DMA_MGR_H +#define HPM_DMA_MGR_H + +#include "hpm_common.h" +#include "hpm_dmamux_drv.h" +#include "hpm_dmamux_src.h" +#ifdef CONFIG_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else +#include "hpm_dma_drv.h" +#endif +#include "hpm_soc_feature.h" + +#ifdef CONFIG_HAS_HPMSDK_DMAV2 +#define DMA_MGR_HAS_INFINITE_LOOP (1U) +#define DMA_MGR_HAS_HALF_TC_INT (1U) +#define DMA_MGR_HAS_HANDSHAKE_OPT (1U) +#define DMA_MGR_HAS_BURST_OPT (1U) +#endif + +#define DMA_MGR_CHANNEL_PRIORITY_LOW DMA_CHANNEL_PRIORITY_LOW +#define DMA_MGR_CHANNEL_PRIORITY_HIGH DMA_CHANNEL_PRIORITY_HIGH + +#define DMA_MGR_NUM_TRANSFER_PER_BURST_1T DMA_NUM_TRANSFER_PER_BURST_1T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_2T DMA_NUM_TRANSFER_PER_BURST_2T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_4T DMA_NUM_TRANSFER_PER_BURST_4T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_8T DMA_NUM_TRANSFER_PER_BURST_8T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_16T DMA_NUM_TRANSFER_PER_BURST_16T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_32T DMA_NUM_TRANSFER_PER_BURST_32T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_64T DMA_NUM_TRANSFER_PER_BURST_64T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_128T DMA_NUM_TRANSFER_PER_BURST_128T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_256T DMA_NUM_TRANSFER_PER_BURST_256T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_512T DMA_NUM_TRANSFER_PER_BURST_512T +#define DMA_MGR_NUM_TRANSFER_PER_BURST_1024T DMA_NUM_TRANSFER_PER_BURST_1024T + +#define DMA_MGR_TRANSFER_WIDTH_BYTE DMA_TRANSFER_WIDTH_BYTE +#define DMA_MGR_TRANSFER_WIDTH_HALF_WORD DMA_TRANSFER_WIDTH_HALF_WORD +#define DMA_MGR_TRANSFER_WIDTH_WORD DMA_TRANSFER_WIDTH_WORD +#define DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD DMA_TRANSFER_WIDTH_DOUBLE_WORD + +#define DMA_MGR_HANDSHAKE_MODE_NORMAL DMA_HANDSHAKE_MODE_NORMAL +#define DMA_MGR_HANDSHAKE_MODE_HANDSHAKE DMA_HANDSHAKE_MODE_HANDSHAKE + +#define DMA_MGR_ADDRESS_CONTROL_INCREMENT DMA_ADDRESS_CONTROL_INCREMENT +#define DMA_MGR_ADDRESS_CONTROL_DECREMENT DMA_ADDRESS_CONTROL_DECREMENT +#define DMA_MGR_ADDRESS_CONTROL_FIXED DMA_ADDRESS_CONTROL_FIXED + +#ifdef DMA_MGR_HAS_BURST_OPT +#define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE DMA_SRC_BURST_OPT_STANDAND_SIZE +#define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE DMA_SRC_BURST_OPT_CUSTOM_SIZE +#else +#define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE 0 +#define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE 0 +#endif + +#ifdef DMA_MGR_HAS_HANDSHAKE_OPT +#define DMA_MGR_HANDSHAKE_OPT_ONE_BURST DMA_HANDSHAKE_OPT_ONE_BURST +#define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE DMA_HANDSHAKE_OPT_ALL_TRANSIZE +#else +#define DMA_MGR_HANDSHAKE_OPT_ONE_BURST 0 +#define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE 0 +#endif + +#define DMA_MGR_CHANNEL_STATUS_ONGOING DMA_CHANNEL_STATUS_ONGOING +#define DMA_MGR_CHANNEL_STATUS_ERROR DMA_CHANNEL_STATUS_ERROR +#define DMA_MGR_CHANNEL_STATUS_ABORT DMA_CHANNEL_STATUS_ABORT +#define DMA_MGR_CHANNEL_STATUS_TC DMA_CHANNEL_STATUS_TC +#ifdef DMA_MGR_HAS_HALF_TC_INT +#define DMA_MGR_CHANNEL_STATUS_HALF_TC DMA_CHANNEL_STATUS_HALF_TC +#else +#define DMA_MGR_CHANNEL_STATUS_HALF_TC 0 +#endif +#define DMA_MGR_INTERRUPT_MASK_NONE DMA_INTERRUPT_MASK_NONE +#define DMA_MGR_INTERRUPT_MASK_ERROR DMA_INTERRUPT_MASK_ERROR +#define DMA_MGR_INTERRUPT_MASK_ABORT DMA_INTERRUPT_MASK_ABORT +#define DMA_MGR_INTERRUPT_MASK_TC DMA_INTERRUPT_MASK_TERMINAL_COUNT +#ifdef DMA_MGR_HAS_HALF_TC_INT +#define DMA_MGR_INTERRUPT_MASK_HALF_TC DMA_INTERRUPT_MASK_HALF_TC +#else +#define DMA_MGR_INTERRUPT_MASK_HALF_TC 0 +#endif +#define DMA_MGR_INTERRUPT_MASK_ALL DMA_INTERRUPT_MASK_ALL + +#ifdef __cplusplus + +extern "C" { +#endif + +/** + * @brief DMA Manager status codes + */ +enum { + status_dma_mgr_no_resource = MAKE_STATUS(status_group_dma_manager, 0), /**< No DMA resource available */ +}; + +/** + * @brief DMA Channel Interrupt callback + * + * @param [in] DMA base address + * @param [in] channel DMA channel index + * @param [in/out] cb_data_ptr callback Data pointer + */ +typedef void (*dma_mgr_chn_cb_t)(DMA_Type *base, uint32_t channel, void *cb_data_ptr); + +/** + * @brief DMA Resource Structure + */ +typedef struct _dma_resource { + DMA_Type *base; /**< The DMA intance that the allocated channel belongs to */ + uint32_t channel; /**< Channel index */ + int32_t irq_num; /**< DMA IRQ number */ +} dma_resource_t; + +typedef struct hpm_dma_mgr_chn_conf { + bool en_dmamux; /**< DMAMUX enable */ + uint8_t dmamux_src; /**< DMAMUX source */ + uint8_t priority; /**< Channel priority */ + uint8_t src_burst_size; /**< Source burst size */ + uint8_t src_mode; /**< Source work mode: 0-Normal, 1-Handshake */ + uint8_t dst_mode; /**< Destination work mode: 0-Normal, 1-Handshake */ + uint8_t src_width; /**< Source width */ + uint8_t dst_width; /**< Destination width */ + uint8_t src_addr_ctrl; /**< Source address control: 0-inc, 1-dec, 2-fix */ + uint8_t dst_addr_ctrl; /**< Destination address control: 0-inc, 1-dec, 2-fix */ + uint16_t interrupt_mask; /**< Interrupt mask */ + uint32_t src_addr; /**< Source address */ + uint32_t dst_addr; /**< Destination address */ + uint32_t linked_ptr; /**< Next linked descriptor */ + uint32_t size_in_byte; /**< Total size to be transferred in byte */ + bool en_infiniteloop; /**< Infinite loop transfer enable. Attention: only DMAV2 support */ + uint8_t handshake_opt; /**< Handshake transfer option. Attention: only DMAV2 support */ + uint8_t burst_opt; /**< Burst size option. Attention: only DMAV2 support */ +} dma_mgr_chn_conf_t; + +typedef struct hpm_dma_mgr_linked_descriptor { + uint32_t descriptor[8]; +} dma_mgr_linked_descriptor_t; + +/** + * @brief Initialize DMA Manager Context + */ +void dma_mgr_init(void); + +/** + * @brief Request DMA resource from DMA Manager + * + * @param [out] resource DMA resource + * @retval status_success if no error occurred + * @retval status_invalid_argument if the parameter is invalid + * @retval status_dma_mgr_no_resource if all DMA channels are occupied; + */ +hpm_stat_t dma_mgr_request_resource(dma_resource_t *resource); + +/** + * @brief Release DMA resource + * + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if the parameter is invalid + */ +hpm_stat_t dma_mgr_release_resource(const dma_resource_t *resource); + +/** + * @brief Enable DMA interrupt with priority + * @param [in] resource DMA resource + * @param [in] priority Interrupt Priority + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_enable_dma_irq_with_priority(const dma_resource_t *resource, uint32_t priority); + +/** + * @brief Disable DMA interrupt + * NOTE: Each DMA instance consists of several DMA channels, disabling the DMA interrupt + * will disable the global DMA interrupt for all DMA channels. Please be aware of the + * impact + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_disable_dma_irq(const dma_resource_t *resource); + +/** + * @brief Install Interrupt Callback for DMA channel transfer complete + * + * @param [in] resource DMA resource + * @param [in] callback Interrupt callback for DMA resource + * @param [in] user_data User data used in the callback + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_install_chn_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); + +/** + * @brief Install Interrupt Callback for DMA channel half transfer complete + * + * @param [in] resource DMA resource + * @param [in] callback Interrupt callback for DMA resource + * @param [in] user_data User data used in the callback + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_install_chn_half_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); + +/** + * @brief Install Interrupt Callback for DMA channel transfer error + * + * @param [in] resource DMA resource + * @param [in] callback Interrupt callback for DMA resource + * @param [in] user_data User data used in the callback + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_install_chn_error_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); + +/** + * @brief Install Interrupt Callback for DMA channel transfer abort + * + * @param [in] resource DMA resource + * @param [in] callback Interrupt callback for DMA resource + * @param [in] user_data User data used in the callback + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_install_chn_abort_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); + +/** + * @brief Get DMA channel default config + * + * @param [out] config config data pointer + */ +void dma_mgr_get_default_chn_config(dma_mgr_chn_conf_t *config); + +/** + * @brief Setup channel config + * + * @param [in] resource DMA resource + * @param [in] config DMA channel config + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_setup_channel(const dma_resource_t *resource, dma_mgr_chn_conf_t *config); + +/** + * @brief Setup chain linked descriptor config + * + * @param [in] resource DMA resource + * @param [in] config DMA channel config + * @param [out] descriptor linked descriptor config data pointer + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_config_linked_descriptor(const dma_resource_t *resource, dma_mgr_chn_conf_t *config, dma_mgr_linked_descriptor_t *descriptor); + +/** + * @brief Enable DMA channel, start transfer + * + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_enable_channel(const dma_resource_t *resource); + +/** + * @brief Disable DMA channel + * + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_disable_channel(const dma_resource_t *resource); + +/** + * @brief Check DMA channel enable status + * + * @param [in] resource DMA resource + * @param [out] enable enable status + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_check_chn_enable(const dma_resource_t *resource, bool *enable); + +/** + * @brief Enable DMA channel interrupt + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_enable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask); + +/** + * @brief Disable DMA channel interrupt + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_disable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask); + +/** + * @brief Set DMA channel priority + * + * @param [in] resource DMA resource + * @param [in] priority DMA channel priority + * @arg @ref DMA_MGR_PRIORITY_LOW + * @arg @ref DMA_MGR_PRIORITY_HIGH + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_priority(const dma_resource_t *resource, uint8_t priority); + +/** + * @brief Set DMA channel source work mode + * + * @param [in] resource DMA resource + * @param [in] mode DMA source work mode + * @arg @ref DMA_MGR_HANDSHAKE_MODE_NORMAL + * @arg @ref DMA_MGR_HANDSHAKE_MODE_HANDSHAKE + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_src_work_mode(const dma_resource_t *resource, uint8_t mode); + +/** + * @brief Set DMA channel destination work mode + * + * @param [in] resource DMA resource + * @param [in] mode DMA destination work mode + * @arg @ref DMA_MGR_HANDSHAKE_MODE_NORMAL + * @arg @ref DMA_MGR_HANDSHAKE_MODE_HANDSHAKE + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_dst_work_mode(const dma_resource_t *resource, uint8_t mode); + +/** + * @brief Set DMA channel source burst size + * + * @param [in] resource DMA resource + * @param [in] burstsize DMA source burst size + * when BURSTOPT is 0, please reference follows: + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_1T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_2T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_4T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_8T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_16T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_32T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_64T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_128T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_256T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_512T + * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_1024T + * when BURSTOPT is 1, burst size is (burstsize + 1). Attention: only DMAV2 support + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_src_burst_size(const dma_resource_t *resource, uint8_t burstsize); + +/** + * @brief Get DMA channel remaining transfer size + * + * @param [in] resource DMA resource + * @param [out] size remaining transfer size of the channel. + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_get_chn_remaining_transize(const dma_resource_t *resource, uint32_t *size); + +/** + * @brief Set DMA channel transfer size + * + * @param [in] resource DMA resource + * @param [in] size transfer size of the channel. + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_transize(const dma_resource_t *resource, uint32_t size); + +/** + * @brief Set DMA channel source width + * + * @param [in] resource DMA resource + * @param [in] width transfer source width of the channel + * @arg @ref DMA_MGR_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_MGR_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_MGR_TRANSFER_WIDTH_WORD + * @arg @ref DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_src_width(const dma_resource_t *resource, uint8_t width); + +/** + * @brief Set DMA channel destination width + * + * @param [in] resource DMA resource + * @param [in] width transfer destination width of the channel + * @arg @ref DMA_MGR_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_MGR_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_MGR_TRANSFER_WIDTH_WORD + * @arg @ref DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_dst_width(const dma_resource_t *resource, uint8_t width); + +/** + * @brief Set DMA channel source address + * + * @param [in] resource DMA resource + * @param [in] addr source address + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_src_addr(const dma_resource_t *resource, uint32_t addr); + +/** + * @brief Set DMA channel destination address + * + * @param [in] resource DMA resource + * @param [in] addr destination address + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_dst_addr(const dma_resource_t *resource, uint32_t addr); + +/** + * @brief Set DMA channel source address control mode + * + * @param [in] resource DMA resource + * @param [in] addr_ctrl source address control mode + * @arg @ref DMA_MGR_ADDRESS_CONTROL_INCREMENT + * @arg @ref DMA_MGR_ADDRESS_CONTROL_DECREMENT + * @arg @ref DMA_MGR_ADDRESS_CONTROL_FIXED + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_src_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl); + +/** + * @brief Set DMA channel destination address control mode + * + * @param [in] resource DMA resource + * @param [in] addr_ctrl destination address control mode + * @arg @ref DMA_MGR_ADDRESS_CONTROL_INCREMENT + * @arg @ref DMA_MGR_ADDRESS_CONTROL_DECREMENT + * @arg @ref DMA_MGR_ADDRESS_CONTROL_FIXED + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_dst_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl); + +/** + * @brief Set DMA channel infinite loop mode. Attention: only DMAV2 support + * + * @param [in] resource DMA resource + * @param [in] infinite_loop false - normal mode(single times mode); true - infinite loop mode(cycle mode) + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_infinite_loop_mode(const dma_resource_t *resource, bool infinite_loop); + +/** + * @brief Set DMA channel source burst option. Attention: only DMAV2 support + * + * @param [in] resource DMA resource + * @param [in] burst_opt burst option + * @arg @ref DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE + * @arg @ref DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_src_busrt_option(const dma_resource_t *resource, uint8_t burst_opt); + +/** + * @brief Set DMA channel handshake option. Attention: only DMAV2 support + * + * @param [in] resource DMA resource + * @param [in] handshake_opt handshake option + * @arg @ref DMA_HANDSHAKE_OPT_ONE_BURST + * @arg @ref DMA_HANDSHAKE_OPT_ALL_TRANSIZE + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_set_chn_handshake_option(const dma_resource_t *resource, uint8_t handshake_opt); + +/** + * @brief Abort DMA channel transfer + * + * @param [in] resource DMA resource + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_abort_chn_transfer(const dma_resource_t *resource); + +/** + * @brief Check DMA channel transfer status + * + * @param [in] resource DMA resource + * @param [out] sts transfer status + * DMA_MGR_CHANNEL_STATUS_ONGOING if transfer is still ongoing + * DMA_MGR_CHANNEL_STATUS_ERROR if any error occurred during transferring + * DMA_MGR_CHANNEL_STATUS_ABORT if transfer is aborted + * DMA_MGR_CHANNEL_STATUS_TC if transfer is finished without error + * DMA_MGR_CHANNEL_STATUS_HALF_TC if half transfer complete without error. Attention: only DMAV2 support + * + * @retval status_success if no error occurred + * @retval status_invalid_argument if any parameters are invalid + */ +hpm_stat_t dma_mgr_check_chn_transfer_status(const dma_resource_t *resource, uint32_t *status); + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_DMA_MGR_H */ diff --git a/common/libraries/hpm_sdk/components/eeprom_emulation/CMakeLists.txt b/common/libraries/hpm_sdk/components/eeprom_emulation/CMakeLists.txt new file mode 100644 index 00000000..e3b2f5c6 --- /dev/null +++ b/common/libraries/hpm_sdk/components/eeprom_emulation/CMakeLists.txt @@ -0,0 +1,19 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +set(EEPROM_USER_CONFIG_PATH ${APP_BIN_DIR}/..) +file(GLOB EEPROM_USER_CONFIG_EXIST "${EEPROM_USER_CONFIG_PATH}/user_config.h") + +if(EEPROM_USER_CONFIG_EXIST) + message(STATUS "eeprom emulation use custom config file") +else() + sdk_inc(config) + message(STATUS "eeprom emulation use default config file") +endif() + + +sdk_inc(.) +sdk_inc(port) +sdk_src(eeprom_emulation.c) +sdk_src(port/hpm_nor_flash.c) + diff --git a/common/libraries/hpm_sdk/components/eeprom_emulation/config/user_config.h b/common/libraries/hpm_sdk/components/eeprom_emulation/config/user_config.h new file mode 100644 index 00000000..b7498856 --- /dev/null +++ b/common/libraries/hpm_sdk/components/eeprom_emulation/config/user_config.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _USER_CONFIG_H +#define _USER_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define E2P_DEBUG_LEVEL (1) +#define E2P_CRITICAL_ENTER() do { disable_global_irq(CSR_MSTATUS_MIE_MASK); } while(0) +#define E2P_CRITICAL_EXIT() do { enable_global_irq(CSR_MSTATUS_MIE_MASK); } while(0) + +#define EEPROM_MAX_VAR_CNT (100) + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/eeprom_emulation/eeprom_emulation.c b/common/libraries/hpm_sdk/components/eeprom_emulation/eeprom_emulation.c new file mode 100644 index 00000000..15e1271d --- /dev/null +++ b/common/libraries/hpm_sdk/components/eeprom_emulation/eeprom_emulation.c @@ -0,0 +1,401 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#include + +#include "eeprom_emulation.h" +#include "hpm_crc32.h" + +#define E2P_OFFSET(TYPE, MEMBER) ((uint32_t)(&(((TYPE *)0)->MEMBER))) +#define E2P_SWAP(a, b)\ +do {\ + uint32_t tmp = (a);\ + (a) = (b);\ + (b) = tmp;\ +} while (0) + +static e2p_block e2p_info_table[E2P_MAX_VAR_CNT]; + +static void e2p_print_info(e2p_t *e2p) +{ + uint32_t info_count; + uint32_t valid_count = E2P_MAX_VAR_CNT; + + info_count = (e2p->config.start_addr + e2p->config.sector_cnt * e2p->config.erase_size - e2p->p_info) / sizeof(e2p_block) - 2; + for (int i = 0; i < E2P_MAX_VAR_CNT; i++) { + if (e2p_info_table[i].block_id == E2P_EARSED_ID) { + valid_count = i; + break; + } + } + + e2p_info("------------ flash->eeprom init ok -----------\n"); + e2p_info("start address: 0x%08x", e2p->config.start_addr); + e2p_info("sector count: %u", e2p->config.sector_cnt); + e2p_info("flash earse granularity: %u", e2p->config.erase_size); + e2p_info("version: 0x%x", e2p->config.version); + e2p_info("end address: 0x%08x", e2p->config.start_addr + e2p->config.sector_cnt * e2p->config.erase_size); + e2p_info("data write addr = 0x%08x, info write addr = 0x%08x, remain flash size = 0x%x\n", \ + e2p->p_data, e2p->p_info, e2p->remain_size); + e2p_info("valid count percent info count( %u / %u )\n", valid_count, info_count); + e2p_info("----------------------------------------------\n"); +} + +static hpm_stat_t e2p_table_update(e2p_block *block) +{ + uint32_t i = 0; + + if (block->valid_state == e2p_invalid) + return E2P_STATUS_OK; + + for ( ; i < E2P_MAX_VAR_CNT; i++) { + if (e2p_info_table[i].block_id == E2P_EARSED_ID) + break; + if (e2p_info_table[i].block_id == block->block_id) { + e2p_trace("block_id[0x%08x] multiple write, flush api solve repeat\n", block->block_id); + break; + } + } + + if (i == E2P_MAX_VAR_CNT) + return E2P_ERROR_MUL_VAR; + + memcpy(&e2p_info_table[i], block, sizeof(e2p_block)); + return E2P_STATUS_OK; +} + +static void e2p_config_info(e2p_t *e2p) +{ + e2p_block block; + e2p_config_t *cfg = &e2p->config; + uint32_t end_addr = cfg->start_addr + cfg->sector_cnt * cfg->erase_size; + + memset(&block, E2P_EARSED_VAR, sizeof(e2p_block)); + block.block_id = cfg->version; + block.data_addr = E2P_MAGIC_ID; + cfg->flash_write((uint8_t *)&block, end_addr - sizeof(e2p_block), sizeof(e2p_block)); + e2p_trace("e2p info has been config\n"); +} + +static uint32_t e2p_data_crc_calc(uint16_t length, uint8_t *data) +{ + return crc32(data, (uint32_t)length); +} + +static hpm_stat_t e2p_retrieve_info(uint32_t block_id, e2p_block *block) +{ + int i = 0; + + if (block_id == E2P_EARSED_ID) + return E2P_ERROR_BAD_ID; + + for ( ; i < E2P_MAX_VAR_CNT; i++) { + if (e2p_info_table[i].block_id == block_id) { + e2p_trace("find read block, pos at table[%u]\n", i); + memcpy(block, &e2p_info_table[i], sizeof(e2p_block)); + break; + } + } + + return (i == E2P_MAX_VAR_CNT ? E2P_ERROR_BAD_ID : E2P_STATUS_OK); +} + + +static hpm_stat_t e2p_write_private(e2p_t *e2p, uint32_t block_id, uint16_t length, uint8_t *data) +{ + int ret = 0; + e2p_block block; + e2p_config_t *cfg = &e2p->config; + + if (e2p->remain_size < length + sizeof(e2p_block)) { + e2p_trace("no enough flash\n"); + return E2P_ERROR_NO_MEM; + } + + block.block_id = block_id; + block.data_addr = e2p->p_data; + block.length = length; + block.valid_state = e2p_valid; + block.crc = e2p_data_crc_calc(length, data); + + if (E2P_STATUS_OK != cfg->flash_write(data, e2p->p_data, length)) { + e2p_trace("flash write data error\n"); + return E2P_ERROR; + } + e2p->p_data += length; + e2p->remain_size -= length; + + if (E2P_STATUS_OK != cfg->flash_write((uint8_t *)&block, e2p->p_info, sizeof(e2p_block))) { + e2p_trace("flash write info error\n"); + return E2P_ERROR; + } + e2p->p_info -= sizeof(e2p_block); + e2p->remain_size -= sizeof(e2p_block); + + ret = e2p_table_update(&block); + if (E2P_STATUS_OK != ret) + return ret; + + e2p_info("block_id[0x%08x] success write, data addr=0x%08x, remain size=0x%08x crc=0x%08x\n", block.block_id, block.data_addr, e2p->remain_size, block.crc); + return E2P_STATUS_OK; +} + +static int e2p_info_table_sort(void) +{ + int count = 0; + e2p_block block; + + do { + if (e2p_info_table[count].block_id == E2P_EARSED_ID) { + break; + } + count++; + } while (count < E2P_MAX_VAR_CNT); + + if (count == 0) + return count; + + for (int i = 0; i < count; i++) { + memcpy(&block, &e2p_info_table[i], sizeof(e2p_block)); + for (int j = i + 1; j < count; j++) { + if (e2p_info_table[j].data_addr < block.data_addr) { + E2P_SWAP(e2p_info_table[j].block_id, block.block_id); + E2P_SWAP(e2p_info_table[j].data_addr, block.data_addr); + E2P_SWAP(e2p_info_table[j].length, block.length); + E2P_SWAP(e2p_info_table[j].valid_state, block.valid_state); + E2P_SWAP(e2p_info_table[j].crc, block.crc); + } + } + memcpy(&e2p_info_table[i], &block, sizeof(e2p_block)); + } + + return count; +} + +static void e2p_earse_info_sector(e2p_t *e2p) +{ + uint32_t data_sec_num, info_sec_num; + uint32_t addr, size; + e2p_config_t *cfg = &e2p->config; + + data_sec_num = (e2p->p_data - cfg->start_addr) / cfg->erase_size; + info_sec_num = (e2p->p_info - cfg->start_addr) / cfg->erase_size; + addr = e2p->p_info - (e2p->p_info % cfg->erase_size); + size = (cfg->sector_cnt - info_sec_num) * cfg->erase_size; + + e2p_trace("data_sector=%u, info_sector=%u, addr=0x%08x, size=0x%08x", data_sec_num, info_sec_num, addr, size); + + if (data_sec_num < info_sec_num) { + cfg->flash_erase(addr, size); + } else { + uint8_t data_buf[cfg->erase_size]; + uint32_t remain_size = e2p->p_info % cfg->erase_size; + memset(data_buf, E2P_EARSED_VAR, sizeof(data_buf)); + + e2p_trace("data tail[0x%08x] and info tail[0x%08x] in same sector\n", e2p->p_data, e2p->p_info); + cfg->flash_read(data_buf, addr, remain_size); + cfg->flash_erase(addr, size); + cfg->flash_write(data_buf, addr, sizeof(data_buf)); + } +} + +hpm_stat_t e2p_config(e2p_t *e2p) +{ + if (e2p->config.erase_size == 0 || e2p->config.sector_cnt == 0) { + e2p_info("config error erase_size = %u, sector_cnt = %u\n", e2p->config.erase_size, e2p->config.sector_cnt); + return E2P_ERROR_INIT_ERR; + } + + if (e2p->config.flash_read == NULL || e2p->config.flash_write == NULL || e2p->config.flash_erase == NULL) { + e2p_info("Not register operate function read = %p, write = %p, erase = %p", \ + e2p->config.flash_read, e2p->config.flash_write, e2p->config.flash_erase); + return E2P_ERROR_INIT_ERR; + } + + e2p_block block; + e2p_config_t *cfg = &e2p->config; + + e2p->p_data = cfg->start_addr; + e2p->p_info = cfg->start_addr + cfg->sector_cnt * cfg->erase_size - 2 * sizeof(e2p_block); + e2p->remain_size = e2p->p_info - e2p->p_data; + memset(e2p_info_table, E2P_EARSED_VAR, sizeof(e2p_info_table)); + + cfg->flash_read((uint8_t *)&block, e2p->p_info + sizeof(e2p_block), sizeof(e2p_block)); + e2p_trace("read data, block_id=%x, addr=%x, length=%x, valid_state=%x, crc=%x\n", \ + block.block_id, block.data_addr, block.length, block.valid_state, block.crc); + + if (block.block_id != cfg->version || block.data_addr != E2P_MAGIC_ID) { + e2p_info("check version failed, begin earse all sector, it will take some time\n"); + cfg->flash_erase(e2p->p_data, cfg->sector_cnt * cfg->erase_size); + e2p_config_info(e2p); + e2p_print_info(e2p); + return E2P_STATUS_OK; + } + + while (1) { + block.data_addr = e2p->p_info; + block.length = sizeof(e2p_block); + + cfg->flash_read((uint8_t *)&block, block.data_addr, block.length); + if (block.block_id == E2P_EARSED_ID) + break; + + int ret = e2p_table_update(&block); + if (E2P_STATUS_OK != ret) + return ret; + + e2p->p_data += block.length; + e2p->p_info -= sizeof(e2p_block); + e2p->remain_size -= (block.length + sizeof(e2p_block)); + + if (e2p->remain_size < 2 * sizeof(e2p_block)) { + e2p_trace("remain flash is not enough\n"); + return E2P_ERROR_NO_MEM; + } + } + + e2p_print_info(e2p); + return E2P_STATUS_OK; +} + +hpm_stat_t e2p_flush(e2p_t *e2p, uint8_t flag) +{ + if (e2p->config.erase_size < e2p->remain_size && flag == 0) { + e2p_trace("no need arrange flash\n"); + return E2P_STATUS_OK; + } + e2p_config_t *cfg = &e2p->config; + + e2p_earse_info_sector(e2p); + + e2p->p_data = cfg->start_addr; + e2p->p_info = cfg->start_addr + cfg->sector_cnt * cfg->erase_size - 2 * sizeof(e2p_block); + e2p->remain_size = e2p->p_info - e2p->p_data; + + int read_len = 0; + int count = 0; + uint32_t head, tail; + uint8_t read_buf[cfg->erase_size * 2]; + int valid_num = e2p_info_table_sort(); + + tail = e2p->p_data; + for (int i = 0; i < valid_num;) { + head = tail; + + while (1) { + if (e2p_info_table[i].block_id == E2P_EARSED_ID || i >= valid_num) { + e2p_trace("e2p blank[%u], need flush num[%u]\n", i, valid_num); + break; + } + cfg->flash_read(read_buf + read_len, e2p_info_table[i].data_addr, e2p_info_table[i].length); + read_len += e2p_info_table[i].length; + tail = e2p_info_table[i].data_addr + e2p_info_table[i].length; + i++; + if (read_len >= cfg->erase_size) + break; + } + + e2p_trace("---- transfer data to buffer: len=%u\n", read_len); + + do { + cfg->flash_erase(head, cfg->erase_size); + head += cfg->erase_size; + } while (head + cfg->erase_size <= tail); + + tail = head; + uint8_t *pdata = read_buf; + while (count < i) { + if (e2p_info_table[count].block_id == E2P_EARSED_ID || e2p->p_data + e2p_info_table[i].length >= tail) { + e2p_trace("write back suspend, write stop at 0x%08x/0x0%x\n", e2p->p_data, read_len); + break; + } + + e2p_write_private(e2p, e2p_info_table[count].block_id, e2p_info_table[count].length, pdata); + pdata += e2p_info_table[count].length; + count++; + } + + e2p_trace("-----write data back: len=%u\n", pdata - read_buf); + + read_len -= (pdata - read_buf); + if (read_len) + memmove(read_buf, pdata, read_len); + } + + while (tail < e2p->p_info - cfg->erase_size) { + cfg->flash_erase(tail, cfg->erase_size); + tail += cfg->erase_size; + } + + uint8_t *ptr = read_buf; + while (read_len) { + e2p_trace("remain write back[%u], block_id[%x], data_addr[%x], length[%u], valid_state[%u], crc[%x]\n", \ + count, e2p_info_table[count].block_id, e2p_info_table[count].data_addr, e2p_info_table[count].length, e2p_info_table[count].valid_state, e2p_info_table[count].crc); + e2p_write_private(e2p, e2p_info_table[count].block_id, e2p_info_table[count].length, ptr); + read_len -= e2p_info_table[count].length; + ptr += e2p_info_table[count].length; + count++; + } + + e2p_config_info(e2p); + return E2P_STATUS_OK; +} + +hpm_stat_t e2p_write(e2p_t *e2p, uint32_t block_id, uint16_t length, uint8_t *data) +{ + if (e2p->remain_size < length + sizeof(e2p_block)) { + e2p_flush(e2p, E2P_FLUSH_BEGIN); + if (e2p->remain_size < length + sizeof(e2p_block)) { + e2p_trace("no enough flash write\n"); + return E2P_ERROR_NO_MEM; + } + } + + return e2p_write_private(e2p, block_id, length, data); +} + +hpm_stat_t e2p_read(e2p_t *e2p, uint32_t block_id, uint16_t length, uint8_t *data) +{ + e2p_block block; + int ret = 0; + + ret = e2p_retrieve_info(block_id, &block); + if (ret != E2P_STATUS_OK) + return ret; + + uint8_t tmp[block.length]; + e2p->config.flash_read(tmp, block.data_addr, block.length); + + if (block.crc != e2p_data_crc_calc(block.length, tmp)) { + e2p_trace("crc check error, data addr = 0x%08x, crc = 0x%08x", block.data_addr, block.crc); + return E2P_ERROR; + } + + length > block.length ? (length=block.length) : length; + memmove(data, tmp, length); + return E2P_STATUS_OK; +} + +void e2p_format(e2p_t *e2p) +{ + e2p_config_t *cfg = &e2p->config; + + cfg->flash_erase(cfg->start_addr, cfg->sector_cnt * cfg->erase_size); +} + +uint32_t e2p_generate_id(const char *name) +{ + return (name[0] << 24) | (name[1] << 16) | (name[2] << 8) | (name[3]); +} + + +void e2p_show_info(e2p_t *e2p) +{ + e2p_print_info(e2p); +} diff --git a/common/libraries/hpm_sdk/components/eeprom_emulation/eeprom_emulation.h b/common/libraries/hpm_sdk/components/eeprom_emulation/eeprom_emulation.h new file mode 100644 index 00000000..f878155e --- /dev/null +++ b/common/libraries/hpm_sdk/components/eeprom_emulation/eeprom_emulation.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _EEPROM_EMULATION_H +#define _EEPROM_EMULATION_H + +#include +#include "user_config.h" +#include "hpm_nor_flash.h" +#include "hpm_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define E2P_DEBUG_LEVEL_TRACE (0) +#define E2P_DEBUG_LEVEL_INFO (1) +#define E2P_DEBUG_LEVEL_WARN (2) +#define E2P_DEBUG_LEVEL_ERROR (3) + +#ifndef E2P_DEBUG_TRACE +# if E2P_DEBUG_LEVEL <= E2P_DEBUG_LEVEL_TRACE +# define E2P_TRACE(fmt, ...) printf("%s: %d: debug: "fmt"%s\n", __func__, __LINE__, __VA_ARGS__) +# define e2p_trace(...) E2P_TRACE(__VA_ARGS__, "") +# else +# define e2p_trace(...) +# endif +#endif + +#ifndef E2P_DEBUG_INFO +# if E2P_DEBUG_LEVEL <= E2P_DEBUG_LEVEL_INFO +# define E2P_INFO(fmt, ...) printf(""fmt"%s\n", __VA_ARGS__) +# define e2p_info(...) E2P_INFO(__VA_ARGS__, "") +# else +# define e2p_info(...) +# endif +#endif + +#ifndef E2P_DEBUG_WARN +# if E2P_DEBUG_LEVEL <= E2P_DEBUG_LEVEL_WARN +# define E2P_WARN(fmt, ...) printf(""fmt"%s\n", __VA_ARGS__) +# define e2p_warn(...) E2P_WARN(__VA_ARGS__, "") +# else +# define e2p_warn(...) +# endif +#endif + +#ifndef E2P_DEBUG_ERROR +# if E2P_DEBUG_LEVEL <= E2P_DEBUG_LEVEL_ERROR +# define E2P_ERR(fmt, ...) printf(""fmt"%s\n", __VA_ARGS__) +# define e2p_err(...) E2P_ERR(__VA_ARGS__, "") +# else +# define e2p_err(...) +# endif +#endif + +#define E2P_MAX_VAR_CNT (100) +#ifdef EEPROM_MAX_VAR_CNT +#undef E2P_MAX_VAR_CNT +#define E2P_MAX_VAR_CNT EEPROM_MAX_VAR_CNT +#endif + +typedef enum { + e2p_invalid = 0xCCCC, + e2p_valid = 0xEEEE, + e2p_earsed = 0xFFFF, +} e2p_valid_state; + +enum { + E2P_STATUS_OK = 0, + E2P_ERROR, + E2P_ERROR_NO_MEM, + E2P_ERROR_INIT_ERR, + E2P_ERROR_BAD_ID, + E2P_ERROR_BAD_ADDR, + E2P_ERROR_MUL_VAR, +}; + +typedef struct { + uint32_t block_id; + uint32_t data_addr; + uint16_t length; + e2p_valid_state valid_state; + uint32_t crc; +} e2p_block; + +typedef struct { + uint32_t start_addr; + uint32_t sector_cnt; + uint16_t erase_size; + uint32_t version; + + uint32_t (*flash_read)(uint8_t *buf, uint32_t addr, uint32_t size); + uint32_t (*flash_write)(uint8_t *buf, uint32_t addr, uint32_t size); + void (*flash_erase)(uint32_t start_addr, uint32_t size); +} e2p_config_t; + +typedef struct { + e2p_config_t config; + nor_flash_config_t nor_config; + + uint32_t p_data; + uint32_t p_info; + uint32_t remain_size; +} e2p_t; + +#define E2P_MAGIC_ID (0x48504D43) /*'H' 'P' 'M' 'C'*/ + +#define E2P_EARSED_ID (0xFFFFFFFF) +#define E2P_EARSED_VAR (0xFF) + +#define E2P_FLUSH_TRY (0) +#define E2P_FLUSH_BEGIN (1) + +/** + * @brief eeprom emulation config + * + * @param e2p instance context + * @return hpm_stat_t + */ +hpm_stat_t e2p_config(e2p_t *e2p); + +/** + * @brief eeprom emulation flush whole area, remove redundancy + * + * @param e2p instance context + * @param flag E2P_FLUSH_TRY - conditional flush, E2P_FLUSH_BEGIN - force flush + * @return hpm_stat_t + */ +hpm_stat_t e2p_flush(e2p_t *e2p, uint8_t flag); + +/** + * @brief eeprom emulation write + * + * @param e2p instance context + * @param block_id custom id + * @param length data length + * @param data + * @return hpm_stat_t + */ +hpm_stat_t e2p_write(e2p_t *e2p, uint32_t block_id, uint16_t length, uint8_t *data); + +/** + * @brief eeprom emulation read + * + * @param e2p instance context + * @param block_id custom id + * @param length data length + * @param data + * @return hpm_stat_t + */ +hpm_stat_t e2p_read(e2p_t *e2p, uint32_t block_id, uint16_t length, uint8_t *data); + +/** + * @brief generate custom id + * + * @param name + * @return uint32_t + */ +uint32_t e2p_generate_id(const char *name); + +/** + * @brief format whole area, 0xFF + * + * @param e2p + */ +void e2p_format(e2p_t *e2p); + +/** + * @brief show e2p instance info include config info and store info + * + * @param e2p + */ +void e2p_show_info(e2p_t *e2p); + +/* + e2p_t demo = { + .config.start_addr = 0x80080000, + .config.erase_size = 4096, + .config.sector_cnt = 128, + .config.version = 0x4553, + .config.flash_read = flash_read, + .config.flash_write = flash_write, + .config.flash_erase = flash_erase, + }; + + + int main(void) + { + e2p_config(&demo); + + + ... + ... + } + +*/ + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/eeprom_emulation/port/hpm_nor_flash.c b/common/libraries/hpm_sdk/components/eeprom_emulation/port/hpm_nor_flash.c new file mode 100644 index 00000000..8c1ecf7e --- /dev/null +++ b/common/libraries/hpm_sdk/components/eeprom_emulation/port/hpm_nor_flash.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_nor_flash.h" +#include "hpm_l1c_drv.h" +#include "board.h" + +hpm_stat_t nor_flash_init(nor_flash_config_t *cfg) +{ + xpi_nor_config_option_t option; + + option.header.U = cfg->opt_header; + option.option0.U = cfg->opt0; + option.option1.U = cfg->opt1; + hpm_stat_t status = rom_xpi_nor_auto_config(cfg->xpi_base, &cfg->nor_config, &option); + if (status != status_success) { + return status; + } + + rom_xpi_nor_get_property(cfg->xpi_base, &cfg->nor_config, xpi_nor_property_sector_size, &cfg->sector_size); + + return status_success; +} + +hpm_stat_t nor_flash_read(nor_flash_config_t *cfg, uint8_t *buf, uint32_t addr, uint32_t size) +{ + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + + l1c_dc_invalidate(aligned_start, aligned_size); + + memcpy(buf, (void *)addr, size); + return status_success; +} + +hpm_stat_t nor_flash_write(nor_flash_config_t *cfg, uint8_t *buf, uint32_t addr, uint32_t size) +{ + addr > cfg->base_addr ? (addr -= cfg->base_addr) : addr; + hpm_stat_t status = rom_xpi_nor_program(cfg->xpi_base, xpi_xfer_channel_auto, \ + &cfg->nor_config, (const uint32_t *)buf, addr, size); + + return status; +} + +static hpm_stat_t nor_flash_erase_sector(nor_flash_config_t *cfg, uint32_t start_addr) +{ + start_addr > cfg->base_addr ? (start_addr -= cfg->base_addr) : start_addr; + hpm_stat_t status = rom_xpi_nor_erase_sector(cfg->xpi_base, xpi_xfer_channel_auto, &cfg->nor_config, start_addr); + + return status; +} + +void nor_flash_erase(nor_flash_config_t *cfg, uint32_t start_addr, uint32_t size) +{ + uint32_t sector_size = cfg->sector_size; + for (int i = 0; i < size / sector_size; i++) { + nor_flash_erase_sector(cfg, start_addr + i * sector_size); + } +} diff --git a/common/libraries/hpm_sdk/components/eeprom_emulation/port/hpm_nor_flash.h b/common/libraries/hpm_sdk/components/eeprom_emulation/port/hpm_nor_flash.h new file mode 100644 index 00000000..04fa9e63 --- /dev/null +++ b/common/libraries/hpm_sdk/components/eeprom_emulation/port/hpm_nor_flash.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef _HPM_NOR_FLASH_H +#define _HPM_NOR_FLASH_H + +#include +#include "hpm_common.h" +#include "hpm_romapi.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + XPI_Type *xpi_base; + uint32_t base_addr; + uint32_t sector_size; + uint32_t opt_header; + uint32_t opt0; + uint32_t opt1; + xpi_nor_config_t nor_config; +} nor_flash_config_t; + +/** + * @brief hpm nor-flash initialization + * + * @param[in] cfg config_context + * @return hpm_stat_t + */ +hpm_stat_t nor_flash_init(nor_flash_config_t *cfg); + +/** + * @brief hpm nor-flash read function + * + * @param[in] cfg config_context + * @param[out] buf store read data + * @param[in] addr read physical start addr + * @param[in] size read bytes size + * @return hpm_stat_t + */ +hpm_stat_t nor_flash_read(nor_flash_config_t *cfg, uint8_t *buf, uint32_t addr, uint32_t size); + +/** + * @brief hpm nor-flash write function + * + * @param[in] cfg config_context + * @param[in] buf data to be written + * @param[in] addr write physical start addr + * @param[in] size write bytes size + * @return hpm_stat_t + */ +hpm_stat_t nor_flash_write(nor_flash_config_t *cfg, uint8_t *buf, uint32_t addr, uint32_t size); + +/** + * @brief hpm nor-flash erase function + * + * @param[in] cfg config_context + * @param[in] start_addr erase physical start addr + * @param[in] size erase bytes size + */ +void nor_flash_erase(nor_flash_config_t *cfg, uint32_t start_addr, uint32_t size); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/enet_phy/dp83848/CMakeLists.txt b/common/libraries/hpm_sdk/components/enet_phy/dp83848/CMakeLists.txt index cc8969e2..7ad3ead7 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/dp83848/CMakeLists.txt +++ b/common/libraries/hpm_sdk/components/enet_phy/dp83848/CMakeLists.txt @@ -1,7 +1,6 @@ -# Copyright (c) 2021 HPMicro +# Copyright (c) 2021-2023 HPMicro # SPDX-License-Identifier: BSD-3-Clause -sdk_compile_definitions(-DRGMII=0) sdk_compile_definitions(-D__USE_DP83848=1) sdk_inc(.) diff --git a/common/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h b/common/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h index f5c28c45..1cf60162 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h +++ b/common/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h @@ -10,17 +10,21 @@ #if defined(__USE_DP83867) && __USE_DP83867 #include "hpm_dp83867.h" #include "hpm_dp83867_regs.h" -#elif defined(__USE_RTL8211) && __USE_RTL8211 +#endif + +#if defined(__USE_RTL8211) && __USE_RTL8211 #include "hpm_rtl8211.h" #include "hpm_rtl8211_regs.h" -#elif defined(__USE_DP83848) && __USE_DP83848 +#endif + +#if defined(__USE_DP83848) && __USE_DP83848 #include "hpm_dp83848.h" #include "hpm_dp83848_regs.h" -#elif defined(__USE_RTL8201) && __USE_RTL8201 +#endif + +#if defined(__USE_RTL8201) && __USE_RTL8201 #include "hpm_rtl8201.h" #include "hpm_rtl8201_regs.h" -#else - #error no specified Ethernet PHY !!! #endif #endif /* HPM_ENET_PHY_H */ diff --git a/common/libraries/hpm_sdk/components/enet_phy/rtl8201/CMakeLists.txt b/common/libraries/hpm_sdk/components/enet_phy/rtl8201/CMakeLists.txt index d2374d00..7f7e3686 100644 --- a/common/libraries/hpm_sdk/components/enet_phy/rtl8201/CMakeLists.txt +++ b/common/libraries/hpm_sdk/components/enet_phy/rtl8201/CMakeLists.txt @@ -1,7 +1,6 @@ -# Copyright (c) 2021-2022 HPMicro +# Copyright (c) 2021-2023 HPMicro # SPDX-License-Identifier: BSD-3-Clause -sdk_compile_definitions(-DRGMII=0) sdk_compile_definitions(-D__USE_RTL8201=1) sdk_inc(.) diff --git a/common/libraries/hpm_sdk/components/serial_nor/CMakeLists.txt b/common/libraries/hpm_sdk/components/serial_nor/CMakeLists.txt new file mode 100644 index 00000000..0357b1c5 --- /dev/null +++ b/common/libraries/hpm_sdk/components/serial_nor/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +add_subdirectory_ifdef(CONFIG_SPI_NOR_FLASH interface/spi) + +sdk_inc(.) +sdk_src(hpm_serial_nor.c) + diff --git a/common/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.c b/common/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.c new file mode 100644 index 00000000..014aec1d --- /dev/null +++ b/common/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.c @@ -0,0 +1,1170 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_serial_nor.h" +#include "hpm_clock_drv.h" + +#ifndef SERIALNOR_CMD_PAGE_PROGRAM_1_1_4_3B +#define SERIALNOR_CMD_PAGE_PROGRAM_1_1_4_3B (0x32U) +#endif + +#ifndef SERIALNOR_CMD_READ_SDR_1_2_2_4B +#define SERIALNOR_CMD_READ_SDR_1_2_2_4B (0xBCU) +#endif + +#ifndef SERIALNOR_CMD_READ_SDR_1_2_2_3B +#define SERIALNOR_CMD_READ_SDR_1_2_2_3B (0xBBU) +#endif + +#ifndef SERIALNOR_CMD_READ_SDR_1_1_2_3B +#define SERIALNOR_CMD_READ_SDR_1_1_2_3B (0x3BU) +#endif + +#ifndef SERIALNOR_CMD_READ_SDR_1_1_2_4B +#define SERIALNOR_CMD_READ_SDR_1_1_2_4B (0x3CU) +#endif + +#ifndef SERIALNOR_CMD_WRITE_STATUS_REG3 +#define SERIALNOR_CMD_WRITE_STATUS_REG3 (0x11U) +#endif + +#ifndef SERIALNOR_CMD_READ_STATUS_REG3 +#define SERIALNOR_CMD_READ_STATUS_REG3 (0x15U) +#endif + +#ifndef kSERIALNOR_CMD_WRITE_STATUS_REG2_VIA_0X31 +#define kSERIALNOR_CMD_WRITE_STATUS_REG2_VIA_0X31 (0x31U) +#endif + + +#ifndef kSERIALNOR_CMD_READ_STATUS_REG2_VIA_0X31 +#define kSERIALNOR_CMD_READ_STATUS_REG2_VIA_0X31 (0x35U) +#endif + + +#define MAX_24BIT_ADDRESSING_SIZE ((1UL << 24)) +#define MAX_24BIT_ADDR_SIZE_IN_KBYTES ((1UL << 24) / SIZE_1KB) + +#define SPI_READ_SFDP_FREQUENCY (10000000U) + +/** + * @brief QE bit enable sequence option + */ +typedef enum { + spi_nor_quad_en_auto_or_ignore = 0U, /**< Auto enable or ignore */ + spi_nor_quad_en_set_bit6_in_status_reg1 = 1U, /**< QE bit is at bit6 in Status register 1 */ + spi_nor_quad_en_set_bit1_in_status_reg2 = 2U, /**< QE bit is at bit1 in Status register 2 register 2 */ + spi_nor_quad_en_set_bit7_in_status_reg2 = 3U, /**< QE bit is at bit7 in Status register 2 */ + spi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd = 4U, /**< QE bit is in status register 2 and configured by CMD 0x31 */ +} spi_nor_quad_enable_seq_t; + +static hpm_stat_t hpm_serial_nor_read_sfdp_info(hpm_serial_nor_t *flash, jedec_info_table_t *tbl, bool address_shift_enable); +static hpm_stat_t hpm_spi_get_read_para(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info); +static hpm_stat_t hpm_spi_get_program_para(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info); +static hpm_stat_t hpm_spi_nor_read_sfdp(hpm_serial_nor_t *flash, uint32_t addr, + uint32_t *buffer, uint32_t bytes); +static hpm_stat_t hpm_spi_nor_set_command(hpm_serial_nor_t *flash, uint8_t cmd); +static hpm_stat_t get_page_sector_block_size_from_sfdp(hpm_serial_nor_info_t *config, jedec_info_table_t *tbl); +static hpm_stat_t hpm_spi_nor_read_status_register(hpm_serial_nor_t *flash, uint8_t *reg_data, uint8_t status_reg); +static hpm_stat_t hpm_spi_nor_write_status_register(hpm_serial_nor_t *flash, uint8_t reg_data, uint8_t status_reg); +static hpm_stat_t prepare_quad_mode_enable_sequence(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info); + +__attribute__((weak)) void hpm_spi_nor_udelay(uint32_t us) +{ + clock_cpu_delay_us(us); +} + +static hpm_stat_t hpm_spi_get_read_para(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info) +{ + uint32_t address_bits; + uint32_t dummy_cycles = 0; + uint8_t mode_cycles = 0; + uint8_t dummy_count = 0; + jedec_flash_param_table_t *param_tbl = &jedec_info->flash_param_tbl; + jedec_4byte_addressing_inst_table_t *flash_4b_tbl = &jedec_info->flash_4b_inst_tbl; + flash->nor_read_para.data_phase_format = quad_io_mode; + flash->nor_read_para.addr_phase_format = single_io_mode; + flash->nor_read_para.data_dummy_count = 1; + address_bits = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + if (address_bits == 32) { + flash->nor_read_para.addr_bit = flash_addrlen_32bit; + } else { + flash->nor_read_para.addr_bit = flash_addrlen_24bit; + } + + if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) { + if (address_bits == 24U) { + if (param_tbl->misc.supports_1_4_4_fast_read != 0U) { + flash->nor_read_para.read_cmd = param_tbl->read_1_4_info.inst_1_4_4_read; + } else if (param_tbl->misc.support_1_1_4_fast_read != 0U) { + flash->nor_read_para.read_cmd = param_tbl->read_1_4_info.inst_1_1_4_read; + } else { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_3B; + dummy_cycles = 0; + mode_cycles = 0; + } + } else { + if (jedec_info->has_4b_addressing_inst_table) { + if (flash_4b_tbl->cmd_4byte_support_info.support_1_4_4_fast_read != 0U) { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_4_4_4B; + flash->nor_read_para.addr_phase_format = quad_io_mode; + } else if (flash_4b_tbl->cmd_4byte_support_info.support_1_1_4_fast_read != 0U) { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_1_4_4B; + } else { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_4B; + dummy_cycles = 0; + mode_cycles = 0; + } + } else if (param_tbl->misc.supports_1_4_4_fast_read != 0U) { /* For device that is only compliant with JESD216 */ + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_4_4_4B; + } else if (param_tbl->misc.support_1_1_4_fast_read != 0U) { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_1_4_4B; + } else { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_4B; + dummy_cycles = 0; + mode_cycles = 0; + } + } + } else if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_DUAL_IO_MODE) { + if (address_bits == 24U) { + if (param_tbl->misc.support_1_2_2_fast_read != 0U) { + flash->nor_read_para.read_cmd = param_tbl->read_1_2_info.inst_1_2_2_read; + flash->nor_read_para.data_phase_format = dual_io_mode; + } else if (param_tbl->misc.support_1_1_2_fast_read != 0U) { + flash->nor_read_para.read_cmd = param_tbl->read_1_2_info.inst_1_1_2_read; + } else { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_3B; + dummy_cycles = 0; + mode_cycles = 0; + } + } else { + if (jedec_info->has_4b_addressing_inst_table) { + if (flash_4b_tbl->cmd_4byte_support_info.support_1_2_2_fast_read != 0U) { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_2_2_4B; + flash->nor_read_para.data_phase_format = dual_io_mode; + } else if (flash_4b_tbl->cmd_4byte_support_info.support_1_1_2_fast_read != 0U) { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_1_2_4B; + flash->nor_read_para.data_phase_format = dual_io_mode; + } else { + flash->nor_read_para.data_phase_format = single_io_mode; + flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_4B; + dummy_cycles = 0; + mode_cycles = 0; + } + } else if (param_tbl->misc.support_1_2_2_fast_read != 0U) { /* For device that is only compliant with JESD216 */ + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_2_2_4B; + flash->nor_read_para.data_phase_format = dual_io_mode; + } else if (param_tbl->misc.support_1_1_2_fast_read != 0U) { + flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_1_2_4B; + flash->nor_read_para.data_phase_format = dual_io_mode; + } else { + flash->nor_read_para.data_phase_format = single_io_mode; + flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_4B; + dummy_cycles = 0; + mode_cycles = 0; + } + } + + } else { + flash->nor_read_para.read_cmd = (address_bits == 32U) ? SERIALNOR_CMD_BASICREAD_4B : SERIALNOR_CMD_BASICREAD_3B; + flash->nor_read_para.data_phase_format = single_io_mode; + flash->nor_read_para.data_dummy_count = 0; + dummy_cycles = 0; + mode_cycles = 0; + } + + /* Determine Read command based on SFDP */ + if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) { + if (param_tbl->misc.supports_1_4_4_fast_read != 0U) { + flash->nor_read_para.addr_phase_format = quad_io_mode; + mode_cycles = param_tbl->read_1_4_info.mode_clocks_1_4_4_read; + dummy_cycles = param_tbl->read_1_4_info.dummy_clocks_1_4_4_read; + } else if (param_tbl->misc.support_1_1_4_fast_read != 0U) { + mode_cycles = param_tbl->read_1_4_info.mode_clocks_1_1_4_read; + dummy_cycles = param_tbl->read_1_4_info.dummy_clocks_1_1_4_read; + } else { + /* Reserved for future use */ + } + } else if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_DUAL_IO_MODE) { + if (param_tbl->misc.support_1_2_2_fast_read != 0U) { + flash->nor_read_para.addr_phase_format = dual_io_mode; + mode_cycles = param_tbl->read_1_2_info.mode_clocks_1_2_2_read; + dummy_cycles = param_tbl->read_1_2_info.dummy_clocks_1_2_2_read; + } else if (param_tbl->misc.support_1_1_2_fast_read != 0U) { + flash->nor_read_para.addr_phase_format = single_io_mode; + mode_cycles = param_tbl->read_1_2_info.mode_clocks_1_1_2_read; + dummy_cycles = param_tbl->read_1_2_info.dummy_clocks_1_1_2_read; + } else { + /* Reserved for future use */ + } + } + + if ((dummy_cycles) && (!(flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_SINGLE_IO_MODE))) { + if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_DUAL_IO_MODE) { + dummy_count = ((dummy_cycles + mode_cycles) / 4); + } else { + dummy_count = ((dummy_cycles + mode_cycles) / 2); + } + /* SPI is only support 4 dummy count*/ + if (dummy_count > 5) { + flash->nor_read_para.data_phase_format = single_io_mode; + flash->nor_read_para.addr_phase_format = single_io_mode; + flash->nor_read_para.read_cmd = (address_bits == 32U) ? SERIALNOR_CMD_BASICREAD_4B : SERIALNOR_CMD_BASICREAD_3B; + } else { + flash->nor_read_para.data_dummy_count = dummy_count; + } + } + return status_success; +} + +static hpm_stat_t hpm_spi_get_program_para(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info) +{ + jedec_4byte_addressing_inst_table_t *flash_4b_tbl; + flash_4b_tbl = &jedec_info->flash_4b_inst_tbl; + flash->nor_program_para.has_4b_addressing_inst_table = jedec_info->has_4b_addressing_inst_table; + flash->nor_program_para.support_1_1_4_page_program = flash_4b_tbl->cmd_4byte_support_info.support_1_1_4_page_program; + flash->nor_program_para.support_1_4_4_page_program = flash_4b_tbl->cmd_4byte_support_info.support_1_4_4_page_program; + return status_success; +} + +static hpm_stat_t hpm_spi_nor_read_sfdp(hpm_serial_nor_t *flash, uint32_t addr, uint32_t *buffer, uint32_t bytes) +{ + hpm_serial_nor_transfer_seq_t command_seq = {0}; + command_seq.use_dma = false; + command_seq.cmd_phase.cmd = SERIAL_FLASH_READ_SFDP; + command_seq.addr_phase.addr = addr; + command_seq.addr_phase.enable = true; + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.dummy_phase.dummy_count = 1; + command_seq.data_phase.direction = read_direction; + command_seq.data_phase.data_io_mode = single_io_mode; + command_seq.data_phase.buf = (uint8_t *)buffer; + command_seq.data_phase.len = bytes; + return flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); +} + +static hpm_stat_t hpm_spi_nor_set_command(hpm_serial_nor_t *flash, uint8_t cmd) +{ + hpm_serial_nor_transfer_seq_t command_seq = {0}; + command_seq.use_dma = false; + command_seq.cmd_phase.cmd = cmd; + return flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); +} + +static hpm_stat_t get_page_sector_block_size_from_sfdp(hpm_serial_nor_info_t *config, jedec_info_table_t *tbl) +{ + hpm_stat_t status = status_invalid_argument; + jedec_flash_param_table_t *param_tbl = &tbl->flash_param_tbl; + jedec_4byte_addressing_inst_table_t *flash_4b_tbl = &tbl->flash_4b_inst_tbl; + + /* Calculate Flash Size */ + uint32_t flash_size; + uint32_t flash_density = tbl->flash_param_tbl.flash_density; + uint32_t page_size; + uint32_t sector_size = 0xFFFFFFUL; + uint32_t block_size = 0U; + uint32_t block_erase_type = 0U; + uint32_t sector_erase_type = 0U; + + if (IS_HPM_BIT_SET(flash_density, 31)) { + /* Flash size >= 4G bits */ + flash_size = 1UL << ((flash_density & ~(1UL << 0x1F)) - 3U); + } else { + /* Flash size < 4G bits */ + flash_size = (flash_density + 1U) >> 3; + } + + do { + HPM_BREAK_IF(flash_size < 1U); + config->size_in_kbytes = flash_size / SIZE_1KB; + /* Calculate Page size */ + if (tbl->flash_param_tbl_size < SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVA) { + config->page_size = 256U; + } else { + page_size = 1UL << (param_tbl->chip_erase_progrm_info.page_size); + config->page_size = (page_size == (1UL << 15)) ? 256U : page_size; + } + /* Calculate Sector Size */ + for (uint32_t index = 0; index < 4U; index++) { + if (param_tbl->erase_info[index].size != 0U) { + uint32_t current_erase_size = 1UL << param_tbl->erase_info[index].size; + if (current_erase_size < SIZE_1KB) { + continue; + } + if (current_erase_size < sector_size) { + sector_size = current_erase_size; + sector_erase_type = index; + } + if ((current_erase_size > block_size) && (current_erase_size < (1024U * 1024U))) { + block_size = current_erase_size; + block_erase_type = index; + } + } + } + + config->sector_size_kbytes = sector_size / SIZE_1KB; + + config->block_size_kbytes = block_size / SIZE_1KB; + + if (flash_size > MAX_24BIT_ADDRESSING_SIZE) { + if (tbl->has_4b_addressing_inst_table) { + config->sector_erase_cmd = flash_4b_tbl->erase_inst_info.erase_inst[sector_erase_type]; + config->block_erase_cmd = flash_4b_tbl->erase_inst_info.erase_inst[block_erase_type]; + } else { + switch (param_tbl->erase_info[sector_erase_type].inst) { + case SERIALNOR_CMD_SE4K_3B: + config->sector_erase_cmd = SERIALNOR_CMD_SE4K_4B; + break; + case SERIALNOR_CMD_SE64K_3B: + config->sector_erase_cmd = SERIALNOR_CMD_SE64K_4B; + break; + default: + /* Reserved for future use */ + break; + } + switch (param_tbl->erase_info[block_erase_type].inst) { + case SERIALNOR_CMD_SE4K_3B: + config->block_erase_cmd = SERIALNOR_CMD_SE4K_4B; + break; + case SERIALNOR_CMD_SE64K_3B: + config->block_erase_cmd = SERIALNOR_CMD_SE64K_4B; + break; + default: + /* Reserved for future use */ + break; + } + } + } else { + config->sector_erase_cmd = param_tbl->erase_info[sector_erase_type].inst; + config->block_erase_cmd = param_tbl->erase_info[block_erase_type].inst; + } + + status = status_success; + + } while (false); + + return status; +} + +static hpm_stat_t hpm_spi_nor_read_status_register(hpm_serial_nor_t *flash, uint8_t *reg_data, uint8_t status_reg) +{ + hpm_serial_nor_transfer_seq_t command_seq = {0}; + command_seq.use_dma = false; + command_seq.cmd_phase.cmd = status_reg; + command_seq.data_phase.direction = read_direction; + command_seq.data_phase.buf = reg_data; + command_seq.data_phase.data_io_mode = single_io_mode; + command_seq.data_phase.len = sizeof(uint8_t); + return flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); +} + +static hpm_stat_t hpm_spi_nor_write_status_register(hpm_serial_nor_t *flash, uint8_t reg_data, uint8_t status_reg) +{ + hpm_stat_t stat; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + } + + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + command_seq.use_dma = false; + command_seq.cmd_phase.cmd = status_reg; + command_seq.data_phase.direction = write_direction; + command_seq.data_phase.buf = (uint8_t *)®_data; + command_seq.data_phase.data_io_mode = single_io_mode; + command_seq.data_phase.len = sizeof(uint8_t); + return flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); +} + +static hpm_stat_t prepare_quad_mode_enable_sequence(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info) +{ + hpm_stat_t status = status_success; + uint8_t status_val = 0; + uint8_t read_status_reg = 0; + uint8_t write_status_reg = 0; + /* See JESD216B 6.4.18 for more details. */ + do { + /* Enter Quad mode */ + spi_nor_quad_enable_seq_t enter_quad_mode_option = spi_nor_quad_en_auto_or_ignore; + /* Ideally, we only need one condition here, however, for some Flash devices that actually support JESD216A + * before the standard is publicly released, the JESD minor revision is still the initial version. That is why + * we use two conditions to handle below logic. + */ + if ((jedec_info->standard_version >= SFDP_VERSION_MINOR_A) || + (jedec_info->flash_param_tbl_size >= SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVA)) { + switch (jedec_info->flash_param_tbl.mode_4_4_info.quad_enable_requirement) { + case 1: + case 4: + case 5: + enter_quad_mode_option = spi_nor_quad_en_set_bit1_in_status_reg2; + break; + case 6: + enter_quad_mode_option = spi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd; + break; + case 2: + enter_quad_mode_option = spi_nor_quad_en_set_bit6_in_status_reg1; + break; + case 3: + enter_quad_mode_option = spi_nor_quad_en_set_bit7_in_status_reg2; + break; + default: + enter_quad_mode_option = spi_nor_quad_en_auto_or_ignore; + flash->flash_info.en_dev_mode_cfg = 0; + break; + } + } else { + /* Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 reads based on instruction */ + enter_quad_mode_option = spi_nor_quad_en_auto_or_ignore; + status = status_spi_nor_flash_not_qe_bit_in_sfdp; + } + /* Retrieve the read status command */ + if (enter_quad_mode_option != spi_nor_quad_en_auto_or_ignore) { + + switch (enter_quad_mode_option) { + case spi_nor_quad_en_set_bit1_in_status_reg2: + case spi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd: + read_status_reg = kSERIALNOR_CMD_READ_STATUS_REG2_VIA_0X31; + break; + case spi_nor_quad_en_set_bit6_in_status_reg1: + read_status_reg = SERIALNOR_CMD_READ_STATUS_REG1; + break; + case spi_nor_quad_en_set_bit7_in_status_reg2: + read_status_reg = SERIALNOR_CMD_READ_STATUS_REG2; + break; + default: + /* Reserved for future use */ + break; + } + status = hpm_spi_nor_read_status_register(flash, &status_val, read_status_reg); + HPM_BREAK_IF(status != status_success); + + /* Do modify-after-read status and then create Quad mode Enable sequence + * Enable QE bit only if it is not enabled. + */ + flash->flash_info.en_dev_mode_cfg = 0; + switch (enter_quad_mode_option) { + case spi_nor_quad_en_set_bit6_in_status_reg1: + if (!IS_HPM_BIT_SET(status_val, 6)) { + write_status_reg = SERIALNOR_CMD_WRITE_STATUS_REG1; + status_val &= (uint8_t) ~0x3cU; /* Clear Block protection */ + status_val |= HPM_BITSMASK(1U, 6); + status = hpm_spi_nor_write_status_register(flash, status_val, write_status_reg); + HPM_BREAK_IF(status != status_success); + flash->flash_info.en_dev_mode_cfg = 1U; + } + break; + case spi_nor_quad_en_set_bit1_in_status_reg2: + if (!IS_HPM_BIT_SET(status_val, 1)) { + write_status_reg = SERIALNOR_CMD_WRITE_STATUS_REG1; + status_val |= HPM_BITSMASK(1U, 1); + /* QE bit will be programmed after status1 register, so need to left shit 8 bit */ + status_val <<= 8; + status = hpm_spi_nor_write_status_register(flash, status_val, write_status_reg); + HPM_BREAK_IF(status != status_success); + flash->flash_info.en_dev_mode_cfg = 1U; + } + break; + case spi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd: + if (!IS_HPM_BIT_SET(status_val, 1)) { + write_status_reg = kSERIALNOR_CMD_WRITE_STATUS_REG2_VIA_0X31; + status_val |= HPM_BITSMASK(1U, 1); + status = hpm_spi_nor_write_status_register(flash, status_val, write_status_reg); + HPM_BREAK_IF(status != status_success); + flash->flash_info.en_dev_mode_cfg = 1U; + } + break; + case spi_nor_quad_en_set_bit7_in_status_reg2: + if (!IS_HPM_BIT_SET(status_val, 7)) { + write_status_reg = SERIALNOR_CMD_WRITE_STATUS_REG2; + status_val |= HPM_BITSMASK(1U, 7); + status = hpm_spi_nor_write_status_register(flash, status_val, write_status_reg); + HPM_BREAK_IF(status != status_success); + flash->flash_info.en_dev_mode_cfg = 1U; + } + break; + default: + flash->flash_info.en_dev_mode_cfg = 0U; + break; + } + } + } while (false); + + return status; +} + +static hpm_stat_t hpm_serial_nor_read_sfdp_info(hpm_serial_nor_t *flash, jedec_info_table_t *tbl, bool address_shift_enable) +{ + hpm_stat_t status = status_spi_nor_sfdp_not_found; + do { + sfdp_header_t sfdp_header; + uint32_t address; + uint32_t parameter_header_number; + uint32_t max_hdr_count; + uint32_t parameter_id; + uint32_t table_size; + + status = hpm_spi_nor_read_sfdp(flash, 0, &sfdp_header.words[0], sizeof(sfdp_header)); + HPM_BREAK_IF(status != status_success); + + if (sfdp_header.signature != SFDP_SIGNATURE) { + status = status_spi_nor_sfdp_not_found; + break; + } + + parameter_header_number = (uint32_t) sfdp_header.param_hdr_num + 1U; + + sfdp_parameter_header_t sfdp_param_hdrs[10]; + (void) memset(&sfdp_param_hdrs, 0, sizeof(sfdp_param_hdrs)); + max_hdr_count = parameter_header_number > 10U ? 10U : parameter_header_number; + address = 0x08U; + if (address_shift_enable) { + address <<= 8; + } + status = hpm_spi_nor_read_sfdp(flash, address, &sfdp_param_hdrs[0].words[0], + max_hdr_count * sizeof(sfdp_parameter_header_t)); + HPM_BREAK_IF(status != status_success); + + (void) memset(tbl, 0, sizeof(*tbl)); + + /* Save the standard version for later use. */ + tbl->standard_version = sfdp_header.minor_rev; + + for (uint32_t i = 0; i < max_hdr_count; i++) { + parameter_id = sfdp_param_hdrs[i].parameter_id_lsb + ((uint32_t) sfdp_param_hdrs[i].parameter_id_msb << 8); + + if ((parameter_id == PARAMETER_ID_BASIC_SPIPROTOCOL) || + (parameter_id == PARAMETER_ID_4BYTEADDRESS_INSTRUCTION_TABLE) || + (parameter_id == PARAMETER_ID_CMDSEQ_CHANGE_TO_OCTAL_DDR) || + (parameter_id == PARAMETER_ID_XSPIPROFILE1_0) || (parameter_id == PARAMETER_ID_STACTRLCFGREGMAP)) { + address = 0; + for (int32_t index = 2; index >= 0; index--) { + address <<= 8; + address |= sfdp_param_hdrs[i].parameter_table_pointer[index]; + } + table_size = (uint32_t) sfdp_param_hdrs[i].table_length_in_32bit * sizeof(uint32_t); + + if (address_shift_enable) { + address <<= 8; + } + + if (parameter_id == PARAMETER_ID_BASIC_SPIPROTOCOL) { + /* Limit table size to the max supported standard */ + if (table_size > sizeof(jedec_flash_param_table_t)) { + table_size = sizeof(jedec_flash_param_table_t); + } + status = hpm_spi_nor_read_sfdp(flash, address, &tbl->flash_param_tbl.words[0], table_size); + HPM_BREAK_IF(status != status_success); + + tbl->flash_param_tbl_size = table_size; + } else if (parameter_id == PARAMETER_ID_4BYTEADDRESS_INSTRUCTION_TABLE) { + status = hpm_spi_nor_read_sfdp(flash, address, &tbl->flash_4b_inst_tbl.words[0], table_size); + HPM_BREAK_IF(status != status_success); + + tbl->has_4b_addressing_inst_table = true; + } else if (parameter_id == PARAMETER_ID_CMDSEQ_CHANGE_TO_OCTAL_DDR) { + status = hpm_spi_nor_read_sfdp(flash, address, &tbl->otcal_ddr_mode_enable_sequence.words[0], + sizeof(jedec_cmd_sequence_change_to_octal_mode_t)); + HPM_BREAK_IF(status != status_success); + + tbl->has_otcal_ddr_mode_enable_sequence_table = true; + } else if (parameter_id == PARAMETER_ID_XSPIPROFILE1_0) { + status = hpm_spi_nor_read_sfdp(flash, address, &tbl->profile1_0_table.words[0], + sizeof(jedec_x_spi_profile1_0_table_t)); + HPM_BREAK_IF(status != status_success); + + tbl->has_spi_profile1_0_table = true; + } else if (parameter_id == PARAMETER_ID_STACTRLCFGREGMAP) { + status = hpm_spi_nor_read_sfdp(flash, address, &tbl->sccr_map.words[0], + sizeof(jedec_status_control_configuration_reg_map_t)); + HPM_BREAK_IF(status != status_success); + + tbl->has_sccr_map = true; + } else { + /* Reserved for future use */ + } + } else { + /* Unsupported parameter type, ignore */ + } + } + + } while (false); + + return status; +} + +hpm_stat_t hpm_serial_nor_is_busy(hpm_serial_nor_t *flash) +{ + uint8_t sr = 0; + hpm_stat_t stat; + if (flash == NULL) { + return status_invalid_argument; + } + stat = hpm_spi_nor_read_status_register(flash, &sr, SERIALNOR_CMD_READ_STATUS_REG1); + if (stat != status_success) { + return stat; + } + return (sr & 0b1) ? status_spi_nor_flash_is_busy : status_success; +} + +hpm_stat_t hpm_serial_nor_write_enable(hpm_serial_nor_t *flash) +{ + hpm_stat_t stat; + uint8_t cmd; + if (flash == NULL) { + return status_invalid_argument; + } + cmd = SERIALNOR_CMD_WRITEENABLE; + stat = hpm_spi_nor_set_command(flash, cmd); + if (stat != status_success) { + return stat; + } + hpm_spi_nor_udelay(1); + return stat; +} + +hpm_stat_t hpm_serial_nor_erase_chip(hpm_serial_nor_t *flash) +{ + hpm_stat_t stat; + uint8_t cmd; + if (flash == NULL) { + return status_invalid_argument; + } + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + + cmd = SERIALNOR_CMD_CHIPERASE; + stat = hpm_spi_nor_set_command(flash, cmd); + if (stat != status_success) { + return stat; + } + + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + return stat; +} + +hpm_stat_t hpm_serial_nor_erase_block_blocking(hpm_serial_nor_t *flash, uint32_t block_addr) +{ + hpm_stat_t stat; + uint8_t cmd; + uint32_t addr; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + + if (flash == NULL) { + return status_invalid_argument; + } + + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + cmd = flash->flash_info.block_erase_cmd; + addr = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + if (addr == 32) { + command_seq.addr_phase.addr_bit = flash_addrlen_32bit; + } else { + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + } + command_seq.addr_phase.enable = true; + command_seq.cmd_phase.cmd = cmd; + command_seq.addr_phase.addr = block_addr; + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.dummy_phase.dummy_count = 0; + command_seq.use_dma = false; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + + if (stat != status_success) { + return stat; + } + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + return stat; +} + +hpm_stat_t hpm_serial_nor_erase_sector_blocking(hpm_serial_nor_t *flash, uint32_t sector_addr) +{ + hpm_stat_t stat; + uint32_t addr; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + if (flash == NULL) { + return status_invalid_argument; + } + + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + + addr = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + command_seq.cmd_phase.cmd = flash->flash_info.sector_erase_cmd; + if (addr == 32) { + command_seq.addr_phase.addr_bit = flash_addrlen_32bit; + } else { + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + } + command_seq.addr_phase.enable = true; + command_seq.addr_phase.addr = sector_addr; + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.use_dma = false; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + if (stat != status_success) { + return stat; + } + + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + return stat; +} + +hpm_stat_t hpm_serial_nor_erase_block_noblocking(hpm_serial_nor_t *flash, uint32_t block_addr) +{ + hpm_stat_t stat; + uint32_t addr; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + + if (flash == NULL) { + return status_invalid_argument; + } + + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + + addr = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + if (addr == 32) { + command_seq.addr_phase.addr_bit = flash_addrlen_32bit; + } else { + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + } + command_seq.addr_phase.enable = true; + command_seq.addr_phase.addr = block_addr; + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.cmd_phase.cmd = flash->flash_info.block_erase_cmd; + command_seq.use_dma = false; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + if (stat != status_success) { + return stat; + } + return stat; +} + +hpm_stat_t hpm_serial_nor_erase_sector_noblocking(hpm_serial_nor_t *flash, uint32_t sector_addr) +{ + hpm_stat_t stat; + uint32_t addr; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + + if (flash == NULL) { + return status_invalid_argument; + } + + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + + addr = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + if (addr == 32) { + command_seq.addr_phase.addr_bit = flash_addrlen_32bit; + } else { + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + } + command_seq.addr_phase.enable = true; + command_seq.addr_phase.addr = sector_addr; + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.cmd_phase.cmd = flash->flash_info.sector_erase_cmd; + command_seq.use_dma = false; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + if (stat != status_success) { + return stat; + } + + return stat; +} + +hpm_stat_t hpm_serial_nor_erase_blocking(hpm_serial_nor_t *flash, uint32_t start, uint32_t length) +{ + hpm_stat_t status = status_invalid_argument; + uint32_t sector_size; + uint32_t block_size; + uint32_t aligned_start; + uint32_t aligned_len; + uint32_t remaining_len; + if (flash == NULL) { + return status_invalid_argument; + } + do { + sector_size = flash->flash_info.sector_size_kbytes * 1024U; + block_size = flash->flash_info.block_size_kbytes * 1024U; + aligned_start = HPM_ALIGN_DOWN(start, sector_size); + aligned_len = HPM_ALIGN_UP(start + length, sector_size) - aligned_start; + + /* If erase address is not block aligned */ + remaining_len = aligned_len; + while (remaining_len > 0U) { + if ((aligned_start % block_size != 0U) || (remaining_len < block_size)) { + status = hpm_serial_nor_erase_sector_blocking(flash, aligned_start); + HPM_BREAK_IF(status != status_success); + aligned_start += sector_size; + remaining_len -= sector_size; + } else { + status = hpm_serial_nor_erase_block_blocking(flash, aligned_start); + HPM_BREAK_IF(status != status_success); + aligned_start += block_size; + remaining_len -= block_size; + } + } + } while (false); + return status; +} + +hpm_stat_t hpm_serial_nor_program_blocking(hpm_serial_nor_t *flash, uint8_t *buf, uint32_t data_len, uint32_t address) +{ + hpm_stat_t stat = status_success; + uint32_t program_size = 0; + uint32_t offset_in_page; + uint32_t remaining_page_size; + uint8_t *src_8; + uint32_t address_bits; + uint32_t offset; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + + if ((buf == NULL) || (data_len == 0) || (flash == NULL)) { + return status_invalid_argument; + } + + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.data_phase.data_io_mode = quad_io_mode; + do { + HPM_BREAK_IF(data_len > (flash->flash_info.size_in_kbytes * SIZE_1KB)); + + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + + offset_in_page = address % flash->flash_info.page_size; + remaining_page_size = flash->flash_info.page_size - offset_in_page; + address_bits = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + if (address_bits == 32) { + command_seq.addr_phase.addr_bit = flash_addrlen_32bit; + if ((flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) && (flash->nor_program_para.has_4b_addressing_inst_table)) { + if (flash->nor_program_para.support_1_4_4_page_program == true) { + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_4_4_4B; + command_seq.addr_phase.addr_io_mode = dual_io_mode; + } else if (flash->nor_program_para.support_1_1_4_page_program == true) { + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_4_4B; + } else { + /* 1_1_1_page_program */ + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B; + command_seq.data_phase.data_io_mode = single_io_mode; + } + } else { /* Only consider 1-1-1 Program */ + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B; + command_seq.data_phase.data_io_mode = single_io_mode; + } + } else { + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + flash->nor_program_para.page_program_cmd = (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) ? + SERIALNOR_CMD_PAGE_PROGRAM_1_1_4_3B : SERIALNOR_CMD_PAGEPROGRAM_1_1_1_3B; + + command_seq.data_phase.data_io_mode = (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) ? + quad_io_mode : single_io_mode; + } + command_seq.cmd_phase.cmd = flash->nor_program_para.page_program_cmd; + command_seq.data_phase.direction = write_direction; + command_seq.use_dma = true; + command_seq.addr_phase.enable = true; + while (data_len > 0) { + /* Send page program command */ + program_size = MIN(data_len, remaining_page_size); + /* Ensure the address doesn't across page boundary */ + offset = address % flash->flash_info.page_size; + HPM_BREAK_IF((offset + program_size) > flash->flash_info.page_size); + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + command_seq.addr_phase.addr = address; + command_seq.data_phase.buf = buf; + command_seq.data_phase.len = program_size; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + + HPM_BREAK_IF(stat != status_success); + stat = status_spi_nor_flash_is_busy; + while (stat == status_spi_nor_flash_is_busy) { + stat = hpm_serial_nor_is_busy(flash); + if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { + return stat; + } else { + if (stat == status_success) { + break; + } else { + if (stat == status_success) { + break; + } else { + hpm_spi_nor_udelay(1); + } + } + } + } + /* Get the new address and length for next iteration */ + address += program_size; + data_len -= program_size; + remaining_page_size = flash->flash_info.page_size; + src_8 = (uint8_t *) buf + program_size; + buf = (uint8_t *) src_8; + } + } while (false); + return stat; +} + +hpm_stat_t hpm_serial_nor_page_program_noblocking(hpm_serial_nor_t *flash, uint8_t *buf, uint32_t data_len, uint32_t address) +{ + hpm_stat_t stat = status_success; + uint32_t program_size = 0; + uint32_t offset_in_page; + uint32_t remaining_page_size; + uint32_t address_bits; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + + if ((buf == NULL) || (data_len == 0) || (flash == NULL)) { + return status_invalid_argument; + } + + command_seq.addr_phase.addr_io_mode = single_io_mode; + command_seq.data_phase.data_io_mode = quad_io_mode; + offset_in_page = address % flash->flash_info.page_size; + remaining_page_size = flash->flash_info.page_size - offset_in_page; + program_size = MIN(data_len, remaining_page_size); + if ((data_len > flash->flash_info.page_size) || + ((offset_in_page + program_size) > flash->flash_info.page_size)) { + return status_invalid_argument; + } + + do { + offset_in_page = address % flash->flash_info.page_size; + remaining_page_size = flash->flash_info.page_size - offset_in_page; + address_bits = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; + if (address_bits == 32) { + command_seq.addr_phase.addr_bit = flash_addrlen_32bit; + if ((flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) && (flash->nor_program_para.has_4b_addressing_inst_table)) { + if (flash->nor_program_para.support_1_4_4_page_program > 0U) { + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_4_4_4B; + command_seq.addr_phase.addr_io_mode = dual_io_mode; + } else if (flash->nor_program_para.support_1_1_4_page_program > 0U) { + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_4_4B; + } else { + /* 1_1_1_page_program */ + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B; + command_seq.data_phase.data_io_mode = single_io_mode; + } + } else { /* Only consider 1-1-1 Program */ + flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B; + command_seq.data_phase.data_io_mode = single_io_mode; + } + } else { + command_seq.addr_phase.addr_bit = flash_addrlen_24bit; + flash->nor_program_para.page_program_cmd = (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) ? + SERIALNOR_CMD_PAGE_PROGRAM_1_1_4_3B : SERIALNOR_CMD_PAGEPROGRAM_1_1_1_3B; + + command_seq.data_phase.data_io_mode = (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) ? + quad_io_mode : single_io_mode; + } + command_seq.cmd_phase.cmd = flash->nor_program_para.page_program_cmd; + stat = hpm_serial_nor_write_enable(flash); + if (stat != status_success) { + return stat; + } + command_seq.use_dma = true; + command_seq.addr_phase.addr = address; + command_seq.data_phase.buf = buf; + command_seq.data_phase.len = program_size; + command_seq.data_phase.direction = write_direction; + command_seq.addr_phase.enable = true; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + HPM_BREAK_IF(stat != status_success); + } while (false); + + return stat; +} + +hpm_stat_t hpm_serial_nor_read(hpm_serial_nor_t *flash, uint8_t *buf, uint16_t data_len, uint32_t address) +{ + hpm_stat_t stat; + hpm_serial_nor_transfer_seq_t command_seq = {0}; + uint32_t read_start = address; + + if ((buf == NULL) || (data_len == 0) || (flash == NULL)) { + return status_invalid_argument; + } + + command_seq.addr_phase.addr = read_start; + command_seq.addr_phase.addr_bit = flash->nor_read_para.addr_bit; + command_seq.addr_phase.addr_io_mode = flash->nor_read_para.addr_phase_format; + command_seq.dummy_phase.dummy_count = flash->nor_read_para.data_dummy_count; + command_seq.data_phase.data_io_mode = flash->nor_read_para.data_phase_format; + command_seq.data_phase.buf = buf; + command_seq.data_phase.len = data_len; + command_seq.cmd_phase.cmd = flash->nor_read_para.read_cmd; + command_seq.data_phase.direction = read_direction; + command_seq.use_dma = true; + command_seq.addr_phase.enable = true; + stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); + return stat; +} + + +hpm_stat_t hpm_serial_nor_init(hpm_serial_nor_t *flash, hpm_serial_nor_info_t *info) +{ + jedec_info_table_t jedec_info; + hpm_stat_t stat; + if (flash == NULL) { + return status_invalid_argument; + } + if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_SPI_INTERFACE) { + serial_nor_host_ops_use_spi(flash); + } else { + /* Reserved for use by other interfaces */ + } + flash->host.host_ops.user_data = &flash->host; + flash->host.host_ops.init(flash->host.host_ops.user_data); + /* in order to ensure read sfdp parameter are correct, spi frequency must be less than 50M, and here,default value is 20M */ + flash->host.host_ops.set_frequency(flash->host.host_ops.user_data, SPI_READ_SFDP_FREQUENCY); + stat = hpm_serial_nor_read_sfdp_info(flash, &jedec_info, false); + if (stat != status_success) { + return stat; + } + flash->host.host_ops.set_frequency(flash->host.host_ops.user_data, flash->host.host_param.param.frequency); + get_page_sector_block_size_from_sfdp(&flash->flash_info, &jedec_info); + memcpy(info, &flash->flash_info, sizeof(hpm_serial_nor_info_t)); + if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) { + stat = prepare_quad_mode_enable_sequence(flash, &jedec_info); + flash->flash_info.sfdp_version = jedec_info.standard_version; + info->sfdp_version = jedec_info.standard_version; + if (stat != status_success) { + flash->host.host_param.flags &= ~SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE | SERIAL_NOR_HOST_SUPPORT_SINGLE_IO_MODE; + } + } + hpm_spi_get_read_para(flash, &jedec_info); + hpm_spi_get_program_para(flash, &jedec_info); + return stat; +} + +hpm_stat_t hpm_serial_nor_get_info(hpm_serial_nor_t *flash, hpm_serial_nor_info_t *info) +{ + if (flash == NULL) { + return status_invalid_argument; + } + memcpy(info, &flash->flash_info, sizeof(hpm_serial_nor_info_t)); + return status_success; +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.h b/common/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.h new file mode 100644 index 00000000..bcd81e4f --- /dev/null +++ b/common/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_SERIAL_NOR_H +#define _HPM_SERIAL_NOR_H + +#include "hpm_serial_nor_host.h" + +/** + * @brief spi nor API error codes + */ +enum { + status_spi_nor_sfdp_not_found = MAKE_STATUS(status_group_spi_nor_flash, 0), /**< SFDP table was not found */ + status_spi_nor_ddr_read_dummy_cycle_probe_failed = MAKE_STATUS(status_group_spi_nor_flash, 1), /**< Probing Dummy cyles for DDR read failed */ + status_spi_nor_flash_not_found = MAKE_STATUS(status_group_spi_nor_flash, 2), /**< FLASH was not detected */ + status_spi_nor_flash_para_err = MAKE_STATUS(status_group_spi_nor_flash, 3), + status_spi_nor_flash_is_busy = MAKE_STATUS(status_group_spi_nor_flash, 4), + status_spi_nor_flash_not_qe_bit_in_sfdp = MAKE_STATUS(status_group_spi_nor_flash, 5), +}; + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief determine whether the serial nor flash is busy + * @param [in] host the serial nor context + * @return hpm_stat_t: status_spi_nor_flash_is_busy if the serial nor flash is busy + */ +hpm_stat_t hpm_serial_nor_is_busy(hpm_serial_nor_t *flash); + +/** + * @brief set serial nor flash write enable + * @param [in] channel serial nor flash channel + * @return hpm_stat_t: status_success if write enable success + */ +hpm_stat_t hpm_serial_nor_write_enable(hpm_serial_nor_t *flash); + +/** + * @brief erase the serial nor flash chip + * @param [in] host the serial nor context + * @return hpm_stat_t: status_success if erase chip success + */ +hpm_stat_t hpm_serial_nor_erase_chip(hpm_serial_nor_t *flash); + +/** + * @brief erase the serial nor flash block using blocking transfer + * + * @note the erase block address must be block alignment + * + * @param [in] host the serial nor context + * @param [in] block_addr the serial nor flash block address + * @return hpm_stat_t: status_success if erase block success + */ +hpm_stat_t hpm_serial_nor_erase_block_blocking(hpm_serial_nor_t *flash, uint32_t block_addr); + +/** + * @brief erase the serial nor flash block using noblocking transfer + * + * @note the erase block address must be block alignment, it'not wait flash busy status. + * + * @param [in] host the serial nor context + * @param [in] block_addr the serial nor flash block address + * @return hpm_stat_t: status_success if erase block success + */ +hpm_stat_t hpm_serial_nor_erase_block_noblocking(hpm_serial_nor_t *flash, uint32_t block_addr); + +/** + * @brief erase the serial nor flash sector using blocking transfer + * + * @note the erase sector address must be sector alignment + * + * @param [in] host the serial nor context + * @param [in] sector_addr the serial nor flash sector address + * @return hpm_stat_t: status_success if erase sector success + */ +hpm_stat_t hpm_serial_nor_erase_sector_blocking(hpm_serial_nor_t *flash, uint32_t sector_addr); + +/** + * @brief erase the serial nor flash sector using noblocking transfer + * + * @note the erase sector address must be sector alignment, it'not wait flash busy status. + * + * @param [in] host the serial nor context + * @param [in] sector_addr the serial nor flash sector address + * @return hpm_stat_t: status_success if erase sector success + */ +hpm_stat_t hpm_serial_nor_erase_sector_noblocking(hpm_serial_nor_t *flash, uint32_t sector_addr); + +/** + * @brief erase the serial nor flash specified start address and length using blocking transfer + * + * @note the erase sector address must be sector alignment + * + * @param [in] host the serial nor context + * @param [in] sector_addr the serial nor flash sector address + * @return hpm_stat_t: status_success if erase success + */ +hpm_stat_t hpm_serial_nor_erase_blocking(hpm_serial_nor_t *flash, uint32_t start, uint32_t length); + +/** + * @brief program data to the specified serial nor flash address using blocking transfer + * @param [in] host the serial nor context + * @param [in] buf the data source pointer + * @param [in] data_len the data length + * @param [in] address the serial nor flash programming address + * @return hpm_stat_t: status_success if program success + */ +hpm_stat_t hpm_serial_nor_program_blocking(hpm_serial_nor_t *flash, uint8_t *buf, uint32_t data_len, + uint32_t address); + +/** + * @brief program data to the page nor flash address using noblocking transfer + * @param [in] host the serial nor context + * @param [in] buf the data source pointer + * @param [in] data_len the data length + * @param [in] address the serial nor flash programming address + * @return hpm_stat_t: status_success if program success + */ +hpm_stat_t hpm_serial_nor_page_program_noblocking(hpm_serial_nor_t *flash, uint8_t *buf, + uint32_t data_len, + uint32_t address); + +/** + * @brief read the data of specified serial nor flash address + * @param [in] host the serial nor context + * @param [in] buf the data source pointer + * @param [in] data_len the data length + * @param [in] address the serial nor flash reading address + * @return hpm_stat_t: status_success if read success + */ +hpm_stat_t hpm_serial_nor_read(hpm_serial_nor_t *flash, uint8_t *buf, uint16_t data_len, + uint32_t address); + +/** + * @brief the serial nor flash initialization + * @param [in] host the serial nor context + * @param [out] info serial_nor_flash_info_t + * @return hpm_stat_t: status_success if initialization success + */ +hpm_stat_t hpm_serial_nor_init(hpm_serial_nor_t *flash, hpm_serial_nor_info_t *info); + +/** + * @brief get the serial nor flash information + * @param [in] host the serial nor context + * @param [out] info serial_nor_flash_info_t + * @return hpm_stat_t: status_success if get information success + */ +hpm_stat_t hpm_serial_nor_get_info(hpm_serial_nor_t *flash, hpm_serial_nor_info_t *info); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/common/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor_host.h b/common/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor_host.h new file mode 100644 index 00000000..78c22460 --- /dev/null +++ b/common/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor_host.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_SERIAL_NOR_HOST_H +#define _HPM_SERIAL_NOR_HOST_H +#include "hpm_common.h" +#include "sfdp_def.h" + +#define SERIAL_NOR_HOST_SUPPORT_SINGLE_IO_MODE (1UL << 0) +#define SERIAL_NOR_HOST_SUPPORT_DUAL_IO_MODE (1UL << 1) +#define SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE (1UL << 2) +#define SERIAL_NOR_HOST_SUPPORT_SPI_INTERFACE (1UL << 3) +#define SERIAL_NOR_HOST_SUPPORT_DMA (1UL << 8) +#define SERIAL_NOR_HOST_CS_CONTROL_AUTO (1UL << 9) + +/** + * @brief IO mode of serial nor flash sequence + */ +typedef enum { + single_io_mode = 0, + dual_io_mode, + quad_io_mode +} hpm_serial_nor_seq_io_mode_t; + +/** + * @brief number of address bits of serial nor flash sequence + */ +typedef enum { + flash_addrlen_24bit = 0, + flash_addrlen_32bit +} hpm_serial_nor_seq_addr_bit_t; + +/** + * @brief transfer direction serial nor flash sequence + */ +typedef enum { + write_direction = 0, + read_direction +} hpm_serial_nor_seq_direction_t; + +/** + * @brief information of serial nor flash + */ +typedef struct { + uint8_t en_dev_mode_cfg; + uint8_t sfdp_version; + uint8_t sector_erase_cmd; + uint8_t block_erase_cmd; + uint32_t size_in_kbytes; + uint16_t page_size; + uint16_t sector_size_kbytes; + uint16_t block_size_kbytes; +} hpm_serial_nor_info_t; + +/** + * @brief dma control param of serial nor flash host + */ +typedef struct { + uint8_t rx_dma_ch; + uint8_t tx_dma_ch; + uint8_t rx_dma_req; + uint8_t tx_dma_req; + void *dma_base; + void *dmamux_base; +} hpm_nor_host_dma_control_t; + +/** + * @brief param and operation of serial nor flash host + */ +typedef struct { + uint8_t pin_or_cs_index; + hpm_nor_host_dma_control_t dma_control; + uint32_t clock_name; + uint32_t frequency; + uint32_t transfer_max_size; + void *host_base; + void (*set_cs)(uint32_t cs_pin, uint8_t state); + void (*set_frequency)(void *host, uint32_t freq); +} hpm_nor_host_param_t; + +/** + * @brief spi nor read parameters structure + */ +typedef struct { + uint8_t read_cmd; + uint8_t data_dummy_count; + hpm_serial_nor_seq_addr_bit_t addr_bit; + hpm_serial_nor_seq_io_mode_t data_phase_format; + hpm_serial_nor_seq_io_mode_t addr_phase_format; +} hpm_sfdp_read_para_t; + +/** + * @brief spi nor program parameters structure + */ +typedef struct { + bool has_4b_addressing_inst_table; + bool support_1_4_4_page_program; + bool support_1_1_4_page_program; + uint8_t page_program_cmd; +} hpm_sfdp_program_para_t; + +/** + * @brief param of serial nor flash host + */ +typedef struct { + uint32_t flags; + hpm_nor_host_param_t param; + void *user_data; +} hpm_serial_nor_host_param_t; + +/** + * @brief operation sequence of serial nor flash + * + * @note it's include command + address(optional) + dummy(optional) + data(optional) + * + */ +typedef struct { + /* can choose whether to use DMA in a transfer, even if the flags has DMA*/ + uint8_t use_dma; + + struct { + uint8_t cmd; + } cmd_phase; + + struct { + bool enable; + hpm_serial_nor_seq_addr_bit_t addr_bit; + hpm_serial_nor_seq_io_mode_t addr_io_mode; + uint32_t addr; + } addr_phase; + + struct { + uint8_t dummy_count; + } dummy_phase; + + struct { + /* the operation direction of the data phase, it's include write and read */ + hpm_serial_nor_seq_direction_t direction; + /* the SPI operation mode of the data phase, it's include SPI/DUAL SPI/QUAD SPI and so on */ + hpm_serial_nor_seq_io_mode_t data_io_mode; + uint32_t len; + uint8_t *buf; + } data_phase; + +} hpm_serial_nor_transfer_seq_t; + +/** + * @brief operation of serial nor flash host + */ +typedef struct { + hpm_stat_t (*init)(void *host); + + hpm_stat_t (*transfer)(void *host, hpm_serial_nor_transfer_seq_t *command_seq); + + void (*set_cs)(uint32_t cs_pin, uint8_t state); + + void (*set_frequency)(void *host, uint32_t freq); + + void *user_data; +} serial_nor_host_ops_t; + +/** + * @brief serial nor flash host parameters structure + */ +typedef struct { + hpm_serial_nor_host_param_t host_param; + serial_nor_host_ops_t host_ops; + void *user_data; +} hpm_serial_nor_host_t; + +/** + * @brief serial nor flash parameters structure + */ +typedef struct { + hpm_serial_nor_host_t host; + hpm_sfdp_read_para_t nor_read_para; + hpm_sfdp_program_para_t nor_program_para; + hpm_serial_nor_info_t flash_info; +} hpm_serial_nor_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief serial nor host operation is use spi operation + * @param [in] dev serial nor device + * @return hpm_stat_t: status_success if success + */ +hpm_stat_t serial_nor_host_ops_use_spi(hpm_serial_nor_t *dev); +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/common/libraries/hpm_sdk/components/serial_nor/interface/spi/CMakeLists.txt b/common/libraries/hpm_sdk/components/serial_nor/interface/spi/CMakeLists.txt new file mode 100644 index 00000000..17b77892 --- /dev/null +++ b/common/libraries/hpm_sdk/components/serial_nor/interface/spi/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +sdk_inc(.) +sdk_inc(../) +sdk_src(hpm_serial_nor_host_spi.c) diff --git a/common/libraries/hpm_sdk/components/serial_nor/interface/spi/hpm_serial_nor_host_spi.c b/common/libraries/hpm_sdk/components/serial_nor/interface/spi/hpm_serial_nor_host_spi.c new file mode 100644 index 00000000..0fb6dda0 --- /dev/null +++ b/common/libraries/hpm_sdk/components/serial_nor/interface/spi/hpm_serial_nor_host_spi.c @@ -0,0 +1,369 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifdef CONFIG_HAS_HPMSDK_DMAV2 +#include "hpm_dmav2_drv.h" +#else +#include "hpm_dma_drv.h" +#endif +#include "hpm_dmamux_drv.h" +#include "hpm_spi_drv.h" +#include "hpm_l1c_drv.h" +#include "board.h" +#include "hpm_serial_nor_host.h" + +static hpm_stat_t spi_nor_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, + uint32_t dst, uint8_t data_width, uint32_t size, uint8_t burst_size); + +static hpm_stat_t spi_nor_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, + uint8_t data_width, uint32_t size, uint8_t burst_size); + +static void hpm_config_cmd_addr_format(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq, spi_control_config_t *control_config); + +static hpm_stat_t hpm_spi_transfer_via_dma(hpm_serial_nor_host_t *host, spi_control_config_t *control_config, + uint8_t cmd, uint32_t addr, + uint8_t *buf, uint32_t len, bool is_read); + +static hpm_stat_t transfer(void *host, hpm_serial_nor_transfer_seq_t *command_seq); + +static hpm_stat_t init(void *ops); + +static hpm_stat_t write(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq); + +static hpm_stat_t read(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq); + +ATTR_WEAK hpm_stat_t serial_nor_host_ops_use_spi(hpm_serial_nor_t *dev) +{ + if (dev == NULL) { + return status_invalid_argument; + } + dev->host.host_ops.init = init; + dev->host.host_ops.transfer = transfer; + dev->host.host_ops.set_cs = dev->host.host_param.param.set_cs; + dev->host.host_ops.set_frequency = dev->host.host_param.param.set_frequency; + return status_success; +} + +static hpm_stat_t transfer(void *host, hpm_serial_nor_transfer_seq_t *command_seq) +{ + hpm_stat_t stat = status_success; + if (command_seq->data_phase.direction == read_direction) { + stat = read(host, command_seq); + } else { + stat = write(host, command_seq); + } + return stat; +} + +static hpm_stat_t spi_nor_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, + uint32_t src, uint8_t data_width, uint32_t size, uint8_t burst_size) +{ + hpm_stat_t stat; + dma_channel_config_t config; + if (ch_num >= DMA_SOC_CHANNEL_NUM) { + return status_invalid_argument; + } + dma_default_channel_config(dma_ptr, &config); + config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + config.src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; + config.src_width = data_width; + config.dst_width = data_width; + config.src_addr = src; + config.dst_addr = (uint32_t)&spi_ptr->DATA; + config.size_in_byte = size; + config.src_burst_size = burst_size; + stat = dma_setup_channel(dma_ptr, ch_num, &config, true); + if (stat != status_success) { + return stat; + } + return stat; +} + +static hpm_stat_t spi_nor_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, + uint8_t data_width, uint32_t size, uint8_t burst_size) +{ + hpm_stat_t stat; + dma_channel_config_t config; + if (ch_num >= DMA_SOC_CHANNEL_NUM) { + return status_invalid_argument; + } + dma_default_channel_config(dma_ptr, &config); + config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; + config.src_width = data_width; + config.dst_width = data_width; + config.src_addr = (uint32_t)&spi_ptr->DATA; + config.dst_addr = dst; + config.size_in_byte = size; + config.src_burst_size = burst_size; + stat = dma_setup_channel(dma_ptr, ch_num, &config, true); + if (stat != status_success) { + return stat; + } + return stat; +} + +static void hpm_config_cmd_addr_format(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq, spi_control_config_t *control_config) +{ + spi_trans_mode_t _trans_mode; + hpm_serial_nor_host_t *host = (hpm_serial_nor_host_t *)ops; + control_config->master_config.cmd_enable = true; + + /* judge the valid of addr */ + if (cmd_seq->addr_phase.enable == true) { + control_config->master_config.addr_enable = true; + if (cmd_seq->addr_phase.addr_io_mode == single_io_mode) { + control_config->master_config.addr_phase_fmt = spi_address_phase_format_single_io_mode; + } else { + control_config->master_config.addr_phase_fmt = spi_address_phase_format_dualquad_io_mode; + } + if (cmd_seq->addr_phase.addr_bit == flash_addrlen_24bit) { + spi_set_address_len((SPI_Type *)host->host_param.param.host_base, addrlen_24bit); + } else { + spi_set_address_len((SPI_Type *)host->host_param.param.host_base, addrlen_32bit); + } + } else { + control_config->master_config.addr_enable = false; + } + + /* judge the valid of buf */ + if ((cmd_seq->data_phase.buf != NULL) || (cmd_seq->data_phase.len != 0)) { + if (cmd_seq->dummy_phase.dummy_count == 0) { + _trans_mode = (cmd_seq->data_phase.direction == read_direction) ? spi_trans_read_only : spi_trans_write_only; + } else { + control_config->common_config.dummy_cnt = cmd_seq->dummy_phase.dummy_count - 1; + _trans_mode = (cmd_seq->data_phase.direction == read_direction) ? spi_trans_dummy_read : spi_trans_dummy_write; + } + control_config->common_config.trans_mode = _trans_mode; + + if ((cmd_seq->data_phase.data_io_mode == single_io_mode) + || (host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_SINGLE_IO_MODE)) { + control_config->common_config.data_phase_fmt = spi_single_io_mode; + } else if (cmd_seq->data_phase.data_io_mode == dual_io_mode) { + control_config->common_config.data_phase_fmt = spi_dual_io_mode; + } else { + control_config->common_config.data_phase_fmt = spi_quad_io_mode; + } + } else { + control_config->common_config.trans_mode = spi_trans_no_data; + } +} + +static hpm_stat_t init(void *ops) +{ + spi_format_config_t format_config = {0}; + hpm_serial_nor_host_t *host = (hpm_serial_nor_host_t *)ops; + if ((host == NULL) || (host->host_param.param.host_base == NULL)) { + return status_invalid_argument; + } + spi_master_get_default_format_config(&format_config); + format_config.common_config.data_len_in_bits = 8; + format_config.common_config.mode = spi_master_mode; + format_config.common_config.cpol = spi_sclk_low_idle; + format_config.common_config.cpha = spi_sclk_sampling_odd_clk_edges; + format_config.common_config.data_merge = false; + spi_format_init(host->host_param.param.host_base, &format_config); + if (host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_DMA) { + if ((host->host_param.param.dma_control.dma_base == NULL) || (host->host_param.param.dma_control.dmamux_base == NULL)) { + return status_invalid_argument; + } + dmamux_config(host->host_param.param.dma_control.dmamux_base, + DMA_SOC_CHN_TO_DMAMUX_CHN(host->host_param.param.dma_control.dma_base, + host->host_param.param.dma_control.rx_dma_ch), + host->host_param.param.dma_control.rx_dma_req, true); + + dmamux_config(host->host_param.param.dma_control.dmamux_base, + DMA_SOC_CHN_TO_DMAMUX_CHN(host->host_param.param.dma_control.dma_base, + host->host_param.param.dma_control.tx_dma_ch), + host->host_param.param.dma_control.tx_dma_req, true); + } + return status_success; +} + +static hpm_stat_t hpm_spi_transfer_via_dma(hpm_serial_nor_host_t *host, spi_control_config_t *control_config, + uint8_t cmd, uint32_t addr, + uint8_t *buf, uint32_t len, bool is_read) +{ + hpm_stat_t stat; + uint32_t data_width = 0; + uint8_t burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + uint32_t timeout_count = 0; + uint16_t dma_send_size; + if (is_read) { + /*The supplement of the byte less than the integer multiple of four bytes is an integer multiple of four bytes to DMA*/ + data_width = DMA_TRANSFER_WIDTH_WORD; + if ((len % 4) == 0) { + dma_send_size = len; + } else { + dma_send_size = ((len >> 2) + 1) << 2; + } + stat = spi_setup_dma_transfer((SPI_Type *)host->host_param.param.host_base, control_config, &cmd, &addr, 0, len); + stat = spi_nor_rx_trigger_dma((DMA_Type *)host->host_param.param.dma_control.dma_base, + host->host_param.param.dma_control.rx_dma_ch, + (SPI_Type *)host->host_param.param.host_base, + core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)buf), + data_width, + dma_send_size, burst_size); + while (spi_is_active((SPI_Type *)host->host_param.param.host_base)) { + timeout_count++; + if (timeout_count >= 0xFFFFFF) { + stat = status_timeout; + break; + } + } + timeout_count = 0; + if ((dma_check_transfer_status( + (DMA_Type *)host->host_param.param.dma_control.dma_base, + host->host_param.param.dma_control.rx_dma_ch) && + DMA_CHANNEL_STATUS_TC) == 0) { + dma_disable_channel((DMA_Type *)host->host_param.param.dma_control.dma_base, host->host_param.param.dma_control.rx_dma_ch); + dma_reset((DMA_Type *)host->host_param.param.dma_control.dma_base); + } + } else { + if ((len % 4) == 0) { + spi_enable_data_merge((SPI_Type *)host->host_param.param.host_base); + data_width = DMA_TRANSFER_WIDTH_WORD; + } else { + data_width = DMA_TRANSFER_WIDTH_BYTE; + } + spi_set_tx_fifo_threshold((SPI_Type *)host->host_param.param.host_base, 3); + burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + stat = spi_setup_dma_transfer((SPI_Type *)host->host_param.param.host_base, control_config, &cmd, &addr, len, 0); + + stat = spi_nor_tx_trigger_dma((DMA_Type *)host->host_param.param.dma_control.dma_base, + host->host_param.param.dma_control.tx_dma_ch, + (SPI_Type *)host->host_param.param.host_base, + core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)buf), + data_width, len, burst_size); + + while (spi_is_active((SPI_Type *)host->host_param.param.host_base)) { + timeout_count++; + if (timeout_count >= 0xFFFFFF) { + stat = status_timeout; + break; + } + } + timeout_count = 0; + spi_disable_data_merge((SPI_Type *)host->host_param.param.host_base); + } + return stat; +} +static hpm_stat_t write(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq) +{ + hpm_stat_t stat = status_success; + spi_control_config_t control_config = {0}; + hpm_serial_nor_host_t *host = (hpm_serial_nor_host_t *)ops; + uint32_t aligned_start; + uint32_t aligned_end; + uint32_t aligned_size; + if ((cmd_seq->data_phase.len > host->host_param.param.transfer_max_size) || (host == NULL) + || (host->host_param.param.host_base == NULL)) { + return status_invalid_argument; + } + + if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { + if (host->host_param.param.set_cs == NULL) { + return status_fail; + } + host->host_param.param.set_cs(host->host_param.param.pin_or_cs_index, false); + } + + spi_master_get_default_control_config(&control_config); + hpm_config_cmd_addr_format(ops, cmd_seq, &control_config); + + if ((host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_DMA) && (cmd_seq->use_dma == 1)) { + control_config.common_config.tx_dma_enable = true; + control_config.common_config.rx_dma_enable = false; + if (l1c_dc_is_enabled()) { + /* cache writeback for sent buff */ + aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)cmd_seq->data_phase.buf); + aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)cmd_seq->data_phase.buf + cmd_seq->data_phase.len); + aligned_size = aligned_end - aligned_start; + l1c_dc_writeback(aligned_start, aligned_size); + } + stat = hpm_spi_transfer_via_dma(host, &control_config, cmd_seq->cmd_phase.cmd, cmd_seq->addr_phase.addr, + (uint8_t *)cmd_seq->data_phase.buf, cmd_seq->data_phase.len, false); + } else { + stat = spi_transfer((SPI_Type *)host->host_param.param.host_base, &control_config, + &cmd_seq->cmd_phase.cmd, &cmd_seq->addr_phase.addr, + cmd_seq->data_phase.buf, cmd_seq->data_phase.len, NULL, 0); + } + if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { + host->host_param.param.set_cs(host->host_param.param.pin_or_cs_index, true); + } + return stat; +} + +static hpm_stat_t read(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq) +{ + hpm_stat_t stat = status_success; + uint32_t aligned_start; + uint32_t aligned_end; + uint32_t aligned_size; + spi_control_config_t control_config = {0}; + hpm_serial_nor_host_t *host = (hpm_serial_nor_host_t *)ops; + uint32_t read_size = 0; + uint32_t read_start = cmd_seq->addr_phase.addr; + uint8_t *dst_8 = (uint8_t *) cmd_seq->data_phase.buf; + uint32_t remaining_len = cmd_seq->data_phase.len; + + if ((host == NULL) || (host->host_param.param.host_base == NULL)) { + return status_invalid_argument; + } + if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { + if (host->host_param.param.set_cs == NULL) { + return status_fail; + } + } + + spi_master_get_default_control_config(&control_config); + hpm_config_cmd_addr_format(ops, cmd_seq, &control_config); + + if ((host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_DMA) && (cmd_seq->use_dma == 1)) { + if (host->host_param.param.dma_control.dma_base == NULL) { + return status_fail; + } + if (((uint32_t)dst_8 % HPM_L1C_CACHELINE_SIZE) != 0) { + return status_invalid_argument; + } + control_config.common_config.tx_dma_enable = false; + control_config.common_config.rx_dma_enable = true; + } + while (remaining_len > 0U) { + if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { + host->host_param.param.set_cs(host->host_param.param.pin_or_cs_index, false); + } + read_size = MIN(remaining_len, host->host_param.param.transfer_max_size); + if ((host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_DMA) && (cmd_seq->use_dma == 1)) { + spi_enable_data_merge((SPI_Type *)host->host_param.param.host_base); + stat = hpm_spi_transfer_via_dma(host, &control_config, cmd_seq->cmd_phase.cmd, read_start, dst_8, read_size, true); + } else { + stat = spi_transfer((SPI_Type *)host->host_param.param.host_base, &control_config, &cmd_seq->cmd_phase.cmd, + &read_start, NULL, 0, dst_8, read_size); + } + HPM_BREAK_IF(stat != status_success); + if (l1c_dc_is_enabled()) { + /* cache invalidate for receive buff */ + aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)dst_8); + aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(read_size); + aligned_size = aligned_end - aligned_start; + l1c_dc_invalidate(aligned_start, aligned_size); + } + read_start += read_size; + remaining_len -= read_size; + dst_8 += read_size; + if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { + host->host_param.param.set_cs(host->host_param.param.pin_or_cs_index, true); + } + } + spi_disable_data_merge((SPI_Type *)host->host_param.param.host_base); + return stat; +} diff --git a/common/libraries/hpm_sdk/components/serial_nor/sfdp_def.h b/common/libraries/hpm_sdk/components/serial_nor/sfdp_def.h index 3b4b7032..07009a5e 100644 --- a/common/libraries/hpm_sdk/components/serial_nor/sfdp_def.h +++ b/common/libraries/hpm_sdk/components/serial_nor/sfdp_def.h @@ -9,22 +9,22 @@ #include "hpm_common.h" /* ! @brief Commands for probing the FLASH device */ -#define kSerialFlash_ReadSFDP (0x5AU) -#define kSerialFlash_ReadManufacturerId (0x9FU) +#define SERIAL_FLASH_READ_SFDP (0x5AU) +#define SERIAL_FLASH_READ_MANUFACTURE_ID (0x9FU) /* !@brief SFDP related definitions */ #define SFDP_SIGNATURE (0x50444653UL) /* ASCII: SFDP */ -#define kSfdp_Version_Major_1_0 (1U) -#define kSfdp_Version_Minor_0 (0U) /* JESD216 */ -#define kSfdp_Version_Minor_A (5U) /* JESD216A */ -#define kSfdp_Version_Minor_B (6U) /* JESD216B */ -#define kSfdp_Version_Minor_C (7U) /* JESD216C */ -#define kSfdp_Version_Minor_D (8U) /* JESD216D */ -#define kSfdp_BasicProtocolTableSize_Rev0 (36U) -#define kSfdp_BasicProtocolTableSize_RevA (64U) -#define kSfdp_BasicProtocolTableSize_RevB kSfdp_BasicProtocolTableSize_RevA -#define kSfdp_BasicProtocolTableSize_RevC (80U) -#define kSfdp_BasicProtocolTableSize_RevD kSfdp_BasicProtocolTableSize_RevC +#define SFDP_VERSION_MAJOR_1_0 (1U) +#define SFDP_VERSION_MINOR_0 (0U) /* JESD216 */ +#define SFDP_VERSION_MINOR_A (5U) /* JESD216A */ +#define SFDP_VERSION_MINOR_B (6U) /* JESD216B */ +#define SFDP_VERSION_MINOR_C (7U) /* JESD216C */ +#define SFDP_VERSION_MINOR_D (8U) /* JESD216D */ +#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REV0 (36U) +#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVA (64U) +#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVB SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVA +#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVC (80U) +#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVD SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVC typedef union _sfdp_header { uint32_t words[2]; @@ -39,28 +39,28 @@ typedef union _sfdp_header { } sfdp_header_t; /* !@brief SFDP parameter Type ID definitions */ -#define kParameterID_BasicSpiProtocol (0xFF00U) +#define PARAMETER_ID_BASIC_SPIPROTOCOL (0xFF00U) /* New Table added in JESD216B */ -#define kParameterID_SectorMap (0xFF81U) -#define kParameterID_4ByteAddressInstructionTable (0xFF84U) +#define PARAMETER_ID_SECTOR_MAP (0xFF81U) +#define PARAMETER_ID_4BYTEADDRESS_INSTRUCTION_TABLE (0xFF84U) /* New Table added in JESD216C */ -#define kParameterID_xSpiProfile1_0 (0xFF05U) -#define kParameterID_xSpiOrofile2_0 (0xFF06U) -#define kParameterID_StaCtrlCfgRegMap (0xFF87U) -#define kParameterID_OpiEnableSeq (0xFF09U) -#define kParameterID_CmdSeqChangeToOctalDdr (0xFF0AU) +#define PARAMETER_ID_XSPIPROFILE1_0 (0xFF05U) +#define PARAMETER_ID_XSPIOROFILE2_0 (0xFF06U) +#define PARAMETER_ID_STACTRLCFGREGMAP (0xFF87U) +#define PARAMETER_ID_OPIENABLESEQ (0xFF09U) +#define PARAMETER_ID_CMDSEQ_CHANGE_TO_OCTAL_DDR (0xFF0AU) -#define kNorFlash_AddressBits_3B (0U) -#define kNorFlash_AddressBits_3B_4B (1U) -#define kNorFlash_AddressBits_4B (2U) +#define NORFLASH_ADDRESSBITS_3B (0U) +#define NORFLASH_ADDRESSBITS_3B_4B (1U) +#define NORFLASH_ADDRESSBITS_4B (2U) -#define kCommandExtensionSameAsCommand (0U) -#define kCommandExtensionInverseOfCommand (1U) -#define kCommandAndCommandExtension16BitWord (2U) +#define COMMAND_EXTENSION_SAME_AS_COMMAND (0U) +#define COMMAND_EXTENSION_INVERSE_OF_COMMAND (1U) +#define COMMAND_AND_COMMANDEXTENSION_16BITWORD (2U) /* !@brief Supported methods to enter 8-8-8 mode from 1-1-1 mode, More details please refer to JESD216C/D */ -#define kEnterOctalMode_Option0 HPM_BITSMASK(1U, 1) -#define kEnterOctalMode_Option1 HPM_BITSMASK(1U, 2) +#define ENTER_OCTAL_MODE_OPTION0 HPM_BITSMASK(1U, 1) +#define ENTER_OCTAL_MODE_OPTION1 HPM_BITSMASK(1U, 2) /* !@brief SFDP Parameter Header, see JESD216D doc for more details */ typedef union _sfdp_parameter_header { @@ -104,12 +104,12 @@ typedef union _jedec_flash_param_table { uint32_t inst_1_1_4_read : 8; } read_1_4_info; /* 3rd word */ struct { - uint32_t dummy_clocks_1_2_2_read : 5; - uint32_t mode_clocks_1_2_2_read : 3; - uint32_t inst_1_2_2_read : 8; uint32_t dummy_clocks_1_1_2_read : 5; uint32_t mode_clocks_1_1_2_read : 3; uint32_t inst_1_1_2_read : 8; + uint32_t dummy_clocks_1_2_2_read : 5; + uint32_t mode_clocks_1_2_2_read : 3; + uint32_t inst_1_2_2_read : 8; } read_1_2_info; /* 4th word */ struct { @@ -373,30 +373,30 @@ typedef struct _jdec_query_table { /* !@brief Typical Serial NOR commands supported by most Serial NOR devices */ -#define kSerialNorCmd_BasicRead_3B (0x03U) -#define kSerialNorCmd_BasicRead_4B (0x13U) -#define kSerialNorCmd_PageProgram_1_1_1_3B (0x02U) -#define kSerialNorCmd_PageProgram_1_1_1_4B (0x12U) -#define kSerialNorCmd_PageProgram_1_4_4_4B (0x3EU) -#define kSerialNorCmd_PageProgram_1_1_4_4B (0x34U) -#define kSerialNorCmd_Read_SDR_1_4_4_3B (0xEBU) -#define kSerialNorCmd_Read_DDR_1_4_4_3B (0xEDU) -#define kSerialNorCmd_Read_SDR_1_4_4_4B (0xECU) -#define kSerialNorCmd_Read_SDR_1_1_4_4B (0x6CU) -#define kSerialNorCmd_Read_DDR_1_4_4_4B (0xEEU) -#define kSerialNorCmd_ChipErase (0x60U) -#define kSerialNorCmd_WriteEnable (0x06U) -#define kSerialNorCmd_WriteStatusReg1 (0x01U) -#define kSerialNorCmd_ReadStatusReg1 (0x05U) -#define kSerialNorCmd_WriteStatusReg2 (0x3EU) -#define kSerialNorCmd_ReadStatusReg2 (0x3FU) -#define kSerialNorCmd_ReadFlagReg (0x70U) -#define kSerialNorCmd_ReadId (0x9FU) -#define kSerialNorCmd_Read_DDR_4B (0x0CU) -#define kSerialNorCmd_Read_DDR_3B (0x0BU) -#define kSerialNorCmd_SE4K_3B (0x20U) -#define kSerialNorCmd_SE4K_4B (0x21U) -#define kSerialNorCmd_SE64K_3B (0xD8U) -#define kSerialNorCmd_SE64K_4B (0xDCU) +#define SERIALNOR_CMD_BASICREAD_3B (0x03U) +#define SERIALNOR_CMD_BASICREAD_4B (0x13U) +#define SERIALNOR_CMD_PAGEPROGRAM_1_1_1_3B (0x02U) +#define SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B (0x12U) +#define SERIALNOR_CMD_PAGEPROGRAM_1_4_4_4B (0x3EU) +#define SERIALNOR_CMD_PAGEPROGRAM_1_1_4_4B (0x34U) +#define SERIALNOR_CMD_READ_SDR_1_4_4_3B (0xEBU) +#define SERIALNOR_CMD_READ_DDR_1_4_4_3B (0xEDU) +#define SERIALNOR_CMD_READ_SDR_1_4_4_4B (0xECU) +#define SERIALNOR_CMD_READ_SDR_1_1_4_4B (0x6CU) +#define SERIALNOR_CMD_READ_DDR_1_4_4_4B (0xEEU) +#define SERIALNOR_CMD_CHIPERASE (0x60U) +#define SERIALNOR_CMD_WRITEENABLE (0x06U) +#define SERIALNOR_CMD_WRITE_STATUS_REG1 (0x01U) +#define SERIALNOR_CMD_READ_STATUS_REG1 (0x05U) +#define SERIALNOR_CMD_WRITE_STATUS_REG2 (0x3EU) +#define SERIALNOR_CMD_READ_STATUS_REG2 (0x3FU) +#define SERIALNOR_CMD_READ_FLAGREG (0x70U) +#define SERIALNOR_CMD_READID (0x9FU) +#define SERIALNOR_CMD_READ_DDR_4B (0x0CU) +#define SERIALNOR_CMD_READ_DDR_3B (0x0BU) +#define SERIALNOR_CMD_SE4K_3B (0x20U) +#define SERIALNOR_CMD_SE4K_4B (0x21U) +#define SERIALNOR_CMD_SE64K_3B (0xD8U) +#define SERIALNOR_CMD_SE64K_4B (0xDCU) #endif diff --git a/common/libraries/hpm_sdk/components/smbus/hpm_smbus.c b/common/libraries/hpm_sdk/components/smbus/hpm_smbus.c index 24b10d26..8f4ef650 100644 --- a/common/libraries/hpm_sdk/components/smbus/hpm_smbus.c +++ b/common/libraries/hpm_sdk/components/smbus/hpm_smbus.c @@ -57,7 +57,6 @@ hpm_stat_t hpm_smbus_master_write_byte_in_command(I2C_Type *ptr, uint8_t slave_a hpm_stat_t hpm_smbus_master_write_word_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint16_t data) { hpm_stat_t stat; - uint8_t pec; uint8_t buf[5]; /* addr + rw bit*/ buf[0] = slave_address << 1; @@ -129,7 +128,6 @@ hpm_stat_t hpm_smbus_master_read_word_in_command(I2C_Type *ptr, uint8_t slave_ad hpm_stat_t hpm_smbus_master_write_block_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint8_t *data, uint32_t size) { hpm_stat_t stat; - uint8_t pec; uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; uint16_t buf_size; /* frame included addr, command, data, and pec */ @@ -150,7 +148,6 @@ hpm_stat_t hpm_smbus_master_read_block_in_command(I2C_Type *ptr, uint8_t slave_a hpm_stat_t stat; uint8_t pec; uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; - uint16_t buf_size; /* frame included addr, command, data, and pec */ assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 3)); /* addr + rw bit*/ @@ -182,7 +179,6 @@ hpm_stat_t hpm_smbus_master_read_block_in_command(I2C_Type *ptr, uint8_t slave_a hpm_stat_t hpm_smbus_master_write(I2C_Type *ptr, uint8_t slave_address, uint8_t *data, uint32_t size) { hpm_stat_t stat; - uint8_t pec; uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; uint16_t buf_size; /* frame included addr, data, and pec */ @@ -201,7 +197,6 @@ hpm_stat_t hpm_smbus_master_read(I2C_Type *ptr, uint8_t slave_address, uint8_t * hpm_stat_t stat; uint8_t pec; uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; - uint16_t buf_size; /* frame included addr, data, and pec */ assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 2)); buf[0] = (slave_address << 1); @@ -220,7 +215,6 @@ hpm_stat_t hpm_smbus_master_read(I2C_Type *ptr, uint8_t slave_address, uint8_t * hpm_stat_t hpm_smbus_slave_write(I2C_Type *ptr, uint8_t *data, uint32_t size) { hpm_stat_t stat; - uint8_t pec; uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; uint16_t buf_size; uint8_t slave_address; @@ -241,7 +235,6 @@ hpm_stat_t hpm_smbus_slave_read(I2C_Type *ptr, uint8_t *data, uint32_t size) hpm_stat_t stat; uint8_t pec; uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; - uint16_t buf_size; uint8_t slave_address; /* frame included addr, data, and pec */ assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 2)); diff --git a/common/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h b/common/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h index dde7ce9a..f0ca6d47 100644 --- a/common/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h +++ b/common/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h @@ -54,9 +54,9 @@ #define GT911_TOUCH_YH (0x8149U) #define GT911_VENDOR_ID (0x814AU) #define GT911_STATUS (0x814EU) -#define GT911_GET_STATUS_NUM_OF_POINTS(x) ((x) & 0xFU) -#define GT911_GET_STATUS_LARGE_DETECT(x) (((x) & 0x40U) >> 6) -#define GT911_GET_STATUS_BUFFER_STAT(x) (((x) & 0x80U) >> 7) +#define GT911_GET_STATUS_NUM_OF_POINTS(x) ((x) & 0xFU) +#define GT911_GET_STATUS_LARGE_DETECT(x) (((x) & 0x40U) >> 6) +#define GT911_GET_STATUS_BUFFER_STAT(x) (((x) & 0x80U) >> 7) #define GT911_FIRST_POINT (0x814FU) #define GT911_MAX_TOUCH_POINTS (5U) diff --git a/common/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c b/common/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c index 95b2ef01..0e89b26a 100644 --- a/common/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c +++ b/common/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c @@ -9,6 +9,7 @@ #include "hpm_touch.h" #include "hpm_gpio_drv.h" #include "hpm_gt911.h" +#include "hpm_touch.h" gt911_context_t gt911 = {0}; @@ -23,16 +24,21 @@ hpm_stat_t touch_get_data(touch_point_t *points, uint8_t *num_of_points) printf("gt911 read data failed\n"); return stat; } - - num = GT911_GET_STATUS_NUM_OF_POINTS(touch_data.status); - *num_of_points = num; - if (num > 0 && num < GT911_MAX_TOUCH_POINTS) { - for (i = 0; i < num; i++) { - points[i].x = (touch_data.points[i].x_h & 0xF) << 8 | touch_data.points[i].x_l; - points[i].y = (touch_data.points[i].y_h & 0xF) << 8 | touch_data.points[i].y_l; + /* the buffer status is ready*/ + if (GT911_GET_STATUS_BUFFER_STAT(touch_data.status) == 1) { + num = GT911_GET_STATUS_NUM_OF_POINTS(touch_data.status); + *num_of_points = num; + if (num > 0 && num <= GT911_MAX_TOUCH_POINTS) { + for (i = 0; i < num; i++) { + points[i].x = (touch_data.points[i].x_h & 0xF) << 8 | touch_data.points[i].x_l; + points[i].y = (touch_data.points[i].y_h & 0xF) << 8 | touch_data.points[i].y_l; + } + } else { + stat = status_touch_points_over_number; } + } else { + stat = status_touch_buffer_no_ready; } - gt911_write_register(>911, GT911_STATUS, 0); return stat; } diff --git a/common/libraries/hpm_sdk/components/touch/hpm_touch.h b/common/libraries/hpm_sdk/components/touch/hpm_touch.h index 201ab587..8c051a1c 100644 --- a/common/libraries/hpm_sdk/components/touch/hpm_touch.h +++ b/common/libraries/hpm_sdk/components/touch/hpm_touch.h @@ -20,6 +20,11 @@ #error "unknown touch type, either have CONFIG_FT5406 or CONFIG_GT911 defined" #endif +enum { + status_touch_buffer_no_ready = MAKE_STATUS(status_group_touch, 0), + status_touch_points_over_number = MAKE_STATUS(status_group_touch, 1), +}; + typedef struct { uint16_t x; uint16_t y; diff --git a/common/libraries/hpm_sdk/drivers/CMakeLists.txt b/common/libraries/hpm_sdk/drivers/CMakeLists.txt index faa01463..0b2c4313 100644 --- a/common/libraries/hpm_sdk/drivers/CMakeLists.txt +++ b/common/libraries/hpm_sdk/drivers/CMakeLists.txt @@ -45,8 +45,18 @@ sdk_src_ifdef(CONFIG_HAS_HPMSDK_SDM src/hpm_sdm_drv.c) sdk_src_ifdef(CONFIG_HAS_HPMSDK_LIN src/hpm_lin_drv.c) sdk_src_ifdef(CONFIG_HAS_HPMSDK_LINV2 src/hpm_linv2_drv.c) sdk_src_ifdef(CONFIG_HAS_HPMSDK_MCAN src/hpm_mcan_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_QEIV2 src/hpm_qeiv2_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_QEIV2 src/hpm_enc_pos_drv.c) sdk_src_ifdef(CONFIG_HAS_HPMSDK_SEI src/hpm_sei_drv.c) sdk_src_ifdef(CONFIG_HAS_HPMSDK_QEO src/hpm_qeo_drv.c) sdk_src_ifdef(CONFIG_HAS_HPMSDK_RDC src/hpm_rdc_drv.c) sdk_src_ifdef(CONFIG_HAS_HPMSDK_MMC src/hpm_mmc_drv.c) sdk_src_ifdef(CONFIG_HAS_HPMSDK_DMAV2 src/hpm_dmav2_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_EWDG src/hpm_ewdg_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_GWC src/hpm_gwc_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_LVB src/hpm_lvb_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_PLB src/hpm_plb_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_SMIX src/hpm_smix_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_MIPI_DSI src/hpm_mipi_dsi_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_MIPI_DSI_PHY src/hpm_mipi_dsi_phy_drv.c) +sdk_src_ifdef(CONFIG_HAS_HPMSDK_OPAMP src/hpm_opamp_drv.c) diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h index f2013f98..cc989546 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -63,6 +63,26 @@ typedef enum { adc12_conv_mode_preemption } adc12_conversion_mode_t; +/** @brief Define ADC12 Clock Divider */ +typedef enum { + adc12_clock_divider_1 = 1, + adc12_clock_divider_2, + adc12_clock_divider_3, + adc12_clock_divider_4, + adc12_clock_divider_5, + adc12_clock_divider_6, + adc12_clock_divider_7, + adc12_clock_divider_8, + adc12_clock_divider_9, + adc12_clock_divider_10, + adc12_clock_divider_11, + adc12_clock_divider_12, + adc12_clock_divider_13, + adc12_clock_divider_14, + adc12_clock_divider_15, + adc12_clock_divider_16, +} adc12_clock_divider_t; + /** @brief Define ADC12 irq events. */ typedef enum { /** This mask indicates that a trigger conversion is complete. */ @@ -96,26 +116,6 @@ typedef enum { adc12_event_dma_fifo_full = ADC12_INT_STS_DMA_FIFO_FULL_MASK } adc12_irq_event_t; -/** @brief Define ADC12 Clock Divider */ -typedef enum { - adc12_clock_divider_1 = 1, - adc12_clock_divider_2, - adc12_clock_divider_3, - adc12_clock_divider_4, - adc12_clock_divider_5, - adc12_clock_divider_6, - adc12_clock_divider_7, - adc12_clock_divider_8, - adc12_clock_divider_9, - adc12_clock_divider_10, - adc12_clock_divider_11, - adc12_clock_divider_12, - adc12_clock_divider_13, - adc12_clock_divider_14, - adc12_clock_divider_15, - adc12_clock_divider_16, -} adc12_clock_divider_t; - /** @brief ADC12 common configuration struct. */ typedef struct { uint8_t res; @@ -132,10 +132,18 @@ typedef struct { uint8_t diff_sel; uint16_t thshdh; uint16_t thshdl; + bool wdog_int_en; uint8_t sample_cycle_shift; uint32_t sample_cycle; } adc12_channel_config_t; +/** @brief ADC12 channel configuration struct. */ +typedef struct { + uint8_t ch; + uint16_t thshdh; + uint16_t thshdl; +} adc12_channel_threshold_t; + /** @brief ADC12 DMA configuration struct. */ typedef struct { uint32_t *start_addr; @@ -220,6 +228,16 @@ void adc12_get_default_config(adc12_config_t *config); */ void adc12_get_channel_default_config(adc12_channel_config_t *config); +/** + * @brief De-initialize an ADC12 instance. + * + * @param[in] ptr An ADC12 peripheral base address. + * @return A result of de-initializing an ADC12 instance. + * @retval status_success De-initialize an ADC12 instance successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument De-initialize an ADC12 instance unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. + */ +hpm_stat_t adc12_deinit(ADC12_Type *ptr); + /** * @brief Initialize an ADC12 instance. * @@ -242,6 +260,18 @@ hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config); */ hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config); +/** + * @brief Get thresholds of an ADC12 channel + * + * @param[in] ptr An ADC12 peripheral base address. + * @param[in] ch An ADC12 channel number + * @param[out] config A pointer to the structure of channel threshold + * @return A result of getting thresholds of an ADC12 channel . + * @retval status_success Initialize an ADC12 channel successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Initialize an ADC12 channel unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. + */ +hpm_stat_t adc12_get_channel_threshold(ADC12_Type *ptr, uint8_t ch, adc12_channel_threshold_t *config); + /** * @brief Configure the the period mode for an ADC12 instance. * @@ -283,7 +313,7 @@ hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config); */ /** - * @brief Configure the stop position offset in the specified memory of DMA write operation for the the sequence mode. + * @brief Configure the stop position offset in the specified memory of DMA write operation for the sequence mode. * * @param[in] ptr An ADC12 peripheral base address. * @param[in] stop_pos A stop position offset. @@ -337,9 +367,10 @@ static inline uint32_t adc12_get_status_flags(ADC12_Type *ptr) /** * @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus - * until the ADC has completed its conversion. + * until the ADC has completed its conversion. * * * @param[in] ptr An ADC12 peripheral base address. + * @deprecated This API will be removed from V2.0.x */ static inline void adc12_disable_busywait(ADC12_Type *ptr) { @@ -351,18 +382,55 @@ static inline void adc12_disable_busywait(ADC12_Type *ptr) * until the ADC completes the conversion. * * @param[in] ptr An ADC12 peripheral base address. + * @deprecated This API will be removed from V2.0.x */ static inline void adc12_enable_busywait(ADC12_Type *ptr) { ptr->BUF_CFG0 &= ~ADC12_BUF_CFG0_WAIT_DIS_MASK; } +/** + * @brief Set nonblocking read in oneshot mode. + * @note An ADC does not block access to the associated peripheral whether it completes a conversion or not. + * + * @param[in] ptr An ADC12 peripheral base address. + */ +static inline void adc12_set_nonblocking_read(ADC12_Type *ptr) +{ + ptr->BUF_CFG0 |= ADC12_BUF_CFG0_WAIT_DIS_MASK; +} + +/** + * @brief Set blocking read in oneshot mode. + * @note An ADC blocks access to the associated peripheral bus until it completes a conversion. + * + * @param[in] ptr An ADC12 peripheral base address. + */ +static inline void adc12_set_blocking_read(ADC12_Type *ptr) +{ + ptr->BUF_CFG0 &= ~ADC12_BUF_CFG0_WAIT_DIS_MASK; +} + +/** + * @brief Judge whether the current setting is none-blocking mode or not. + * + * @param[in] ptr An ADC12 peripheral base address. + * @return A result indicating the status of bus waiting. + * @retval True means that nonblocking reading. + * @retval False means that blocking reading. + * + */ +static inline bool adc12_is_nonblocking_mode(ADC12_Type *ptr) +{ + return (ADC12_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0) ? true : false); +} + /** * @brief Get the status of a conversion validity. * * @param[in] ptr An ADC12 peripheral base address. * @param[in] ch An ADC12 peripheral channel. - * @retval Status indicating the validity of the current conversion result. + * @return Status indicating the validity of the current conversion result. * * @note This function is only used when the WAIT_DIS bit in the BUF_RESULT register is 1. */ @@ -382,7 +450,7 @@ static inline bool adc12_get_conv_valid_status(ADC12_Type *ptr, uint8_t ch) */ static inline void adc12_clear_status_flags(ADC12_Type *ptr, uint32_t mask) { - ptr->INT_STS |= mask; + ptr->INT_STS = mask; } /** @} */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h index 5920c3b8..cc7444a4 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -57,7 +57,7 @@ typedef enum { adc16_conv_mode_preemption } adc16_conversion_mode_t; -/** @brief Define adc16 Clock Divider */ +/** @brief Define ADC16 Clock Divider */ typedef enum { adc16_clock_divider_1 = 1, adc16_clock_divider_2, @@ -116,7 +116,7 @@ typedef struct { uint8_t conv_mode; uint32_t adc_clk_div; uint16_t conv_duration; - bool port3_rela_time; + bool port3_realtime; bool wait_dis; bool sel_sync_ahb; bool adc_ahb_en; @@ -127,10 +127,18 @@ typedef struct { uint8_t ch; uint16_t thshdh; uint16_t thshdl; + bool wdog_int_en; uint8_t sample_cycle_shift; uint32_t sample_cycle; } adc16_channel_config_t; +/** @brief ADC16 channel configuration struct. */ +typedef struct { + uint8_t ch; + uint16_t thshdh; + uint16_t thshdl; +} adc16_channel_threshold_t; + /** @brief ADC16 DMA configuration struct. */ typedef struct { uint32_t *start_addr; @@ -140,6 +148,7 @@ typedef struct { } adc16_dma_config_t; /** @brief ADC16 DMA configuration struct for the sequence mode. */ +#if defined(ADC_SOC_IP_VERSION) && (ADC_SOC_IP_VERSION < 2) typedef struct { uint32_t result :16; uint32_t seq_num :4; @@ -148,8 +157,18 @@ typedef struct { uint32_t :2; uint32_t cycle_bit :1; } adc16_seq_dma_data_t; +#else +typedef struct { + uint32_t result :16; + uint32_t seq_num :4; + uint32_t adc_ch :5; + uint32_t :6; + uint32_t cycle_bit :1; +} adc16_seq_dma_data_t; +#endif /** @brief ADC16 DMA configuration struct for the preemption mode. */ +#if defined(ADC_SOC_IP_VERSION) && (ADC_SOC_IP_VERSION < 2) typedef struct { uint32_t result :16; uint32_t seq_num :2; @@ -159,8 +178,18 @@ typedef struct { uint32_t :2; uint32_t cycle_bit :1; } adc16_pmt_dma_data_t; +#else +typedef struct { + uint32_t result :16; + uint32_t :4; + uint32_t adc_ch :5; + uint32_t trig_ch :4; + uint32_t seq_num :2; + uint32_t cycle_bit :1; +} adc16_pmt_dma_data_t; +#endif -/** @brief ADC16 configuration struct for the the period mode. */ +/** @brief ADC16 configuration struct for the period mode. */ typedef struct { uint8_t ch; uint8_t prescale; @@ -214,6 +243,16 @@ void adc16_get_default_config(adc16_config_t *config); */ void adc16_get_channel_default_config(adc16_channel_config_t *config); +/** + * @brief De-initialize an ADC16 instance. + * + * @param[in] ptr An ADC16 peripheral base address. + * @return A result of de-initializing an ADC16 instance. + * @retval status_success De-initialize an ADC16 instance successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument De-initialize an ADC16 instance unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. + */ +hpm_stat_t adc16_deinit(ADC16_Type *ptr); + /** * @brief Initialize an ADC16 instance. * @@ -236,6 +275,34 @@ hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config); */ hpm_stat_t adc16_init_channel(ADC16_Type *ptr, adc16_channel_config_t *config); +/** + * @brief Get thresholds of an ADC16 channel + * + * @param[in] ptr An ADC16 peripheral base address. + * @param[in] ch An ADC16 channel number + * @param[out] config A pointer to the structure of channel threshold + * @return A result of getting thresholds of an ADC16 channel . + * @retval status_success Initialize an ADC16 channel successfully. Please refer to @ref hpm_stat_t. + * @retval status_invalid_argument Initialize an ADC16 channel unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. + */ +hpm_stat_t adc16_get_channel_threshold(ADC16_Type *ptr, uint8_t ch, adc16_channel_threshold_t *config); + +#if defined (ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT) && ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT +/** + * @brief Enable oneshot mode (bus mode) + * + * @param[in] ptr An ADC16 peripheral base address. + */ +void adc16_enable_oneshot_mode(ADC16_Type *ptr); + +/** + * @brief Disable oneshot mode (bus mode) + * + * @param[in] ptr An ADC16 peripheral base address. + */ +void adc16_disable_oneshot_mode(ADC16_Type *ptr); +#endif + /** * @brief Configure the the period mode for an ADC16 instance. * @@ -275,6 +342,7 @@ hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config); * @param[in] ptr An ADC16 peripheral base address. * @param[in] trig_ch An ADC16 peripheral trigger channel. * @param[in] enable A enable control + * @return A result of setting queue enable in preemption * @retval status_success Get the result of an ADC16 conversion in oneshot mode successfully. * @retval status_invalid_argument Get the result of an ADC16 conversion in oneshot mode unsuccessfully due to passing invalid arguments. */ @@ -311,7 +379,7 @@ static inline void adc16_init_pmt_dma(ADC16_Type *ptr, uint32_t addr) } /** - * @brief Configure the start address of DMA write operation for the preemption mode. + * @brief Configure the start address of DMA write operation for the sequence mode. * * @param[in] ptr An ADC16 peripheral base address. * @param[in] config A pointer to configuration struct of @ref adc16_dma_config_t. @@ -345,6 +413,7 @@ static inline uint32_t adc16_get_status_flags(ADC16_Type *ptr) * until the ADC has completed its conversion. * * @param[in] ptr An ADC16 peripheral base address. + * @deprecated This API will be removed from V2.0.x */ static inline void adc16_disable_busywait(ADC16_Type *ptr) { @@ -356,18 +425,55 @@ static inline void adc16_disable_busywait(ADC16_Type *ptr) * until the ADC completes the conversion. * * @param[in] ptr An ADC16 peripheral base address. + * @deprecated This API will be removed from V2.0.x */ static inline void adc16_enable_busywait(ADC16_Type *ptr) { ptr->BUF_CFG0 &= ~ADC16_BUF_CFG0_WAIT_DIS_MASK; } +/** + * @brief Set nonblocking read in oneshot mode. + * @note An ADC does not block access to the associated peripheral whether it completes a conversion or not. + * + * @param[in] ptr An ADC16 peripheral base address. + */ +static inline void adc16_set_nonblocking_read(ADC16_Type *ptr) +{ + ptr->BUF_CFG0 |= ADC16_BUF_CFG0_WAIT_DIS_MASK; +} + +/** + * @brief Set blocking read in oneshot mode. + * @note An ADC blocks access to the associated peripheral bus until it completes a conversion. + * + * @param[in] ptr An ADC16 peripheral base address. + */ +static inline void adc16_set_blocking_read(ADC16_Type *ptr) +{ + ptr->BUF_CFG0 &= ~ADC16_BUF_CFG0_WAIT_DIS_MASK; +} + +/** + * @brief Judge whether the current setting is none-blocking mode or not. + * + * @param[in] ptr An ADC16 peripheral base address. + * @return A result indicating the status of bus waiting. + * @retval True means that nonblocking reading. + * @retval False means that blocking reading. + * + */ +static inline bool adc16_is_nonblocking_mode(ADC16_Type *ptr) +{ + return (ADC16_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0) ? true : false); +} + /** * @brief Get the status of a conversion validity. * * @param[in] ptr An ADC16 peripheral base address. * @param[in] ch An ADC16 peripheral channel. - * @retval Status indicating the validity of the current conversion result. + * @return Status indicating the validity of the current conversion result. * * @note This function is only used when the WAIT_DIS bit in the BUF_RESULT register is 1. */ @@ -387,7 +493,7 @@ static inline bool adc16_get_conv_valid_status(ADC16_Type *ptr, uint8_t ch) */ static inline void adc16_clear_status_flags(ADC16_Type *ptr, uint32_t mask) { - ptr->INT_STS |= mask; + ptr->INT_STS = mask; } /** @} */ @@ -488,6 +594,16 @@ void adc16_enable_temp_sensor(ADC16_Type *ptr); void adc16_disable_temp_sensor(ADC16_Type *ptr); #endif +/** + * @brief enable the transmission of adc data to the motor sensor unit. + * + * @param[in] ptr An ADC16 peripheral base address. + */ +static inline void adc16_enable_motor(ADC16_Type *ptr) +{ + ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_MOTO_EN_MASK; +} + /** @} */ #ifdef __cplusplus diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_bgpr_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_bgpr_drv.h new file mode 100644 index 00000000..42b38507 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_bgpr_drv.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BGPR_DRV_H +#define HPM_BGPR_DRV_H + +#include "hpm_common.h" +#include "hpm_soc_feature.h" +#include "hpm_bgpr_regs.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief read BGPR value + * + * @note the bgpr_index range is 0 ~ (GPR count of BGPR - 1) + * + * @param ptr BGPR base address + * @param bgpr_index BGPR GPR index + * @param bgpr_val the BGPR GPR value pointer + * + * @return hpm_stat_t status_success if read bgpr without any error + */ +static inline hpm_stat_t bgpr_read32(BGPR_Type *ptr, uint8_t bgpr_index, uint32_t *bgpr_val) +{ + hpm_stat_t stat = status_invalid_argument; + uint8_t gpr_count = sizeof(ptr->GPR) / sizeof(uint32_t); + if (bgpr_index < gpr_count) { + (*bgpr_val) = ptr->GPR[bgpr_index]; + stat = status_success; + } + return stat; +} + +/** + * @brief write BGPR value + * + * @note the bgpr_index range is 0 ~ (GPR count of BGPR - 1) + * + * @param ptr BGPR base address + * @param bgpr_index BGPR GPR index + * @param bgpr_val the BGPR GPR value + * + * @return hpm_stat_t status_success if write bgpr without any error + */ +static inline hpm_stat_t bgpr_write32(BGPR_Type *ptr, uint8_t bgpr_index, uint32_t bgpr_val) +{ + hpm_stat_t stat = status_invalid_argument; + uint8_t gpr_count = sizeof(ptr->GPR) / sizeof(uint32_t); + if (bgpr_index < gpr_count) { + ptr->GPR[bgpr_index] = bgpr_val; + stat = status_success; + } + return stat; +} + +/** + * @} + */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h index 53ea697e..c044335f 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h @@ -32,6 +32,7 @@ */ #define CAM_SENSOR_BITWIDTH_8BITS (CAM_CR1_SENSOR_BIT_WIDTH_SET(0)) #define CAM_SENSOR_BITWIDTH_10BITS (CAM_CR1_SENSOR_BIT_WIDTH_SET(1)) +#define CAM_SENSOR_BITWIDTH_24BITS (CAM_CR1_SENSOR_BIT_WIDTH_SET(2)) /** * @brief CAM IRQ mask @@ -79,6 +80,7 @@ typedef struct { uint32_t width; uint32_t height; bool pixclk_sampling_falling; + bool de_active_low; /* de_active_low must is same with hsync_active_low when dvp be used */ bool hsync_active_low; bool vsync_active_low; bool color_ext; @@ -300,7 +302,7 @@ static inline bool cam_check_status(CAM_Type *ptr, cam_status_mask_t sta_mask) */ static inline void cam_clear_status(CAM_Type *ptr, cam_status_mask_t sta_mask) { - ptr->STA |= sta_mask; + ptr->STA = sta_mask; } diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h index df698bef..40b00975 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h @@ -717,7 +717,18 @@ static inline uint8_t can_get_transmit_error_count(CAN_Type *base) } /** - * @brief Disable CAN filter + * @brief Enable a specified CAN filter + * + * @param [in] base CAN base address + * @param index CAN filter index + */ +static inline void can_enable_filter(CAN_Type *base, uint32_t index) +{ + base->ACF_EN |= (uint16_t) (1U << index); +} + +/** + * @brief Disable a specified CAN filter * * @param [in] base CAN base address * @param index CAN filter index @@ -744,6 +755,14 @@ hpm_stat_t can_get_default_config(can_config_t *config); hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq); +/** + * @brief De-initialize the CAN controller + * + * @param [in] base CAN base address + */ +void can_deinit(CAN_Type *base); + + /** * @brief Configure the Slow Speed Bit timing using low-level interface * @param [in] base CAN base address @@ -840,27 +859,30 @@ hpm_stat_t can_send_high_priority_message_nonblocking(CAN_Type *base, const can_ /** * @brief Receive CAN message using blocking transfer + * * @param [in] base CAN base address * @param [out] message CAN message buffer - * @retval API execution status - * @arg status_success API exection is successful - * @arg status_invalid_argument Invalid parameters - * @arg status_can_bit_error CAN bit error happened during receiving message - * @arg status_can_form_error CAN form error happened during receiving message - * @arg status_can_stuff_error CAN stuff error happened during receiving message - * @arg status_can_ack_error CAN ack error happened during receiving message - * @arg status_can_crc_error CAN crc error happened during receiving message - * @arg status_can_other_error Other error happened during receiving message + * + * @retval status_success API exection is successful + * @retval status_invalid_argument Invalid parameters + * @retval status_can_bit_error CAN bit error happened during receiving message + * @retval status_can_form_error CAN form error happened during receiving message + * @retval status_can_stuff_error CAN stuff error happened during receiving message + * @retval status_can_ack_error CAN ack error happened during receiving message + * @retval status_can_crc_error CAN crc error happened during receiving message + * @retval status_can_other_error Other error happened during receiving message */ hpm_stat_t can_receive_message_blocking(CAN_Type *base, can_receive_buf_t *message); /** * @brief Read Received CAN message + * * @note This API assumes that the received CAN message is available. * It can be used in the interrupt handler * @param [in] base CAN base address * @param [out] message CAN message buffer + * * @retval status_success API exection is successful * @retval status_invalid_argument Invalid parameters * @retval status_can_bit_error CAN bit error happened during receiving message diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_common.h b/common/libraries/hpm_sdk/drivers/inc/hpm_common.h index 28e028f5..25c0d7f6 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_common.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_common.h @@ -49,6 +49,14 @@ #define MIN(a, b) ((a) < (b) ? (a) : (b)) #endif +#ifndef HPM_ALIGN_DOWN +#define HPM_ALIGN_DOWN(a, n) ((uint32_t)(a) & ~(n-1U)) +#endif + +#ifndef HPM_ALIGN_UP +#define HPM_ALIGN_UP(a, n) (((uint32_t)(a) + (n-1U)) & ~(n-1U)) +#endif + #define HPM_BITSMASK(val, offset) ((uint32_t)(val) << (offset)) #define IS_HPM_BITMASK_SET(val, mask) (((uint32_t)(val) & (uint32_t)(mask)) != 0U) #define IS_HPM_BIT_SET(val, offset) (((uint32_t)(val) & (1UL << (offset))) != 0U) @@ -58,6 +66,9 @@ #define HPM_BREAK_IF(cond) if (cond) { break; } #define HPM_CONTINUE_IF(cond) if (cond) { continue; } +#define HPM_DIV_ROUND_CLOSEST(x, div) (((x) + (div) / 2) / (div)) +#define HPM_DIV_ROUND_UP(x, div) (((x) + (div) - 1) / (div)) + #define HPM_CHECK_RET(x) \ do { \ stat = (x); \ @@ -69,6 +80,39 @@ #define SIZE_1KB (1024UL) #define SIZE_1MB (1048576UL) +#define BIT0_MASK (0x00000001UL) +#define BIT1_MASK (0x00000002UL) +#define BIT2_MASK (0x00000004UL) +#define BIT3_MASK (0x00000008UL) +#define BIT4_MASK (0x00000010UL) +#define BIT5_MASK (0x00000020UL) +#define BIT6_MASK (0x00000040UL) +#define BIT7_MASK (0x00000080UL) +#define BIT8_MASK (0x00000100UL) +#define BIT9_MASK (0x00000200UL) +#define BIT10_MASK (0x00000400UL) +#define BIT11_MASK (0x00000800UL) +#define BIT12_MASK (0x00001000UL) +#define BIT13_MASK (0x00002000UL) +#define BIT14_MASK (0x00004000UL) +#define BIT15_MASK (0x00008000UL) +#define BIT16_MASK (0x00010000UL) +#define BIT17_MASK (0x00020000UL) +#define BIT18_MASK (0x00040000UL) +#define BIT19_MASK (0x00080000UL) +#define BIT20_MASK (0x00100000UL) +#define BIT21_MASK (0x00200000UL) +#define BIT22_MASK (0x00400000UL) +#define BIT23_MASK (0x00800000UL) +#define BIT24_MASK (0x01000000UL) +#define BIT25_MASK (0x02000000UL) +#define BIT26_MASK (0x04000000UL) +#define BIT27_MASK (0x08000000UL) +#define BIT28_MASK (0x10000000UL) +#define BIT29_MASK (0x20000000UL) +#define BIT30_MASK (0x40000000UL) +#define BIT31_MASK (0x80000000UL) + typedef uint32_t hpm_stat_t; /* @brief Enum definition for the Status group @@ -108,11 +152,14 @@ enum { status_group_pllctlv2, status_group_ffa, status_group_mcan, + status_group_ewdg, status_group_middleware_start = 500, status_group_sdmmc = status_group_middleware_start, status_group_audio_codec, status_group_dma_manager, + status_group_spi_nor_flash, + status_group_touch, }; /* @brief Common status code definitions */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h index 9214b919..4d2a9e48 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h @@ -23,7 +23,8 @@ typedef enum { dac_mode_direct = 0, dac_mode_step, - dac_mode_buffer + dac_mode_buffer, + dac_mode_trig } dac_mode_t; typedef enum { diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h index c9dd1ac4..653714ca 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h @@ -20,6 +20,9 @@ * @{ */ +#define DMA_CHANNEL_PRIORITY_LOW (0U) +#define DMA_CHANNEL_PRIORITY_HIGH (1U) + #define DMA_NUM_TRANSFER_PER_BURST_1T (0U) #define DMA_NUM_TRANSFER_PER_BURST_2T (1U) #define DMA_NUM_TRANSFER_PER_BURST_4T (2U) @@ -41,24 +44,24 @@ #define DMA_STATUS_ABORT_SHIFT (8U) #define DMA_STATUS_TC_SHIFT (16U) -#define DMA_CHANNEL_STATUS_ONGOING (1U) -#define DMA_CHANNEL_STATUS_ERROR (2U) -#define DMA_CHANNEL_STATUS_ABORT (4U) -#define DMA_CHANNEL_STATUS_TC (8U) +#define DMA_CHANNEL_STATUS_ONGOING (1U) +#define DMA_CHANNEL_STATUS_ERROR (2U) +#define DMA_CHANNEL_STATUS_ABORT (4U) +#define DMA_CHANNEL_STATUS_TC (8U) -#define DMA_CHANNEL_IRQ_STATUS_ERROR(x) (uint32_t)(1 << (DMA_STATUS_ERROR_SHIFT + x)) -#define DMA_CHANNEL_IRQ_STATUS_ABORT(x) (uint32_t)(1 << (DMA_STATUS_ABORT_SHIFT + x)) -#define DMA_CHANNEL_IRQ_STATUS_TC(x) (uint32_t)(1 << (DMA_STATUS_TC_SHIFT + x)) -#define DMA_CHANNEL_IRQ_STATUS(x) (uint32_t)(DMA_CHANNEL_IRQ_STATUS_TC(x) | \ - DMA_CHANNEL_IRQ_STATUS_ABORT(x) | \ - DMA_CHANNEL_IRQ_STATUS_ERROR(x)) +#define DMA_CHANNEL_IRQ_STATUS_ERROR(x) (uint32_t)(1 << (DMA_STATUS_ERROR_SHIFT + x)) +#define DMA_CHANNEL_IRQ_STATUS_ABORT(x) (uint32_t)(1 << (DMA_STATUS_ABORT_SHIFT + x)) +#define DMA_CHANNEL_IRQ_STATUS_TC(x) (uint32_t)(1 << (DMA_STATUS_TC_SHIFT + x)) +#define DMA_CHANNEL_IRQ_STATUS(x) (uint32_t)(DMA_CHANNEL_IRQ_STATUS_TC(x) | \ + DMA_CHANNEL_IRQ_STATUS_ABORT(x) | \ + DMA_CHANNEL_IRQ_STATUS_ERROR(x)) #define DMA_CHANNEL_IRQ_STATUS_GET_ALL_TC(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_TC_SHIFT)) #define DMA_CHANNEL_IRQ_STATUS_GET_ALL_ABORT(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_ABORT_SHIFT)) #define DMA_CHANNEL_IRQ_STATUS_GET_ALL_ERROR(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_ERROR_SHIFT)) -#define DMA_HANDSHAKE_MODE_HANDSHAKE (1U) #define DMA_HANDSHAKE_MODE_NORMAL (0U) +#define DMA_HANDSHAKE_MODE_HANDSHAKE (1U) #define DMA_ADDRESS_CONTROL_INCREMENT (0U) #define DMA_ADDRESS_CONTROL_DECREMENT (1U) @@ -196,15 +199,84 @@ static inline bool dma_channel_is_enable(DMA_Type *ptr, uint32_t ch_index) } /** - * @brief Get DMA channel residue transfer size + * @brief Set DMA channel priority * * @param[in] ptr DMA base address * @param[in] ch_index Index of the channel + * @param[in] priority dma priority + * @arg @ref DMA_PRIORITY_LOW + * @arg @ref DMA_PRIORITY_HIGH * - * @return residue transfer size + */ +static inline void dma_set_priority(DMA_Type *ptr, uint32_t ch_index, uint8_t priority) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_PRIORITY_MASK) | DMA_CHCTRL_CTRL_PRIORITY_SET(priority); +} + +/** + * @brief Set DMA channel source work mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] mode source work mode + * @arg @ref DMA_HANDSHAKE_MODE_NORMAL + * @arg @ref DMA_HANDSHAKE_MODE_HANDSHAKE * */ -static inline uint32_t dma_get_residue_transfer_size(DMA_Type *ptr, uint32_t ch_index) +static inline void dma_set_source_work_mode(DMA_Type *ptr, uint32_t ch_index, uint8_t mode) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCMODE_MASK) | DMA_CHCTRL_CTRL_SRCMODE_SET(mode); +} + +/** + * @brief Set DMA channel destination work mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] mode destination work mode + * @arg @ref DMA_HANDSHAKE_MODE_NORMAL + * @arg @ref DMA_HANDSHAKE_MODE_HANDSHAKE + * + */ +static inline void dma_set_destination_work_mode(DMA_Type *ptr, uint32_t ch_index, uint8_t mode) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_DSTMODE_MASK) | DMA_CHCTRL_CTRL_DSTMODE_SET(mode); +} + +/** + * @brief Set DMA channel source burst size + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] burstsize source burst size + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_1T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_2T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_4T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_8T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_16T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_32T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_64T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_128T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_256T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_512T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_1024T + * + */ +static inline void dma_set_source_burst_size(DMA_Type *ptr, uint32_t ch_index, uint8_t burstsize) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(burstsize); +} + +/** + * @brief Get DMA channel remaining transfer size + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * + * @return remaining transfer size + * + */ +static inline uint32_t dma_get_remaining_transfer_size(DMA_Type *ptr, uint32_t ch_index) { return ptr->CHCTRL[ch_index].TRANSIZE; } @@ -223,6 +295,38 @@ static inline void dma_set_transfer_size(DMA_Type *ptr, uint32_t ch_index, uint3 ptr->CHCTRL[ch_index].TRANSIZE = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_width); } +/** + * @brief Set DMA channel source width + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] width transfer source width of the channel + * @arg @ref DMA_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_TRANSFER_WIDTH_WORD + * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD + */ +static inline void dma_set_source_width(DMA_Type *ptr, uint32_t ch_index, uint8_t width) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCWIDTH_MASK) | DMA_CHCTRL_CTRL_SRCWIDTH_SET(width); +} + +/** + * @brief Set DMA channel destination width + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] width transfer destination width of the channel + * @arg @ref DMA_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_TRANSFER_WIDTH_WORD + * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD + */ +static inline void dma_set_destination_width(DMA_Type *ptr, uint32_t ch_index, uint8_t width) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_DSTWIDTH_MASK) | DMA_CHCTRL_CTRL_DSTWIDTH_SET(width); +} + /** * @brief Set DMA channel transfer width and size in byte * @@ -271,6 +375,38 @@ static inline void dma_set_destination_address(DMA_Type *ptr, uint32_t ch_index, ptr->CHCTRL[ch_index].DSTADDR = addr; } +/** + * @brief Set DMA channel source address control mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr_ctrl source address control mode + * @arg @ref DMA_ADDRESS_CONTROL_INCREMENT + * @arg @ref DMA_ADDRESS_CONTROL_DECREMENT + * @arg @ref DMA_ADDRESS_CONTROL_FIXED + * + */ +static inline void dma_set_source_address_ctrl(DMA_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) | DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(addr_ctrl); +} + +/** + * @brief Set DMA channel destination address control mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr_ctrl destination address control mode + * @arg @ref DMA_ADDRESS_CONTROL_INCREMENT + * @arg @ref DMA_ADDRESS_CONTROL_DECREMENT + * @arg @ref DMA_ADDRESS_CONTROL_FIXED + * + */ +static inline void dma_set_destination_address_ctrl(DMA_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) | DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(addr_ctrl); +} + /** * @brief Abort channel transfer with mask * @@ -315,10 +451,10 @@ static inline bool dma_has_linked_pointer_configured(DMA_Type *ptr, uint32_t ch_ * @param[in] ptr DMA base address * @param[in] ch_index Target channel index to be checked * - * @retval 1 if transfer is still ongoing - * @retval 2 if any error occurred during transferring - * @retval 4 if transfer is aborted - * @retval 8 if transfer is finished without error + * @retval DMA_CHANNEL_STATUS_ONGOING if transfer is still ongoing + * @retval DMA_CHANNEL_STATUS_ERROR if any error occurred during transferring + * @retval DMA_CHANNEL_STATUS_ABORT if transfer is aborted + * @retval DMA_CHANNEL_STATUS_TC if transfer is finished without error */ static inline uint32_t dma_check_transfer_status(DMA_Type *ptr, uint8_t ch_index) { @@ -369,7 +505,7 @@ static inline void dma_clear_transfer_status(DMA_Type *ptr, uint8_t ch_index) */ static inline void dma_enable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) { - ptr->CHCTRL[ch_index].CTRL &= ~(interrupt_mask & (DMA_INTERRUPT_MASK_ERROR | DMA_INTERRUPT_MASK_ABORT | DMA_INTERRUPT_MASK_TERMINAL_COUNT)); + ptr->CHCTRL[ch_index].CTRL &= ~(interrupt_mask & DMA_INTERRUPT_MASK_ALL); } /** @@ -381,7 +517,7 @@ static inline void dma_enable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index, */ static inline void dma_disable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) { - ptr->CHCTRL[ch_index].CTRL |= (interrupt_mask & (DMA_INTERRUPT_MASK_ERROR | DMA_INTERRUPT_MASK_ABORT | DMA_INTERRUPT_MASK_TERMINAL_COUNT)); + ptr->CHCTRL[ch_index].CTRL |= (interrupt_mask & DMA_INTERRUPT_MASK_ALL); } @@ -394,7 +530,7 @@ static inline void dma_disable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index */ static inline uint32_t dma_check_channel_interrupt_mask(DMA_Type *ptr, uint8_t ch_index) { - return ptr->CHCTRL[ch_index].CTRL & (DMA_INTERRUPT_MASK_ERROR | DMA_INTERRUPT_MASK_ABORT | DMA_INTERRUPT_MASK_TERMINAL_COUNT); + return ptr->CHCTRL[ch_index].CTRL & DMA_INTERRUPT_MASK_ALL; } /** diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_dmav2_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_dmav2_drv.h new file mode 100644 index 00000000..ee624711 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_dmav2_drv.h @@ -0,0 +1,682 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAV2_DRV_H +#define HPM_DMAV2_DRV_H +#include "hpm_common.h" +#include "hpm_soc_feature.h" +#include "hpm_dmav2_regs.h" + +/** + * + * @brief DMA driver APIs + * @defgroup dma_interface DMA driver APIs + * @ingroup io_interfaces + * @{ + */ + +#define DMA_Type DMAV2_Type + +#define DMA_CHANNEL_PRIORITY_LOW (0U) +#define DMA_CHANNEL_PRIORITY_HIGH (1U) + +#define DMA_NUM_TRANSFER_PER_BURST_1T (0U) +#define DMA_NUM_TRANSFER_PER_BURST_2T (1U) +#define DMA_NUM_TRANSFER_PER_BURST_4T (2U) +#define DMA_NUM_TRANSFER_PER_BURST_8T (3U) +#define DMA_NUM_TRANSFER_PER_BURST_16T (4U) +#define DMA_NUM_TRANSFER_PER_BURST_32T (5U) +#define DMA_NUM_TRANSFER_PER_BURST_64T (6U) +#define DMA_NUM_TRANSFER_PER_BURST_128T (7U) +#define DMA_NUM_TRANSFER_PER_BURST_256T (8U) +#define DMA_NUM_TRANSFER_PER_BURST_512T (9U) +#define DMA_NUM_TRANSFER_PER_BURST_1024T (10U) + +#define DMA_TRANSFER_WIDTH_BYTE (0U) +#define DMA_TRANSFER_WIDTH_HALF_WORD (1U) +#define DMA_TRANSFER_WIDTH_WORD (2U) +#define DMA_TRANSFER_WIDTH_DOUBLE_WORD (3U) + +#define DMA_CHANNEL_STATUS_ONGOING (1U) +#define DMA_CHANNEL_STATUS_ERROR (2U) +#define DMA_CHANNEL_STATUS_ABORT (4U) +#define DMA_CHANNEL_STATUS_TC (8U) +#define DMA_CHANNEL_STATUS_HALF_TC (16U) + +#define DMA_CHANNEL_IRQ_STATUS_ERROR(x) (uint32_t)(1 << x) +#define DMA_CHANNEL_IRQ_STATUS_ABORT(x) (uint32_t)(1 << x) +#define DMA_CHANNEL_IRQ_STATUS_TC(x) (uint32_t)(1 << x) +#define DMA_CHANNEL_IRQ_STATUS_HALF_TC(x) (uint32_t)(1 << x) + +#define DMA_HANDSHAKE_MODE_NORMAL (0U) +#define DMA_HANDSHAKE_MODE_HANDSHAKE (1U) + +#define DMA_ADDRESS_CONTROL_INCREMENT (0U) +#define DMA_ADDRESS_CONTROL_DECREMENT (1U) +#define DMA_ADDRESS_CONTROL_FIXED (2U) + +#define DMA_SRC_BURST_OPT_STANDAND_SIZE (0U) +#define DMA_SRC_BURST_OPT_CUSTOM_SIZE (1U) + +#define DMA_HANDSHAKE_OPT_ONE_BURST (0U) +#define DMA_HANDSHAKE_OPT_ALL_TRANSIZE (1U) + +#define DMA_INTERRUPT_MASK_NONE (0U) +#define DMA_INTERRUPT_MASK_ERROR DMAV2_CHCTRL_CTRL_INTERRMASK_MASK +#define DMA_INTERRUPT_MASK_ABORT DMAV2_CHCTRL_CTRL_INTABTMASK_MASK +#define DMA_INTERRUPT_MASK_TERMINAL_COUNT DMAV2_CHCTRL_CTRL_INTTCMASK_MASK +#define DMA_INTERRUPT_MASK_HALF_TC DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK +#define DMA_INTERRUPT_MASK_ALL \ + (uint8_t)(DMA_INTERRUPT_MASK_TERMINAL_COUNT \ + | DMA_INTERRUPT_MASK_ABORT \ + | DMA_INTERRUPT_MASK_ERROR \ + | DMA_INTERRUPT_MASK_HALF_TC) + +#define DMA_SUPPORT_64BIT_ADDR (0) + + +enum { + dmav2_state_idle = 0, + dmav2_state_read, + dmav2_state_read_ack, + dmav2_state_write, + dmav2_state_write_ack, + dmav2_state_ll, + dmav2_state_end, + dmav2_state_end_wait, +}; + +/** + * @brief Linked descriptor + * + * It is consumed by DMA controlled directly + */ +typedef struct dma_linked_descriptor { + uint32_t ctrl; /**< Control */ + uint32_t trans_size; /**< Transfer size in source width */ + uint32_t src_addr; /**< Source address */ + uint32_t req_ctrl; /**< Request select */ + uint32_t dst_addr; /**< Destination address */ + uint32_t reserved0; /**< not used on dmav2 */ + uint32_t linked_ptr; /**< Linked descriptor address */ + uint32_t reserved1; /**< not used on dmav2 */ +} dma_linked_descriptor_t; + +/* @brief Channel config */ +typedef struct dma_channel_config { + uint8_t priority; /**< Channel priority */ + uint8_t src_burst_size; /**< Source burst size */ + uint8_t src_mode; /**< Source work mode */ + uint8_t dst_mode; /**< Destination work mode */ + uint8_t src_width; /**< Source width */ + uint8_t dst_width; /**< Destination width */ + uint8_t src_addr_ctrl; /**< Source address control */ + uint8_t dst_addr_ctrl; /**< Destination address control */ + uint16_t interrupt_mask; /**< Interrupt mask */ + uint32_t src_addr; /**< Source address */ + uint32_t dst_addr; /**< Destination address */ + uint32_t linked_ptr; /**< Next linked descriptor */ + uint32_t size_in_byte; /**< Total size to be transferred in byte */ + bool en_infiniteloop; /**< Infinite loop transfer enable. Attention: only DMAV2 support */ + uint8_t handshake_opt; /**< Handshake transfer option. Attention: only DMAV2 support */ + uint8_t burst_opt; /**< Burst size option. Attention: only DMAV2 support */ +} dma_channel_config_t; + +/* @brief Channel config */ +typedef struct dma_handshake_config { + uint32_t dst; + uint32_t src; + uint32_t size_in_byte; + uint8_t data_width; /* data width, value defined by DMA_TRANSFER_WIDTH_xxx */ + uint8_t ch_index; + bool dst_fixed; + bool src_fixed; + bool en_infiniteloop; + uint16_t interrupt_mask; +} dma_handshake_config_t; + + +/* @brief DMA specific status */ +enum { + status_dma_transfer_done = MAKE_STATUS(status_group_dma, 0), + status_dma_transfer_error = MAKE_STATUS(status_group_dma, 1), + status_dma_transfer_abort = MAKE_STATUS(status_group_dma, 2), + status_dma_transfer_ongoing = MAKE_STATUS(status_group_dma, 3), + status_dma_alignment_error = MAKE_STATUS(status_group_dma, 4), + status_dma_transfer_half_done = MAKE_STATUS(status_group_dma, 5), +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Reset DMA + * + * @param[in] ptr DMA base address + */ +static inline void dma_reset(DMAV2_Type *ptr) +{ + ptr->DMACTRL |= DMAV2_DMACTRL_RESET_MASK; +} + +/** + * @brief Enable DMA channel + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel to be enabled + * + * @return status_success if everything's okay + */ +static inline hpm_stat_t dma_enable_channel(DMAV2_Type *ptr, uint32_t ch_index) +{ + ptr->CHCTRL[ch_index].CTRL |= DMAV2_CHCTRL_CTRL_ENABLE_MASK; + + if ((ptr->CHEN == 0) || !(ptr->CHEN & 1 << ch_index)) { + return status_fail; + } + return status_success; +} + +/** + * @brief Disable DMA channel + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel to be disabled + * + */ +static inline void dma_disable_channel(DMAV2_Type *ptr, uint32_t ch_index) +{ + ptr->CHCTRL[ch_index].CTRL &= ~DMAV2_CHCTRL_CTRL_ENABLE_MASK; +} + +/** + * @brief Check whether DMA channel is enable + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * + * @return true if DMA channel is enable + * + */ +static inline bool dma_channel_is_enable(DMAV2_Type *ptr, uint32_t ch_index) +{ + return (ptr->CHCTRL[ch_index].CTRL & DMAV2_CHCTRL_CTRL_ENABLE_MASK) ? true : false; +} + +/** + * @brief Set DMA channel priority + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] priority dma priority + * @arg @ref DMA_PRIORITY_LOW + * @arg @ref DMA_PRIORITY_HIGH + * + */ +static inline void dma_set_priority(DMAV2_Type *ptr, uint32_t ch_index, uint8_t priority) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_PRIORITY_MASK) | DMAV2_CHCTRL_CTRL_PRIORITY_SET(priority); +} + +/** + * @brief Set DMA channel source work mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] mode source work mode + * @arg @ref DMA_HANDSHAKE_MODE_NORMAL + * @arg @ref DMA_HANDSHAKE_MODE_HANDSHAKE + * + */ +static inline void dma_set_source_work_mode(DMAV2_Type *ptr, uint32_t ch_index, uint8_t mode) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCMODE_MASK) | DMAV2_CHCTRL_CTRL_SRCMODE_SET(mode); +} + +/** + * @brief Set DMA channel destination work mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] mode destination work mode + * @arg @ref DMA_HANDSHAKE_MODE_NORMAL + * @arg @ref DMA_HANDSHAKE_MODE_HANDSHAKE + * + */ +static inline void dma_set_destination_work_mode(DMAV2_Type *ptr, uint32_t ch_index, uint8_t mode) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DSTMODE_MASK) | DMAV2_CHCTRL_CTRL_DSTMODE_SET(mode); +} + +/** + * @brief Set DMA channel source burst size + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] burstsize source burst size + * when BURSTOPT is 0, please reference follows: + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_1T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_2T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_4T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_8T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_16T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_32T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_64T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_128T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_256T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_512T + * @arg @ref DMA_NUM_TRANSFER_PER_BURST_1024T + * when BURSTOPT is 1, burst size is (burstsize + 1). + * + */ +static inline void dma_set_source_burst_size(DMAV2_Type *ptr, uint32_t ch_index, uint8_t burstsize) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) | DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(burstsize); +} + +/** + * @brief Get DMA channel remaining transfer size + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * + * @return remaining transfer size + * + */ +static inline uint32_t dma_get_remaining_transfer_size(DMAV2_Type *ptr, uint32_t ch_index) +{ + return ptr->CHCTRL[ch_index].TRANSIZE; +} + +/** + * @brief Set DMA channel transfer size + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] size_in_width transfer size of the channel. The width is current dma channel configured source width. + * Transfer total bytes are (size_in_width * source width). + * + */ +static inline void dma_set_transfer_size(DMAV2_Type *ptr, uint32_t ch_index, uint32_t size_in_width) +{ + ptr->CHCTRL[ch_index].TRANSIZE = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_width); +} + +/** + * @brief Set DMA channel source width + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] width transfer source width of the channel + * @arg @ref DMA_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_TRANSFER_WIDTH_WORD + * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD + */ +static inline void dma_set_source_width(DMAV2_Type *ptr, uint32_t ch_index, uint8_t width) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(width); +} + +/** + * @brief Set DMA channel destination width + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] width transfer destination width of the channel + * @arg @ref DMA_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_TRANSFER_WIDTH_WORD + * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD + */ +static inline void dma_set_destination_width(DMAV2_Type *ptr, uint32_t ch_index, uint8_t width) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) | DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(width); +} + +/** + * @brief Set DMA channel transfer width and size in byte + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] src_width transfer source width of the channel + * @arg @ref DMA_TRANSFER_WIDTH_BYTE + * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD + * @arg @ref DMA_TRANSFER_WIDTH_WORD + * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD + * @param[in] size_in_byte transfer size in byte of the channel. The dma transfer size is (size_in_byte >> src_width). + * + */ +static inline void dma_set_transfer_src_width_byte_size(DMAV2_Type *ptr, uint32_t ch_index, uint8_t src_width, uint32_t size_in_byte) +{ + assert((src_width == DMA_TRANSFER_WIDTH_BYTE) || (src_width == DMA_TRANSFER_WIDTH_HALF_WORD) + || (src_width == DMA_TRANSFER_WIDTH_WORD) || (src_width == DMA_TRANSFER_WIDTH_DOUBLE_WORD)); + + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(src_width); + ptr->CHCTRL[ch_index].TRANSIZE = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_byte >> src_width); +} + +/** + * @brief Set DMA channel source address + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr source address + * + */ +static inline void dma_set_source_address(DMAV2_Type *ptr, uint32_t ch_index, uint32_t addr) +{ + ptr->CHCTRL[ch_index].SRCADDR = addr; +} + +/** + * @brief Set DMA channel destination address + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr destination address + * + */ +static inline void dma_set_destination_address(DMAV2_Type *ptr, uint32_t ch_index, uint32_t addr) +{ + ptr->CHCTRL[ch_index].DSTADDR = addr; +} + +/** + * @brief Set DMA channel source address control mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr_ctrl source address control mode + * @arg @ref DMA_ADDRESS_CONTROL_INCREMENT + * @arg @ref DMA_ADDRESS_CONTROL_DECREMENT + * @arg @ref DMA_ADDRESS_CONTROL_FIXED + * + */ +static inline void dma_set_source_address_ctrl(DMAV2_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) | DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(addr_ctrl); +} + +/** + * @brief Set DMA channel destination address control mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] addr_ctrl destination address control mode + * @arg @ref DMA_ADDRESS_CONTROL_INCREMENT + * @arg @ref DMA_ADDRESS_CONTROL_DECREMENT + * @arg @ref DMA_ADDRESS_CONTROL_FIXED + * + */ +static inline void dma_set_destination_address_ctrl(DMAV2_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) | DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(addr_ctrl); +} + +/** + * @brief Set DMA channel infinite loop mode + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] infinite_loop false - normal mode(single times mode); true - infinite loop mode(cycle mode) + * + */ +static inline void dma_set_infinite_loop_mode(DMAV2_Type *ptr, uint32_t ch_index, bool infinite_loop) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) | DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(infinite_loop); +} + +/** + * @brief Set DMA channel source burst option + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] burst_opt burst option + * @arg @ref DMA_SRC_BURST_OPT_STANDAND_SIZE + * @arg @ref DMA_SRC_BURST_OPT_CUSTOM_SIZE + * + */ +static inline void dma_set_src_busrt_option(DMAV2_Type *ptr, uint32_t ch_index, uint8_t burst_opt) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) | DMAV2_CHCTRL_CTRL_BURSTOPT_SET(burst_opt); +} + +/** + * @brief Set DMA channel handshake option + * + * @param[in] ptr DMA base address + * @param[in] ch_index Index of the channel + * @param[in] handshake_opt handshake option + * @arg @ref DMA_HANDSHAKE_OPT_ONE_BURST + * @arg @ref DMA_HANDSHAKE_OPT_ALL_TRANSIZE + * + */ +static inline void dma_set_handshake_option(DMAV2_Type *ptr, uint32_t ch_index, uint8_t handshake_opt) +{ + ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) | DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(handshake_opt); +} + +/** + * @brief Abort channel transfer with mask + * + * @param[in] ptr DMA base address + * @param[in] ch_index_mask Mask of channels to be aborted + */ +static inline void dma_abort_channel(DMAV2_Type *ptr, uint32_t ch_index_mask) +{ + ptr->CHABORT |= DMAV2_CHABORT_CHABORT_SET(ch_index_mask); +} + +/** + * @brief Check if channels are enabled with mask + * + * @param[in] ptr DMA base address + * @param[in] ch_index_mask Mask of channels to be checked + * + * @return Enabled channel mask + */ +static inline uint32_t dma_check_enabled_channel(DMAV2_Type *ptr, + uint32_t ch_index_mask) +{ + return (ch_index_mask & ptr->CHEN); +} + +/** + * @brief Check if linked pointer has been configured + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index to be checked + * + * @return true if linked pointer has been configured + */ +static inline bool dma_has_linked_pointer_configured(DMAV2_Type *ptr, uint32_t ch_index) +{ + return ptr->CHCTRL[ch_index].LLPOINTER != 0; +} + +/** + * @brief Check transfer status + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index to be checked + * + * @retval DMA_CHANNEL_STATUS_ONGOING if transfer is still ongoing + * @retval DMA_CHANNEL_STATUS_ERROR if any error occurred during transferring + * @retval DMA_CHANNEL_STATUS_ABORT if transfer is aborted + * @retval DMA_CHANNEL_STATUS_TC if transfer is finished without error + * @retval DMA_CHANNEL_STATUS_HALF_TC if half transfer complete without error + */ +static inline uint32_t dma_check_transfer_status(DMAV2_Type *ptr, uint8_t ch_index) +{ + uint32_t dma_status = 0; + + if (ptr->INTTCSTS & (1 << ch_index)) { + dma_status |= DMA_CHANNEL_STATUS_TC; + ptr->INTTCSTS = (1 << ch_index); /* W1C clear status*/ + } + if (ptr->INTHALFSTS & (1 << ch_index)) { + dma_status |= DMA_CHANNEL_STATUS_HALF_TC; + ptr->INTHALFSTS = (1 << ch_index); /* W1C clear status*/ + } + if (ptr->INTERRSTS & (1 << ch_index)) { + dma_status |= DMA_CHANNEL_STATUS_ERROR; + ptr->INTERRSTS = (1 << ch_index); /* W1C clear status*/ + } + if (ptr->INTABORTSTS & (1 << ch_index)) { + dma_status |= DMA_CHANNEL_STATUS_ABORT; + ptr->INTABORTSTS = (1 << ch_index); /* W1C clear status*/ + } + if (dma_status == 0) { + dma_status = DMA_CHANNEL_STATUS_ONGOING; + } + return dma_status; +} + +/** + * @brief Clear transfer status + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index + * + */ +static inline void dma_clear_transfer_status(DMAV2_Type *ptr, uint8_t ch_index) +{ + /* W1C */ + ptr->INTHALFSTS = (1 << ch_index); + ptr->INTTCSTS = (1 << ch_index); + ptr->INTABORTSTS = (1 << ch_index); + ptr->INTERRSTS = (1 << ch_index); +} + +/** + * @brief Enable DMA Channel interrupt + * + * @param [in] ptr DMA base address + * @param [in] ch_index Target channel index + * @param [in] interrupt_mask Interrupt mask + */ +static inline void dma_enable_channel_interrupt(DMAV2_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) +{ + ptr->CHCTRL[ch_index].CTRL &= ~(interrupt_mask & DMA_INTERRUPT_MASK_ALL); +} + +/** + * @brief Disable DMA Channel interrupt + * + * @param [in] ptr DMA base address + * @param [in] ch_index Target channel index + * @param [in] interrupt_mask Interrupt mask + */ +static inline void dma_disable_channel_interrupt(DMAV2_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) +{ + ptr->CHCTRL[ch_index].CTRL |= (interrupt_mask & DMA_INTERRUPT_MASK_ALL); +} + + +/** + * @brief Check Channel interrupt master + * + * @param[in] ptr DMA base address + * @param[in] ch_index Target channel index to be checked + * @return uint32_t Interrupt mask + */ +static inline uint32_t dma_check_channel_interrupt_mask(DMAV2_Type *ptr, uint8_t ch_index) +{ + return ptr->CHCTRL[ch_index].CTRL & DMA_INTERRUPT_MASK_ALL; +} + +/** + * @brief Get default channel config + * + * @param[in] ptr DMA base address + * @param[in] ch Channel config + */ +void dma_default_channel_config(DMAV2_Type *ptr, dma_channel_config_t *ch); + +/** + * @brief Setup DMA channel + * + * @param[in] ptr DMA base address + * @param[in] ch_num Target channel index to be configured + * @param[in] ch Channel config + * @param[in] start_transfer Set true to start transfer + * + * @return status_success if everything is okay + */ +hpm_stat_t dma_setup_channel(DMAV2_Type *ptr, uint8_t ch_num, + dma_channel_config_t *ch, bool start_transfer); + +/** + * @brief Config linked descriptor function + * + * @param[in] ptr DMA base address + * @param[in] descriptor Linked descriptor pointer + * @param[in] ch_num Target channel index to be configured + * @param[in] config Descriptor config pointer + * + * @return status_success if everything is okay + */ +hpm_stat_t dma_config_linked_descriptor(DMAV2_Type *ptr, dma_linked_descriptor_t *descriptor, uint8_t ch_num, dma_channel_config_t *config); + +/** + * @brief Start DMA copy + * + * @param[in] ptr DMA base address + * @param[in] ch_num Target channel index + * @param[in] dst Destination address + * @param[in] src Source Address + * @param[in] size_in_byte Size in byte + * @param[in] burst_len_in_byte Burst length in byte + * + * @return status_success if everthing is okay + * @note: dst, src, size should be aligned with burst_len_in_byte + */ +hpm_stat_t dma_start_memcpy(DMAV2_Type *ptr, uint8_t ch_num, + uint32_t dst, uint32_t src, + uint32_t size_in_byte, uint32_t burst_len_in_byte); + +/** + * @brief Get default handshake config + * + * @param[in] ptr DMA base address + * @param[in] config default config + */ +void dma_default_handshake_config(DMAV2_Type *ptr, dma_handshake_config_t *config); + +/** + * @brief config dma handshake function + * + * @param[in] ptr DMA base address + * @param[in] pconfig dma handshake config pointer + * @param[in] start_transfer Set true to start transfer + * + * @return status_success if everything is okay + */ +hpm_stat_t dma_setup_handshake(DMAV2_Type *ptr, dma_handshake_config_t *pconfig, bool start_transfer); + +/** + * @brief Check whether DMA is idle + * @param [in] ptr DMA base address + * @return true DMA is idle + * @return false DMA is busy + */ +static inline bool dma_is_idle(DMAV2_Type *ptr) +{ + return (DMAV2_IDMISC_DMASTATE_GET(ptr->IDMISC) == dmav2_state_idle) ? true : false; +} + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_DMAV2_DRV_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_enc_pos_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_enc_pos_drv.h new file mode 100644 index 00000000..b886f802 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_enc_pos_drv.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ENC_POS_COMMON_H +#define HPM_ENC_POS_COMMON_H + +#include "hpm_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief caculate degree of angle from pos + * + * @param[in] pos position value + * @return degree of angle. + */ +float encoder_position_to_deg(uint32_t pos); + +/** + * @brief caculate posistion from degree of angle + * + * @param[in] deg degree of angle + * @return position value. + */ +uint32_t encoder_deg_to_position(float deg); + +/** + * @brief caculate radian of angle from pos + * + * @param[in] pos position value + * @return radian of angle. + */ +float encoder_position_to_rad(uint32_t pos); + +/** + * @brief caculate posistion from radian of angle + * + * @param[in] rad radian of angle + * @return position value. + */ +uint32_t encoder_rad_to_position(float rad); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_ENC_POS_COMMON_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h index d7cbb8bf..ebcfb2c6 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -55,14 +55,14 @@ *--------------------------------------------------------------------- */ -/** @brief Programmable burst length selections */ +/** @brief interrupt enable type */ typedef enum { enet_normal_int_sum_en = ENET_DMA_INTR_EN_NIE_MASK, enet_aboarmal_int_sum_en = ENET_DMA_INTR_EN_AIE_MASK, enet_receive_int_en = ENET_DMA_INTR_EN_RIE_MASK } enet_interrupt_enable_t; -/** @brief Programmable burst length selections */ +/** @brief interrupt mask type */ typedef enum { enet_lpi_int_mask = ENET_INTR_MASK_LPIIM_MASK, enet_rgsmii_int_mask = ENET_INTR_MASK_RGSMIIIM_MASK @@ -592,8 +592,9 @@ uint32_t enet_get_mmc_tx_interrupt_status(ENET_Type *ptr); * @param[in] desc A pointer to descriptor config * @param[in] cfg A pointer to mac config * @param[in] int_cfg A pointer to the masks of the specified enabled interrupts and the specified masked interrupts + * @return A result of the specified controller initialization */ -int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *cfg, enet_int_config_t *int_config); +hpm_stat_t enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *cfg, enet_int_config_t *int_config); /** * @brief Set port line speed @@ -631,6 +632,14 @@ uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr); */ void enet_write_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data); +/** + * @brief Resume reception process + * + * @param[in] ptr An Ethernet peripheral base address + * + */ +void enet_rx_resume(ENET_Type *ptr); + /** * @brief Check if there is a received frame * diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_ewdg_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_ewdg_drv.h new file mode 100644 index 00000000..cb538cfc --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_ewdg_drv.h @@ -0,0 +1,523 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_EWDG_DRV_H +#define HPM_EWDG_DRV_H + +#include "hpm_common.h" +#include "hpm_ewdg_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief EWDG driver APIs + * @defgroup ewdg_interface EWDG driver APIs + * @addtogroup ewdg_interface + * @{ + */ + + +/** + * @brief EWDG error codes + */ +enum { + status_ewdg_tick_out_of_range = MAKE_STATUS(status_group_ewdg, 0), /*!< The tick is out of range */ + status_ewdg_div_out_of_range = MAKE_STATUS(status_group_ewdg, 1), /*!< Clock Divider is out of range */ + status_ewdg_feature_unsupported = MAKE_STATUS(status_group_ewdg, 2), /*!< Feature is not supported */ +}; + +/** + * @brief EWDG Password Definitions + * + * @defgroup ewdg_password_def + * @ingroup ewdg_password_def + * @{ + */ +#define EWDG_REFRESH_UNLOCK_PASSWORD_DEFAULT (0xED09U) /*!< Default EWDG Refresh Password */ +#define EWDG_UPDATE_PASSWORD_DEFAULT (0xECF9U) /*!< Default EWDG Update Password */ +#define EWDG_REFRESH_UNLOCK_FIXED_KEY (0x55AAU) /*!< EWDG Unlock Fixed key */ +#define EWDG_REFRESH_KEY (0x5A45524FUL) /*!< EWDG Refresh key */ +/** + * @} + */ + +/** + * @brief EWDG Events + * + * @defgroup ewdg_event + * @ingroup ewdg_event + * @{ + */ +#define EWDG_EVENT_PARITY_ERROR (1UL << 6) /*!< Parity Error Event */ +#define EWDG_EVENT_TIMEOUT_RESET (1UL << 5) /*!< Timeout Reset Event */ +#define EWDG_EVENT_TIMEOUT_INTERRUPT (1UL << 4) /*!< Timeout Interrupt Event */ +#define EWDG_EVENT_CFG_REG_UPDATE_UNLOCK_FAIL (1UL << 3) /*!< Update Unlock Fail Event */ +#define EWDG_EVENT_CFG_REG_UPDATE_VIOLATION (1UL << 2) /*!< Update Violation Event */ +#define EWDG_EVENT_REFRESH_UNLOCK_FAIL (1UL << 1) /*!< Refresh Unlock Fail Event */ +#define EWDG_EVENT_REFRESH_VIOLATION (1UL << 0) /*!< Refresh Violation Event */ +/** + * @} + */ + +/** + * @brief EWDG Interrupts + * @defgroup ewdg_interrupt + * @ingroup ewdg_interrupt + * @{ + */ +#define EWDG_INT_PARITY_FAIL (1UL << 2) /*!< Parity Error Interrupt */ +#define EWDG_INT_CTRL_REG_UNLOCK_FAIL (1UL << 4) /*!< Unlock Control Register Fail Interrupt */ +#define EWDG_INT_CTRL_REG_UPDATE_FAIL (1UL << 6) /*!< Update Control Register Violation Interrupt */ +#define EWDG_INT_TIMEOUT (1UL << 16) /*!< Watchdog Timeout Interrupt */ +#define EWDG_INT_REFRESH_UNLOCK_FAIL (1UL << 20) /*!< Refresh Register Unlock Fail interrupt */ +#define EWDG_INT_REFRESH_VIOLATION (1UL << 22) /*!< Refresh Register Violation interrupt */ +/*! All Interrupt masks */ +#define EWDG_INT_ALL (EWDG_INT_PARITY_FAIL | EWDG_INT_CTRL_REG_UNLOCK_FAIL | EWDG_INT_CTRL_REG_UPDATE_FAIL | \ + EWDG_INT_TIMEOUT | EWDG_INT_REFRESH_UNLOCK_FAIL | EWDG_INT_REFRESH_VIOLATION) +/** + * @} + */ + +/** + * @brief EWDG Resets + * + * @defgroup ewdg_reset_source + * @ingroup ewdg_reset_source + * @{ + */ +#define EWDG_RST_PARITY_FAIL (1UL << 3) /*!< Parity Error Reset */ +#define EWDG_RST_CTRL_REG_UNLOCK_FAIL (1UL << 5) /*!< Unlock Control Register Fail Reset */ +#define EWDG_RST_CTRL_REG_UPDATE_FAIL (1UL << 7) /*!< Update Control Register Violation Reset */ +#define EWDG_RST_TIMEOUT (1UL << 17) /*!< Watchdog Timeout Reset */ +#define EWDG_RST_REFRESH_UNLOCK_FAIL (1UL << 21) /*!< Refresh Register Unlock Fail Reset */ +#define EWDG_RST_REFRESH_VIOLATION (1UL << 23) /*!< Refresh Register Violation Reset */ +/*! All Reset masks */ +#define EWDG_RST_ALL (EWDG_RST_PARITY_FAIL | EWDG_RST_CTRL_REG_UNLOCK_FAIL | EWDG_RST_CTRL_REG_UPDATE_FAIL | \ + EWDG_RST_TIMEOUT | EWDG_RST_REFRESH_UNLOCK_FAIL | EWDG_RST_REFRESH_VIOLATION) +/** + * @} + */ + + + +/** + * @brief EWDG Refresh Unlock Methods + */ +typedef enum { + /*! Use the Unlock Password directly */ + ewdg_refresh_unlock_method_password = 0, + /*! Use password[14:0] | password[15] */ + ewdg_refresh_unlock_method_ring_left_shift_password_by_1 = 1, + /*! Use fixed key: 0x55AA */ + ewdg_refresh_unlock_method_fixed_key = 2, + /*! Use last_password[14:0] | (last_password[15] ^ password[0]) */ + ewdg_refresh_unlock_method_ring_left_shift_password_by_1_bit0_xor_password_bit0 = 3, + /*! Max allowed range */ + ewdg_refresh_unlock_method_max = ewdg_refresh_unlock_method_ring_left_shift_password_by_1_bit0_xor_password_bit0 +} ewdg_refresh_unlock_method_t; + +/** + * @brief EWDG Clock source for internal counter + */ +typedef enum { + ewdg_cnt_clk_src_bus_clk, /*!< Clock is from BUS clock */ + ewdg_cnt_clk_src_ext_osc_clk, /*!< Clock is from External OSC */ +} ewdg_cnt_clk_sel_t; + +/** + * @brief EWDG Lower Window Limitations + */ +typedef enum { + /*! Refresh should be issued after 8/16 of timeout period */ + ewdg_window_lower_timeout_period_8_div_16 = 0, + /*! Refresh should be issued after 10/16 of timeout period */ + ewdg_window_lower_timeout_period_10_div_16 = 1, + /*! Refresh should be issued after 12/16 of timeout period */ + ewdg_window_lower_timeout_period_12_div_16 = 2, + /*! Refresh should be issued after 14/16 of timeout period */ + ewdg_window_lower_timeout_period_14_div_16 = 3, + /*! Maximum allowed limit value */ + ewdg_window_lower_timeout_period_max = ewdg_window_lower_timeout_period_14_div_16 +} ewdg_window_low_limit_t; + +/** + * @brief EWDG Upper Window Limitations + * + * The Actual Upper Window = Lower Window + Upper Window Limit + */ +typedef enum { + ewdg_window_upper_timeout_period_8_div_16 = 0, /*!< 8/16 of @ref timeout_reset_val */ + ewdg_window_upper_timeout_period_1_div_16 = 1, /*!< 1/16 of @ref timeout_reset_val */ + ewdg_window_upper_timeout_period_2_div_16 = 2, /*!< 2/16 of @ref timeout_reset_val */ + ewdg_window_upper_timeout_period_3_div_16 = 3, /*!< 3/16 of @ref timeout_reset_val */ + ewdg_window_upper_timeout_period_4_div_16 = 4, /*!< 4/16 of @ref timeout_reset_val */ + ewdg_window_upper_timeout_period_5_div_16 = 5, /*!< 5/16 of @ref timeout_reset_val */ + ewdg_window_upper_timeout_period_6_div_16 = 6, /*!< 6/16 of @ref timeout_reset_val */ + ewdg_window_upper_timeout_period_7_div_16 = 8, /*!< 7/16 of @ref timeout_reset_val */ + /*! Maximum allowed upper limit */ + ewdg_window_upper_timeout_period_max = ewdg_window_upper_timeout_period_7_div_16 +} ewdg_window_upper_limit_t; + +typedef enum { + ewdg_low_power_mode_halt = 0, /*!< Watchdog is halted in low power mode */ + ewdg_low_power_mode_work_clock_div_4 = 1, /*!< Watchdog is will work with 1/4 normal clock in low power mode */ + ewdg_low_power_mode_work_clock_div_2 = 2, /*!< Watchdog is will work with 1/2 normal clock in low power mode */ + ewdg_low_power_mode_work_clock_normal = 3, /*!< Watchdog is will work with normal clock in low power mode */ +} ewdg_low_power_mode_t; + +/*** + * @brief EWDG Function Control Configurations + */ +typedef struct { + ewdg_cnt_clk_sel_t cnt_clk_sel; /*!< Clock source for counter */ + bool enable_window_mode; /*!< Enable window mode */ + ewdg_window_low_limit_t window_lower_limit; /*!< Lower limit of the window */ + /*! Upper limit of the window + * The real upper window = (window_lower_limit/8 + window_upper_limit/16) * timeout_reset_val + */ + ewdg_window_upper_limit_t window_upper_limit; + + bool enable_config_lock; /*!< Enable Lock for the Configuration Registers */ + + bool enable_refresh_period; /*!< Enable Refresh period */ + bool enable_refresh_lock; /*!< Enable Refresh lock */ + ewdg_refresh_unlock_method_t refresh_unlock_method; /*!< Method to unlock REFRESH_REG */ + + bool enable_overtime_self_clear; /*!< Enable Over time self clear */ + + bool keep_running_in_debug_mode; /*!< Keep running even in debug mode */ + ewdg_low_power_mode_t low_power_mode; /*!< Watchdog behavior in low power mode */ + /*! + * Select timeout value type + * - true: use the IP-level value (in terms of EWDG counter ticks) + * - false: Use the user friendly timeout value (in terms of microseconds) + */ + bool use_lowlevel_timeout; + union { + struct { + uint32_t timeout_interrupt_us; /*!< Timeout value for interrupt (in terms of microseconds) */ + uint32_t timeout_reset_us; /*!< Timeout value for reset (in terms of microseconds */ + }; + struct { + uint32_t timeout_interrupt_val; /*!< Timeout value for interrupt (in terms of counter ticks) */ + /*! Timeout value for reset (in terms of counter ticks + * Note: timeout_reset_val must > timeout_interrupt_val + */ + uint32_t timeout_reset_val; + uint32_t clock_div_by_power_of_2; /*!< Power of 2 Divider */ + }; + }; + + uint16_t refresh_period_in_bus_cycles; /*!< Refresh period */ + uint16_t refresh_unlock_password; /*!< Password for unlocking write to REFRESH_REG */ + + uint16_t ctrl_reg_update_password; /*!< Update Password */ + uint16_t ctrl_reg_update_period_bus_clk_x_128; /*!< Update Period */ +} ewdg_func_ctrl_config_t; + +/** + * @brief EWDG Reset and Interrupt Configurations + */ +typedef struct { + bool enable_ctrl_parity_fail_interrupt; /*!< Enable Parity Fail Interrupt */ + bool enable_ctrl_parity_fail_reset; /*!< Enable Parity Fail Reset */ + bool enable_ctrl_unlock_fail_interrupt; /*!< Enable Control Register Unlock Fail Interrupt */ + bool enable_ctrl_unlock_fail_reset; /*!< Enable Control Register Unlock Fail Reset */ + bool enable_ctrl_update_violation_interrupt; /*!< Enable Control Register Update Violation Interrupt */ + bool enable_ctrl_update_violation_reset; /*!< Enable Control Register Update Violation Reset */ + bool enable_timeout_interrupt; /*!< Enable Timeout Interrupt */ + bool enable_timeout_reset; /*!< Enable Timeout Reset */ + bool enable_refresh_unlock_fail_interrupt; /*!< Enable Refresh Unlock Fail Interrupt */ + bool enable_refresh_unlock_fail_reset; /*!< Enable Refresh Unlock Fail Reset */ + bool enable_refresh_violation_interrupt; /*!< Enable Refresh Violation Interrupt */ + bool enable_refresh_violation_reset; /*!< Enable Refresh Violation Reset */ +} ewdg_interrupt_reset_config_t; + +/** + * @brief Enhanced Watchdog Configuration Structure + */ +typedef struct { + ewdg_interrupt_reset_config_t int_rst_config; /*!< Error Control Configuration */ + ewdg_func_ctrl_config_t ctrl_config; /*!< Function Control Configuration */ + bool enable_watchdog; /*!< Enable Watchdog */ + uint32_t cnt_src_freq; /*!< Frequency for the clock used as the counter clock source */ +} ewdg_config_t; + +/** + * @brief Check whether the Control Registers are locked + * + * @param [in] ptr EWDG base + * + * @retval true Control Registers are locked + * @retval false Control Registers are unlocked + */ +static inline bool ewdg_is_ctrl_reg_locked(EWDG_Type *ptr) +{ + return ((ptr->CTRL0 & EWDG_CTRL0_CFG_LOCK_MASK) != 0U); +} + +/** + * @brief Get the Divider for Counter Clock + * + * @param [in] ptr EWDG base + * + * @return divider value + */ +static inline uint32_t ewdg_get_count_clk_divider(EWDG_Type *ptr) +{ + return (1UL << EWDG_CTRL0_DIV_VALUE_GET(ptr->CTRL0)); +} + +/** + * @brief Check whether the Refresh register is locked + * + * @param [in] ptr EWDG base + * + * @retval true Control Registers are locked + * @retval false Control Registers are unlocked + */ +static inline bool ewdg_is_refresh_locked(EWDG_Type *ptr) +{ + return ((ptr->CTRL0 & EWDG_CTRL0_REF_LOCK_MASK) != 0U); +} + +/** + * @brief Unlock Write to Control Registers + * + * @param [in] ptr EWDG base + */ +static inline void ewdg_unlock_ctrl_regs(EWDG_Type *ptr) +{ + uint32_t ctrl_update_prot = ptr->CFG_PROT; + ptr->CFG_PROT = ctrl_update_prot; +} + +/** + * @brief Write Refresh Magic Number to EWDG Refresh register + * @param [in] ptr EWDG base + */ +static inline void ewdg_write_refresh_reg(EWDG_Type *ptr) +{ + ptr->WDT_REFRESH_REG = EWDG_REFRESH_KEY; +} + +/** + * @brief Get the Timeout Reset ticks + * @param [in] ptr EWDG base + * @return Timeout Reset ticks + */ +static inline uint32_t ewdg_get_timeout_reset_ticks(EWDG_Type *ptr) +{ + return ptr->OT_RST_VAL; +} + +#if !defined(EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT) || (EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT == 1) +/** + * @brief Get the Timeout Interrupt ticks + * @param [in] ptr EWDG base + * @return Timeout Interrupt ticks + */ +static inline uint32_t ewdg_get_timeout_interrupt_ticks(EWDG_Type *ptr) +{ + return ptr->OT_INT_VAL; +} +#endif + +/** + * @brief Clear Interrupt Status for EWDG + * + * @note The TIMEOUT_INT_EVENT cannot be cleared directly, it needs to be cleared by the refresh sequence + * + * @param [in] ptr EWDG base + * @param [in] mask Status Mask Bits, @ref ewdg_event + */ +static inline void ewdg_clear_status_flags(EWDG_Type *ptr, uint32_t mask) +{ + ptr->WDT_STATUS = mask; +} + +/** + * @brief Get the Status of EWDG + * + * @param [in] ptr EWDG base + * + * @return STATUS register value + */ +static inline uint32_t ewdg_get_status_flags(EWDG_Type *ptr) +{ + return ptr->WDT_STATUS; +} + +/** + * @brief Get the Refresh Unlock Mechanism + * @param [in] ptr EWDG base + * @return EWDG refresh unlock method + */ +static inline ewdg_refresh_unlock_method_t ewdg_get_refresh_unlock_method(EWDG_Type *ptr) +{ + return (ewdg_refresh_unlock_method_t) (EWDG_CTRL0_REF_UNLOCK_MEC_GET(ptr->CTRL0)); +} + +/** + * @brief Enable EWDG + * + * This function enables the functionality of the EWDG and start the watchdog timer + * + * @param [in] ptr EWDG base + * + * @note Once the EWDG is enabled, + * - if the software needs to update the control register, the update unlock must be + * performed first if the control register lock is enabled. + * + */ +void ewdg_enable(EWDG_Type *ptr); + + +/** + * @brief Disable EWDG + * @param [in] ptr EWDG base + */ +void ewdg_disable(EWDG_Type *ptr); + +/** + * @brief Initialize the Control function for EWDG + * + * @param [in] ptr EWDG base + * @param [in] config Control Function Configuration + * + * @retval status_invalid_argument Invalid argument was detected + * @retval status_success No error happened + */ +hpm_stat_t ewdg_init_ctrl_func(EWDG_Type *ptr, ewdg_func_ctrl_config_t *config, uint32_t cnt_src_freq); + +/** + * @brief Initialize the Error function for EWDG + * + * @param [in] ptr EWDG base + * @param [in] config Error Function Configuration + * + * @retval status_invalid_argument Invalid argument was detected + * @retval status_success No error happened + */ +hpm_stat_t ewdg_init_interrupt_reset(EWDG_Type *ptr, ewdg_interrupt_reset_config_t *config); + +/** + * @brief Get default configuration for EWDG + * @param [in] ptr EWDG base + * @param [out] config EWDG Configuration + */ +void ewdg_get_default_config(EWDG_Type *ptr, ewdg_config_t *config); + +/** + * @brief Initialize the EWDG module + * + * @param [in] ptr EWDG base + * @param [in] config EWDG configuration + * + * @retval status_invalid_argument Invalid argument was detected + * @retval status_success No error happened + */ +hpm_stat_t ewdg_init(EWDG_Type *ptr, ewdg_config_t *config); + +/** + * @brief Unlock the write to refresh register + * + * @param [in] ptr EWDG base + * + * @retval status_invalid_argument Invalid argument was detected + * @retval status_success No error happened + */ +hpm_stat_t ewdg_unlock_refresh(EWDG_Type *ptr); + +/** + * @brief Refresh EWDG + * + * @param [in] ptr EWDG base + * + * @retval status_invalid_argument Invalid argument was detected + * @retval status_success No error happened + */ +hpm_stat_t ewdg_refresh(EWDG_Type *ptr); + +/** + * @brief Get the Divided Counter Clock Frequency for EWDG + * + * @param [in] ptr EWDG base + * @param [in] src_clk_freq Source clock of the Counter clock + * + * @return divided Counter clock Frequency + */ +uint32_t ewdg_get_count_clock_freq(EWDG_Type *ptr, uint32_t src_clk_freq); + +/** + * @brief Convert the timeout in terms of microseconds to the timeout in terms of timeout ticks + * + * @param [in] src_clk_freq Clock Frequency of the counter clock source + * @param [in] timeout_us Timeout in terms of microseconds + * + * @return timeout in terms of counter clock ticks + */ +uint64_t ewdg_convert_timeout_us_to_timeout_ticks(uint32_t src_clk_freq, uint32_t timeout_us); + +/** + * @brief Convert the timeout in terms of timeout ticks to the timeout in terms of microseconds + * + * @param [in] ptr EWDG base + * @param [in] src_clk_freq Clock Frequency of the counter clock source + * @param [in] timeout_ticks Timeout in terms of ticks + * + * @return timeout in terms of counter clock ticks + */ +uint32_t ewdg_convert_timeout_ticks_to_timeout_us(EWDG_Type *ptr, uint32_t srk_clk_freq, uint32_t timeout_ticks); + +/** + * @brief Enable EWDG interrupt + * @param [in] ptr EWDG base + * @param [in] mask Interrupt Mask, valid value refer to @ref ewdg_interrupt + */ +void ewdg_enable_interrupt(EWDG_Type *ptr, uint32_t mask); + +/** + * @brief Disable EWDG interrupt + * @param [in] ptr EWDG base + * @param [in] mask Interrupt Mask, valid value refer to @ref ewdg_interrupt + */ +void ewdg_disable_interrupt(EWDG_Type *ptr, uint32_t mask); + +/** + * @brief Enable EWDG Reset + * @param [in] ptr EWDG base + * @param [in] mask Reset Mask, valid value refer to @ref ewdg_reset_source + */ +void ewdg_enable_reset(EWDG_Type *ptr, uint32_t mask); + +/** + * @brief Disable EWDG Reset + * @param [in] ptr EWDG base + * @param [in] mask Reset Mask, valid value refer to @ref ewdg_reset_source + */ +void ewdg_disable_reset(EWDG_Type *ptr, uint32_t mask); + +/** + * @brief Switch the EWDG clock source + * @param [in] ptr EWDG base + * @param [in] clk_sel Clock source selection for EWDG counter + */ +void ewdg_switch_clock_source(EWDG_Type *ptr, ewdg_cnt_clk_sel_t clk_sel); + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* HPM_EWDG_DRV_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h index 1fc1301e..52e2994f 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h @@ -10,6 +10,7 @@ #include "hpm_common.h" #include "hpm_gpio_regs.h" +#include "hpm_soc_feature.h" #ifndef PORT_PIN_COUNT #define PORT_PIN_COUNT (32U) @@ -33,6 +34,9 @@ typedef enum gpio_interrupt_trigger { gpio_interrupt_trigger_level_low, gpio_interrupt_trigger_edge_rising, gpio_interrupt_trigger_edge_falling, +#if defined(GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT) && (GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT == 1) + gpio_interrupt_trigger_edge_both, +#endif } gpio_interrupt_trigger_t; #ifdef __cplusplus @@ -53,6 +57,20 @@ static inline uint8_t gpio_read_pin(GPIO_Type *ptr, uint32_t port, uint8_t pin) return (ptr->DI[port].VALUE & (1 << pin)) >> pin; } +/** + * @brief Read target pin output state + * + * @param ptr GPIO base address + * @param port Port index + * @param pin Pin index + * + * @return Pin output state + */ +static inline uint32_t gpio_get_pin_output_status(GPIO_Type *ptr, uint32_t port, uint8_t pin) +{ + return (ptr->DO[port].VALUE & (1 << pin)) >> pin; +} + /** * @brief Toggle pin level * diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h index 8e457e3d..0d12f0c1 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h @@ -267,7 +267,7 @@ static inline bool gptmr_check_status(GPTMR_Type *ptr, uint32_t mask) */ static inline void gptmr_clear_status(GPTMR_Type *ptr, uint32_t mask) { - ptr->SR |= mask; + ptr->SR = mask; } /** diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_gwc_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_gwc_drv.h new file mode 100644 index 00000000..13df9cf1 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_gwc_drv.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GWC_DRV_H +#define HPM_GWC_DRV_H + +/** + * @brief GWC APIs + * @defgroup gwc_interface GWC driver APIs + * @ingroup gwc_interfaces + * @{ + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_gwc_regs.h" + +/** + * @brief gwc channel config + * + * @note area of channel do not overlap. in other words, eache pixel belongs to a single channel at most. + */ +typedef struct gwc_ch_config { + bool freeze; /*!< freeze the channel configuration except reference CRC32 value setting. */ + uint16_t start_col; /*!< start col is X of upper left corner. Range: 0 to 2^13-1. */ + uint16_t start_row; /*!< start row is Y of upper left corner. Range: 0 to 2^12-1. */ + uint16_t end_col; /*!< end col is X of lower right corner. Range: 0 to 2^13-1. */ + uint16_t end_row; /*!< end row is Y of lower right corner. Range: 0 to 2^12-1. */ + uint32_t ref_crc; /*!< Reference CRC32 value.*/ +} gwc_ch_config_t; + +/** + * @brief gwc clk polarity + */ +typedef enum gwc_clk_pol { + gwc_clk_pol_normal = 0, + gwc_clk_pol_invert +} gwc_clk_pol_t; + +/** + * @brief gwc config + */ +typedef struct gwc_config { + gwc_clk_pol_t clk_pol; +} gwc_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief init the gwc + * + * @param[in] cfg GWC config @ref gwc_config_t + */ +void gwc_get_default_config(gwc_config_t *cfg); + +/** + * @brief init the gwc + * + * @param[in] ptr GWC base address + * @param[in] cfg GWC config @ref gwc_config_t + * + * @note the function is called while gwc is disable only + */ +void gwc_init(GWC_Type *ptr, gwc_config_t *cfg); + +/** + * @brief enable the gwc + * + * @param[in] ptr GWC base address + */ +void gwc_enable(GWC_Type *ptr); + +/** + * @brief disable the gwc + * + * @param[in] ptr GWC base address + */ +void gwc_disable(GWC_Type *ptr); + +/** + * @brief enable interrupts + * + * @param[in] ptr GWC base address + * @param[in] mask Mask of interrupt events that would be enabled + * @ref GWC_IRQ_MASK_ERR_MASK_MASK + * @ref GWC_IRQ_MASK_FUNC_MASK_MASK + */ +static inline void gwc_enable_interrupt(GWC_Type *ptr, uint32_t mask) +{ + ptr->IRQ_MASK &= ~mask; +} + +/** + * @brief disable interrupts. + * + * @param[in] ptr GWC base address + * @param[in] mask mask of interrupt events that would be enabled. + * @ref GWC_IRQ_MASK_ERR_MASK_MASK + * @ref GWC_IRQ_MASK_FUNC_MASK_MASK + */ +static inline void gwc_disable_interrupt(GWC_Type *ptr, uint32_t mask) +{ + ptr->IRQ_MASK |= mask; +} + +/** + * @brief get gwc status flag + * + * @param[in] ptr GWC base address + * @return gwc status + */ +static inline uint32_t gwc_get_status(GWC_Type *ptr) +{ + return ptr->IRQ_STS; +} + +/** + * @brief clear gwc status flag + * + * @param[in] ptr GWC base address + * @param[in] mask logical OR'ed of GWC_IRQ_STS_XXX_STS_MASK + */ +static inline void gwc_clear_status(GWC_Type *ptr, uint32_t mask) +{ + ptr->IRQ_STS = mask; +} + +/** + * @brief disable change of interrupt masks + * + * Once this function is called, the interrupt enabled status could not be changed + * until reset. + * + * @param[in] ptr GWC base address + */ +void gwc_freeze_interrupt_control(GWC_Type *ptr); + +/** + * @brief init gwc channel + * + * @param[in] ptr GWC base address + * @param[in] ch_index channel index @ref GWC_CHANNEL_CHn + * @param[in] cfg config of gwc channel + * + * @note the function is called while gwc channel is disable only + */ +void gwc_ch_init(GWC_Type *ptr, uint8_t ch_index, gwc_ch_config_t *cfg); + +/** + * @brief enable gwc channel + * + * @param[in] ptr GWC base address + * @param[in] ch_index channel index @ref GWC_CHANNEL_CHn + */ +static inline void gwc_ch_enable(GWC_Type *ptr, uint8_t ch_index) +{ + assert(ch_index <= GWC_CHANNEL_CH15); + ptr->CHANNEL[ch_index].CFG0 |= GWC_CHANNEL_CFG0_ENABLE_MASK; +} + +/** + * @brief disable gwc channel + * + * @param[in] ptr GWC base address + * @param[in] ch_index channel index @ref GWC_CHANNEL_CHn + */ +static inline void gwc_ch_disable(GWC_Type *ptr, uint8_t ch_index) +{ + assert(ch_index <= GWC_CHANNEL_CH15); + ptr->CHANNEL[ch_index].CFG0 &= ~GWC_CHANNEL_CFG0_ENABLE_MASK; +} + +/** + * @brief get gwc channel calc crc + * + * @param[in] ptr GWC base address + * @param[in] ch_index channel index @ref GWC_CHANNEL_CHn + */ +static inline uint32_t gwc_ch_get_crc(GWC_Type *ptr, uint8_t ch_index) +{ + assert(ch_index <= GWC_CHANNEL_CH15); + return ptr->CHANNEL[ch_index].CALCRC; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_GWC_DRV_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h index a5df49df..f522ac65 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h @@ -29,7 +29,7 @@ enum { status_i2c_not_supported = MAKE_STATUS(status_group_i2c, 9), }; -/* convert data count value into CTRL[DATACNT] value map */ +/* convert data count value into register(CTRL[DATACNT] and CTRL[DATACNT_HIGH] if exist) */ /* x range from 1 to I2C_SOC_TRANSFER_COUNT_MAX */ /* 0 for I2C_SOC_TRANSFER_COUNT_MAX */ #define I2C_DATACNT_MAP(x) (((x) == I2C_SOC_TRANSFER_COUNT_MAX) ? 0 : x) @@ -158,7 +158,7 @@ static inline void i2c_clear_fifo(I2C_Type *ptr) */ static inline uint8_t i2c_get_data_count(I2C_Type *ptr) { - return I2C_CTRL_DATACNT_GET(ptr->CTRL); + return (I2C_CTRL_DATACNT_HIGH_GET(ptr->CTRL) << 8U) + I2C_CTRL_DATACNT_GET(ptr->CTRL); } /** @@ -263,7 +263,7 @@ static inline bool i2c_get_line_scl_status(I2C_Type *ptr) */ static inline void i2c_clear_status(I2C_Type *ptr, uint32_t mask) { - ptr->STATUS |= (mask & I2C_EVENT_ALL_MASK); + ptr->STATUS = mask; } /** @@ -622,6 +622,20 @@ hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address, uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt); +#if defined(I2C_SOC_SUPPORT_RESET) && (I2C_SOC_SUPPORT_RESET == 1) +/** + * @brief generate SCL clock as reset signal + * + * @param i2c_ptr [in] ptr I2C base address + * @param [in] clk_len SCL clock length + */ +static inline void i2s_gen_reset_signal(I2C_Type *ptr, uint8_t clk_len) +{ + ptr->CTRL = (ptr->CTRL & ~I2C_CTRL_RESET_LEN_MASK) | I2C_CTRL_RESET_LEN_SET(clk_len) \ + | I2C_CTRL_RESET_HOLD_SCKIN_MASK | I2C_CTRL_RESET_ON_MASK; +} +#endif + /** * @} */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h index 97895066..dfd8f1e5 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h @@ -234,6 +234,8 @@ static inline void i2s_disable_irq(I2S_Type *ptr, uint32_t mask) /** * @brief I2S enable * + * @note dropped API, please use i2s_start + * * @param [in] ptr I2S base address */ static inline void i2s_enable(I2S_Type *ptr) @@ -244,6 +246,8 @@ static inline void i2s_enable(I2S_Type *ptr) /** * @brief I2S disable * + * @note dropped API, please use i2s_stop + * * @param [in] ptr I2S base address */ static inline void i2s_disable(I2S_Type *ptr) @@ -251,6 +255,26 @@ static inline void i2s_disable(I2S_Type *ptr) ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; } +/** + * @brief I2S start + * + * @param [in] ptr I2S base address + */ +static inline void i2s_start(I2S_Type *ptr) +{ + ptr->CTRL |= I2S_CTRL_I2S_EN_MASK; +} + +/** + * @brief I2S stop + * + * @param [in] ptr I2S base address + */ +static inline void i2s_stop(I2S_Type *ptr) +{ + ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; +} + /** * @brief I2S enable rx function * @@ -295,30 +319,6 @@ static inline void i2s_disable_tx(I2S_Type *ptr, uint8_t tx_mask) ptr->CTRL &= ~I2S_CTRL_TX_EN_SET(tx_mask); } -/** - * @brief I2S clear tx fifo - * - * @param [in] ptr I2S base address - */ -static inline void i2s_clear_tx_fifo(I2S_Type *ptr) -{ - ptr->CTRL |= I2S_CTRL_TXFIFOCLR_MASK; - while (ptr->CTRL & I2S_CTRL_TXFIFOCLR_MASK) { - } -} - -/** - * @brief I2S clear rx fifo - * - * @param [in] ptr I2S base address - */ -static inline void i2s_clear_rx_fifo(I2S_Type *ptr) -{ - ptr->CTRL |= I2S_CTRL_RXFIFOCLR_MASK; - while (ptr->CTRL & I2S_CTRL_RXFIFOCLR_MASK) { - } -} - /** * @brief I2S reset clock generator * @@ -333,23 +333,52 @@ static inline void i2s_reset_clock_gen(I2S_Type *ptr) /** * @brief I2S reset tx function * + * @note This API will disable I2S, reset tx function + * * @param [in] ptr I2S base address */ static inline void i2s_reset_tx(I2S_Type *ptr) { - ptr->CTRL |= I2S_CTRL_SFTRST_TX_MASK; - ptr->CTRL &= ~I2S_CTRL_SFTRST_TX_MASK; + /* disable I2S */ + ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; + + /* reset tx and clear fifo */ + ptr->CTRL |= (I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_SFTRST_TX_MASK); + ptr->CTRL &= ~(I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_SFTRST_TX_MASK); } /** * @brief I2S reset rx function * + * @note This API will disable I2S, reset rx function + * * @param [in] ptr I2S base address */ static inline void i2s_reset_rx(I2S_Type *ptr) { - ptr->CTRL |= I2S_CTRL_SFTRST_RX_MASK; - ptr->CTRL &= ~I2S_CTRL_SFTRST_RX_MASK; + /* disable I2S */ + ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; + + /* reset rx and clear fifo */ + ptr->CTRL |= (I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_RX_MASK); + ptr->CTRL &= ~(I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_RX_MASK); +} + +/** + * @brief I2S reset tx and rx function + * + * @note This API will disable I2S, reset tx/rx function + * + * @param [in] ptr I2S base address + */ +static inline void i2s_reset_tx_rx(I2S_Type *ptr) +{ + /* disable I2S */ + ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; + + /* reset tx/rx and clear fifo */ + ptr->CTRL |= (I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); + ptr->CTRL &= ~(I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); } /** diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h index 54332343..6869a819 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h @@ -383,6 +383,31 @@ static inline void lcdc_set_background(LCDC_Type *ptr, | LCDC_BGND_CL_B_SET(color.b); } +/** + * + * @brief enable background on alpha blender + * + * @note it not depend the background color of the layer itself. it can be used with lcdc_set_background API + * + * @param[in] ptr LCD base address + */ +static inline void lcdc_enable_background_in_alpha_blender(LCDC_Type *ptr) +{ + ptr->CTRL |= LCDC_CTRL_BGDCL4CLR_MASK; +} + +/** + * + * @brief disable background on alpha blender + * + * @note if not use background but want depend the the background color of the layer itself, can be use the API + * + * @param[in] ptr LCD base address + */ +static inline void lcdc_disable_background_in_alpha_blender(LCDC_Type *ptr) +{ + ptr->CTRL &= ~LCDC_CTRL_BGDCL4CLR_MASK; +} /** * * @brief Get default layer configuration value diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_linv2_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_linv2_drv.h new file mode 100644 index 00000000..bb26fd74 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_linv2_drv.h @@ -0,0 +1,376 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_LINV2_DRV_H +#define HPM_LINV2_DRV_H + +#include +#include "hpm_common.h" +#include "hpm_linv2_regs.h" +#include "hpm_soc_feature.h" + +/** bit4 and bit5 encode data length in ID */ +#define LIN_ID_DATA_LEN_SHIFT 4U +#define LIN_ID_DATA_LEN_MASK 0x30U +#define LIN_ID_DATA_LEN_GET(x) (((uint8_t)(x) & LIN_ID_DATA_LEN_MASK) >> LIN_ID_DATA_LEN_SHIFT) + +/** + * @brief LINV2 driver APIs + * @defgroup linv2_interface LINV2 driver APIs + * @ingroup linv2_interface + * @{ + */ + +/** + * @brief data length in ID bit4 and bit5 + */ +typedef enum { + id_data_length_2bytes, + id_data_length_2bytes_2, /**< both 0 and 1 represent 2 bytes */ + id_data_length_4bytes, + id_data_length_8bytes +} lin_id_data_length_t; + +/** + * @brief bus inactivity tome to go to sleep + */ +typedef enum { + bus_inactivity_time_4s, + bus_inactivity_time_6s, + bus_inactivity_time_8s, + bus_inactivity_time_10s +} lin_bus_inactivity_time_t; + +/** + * @brief wakeup repeat time + */ +typedef enum { + wakeup_repeat_time_180ms, + wakeup_repeat_time_200ms, + wakeup_repeat_time_220ms, + wakeup_repeat_time_240ms +} lin_wakeup_repeat_time_t; + +typedef struct { + uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */ + uint32_t baudrate; /**< Baudrate */ +} lin_timing_t; + +/** + * @brief LIN config + */ +typedef struct { + uint8_t id; /**< ID */ + uint8_t *data_buff; /**< data buff */ + bool data_length_from_id; /**< data length should be decoded from the identifier or not, dma mode not use this config */ + uint8_t data_length; /**< used when data_length_from_id is false or dma mode */ + bool enhanced_checksum; /**< true for enhanced checksum; false for classic checksum */ + bool transmit; /**< true for transmit operation; false for receive operation */ + /* bool start; */ /**< true for start operation; false for only configuration */ +} lin_trans_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief lin get control and status register value + * + * @param [in] ptr lin base address + * @return uint32_t control and status register value + */ +static inline uint32_t lin_get_control_and_status(LINV2_Type *ptr) +{ + return ptr->CONTROL_STATUS; +} + +/** + * @brief lin reset interrupt + * + * @param ptr lin base address + */ +static inline void lin_reset_interrupt(LINV2_Type *ptr) +{ + ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_RESET_INT_MASK; +} + +/** + * @brief lin reset error + * + * @param ptr lin base address + */ +static inline void lin_reset_error(LINV2_Type *ptr) +{ + ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_RESET_ERROR_MASK; +} + +/** + * @brief lin wakeup + * + * @param ptr lin base address + */ +static inline void lin_wakeup(LINV2_Type *ptr) +{ + ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK; +} + +/** + * @brief lin sleep + * + * @param ptr lin base address + */ +static inline void lin_sleep(LINV2_Type *ptr) +{ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_SLEEP_MASK; +} + +/** + * @brief lin slave stop + * + * @param ptr lin base address + */ +static inline void lin_slave_stop(LINV2_Type *ptr) +{ + ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_STOP_MASK; +} + +/** + * @brief lin slave ack + * + * @param ptr lin base address + */ +static inline void lin_slave_ack(LINV2_Type *ptr) +{ + ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_DATA_ACK_MASK; +} + +/** + * @brief lin slave set bus inactivity time + * + * @param ptr lin base address + * @param time lin_bus_inactivity_time_t + */ +static inline void lin_slave_set_bus_inactivity_time(LINV2_Type *ptr, lin_bus_inactivity_time_t time) +{ + ptr->TIMING_CONTROL = (ptr->TIMING_CONTROL & (~LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK)) + | LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SET(time); +} + +/** + * @brief lin slave set wakeup repeat time + * + * @param ptr lin base address + * @param time lin_wakeup_repeat_time_t + */ +static inline void lin_slave_set_wakeup_repeat_time(LINV2_Type *ptr, lin_wakeup_repeat_time_t time) +{ + ptr->TIMING_CONTROL = (ptr->TIMING_CONTROL & (~LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK)) + | LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SET(time); +} + +/** + * @brief lin set mode + * + * @param ptr lin base address + * @param master true for master mode, false for slave mode + */ +static inline void lin_set_mode(LINV2_Type *ptr, bool master) +{ + if (master) { + ptr->TIMING_CONTROL |= LINV2_TIMING_CONTROL_MASTER_MODE_MASK; + } else { + ptr->TIMING_CONTROL &= ~LINV2_TIMING_CONTROL_MASTER_MODE_MASK; + } +} + +/** + * @brief lin set checksum mode + * + * @param ptr lin base address + * @param enhance_check true for enhance checksum mode, false for normal checksum mode + */ +static inline void lin_set_checksum_mode(LINV2_Type *ptr, bool enhance_checksum) +{ + if (enhance_checksum) { + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_MASK; + } else { + ptr->DATA_LEN_ID &= ~LINV2_DATA_LEN_ID_ENH_CHECK_MASK; + } +} + +/** + * @brief lin get data value in byte + * + * @param ptr lin base address + * @param index byte index + * @return uint8_t byte value + */ +static inline uint8_t lin_get_data_byte(LINV2_Type *ptr, uint8_t index) +{ + return ptr->DATA_BYTE[index]; +} + +/** + * @brief lin write data value in byte + * + * @param ptr lin base address + * @param index byte index + * @param data byte value + */ +static inline void lin_write_data_byte(LINV2_Type *ptr, uint8_t index, uint8_t data) +{ + ptr->DATA_BYTE[index] = data; +} + +/** + * @brief lin get ID + * + * @param ptr lin base address + * @return uint8_t ID value + */ +static inline uint8_t lin_get_id(LINV2_Type *ptr) +{ + return (uint8_t)LINV2_DATA_LEN_ID_ID_GET(ptr->DATA_LEN_ID); +} + +/** + * @brief lin get checksum value + * + * @param ptr lin base address + * @return uint8_t checksum value + */ +static inline uint8_t lin_get_checksum(LINV2_Type *ptr) +{ + return (uint8_t)LINV2_DATA_LEN_ID_CHECKSUM_GET(ptr->DATA_LEN_ID); +} + +/** + * @brief lin active status + * + * @param ptr lin base address + * @return bool true for active, false for inactive + */ +static inline uint8_t lin_is_active(LINV2_Type *ptr) +{ + return ((ptr->CONTROL_STATUS & LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK) == LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK) ? true : false; +} + +/** + * @brief lin complete status + * + * @param ptr lin base address + * @return bool true for complete, false for incomplete + */ +static inline uint8_t lin_is_complete(LINV2_Type *ptr) +{ + return ((ptr->CONTROL_STATUS & LINV2_CONTROL_STATUS_COMPLETE_MASK) == LINV2_CONTROL_STATUS_COMPLETE_MASK) ? true : false; +} + +/** + * @brief lin configure timing on master mode + * + * @param ptr lin base address + * @param timing lin_timing_t + * @return hpm_stat_t + */ +hpm_stat_t lin_master_configure_timing(LINV2_Type *ptr, lin_timing_t *timing); + +/** + * @brief lin config timing on slave mode + * + * @param ptr lin base address + * @param src_freq_in_hz source frequency + * @return hpm_stat_t + */ +hpm_stat_t lin_slave_configure_timing(LINV2_Type *ptr, uint32_t src_freq_in_hz); + +/** + * @brief lin transfer on master mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + */ +void lin_master_transfer(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin transfer on slave mode + * + * @note call this function after lin generate data request interrupt + * + * @param ptr lin base address + * @param config lin_trans_config_t + */ +void lin_slave_transfer(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @brief get data length + * + * @note data length is determined by DATA_LEN register and ID + * + * @param ptr lin base address + * @return uint8_t data length + */ +uint8_t lin_get_data_length(LINV2_Type *ptr); + +/** + * @brief lin send data on master mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_master_sent(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin receive data on master mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_master_receive(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin send data on slave mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_slave_sent(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin receive data on slave mode + * + * @param ptr lin base address + * @param config lin_trans_config_t + * @return status_timeout + * @return status_success + */ +hpm_stat_t lin_slave_receive(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @brief lin slave dma transfer + * + * @param ptr lin base address + * @param config lin_trans_config_t + */ +void lin_slave_dma_transfer(LINV2_Type *ptr, lin_trans_config_t *config); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_LINV2_DRV_H */ + diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h index 46f43b03..3201d4fb 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h @@ -104,6 +104,30 @@ enum { */ #define MCAN_RX_RETRY_COUNT_MAX (80000000UL) +/** + * @brief MCAN Last Error Code + */ +typedef enum mcan_last_error_code { + mcan_last_error_code_no_error = 0, /*!< No error happened */ + mcan_last_error_code_stuff_error, /*!< Stuff Error */ + mcan_last_error_code_format_error, /*!< Format Error */ + mcan_last_error_code_ack_error, /*!< Acknowledge Error */ + mcan_last_error_code_bit1_error, /*!< Sent logic 1 but monitored value is logic 0 */ + mcan_last_error_code_bit0_error, /*!< Sent logic 0 but monitored value is logic 1 */ + mcan_last_error_code_crc_error, /*!< CRC checksum for received message is wrong */ + mcan_last_error_code_no_change, /*!< Error code was not changed */ +} mcan_last_err_code_t; + +/** + * @brief MCAN Communication State + */ +typedef enum mcan_activity_enum { + mcan_activity_sync = 0, /*!< Node is synchronizing on CAN communication */ + mcan_activity_idle, /*!< Node is neither receiver nor transmitter */ + mcan_activity_receiver, /*!< Node is operating as receiver */ + mcan_activity_transmitter, /*!< Node is operating as transmitter */ +} mcan_activity_state_t; + /*********************************************************************************************************************** * @brief Default CAN RAM definitions **********************************************************************************************************************/ @@ -385,7 +409,7 @@ typedef union { /** * @brief MCAN RAM Flexible Configuration * - * @Note This Configration provides the full MCAN RAM configuration, this configuration is recommended only for + * @Note This Configuration provides the full MCAN RAM configuration, this configuration is recommended only for * experienced developers who is skilled at the MCAN IP */ typedef struct mcan_ram_flexible_config_struct { @@ -513,7 +537,7 @@ typedef struct mcan_std_id_filter_elem_struct { }; /* This definition takes effect if the filter configuration is "store into RX Buffer or as debug message" * - * In this definition, only the extact ID matching mode is activated + * In this definition, only the exact ID matching mode is activated */ struct { uint32_t match_id; /*!< Matching ID */ @@ -578,7 +602,8 @@ typedef struct mcan_tsu_config_struct { uint16_t prescaler; /*!< Prescaler for MCAN clock, Clock source: AHB clock */ bool capture_on_sof; /*!< Capture On SOF, true - Capture on SOF, false - Capture on EOF */ bool use_ext_timebase; /*!< Use External Timebase */ - uint16_t ext_timebase_src; /*!< External Timebase source, see the hpm_mcan_soc.h for more details */ + uint8_t ext_timebase_src; /*!< External Timebase source, see the hpm_mcan_soc.h for more details */ + uint8_t tbsel_option; /*!< Timebase selection option, see the hpm_mcan_soc.h for more details */ bool enable_tsu; /*!< Enable Timestamp Unit */ bool enable_64bit_timestamp; /*!< Enable 64bit Timestamp */ } mcan_tsu_config_t; @@ -630,10 +655,17 @@ typedef struct mcan_config_struct { bool use_timestamping_unit; /*!< Use external Timestamp Unit */ bool enable_canfd; /*!< Enable CANFD mode */ bool enable_tdc; /*!< Enable transmitter delay compensation */ + bool enable_restricted_operation_mode; /*!< Enable Resricted Operation Mode: Receive only */ + bool disable_auto_retransmission; /*!< Disable auto retransmission */ + uint8_t padding[2]; mcan_internal_timestamp_config_t timestamp_cfg; /*!< Internal Timestamp Configuration */ mcan_tsu_config_t tsu_config; /*!< TSU configuration */ mcan_ram_config_t ram_config; /*!< MCAN RAM configuration */ mcan_all_filters_config_t all_filters_config; /*!< All Filter configuration */ + + uint32_t interrupt_mask; /*!< Interrupt Enable mask */ + uint32_t txbuf_trans_interrupt_mask; /*!< Tx Buffer Transmission Interrupt Enable mask */ + uint32_t txbuf_cancel_finish_interrupt_mask; /*!< TX Buffer Cancellation Finished Interrupt Enable Mask */ } mcan_config_t; /** @@ -663,6 +695,22 @@ typedef struct mcan_error_count_struct { uint8_t can_error_logging_count; /*!< CAN Error Logging count */ } mcan_error_count_t; +/** + * @brief MCAN Protocol Status + */ +typedef struct mcan_protocol_status { + uint8_t tdc_val; /*!< Transmitter Delay Compensation Value */ + mcan_activity_state_t activity; /*!< Current communication state */ + mcan_last_err_code_t last_error_code; /*!< Last Error code */ + bool protocol_exception_evt_occurred; /*!< Protocol Exception Event occurred */ + bool canfd_msg_received; /*!< CANFD message was received */ + bool brs_flag_set_in_last_rcv_canfd_msg; /*!< Bitrate Switch bit is set in last received CANFD message */ + bool esi_flag_set_in_last_rcv_canfd_msg; /*!< Error State Indicator bit is set in last received CANFD message */ + bool in_bus_off_state; /*!< Node is in bus-off state */ + bool in_warning_state; /*!< Node is in warning state */ + bool in_error_passive_state; /*!< Node is in error passive state */ +} mcan_protocol_status_t; + /** * @brief MCAN Transmitter Delay Compensation Configuration */ @@ -839,48 +887,62 @@ static inline void mcan_disable_auto_retransmission(MCAN_Type *ptr) } /** - * @brief Disable Bus monitoring Mode + * @brief Enable Bus monitoring Mode * @param [in] ptr MCAN base */ -static inline void mcan_disable_bus_monitoring_mode(MCAN_Type *ptr) +static inline void mcan_enable_bus_monitoring_mode(MCAN_Type *ptr) { - ptr->CCCR &= ~MCAN_CCCR_MON_MASK; + ptr->CCCR |= MCAN_CCCR_MON_MASK; } /** - * @brief Enable Clock Stop Request + * @brief Stop MCAN clock * @param [in] ptr MCAN base */ -static inline void mcan_enable_clock_stop_request(MCAN_Type *ptr) +static inline void mcan_stop_clock(MCAN_Type *ptr) { ptr->CCCR |= MCAN_CCCR_CSR_MASK; } /** - * @brief Disable Clock Stop Request + * @brief Enable MCAN clock * @param [in] ptr MCAN base */ -static inline void mcan_disable_clock_stop_request(MCAN_Type *ptr) +static inline void mcan_enable_clock(MCAN_Type *ptr) { ptr->CCCR &= ~MCAN_CCCR_CSR_MASK; } +static inline bool mcan_is_clock_enabled(MCAN_Type *ptr) +{ + return ((ptr->CCCR & MCAN_CCCR_CSR_MASK) == 0UL); +} + /** - * @brief Enable Clock Stop Acknowledge + * @brief Disable Bus monitoring Mode * @param [in] ptr MCAN base */ -static inline void mcan_enable_clock_stop_acknowledge(MCAN_Type *ptr) +static inline void mcan_disable_bus_monitoring_mode(MCAN_Type *ptr) { - ptr->CCCR |= MCAN_CCCR_CSA_MASK; + ptr->CCCR &= ~MCAN_CCCR_MON_MASK; } /** - * @brief Disable Clock Stop Acknowledge + * @brief Check whether CAN clock is stopped or not * @param [in] ptr MCAN base */ -static inline void mcan_disable_clock_stop_acknowledge(MCAN_Type *ptr) +static inline bool mcan_is_clock_stopped(MCAN_Type *ptr) { - ptr->CCCR &= ~MCAN_CCCR_CSA_MASK; + return ((ptr->CCCR & MCAN_CCCR_CSA_MASK) != 0U); +} + +/** + * @brief Enable Restricted Operation Mode + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_restricted_operation_mode(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_ASM_MASK; } /** @@ -892,6 +954,24 @@ static inline void mcan_disable_restricted_operation_mode(MCAN_Type *ptr) ptr->CCCR &= ~MCAN_CCCR_ASM_MASK; } +/** + * @brief Enable Write Access to Protected Configuration Registers + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_write_to_prot_config_registers(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_CCE_MASK; +} + +/** + * @brief Disalbe Write Access to Protected Configuration Registers + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_write_to_prot_config_registers(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_CCE_MASK; +} + /** * @brief Get Timestamp Counter Value * @param [in] ptr MCAN base @@ -902,6 +982,24 @@ static inline uint16_t mcan_get_timestamp_counter_value(MCAN_Type *ptr) return ptr->TSCV; } +/** + * @brief Switch MCAN to Initialization mode + * @param [in] ptr MCAN base + */ +static inline void mcan_enter_init_mode(MCAN_Type *ptr) +{ + ptr->CCCR |= MCAN_CCCR_INIT_MASK; +} + +/** + * @brief Switch MCAN to Normal mode + * @param [in] ptr MCAN base + */ +static inline void mcan_enter_normal_mode(MCAN_Type *ptr) +{ + ptr->CCCR &= ~MCAN_CCCR_INIT_MASK; +} + /** * @brief Get Timeout value * @param [in] ptr MCAN base @@ -989,6 +1087,7 @@ static inline bool mcan_is_in_busoff_state(MCAN_Type *ptr) /** * @brief Get the Last Data Phase Error * @param [in] ptr MCAN base + * @deprecated This API will be removed in later SDK release * @return The last Data Phase Error */ static inline uint8_t mcan_get_data_phase_last_error_code(MCAN_Type *ptr) @@ -1080,6 +1179,7 @@ static inline void mcan_enable_interrupts(MCAN_Type *ptr, uint32_t mask) /** * @brief Enable TXBUF Interrupt + * @deprecated This API is deprecated, will be removed in later SDK release * @param [in] ptr MCAN base * @param [in] mask Interrupt mask */ @@ -1090,6 +1190,7 @@ static inline void mcan_enable_txbuf_interrupt(MCAN_Type *ptr, uint32_t mask) /** * @brief Disable TXBUF Interrupt + * @deprecated This API is deprecated, will be removed in later SDK release * @param [in] ptr MCAN base * @param [in] mask Interrupt mask */ @@ -1262,6 +1363,14 @@ static inline bool mcan_is_interrupt_flag_set(MCAN_Type *ptr, uint32_t mask) return ((ptr->IR & mask) != 0U); } +/** + * @brief Check whether the TSU timestamp is available + * + * @param [in] ptr MCAN base + * @param [in] index Timestamp pointer + * @retval true TSU Timestamp is available + * @retval false TSU timestamp is unavailable + */ static inline bool mcan_is_tsu_timestamp_available(MCAN_Type *ptr, uint32_t index) { bool is_available = false; @@ -1308,6 +1417,12 @@ void mcan_get_default_config(MCAN_Type *ptr, mcan_config_t *config); */ uint8_t mcan_get_message_size_from_dlc(uint8_t dlc); +/** + * @brief Get the Data field size from data field size option + * + * @param [in] data_field_size_option Data size option + * @return data field size in bytes + */ uint8_t mcan_get_data_field_size(uint8_t data_field_size_option); /** @@ -1410,6 +1525,13 @@ void mcan_get_default_ram_config(MCAN_Type *ptr, mcan_ram_config_t *simple_confi */ hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_freq); +/** + * @brief De-Initialize CAN controller + * + * @param [in] ptr MCAN base + */ +void mcan_deinit(MCAN_Type *ptr); + /** * @brief Configure MCAN RAM will Full RAM configuration * @param [in] ptr MCAN base @@ -1513,9 +1635,20 @@ hpm_stat_t mcan_read_tx_evt_fifo(MCAN_Type *ptr, mcan_tx_event_fifo_elem_t *tx_e hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame); /** - * @brief Transmit CAN message via TX in blocking way + * @brief Transmit CAN message via TX FIFO in non-blocking way * @param [in] ptr MCAN base * @param [in] tx_frame CAN Transmit Message buffer + * @param [out] fifo_index The index of the element in FIFO assigned to the tx_frame + * + * @return status_success if no errors reported + */ +hpm_stat_t mcan_transmit_via_txfifo_nonblocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame, uint32_t *fifo_index); + +/** + * @brief Transmit CAN message via TX in non-blocking way + * @param [in] ptr MCAN base + * @param [in] index Index of TX Buffer + * @param [in] tx_frame CAN Transmit Message buffer * @return status_success if no errors reported */ hpm_stat_t mcan_transmit_via_txbuf_nonblocking(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame); @@ -1564,6 +1697,26 @@ hpm_stat_t mcan_get_timestamp_from_received_message(MCAN_Type *ptr, const mcan_rx_message_t *rx_msg, mcan_timestamp_value_t *timestamp); +/** + * @brief Parse the Protocol Status register value + * @param [in] psr Protocol Status Register Value + * @param [out] protocol_status Translated Protocol Status + * + * @retval status_invalid_argument if any parameters are invalid + * @retval status_success if no errors happened + */ +hpm_stat_t mcan_parse_protocol_status(uint32_t psr, mcan_protocol_status_t *protocol_status); + +/** + * @brief Get MCAN Protocol Status + * @param [in] ptr MCAN base + * @param [out] protocol_status Translated Protocol status + * + * @retval status_invalid_argument if any parameters are invalid + * @retval status_success if no errors happened + */ +hpm_stat_t mcan_get_protocol_status(MCAN_Type *ptr, mcan_protocol_status_t *protocol_status); + /** * @} * diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_mmc_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_mmc_drv.h new file mode 100644 index 00000000..a7417b79 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_mmc_drv.h @@ -0,0 +1,610 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MMC_DRV_H +#define HPM_MMC_DRV_H + +#include "hpm_common.h" +#include "hpm_mmc_regs.h" +/** + * @brief MMC driver APIs + * @defgroup mmc_interface MMC driver APIs + * @ingroup mmc_interface + * @{ + */ + +/* trigger source to update position parameter */ +typedef enum { + mmc_pos_update_by_timestamp = 0, + mmc_pos_update_by_intrgr0_rise_edge = 1, + mmc_pos_update_by_intrgr1_rise_edge = 2, + mmc_pos_update_by_outtrgr0_rise_edge = 3, + mmc_pos_update_by_outtrgr1_rise_edge = 4, + mmc_pos_update_by_self_pos_thr = 5, + mmc_pos_update_by_self_speed_thr = 6, +} mmc_pos_update_trigger_t; + + +/* cmd mask to update position parameter */ +typedef enum { + mmc_pos_update_none = 0, + mmc_pos_update_position = 1 << 0, + mmc_pos_update_revolution = 1 << 1, + mmc_pos_update_speed = 1 << 2, + mmc_pos_update_accel = 1 << 3, + mmc_pos_update_all = 0b1111, +} mmc_pos_update_cmd_mask_t; + +typedef enum { + mmc_coef_not_update = 0, + mmc_coef_p_update = 1 << 0, + mmc_coef_i_update = 1 << 1, + mmc_coef_a_update = 1 << 2, + mmc_coef_update_all = 0b111, +} mmc_coef_update_cmd_mask_t; + +typedef struct { + bool discrete_pos_mode; + uint32_t discrete_line; + uint32_t continuous_step_thr; + uint32_t continuous_circ_thr; + uint32_t oosync_theta_thr; +} mmc_track_pos_mode_t; + +typedef struct { + bool force_accel_to_zero; + bool en_ms_coef; + bool open_loop_mode; + bool pos_16bit_type; /* true for output 16bit position, false for output 32bit position */ + bool sync_new_pos; /* predictor base new track position data */ + mmc_track_pos_mode_t pos_mode; +} mmc_track_mode_t; + +typedef struct { + uint32_t pos_time; + uint32_t position; + int32_t revolution; + double speed; + double accel; + uint32_t cmd_mask; /*!< cmd to to select which parameters to update */ + uint32_t trigger; /*!< trigger source for when to update parameters */ +} mmc_pos_or_delta_pos_input_t; + +typedef struct { + uint32_t coef_time; + double coef_p; + double coef_i; + double coef_a; + uint32_t cmd_mask; /* cmd to select change which parameter */ +} mmc_coef_input_t; + +typedef struct { + uint32_t err_thr; + uint32_t hold_time; + double coef_p; + double coef_i; + double coef_a; +} mmc_coef_trig_config_t; + +typedef struct { + uint32_t time; + uint32_t position; + int32_t revolution; + double speed; + double accel; +} mmc_pos_out_t; + +typedef struct { + double coef_p; + double coef_i; + double coef_a; +} mmc_coef_out_t; + +/* track event, definition align with interrupt mask and status mask */ +typedef enum { + mmc_track_shadow_read_done = 1 << 0, + mmc_track_init_coefs_done = 1 << 1, + mmc_track_init_pos_done = 1 << 2, + mmc_track_oosync = 1 << 4, + mmc_track_idle = 1 << 5, /*!< no corresponding interrupt */ + mmc_pred1_init_pos_done = 1 << 6, + mmc_pred0_init_pos_done = 1 << 7, + mmc_track_init_delta_pos_done = 1 << 8, + mmc_track_pos_trig_valid = 1 << 9, + mmc_track_speed_trig_valid = 1 << 10, +} mmc_track_event_t; + +typedef enum { + mmc_pred_idle = MMC_BR_BR_ST_IDLE_MASK, + mmc_pred_init_delta_pos_done = MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK, + mmc_pred_pos_trig_valid = MMC_BR_BR_ST_POS_TRG_VLD_MASK, + mmc_pred_speed_trig_valid = MMC_BR_BR_ST_SPEED_TRG_VLD_MASK, + mmc_pred_open_loop = MMC_BR_BR_ST_OPEN_LOOP_ST_MASK, +} mmc_pred_event_t; + +typedef enum { + mmc_pred_pos_trig_valid_int = MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK, + mmc_pred_speed_trig_valid_int = MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK, + mmc_pred_init_delta_pos_done_int = MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK +} mmc_pred_int_t; + +typedef struct { + bool speed_trig_int; + bool position_trig_int; + bool delta_pos_done_trig_int; + bool open_loop_mode; + uint8_t pred_mode; + uint8_t not_first_pred_trig_type; + uint8_t first_pred_trig_type; +} mmc_pred_mode_t; + +typedef enum { + mmc_pred_not_reload_pos_cmd = 0, + mmc_pred_0_reload_pos_cmd = 2, + mmc_pred_1_reload_pos_cmd = 1, + mmc_pred_both_reload_pos_cmd = 3, +} mmc_pred_reload_pos_cmd_t; + +typedef enum { + mmc_pred_by_period = 0, + mmc_pred_continuously_repeat = 1, + mmc_pred_only_once = 2, +} mmc_pred_time_t; + +/* using for mmc_pred_by_period mode */ +typedef struct { + uint32_t offset_time; + uint32_t period_time; + uint32_t first_time; +} mmc_pred_period_time_t; + +typedef struct { + bool less_than; /*!< true for less than, false for greater than */ + bool enable; + uint32_t position_thr; /*!< position in a cycle */ + int32_t revolution_thr; /*!< cycle */ +} mmc_pos_trig_t; + +typedef struct { + bool absolute_compare; /*!< true for absolute value compare, false for signed value compare */ + bool less_than; /*!< true for less than, false for greater than */ + bool enable; + int32_t speed_thr; +} mmc_speed_trig_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief MMC set frequency + * @param [in] base MMC base address + * @param [in] freq the moto system freq + */ +static inline void mmc_set_sysclk_freq(MMC_Type *base, uint32_t freq) +{ + uint32_t period; + base->SYSCLK_FREQ = freq; + /* 1/freq *(2^24)*(2^20) */ + period = (uint32_t)((double)(1 << 20) * (1 << 24) / freq); + base->SYSCLK_PERIOD = period; +} + +/** + * @brief MMC software reset + * @param [in] base MMC base address + */ +static inline void mmc_software_reset(MMC_Type *base) +{ + base->CR |= MMC_CR_SFTRST_MASK; + base->CR &= ~MMC_CR_SFTRST_MASK; +} + +/** + * @brief MMC module enable + * @param [in] base MMC base address + */ +static inline void mmc_enable_module(MMC_Type *base) +{ + base->CR |= MMC_CR_MOD_EN_MASK; +} + +/** + * @brief MMC module disable + * @param [in] base MMC base address + */ +static inline void mmc_disable_module(MMC_Type *base) +{ + base->CR &= ~MMC_CR_MOD_EN_MASK; +} + +/** + * @brief MMC track set loop mode + * @param [in] base MMC base address + * @param [in] open_loop true for open loop, false for close loop + */ +static inline void mmc_track_set_open_loop_mode(MMC_Type *base, bool open_loop) +{ + if (open_loop) { + base->CR |= MMC_CR_OPEN_LOOP_MODE_MASK; + } else { + base->CR &= ~MMC_CR_OPEN_LOOP_MODE_MASK; + } +} + +/** + * @brief MMC track set adjop mode + * @param [in] base MMC base address + * @param [in] adjop true for adjop mode, false for normal mode + */ +static inline void mmc_track_set_adjop_mode(MMC_Type *base, bool adjop) +{ + if (adjop) { + base->CR |= MMC_CR_ADJOP_MASK; + } else { + base->CR &= ~MMC_CR_ADJOP_MASK; + } +} + +/** + * @brief MMC track request shadow read + * @param [in] base MMC base address + * + * @note request shadow before read mmc track resoult register + */ +static inline void mmc_track_enable_shadow_read(MMC_Type *base) +{ + base->CR |= MMC_CR_SHADOW_RD_REQ_MASK; + /* SHADOW_RD_REQ clear indicates that the shadow is complete */ + while ((base->CR & MMC_CR_SHADOW_RD_REQ_MASK) == MMC_CR_SHADOW_RD_REQ_MASK) { + } +} + +/** + * @brief MMC track enable interrupt + * @param [in] base MMC base address + * @param [in] int_mask interrupt_mask @ref mmc_track_event_t + */ +static inline void mmc_track_enable_interrupt(MMC_Type *base, uint32_t int_mask) +{ + base->INT_EN = int_mask; +} + +/** + * @brief MMC track disable interrupt + * @param [in] base MMC base address + * @param [in] int_mask interrupt_mask @ref mmc_track_event_t + */ +static inline void mmc_track_disable_interrupt(MMC_Type *base, uint32_t int_mask) +{ + base->INT_EN &= ~int_mask; +} + +/** + * @brief MMC track get status register value + * @param [in] base MMC base address + * @retval status register value + */ +static inline uint32_t mmc_track_get_status(MMC_Type *base) +{ + return base->STA; +} + +/** + * @brief MMC track clear status flag in status register + * @param [in] base MMC base address + * @param [in] clr_mask @ref mmc_track_event_t + */ +static inline void mmc_track_clear_status(MMC_Type *base, uint32_t clr_mask) +{ + base->STA = clr_mask; /* W1C */ +} + +/** + * @brief MMC track set the threshold of theta for out-of-sync + * @param [in] base MMC base address + * @param [in] threshold threshold value + */ +static inline void mmc_track_set_oosync_theta_threshold(MMC_Type *base, uint32_t threshold) +{ + base->OOSYNC_THETA_THR = MMC_OOSYNC_THETA_THR_VAL_SET(threshold); +} + +/** + * @brief MMC track config position mode + * @param [in] base MMC base address + * @param [in] mode mmc_track_pos_mode_t + */ +void mmc_track_config_pos_mode(MMC_Type *base, mmc_track_pos_mode_t *mode); + +/** + * @brief MMC track get default mode config + * @param [in] base MMC base address + * @param [in] config mmc_track_mode_t + */ +void mmc_track_get_default_mode_config(MMC_Type *base, mmc_track_mode_t *config); + +/** + * @brief MMC track config mode + * @param [in] base MMC base address + * @param [in] config mmc_track_mode_t + */ +void mmc_track_config_mode(MMC_Type *base, mmc_track_mode_t *config); + +/** + * @brief MMC track config position parameter + * @param [in] base MMC base address + * @param [in] para mmc_pos_or_delta_pos_input_t + */ +void mmc_track_config_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para); + +/** + * @brief MMC track config delta parameter + * @param [in] base MMC base address + * @param [in] para mmc_pos_or_delta_pos_input_t + */ +void mmc_track_config_delta_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para); + +/** + * @brief MMC track config coef parameter + * @param [in] base MMC base address + * @param [in] para mmc_coef_input_t + */ +void mmc_track_config_coef_para(MMC_Type *base, mmc_coef_input_t *para); + +/** + * @brief MMC track config position trigger + * @param [in] base MMC base address + * @param [in] para mmc_pos_trig_t + */ +void mmc_track_config_position_trig(MMC_Type *base, mmc_pos_trig_t *trig); + +/** + * @brief MMC track config speed trigger + * @param [in] base MMC base address + * @param [in] para mmc_speed_trig_t + */ +void mmc_track_config_speed_trig(MMC_Type *base, mmc_speed_trig_t *trig); + +/** + * @brief MMC track disable position trigger + * @param [in] base MMC base address + */ +static inline void mmc_track_disable_position_trig(MMC_Type *base) +{ + base->POS_TRG_CFG &= ~MMC_POS_TRG_CFG_EN_MASK; +} + +/** + * @brief MMC track disable speed trigger + * @param [in] base MMC base address + */ +static inline void mmc_track_disable_speed_trig(MMC_Type *base) +{ + base->SPEED_TRG_CFG &= ~MMC_SPEED_TRG_CFG_EN_MASK; +} + +/** + * @brief MMC track config multiple coef trigger + * @param [in] base MMC base address + * @param [in] config mmc_coef_trig_config_t + */ +void mmc_track_config_coef_trig(MMC_Type *base, uint8_t index, mmc_coef_trig_config_t *config); + +/** + * @brief MMC track get result + * @param [in] base MMC base address + * @param [out] pos_out mmc_pos_out_t + * @param [out] coef_out mmc_coef_out_t + */ +void mmc_track_get_result(MMC_Type *base, mmc_pos_out_t *pos_out, mmc_coef_out_t *coef_out); + +/* predictor */ +/** + * @brief MMC enable predictor + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + */ +static inline void mmc_enable_pred(MMC_Type *base, uint8_t index) +{ + base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_BR_EN_MASK; +} + +/** + * @brief MMC disable predictor + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + */ +static inline void mmc_disable_pred(MMC_Type *base, uint8_t index) +{ + base->BR[index].BR_CTRL &= ~MMC_BR_BR_CTRL_BR_EN_MASK; +} + +/** + * @brief MMC predictor set loop mode + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] open_loop true for open loop, false for close loop + */ +static inline void mmc_pred_set_open_loop_mode(MMC_Type *base, uint8_t index, bool open_loop) +{ + if (open_loop) { + base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK; + } else { + base->BR[index].BR_CTRL &= ~MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK; + } +} + +/** + * @brief MMC predictor set pred time + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] time mmc_pred_time_t + */ +static inline void mmc_pred_set_pred_time(MMC_Type *base, uint8_t index, mmc_pred_time_t time) +{ + base->BR[index].BR_CTRL &= ~MMC_BR_BR_CTRL_PRED_MODE_MASK; + base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_PRED_MODE_SET(time); +} + +/** + * @brief MMC pred enable interrupt + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] int_mask interrupt_mask @ref mmc_pred_int_t + */ +static inline void mmc_pred_enable_interrupt(MMC_Type *base, uint8_t index, uint32_t int_mask) +{ + base->BR[index].BR_CTRL |= int_mask; +} + +/** + * @brief MMC pred disable interrupt + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] int_mask interrupt_mask @ref mmc_pred_int_t + */ +static inline void mmc_pred_disable_interrupt(MMC_Type *base, uint8_t index, uint32_t int_mask) +{ + base->BR[index].BR_CTRL &= ~int_mask; +} + +/** + * @brief MMC predictor get status register value + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @retval predictor status register value + */ +static inline uint32_t mmc_pred_get_status(MMC_Type *base, uint8_t index) +{ + return base->BR[index].BR_ST; +} + +/** + * @brief MMC predictor clear status bit in reigster + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] clr_mask bit mask @ref mmc_pred_event_t + */ +static inline void mmc_pred_clear_status(MMC_Type *base, uint8_t index, uint32_t clr_mask) +{ + base->BR[index].BR_ST = clr_mask; /*!< W1C */ +} + +/** + * @brief MMC predictor get default mode config + * @param [in] base MMC base address + * @param [in] config mmc_pred_mode_t + */ +void mmc_pred_get_default_mode_config(MMC_Type *base, mmc_pred_mode_t *config); + +/** + * @brief MMC predictor config mode + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] config mmc_pred_mode_t + */ +void mmc_pred_config_mode(MMC_Type *base, uint8_t index, mmc_pred_mode_t *config); + +/** + * @brief MMC predictor config position parameter + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] para mmc_pos_or_delta_pos_input_t + * @param [in] req_reload request to update parameter cmd + * + * @note 2 predictors can be set simultaneously by call mmc_pred_reload_pos_cmd() + */ +void mmc_pred_config_pos_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para, bool req_reload); + +/** + * @brief MMC predictor reload position parameter cmd + * @param [in] base MMC base address + * @param [in] cmd mmc_pred_reload_pos_cmd_t + */ +static inline void mmc_pred_reload_pos_cmd(MMC_Type *base, mmc_pred_reload_pos_cmd_t cmd) +{ + base->CR &= ~(MMC_CR_INI_BR0_POS_REQ_MASK | MMC_CR_INI_BR0_POS_REQ_MASK); + base->CR |= cmd << MMC_CR_INI_BR1_POS_REQ_SHIFT; +} + +/** + * @brief MMC predictor update delta parameter + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] para mmc_pos_or_delta_pos_input_t + */ +void mmc_pred_config_delta_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para); + +/** + * @brief MMC predictor config period time + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] time mmc_pred_period_time_t + */ +void mmc_pred_config_period_time(MMC_Type *base, uint8_t index, mmc_pred_period_time_t *time); + +/** + * @brief MMC predictor config position trigger + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] trig mmc_pos_trig_t + */ +void mmc_pred_config_position_trig(MMC_Type *base, uint8_t index, mmc_pos_trig_t *trig); + +/** + * @brief MMC predictor config speed trigger + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [in] trig mmc_speed_trig_t + */ +void mmc_pred_config_speed_trig(MMC_Type *base, uint8_t index, mmc_speed_trig_t *trig); + +/** + * @brief MMC predictor disable position trigger + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + */ +static inline void mmc_pred_disable_position_trig(MMC_Type *base, uint8_t index) +{ + base->BR[index].BR_TRG_POS_CFG &= ~MMC_BR_BR_TRG_POS_CFG_EN_MASK; +} + +/** + * @brief MMC predictor disable speed trigger + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + */ +static inline void mmc_pred_disable_speed_trig(MMC_Type *base, uint8_t index) +{ + base->BR[index].BR_TRG_SPEED_CFG &= ~MMC_BR_BR_TRG_SPEED_CFG_EN_MASK; +} + +/** + * @brief MMC predictor get result + * @param [in] base MMC base address + * @param [in] index predictor index(0/1) + * @param [out] pos_out mmc_pos_out_t + */ +void mmc_pred_get_result(MMC_Type *base, uint8_t index, mmc_pos_out_t *pos_out); + +/** + * @brief MMC predictor get result + * @param [in] base MMC base address + * @param [out] para mmc_pos_or_delta_pos_input_t + */ +void mmc_get_default_pos_or_delta_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_MMC_DRV_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_opamp_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_opamp_drv.h new file mode 100644 index 00000000..3ebf9304 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_opamp_drv.h @@ -0,0 +1,546 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_OPAMP_DRV_H +#define HPM_OPAMP_DRV_H + +#include "hpm_common.h" +#include "hpm_opamp_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief OPMAP driver APIs + * @defgroup opamp_interface OPAMP driver APIs + * @ingroup io_interfaces + * @{ + * + */ +#define OPAMP_MODE_FOLLOW_KEY (0x06) +#define OPAMP_MODE_INVERT_INDEX0_KEY (0x08) +#define OPAMP_MODE_INVERT_INDEX1_KEY (0x18) +#define OPAMP_MODE_NON_INVERT_INDEX0_KEY (0x01) +#define OPAMP_MODE_NON_INVERT_INDEX1_KEY (0x09) +#define OPAMP_MODE_NON_INVERT_INDEX2_KEY (0x11) +#define OPAMP_MODE_NON_INVERT_INDEX3_KEY (0x19) +#define OPAMP_MODE_NON_INVERT_INDEX4_KEY (0x09) +#define OPAMP_MODE_USER_DEFINE_KEY (0x04) + +/** + * @brief Reverse Input Pin Selection + * + */ +typedef enum { + inm_pad_vim0 = 0, /**< Connect pad vim0 */ + inm_pad_vim1 = 1, /**< Connect pad vim1 */ + inm_pad_vim2 = 2, /**< Connect pad vim2 */ + inm_pad_dac = 3, /**< Connect pad vim dac */ + inm_pad_floating = 4 /**< Connect inm floating */ +} opamp_inm_pad_t; + +/** + * @brief Gain multiplier selection + * + */ +typedef enum { + gain_x_2 = 0, /**< gain x2 */ + gain_x_4 = 1, + gain_x_8 = 2, + gain_x_16 = 3, + gain_x_32 = 4, + gain_x_64 = 5, + gain_x_128 = 6, /**< gain x128 */ +} opamp_gain_t; + +/** + * @brief Miller Capacitor Selection + * + */ +typedef enum { + miller_cap_x_7 = 0, /**< 7 unit cap */ + miller_cap_x_8 = 1, + miller_cap_x_10 = 2, + miller_cap_x_13 = 3, + miller_cap_x_15 = 4, /**< 15 unit cap */ + miller_cap_x_18 = 5, + miller_cap_x_5 = 6, + miller_cap_x_6 = 7, /**< 6 unit cap */ +} opamp_miller_cap_t; + +/** + * @brief Positive Input Pin Selection + * + */ +typedef enum { + inp_pad_vip0 = 0, /**< Connect pad vip0 */ + inp_pad_vip1 = 1, /**< Connect pad vip1 */ + inp_pad_vip2 = 2, /**< Connect pad vip2 */ + inp_pad_dac = 3, /**< Connect pad vip dac */ + inp_pad_vsupply_x_0_25 = 4, /**< Connect reference = 0.25 * vsupply */ + inp_pad_vsupply_x_0_5 = 5, /**< Connect reference = 0.5 * vsupply */ + inp_pad_vsupply_x_0_75 = 6, /**< Connect reference = 0.75 * vsupply */ + inp_pad_floating = 7 /**< Connect inp floating */ +} opamp_inp_pad_t; + +/** + * @brief opamp preset channel + * + */ +typedef enum { + cfg_preset_0 = OPAMP_CFG_PRESET0, + cfg_preset_1 = OPAMP_CFG_PRESET1, + cfg_preset_2 = OPAMP_CFG_PRESET2, + cfg_preset_3 = OPAMP_CFG_PRESET3, + cfg_preset_4 = OPAMP_CFG_PRESET4, + cfg_preset_5 = OPAMP_CFG_PRESET5, + cfg_preset_6 = OPAMP_CFG_PRESET6, + cfg_preset_7 = OPAMP_CFG_PRESET7, +} opamp_cfg_preset_chn_t; + +/** + * @brief operational amplifier + * + */ +typedef enum { + mode_follow = 0, /**< opamp follow mode */ + mode_invert_intern_vol = 1, /**< inverting opamp */ + mode_invert_extern_vol = 2, /**< inverted amplification mode, external reference voltage */ + mode_invert_dac_vol = 3, /**< inverted amplification mode, DAC output reference voltage */ + mode_non_invert_gnd_vol = 4, /**< forward amplification mode, GND is the reference voltage */ + mode_non_invert_extern_vol = 5, /**< forward amplification mode, external reference voltage */ + mode_non_invert_dac_vol = 6, /**< forward amplification mode, DAC output reference voltage */ + mode_user = 7, /**< custom Mode */ +} opamp_mode_t; + +/** + * @brief opamp configuration preset0 + * + */ +typedef union opamp_cfg_preset0 { + struct { + uint32_t vip_select: 3; + uint32_t vim_select: 3; + uint32_t vswitch_select: 3; + uint32_t cap_select: 4; + uint32_t reserve: 19; + }; + uint32_t val; +} opamp_ctrl_cfg_preset0_t; + +/** + * @brief opamp configuration preset1 + * + */ +typedef union opamp_cfg_preset1 { + struct { + uint32_t res_select: 3; + uint32_t function_mode: 5; + uint32_t iref_select: 2; + uint32_t opaout_select: 2; + uint32_t is_vssa_disconnect: 1; + uint32_t en_lv: 1; + uint32_t hw_trig_en: 1; + uint32_t reserve: 17; + }; + uint32_t val; +} opamp_ctrl_cfg_preset1_t; + +typedef struct opamp_cfg { + opamp_mode_t mode; + opamp_inm_pad_t negative_input_pin; + opamp_inp_pad_t positive_input_pin; + opamp_gain_t gain; + opamp_miller_cap_t miller_cap; + bool enable_extern_filter_cap; + bool enable_phase_margin_cap; +} opamp_cfg_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief opamp initialisation functions + * Use this function to initialise the op-amp to different modes + * @param opamp @ref OPAMP_Type + * @param cfg @ref opamp_cfg_t + * @return @ref hpm_stat_t + */ +hpm_stat_t opamp_init(OPAMP_Type *opamp, opamp_cfg_t *cfg); +/** + * @brief enable opamp function + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_enable(OPAMP_Type *opamp) +{ + opamp->CTRL0 |= OPAMP_CTRL0_EN_LV_MASK; +} + +/** + * @brief preset enable opamp function + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_opamp_enable(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG1 |= OPAMP_CFG_CFG1_EN_LV_MASK; +} + +/** + * @brief disable opamp function + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_disable(OPAMP_Type *opamp) +{ + opamp->CTRL0 &= ~OPAMP_CTRL0_EN_LV_MASK; +} + +/** + * @brief preset disable opamp function + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_opamp_disable(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG1 &= ~OPAMP_CFG_CFG1_EN_LV_MASK; +} + +/** + * @brief opamp miller cap selection + * + * @param opamp @ref OPAMP_Type + * @param select @ref opamp_iref_select_t + */ +static inline void opamp_miller_cap_select(OPAMP_Type *opamp, opamp_miller_cap_t select) +{ + opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_MILLER_SEL_MASK)) | OPAMP_CTRL0_MILLER_SEL_SET(select); +} + +/** + * @brief opamp miller cap selection preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param select @ref opamp_iref_select_t + */ +static inline void opamp_preset_miller_cap_select(OPAMP_Type *opamp, uint8_t preset_chn, opamp_miller_cap_t select) +{ + opamp->CFG[preset_chn].CFG0 = (opamp->CFG[preset_chn].CFG0 & (~OPAMP_CFG_CFG0_MILLER_SEL_MASK)) | OPAMP_CFG_CFG0_MILLER_SEL_SET(select); +} + +/** + * @brief enable phase margin compensation cap + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_phase_margin_cap_enable(OPAMP_Type *opamp) +{ + opamp->CTRL0 &= ~OPAMP_CTRL0_DISABLE_PM_CAP_MASK; +} + +/** + * @brief enable phase margin compensation cap preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_phase_margin_cap_enable(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG0 &= ~OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK; +} + +/** + * @brief disable phase margin compensation cap + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_phase_margin_cap_disable(OPAMP_Type *opamp) +{ + opamp->CTRL0 |= OPAMP_CTRL0_DISABLE_PM_CAP_MASK; +} + +/** + * @brief disable phase margin compensation cap preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_phase_margin_cap_disable(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG0 |= OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK; +} + +/** + * @brief opamp core inm connect pad + * + * @param opamp @ref OPAMP_Type + * @param select @ref opamp_inm_pad_t + */ +static inline void opamp_inn_pad_select(OPAMP_Type *opamp, opamp_inm_pad_t select) +{ + opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_VIM_SEL_MASK)) | OPAMP_CTRL0_VIM_SEL_SET(select); +} + +/** + * @brief opamp core inm connect pad preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param select @ref opamp_inm_pad_t + */ +static inline void opamp_preset_inn_pad_select(OPAMP_Type *opamp, uint8_t preset_chn, opamp_inm_pad_t select) +{ + opamp->CFG[preset_chn].CFG0 = (opamp->CFG[preset_chn].CFG0 & (~OPAMP_CFG_CFG0_VIM_SEL_MASK)) | OPAMP_CFG_CFG0_VIM_SEL_SET(select); +} + +/** + * @brief main string resistor selection + * + * @param opamp @ref OPAMP_Type + * @param select @ref opamp_gain_t + * + */ +static inline void opamp_gain_select(OPAMP_Type *opamp, opamp_gain_t select) +{ + opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_GAIN_SEL_MASK)) | OPAMP_CTRL0_GAIN_SEL_SET(select); +} + +/** + * @brief main string resistor selection preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param select @ref opamp_gain_t + * + */ +static inline void opamp_preset_gain_select(OPAMP_Type *opamp, uint8_t preset_chn, opamp_gain_t select) +{ + opamp->CFG[preset_chn].CFG1 = (opamp->CFG[preset_chn].CFG1 & (~OPAMP_CFG_CFG1_GAIN_SEL_MASK)) | OPAMP_CFG_CFG1_GAIN_SEL_SET(select); +} + +/** + * @brief disconnect the main series resistor and VSSA + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_disconnect_vssa(OPAMP_Type *opamp) +{ + opamp->CTRL0 |= OPAMP_CTRL0_VBYPASS_MASK; +} + +/** + * @brief disconnect the main series resistor and VSSA preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_disconnect_vssa(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG1 |= OPAMP_CFG_CFG1_VBYPASS_LV_MASK; +} + +/** + * @brief connect the main series resistor and VSSA + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_connect_vssa(OPAMP_Type *opamp) +{ + opamp->CTRL0 &= ~OPAMP_CTRL0_VBYPASS_MASK; +} + +/** + * @brief connect the main series resistor and VSSA preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_connect_vssa(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG1 &= ~OPAMP_CFG_CFG1_VBYPASS_LV_MASK; +} + +/** + * @brief opamp inp select + * + * @param opamp @ref OPAMP_Type + * @param select @ref opamp_inp_pad_t + */ +static inline void opamp_inp_pad_select(OPAMP_Type *opamp, opamp_inp_pad_t select) +{ + opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_VIP_SEL_MASK)) | OPAMP_CTRL0_VIP_SEL_SET(select); +} + +/** + * @brief opamp inp select preset + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param select @ref opamp_inp_pad_t + */ +static inline void opamp_preset_inp_pad_select(OPAMP_Type *opamp, uint8_t preset_chn, opamp_inp_pad_t select) +{ + opamp->CFG[preset_chn].CFG0 = (opamp->CFG[preset_chn].CFG0 & (~OPAMP_CFG_CFG0_VIP_SEL_MASK)) | OPAMP_CFG_CFG0_VIP_SEL_SET(select); +} + + +/** + * @brief opamp get current preset + * + * @param opamp @ref OPAMP_Type + * @return value + */ +static inline uint8_t opamp_get_cur_preset(OPAMP_Type *opamp) +{ + return OPAMP_STATUS_CUR_PRESET_GET(opamp->STATUS); +} + +/** + * @brief get the current preset value + * + * @param opamp @ref OPAMP_Type + * @return true one of cur_preset is selected for opamp + * @return false opamp use cfg0 parameters + */ +static inline bool opamp_get_is_preset(OPAMP_Type *opamp) +{ + return OPAMP_STATUS_PRESET_ACT_GET(opamp->STATUS); +} + +/** + * @brief Get the trigger conflict status + * + * @param opamp @ref OPAMP_Type + * @return if more than one hardware trigger is set, will put all trigger input there. + */ +static inline uint8_t opamp_get_trig_conflict_status(OPAMP_Type *opamp) +{ + return OPAMP_STATUS_TRIG_CONFLICT_GET(opamp->STATUS); +} + +/** + * @brief Clear the trigger conflict status + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_clear_conflict_status(OPAMP_Type *opamp) +{ + opamp->STATUS = OPAMP_STATUS_TRIG_CONFLICT_MASK; +} + +/** + * @brief Set opamp preset value + * + * @param opamp @ref OPAMP_Type + * @param val @ref opamp_cfg_preset_chn_t + */ +static inline void opamp_set_sw_preset_val(OPAMP_Type *opamp, opamp_cfg_preset_chn_t val) +{ + opamp->CTRL1 = (opamp->CTRL1 & (~OPAMP_CTRL1_SW_SEL_MASK)) | OPAMP_CTRL1_SW_SEL_SET(val); +} + +/** + * @brief Enable software preset + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_enable_sw_preset(OPAMP_Type *opamp) +{ + opamp->CTRL1 |= OPAMP_CTRL1_SW_PRESET_MASK; +} + +/** + * @brief Disable software preset + * + * @param opamp @ref OPAMP_Type + */ +static inline void opamp_disable_sw_preset(OPAMP_Type *opamp) +{ + opamp->CTRL1 &= ~OPAMP_CTRL1_SW_PRESET_MASK; +} + + +/** + * @brief Set preset x channel value + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param chn channel + */ +static inline void opamp_set_preset_x_chn(OPAMP_Type *opamp, uint8_t preset_chn, uint8_t chn) +{ + opamp->CFG[preset_chn].CFG2 = OPAMP_CFG_CFG2_CHANNEL_SET(chn); +} + +/** + * @brief Set preset cfg + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param cfg @ref opamp_cfg_t + * @return hpm_stat_t + */ +hpm_stat_t opamp_set_preset_cfg(OPAMP_Type *opamp, uint8_t preset_chn, opamp_cfg_t *cfg); + +/** + * @brief opamp enable preset hardware trig + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_enable_hw_trig(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG1 |= OPAMP_CFG_CFG1_HW_TRIG_EN_MASK; +} + +/** + * @brief opamp disable preset hardware trig + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + */ +static inline void opamp_preset_disable_hw_trig(OPAMP_Type *opamp, uint8_t preset_chn) +{ + opamp->CFG[preset_chn].CFG1 &= ~OPAMP_CFG_CFG1_HW_TRIG_EN_MASK; +} + +/** + * @brief opamp set mode + * + * @param opamp @ref OPAMP_Type + * @param mode @ref OPAMP_MODE_XX + */ +static inline void opamp_mode_set(OPAMP_Type *opamp, uint8_t mode) +{ + opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_MODE_MASK)) | OPAMP_CTRL0_MODE_SET(mode); +} + +/** + * @brief opamp preset set mode + * + * @param opamp @ref OPAMP_Type + * @param preset_chn preset channel + * @param mode @ref OPAMP_MODE_XX + */ +static inline void opamp_preset_mode_set(OPAMP_Type *opamp, uint8_t preset_chn, uint8_t mode) +{ + opamp->CFG[preset_chn].CFG1 = (opamp->CFG[preset_chn].CFG1 & (~OPAMP_CFG_CFG1_MODE_MASK)) | OPAMP_CFG_CFG1_MODE_SET(mode); +} + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_ACMP_DRV_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_pdgo_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_pdgo_drv.h new file mode 100644 index 00000000..40e6cdfb --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_pdgo_drv.h @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PDGO_DRV_H +#define HPM_PDGO_DRV_H + +#include "hpm_common.h" +#include "hpm_pdgo_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DGO_GPR_WORD_COUNT (4U) /*!< DGO GPR register count */ +#define DGO_WAKEUP_COUNTER_TICKS_PER_SEC (32768UL) /*!< DGO Wakeup Counter frequency */ +#define DGO_TURNOFF_COUNTER_TICKS_PER_SEC (24000000UL) /*!< DGO Turn-off counter frequency */ +#define DGO_WAKEUP_TICK_IN_US (1000000UL / DGO_WAKEUP_COUNTER_TICKS_PER_SEC) +#define DGO_TURNOFF_TICKS_PER_US (DGO_TURNOFF_COUNTER_TICKS_PER_SEC / 1000000UL) + +/** +* +* @brief PDGO driver APIs +* @defgroup pdgo_interface DGO driver APIs +* @ingroup pdgo_interfaces +* @{ +* +*/ + +/** + * @brief Set DGO turn-off counter + * @param [in] ptr DGO base address + * @param [in] counter Turn-off counter value. Clock source is 32K + */ +static inline void pdgo_set_turnoff_counter(PDGO_Type *ptr, uint32_t counter) +{ + ptr->DGO_TURNOFF = counter; +} + +/** + * @brief Enable Software Wake-up feature on DGO + * @param [in] ptr DGO base address + */ +static inline void pdgo_enable_software_wakeup(PDGO_Type *ptr) +{ + ptr->DGO_CTR1 |= PDGO_DGO_CTR1_WAKEUP_EN_MASK; +} + +/** + * @brief Disable Software Wake-up feature on DGO + * @param [in] ptr DGO base address + */ +static inline void pdgo_disable_software_wakeup(PDGO_Type *ptr) +{ + ptr->DGO_CTR1 &= ~PDGO_DGO_CTR1_WAKEUP_EN_MASK; +} + +/** + * @brief Set DGO to one-shot wakeup mode + * @param [in] ptr DGO base address + */ +static inline void pdgo_enable_oneshot_wakeup(PDGO_Type *ptr) +{ + ptr->DGO_CTR1 &= ~PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK; +} + +/** + * @brief Enable DGO register retention mode + * @param [in] ptr DGO base address + */ +static inline void pdgo_enable_retention_mode(PDGO_Type *ptr) +{ + ptr->DGO_CTR1 |= PDGO_DGO_CTR0_RETENTION_MASK; +} + +/** + * @brief Check whether the DGO retention mode is enabled or not + * @param [in] ptr DGO base address + * + * @retval true Retention mode is enabled + * @retval false Retention mode is disabled + */ +static inline bool pdgo_is_retention_mode_enabled(PDGO_Type *ptr) +{ + return ((ptr->DGO_CTR1 & PDGO_DGO_CTR0_RETENTION_MASK) != 0U); +} + +/** + * @brief Disable DGO register retention mode + * @param [in] ptr DGO base address + */ +static inline void pdgo_disable_retention_mode(PDGO_Type *ptr) +{ + ptr->DGO_CTR1 &= ~PDGO_DGO_CTR0_RETENTION_MASK; +} + +/** + * @brief Set DGO to automatic wakeup mode + * @param [in] ptr DGO base address + */ +static inline void pdgo_enable_auto_wakeup(PDGO_Type *ptr) +{ + ptr->DGO_CTR1 |= PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK; +} + +#if defined(PDGO_SUPPORT_SYS_WAKEUP_STATUS) && (PDGO_SUPPORT_SYS_WAKEUP_STATUS == 1) +/** + * @brief Check whether DGO is waked up by System/Software + * @param [in] ptr DGO base address + * + * @retval true if DGO is waked up by System/Software + */ +static inline bool pdgo_is_system_wakeup(PDGO_Type *ptr) +{ + return ((ptr->DGO_CTR1 & PDGO_DGO_CTR1_SYS_WAKEUP_STATUS_MASK) != 0U); +} +#endif + +/** + * @brief Check whether DGO is waked up by Wake-up/Reset Pin + * @param [in] ptr DGO base address + * + * @retval true if DGO is waked up by Wakeup/Reset pin + */ +static inline bool pdgo_is_pin_wakeup(PDGO_Type *ptr) +{ + return ((ptr->DGO_CTR1 & PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK) != 0U); +} + + +/** + * @brief Check whether Auto wake-up is enabled + * @param [in] ptr DGO base address + * + * @retval true - Auto wake-up is enabled + * @retval false - Auto wake-up is disabled + */ +static inline bool pdgo_is_auto_wakeup_enabled(PDGO_Type *ptr) +{ + return ((ptr->DGO_CTR1 & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) != 0U); +} + +/** + * @brief Enable pull-up resistor for Reset Pin + * [in] ptr DGO base address + */ +static inline void pdgo_enable_pullup_resistor_for_reset_pin(PDGO_Type *ptr) +{ + ptr->DGO_CTR2 &= ~PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK; +} + +/** + * @brief Disable pull-up resistor for Reset Pin + * [in] ptr DGO base address + */ +static inline void pdgo_disable_pullup_resistor_for_reset_pin(PDGO_Type *ptr) +{ + ptr->DGO_CTR2 |= PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK; +} + +/** + * Enable pull-down resistor for Wakeup pin + * [in] ptr DGO base address + */ +static inline void pdgo_enable_pulldown_resistor_for_wakeup_pin(PDGO_Type *ptr) +{ + ptr->DGO_CTR2 &= ~PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK; +} + +/** + * Disable pull-down resistor for Wakeup pin + * [in] ptr DGO base address + */ +static inline void pdgo_disable_pulldown_resistor_for_wakeup_pin(PDGO_Type *ptr) +{ + ptr->DGO_CTR2 |= PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK; +} + +/** + * @brief Set DGO wakeup counter + * @param [in] ptr DGO base address + * @param [in] counter Wakeup counter value. clock source is 32K + */ +static inline void pdgo_set_wakeup_counter(PDGO_Type *ptr, uint32_t wakeup_ctr) +{ + ptr->DGO_CTR3 = wakeup_ctr; +} + +/** + * @brief Get DGO wakeup counter value + * @param [in] ptr DGO base address + * + * @return DGO wakeup counter value + */ +static inline uint32_t pdgo_get_wakeup_counter(PDGO_Type *ptr) +{ + return ptr->DGO_CTR3; +} + +/** + * @brief Write data to DGO GPR register + * @param [in] ptr DGO base address + * @param [in] index GPR register index + * @param [in] content Data to be written to DGO GPR register + */ +static inline void pdgo_write_gpr(PDGO_Type *ptr, uint32_t index, uint32_t content) +{ + if (index < DGO_GPR_WORD_COUNT) { + *(volatile uint32_t *) ((uint32_t) &ptr->DGO_GPR00 + index * 4) = content; + } +} + +/** + * @brief Read data from DGO GPR register + * @param [in] ptr DGO base address + * @param [in] index GPR register index + * + * @return DGO GPR register value + */ +static inline uint32_t pdgo_read_gpr(PDGO_Type *ptr, uint32_t index) +{ + uint32_t reg_val = 0; + if (index < DGO_GPR_WORD_COUNT) { + reg_val = *(volatile uint32_t *) ((uint32_t) &ptr->DGO_GPR00 + index * 4); + } + return reg_val; +} + +/** + * @brief Convert the microsecond to DGO Wake-up counter value + * @param [in] us microsecond to be converted + * + * @return Converted DGO Wake-up counter value + */ +static inline uint32_t pdgo_get_wakeup_counter_from_us(uint32_t us) +{ + return (us + DGO_WAKEUP_TICK_IN_US - 1U) / DGO_WAKEUP_TICK_IN_US; +} + +/** + * @brief Convert the DGO Wake-up counter to microseconds + * @param [in] counter DGO counter + * + * @return Converted microseconds + */ +static inline uint32_t pdgo_get_us_from_wakeup_counter(uint32_t counter) +{ + return (counter * DGO_WAKEUP_TICK_IN_US); +} + +/** + * @brief Convert the microsecond to DGO Turn-off counter value + * @param [in] us microsecond to be converted + * + * @return Converted DGO Turn-off counter value + */ +static inline uint32_t pdgo_get_turnoff_counter_from_us(uint32_t us) +{ + return (us * DGO_TURNOFF_TICKS_PER_US); +} + +/** + * @brief Convert the DGO Turn-off counter to microseconds + * @param [in] counter DGO Turn-off counter + * + * @return Converted microseconds + */ +static inline uint32_t pdgo_get_us_from_turnoff_counter(uint32_t counter) +{ + return (counter + DGO_TURNOFF_TICKS_PER_US - 1U) / DGO_TURNOFF_TICKS_PER_US; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* HPM_DGO_DRV_H */ \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_plb_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_plb_drv.h new file mode 100644 index 00000000..421418bf --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_plb_drv.h @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLB_DRV_H +#define HPM_PLB_DRV_H + +#include "hpm_common.h" +#include "hpm_plb_regs.h" + +/** + * @brief PLB driver APIs + * @defgroup pla_interface PLB driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief plb channels + * + */ +typedef enum plb_chn { + plb_chn0 = 0, + plb_chn1 = 1, + plb_chn2 = 2, + plb_chn3 = 3, +} plb_chn_t; + +/** + * @brief PLB look-up table unit + * + */ +typedef enum plb_type_a_lut_num { + plb_type_a_table0 = PLB_TYPE_A_0, + plb_type_a_table1 = PLB_TYPE_A_1, + plb_type_a_table2 = PLB_TYPE_A_2, + plb_type_a_table3 = PLB_TYPE_A_3, +} plb_type_a_lut_num_t; + +/** + * @brief PLB truth table configuration unit + * + */ +typedef union { + struct { + uint16_t index0_1bit_out: 1; + uint16_t index1_1bit_out: 1; + uint16_t index2_1bit_out: 1; + uint16_t index3_1bit_out: 1; + uint16_t index4_1bit_out: 1; + uint16_t index5_1bit_out: 1; + uint16_t index6_1bit_out: 1; + uint16_t index7_1bit_out: 1; + uint16_t index8_1bit_out: 1; + uint16_t index9_1bit_out: 1; + uint16_t index10_1bit_out: 1; + uint16_t index11_1bit_out: 1; + uint16_t index12_1bit_out: 1; + uint16_t index13_1bit_out: 1; + uint16_t index14_1bit_out: 1; + uint16_t index15_1bit_out: 1; + }; + uint16_t val; +} plb_type_a_truth_t; + +/** + * @brief Index of slice + * + */ +typedef enum plb_type_b_lut_slice { + plb_type_b_slice_0 = 0, + plb_type_b_slice_1 = 1, + plb_type_b_slice_2 = 2, + plb_type_b_slice_3 = 3, + plb_type_b_slice_4 = 4, + plb_type_b_slice_5 = 5, + plb_type_b_slice_6 = 6, + plb_type_b_slice_7 = 7, + plb_type_b_slice_8 = 8, + plb_type_b_slice_9 = 9, + plb_type_b_slice_10 = 10, + plb_type_b_slice_11 = 11, + plb_type_b_slice_12 = 12, + plb_type_b_slice_13 = 13, + plb_type_b_slice_14 = 14, + plb_type_b_slice_15 = 15, +} plb_type_b_lut_slice_t; + +/** + * @brief Configuration of slice + * + */ +typedef enum plb_type_b_slice_opt { + plb_slice_opt_keep = 0, /**< The data unit keeps the value of the previous cycle */ + plb_slice_opt_get_cmp0_val = 1, /**< The data unit will take the value of the cmp0 register as the value for the next cycle */ + plb_slice_opt_get_cmp1_val = 2, /**< The data unit will take the value of the cmp1 register as the value for the next cycle */ + plb_slice_opt_get_cmp2_val = 3, /**< The data unit will take the value of the cmp2 register as the value for the next cycle */ + plb_slice_opt_add_one = 4, /**< The next cycle value of the data cell is the current value plus 1 */ + plb_slice_opt_add_two = 5, /**< The next cycle value of the data cell is the current value plus 2 */ + plb_slice_opt_sub_one = 6, /**< The next cycle value of the data cell is the current value minus 1 */ + plb_slice_opt_sub_two = 7, /**< The next cycle value of the data cell is the current value minus 2 */ + plb_slice_opt_shift_left = 4 << 8, /**< The value of the next cycle of the data cell is shifted one place to the left of the current value */ + plb_slice_opt_shift_left_add_one = 5 << 8, /**< The next cycle value of the data cell is the current value shifted one place to the left, with the lower bit complemented by one */ + plb_slice_opt_shift_right = 6 << 8, /**< The value of the next cycle of the data cell is shifted one place to the right of the current value */ + plb_slice_opt_shift_right_add_one = 7 << 8, /**< The next cycle value of the data cell is the current value shifted one place to the right, with the lower bit complemented by one */ +} plb_type_b_slice_opt_t; + +/** + * @brief Comparator index + * + */ +typedef enum plb_type_b_cmp { + plb_type_b_cmp0 = PLB_TYPE_B_CMP_0, + plb_type_b_cmp1 = PLB_TYPE_B_CMP_1, + plb_type_b_cmp2 = PLB_TYPE_B_CMP_2, + plb_type_b_cmp3 = PLB_TYPE_B_CMP_3, +} plb_type_b_cmp_t; + +/** + * @brief Comparator operation + * + */ +typedef enum plb_type_b_cmp_mode { + plb_cmp_mode_out_zero = 0, /**< output zero */ + plb_cmp_mode_out_one = 1, /**< output one */ + plb_cmp_mode_gt = 2, /**< Data unit greater than cmp output one, otherwise output zero */ + plb_cmp_mode_lt = 3, /**< Data unit less than cmp output one, otherwise output zero */ + plb_cmp_mode_eq = 4, /**< Data unit equal to cmp output one, otherwise output zero */ + plb_cmp_mode_ne = 5, /**< Data unit not equal to cmp output one, otherwise output zero */ + plb_cmp_mode_ge = 6, /**< Data unit greater than or equal to cmp output one, otherwise output zero */ + plb_cmp_mode_le = 7, /**< Data unit less than or equal to cmp output one, otherwise output zero */ + plb_cmp_mode_and_mask = 10, /**< The data cell corresponding to the bit set to one by cmp is and */ + plb_cmp_mode_or_mask = 11, /**< The data cell corresponding to the bit set to one by cmp is or */ + plb_cmp_mode_xor_mask = 12, /**< The data cell corresponding to the bit set to one by cmp is xor */ + plb_cmp_mode_nand_mask = 13, /**< The data cell corresponding to the bit set to one by cmp is nand */ + plb_cmp_mode_nor_mask = 14, /**< The data cell corresponding to the bit set to one by cmp is nor */ + plb_cmp_mode_xnor_mask = 15, /**< The data cell corresponding to the bit set to one by cmp is xnor */ +} plb_type_b_cmp_mode_t; + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Configuring the truth table for lookup tables + * + * @param plb @ref PLB_Type plb base + * @param chn @ref plb_chn_t + * @param lut_num @ref plb_type_a_lut_num_t + * @param truth @ref plb_type_a_truth_t + */ +static inline void plb_type_a_set_lut(PLB_Type *plb, plb_chn_t chn, plb_type_a_lut_num_t lut_num, plb_type_a_truth_t *truth) +{ + plb->TYPE_A[chn].LOOKUP_TABLE[lut_num] = PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SET(truth->val); +} + +/** + * @brief The software injects a cycle value into the TYPE A channel. + * + * @param plb @ref PLB_Type plb base + * @param chn @ref plb_chn_t + * @param inject_val Injected values + */ +static inline void plb_type_a_inject_by_sw(PLB_Type *plb, plb_chn_t chn, uint8_t inject_val) +{ + plb->TYPE_A[chn].SW_INJECT = PLB_TYPE_A_SW_INJECT_SW_INJECT_SET(inject_val); +} + +/** + * @brief Configure the value of the CMP + * + * @param plb @ref PLB_Type plb base + * @param chn @ref plb_chn_t + * @param cmp_index @ref plb_type_b_cmp_t + * @param val CMP value + */ +static inline void plb_type_b_set_cmp_val(PLB_Type *plb, plb_chn_t chn, plb_type_b_cmp_t cmp_index, uint32_t val) +{ + plb->TYPE_B[chn].CMP[cmp_index] = PLB_TYPE_B_CMP_CMP_VALUE_SET(val); +} + +/** + * @brief Setting the mode of the CMP + * + * @param plb @ref PLB_Type plb base + * @param chn @ref plb_chn_t + * @param cmp_index @ref plb_type_b_cmp_t + * @param cmp_mode @ref plb_type_b_cmp_mode_t + */ +static inline void plb_type_b_set_cmp_mode(PLB_Type *plb, plb_chn_t chn, plb_type_b_cmp_t cmp_index, plb_type_b_cmp_mode_t cmp_mode) +{ + plb->TYPE_B[chn].MODE = (plb->TYPE_B[chn].MODE & (~(PLB_TYPE_B_MODE_OUT0_SEL_MASK << (cmp_index << 2)))) | + ((PLB_TYPE_B_MODE_OUT0_SEL_MASK & cmp_mode) << (cmp_index << 2)); +} + +/** + * @brief Software injection values + * + * @param plb @ref PLB_Type plb base + * @param chn @ref plb_chn_t + * @param val value + */ +static inline void plb_type_b_inject_by_sw(PLB_Type *plb, plb_chn_t chn, uint32_t val) +{ + plb->TYPE_B[chn].SW_INJECT = val; +} + +/** + * @brief Configuring the PLB type_b's lookup table + * + * @param plb @ref PLB_Type plb base + * @param chn @ref plb_chn_t + * @param slice @ref plb_type_b_lut_slice_t + * @param opt @ref plb_type_b_slice_opt_t + */ +void plb_type_b_set_lut(PLB_Type *plb, plb_chn_t chn, plb_type_b_lut_slice_t slice, plb_type_b_slice_opt_t opt); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* HPM_PLB_DRV_H */ + diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h index 8b0285a4..84eb9fec 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h @@ -389,6 +389,17 @@ static inline void pllctl_xtal_set_rampup_time(PLLCTL_Type *ptr, uint32_t cycles ptr->XTAL = (ptr->XTAL & ~PLLCTL_XTAL_RAMP_TIME_MASK) | PLLCTL_XTAL_RAMP_TIME_SET(cycles); } +/** + * @brief Set pll work mode + * + * @param[in] ptr PLLCTL base address + * @param[in] pll Target PLL index + * @param[in] int_mode true: integer mode, false - fraction mode + * + * @return status_success if everything is okay + */ +hpm_stat_t pllctl_set_pll_work_mode(PLLCTL_Type *ptr, uint8_t pll, bool int_mode); + /** * @brief Set refdiv * diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h index 70b3ab15..2f200b04 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h @@ -8,6 +8,7 @@ #define HPM_PMP_DRV_H #include "hpm_common.h" +#include "hpm_soc_feature.h" /** * @brief PMP Entry structure @@ -26,6 +27,7 @@ typedef struct pmp_entry_struct { } pmp_cfg; uint8_t reserved0[3]; uint32_t pmp_addr; +#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) union { struct { uint8_t entry_addr_matching_mode: 2; @@ -37,6 +39,7 @@ typedef struct pmp_entry_struct { } pma_cfg; uint8_t reserved1[3]; uint32_t pma_addr; +#endif } pmp_entry_t; /** @@ -134,13 +137,6 @@ extern "C" { */ void write_pmp_cfg(uint32_t value, uint32_t idx); -/** - * @brief Write PMA Configuration to corresponding PMA_CFG register - * @param value PMA configuration - * @param idx PMA entry index, valid value is 0-15 - */ -void write_pma_cfg(uint32_t value, uint32_t idx); - /** * @brief Read PMP configuration * @param idx PMP entry index @@ -148,6 +144,22 @@ void write_pma_cfg(uint32_t value, uint32_t idx); */ uint32_t read_pmp_cfg(uint32_t idx); + +/** + * @brief Write PMP address to corresponding PMP_ADDR register + * @param value PMP address + * @param idx PMP address entry index, valid value is 0-15 + */ +void write_pmp_addr(uint32_t value, uint32_t idx); + +/** + * @brief Read PMP address entry + * @param idx PMP address entry index + * @return PMP address + */ +uint32_t read_pmp_addr(uint32_t idx); + +#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) /** * @brief Read PMA configuration * @param idx PMA entry index @@ -156,11 +168,11 @@ uint32_t read_pmp_cfg(uint32_t idx); uint32_t read_pma_cfg(uint32_t idx); /** - * @brief Write PMP address to corresponding PMP_ADDR register - * @param value PMP address - * @param idx PMP address entry index, valid value is 0-15 + * @brief Write PMA Configuration to corresponding PMA_CFG register + * @param value PMA configuration + * @param idx PMA entry index, valid value is 0-15 */ -void write_pmp_addr(uint32_t value, uint32_t idx); +void write_pma_cfg(uint32_t value, uint32_t idx); /** * @brief Write PMA address to corresponding PMA_ADDR register @@ -169,20 +181,13 @@ void write_pmp_addr(uint32_t value, uint32_t idx); */ void write_pma_addr(uint32_t value, uint32_t idx); -/** - * @brief Read PMP address entry - * @param idx PMP address entry index - * @return PMP address - */ -uint32_t read_pmp_addr(uint32_t idx); - /** * @brief Read PMA address entry * @param idx PMA address entry index, valid value is 0-15 * @return PMA address */ uint32_t read_pma_addr(uint32_t idx); - +#endif /* #if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) */ /** * @brief Configure PMP and PMA for specified PMP/PMA entry diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h index a03c9bd5..08da278c 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h @@ -290,7 +290,7 @@ static inline uint32_t ptpc_get_capture_second(PTPC_Type *ptr, uint8_t index) */ static inline void ptpc_clear_irq_status(PTPC_Type *ptr, uint32_t mask) { - ptr->INT_STS |= mask; + ptr->INT_STS = mask; } /** diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h index 4992eca5..4eeedacb 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h @@ -10,6 +10,7 @@ #include "hpm_common.h" #include "hpm_pwm_regs.h" +#include "hpm_soc_feature.h" /** * @brief PWM driver APIs * @defgroup pwm_interface PWM driver APIs @@ -159,10 +160,11 @@ typedef struct pwm_output_channel { * */ typedef struct pwm_fault_source_config { - uint32_t source_mask; /**< fault source mask*/ - bool fault_recover_at_rising_edge; /**< recover fault at rising edge */ - bool external_fault_active_low; /**< active external fault by low */ - uint8_t fault_output_recovery_trigger; /**< fault output recoverty trigger */ + uint32_t source_mask; /**< fault source mask*/ + bool fault_recover_at_rising_edge; /**< recover fault at rising edge */ + bool fault_external_0_active_low; /**< active external fault0 by low */ + bool fault_external_1_active_low; /**< active external fault1 by low */ + uint8_t fault_output_recovery_trigger; /**< fault output recoverty trigger */ } pwm_fault_source_config_t; /** @@ -170,6 +172,9 @@ typedef struct pwm_fault_source_config { * */ typedef struct pwm_config { +#if PWM_SOC_HRPWM_SUPPORT + bool hrpwm_update_mode; /**< mode one or zero, HR CMP update timing */ +#endif bool enable_output; /**< enable pwm output */ bool invert_output; /**< invert pwm output level */ uint8_t update_trigger; /**< pwm config update trigger */ @@ -191,6 +196,33 @@ typedef struct pwm_pair_config { extern "C" { #endif +/** + * @brief pwm deinitialize function + * + * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) + * + */ +static inline void pwm_deinit(PWM_Type *pwm_x) +{ + pwm_x->IRQEN = 0; + pwm_x->DMAEN = 0; + pwm_x->SR |= pwm_x->SR; + pwm_x->STA = 0; + pwm_x->RLD = PWM_RLD_RLD_MASK; + for (uint8_t i = 0; i < PWM_SOC_CMP_MAX_COUNT; i++) { + pwm_x->CMP[i] = PWM_CMP_CMP_MASK; + pwm_x->CMPCFG[i] = 0; + pwm_x->CHCFG[i] = PWM_CHCFG_CMPSELEND_SET(PWM_SOC_CMP_MAX_COUNT - 1) | PWM_CHCFG_CMPSELBEG_SET(PWM_SOC_CMP_MAX_COUNT - 1); + } + pwm_x->FRCMD = 0; + pwm_x->GCR = 0; + pwm_x->SHCR = 0; + pwm_x->HRPWM_CFG = 0; + for (uint8_t i = 0; i < PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT; i++) { + pwm_x->PWMCFG[i] = 0; + } +} + /** * @brief issue all shawdow register * @@ -463,6 +495,19 @@ static inline void pwm_load_cmp_shadow_on_capture(PWM_Type *pwm_x, } #if PWM_SOC_SHADOW_TRIG_SUPPORT + +/** + * @brief RLD, STA shadow registers take effect at the reload point + * + * @param pwm_x pwm_x PWM base address, HPM_PWMx(x=0..n) + * @param is_enable true or false + */ +static inline void pwm_set_cnt_shadow_trig_reload(PWM_Type *pwm_x, bool is_enable) +{ + pwm_x->SHCR = ((pwm_x->SHCR & ~PWM_SHCR_CNT_UPDATE_RELOAD_MASK) + | PWM_SHCR_CNT_UPDATE_RELOAD_SET(is_enable)); +} + /** * @brief Set the timer shadow register to update the trigger edge * @@ -590,7 +635,7 @@ static inline void pwm_config_cmp(PWM_Type *pwm_x, uint8_t index, pwm_cmp_config | PWM_CMP_HRPWM_CMP_HR_SET(config->hrcmp); } else { #endif - pwm_x->CMPCFG[index] = PWM_CMPCFG_XCNTCMPEN_SET(config->enable_ex_cmp) + pwm_x->CMPCFG[index] = (config->enable_ex_cmp ? PWM_CMPCFG_XCNTCMPEN_MASK : 0) | PWM_CMPCFG_CMPSHDWUPT_SET(config->update_trigger); pwm_x->CMP[index] = PWM_CMP_CMP_SET(config->cmp) | PWM_CMP_XCMP_SET(config->ex_cmp) @@ -632,7 +677,7 @@ static inline void pwm_config_fault_source(PWM_Type *pwm_x, pwm_fault_source_con | PWM_GCR_FAULTRECEDG_MASK | PWM_GCR_FAULTEXPOL_MASK | PWM_GCR_FAULTRECHWSEL_MASK)) | config->source_mask - | PWM_GCR_FAULTEXPOL_SET(config->external_fault_active_low) + | PWM_GCR_FAULTEXPOL_SET((config->fault_external_0_active_low ? 0x1 : 0) | (config->fault_external_1_active_low ? 0x2 : 0)) | PWM_GCR_FAULTRECEDG_SET(config->fault_recover_at_rising_edge) | PWM_GCR_FAULTRECHWSEL_SET(config->fault_output_recovery_trigger); } @@ -796,6 +841,9 @@ static inline void pwm_config_pwm(PWM_Type *pwm_x, uint8_t index, | PWM_PWMCFG_FAULTRECTIME_SET(config->fault_recovery_trigger) | PWM_PWMCFG_FRCSRCSEL_SET(config->force_source) | PWM_PWMCFG_PAIR_SET(enable_pair_mode) +#if PWM_SOC_HRPWM_SUPPORT + | PWM_PWMCFG_HR_UPDATE_MODE_SET(config->hrpwm_update_mode) +#endif | PWM_PWMCFG_DEADAREA_SET(config->dead_zone_in_half_cycle); } diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h index bfd6ffb1..3d333257 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h @@ -361,6 +361,50 @@ static inline uint32_t qei_get_current_count(QEI_Type *qei_x, return *(&qei_x->COUNT[QEI_COUNT_CURRENT].Z + type); } +/** + * @brief get current phcnt value + * + * @param qei_x QEI base address, HPM_QEIx(x=0...n) + * @return phcnt value + */ +static inline uint32_t qei_get_current_phase_phcnt(QEI_Type *qei_x) +{ + return QEI_COUNT_PH_PHCNT_GET(qei_get_current_count(qei_x, qei_counter_type_phase)); +} + +/** + * @brief get current a phase status + * + * @param qei_x QEI base address, HPM_QEIx(x=0...n) + * @return a phase level + */ +static inline bool qei_get_current_phase_astat(QEI_Type *qei_x) +{ + return QEI_COUNT_PH_ASTAT_GET(qei_get_current_count(qei_x, qei_counter_type_phase)); +} + +/** + * @brief get current b phase status + * + * @param qei_x QEI base address, HPM_QEIx(x=0...n) + * @return b phase level + */ +static inline bool qei_get_current_phase_bstat(QEI_Type *qei_x) +{ + return QEI_COUNT_PH_BSTAT_GET(qei_get_current_count(qei_x, qei_counter_type_phase)); +} + +/** + * @brief get current phase dir + * + * @param qei_x QEI base address, HPM_QEIx(x=0...n) + * @return dir + */ +static inline bool qei_get_current_phase_dir(QEI_Type *qei_x) +{ + return QEI_COUNT_PH_DIR_GET(qei_get_current_count(qei_x, qei_counter_type_phase)); +} + /** * @brief get read event count value * diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_qeiv2_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_qeiv2_drv.h new file mode 100644 index 00000000..681a75e1 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_qeiv2_drv.h @@ -0,0 +1,1426 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_QEIV2_DRV_H +#define HPM_QEIV2_DRV_H + +#include "hpm_common.h" +#include "hpm_qeiv2_regs.h" +/** + * @brief QEIV2 driver APIs + * @defgroup qeiv2_interface QEIV2 driver APIs + * @ingroup io_interfaces + * @{ + */ +#define QEIV2_EVENT_WDOG_FLAG_MASK (1U << 31U) /**< watchdog flag */ +#define QEIV2_EVENT_HOME_FLAG_MASK (1U << 30U) /**< home flag */ +#define QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK (1U << 29U) /**< postion compare match flag */ +#define QEIV2_EVENT_Z_PHASE_FLAG_MASK (1U << 28U) /**< z input flag */ +#define QEIV2_EVENT_Z_MISS_FLAG_MASK (1U << 27U) /**< z miss flag */ +#define QEIV2_EVENT_WIDTH_TIME_FLAG_MASK (1U << 26U) /**< width time flag */ +#define QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK (1U << 25U) /**< postion2 compare match flag */ +#define QEIV2_EVENT_DIR_CHG_FLAG_MASK (1U << 24U) /**< direction change flag */ +#define QEIV2_EVENT_CYCLE0_FLAG_MASK (1U << 23U) /**< cycle0 flag */ +#define QEIV2_EVENT_CYCLE1_FLAG_MASK (1U << 22U) /**< cycle1 flag */ +#define QEIV2_EVENT_PULSE0_FLAG_MASK (1U << 21U) /**< pulse0 flag */ +#define QEIV2_EVENT_PULSE1_FLAG_MASK (1U << 20U) /**< pulse1 flag */ +#define QEIV2_EVENT_HOME2_FLAG_MASK (1U << 19U) /**< home2 flag */ +#define QEIV2_EVENT_FAULT_FLAG_MASK (1U << 18U) /**< fault flag */ + +/** + * @brief qeiv2 work mode + * + */ +typedef enum qeiv2_work_mode { + qeiv2_work_mode_abz = 0, /**< Orthogonal decoder mode */ + qeiv2_work_mode_pd = 1, /**< Directional (PD) mode */ + qeiv2_work_mode_ud = 2, /**< Up and Down (UD) mode */ + qeiv2_work_mode_uvw = 3, /**< UVW mode */ + qeiv2_work_mode_single = 4, /**< Single-phase mode */ + qeiv2_work_mode_sin = 5, /**< Single sinewave mode */ + qeiv2_work_mode_sincos = 6, /**< Orthogonal sinewave mode */ +} qeiv2_work_mode_t; + +/** + * @brief spd and tmr read selection + * + */ +typedef enum qeiv2_spd_tmr_content { + qeiv2_spd_tmr_as_spd_tm = 0, /**< spd and timer register as spd and time */ + qeiv2_spd_tmr_as_pos_angle = 1, /**< spd and timer register as position and angle */ +} qeiv2_spd_tmr_content_t; + +/** + * @brief compare match rotate direction + * + */ +typedef enum qeiv2_rotate_dir { + qeiv2_rotate_dir_forward = 0, + qeiv2_rotate_dir_reverse = 1, +} qeiv2_rotate_dir_t; /**< compare match rotate direction */ + +/** + * @brief compare match position direction + * + */ +typedef enum qeiv2_position_dir { + qeiv2_pos_dir_decrease = 0, + qeiv2_pos_dir_increase = 1, +} qeiv2_position_dir_t; /**< compare match position direction */ + +/** + * @brief counting mode of Z-phase counter + * + */ +typedef enum qeiv2_z_count_work_mode { + qeiv2_z_count_inc_on_z_input_assert = 0, /**< zcnt will increment or decrement when Z input assert */ + qeiv2_z_count_inc_on_phase_count_max = 1, /**< zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 */ +} qeiv2_z_count_work_mode_t; + +/** + * @brief counter type + * + */ +typedef enum qeiv2_counter_type { + qeiv2_counter_type_z = 0, /**< Z counter */ + qeiv2_counter_type_phase = 1, /**< Phase counter */ + qeiv2_counter_type_speed = 2, /**< Speed counter */ + qeiv2_counter_type_timer = 3, /**< Timer counter */ +} qeiv2_counter_type_t; + +/** + * @brief filter mode + * + */ +typedef enum qeiv2_filter_mode { + qeiv2_filter_mode_bypass = 0, /**< bypass */ + qeiv2_filter_mode_burr = 4, /**< rapid change mode */ + qeiv2_filter_mode_delay, /**< delay filter mode */ + qeiv2_filter_mode_peak, /**< stable low mode */ + qeiv2_filter_mode_valley, /**< stable high mode */ +} qeiv2_filter_mode_t; + +/** + * @brief filter type + * + */ +typedef enum qeiv2_filter_phase { + qeiv2_filter_phase_a = 0, /**< filter phase a */ + qeiv2_filter_phase_b, /**< filter phase b */ + qeiv2_filter_phase_z, /**< filter phase z */ + qeiv2_filter_phase_h, /**< filter phase h */ + qeiv2_filter_phase_h2, /**< filter phase h2 */ + qeiv2_filter_phase_f, /**< filter phase f */ +} qeiv2_filter_phase_t; /**< qeiv2_filter_phase_t */ + +/** + * @brief uvw position option + * + */ +typedef enum qeiv2_uvw_pos_opt { + qeiv2_uvw_pos_opt_current = 0, /**< output exact point position, MMC use this */ + qeiv2_uvw_pos_opt_next, /**< output next area position, QEO use this */ +} qeiv2_uvw_pos_opt_t; + +typedef enum qeiv2_uvw_pos_sel { + qeiv2_uvw_pos_sel_low = 0, + qeiv2_uvw_pos_sel_high, + qeiv2_uvw_pos_sel_edge +} qeiv2_uvw_pos_sel_t; /**< qeiv2_uvw_pos_sel_t */ + +/** + * @brief qeiv2 uvw position selection + * + */ +#define QEIV2_UVW_POS_OPT_CUR_SEL_LOW 0u +#define QEIV2_UVW_POS_OPT_CUR_SEL_HIGH 1u +#define QEIV2_UVW_POS_OPT_CUR_SEL_EDGE 2u +#define QEIV2_UVW_POS_OPT_NEX_SEL_LOW 0u +#define QEIV2_UVW_POS_OPT_NEX_SEL_HIGH 3u + +typedef enum qeiv2_uvw_pos_idx { + qeiv2_uvw_pos0 = 0, + qeiv2_uvw_pos1, + qeiv2_uvw_pos2, + qeiv2_uvw_pos3, + qeiv2_uvw_pos4, + qeiv2_uvw_pos5, +} qeiv2_uvw_pos_idx_t; /**< qeiv2_uvw_pos_idx_t */ + +/** + * @brief phase counter compare match config structure + * + */ +typedef struct { + uint32_t phcnt_cmp_value; + bool ignore_rotate_dir; + qeiv2_rotate_dir_t rotate_dir; + bool ignore_zcmp; + uint32_t zcmp_value; +} qeiv2_phcnt_cmp_match_config_t; + +/** + * @brief position compare match config structure + * + */ +typedef struct { + uint32_t pos_cmp_value; + bool ignore_pos_dir; + qeiv2_position_dir_t pos_dir; +} qeiv2_pos_cmp_match_config_t; + +/** + * @brief uvw config structure + */ +typedef struct { + qeiv2_uvw_pos_opt_t pos_opt; + qeiv2_uvw_pos_sel_t u_pos_sel[6]; + qeiv2_uvw_pos_sel_t v_pos_sel[6]; + qeiv2_uvw_pos_sel_t w_pos_sel[6]; + uint32_t pos_cfg[6]; +} qeiv2_uvw_config_t; + +/** + * @brief adc config structure + */ +typedef struct { + uint8_t adc_select; + uint8_t adc_channel; + int16_t param0; + int16_t param1; + uint32_t offset; +} qeiv2_adc_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief load phcnt, zcnt, spdcnt and tmrcnt into their read registers + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + */ +static inline void qeiv2_load_counter_to_read_registers(QEIV2_Type *qeiv2_x) +{ + qeiv2_x->CR |= QEIV2_CR_READ_MASK; +} + +/** + * @brief config z phase counter increment and decrement mode + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mode + * @arg 1 zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 + * @arg 0 zcnt will increment or decrement when Z input assert + */ +static inline void qeiv2_config_z_phase_counter_mode(QEIV2_Type *qeiv2_x, qeiv2_z_count_work_mode_t mode) +{ + qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_ZCNTCFG_MASK) | QEIV2_CR_ZCNTCFG_SET(mode); +} + +/** + * @brief config phase max value and phase param + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] phmax maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + */ +static inline void qeiv2_config_phmax_phparam(QEIV2_Type *qeiv2_x, uint32_t phmax) +{ + uint32_t tmp; + + if (phmax > 0u) { + phmax--; + } + qeiv2_x->PHCFG = QEIV2_PHCFG_PHMAX_SET(phmax); + if (phmax == 0u) { + qeiv2_x->PHASE_PARAM = 0xFFFFFFFFu; + } else { + tmp = (0x80000000u / (phmax + 1u)); + tmp <<= 1u; + qeiv2_x->PHASE_PARAM = QEIV2_PHASE_PARAM_PHASE_PARAM_SET(tmp); + } +} + +/** + * @brief config phase calibration value trigged by z phase + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] enable phcnt will set to phidx when Z input assert + * @param[in] phidx phcnt reset value + * @param[in] mode qeiv2_work_mode_t + */ +static inline void qeiv2_config_z_phase_calibration(QEIV2_Type *qeiv2_x, uint32_t phidx, bool enable, qeiv2_work_mode_t mode) +{ + uint32_t tmp = qeiv2_x->CR; + qeiv2_x->PHIDX = QEIV2_PHIDX_PHIDX_SET(phidx); + if (enable) { + tmp |= QEIV2_CR_PHCALIZ_MASK; + } else { + tmp &= ~QEIV2_CR_PHCALIZ_MASK; + } + if (enable && ((mode == qeiv2_work_mode_sin) || (mode == qeiv2_work_mode_sincos))) { + tmp |= QEIV2_CR_Z_ONLY_EN_MASK; + } else { + tmp &= ~QEIV2_CR_Z_ONLY_EN_MASK; + } + qeiv2_x->CR = tmp; +} + +/** + * @brief pause counter when pause assert + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] counter_mask + * @arg QEIV2_CR_PAUSEPOS_MASK + * @arg QEIV2_CR_PAUSESPD_MASK + * @arg QEIV2_CR_PAUSEPH_MASK + * @arg QEIV2_CR_PAUSEZ_MASK + * @param[in] enable enable or disable pause + */ +static inline void qeiv2_pause_counter(QEIV2_Type *qeiv2_x, uint32_t counter_mask, bool enable) +{ + if (enable) { + qeiv2_x->CR |= counter_mask; + } else { + qeiv2_x->CR &= ~counter_mask; + } +} + +/** + * @brief pause pos counter when fault assert + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] enable enable or disable pause + */ +static inline void qeiv2_pause_pos_counter_on_fault(QEIV2_Type *qeiv2_x, bool enable) +{ + if (enable) { + qeiv2_x->CR |= QEIV2_CR_FAULTPOS_MASK; + } else { + qeiv2_x->CR &= ~QEIV2_CR_FAULTPOS_MASK; + } +} + +/** + * @brief enable load phcnt, zcnt, spdcnt and tmrcnt into their snap registers + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + */ +static inline void qeiv2_enable_snap(QEIV2_Type *qeiv2_x) +{ + qeiv2_x->CR |= QEIV2_CR_SNAPEN_MASK; +} + +/** + * @brief disable snap + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + */ +static inline void qeiv2_disable_snap(QEIV2_Type *qeiv2_x) +{ + qeiv2_x->CR &= ~QEIV2_CR_SNAPEN_MASK; +} + +/** + * @brief reset zcnt, spdcnt and tmrcnt to 0, reset phcnt to phidx. + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + */ +static inline void qeiv2_reset_counter(QEIV2_Type *qeiv2_x) +{ + qeiv2_x->CR |= QEIV2_CR_RSTCNT_MASK; +} + +/** + * @brief release counter. + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + */ +static inline void qeiv2_release_counter(QEIV2_Type *qeiv2_x) +{ + qeiv2_x->CR &= ~QEIV2_CR_RSTCNT_MASK; +} + +/** + * @brief select spd and tmr register content + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mode @ref qeiv2_spd_tmr_content_select_t + */ +static inline void qeiv2_select_spd_tmr_register_content(QEIV2_Type *qeiv2_x, qeiv2_spd_tmr_content_t content) +{ + qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_RD_SEL_MASK) | QEIV2_CR_RD_SEL_SET(content); +} + +/** + * @brief check spd and tmr register content as pos and angle + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @return true if spd and timer register as pos and angle register + */ +static inline bool qeiv2_check_spd_tmr_as_pos_angle(QEIV2_Type *qeiv2_x) +{ + return ((qeiv2_x->CR & QEIV2_CR_RD_SEL_MASK) != 0) ? true : false; +} + +/** + * @brief set qeiv2 work mode + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mode @ref qeiv2_work_mode_t + */ +static inline void qeiv2_set_work_mode(QEIV2_Type *qeiv2_x, qeiv2_work_mode_t mode) +{ + qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_ENCTYP_MASK) | QEIV2_CR_ENCTYP_SET(mode); +} + +/** + * @brief config watchdog + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] timeout watchdog timeout time + * @param[in] clr_phcnt the phase_cnt time passed, then clear wdog counter + * @param[in] enable + * @arg 1 - enable watchdog + * @arg 0 - disable watchdog + */ +static inline void qeiv2_config_wdog(QEIV2_Type *qeiv2_x, uint32_t timeout, uint8_t clr_phcnt, bool enable) +{ + uint32_t tmp; + tmp = QEIV2_WDGCFG_WDGTO_SET(timeout) | QEIV2_WDGCFG_WDOG_CFG_SET(clr_phcnt); + if (enable) { + tmp |= QEIV2_WDGCFG_WDGEN_MASK; + } else { + tmp &= ~QEIV2_WDGCFG_WDGEN_MASK; + } + qeiv2_x->WDGCFG = tmp; +} + +/** + * @brief enable trig out trigger event + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] event_mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_enable_trig_out_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask) +{ + qeiv2_x->TRGOEN |= event_mask; +} + +/** + * @brief disable trig out trigger event + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] event_mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_disable_trig_out_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask) +{ + qeiv2_x->TRGOEN &= ~event_mask; +} + +/** + * @brief enable load read trigger event + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] event_mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_enable_load_read_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask) +{ + qeiv2_x->READEN |= event_mask; +} + +/** + * @brief disable load read trigger event + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] event_mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_disable_load_read_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask) +{ + qeiv2_x->READEN &= ~event_mask; +} + +/** + * @brief enable dma request + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_enable_dma_request(QEIV2_Type *qeiv2_x, uint32_t mask) +{ + qeiv2_x->DMAEN |= mask; +} + +/** + * @brief disable qeiv2 dma + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_disable_dma_request(QEIV2_Type *qeiv2_x, uint32_t mask) +{ + qeiv2_x->DMAEN &= ~mask; +} + +/** + * @brief clear qeiv2 status register + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_clear_status(QEIV2_Type *qeiv2_x, uint32_t mask) +{ + qeiv2_x->SR = mask; +} + +/** + * @brief get qeiv2 status + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval qeiv2 status: + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline uint32_t qeiv2_get_status(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->SR; +} + +/** + * @brief get qeiv2 bit status + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + * @retval true or false + */ +static inline bool qeiv2_get_bit_status(QEIV2_Type *qeiv2_x, uint32_t mask) +{ + return ((qeiv2_x->SR & mask) == mask) ? true : false; +} + +/** + * @brief enable qeiv2 irq + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_enable_irq(QEIV2_Type *qeiv2_x, uint32_t mask) +{ + qeiv2_x->IRQEN |= mask; +} + +/** + * @brief disable qeiv2 irq + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] mask + * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK + * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK + * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK + * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK + * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK + * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK + * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK + * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK + */ +static inline void qeiv2_disable_irq(QEIV2_Type *qeiv2_x, uint32_t mask) +{ + qeiv2_x->IRQEN &= ~mask; +} + +/** + * @brief get current counter value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] type @ref qeiv2_counter_type_t + * @retval counter value + */ +static inline uint32_t qeiv2_get_current_count(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) +{ + return *(&qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z + type); +} + +/** + * @brief get current phcnt value + * + * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n) + * @return phcnt value + */ +static inline uint32_t qeiv2_get_current_phase_phcnt(QEIV2_Type *qeiv2_x) +{ + return QEIV2_COUNT_PH_PHCNT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase)); +} + +/** + * @brief get current a phase level + * + * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n) + * @return a phase level + */ +static inline bool qeiv2_get_current_phase_a_level(QEIV2_Type *qeiv2_x) +{ + return QEIV2_COUNT_PH_ASTAT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase)); +} + +/** + * @brief get current b phase level + * + * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n) + * @return b phase level + */ +static inline bool qeiv2_get_current_phase_b_level(QEIV2_Type *qeiv2_x) +{ + return QEIV2_COUNT_PH_BSTAT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase)); +} + +/** + * @brief get current phase dir + * + * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n) + * @return dir + */ +static inline bool qeiv2_get_current_phase_dir(QEIV2_Type *qeiv2_x) +{ + return QEIV2_COUNT_PH_DIR_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase)); +} + + +/** + * @brief get read event count value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] type @ref qeiv2_counter_type_t + * @retval counter value + */ +static inline uint32_t qeiv2_get_count_on_read_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) +{ + return *(&(qeiv2_x->COUNT[QEIV2_COUNT_READ].Z) + type); +} + +/** + * @brief read the value of each phase snapshot 0 counter + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] type @ref qeiv2_counter_type_t + * @retval counter value + */ +static inline uint32_t qeiv2_get_count_on_snap0_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) +{ + return *(&qeiv2_x->COUNT[QEIV2_COUNT_SNAP0].Z + type); +} + +/** + * @brief read the value of each phase snapshot 1 counter + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] type @ref qeiv2_counter_type_t + * @retval counter value + */ +static inline uint32_t qeiv2_get_count_on_snap1_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) +{ + return *(&qeiv2_x->COUNT[QEIV2_COUNT_SNAP1].Z + type); +} + +/** + * @brief set zcnt compare value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cmp zcnt compare value + */ +static inline void qeiv2_set_z_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp) +{ + qeiv2_x->ZCMP = QEIV2_ZCMP_ZCMP_SET(cmp); +} + +/** + * @brief set phcnt compare value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cmp phcnt compare value + */ +static inline void qeiv2_set_phcnt_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp) +{ + qeiv2_x->PHCMP = QEIV2_PHCMP_PHCMP_SET(cmp); +} + +/** + * @brief set spdcnt or position compare value. It's selected by CR register rd_sel bit. + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cmp spdcnt or position compare value + * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder) + * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder) + */ +static inline void qeiv2_set_spd_pos_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp) +{ + qeiv2_x->SPDCMP = QEIV2_SPDCMP_SPDCMP_SET(cmp); +} + +/** + * @brief set compare match options + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] ignore_zcmp ignore zcmp + * @param[in] ignore_phcmp ignore phcmp + * @param[in] ignore_spdposcmp ignore spdposcmp + * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder) + * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder) + * @param[in] ignore_rotate_dir ignore encoder rotation direction. (ABZ encoder) + * @param[in] rotate_dir when don't ignore rotation direction, match rotation direction. @ref qeiv2_rotate_dir_t. (ABZ encoder) + * @param[in] ignore_pos_dir ignore position increase or decrease direction. (sin or sincos encoder) + * @param[in] pos_dir when don't ignore position direction, match position direction. @ref qeiv2_position_dir_t. (sin or sincos encoder) + */ +static inline void qeiv2_set_cmp_match_option(QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp, + bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir) +{ + qeiv2_x->MATCH_CFG = (qeiv2_x->MATCH_CFG & (~(QEIV2_MATCH_CFG_ZCMPDIS_MASK | QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK | QEIV2_MATCH_CFG_SPDCMPDIS_MASK + | QEIV2_MATCH_CFG_DIRCMPDIS_MASK | QEIV2_MATCH_CFG_DIRCMP_MASK + | QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK | QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK))) + | QEIV2_MATCH_CFG_ZCMPDIS_SET(ignore_zcmp) | QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(ignore_phcmp) + | QEIV2_MATCH_CFG_SPDCMPDIS_SET(ignore_spdposcmp) + | QEIV2_MATCH_CFG_DIRCMPDIS_SET(ignore_rotate_dir) | QEIV2_MATCH_CFG_DIRCMP_SET(rotate_dir) + | QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(!ignore_pos_dir) | QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(pos_dir); +} + +/** + * @brief set zcnt compare2 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cmp zcnt compare2 value + */ +static inline void qeiv2_set_z_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp) +{ + qeiv2_x->ZCMP2 = QEIV2_ZCMP2_ZCMP2_SET(cmp); +} + +/** + * @brief set phcnt compare2 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cmp phcnt compare2 value + */ +static inline void qeiv2_set_phcnt_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp) +{ + qeiv2_x->PHCMP2 = QEIV2_PHCMP2_PHCMP2_SET(cmp); +} + +/** + * @brief set spdcnt or position compare2 value. It's selected by CR register rd_sel bit. + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cmp spdcnt or position compare2 value + */ +static inline void qeiv2_set_spd_pos_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp) +{ + qeiv2_x->SPDCMP2 = QEIV2_SPDCMP2_SPDCMP2_SET(cmp); +} + +/** + * @brief set compare2 match options + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] ignore_zcmp ignore zcmp + * @param[in] ignore_phcmp ignore phcmp + * @param[in] ignore_spdposcmp ignore spdposcmp. + * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder) + * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder) + * @param[in] ignore_rotate_dir ignore encoder rotation direction. (ABZ encoder) + * @param[in] rotate_dir when don't ignore rotation direction, match rotation direction. @ref qeiv2_rotate_dir_t. (ABZ encoder) + * @param[in] ignore_pos_dir ignore position increase or decrease direction. (sin or sincos encoder) + * @param[in] pos_dir when don't ignore position direction, match position direction. @ref qeiv2_position_dir_t. (sin or sincos encoder) + */ +static inline void qeiv2_set_cmp2_match_option(QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp, + bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir) +{ + qeiv2_x->MATCH_CFG = (qeiv2_x->MATCH_CFG & ~(QEIV2_MATCH_CFG_ZCMP2DIS_MASK | QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK | QEIV2_MATCH_CFG_SPDCMP2DIS_MASK + | QEIV2_MATCH_CFG_DIRCMP2DIS_MASK | QEIV2_MATCH_CFG_DIRCMP2_MASK + | QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK | QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK)) + | QEIV2_MATCH_CFG_ZCMP2DIS_SET(ignore_zcmp) | QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(ignore_phcmp) + | QEIV2_MATCH_CFG_SPDCMP2DIS_SET(ignore_spdposcmp) + | QEIV2_MATCH_CFG_DIRCMP2DIS_SET(ignore_rotate_dir) | QEIV2_MATCH_CFG_DIRCMP2_SET(rotate_dir) + | QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(!ignore_pos_dir) | QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(pos_dir); +} + +/** + * @brief config signal filter + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] idx filter index + * @arg @ref qeiv2_filter_phase_t + * @param[in] outinv Filter will invert the output + * @param[in] mode qeiv2_filter_mode_t + * @param[in] sync set to enable sychronization input signal with TRGM clock + * @param[in] filtlen defines the filter counter length. + */ +static inline void qeiv2_config_filter(QEIV2_Type *qeiv2_x, qeiv2_filter_phase_t phase, bool outinv, qeiv2_filter_mode_t mode, bool sync, uint16_t filtlen) +{ + qeiv2_x->FILT_CFG[phase] = + QEIV2_FILT_CFG_OUTINV_SET(outinv) | QEIV2_FILT_CFG_MODE_SET(mode) | QEIV2_FILT_CFG_SYNCEN_SET(sync) | QEIV2_FILT_CFG_FILTLEN_SET(filtlen); +} + +/** + * @brief config signal enablement and edge + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] siga_en enable signal A/U + * @param[in] sigb_en enable signal B/V + * @param[in] sigz_en enable signal Z/W + * @param[in] posedge_en enable rise edge + * @param[in] negedge_en enable fall edge + */ +static inline void qeiv2_config_abz_uvw_signal_edge(QEIV2_Type *qeiv2_x, bool siga_en, bool sigb_en, bool sigz_en, bool posedge_en, bool negedge_en) +{ + qeiv2_x->QEI_CFG = (qeiv2_x->QEI_CFG & ~(QEIV2_QEI_CFG_SIGA_EN_MASK | QEIV2_QEI_CFG_SIGB_EN_MASK | QEIV2_QEI_CFG_SIGZ_EN_MASK + | QEIV2_QEI_CFG_POSIDGE_EN_MASK | QEIV2_QEI_CFG_NEGEDGE_EN_MASK)) + | (QEIV2_QEI_CFG_SIGA_EN_SET(siga_en) | QEIV2_QEI_CFG_SIGB_EN_SET(sigb_en) | QEIV2_QEI_CFG_SIGZ_EN_SET(sigz_en) + | QEIV2_QEI_CFG_POSIDGE_EN_SET(posedge_en) | QEIV2_QEI_CFG_NEGEDGE_EN_SET(negedge_en)); +} + +/** + * @brief set pulse0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] pulse_num for speed detection, will count the cycle number for configed pulse_num + */ +static inline void qeiv2_set_pulse0_num(QEIV2_Type *qeiv2_x, uint32_t pulse_num) +{ + qeiv2_x->PULSE0_NUM = QEIV2_PULSE0_NUM_PULSE0_NUM_SET(pulse_num); +} + +/** + * @brief get cycle0 snap0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval cycle0 snap0 value + */ +static inline uint32_t qeiv2_get_pulse0_cycle_snap0(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->CYCLE0_SNAP0; +} + +/** + * @brief get cycle0 snap1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval cycle0 snap1 value + */ +static inline uint32_t qeiv2_get_pulse0_cycle_snap1(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->CYCLE0_SNAP1; +} + +/** + * @brief set pulse1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] pulse_num for speed detection, will count the cycle number for configed pulse_num + */ +static inline void qeiv2_set_pulse1_num(QEIV2_Type *qeiv2_x, uint32_t pulse_num) +{ + qeiv2_x->PULSE1_NUM = QEIV2_PULSE1_NUM_PULSE1_NUM_SET(pulse_num); +} + +/** + * @brief get cycle1 snap0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval cycle1 snap0 value + */ +static inline uint32_t qeiv2_get_pulse1_cycle_snap0(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->CYCLE1_SNAP0; +} + +/** + * @brief get cycle1 snap1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval cycle1 snap1 value + */ +static inline uint32_t qeiv2_get_pulse1_cycle_snap1(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->CYCLE1_SNAP1; +} + +/** + * @brief set cycle0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cycle_num for speed detection, will count the pulse number for configed cycle_num + */ +static inline void qeiv2_set_cycle0_num(QEIV2_Type *qeiv2_x, uint32_t cycle_num) +{ + qeiv2_x->CYCLE0_NUM = QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(cycle_num); +} + +/** + * @brief get pulse0 snap0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse0 snap0 value + */ +static inline uint32_t qeiv2_get_cycle0_pulse_snap0(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE0_SNAP0; +} + +/** + * @brief get pulse0 snap1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse0 snap1 value + */ +static inline uint32_t qeiv2_get_cycle0_pulse_snap1(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE0_SNAP1; +} + +/** + * @brief get pulse0cycle snap0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse0cycle snap0 value + */ +static inline uint32_t qeiv2_get_cycle0_pulse0cycle_snap0(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE0CYCLE_SNAP0; +} + +/** + * @brief get pulse0cycle snap1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse0cycle snap1 value + */ +static inline uint32_t qeiv2_get_cycle0_pulse0cycle_snap1(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE0CYCLE_SNAP1; +} + +/** + * @brief set cycle1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cycle_num for speed detection, will count the pulse number for configed cycle_num + */ +static inline void qeiv2_set_cycle1_num(QEIV2_Type *qeiv2_x, uint32_t cycle_num) +{ + qeiv2_x->CYCLE1_NUM = QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(cycle_num); +} + +/** + * @brief get pulse1 snap0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse1 snap0 value + */ +static inline uint32_t qeiv2_get_cycle1_pulse_snap0(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE1_SNAP0; +} + +/** + * @brief get pulse1 snap1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse1 snap1 value + */ +static inline uint32_t qeiv2_get_cycle1_pulse_snap1(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE1_SNAP1; +} + +/** + * @brief get pulse1cycle snap0 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse1cycle snap0 value + */ +static inline uint32_t qeiv2_get_cycle1_pulse1cycle_snap0(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE1CYCLE_SNAP0; +} + +/** + * @brief get pulse1cycle snap1 value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval pulse01cycle snap1 value + */ +static inline uint32_t qeiv2_get_cycle1_pulse1cycle_snap1(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PULSE1CYCLE_SNAP1; +} + +/** + * @brief enable or disable clear counter if detect direction change + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] enable enable or disable clear counter if detect direction change + */ +static inline void qeiv2_clear_counter_when_dir_chg(QEIV2_Type *qeiv2_x, bool enable) +{ + if (enable) { + qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK; + } else { + qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK; + } +} + +/** + * @brief adcx config + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config qeiv2_adc_config_t + */ +static inline void qeiv2_config_adcx(QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable) +{ + uint32_t tmp; + tmp = QEIV2_ADCX_CFG0_X_ADCSEL_SET(config->adc_select) | QEIV2_ADCX_CFG0_X_CHAN_SET(config->adc_channel); + qeiv2_x->ADCX_CFG1 = QEIV2_ADCX_CFG1_X_PARAM1_SET(config->param1) | QEIV2_ADCX_CFG1_X_PARAM0_SET(config->param0); + qeiv2_x->ADCX_CFG2 = QEIV2_ADCX_CFG2_X_OFFSET_SET(config->offset); + if (enable) { + tmp |= QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK; + } else { + tmp &= ~QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK; + } + qeiv2_x->ADCX_CFG0 = tmp; +} + +/** + * @brief adcy config + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config qeiv2_adc_config_t + */ +static inline void qeiv2_config_adcy(QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable) +{ + uint32_t tmp; + tmp = QEIV2_ADCY_CFG0_Y_ADCSEL_SET(config->adc_select) | QEIV2_ADCY_CFG0_Y_CHAN_SET(config->adc_channel); + qeiv2_x->ADCY_CFG1 = QEIV2_ADCY_CFG1_Y_PARAM1_SET(config->param1) | QEIV2_ADCY_CFG1_Y_PARAM0_SET(config->param0); + qeiv2_x->ADCY_CFG2 = QEIV2_ADCY_CFG2_Y_OFFSET_SET(config->offset); + if (enable) { + tmp |= QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK; + } else { + tmp &= ~QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK; + } + qeiv2_x->ADCY_CFG0 = tmp; +} + +/** + * @brief set adcx and adcy delay + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] delay x/y delay, default 1.25us@200MHz, max 80ms + */ +static inline void qeiv2_set_adc_xy_delay(QEIV2_Type *qeiv2_x, uint32_t delay) +{ + qeiv2_x->CAL_CFG = QEIV2_CAL_CFG_XY_DELAY_SET(delay); +} + +/** + * @brief set position threshold + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] threshold Position change threshold. When two position changes exceed this value, + * it will be considered as an invalid position and no valid signal will be output. + */ +static inline void qeiv2_set_position_threshold(QEIV2_Type *qeiv2_x, uint32_t threshold) +{ + qeiv2_x->POS_THRESHOLD = QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(threshold); +} + +/** + * @brief set uvw position option + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] opt qeiv2_uvw_pos_opt_t + */ +static inline void qeiv2_set_uvw_position_opt(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_opt_t opt) +{ + qeiv2_x->QEI_CFG = (qeiv2_x->QEI_CFG & ~QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) | QEIV2_QEI_CFG_UVW_POS_OPT0_SET(opt); +} + +/** + * @brief set config uvw position + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] idx uvw position config index + * @arg @ref qeiv2_uvw_pos_idx_t + * @param[in] u_pos_sel U position selection based by uvw position option + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE + * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW + * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH + * @param[in] v_pos_sel V position selection based by uvw position option + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE + * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW + * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH + * @param[in] w_pos_sel W position selection based by uvw position option + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH + * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE + * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW + * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH + * @param[in] enable enable this uvw config + */ +static inline void qeiv2_set_uvw_position_sel(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint8_t u_pos_sel, uint8_t v_pos_sel, + uint8_t w_pos_sel, bool enable) +{ + uint32_t tmp; + tmp = QEIV2_UVW_POS_CFG_U_POS_SEL_SET(u_pos_sel) + | QEIV2_UVW_POS_CFG_V_POS_SEL_SET(v_pos_sel) + | QEIV2_UVW_POS_CFG_W_POS_SEL_SET(w_pos_sel); + if (enable) { + tmp |= QEIV2_UVW_POS_CFG_POS_EN_MASK; + } else { + tmp &= ~QEIV2_UVW_POS_CFG_POS_EN_MASK; + } + qeiv2_x->UVW_POS_CFG[idx] = tmp; +} + +/** + * @brief set uvw position + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] idx uvw position config index + * @arg @ref qeiv2_uvw_pos_idx_t + * @param[in] pos angle corresponding to UVW signal position + */ +static inline void qeiv2_set_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint32_t pos) +{ + qeiv2_x->UVW_POS[idx] = pos; +} + +/** + * @brief set z phase counter value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cnt z phase counter value + */ +static inline void qeiv2_set_z_phase(QEIV2_Type *qeiv2_x, uint32_t cnt) +{ + qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z = cnt; +} + +/** + * @brief set phase counter value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] cnt phase counter value + */ +static inline void qeiv2_set_phase_cnt(QEIV2_Type *qeiv2_x, uint32_t cnt) +{ + qeiv2_x->PHASE_CNT = cnt; +} + +/** + * @brief get phase counter value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval phase counter value + */ +static inline uint32_t qeiv2_get_phase_cnt(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->PHASE_CNT; +} + +/** + * @brief update phase counter value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] inc set to add value to phase_cnt + * @param[in] inc set to minus value to phase_cnt (set inc and dec same time willl act inc) + * @param[in] value value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation. + */ +static inline void qeiv2_update_phase_cnt(QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value) +{ + qeiv2_x->PHASE_UPDATE = QEIV2_PHASE_UPDATE_INC_SET(inc) | QEIV2_PHASE_UPDATE_DEC_SET(dec) | QEIV2_PHASE_UPDATE_VALUE_SET(value); +} + +/** + * @brief set position value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] pos position + */ +static inline void qeiv2_set_position(QEIV2_Type *qeiv2_x, uint32_t pos) +{ + qeiv2_x->POSITION = pos; +} + +/** + * @brief get position value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval position value + */ +static inline uint32_t qeiv2_get_postion(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->POSITION; +} + +/** + * @brief update position value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] inc set to add value to position + * @param[in] inc set to minus cnt value to position (set inc and dec same time willl act inc) + * @param[in] value value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation. + */ +static inline void qeiv2_update_position(QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value) +{ + qeiv2_x->POSITION_UPDATE = QEIV2_POSITION_UPDATE_INC_SET(inc) | QEIV2_POSITION_UPDATE_DEC_SET(dec) | QEIV2_POSITION_UPDATE_VALUE_SET(value); +} + +/** + * @brief get angle value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @retval angle value + */ +static inline uint32_t qeiv2_get_angle(QEIV2_Type *qeiv2_x) +{ + return qeiv2_x->ANGLE; +} + +/** + * @brief set angle adjust value + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] angle_adj angle adjust value + */ +static inline void qeiv2_set_angle_adjust_value(QEIV2_Type *qeiv2_x, int32_t angle_adj) +{ + qeiv2_x->ANGLE_ADJ = QEIV2_ANGLE_ADJ_ANGLE_ADJ_SET(angle_adj); +} + +/** + * @brief config position timeout for mmc module + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] tm postion timeout value + * @param[in] enable enable position timeout feature. If timeout, send valid again. + */ +static inline void qeiv2_config_position_timeout(QEIV2_Type *qeiv2_x, uint32_t tm, bool enable) +{ + uint32_t tmp; + tmp = QEIV2_POS_TIMEOUT_TIMEOUT_SET(tm); + if (enable) { + tmp |= QEIV2_POS_TIMEOUT_ENABLE_MASK; + } else { + tmp &= ~QEIV2_POS_TIMEOUT_ENABLE_MASK; + } + qeiv2_x->POS_TIMEOUT = tmp; +} + +/** + * @brief config phcnt compare match condition + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config @ref qeiv2_phcnt_cmp_match_config_t + * @return status_invalid_argument or status_success + */ +hpm_stat_t qeiv2_config_phcnt_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config); + +/** + * @brief config position compare match condition + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config @ref qeiv2_pos_cmp_match_config_t + * @return status_invalid_argument or status_success + */ +hpm_stat_t qeiv2_config_position_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config); + +/** + * @brief config phcnt compare2 match condition + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config @ref qeiv2_phcnt_cmp_match_config_t + * @return status_invalid_argument or status_success + */ +hpm_stat_t qeiv2_config_phcnt_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config); + +/** + * @brief config position compare2 match condition + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config @ref qeiv2_pos_cmp_match_config_t + * @return status_invalid_argument or status_success + */ +hpm_stat_t qeiv2_config_position_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config); + +/** + * @brief get uvw position default config + * + * @param[out] config uvw position default config structure pointer + */ +void qeiv2_get_uvw_position_defconfig(qeiv2_uvw_config_t *config); + +/** + * @brief config uvw position + * + * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) + * @param[in] config uvw position config structure pointer + * @return status_invalid_argument or status_success + */ +hpm_stat_t qeiv2_config_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_config_t *config); + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_QEIV2_DRV_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_qeo_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_qeo_drv.h new file mode 100644 index 00000000..cf255dbd --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_qeo_drv.h @@ -0,0 +1,558 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_QEO_DRV_H +#define HPM_QEO_DRV_H + +#include "hpm_common.h" +#include "hpm_qeo_regs.h" +/** + * @brief QEO driver APIs + * @defgroup qeo_interface QEO driver APIs + * @ingroup qeo_interface + * @{ + */ + +typedef enum { + qeo_wave_cosine = 0, + qeo_wave_saddle = 1, + qeo_wave_abs_cosine = 2, + qeo_wave_saw = 3, +} qeo_wave_type_t; + +typedef enum { + qeo_wave_above_max_limit_max_val = 0, + qeo_wave_above_max_limit_zero = 1, + qeo_wave_above_max_limit_max_level0_val = 2, + + qeo_wave_high_area_limit_max_val = 0, + qeo_wave_high_area_limit_max_level0_val = 1, + + qeo_wave_low_area_limit_zero = 0, + qeo_wave_low_area_limit_min_level1_val = 1, + + qeo_wave_below_min_limit_zero = 0, + qeo_wave_below_min_limit_max_val = 1, + qeo_wave_below_min_limit_min_level1_val = 2, +} qeo_wave_limit_t; + +typedef struct { + uint8_t above_max_limit; + uint8_t high_area0_limit; + uint8_t high_area1_limit; + uint8_t low_area0_limit; + uint8_t low_area1_limit; + uint8_t below_min_limit; +} qeo_wave_limit_config_t; + +typedef struct { + qeo_wave_limit_config_t wave0; + qeo_wave_limit_config_t wave1; + qeo_wave_limit_config_t wave2; + uint8_t wave_type; + uint8_t saddle_type; +} qeo_wave_mode_t; + +typedef enum { + qeo_abz_output_abz = 0, /*< A and B are orthogonal signals, Z is zero pulse */ + qeo_abz_output_pulse_revise = 1, /*< A is speed pulse, B is directional pulse, Z not used */ + qeo_abz_output_up_down = 2, /*< A is forward pulse, B is reverse pusle, Z not used */ + qeo_abz_output_three_phase = 3, /*< A/B/Z are 3-phase orthogonal pulse */ +} qeo_abz_type_t; + +/* take effect when output type is qeo_abz_output_abz */ +typedef enum { + qeo_z_pulse_25_percent = 0, + qeo_z_pulse_75_percent = 1, + qeo_z_pulse_100_percent = 2, +} qeo_z_pulse_period_t; + +typedef struct { + bool z_inv_pol; + bool b_inv_pol; + bool a_inv_pol; + uint8_t output_type; /*!< @ref qeo_abz_type_t */ + uint8_t z_pulse_period; /*!< @ref qeo_z_pulse_period_t */ +} qeo_abz_mode_t; + +typedef enum { + qeo_pwm_output_force_0 = 2, + qeo_pwm_output_force_1 = 3, + qeo_pwm_output_not_force = 0, +} qeo_pwm_force_output_t; + +typedef enum { + qeo_pwm_safety_output_0 = 0, + qeo_pwm_safety_output_1 = 1, + qeo_pwm_safety_output_highz = 2, +} qeo_pwm_safety_output_t; + +typedef struct { + uint8_t pwm0_output; /*!< @ref qeo_pwm_force_output_t */ + uint8_t pwm1_output; + uint8_t pwm2_output; + uint8_t pwm3_output; + uint8_t pwm4_output; + uint8_t pwm5_output; + uint8_t pwm6_output; + uint8_t pwm7_output; +} qeo_pwm_phase_output_table_t; + +typedef struct { + uint8_t pwm0_output; /*!< @ref qeo_pwm_safety_output_t */ + uint8_t pwm1_output; + uint8_t pwm2_output; + uint8_t pwm3_output; + uint8_t pwm4_output; + uint8_t pwm5_output; + uint8_t pwm6_output; + uint8_t pwm7_output; +} qeo_pwm_safety_output_table_t; + +typedef struct { + uint8_t phase_num; + bool shield_hardware_trig_safety; + bool revise_pairs_output; +} qeo_pwm_mode_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* WAVE API */ +/** + * @brief QEO set resolution lines for wave mode + * @param [in] base QEO base address + * @param [in] lines resolution lines + */ +static inline void qeo_wave_set_resolution_lines(QEO_Type *base, uint32_t lines) +{ + base->WAVE.RESOLUTION = QEO_WAVE_RESOLUTION_LINES_SET(lines); +} + +/** + * @brief QEO set output type for wave mode + * @param [in] base QEO base address + * @param [in] type qeo_wave_type_t + */ +static inline void qeo_wave_set_output_type(QEO_Type *base, qeo_wave_type_t type) +{ + base->WAVE.MODE = (base->WAVE.MODE & ~QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) | QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(type); +} + +/** + * @brief QEO set saddle type for wave mode + * @param [in] base QEO base address + * @param [in] standard true for standard saddle, false for triangular wave stacking + */ +static inline void qeo_wave_set_saddle_type(QEO_Type *base, bool standard) +{ + if (standard) { + base->WAVE.MODE &= ~QEO_WAVE_MODE_SADDLE_TYPE_MASK; + } else { + base->WAVE.MODE |= QEO_WAVE_MODE_SADDLE_TYPE_MASK; + } +} + +/** + * @brief QEO set phase shift for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] angle left shift angle + */ +static inline void qeo_wave_set_phase_shift(QEO_Type *base, uint8_t index, double angle) +{ + assert((angle >= 0) && (angle <= 360)); + uint32_t val = (uint32_t)(angle * 0x10000U / 360); + base->WAVE.PHASE_SHIFT[index] = QEO_WAVE_PHASE_SHIFT_VAL_SET(val); +} + +/** + * @brief QEO enable vd vq inject for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] vd_val vd value + * @param [in] vq_val vq value + */ +static inline void qeo_wave_enable_vd_vq_inject(QEO_Type *base, uint8_t index, int32_t vd_val, int32_t vq_val) +{ + assert(index < 3); + base->WAVE.MODE |= (1U << (QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK + index)); + base->WAVE.VD_VQ_INJECT[index] = QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SET(vq_val) | QEO_WAVE_VD_VQ_INJECT_VD_VAL_SET(vq_val); +} + +/** + * @brief QEO disable vd vq inject for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + */ +static inline void qeo_wave_disable_vd_vq_inject(QEO_Type *base, uint8_t index) +{ + assert(index < 3); + base->WAVE.MODE &= ~(1U << (QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK + index)); +} + +/** + * @brief QEO load vd vq inject value for wave mode + * @param [in] base QEO base address + */ +static inline void qeo_wave_load_vd_vq(QEO_Type *base) +{ + base->WAVE.VD_VQ_LOAD = QEO_WAVE_VD_VQ_LOAD_LOAD_MASK; +} + +/** + * @brief QEO enable amplitude for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] amp amplitude value + */ +static inline void qeo_wave_enable_amplitude(QEO_Type *base, uint8_t index, double amp) +{ + assert(amp > 0); + uint32_t val = (uint32_t)(amp * (1U << 12U)); + base->WAVE.AMPLITUDE[index] = QEO_WAVE_AMPLITUDE_EN_SCAL_MASK | QEO_WAVE_AMPLITUDE_AMP_VAL_SET(val); +} + +/** + * @brief QEO disable amplitude for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + */ +static inline void qeo_wave_disable_amplitude(QEO_Type *base, uint8_t index) +{ + base->WAVE.AMPLITUDE[index] &= ~QEO_WAVE_AMPLITUDE_EN_SCAL_MASK; +} + +/** + * @brief QEO set mid point shift for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] shift mid point shift value + */ +static inline void qeo_wave_set_mid_point_shift(QEO_Type *base, uint8_t index, double shift) +{ + int32_t val = (int32_t)(shift * (1U << 27U)); + base->WAVE.MID_POINT[index] = QEO_WAVE_MID_POINT_VAL_SET(val); +} + +/** + * @brief QEO set max limmit for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] limit0 limit0 value + * @param [in] limit1 limit1 value + */ +static inline void qeo_wave_set_max_limit(QEO_Type *base, uint8_t index, uint32_t limit0, uint32_t limit1) +{ + base->WAVE.LIMIT[index].MAX = QEO_WAVE_LIMIT_MAX_LIMIT0_SET(limit0) | QEO_WAVE_LIMIT_MAX_LIMIT1_SET(limit1); +} + +/** + * @brief QEO set min limmit for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] limit0 limit0 value + * @param [in] limit1 limit1 value + */ +static inline void qeo_wave_set_min_limit(QEO_Type *base, uint8_t index, uint32_t limit0, uint32_t limit1) +{ + base->WAVE.LIMIT[index].MIN = QEO_WAVE_LIMIT_MIN_LIMIT0_SET(limit0) | QEO_WAVE_LIMIT_MIN_LIMIT1_SET(limit1); +} + +/** + * @brief QEO set deadzone shift for wave mode + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @param [in] shift deadzone shift value + */ +static inline void qeo_wave_set_deadzone_shift(QEO_Type *base, uint8_t index, int16_t shift) +{ + base->WAVE.DEADZONE_SHIFT[index] = QEO_WAVE_DEADZONE_SHIFT_VAL_SET(shift); +} + +/** + * @brief QEO get wave output value + * @param [in] base QEO base address + * @param [in] index wave index(0/1/2) + * @retval wave output value + */ +static inline uint16_t qeo_get_wave_output_val(QEO_Type *base, uint8_t index) +{ + if (index == 0) { + return QEO_DEBUG0_WAVE0_GET(base->DEBUG0); + } else if (index == 1) { + return QEO_DEBUG0_WAVE1_GET(base->DEBUG0); + } else if (index == 2) { + return QEO_DEBUG1_WAVE2_GET(base->DEBUG1); + } + return 0; +} + +/** + * @brief QEO wave get defalut mode config + * @param [in] base QEO base address + * @param [in] config qeo_wave_mode_t + */ +void qeo_wave_get_default_mode_config(QEO_Type *base, qeo_wave_mode_t *config); + +/** + * @brief QEO wave config mode + * @param [in] base QEO base address + * @param [in] config qeo_wave_mode_t + */ +void qeo_wave_config_mode(QEO_Type *base, qeo_wave_mode_t *config); + +/* ABZ API */ +/** + * @brief QEO set resolution lines for ABZ mode + * @param [in] base QEO base address + * @param [in] lines resolution lines + */ +static inline void qeo_abz_set_resolution_lines(QEO_Type *base, uint32_t lines) +{ + base->ABZ.RESOLUTION = QEO_ABZ_RESOLUTION_LINES_SET(lines); +} + +/** + * @brief QEO set phase shift for ABZ mode + * @param [in] base QEO base address + * @param [in] index ABZ index(0/1/2) + * @param [in] angle left shift angle + */ +static inline void qeo_abz_set_phase_shift(QEO_Type *base, uint8_t index, double angle) +{ + assert((angle >= 0) && (angle <= 360)); + uint32_t val = (uint32_t)(angle * 0x10000U / 360); + base->ABZ.PHASE_SHIFT[index] = QEO_ABZ_PHASE_SHIFT_VAL_SET(val); +} + +/** + * @brief QEO set max frequency for ABZ mode + * @param [in] base QEO base address + * @param [in] src_freq QEO(MOTO system) frequency + * @param [in] freq abz signal frequency (A pulse frequency) + * @retval status_success or status_invalid_argument + */ +hpm_stat_t qeo_abz_set_max_frequency(QEO_Type *base, uint32_t src_freq, uint32_t freq); + +/** + * @brief QEO set wdog frequency for ABZ mode + * @param [in] base QEO base address + * @param [in] src_freq QEO(MOTO system) frequency + * @param [in] freq wdog frequency + * @retval status_success or status_invalid_argument + */ +hpm_stat_t qeo_abz_set_wdog_frequency(QEO_Type *base, uint32_t src_freq, uint32_t freq); + +/** + * @brief QEO disable wdog for ABZ mode + * @param [in] base QEO base address + */ +static inline void qeo_abz_disable_wdog(QEO_Type *base) +{ + base->ABZ.MODE &= ~QEO_ABZ_MODE_EN_WDOG_MASK; +} + +/** + * @brief QEO config reverse edge for ABZ mode + * @param [in] base QEO base address + * @param [in] speed_pulse_negedge true for reverse edge point speed pulse's negedge + * false for reverse edge point between speed pulse's posedge and negedge, min period dedicated by the num line_width + * + * @note take effect when ABZ work on qeo_abz_output_pulse_revise mode + */ +static inline void qeo_abz_config_reverse_edge(QEO_Type *base, bool speed_pulse_negedge) +{ + if (speed_pulse_negedge) { + base->ABZ.MODE |= QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK; + } else { + base->ABZ.MODE &= ~QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK; + } +} + +/** + * @brief QEO sync position for ABZ mode + * @param [in] base QEO base address + * @param [in] lines ABZ line counter + * @param [in] sync_pos the position value to be synchronized + */ +void qeo_abz_position_sync(QEO_Type *base, uint32_t lines, uint32_t sync_pos); + +/** + * @brief QEO ABZ get default mode config + * @param [in] base QEO base address + * @param [in] config qeo_abz_mode_t + */ +void qeo_abz_get_default_mode_config(QEO_Type *base, qeo_abz_mode_t *config); + +/** + * @brief QEO ABZ config mode + * @param [in] base QEO base address + * @param [in] config qeo_abz_mode_t + */ +void qeo_abz_config_mode(QEO_Type *base, qeo_abz_mode_t *config); + +/* PWM API */ +/** + * @brief QEO set resolution lines for PWM mode + * @param [in] base QEO base address + * @param [in] lines resolution lines + */ +static inline void qeo_pwm_set_resolution_lines(QEO_Type *base, uint32_t lines) +{ + base->PWM.RESOLUTION = QEO_PWM_RESOLUTION_LINES_SET(lines); +} + +/** + * @brief QEO set phase shift for PWM mode + * @param [in] base QEO base address + * @param [in] index PWM index(0/1/2/3) + * @param [in] angle left shift angle + */ +static inline void qeo_pwm_set_phase_shift(QEO_Type *base, uint8_t index, double angle) +{ + assert((angle >= 0) && (angle <= 360)); + uint32_t val = (uint32_t)(angle * 0x10000U / 360); + base->PWM.PHASE_SHIFT[index] = QEO_PWM_PHASE_SHIFT_VAL_SET(val); +} + +/** + * @brief QEO PWM check if it is triggered by hardware to enter safety mode + * + * @note This bit is only valid if the hardware trigger source has not been cleared + * + * @param [in] base QEO base address + * @retval true or false + */ +static inline bool qeo_pwm_check_hardware_trig_safety(QEO_Type *base) +{ + return ((base->STATUS & QEO_STATUS_PWM_SAFETY_MASK) != 0) ? true : false; +} + +/** + * @brief QEO PWM select phase table + * @param [in] base QEO base address + * @param [in] positive true for using positive phase table, false for using negative phase table + */ +static inline void qeo_pwm_select_phase_table(QEO_Type *base, bool positive) +{ + if (positive) { + base->PWM.MODE &= ~QEO_PWM_MODE_REVISE_UP_DN_MASK; + } else { + base->PWM.MODE |= QEO_PWM_MODE_REVISE_UP_DN_MASK; + } +} + +/** + * @brief QEO PWM enter safety mode by software + * + * @note call qeo_pwm_software_exit_safety to exit safety mode + * + * @param [in] base QEO base address + */ +static inline void qeo_pwm_software_enter_safety(QEO_Type *base) +{ + base->PWM.MODE |= QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK; +} + +/** + * @brief QEO PWM exit safety mode by software + * @param [in] base QEO base address + */ +static inline void qeo_pwm_software_exit_safety(QEO_Type *base) +{ + base->PWM.MODE &= ~QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK; +} + +/** + * @brief QEO PWM get default mode config + * @param [in] base QEO base address + * @param [in] config qeo_pwm_mode_t + */ +void qeo_pwm_get_default_mode_config(QEO_Type *base, qeo_pwm_mode_t *config); + +/** + * @brief QEO PWM config mode + * @param [in] base QEO base address + * @param [in] config qeo_pwm_mode_t + */ +void qeo_pwm_config_mode(QEO_Type *base, qeo_pwm_mode_t *config); + +/** + * @brief QEO PWM get default safety table + * @param [in] base QEO base address + * @param [in] table qeo_pwm_safety_output_table_t + */ +void qeo_pwm_get_default_safety_table_config(QEO_Type *base, qeo_pwm_safety_output_table_t *table); + +/** + * @brief QEO PWM get default phase table + * @param [in] base QEO base address + * @param [in] table qeo_pwm_phase_output_table_t + */ +void qeo_pwm_get_default_phase_table_config(QEO_Type *base, qeo_pwm_phase_output_table_t *table); + +/** + * @brief QEO PWM config safety table + * @param [in] base QEO base address + * @param [in] table qeo_pwm_safety_output_table_t + */ +void qeo_pwm_config_safety_table(QEO_Type *base, qeo_pwm_safety_output_table_t *table); + +/** + * @brief QEO PWM onfig phase table + * @param [in] base QEO base address + * @param [in] table qeo_pwm_phase_output_table_t + */ +void qeo_pwm_config_phase_table(QEO_Type *base, uint8_t index, qeo_pwm_phase_output_table_t *table); + +/** + * @brief QEO enable software position inject + * @param [in] base QEO base address + */ +static inline void qeo_enable_software_position_inject(QEO_Type *base) +{ + base->POSTION_SEL |= QEO_POSTION_SEL_POSTION_SEL_MASK; +} + +/** + * @brief QEO software inject position + * @param [in] base QEO base address + * @param [in] base position value + */ +static inline void qeo_software_position_inject(QEO_Type *base, uint32_t position) +{ + base->POSTION_SOFTWARE = QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET(position); +} + +/** + * @brief QEO disable software position inject, QEO will using position from hardware + * @param [in] base QEO base address + */ +static inline void qeo_disable_software_position_inject(QEO_Type *base) +{ + base->POSTION_SEL &= ~QEO_POSTION_SEL_POSTION_SEL_MASK; +} + +/** + * @brief QEO check calculate finish status + * @param [in] base QEO base address + * @retval true or false + */ +static inline bool qeo_check_calculate_finish(QEO_Type *base) +{ + return (QEO_DEBUG1_QEO_FINISH_GET(base->DEBUG1) != 0) ? true : false; +} + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_QEO_DRV_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_rdc_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_rdc_drv.h new file mode 100644 index 00000000..1abbb55d --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_rdc_drv.h @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_RDC_DRV_H +#define HPM_RDC_DRV_H + +#include "hpm_common.h" +#include "hpm_rdc_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief RDC driver APIs + * @defgroup rdc_interface RDC driver APIs + * @ingroup rdc_interfaces + * @{ + */ + + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @name Initialization and Deinitialization + * @{ + */ + + +/** + * @brief Rdc output precision, use n points to form an excitation signal period. + * + */ +typedef enum rdc_output_precision { + rdc_output_precision_4_point = 0, + rdc_output_precision_8_point = 1, + rdc_output_precision_16_point = 2, + rdc_output_precision_32_point = 3, + rdc_output_precision_64_point = 4, + rdc_output_precision_128_point = 5, + rdc_output_precision_256_point = 6, + rdc_output_precision_512_point = 7, + rdc_output_precision_1024_point = 8, +} rdc_output_precision_t; + +/** + * @brief Pwm output period in samples + * + */ +typedef enum rdc_output_pwm_period { + rdc_output_pwm_period_1_sample = 0, + rdc_output_pwm_period_2_sample, + rdc_output_pwm_period_3_sample, + rdc_output_pwm_period_4_sample, + rdc_output_pwm_period_5_sample, + rdc_output_pwm_period_6_sample, + rdc_output_pwm_period_7_sample, + rdc_output_pwm_period_8_sample, + rdc_output_pwm_period_9_sample, + rdc_output_pwm_period_10_sample, + rdc_output_pwm_period_11_sample, + rdc_output_pwm_period_12_sample, + rdc_output_pwm_period_13_sample, + rdc_output_pwm_period_14_sample, + rdc_output_pwm_period_15_sample, + rdc_output_pwm_period_16_sample, +} rdc_output_pwm_period_t; + + + +/** + * @brief Rdc output mode + * + */ +typedef enum rdc_output_mode { + rdc_output_dac, + rdc_output_pwm +} rdc_output_mode_t; + +/** + * @brief Synchronize output trig adc position + * + */ +typedef enum rdc_sync_out_src { + rdc_sync_out_exc_0_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(0), + rdc_sync_out_exc_90_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(1), + rdc_sync_out_exc_180_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(2), + rdc_sync_out_exc_270_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(3), + rdc_sync_out_max = RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK, + rdc_sync_out_min = RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK, +} rdc_sync_out_src_t; + +/** + * @brief Select reference point of rectify signal + * + */ +typedef enum rdc_rectify_signal { + rdc_rectify_signal_exc_0_ph = 0, + rdc_rectify_signal_exc_90_ph = 1, + rdc_rectify_signal_exc_180_ph = 2, + rdc_rectify_signal_exc_270_ph = 3, + rdc_rectify_signal_external = 4, + rdc_rectify_signal_external_invert = 5, +} rdc_rectify_signal_t; + +/** + * @brief Time stamp selection for accumulation + * + */ +typedef enum rdc_acc_stamp_time { + rdc_acc_stamp_end_of_acc = 0, /**< End of accumulation */ + rdc_acc_stamp_start_of_acc = 1, /**< Start of accumulation */ + rdc_acc_stamp_center_of_acc = 2, /**< Center of accumulation */ +} rdc_acc_stamp_time_t; + +/** + * @brief Rdc trigger out channel 0 or channel 1 + * + */ +typedef enum rdc_output_trig_chn { + trigger_out_0 = 0, + trigger_out_1 = 1 +} rdc_output_trig_chn_t; + + +/** + * @brief Rdc input channel + * + */ +typedef enum rdc_input_acc_chn { + rdc_acc_chn_i = 0, + rdc_acc_chn_q = 1 +} rdc_input_acc_chn_t; + +/** + * @brief Rdc status flags + * + */ +typedef enum rdc_interrupt_stat { + acc_vld_i_stat = RDC_INT_EN_ACC_VLD_I_EN_MASK, + acc_vld_q_stat = RDC_INT_EN_ACC_VLD_Q_EN_MASK, + rising_delay_i_stat = RDC_INT_EN_RISING_DELAY_I_EN_MASK, + falling_delay_i_stat = RDC_INT_EN_FALLING_DELAY_I_EN_MASK, + rising_delay_q_stat = RDC_INT_EN_RISING_DELAY_Q_EN_MASK, + falling_delay_q_stat = RDC_INT_EN_FALLING_DELAY_Q_EN_MASK, + sample_rising_i_stat = RDC_INT_EN_SAMPLE_RISING_I_EN_MASK, + sample_falling_i_stat = RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK, + sample_rising_q_stat = RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK, + sample_falling_q_stat = RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK, + acc_vld_i_ovh_stat = RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK, + acc_vld_q_ovh_stat = RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK, + acc_vld_i_ovl_stat = RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK, + acc_vld_q_ovl_stat = RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK, + acc_amp_ovh_stat = RDC_INT_EN_ACC_AMP_OVH_EN_MASK, + acc_amp_ovl_stat = RDC_INT_EN_ACC_AMP_OVL_EN_MASK, +} rdc_interrupt_stat_t; + +/** + * @brief Rdc output configuration + * + */ +typedef struct rdc_output_cfg { + rdc_output_mode_t mode; /**< pwm or dac */ + uint32_t excitation_period_cycle; /**< The period of the excitation signal, in cycles */ + rdc_output_precision_t excitation_precision; /**< Excitation signal precision */ + rdc_output_pwm_period_t pwm_period; /**< Pwm period in samples */ + bool output_swap; /**< Swap output of PWM and DAC */ + int32_t amp_offset; /**< Offset for excitation, signed value*/ + uint16_t amp_man; /**< Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp */ + uint16_t amp_exp; /**< Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp */ + bool pwm_dither_enable; /**< Enable dither of pwm */ + bool pwm_exc_p_low_active; /**< Polarity of exc_p signal */ + bool pwm_exc_n_low_active; /**< Polarity of exc_n signal */ + bool trig_by_hw; /**< Hardware triggered excitation signal generation. Software triggering is required after shutdown */ + uint32_t hw_trig_delay; /**< Trigger in delay timming in bus cycle from rising edge of trigger signal */ + uint8_t dac_chn_i_sel; /**< Output channel selection for i_channel */ + uint8_t dac_chn_q_sel; /**< Output channel selection for q_channel */ + uint8_t pwm_deadzone_p; /**< Exc_p dead zone in clock cycle before swap */ + uint8_t pwm_deadzone_n; /**< Exc_n dead zone in clock cycle before swap */ +} rdc_output_cfg_t; + + +/** + * @brief Rdc input configuration + * + */ +typedef struct rdc_input_cfg { + rdc_rectify_signal_t rectify_signal_sel; /**< Select reference point of rectify signal */ + uint8_t acc_cycle_len; /**< Accumulate time, support on the fly change */ + rdc_acc_stamp_time_t acc_stamp; /**< Time stamp selection for accumulation */ + uint32_t acc_input_chn_i; /**< Input channel selection for i_channel */ + uint32_t acc_input_port_i; /**< Input port selection for i_channel */ + uint32_t acc_input_chn_q; /**< Input channel selection for q_channel */ + uint32_t acc_input_port_q; /**< Input port selection for q_channel */ +} rdc_input_cfg_t; + +/** + * @brief Accumulated configuration information + * + */ +typedef struct rdc_acc_cfg { + struct { + uint16_t continue_edge_num: 3; /**< Filtering val: 1 - 8 */ + uint16_t edge_distance: 6; /**< Minimum distance between two edges 0-63 */ + }; + uint8_t right_shift_without_sign; /**< Right shift without sign bit */ + bool error_data_remove; /**< Toxic accumulation data be removed */ + uint32_t exc_carrier_period; /**< The num in clock cycle for period of excitation 0-NULL others-cycles */ + uint32_t sync_delay_i; /**< Delay in clock cycle for synchronous signal, the value should less than half of exc_period.exc_period. */ + uint32_t sync_delay_q; /**< Delay in clock cycle for synchronous signal, the value should less than half of exc_period.exc_period. */ + uint32_t amp_max; /**< The maximum of acc amplitude */ + uint32_t amp_min; /**< The minimum of acc amplitude */ +} rdc_acc_cfg_t; + +/** @} */ + +/** + * @name RDC Control + * @{ + */ + +/** + * @brief Rdc output configuration, can be configured pwm output or dac output + * + * @param ptr @ref RDC_Type base + * @param cfg @ref rdc_output_cfg_t + */ +void rdc_output_config(RDC_Type *ptr, rdc_output_cfg_t *cfg); + +/** + * @brief Rdc input configuration, configuration of adc signal source and calculation parameters + * + * @param ptr @ref RDC_Type base + * @param cfg @ref rdc_input_cfg_t + */ +void rdc_input_config(RDC_Type *ptr, rdc_input_cfg_t *cfg); + +/** + * @brief Configuration accumulate time, support on the fly change + * + * @param ptr @ref RDC_Type base + * @param len accumulate time 0-255 + */ +static inline void rdc_set_acc_len(RDC_Type *ptr, uint8_t len) +{ + ptr->RDC_CTL = (ptr->RDC_CTL & (~RDC_RDC_CTL_ACC_LEN_MASK)) + | RDC_RDC_CTL_ACC_LEN_SET(len); +} + +/** + * @brief Enable accumulate calculation function + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_acc_enable(RDC_Type *ptr) +{ + ptr->RDC_CTL |= RDC_RDC_CTL_ACC_EN_MASK; +} + +/** + * @brief Disable accumulate calculation function + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_acc_disable(RDC_Type *ptr) +{ + ptr->RDC_CTL &= ~RDC_RDC_CTL_ACC_EN_MASK; +} + +/** + * @brief Get the accumulate value + * + * @param ptr @ref RDC_Type base + * @param chn @ref rdc_input_acc_chn_t + * @return uint32_t accumulate value + */ +uint32_t rdc_get_acc_avl(RDC_Type *ptr, rdc_input_acc_chn_t chn); + +/** + * @brief Output trigger configuration + * Lead time for trigger out0 or out1 from center of low level , this is a signed value + * @param ptr @ref RDC_Type base + * @param chn @ref rdc_output_trig_chn_t + * @param offset lead_time + */ +void rdc_output_trig_offset_config(RDC_Type *ptr, rdc_output_trig_chn_t chn, int32_t offset); + +/** + * @brief Enable output trigger configuration + * + * @param ptr @ref RDC_Type base + * @param chn @ref rdc_output_trig_chn_t + */ +void rdc_output_trig_enable(RDC_Type *ptr, rdc_output_trig_chn_t chn); + +/** + * @brief Disable rdc output trigger configuration + * + * @param ptr @ref RDC_Type base + * @param chn @ref rdc_output_trig_chn_t + */ +void rdc_output_trig_disable(RDC_Type *ptr, rdc_output_trig_chn_t chn); + +/** + * @brief Select output synchornize signal + * + * @param ptr @ref RDC_Type base + * @param sel @ref rdc_sync_out_src_t + */ +static inline void rdc_sync_output_trig_adc_cfg(RDC_Type *ptr, rdc_sync_out_src_t sel) +{ + ptr->SYNC_OUT_CTRL = sel; +} + +/** + * @brief Enable rdc excite signal + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_exc_enable(RDC_Type *ptr) +{ + ptr->RDC_CTL |= RDC_RDC_CTL_EXC_EN_MASK; +} + +/** + * @brief Disable rdc excite signal + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_exc_disable(RDC_Type *ptr) +{ + ptr->RDC_CTL &= ~RDC_RDC_CTL_EXC_EN_MASK; +} + +/** + * @brief Software triggered excitation signal output + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_output_trig_sw(RDC_Type *ptr) +{ + ptr->RDC_CTL |= RDC_RDC_CTL_EXC_START_MASK; +} + +/** + * @brief Get I-phase maximum + * + * @param ptr @ref RDC_Type base + * @retval - other max value + * - -1 illegal data + */ +int32_t rdc_get_i_maxval(RDC_Type *ptr); + +/** + * @brief Clear Maximum + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_clear_i_maxval(RDC_Type *ptr) +{ + ptr->MAX_I = 0; +} + +/** + * @brief Get I-phase minimum + * + * @param ptr @ref RDC_Type base + * @retval - other max value + * - -1 illegal data + */ +int32_t rdc_get_i_minval(RDC_Type *ptr); + +/** + * @brief Clear I-phase minimum + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_clear_i_minval(RDC_Type *ptr) +{ + ptr->MIN_I = 0; +} + +/** + * @brief Set Acc sync delay + * + * @param ptr @ref RDC_Type base + * @param chn @ref rdc_input_acc_chn_t + * @param delay delay tick + */ +void rdc_set_acc_sync_delay(RDC_Type *ptr, rdc_input_acc_chn_t chn, uint32_t delay); + +/** + * @brief Delay bettween the delyed trigger and + * the first pwm pulse in clock cycle + * + * @param ptr @ref RDC_Type base + * @retval delay tick + */ +static inline uint32_t rdc_get_sync_output_delay(RDC_Type *ptr) +{ + return RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_GET(ptr->SYNC_OUT_CTRL); +} + +/** + * @brief Get Q-phase maximum + * + * @param ptr @ref RDC_Type base + * @retval - other max value + * - -1 illegal data + */ +int32_t rdc_get_q_maxval(RDC_Type *ptr); + +/** + * @brief Clear Q-phase maxval + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_clear_q_maxval(RDC_Type *ptr) +{ + ptr->MAX_Q = 0; +} + +/** + * @brief Get Q-phase Minval + * + * @param ptr @ref RDC_Type base + * @retval - other max value + * - -1 illegal data + */ +int32_t rdc_get_q_minval(RDC_Type *ptr); + +/** + * @brief Clear Q-phase Minval + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_clear_q_minval(RDC_Type *ptr) +{ + ptr->MIN_Q = 0; +} + +/** + * @brief The offset setting for edge detection of the i_channel or q_channel + * + * @param ptr @ref RDC_Type base + * @param chn @ref rdc_input_acc_chn_t + * @param offset offset value + */ +void rdc_set_edge_detection_offset(RDC_Type *ptr, rdc_input_acc_chn_t chn, int32_t offset); + +/** + * @brief RDC set accumulate configuration + * + * @param ptr @ref RDC_Type base + * @param cfg @ref rdc_acc_cfg_t + */ +void rdc_set_acc_config(RDC_Type *ptr, rdc_acc_cfg_t *cfg); + +/** + * @brief Get delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data + * + * @param ptr @ref RDC_Type base + * @retval clock cycle + */ +static inline uint32_t rdc_get_rise_delay_i(RDC_Type *ptr) +{ + return RDC_RISE_DELAY_I_RISE_DELAY_GET(ptr->RISE_DELAY_I); +} + +/** + * @brief Get delay in clock cycle between excitation synchrnous signal and fall edge of i_channel data + * + * @param ptr @ref RDC_Type base + * @retval clock cycle + */ +static inline uint32_t rdc_get_fall_delay_i(RDC_Type *ptr) +{ + return RDC_FALL_DELAY_I_FALL_DELAY_GET(ptr->FALL_DELAY_I); +} + +/** + * @brief Get sample value on rising edge of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval clock cycle + */ +static inline uint32_t rdc_get_sample_rise_i(RDC_Type *ptr) +{ + return RDC_SAMPLE_RISE_I_VALUE_GET(ptr->SAMPLE_RISE_I); +} + +/** + * @brief Get sample value on falling edge of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval clock cycle + */ +static inline uint32_t rdc_get_sample_fall_i(RDC_Type *ptr) +{ + return RDC_SAMPLE_FALL_I_VALUE_GET(ptr->SAMPLE_FALL_I); +} + +/** + * @brief Get sample number during the positive of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval counter + */ +static inline uint32_t rdc_get_acc_cnt_positive_i(RDC_Type *ptr) +{ + return RDC_ACC_CNT_I_CNT_POS_GET(ptr->ACC_CNT_I); +} + +/** + * @brief Get sample number during the negtive of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval counter + */ +static inline uint32_t rdc_get_acc_cnt_negative_i(RDC_Type *ptr) +{ + return RDC_ACC_CNT_I_CNT_POS_GET(ptr->ACC_CNT_I); +} + +/** + * @brief Get Negative sample counter during positive rectify signal + * + * @param ptr @ref RDC_Type base + * @retval counter + */ +static inline uint32_t rdc_get_sign_cnt_poitive_i(RDC_Type *ptr) +{ + return RDC_SIGN_CNT_I_CNT_POS_GET(ptr->SIGN_CNT_I); +} + +/** + * @brief Get Positive sample counter during negative rectify signal + * + * @param ptr @ref RDC_Type base + * @retval counter + */ +static inline uint32_t rdc_get_sign_cnt_negative_i(RDC_Type *ptr) +{ + return RDC_SIGN_CNT_I_CNT_NEG_GET(ptr->SIGN_CNT_I); +} + +/** + * @brief Get delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data + * + * @param ptr @ref RDC_Type base + * @retval cycles + */ +static inline uint32_t rdc_get_rise_delay_q(RDC_Type *ptr) +{ + return RDC_RISE_DELAY_Q_RISE_DELAY_GET(ptr->RISE_DELAY_Q); +} + +/** + * @brief Get delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data + * + * @param ptr @ref RDC_Type base + * @retval cycles + */ +static inline uint32_t rdc_get_fall_delay_q(RDC_Type *ptr) +{ + return RDC_FALL_DELAY_Q_FALL_DELAY_GET(ptr->FALL_DELAY_Q); +} + +/** + * @brief Get q channel sample value on rising edge of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval cycles + */ +static inline uint32_t rdc_get_sample_rise_q(RDC_Type *ptr) +{ + return RDC_SAMPLE_RISE_Q_VALUE_GET(ptr->SAMPLE_RISE_Q); +} + +/** + * @brief Get q channel sample value on falling edge of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval cycles + */ +static inline uint32_t rdc_get_sample_fall_q(RDC_Type *ptr) +{ + return RDC_SAMPLE_FALL_Q_VALUE_GET(ptr->SAMPLE_FALL_Q); +} + +/** + * @brief Get q channel sample number during the positive of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval number + */ +static inline uint32_t rdc_get_acc_cnt_positive_q(RDC_Type *ptr) +{ + return RDC_ACC_CNT_Q_CNT_POS_GET(ptr->ACC_CNT_Q); +} + +/** + * @brief Get q channel sample number during the negtive of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval number + */ +static inline uint32_t rdc_get_acc_cnt_negative_q(RDC_Type *ptr) +{ + return RDC_ACC_CNT_Q_CNT_POS_GET(ptr->ACC_CNT_Q); +} + +/** + * @brief Get q channel negative sample counter during positive rectify signal + * + * @param ptr @ref RDC_Type base + * @retval counter + */ +static inline uint32_t rdc_get_sign_cnt_poitive_q(RDC_Type *ptr) +{ + return RDC_SIGN_CNT_Q_CNT_POS_GET(ptr->SIGN_CNT_Q); +} + +/** + * @brief Get q channel sample number during the negtive of rectify signal + * + * @param ptr @ref RDC_Type base + * @retval counter + */ +static inline uint32_t rdc_get_sign_cnt_negative_q(RDC_Type *ptr) +{ + return RDC_SIGN_CNT_Q_CNT_NEG_GET(ptr->SIGN_CNT_Q); +} + +/** + * @brief Enables configured interrupts + * + * @param ptr @ref RDC_Type base + * @param status @ref rdc_interrupt_stat_t + */ +static inline void rdc_interrupt_config(RDC_Type *ptr, uint32_t status) +{ + ptr->INT_EN |= status; +} + +/** + * @brief Clear interrupts configured + * + * @param ptr @ref RDC_Type base + * @param status @ref rdc_interrupt_stat_t + */ +static inline void rdc_interrupt_reset_config(RDC_Type *ptr, uint32_t status) +{ + ptr->INT_EN &= ~status; +} + +/** + * @brief Enable rdc interrupt + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_interrupt_enable(RDC_Type *ptr) +{ + ptr->INT_EN |= RDC_INT_EN_INT_EN_MASK; +} + +/** + * @brief Disable rdc interrupt + * + * @param ptr @ref RDC_Type base + */ +static inline void rdc_interrupt_disable(RDC_Type *ptr) +{ + ptr->INT_EN &= ~RDC_INT_EN_INT_EN_MASK; +} + +/** + * @brief Clear interrupt flag bits + * + * @param ptr @ref RDC_Type base + * @param mask @ref rdc_interrupt_stat_t + */ +static inline void rdc_interrupt_clear_flag_bits(RDC_Type *ptr, uint32_t mask) +{ + ptr->ADC_INT_STATE &= mask; +} + +/** + * @brief Get the interrupt status object + * + * @param ptr @ref RDC_Type base + * @retval @ref rdc_interrupt_stat_t + */ +static inline uint32_t get_interrupt_status(RDC_Type *ptr) +{ + return ptr->ADC_INT_STATE; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +/** @} */ +#endif /* HPM_ADC12_DRV_H */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h index 90bce46e..4339cb01 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h @@ -17,7 +17,7 @@ #include "hpm_common.h" #include "hpm_rtc_regs.h" -#include +#include "sys/time.h" /** * @brief RTC alarm configuration @@ -70,6 +70,15 @@ hpm_stat_t rtc_config_alarm(RTC_Type *base, rtc_alarm_config_t *config); */ time_t rtc_get_time(RTC_Type *base); + +/** + * @brief Get accurate time return by RTC module + * @param [in] base RTC base address + * + * @return accurate time(including second and subsecond) + */ +struct timeval rtc_get_timeval(RTC_Type *base); + /** * @brief Enable RTC alarm interrupt * @param [in] base RTC base address @@ -94,7 +103,7 @@ static inline void rtc_enable_alarm_interrupt(RTC_Type *base, uint32_t index, bo } /** - * @brief Clear RTC alarm flag + * @brief Clear RTC alarm flag based on alarm index * @param [in] base RTC base address * @param [in] index RTC alarm index, valid value is 0 or 1 */ @@ -108,6 +117,16 @@ static inline void rtc_clear_alarm_flag(RTC_Type *base, uint32_t index) base->ALARM_FLAG = mask; } +/** + * @brief Clear RTC alarm flags based on flag masks + * @param [in] base RTC base address + * @param [in] masks RTC alarm masks + */ +static inline void rtc_clear_alarm_flags(RTC_Type *base, uint32_t masks) +{ + base->ALARM_FLAG = masks; +} + /** * @brief Check whether RTC alarm flag is set or not * @param [in] base RTC base address @@ -124,6 +143,15 @@ static inline bool rtc_is_alarm_flag_asserted(RTC_Type *base, uint32_t index) return IS_HPM_BITMASK_SET(base->ALARM_FLAG, mask); } +/** + * @brief Get the RTC alarm flags + * @param [in] base RTC base address + * @return RTC alarm flags + */ +static inline uint32_t rtc_get_alarm_flags(RTC_Type *base) +{ + return base->ALARM_FLAG; +} #ifdef __cplusplus } diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h index 759752a4..60bf00c8 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h @@ -39,8 +39,8 @@ typedef enum { } sdm_filter_type_t; typedef struct { - bool clk_signal_sync; - bool data_signal_sync; + uint8_t clk_signal_sync; /* clk sync for channel */ + uint8_t data_signal_sync; /* data sync for channel */ bool interrupt_en; } sdm_control_t; diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_sei_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_sei_drv.h new file mode 100644 index 00000000..8eb323d2 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_sei_drv.h @@ -0,0 +1,1009 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SEI_DRV_H +#define HPM_SEI_DRV_H + +#include "hpm_common.h" +#include "hpm_sei_regs.h" +#include "hpm_soc_feature.h" + +/** + * @brief sei arming action + */ +typedef enum { + sei_arming_direct_exec = 0, + sei_arming_wait_trigger +} sei_arming_mode_t; + +/** + * @brief sei watchdog action + */ +typedef enum { + sei_wdg_exec_next_instr = 0, + sei_wdg_exec_exception_instr +} sei_wdg_action_t; + +/** + * @brief sei transfer mode + */ +typedef enum { + sei_synchronous_master_mode = 0, + sei_synchronous_slave_mode, + sei_asynchronous_mode +} sei_tranceiver_mode_t; + +/** + * @brief sei asynchronous mode parity + */ +typedef enum { + sei_asynchronous_parity_even = 0, + sei_asynchronous_parity_odd +} sei_asynchronous_parity_t; + +/** + * @brief sei ilde state + */ +typedef enum { + sei_idle_low_state = 0, + sei_idle_high_state, +} sei_idle_state_t; + +/** + * @brief sei data mode + */ +typedef enum { + sei_data_mode = 0, + sei_check_mode, + sei_crc_mode +} sei_data_mode_t; + +/** + * @brief sei data bit order + */ +typedef enum { + sei_bit_lsb_first = 0, + sei_bit_msb_first +} sei_data_bit_order_t; + +/** + * @brief sei data word order + */ +typedef enum { + sei_word_nonreverse = 0, + sei_word_reverse +} sei_data_word_order_t; + +/** + * @brief sei state transition condition + */ +typedef enum { + sei_state_tran_condition_high_match = 0, + sei_state_tran_condition_low_dismatch, + sei_state_tran_condition_rise_entry, + sei_state_tran_condition_fall_leave +} sei_state_tran_condition_t; + +/** + * @brief sei trig in type + */ +typedef enum { + sei_trig_in0 = 0, + sei_trig_in1, + sei_trig_in_period, + sei_trig_in_soft +} sei_trig_in_type_t; /**< trig input type */ + +/** + * @brief sei irq event + */ +typedef enum { + sei_irq_stall_event = SEI_CTRL_IRQ_INT_FLAG_STALL_MASK, + sei_irq_execpt_event = SEI_CTRL_IRQ_INT_FLAG_EXECPT_MASK, + sei_irq_wdog_event = SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK, + sei_irq_instr_ptr0_start_event = SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK, + sei_irq_instr_ptr1_start_event = SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK, + sei_irq_instr_value0_start_event = SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK, + sei_irq_instr_value1_start_event = SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK, + sei_irq_instr_ptr0_end_event = SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK, + sei_irq_instr_ptr1_end_event = SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK, + sei_irq_instr_value0_end_event = SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK, + sei_irq_instr_value1_end_event = SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK, + sei_irq_trx_err_event = SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK, + sei_irq_timeout_event = SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK, + sei_irq_latch0_event = SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK, + sei_irq_latch1_event = SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK, + sei_irq_latch2_event = SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK, + sei_irq_latch3_event = SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK, + sei_irq_sample_err_event = SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK, + sei_irq_trig0_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK, + sei_irq_trig1_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK, + sei_irq_trig2_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK, + sei_irq_trig3_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK, + sei_irq_trig0_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK, + sei_irq_trig1_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK, + sei_irq_trig2_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK, + sei_irq_trig3_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK, +} sei_irq_event_t; /**< irq event type */ + +/** + * @brief sei select command or data + */ +#define SEI_SELECT_CMD true /**< select cmd */ +#define SEI_SELECT_DATA false /**< select data */ + +/** + * @brief sei instruction operation command + */ +#define SEI_INSTR_OP_HALT 0u /**< op halt */ +#define SEI_INSTR_OP_JUMP 1u /**< op jump */ +#define SEI_INSTR_OP_SEND_WDG 2u /**< op send with watchdog */ +#define SEI_INSTR_OP_SEND 3u /**< op send */ +#define SEI_INSTR_OP_WAIT_WDG 4u /**< op wait with watchdog */ +#define SEI_INSTR_OP_WAIT 5u /**< op wait */ +#define SEI_INSTR_OP_RECV_WDG 6u /**< op recv with watchdog */ +#define SEI_INSTR_OP_RECV 7u /**< op recv */ + +/** + * @brief sei instruction synchronous master clock type + */ +#define SEI_INSTR_M_CK_LOW 0u /**< clock low */ +#define SEI_INSTR_M_CK_RISE_FALL 1u /**< clock rise fall */ +#define SEI_INSTR_M_CK_FALL_RISE 2u /**< clock fall rise */ +#define SEI_INSTR_M_CK_HIGH 3u /**< clock high */ + +/** + * @brief sei instruction synchronous slave clock type + */ +#define SEI_INSTR_S_CK_DEFAULT 0u /**< default */ +#define SEI_INSTR_S_CK_TRX_EXCH 1u /**< rx tx exchange */ +#define SEI_INSTR_S_CK_TIMEOUT_EN 2u /**< enable timeout */ +#define SEI_INSTR_S_CK_TRX_EXCH_TIMEOUT_EN 3u /**< rx tx exchange and enable timeout */ + +/** + * @brief sei instruction jump intructions index + */ +#define SEI_JUMP_INIT_INSTR_IDX 0x00u /**< jump init instr index */ +#define SEI_JUMP_WDG_INSTR_IDX 0x01u /**< jump watchdog instr index */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX0 0x10u /**< jump command table instr ptr0 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX1 0x11u /**< jump command table instr ptr1 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX2 0x12u /**< jump command table instr ptr2 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX3 0x13u /**< jump command table instr ptr3 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX4 0x14u /**< jump command table instr ptr4 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX5 0x15u /**< jump command table instr ptr5 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX6 0x16u /**< jump command table instr ptr6 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX7 0x17u /**< jump command table instr ptr7 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX8 0x18u /**< jump command table instr ptr8 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX9 0x19u /**< jump command table instr ptr9 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX10 0x1Au /**< jump command table instr ptr10 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX11 0x1Bu /**< jump command table instr ptr11 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX12 0x1Cu /**< jump command table instr ptr12 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX13 0x1Du /**< jump command table instr ptr13 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX14 0x1Eu /**< jump command table instr ptr14 */ +#define SEI_JUMP_CMD_TABLE_INSTR_IDX15 0x1Fu /**< jump command table instr ptr15 */ + +/** + * @brief sei engine config structure + */ +typedef struct { + sei_arming_mode_t arming_mode; + uint8_t data_cdm_idx; + uint8_t data_base_idx; + uint8_t init_instr_idx; + bool wdg_enable; + sei_wdg_action_t wdg_action; + uint8_t wdg_instr_idx; + uint16_t wdg_time; +} sei_engine_config_t; /**< engine config struct */ + +/** + * @brief sei tranceiver synchronous master mode config structure + */ +typedef struct { + bool data_idle_high_z; + sei_idle_state_t data_idle_state; + bool clock_idle_high_z; + sei_idle_state_t clock_idle_state; + uint32_t baudrate; +} sei_tranceiver_synchronous_master_config_t; /**< tranceiver synchronous master config struct */ + +/** + * @brief sei tranceiver synchronous master mode config structure + */ +typedef struct { + bool data_idle_high_z; + sei_idle_state_t data_idle_state; + bool clock_idle_high_z; + sei_idle_state_t clock_idle_state; + uint32_t max_baudrate; + uint16_t ck0_timeout_us; + uint16_t ck1_timeout_us; +} sei_tranceiver_synchronous_slave_config_t; /**< tranceiver synchronous slave config struct */ + +/** + * @brief sei tranceiver asynchronous mode config structure + */ +typedef struct { + uint8_t wait_len; + uint8_t data_len; + bool parity_enable; + sei_asynchronous_parity_t parity; + bool data_idle_high_z; + sei_idle_state_t data_idle_state; + uint32_t baudrate; +} sei_tranceiver_asynchronous_config_t; /**< tranceiver asynchronous config struct */ + +/** + * @brief sei tranceiver config structure + */ +typedef struct { + sei_tranceiver_mode_t mode; + bool tri_sample; + uint32_t src_clk_freq; + sei_tranceiver_synchronous_master_config_t synchronous_master_config; + sei_tranceiver_synchronous_slave_config_t synchronous_slave_config; + sei_tranceiver_asynchronous_config_t asynchronous_config; +} sei_tranceiver_config_t; /**< tranceiver config struct */ + +/** + * @brief sei trigger input config structure + */ +typedef struct { + bool trig_in0_enable; + uint8_t trig_in0_select; + bool trig_in1_enable; + uint8_t trig_in1_select; + bool trig_period_enable; + sei_arming_mode_t trig_period_arming_mode; + bool trig_period_sync_enable; + uint8_t trig_period_sync_select; + uint32_t trig_period_time; +} sei_trigger_input_config_t; /**< trigger input config struct */ + +/** + * @brief sei trigger output config structure + */ +typedef struct { + uint8_t src_latch_select; + bool trig_out_enable; + uint8_t trig_out_select; +} sei_trigger_output_config_t; /**< trigger output config struct */ + +/** + * @brief sei data format config structure + */ +typedef struct { + sei_data_mode_t mode; + bool signed_flag; + sei_data_bit_order_t bit_order; + sei_data_word_order_t word_order; + uint8_t word_len; + bool crc_invert; + bool crc_shift_mode; + uint8_t crc_len; + uint8_t last_bit; + uint8_t first_bit; + uint8_t max_bit; + uint8_t min_bit; + uint32_t gold_value; + uint32_t crc_init_value; + uint32_t crc_poly; +} sei_data_format_config_t; /**< cmd or data format config struct */ + +/** + * @brief sei command table config structure + */ +typedef struct { + uint32_t cmd_min_value; + uint32_t cmd_max_value; + uint32_t cmd_mask_value; + uint8_t instr_idx[16]; +} sei_command_table_config_t; /**< cmd table config struct */ + +/** + * @brief sei state transition config structure + */ +typedef struct { + bool disable_instr_ptr_check; + sei_state_tran_condition_t instr_ptr_cfg; + uint8_t instr_ptr_value; + bool disable_clk_check; + sei_state_tran_condition_t clk_cfg; + bool disable_txd_check; + sei_state_tran_condition_t txd_cfg; + bool disable_rxd_check; + sei_state_tran_condition_t rxd_cfg; + bool disable_timeout_check; + sei_state_tran_condition_t timeout_cfg; +} sei_state_transition_config_t; /**< state transition config struct */ + +/** + * @brief sei state transition latch config structure + */ +typedef struct { + bool enable; + uint8_t output_select; + uint16_t delay; +} sei_state_transition_latch_config_t; /**< state transition latch config struct */ + +/** + * @brief sei sample config structure + */ +typedef struct { + uint8_t acc_data_idx; + uint8_t spd_data_idx; + uint8_t rev_data_idx; + uint8_t pos_data_idx; + bool acc_data_use_rx; /**< true - use rx data, false - use override data */ + bool spd_data_use_rx; /**< true - use rx data, false - use override data */ + bool rev_data_use_rx; /**< true - use rx data, false - use override data */ + bool pos_data_use_rx; /**< true - use rx data, false - use override data */ + uint8_t latch_select; + bool sample_once; + uint16_t sample_window; + uint32_t data_register_select; +} sei_sample_config_t; /**< sample config struct */ + +/** + * @brief sei update config structure + */ +typedef struct { + uint8_t acc_data_idx; + uint8_t spd_data_idx; + uint8_t rev_data_idx; + uint8_t pos_data_idx; + bool acc_data_use_rx; /**< true - use rx data, false - use override data */ + bool spd_data_use_rx; /**< true - use rx data, false - use override data */ + bool rev_data_use_rx; /**< true - use rx data, false - use override data */ + bool pos_data_use_rx; /**< true - use rx data, false - use override data */ + bool time_use_override; /**< true - use override data, false - use timestamp data */ + bool update_on_err; + uint8_t latch_select; + uint32_t data_register_select; +} sei_update_config_t; /**< update config struct */ + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Set the SEI engine enable or disable + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] enable enable or disable + * @arg true enable + * @arg false disable + */ +static inline void sei_set_engine_enable(SEI_Type *ptr, uint8_t idx, bool enable) +{ + if (enable) { + ptr->CTRL[idx].ENGINE.CTRL |= SEI_CTRL_ENGINE_CTRL_ENABLE_MASK; + } else { + ptr->CTRL[idx].ENGINE.CTRL &= ~SEI_CTRL_ENGINE_CTRL_ENABLE_MASK; + } +} + +/** + * @brief Rewind the SEI engine + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + */ +static inline void sei_set_engine_rewind(SEI_Type *ptr, uint8_t idx) +{ + ptr->CTRL[idx].ENGINE.CTRL |= SEI_CTRL_ENGINE_CTRL_REWIND_MASK; +} + +/** + * @brief Set the SEI trigger input trig in0 enable or disable + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] enable enable or disable + * @arg true enable + * @arg false disable + */ +static inline void sei_set_trig_input_in0_enable(SEI_Type *ptr, uint8_t idx, bool enable) +{ + if (enable) { + ptr->CTRL[idx].TRG.IN_CFG |= SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK; + } else { + ptr->CTRL[idx].TRG.IN_CFG &= ~SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK; + } +} + +/** + * @brief Set the SEI trigger input trig in1 enable or disable + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] enable enable or disable + * @arg true enable + * @arg false disable + */ +static inline void sei_set_trig_input_in1_enable(SEI_Type *ptr, uint8_t idx, bool enable) +{ + if (enable) { + ptr->CTRL[idx].TRG.IN_CFG |= SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK; + } else { + ptr->CTRL[idx].TRG.IN_CFG &= ~SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK; + } +} + +/** + * @brief Set the SEI trigger input period enable or disable + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] enable enable or disable + * @arg true enable + * @arg false disable + */ +static inline void sei_set_trig_input_period_enable(SEI_Type *ptr, uint8_t idx, bool enable) +{ + if (enable) { + ptr->CTRL[idx].TRG.IN_CFG |= SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK; + } else { + ptr->CTRL[idx].TRG.IN_CFG &= ~SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK; + } +} + +/** + * @brief Set the SEI trigger input soft enable or disable + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] enable enable or disable + * @arg true enable + * @arg false disable + */ +static inline void sei_set_trig_input_soft_enable(SEI_Type *ptr, uint8_t idx) +{ + ptr->CTRL[idx].TRG.SW |= SEI_CTRL_TRG_SW_SOFT_MASK; +} + +/** + * @brief Set the SEI trigger input command value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] type trigger input type @ref sei_trig_in_type_t + * @param [in] data command data + */ +static inline void sei_set_trig_input_command_value(SEI_Type *ptr, uint8_t idx, sei_trig_in_type_t type, uint32_t data) +{ + ptr->CTRL[idx].TRG_TABLE.CMD[type] = data; +} + +/** + * @brief Get the SEI trigger input time + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] type trigger input type @ref sei_trig_in_type_t + * @retval trigger input time + */ +static inline uint32_t sei_get_trig_input_time(SEI_Type *ptr, uint8_t idx, sei_trig_in_type_t type) +{ + return ptr->CTRL[idx].TRG_TABLE.TIME[type]; +} + +/** + * @brief Get the SEI latch time + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] latch_idx + * @arg SEI_LATCH_0 + * @arg SEI_LATCH_1 + * @arg SEI_LATCH_2 + * @arg SEI_LATCH_3 + * @retval latch time + */ +static inline uint32_t sei_get_latch_time(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx) +{ + return ptr->CTRL[idx].LATCH[latch_idx].TIME; +} + +/** + * @brief Set the SEI tranceiver rx point + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] point rx point value + */ +static inline void sei_set_xcvr_rx_point(SEI_Type *ptr, uint8_t idx, uint16_t point) +{ + uint32_t tmp; + + assert(point > 0); + tmp = ptr->CTRL[idx].XCVR.DATA_CFG; + tmp &= ~SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK; + tmp |= SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(point); + ptr->CTRL[idx].XCVR.DATA_CFG = tmp; +} + +/** + * @brief Set the SEI tranceiver tx point + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] point tx point value + */ +static inline void sei_set_xcvr_tx_point(SEI_Type *ptr, uint8_t idx, uint16_t point) +{ + uint32_t tmp; + + assert(point > 0); + tmp = ptr->CTRL[idx].XCVR.DATA_CFG; + tmp &= ~SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK; + tmp |= SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(point); + ptr->CTRL[idx].XCVR.DATA_CFG = tmp; +} + +/** + * @brief Set the SEI tranceiver ck0 point + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] point ck0 point value + */ +static inline void sei_set_xcvr_ck0_point(SEI_Type *ptr, uint8_t idx, uint16_t point) +{ + uint32_t tmp; + + assert(point > 0); + tmp = ptr->CTRL[idx].XCVR.CLK_CFG; + tmp &= ~SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK; + tmp |= SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(point); + ptr->CTRL[idx].XCVR.CLK_CFG = tmp; +} + +/** + * @brief Set the SEI tranceiver ck1 point + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] point ck1 point value + */ +static inline void sei_set_xcvr_ck1_point(SEI_Type *ptr, uint8_t idx, uint16_t point) +{ + uint32_t tmp; + + assert(point > 0); + tmp = ptr->CTRL[idx].XCVR.CLK_CFG; + tmp &= ~SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK; + tmp |= SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(point); + ptr->CTRL[idx].XCVR.CLK_CFG = tmp; +} + +/** + * @brief Get the SEI tranceiver ck0 point + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @retval ck0 point value + */ +static inline uint16_t sei_get_xcvr_ck0_point(SEI_Type *ptr, uint8_t idx) +{ + return SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(ptr->CTRL[idx].XCVR.CLK_CFG); +} + +/** + * @brief Get the SEI tranceiver ck1 point + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @retval ck1 point value + */ +static inline uint16_t sei_get_xcvr_ck1_point(SEI_Type *ptr, uint8_t idx) +{ + return SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(ptr->CTRL[idx].XCVR.CLK_CFG); +} + +/** + * @brief Set the SEI command value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] cmd command value + */ +static inline void sei_set_command_value(SEI_Type *ptr, uint8_t idx, uint32_t cmd) +{ + ptr->CTRL[idx].CMD.CMD = cmd; +} + +/** + * @brief Get the SEI command value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @retval command value + */ +static inline uint32_t sei_get_command_value(SEI_Type *ptr, uint8_t idx) +{ + return ptr->CTRL[idx].CMD.CMD; +} + +/** + * @brief Rewind the SEI command + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + */ +static inline void sei_set_command_rewind(SEI_Type *ptr, uint8_t idx) +{ + ptr->CTRL[idx].CMD.MODE |= SEI_CTRL_CMD_MODE_REWIND_MASK; +} + +/** + * @brief Set the SEI data value + * @param [in] ptr SEI base address + * @param [in] idx SEI data index, such as SEI_DAT_2, SEI_DAT_3, etc. + * @param [in] data data value + */ +static inline void sei_set_data_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->DAT[idx].DATA = data; +} + +/** + * @brief Get the SEI data value + * @param [in] ptr SEI base address + * @param [in] idx SEI data index, such as SEI_DAT_2, SEI_DAT_3, etc. + * @retval data value + */ +static inline uint32_t sei_get_data_value(SEI_Type *ptr, uint8_t idx) +{ + return ptr->DAT[idx].DATA; +} + +/** + * @brief Rewind the SEI data + * @param [in] ptr SEI base address + * @param [in] idx SEI data index, such as SEI_DAT_2, SEI_DAT_3, etc. + */ +static inline void sei_set_data_rewind(SEI_Type *ptr, uint8_t idx) +{ + ptr->DAT[idx].MODE |= SEI_DAT_MODE_REWIND_MASK; +} + +/** + * @brief Set the SEI sample position (singleturn) override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data position (singleturn) override value + */ +static inline void sei_set_sample_pos_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.SMP_POS = data; +} + +/** + * @brief Set the SEI sample revolution (multiturn) override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data revolution (multiturn) override value + */ +static inline void sei_set_sample_rev_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.SMP_REV = data; +} + +/** + * @brief Set the SEI sample speed override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data speed override value + */ +static inline void sei_set_sample_spd_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.SMP_SPD = data; +} + +/** + * @brief Set the SEI sample acceleration override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data acceleration override value + */ +static inline void sei_set_sample_acc_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.SMP_ACC = data; +} + +/** + * @brief Set the SEI update position (singleturn) override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data position (singleturn) override value + */ +static inline void sei_set_update_pos_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.UPD_POS = data; +} + +/** + * @brief Set the SEI update revolution (multiturn) override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data revolution (multiturn) override value + */ +static inline void sei_set_update_rev_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.UPD_REV = data; +} + +/** + * @brief Set the SEI update speed override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data speed override value + */ +static inline void sei_set_update_spd_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.UPD_SPD = data; +} + +/** + * @brief Set the SEI update acceleration override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data acceleration override value + */ +static inline void sei_set_update_acc_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.UPD_ACC = data; +} + +/** + * @brief Set the SEI update time override value + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] data time override value + */ +static inline void sei_set_update_time_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) +{ + ptr->CTRL[idx].POS.UPD_TIME = data; +} + +/** + * @brief Set the SEI irq match pointer0 + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] instr_idx match instr0 index + */ +static inline void sei_set_irq_match_instr0_ptr(SEI_Type *ptr, uint8_t idx, uint8_t instr_idx) +{ + ptr->CTRL[idx].IRQ.POINTER0 = SEI_CTRL_IRQ_POINTER0_POINTER_SET(instr_idx); +} + +/** + * @brief Set the SEI irq match pointer1 + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] instr_idx match instr1 index + */ +static inline void sei_set_irq_match_instr1_ptr(SEI_Type *ptr, uint8_t idx, uint8_t instr_idx) +{ + ptr->CTRL[idx].IRQ.POINTER1 = SEI_CTRL_IRQ_POINTER1_POINTER_SET(instr_idx); +} + +/** + * @brief Set the SEI irq match instr0 + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] instr_value match instr0 value + */ +static inline void sei_set_irq_match_instr0_value(SEI_Type *ptr, uint8_t idx, uint32_t instr_value) +{ + ptr->CTRL[idx].IRQ.INSTR0 = SEI_CTRL_IRQ_INSTR0_INSTR_SET(instr_value); +} + +/** + * @brief Set the SEI irq match instr1 + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] instr_value match instr1 value + */ +static inline void sei_set_irq_match_instr1_value(SEI_Type *ptr, uint8_t idx, uint32_t instr_value) +{ + ptr->CTRL[idx].IRQ.INSTR1 = SEI_CTRL_IRQ_INSTR1_INSTR_SET(instr_value); +} + +/** + * @brief Set the SEI irq enable or disable + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] irq_mask irq mask, @ref sei_irq_event_t + * @param [in] enable enable or disable + * @arg true enable + * @arg false disable + */ +static inline void sei_set_irq_enable(SEI_Type *ptr, uint8_t idx, uint32_t irq_mask, bool enable) +{ + if (enable) { + ptr->CTRL[idx].IRQ.INT_EN |= irq_mask; + } else { + ptr->CTRL[idx].IRQ.INT_EN &= ~irq_mask; + } +} + +/** + * @brief Get the SEI irq status + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] irq_mask irq mask, @ref sei_irq_event_t + * + * @retval true-has irq req, false-no irq req. + */ +static inline bool sei_get_irq_status(SEI_Type *ptr, uint8_t idx, uint32_t irq_mask) +{ + return ((ptr->CTRL[idx].IRQ.INT_FLAG & irq_mask) == irq_mask) ? true : false; +} + +/** + * @brief Clear the SEI irq flag + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] irq_mask irq mask, @ref sei_irq_event_t + */ +static inline void sei_clear_irq_flag(SEI_Type *ptr, uint8_t idx, uint32_t irq_mask) +{ + ptr->CTRL[idx].IRQ.INT_FLAG = irq_mask; +} + +/** + * @brief Init SEI tranceiver configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] config tranceiver configuration @ref sei_tranceiver_config_t + * @retval API execution status + */ +hpm_stat_t sei_tranceiver_config_init(SEI_Type *ptr, uint8_t idx, sei_tranceiver_config_t *config); + +/** + * @brief Init SEI command or data format configuration + * @param [in] ptr SEI base address + * @param [in] cmd_data_select + * @arg @ref SEI_SELECT_CMD select command + * @arg @ref SEI_SELECT_DATA select data + * @param [in] idx SEI ctrl index or data index, decided by cmd_data_select, such as SEI_CTRL_0, SEI_CTRL_1, SEI_DAT_2, SEI_DAT_3, etc. + * @param [in] config command or data format configuration @ref sei_data_format_config_t + * @retval API execution status + */ +hpm_stat_t sei_cmd_data_format_config_init(SEI_Type *ptr, bool cmd_data_select, uint8_t idx, sei_data_format_config_t *config); + +/** + * @brief Init SEI command table configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] table_idx command table index, 0 - 7 + * @param [in] config command table configuration @ref sei_command_table_config_t + * @retval API execution status + */ +hpm_stat_t sei_cmd_table_config_init(SEI_Type *ptr, uint8_t idx, uint8_t table_idx, sei_command_table_config_t *config); + +/** + * @brief Init SEI state transition configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] latch_idx latch index + * @arg SEI_LATCH_0 + * @arg SEI_LATCH_1 + * @arg SEI_LATCH_2 + * @arg SEI_LATCH_3 + * @param [in] state transition state + * @arg SEI_CTRL_LATCH_TRAN_0_1 + * @arg SEI_CTRL_LATCH_TRAN_1_2 + * @arg SEI_CTRL_LATCH_TRAN_2_3 + * @arg SEI_CTRL_LATCH_TRAN_3_0 + * @param [in] config state transition configuration @ref sei_state_transition_config_t + * @retval API execution status + */ +hpm_stat_t sei_state_transition_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, uint8_t state, sei_state_transition_config_t *config); + +/** + * @brief Init SEI state transition latch configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] latch_idx latch index + * @arg SEI_LATCH_0 + * @arg SEI_LATCH_1 + * @arg SEI_LATCH_2 + * @arg SEI_LATCH_3 + * @param [in] config state transition latch configuration @ref sei_state_transition_latch_config_t + * @retval API execution status + */ +hpm_stat_t sei_state_transition_latch_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, sei_state_transition_latch_config_t *config); + +/** + * @brief Init SEI sample configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] config sample configuration @ref sei_sample_config_t + * @retval API execution status + */ +hpm_stat_t sei_sample_config_init(SEI_Type *ptr, uint8_t idx, sei_sample_config_t *config); + +/** + * @brief Init SEI update configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] config update configuration @ref sei_update_config_t + * @retval API execution status + */ +hpm_stat_t sei_update_config_init(SEI_Type *ptr, uint8_t idx, sei_update_config_t *config); + +/** + * @brief Init SEI trigger input configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] config trigger input configuration @ref sei_trigger_input_config_t + * @retval API execution status + */ +hpm_stat_t sei_trigger_input_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_input_config_t *config); + +/** + * @brief Init SEI trigger output configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] config trigger output configuration @ref sei_trigger_output_config_t + * @retval API execution status + */ +hpm_stat_t sei_trigger_output_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_output_config_t *config); + +/** + * @brief Init SEI engine configuration + * @param [in] ptr SEI base address + * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. + * @param [in] config engine configuration @ref sei_engine_config_t + * @retval API execution status + */ +hpm_stat_t sei_engine_config_init(SEI_Type *ptr, uint8_t idx, sei_engine_config_t *config); + +/** + * @brief Set SEI Intsructions + * @param [in] ptr SEI base address + * @param [in] idx SEI instruction index. + * @param [in] op SEI instruction operation + * @arg @ref SEI_INSTR_OP_HALT + * @arg @ref SEI_INSTR_OP_JUMP + * @arg @ref SEI_INSTR_OP_SEND_WDG + * @arg @ref SEI_INSTR_OP_SEND + * @arg @ref SEI_INSTR_OP_WAIT_WDG + * @arg @ref SEI_INSTR_OP_WAIT + * @arg @ref SEI_INSTR_OP_RECV_WDG + * @arg @ref SEI_INSTR_OP_RECV + * @param [in] ck SEI instruction clock + * [1] synchronous master clock type + * @arg @ref SEI_INSTR_M_CK_LOW + * @arg @ref SEI_INSTR_M_CK_RISE_FALL + * @arg @ref SEI_INSTR_M_CK_FALL_RISE + * @arg @ref SEI_INSTR_M_CK_HIGH + * [2] synchronous slave clock type + * @arg @ref SEI_INSTR_S_CK_DEFAULT + * @arg @ref SEI_INSTR_S_CK_TRX_EXCH + * @arg @ref SEI_INSTR_S_CK_TIMEOUT_EN + * @arg @ref SEI_INSTR_S_CK_TRX_EXCH_TIMEOUT_EN + * @param [in] crc SEI instruction crc register, such as SEI_DAT_0, SEI_DAT_1, etc. + * @param [in] data SEI instruction data register, such as SEI_DAT_0, SEI_DAT_1, etc. + * @param [in] opr SEI instruction operand. + * [1] When OP is SEI_INSTR_OP_HALT, opr is the halt time in baudrate, 0 represents infinite time. + * [2] When OP is SEI_INSTR_OP_JUMP, opr is command table pointer, init pointer or wdg pointer. + * @arg @ref SEI_JUMP_INIT_INSTR_IDX + * @arg @ref SEI_JUMP_WDG_INSTR_IDX + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX0 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX1 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX2 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX3 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX4 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX5 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX6 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX7 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX8 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX9 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX10 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX11 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX12 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX13 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX14 + * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX15 + * [3] Other OP, this area is the data length. + */ +void sei_set_instr(SEI_Type *ptr, uint8_t idx, uint8_t op, uint8_t ck, uint8_t crc, uint8_t data, uint8_t opr); + + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h index 84ccb2f2..4c9e897a 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h @@ -216,7 +216,10 @@ typedef struct { uint8_t trans_mode; uint8_t data_phase_fmt; uint8_t dummy_cnt; -} spi_common_control_config_t; +#if defined(SPI_SOC_HAS_CS_SELECT) && (SPI_SOC_HAS_CS_SELECT == 1) + uint8_t cs_index; +#endif +} spi_common_control_config_t; /*!< value in spi_cs_index_t */ /** * @brief spi control config structure @@ -227,6 +230,33 @@ typedef struct { spi_common_control_config_t common_config; } spi_control_config_t; +#if defined(SPI_SOC_HAS_CS_SELECT) && (SPI_SOC_HAS_CS_SELECT == 1) +typedef enum { + spi_cs_0 = 1, + spi_cs_1 = 2, + spi_cs_2 = 4, + spi_cs_3 = 8, +} spi_cs_index_t; +#endif + +typedef enum { + addrlen_8bit = 0, + addrlen_16bit, + addrlen_24bit, + addrlen_32bit +} spi_address_len_t; + +#if defined(SPI_SOC_SUPPORT_DIRECTIO) && (SPI_SOC_SUPPORT_DIRECTIO == 1) +typedef enum { + hold_pin = 0, + wp_pin, + miso_pin, + mosi_pin, + sclk_pin, + cs_pin +} spi_directio_pin_t; +#endif + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -616,7 +646,11 @@ static inline void spi_disable_rx_dma(SPI_Type *ptr) */ static inline uint32_t spi_slave_get_sent_data_count(SPI_Type *ptr) { +#if defined(SPI_SOC_HAS_NEW_TRANS_COUNT) && (SPI_SOC_HAS_NEW_TRANS_COUNT == 1) + return ptr->SLVDATAWCNT; +#else return SPI_SLVDATACNT_WCNT_GET(ptr->SLVDATACNT); +#endif } /** @@ -627,7 +661,11 @@ static inline uint32_t spi_slave_get_sent_data_count(SPI_Type *ptr) */ static inline uint32_t spi_slave_get_received_data_count(SPI_Type *ptr) { +#if defined(SPI_SOC_HAS_NEW_TRANS_COUNT) && (SPI_SOC_HAS_NEW_TRANS_COUNT == 1) + return ptr->SLVDATARCNT; +#else return SPI_SLVDATACNT_RCNT_GET(ptr->SLVDATACNT); +#endif } /** @@ -677,6 +715,7 @@ static inline spi_sclk_idle_state_t spi_get_clock_polarity(SPI_Type *ptr) /** * @brief set spi the length of each data unit in bits * + * @param [in] ptr SPI base address * @param [in] nbit the actual bits number of a data * @retval hpm_stat_t status_success if spi transfer without any error */ @@ -685,7 +724,7 @@ static inline hpm_stat_t spi_set_data_bits(SPI_Type *ptr, uint8_t nbits) if (nbits > 32) { return status_invalid_argument; } else { - ptr->TRANSFMT |= SPI_TRANSFMT_DATALEN_SET(nbits - 1); + ptr->TRANSFMT = (ptr->TRANSFMT & ~SPI_TRANSFMT_DATALEN_MASK) | SPI_TRANSFMT_DATALEN_SET(nbits - 1); return status_success; } } @@ -719,6 +758,135 @@ static inline void spi_reset(SPI_Type *ptr) { ptr->CTRL |= SPI_CTRL_SPIRST_MASK; } + +/** + * @brief set spi the length of address + * + * @param [in] ptr SPI base address + * @param [in] addrlen address lenth enum + */ +static inline void spi_set_address_len(SPI_Type *ptr, spi_address_len_t addrlen) +{ + ptr->TRANSFMT = (ptr->TRANSFMT & ~SPI_TRANSFMT_ADDRLEN_MASK) | SPI_TRANSFMT_ADDRLEN_SET(addrlen); +} + +/** + * @brief Enable SPI data merge + * + * @param [in] ptr SPI base address + */ +static inline void spi_enable_data_merge(SPI_Type *ptr) +{ + ptr->TRANSFMT |= SPI_TRANSFMT_DATAMERGE_MASK; +} + +/** + * @brief Disable SPI data merge + * + * @param [in] ptr SPI base address + */ +static inline void spi_disable_data_merge(SPI_Type *ptr) +{ + ptr->TRANSFMT &= ~SPI_TRANSFMT_DATAMERGE_MASK; +} + +#if defined(SPI_SOC_SUPPORT_DIRECTIO) && (SPI_SOC_SUPPORT_DIRECTIO == 1) +/** + * @brief enable specific pin output for spi directio + * + * @note must be used spi_enable_directio API before enable output function + * + * @param [in] ptr SPI base address + * @param [in] pin spi_directio_pin_t enum + */ +hpm_stat_t spi_directio_enable_output(SPI_Type *ptr, spi_directio_pin_t pin); + +/** + * @brief disable specific pin output for spi directio + * + * @param [in] ptr SPI base address + * @param [in] pin spi_directio_pin_t enum + */ +hpm_stat_t spi_directio_disable_output(SPI_Type *ptr, spi_directio_pin_t pin); + +/** + * @brief write specified pin level for spi directio + * + * @param [in] ptr SPI base address + * @param [in] pin spi_directio_pin_t enum + * @param [in] high Pin level set to high when it is set to true + */ +hpm_stat_t spi_directio_write(SPI_Type *ptr, spi_directio_pin_t pin, bool high); + +/** + * @brief Read specified pin level for spi directio + * + * @param [in] ptr SPI base address + * @param pin spi_directio_pin_t enum + * + * @return Pin status + */ +uint8_t spi_directio_read(SPI_Type *ptr, spi_directio_pin_t pin); + +/** + * @brief Enable SPI directIO control function + * + * @note if SPI transmission is required, the function must be disable + * + * @param [in] ptr SPI base address + */ +static inline void spi_enable_directio(SPI_Type *ptr) +{ + ptr->DIRECTIO |= SPI_DIRECTIO_DIRECTIOEN_MASK; +} + +/** + * @brief Disable SPI directIO control function + * + * @param [in] ptr SPI base address + */ +static inline void spi_disable_directio(SPI_Type *ptr) +{ + ptr->DIRECTIO &= ~SPI_DIRECTIO_DIRECTIOEN_MASK; +} + +/** + * @brief get whether spi directio function is enabled + * + * @param [in] ptr SPI base address + * + * @return if pi directio function is enable, it will return 1 + */ +static inline uint8_t spi_get_directio_enable_status(SPI_Type *ptr) +{ + return SPI_DIRECTIO_DIRECTIOEN_GET(ptr->DIRECTIO); +} + +#endif + +/** + * @brief Get valid data size in receive FIFO + * + * @param [in] ptr SPI base address + * + * @return rx fifo valid data size + */ +static inline uint8_t spi_get_rx_fifo_valid_data_size(SPI_Type *ptr) +{ + return ((SPI_STATUS_RXNUM_7_6_GET(ptr->STATUS) << 5) | SPI_STATUS_RXNUM_5_0_GET(ptr->STATUS)); +} + +/** + * @brief Get valid data size in transmit FIFO + * + * @param [in] ptr SPI base address + * + * @return tx fifo valid data size + */ +static inline uint8_t spi_get_tx_fifo_valid_data_size(SPI_Type *ptr) +{ + return ((SPI_STATUS_TXNUM_7_6_GET(ptr->STATUS) << 5) | SPI_STATUS_TXNUM_5_0_GET(ptr->STATUS)); +} /** * @} */ diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h index 6cb4b7ef..9131c591 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h @@ -46,6 +46,55 @@ static inline uint32_t synt_get_current_count(SYNT_Type *ptr) return (ptr->CNT & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT; } +#if defined(SYNT_SOC_HAS_TIMESTAMP) && SYNT_SOC_HAS_TIMESTAMP + +static inline void synt_enable_timestamp(SYNT_Type *ptr, bool enable) +{ + ptr->GCR = (ptr->GCR & ~(SYNT_GCR_TIMESTAMP_ENABLE_MASK)) | SYNT_GCR_TIMESTAMP_ENABLE_SET(enable); +} + +static inline void synt_enable_timestamp_debug_stop(SYNT_Type *ptr, bool enable) +{ + ptr->GCR = (ptr->GCR & ~(SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK)) | SYNT_GCR_TIMESTAMP_DEBUG_EN_SET(enable); +} + +static inline void synt_reset_timestamp(SYNT_Type *ptr) +{ + ptr->GCR |= SYNT_GCR_TIMESTAMP_RESET_MASK; +} + +static inline void synt_update_timestamp_new(SYNT_Type *ptr) +{ + ptr->GCR |= SYNT_GCR_TIMESTAMP_SET_NEW_MASK; +} + +static inline void synt_update_timestamp_dec(SYNT_Type *ptr) +{ + ptr->GCR |= SYNT_GCR_TIMESTAMP_DEC_NEW_MASK; +} + +static inline void synt_update_timestamp_inc(SYNT_Type *ptr) +{ + ptr->GCR |= SYNT_GCR_TIMESTAMP_INC_NEW_MASK; +} + +static inline void synt_set_timestamp_new_value(SYNT_Type *ptr, uint32_t new_value) +{ + ptr->TIMESTAMP_NEW = SYNT_TIMESTAMP_NEW_VALUE_SET(new_value); +} + +static inline uint32_t synt_get_timestamp_save_value(SYNT_Type *ptr) +{ + return SYNT_TIMESTAMP_SAV_VALUE_GET(ptr->TIMESTAMP_SAV); +} + +static inline uint32_t synt_get_timestamp_current_value(SYNT_Type *ptr) +{ + return SYNT_TIMESTAMP_CUR_VALUE_GET(ptr->TIMESTAMP_CUR); +} + +#endif + #ifdef __cplusplus } #endif diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h index fa29d1be..5064511e 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h @@ -24,10 +24,10 @@ */ typedef enum trgm_filter_mode { trgm_filter_mode_bypass = 0, - trgm_filter_mode_rapid_change = 1, - trgm_filter_mode_delay = 2, - trgm_filter_mode_stable_low = 3, - trgm_filter_mode_stable_high = 4, + trgm_filter_mode_rapid_change = 4, + trgm_filter_mode_delay = 5, + trgm_filter_mode_stable_high = 6, + trgm_filter_mode_stable_low = 7, } trgm_filter_mode_t; /** diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h index 073b7366..634f6177 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h @@ -52,20 +52,7 @@ typedef enum word_length { /* @brief UART fifo trigger levels */ typedef enum uart_fifo_trg_lvl { - uart_rx_fifo_trg_not_empty = 0, - uart_rx_fifo_trg_gt_one_quarter = 1, - uart_rx_fifo_trg_gt_half = 2, - uart_rx_fifo_trg_gt_three_quarters = 3, - - uart_tx_fifo_trg_not_full = 0, - uart_tx_fifo_trg_lt_three_quarters = 1, - uart_tx_fifo_trg_lt_half = 2, - uart_tx_fifo_trg_lt_one_quarter = 3, -} uart_fifo_trg_lvl_t; - -#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) -/* @brief UART new fifo trigger levels */ -typedef enum uart_new_fifo_trg_lvl { +#if defined(UART_SOC_HAS_FINE_FIFO_THR) && (UART_SOC_HAS_FINE_FIFO_THR == 1) uart_fifo_1_byte = 0, uart_fifo_2_bytes = 1, uart_fifo_3_bytes = 2, @@ -82,8 +69,28 @@ typedef enum uart_new_fifo_trg_lvl { uart_fifo_14_bytes = 13, uart_fifo_15_bytes = 14, uart_fifo_16_bytes = 15, -} uart_new_fifo_trg_lvl_t; + + uart_rx_fifo_trg_not_empty = uart_fifo_1_byte, + uart_rx_fifo_trg_gt_one_quarter = uart_fifo_4_bytes, + uart_rx_fifo_trg_gt_half = uart_fifo_8_bytes, + uart_rx_fifo_trg_gt_three_quarters = uart_fifo_12_bytes, + + uart_tx_fifo_trg_not_full = uart_fifo_16_bytes, + uart_tx_fifo_trg_lt_three_quarters = uart_fifo_12_bytes, + uart_tx_fifo_trg_lt_half = uart_fifo_8_bytes, + uart_tx_fifo_trg_lt_one_quarter = uart_fifo_4_bytes, +#else + uart_rx_fifo_trg_not_empty = 0, + uart_rx_fifo_trg_gt_one_quarter = 1, + uart_rx_fifo_trg_gt_half = 2, + uart_rx_fifo_trg_gt_three_quarters = 3, + + uart_tx_fifo_trg_not_full = 0, + uart_tx_fifo_trg_lt_three_quarters = 1, + uart_tx_fifo_trg_lt_half = 2, + uart_tx_fifo_trg_lt_one_quarter = 3, #endif +} uart_fifo_trg_lvl_t; /* @brief UART signals */ typedef enum uart_signal { @@ -111,6 +118,14 @@ typedef enum uart_intr_enable { #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) uart_intr_rx_line_idle = UART_IER_ERXIDLE_MASK, #endif +#if defined(UART_SOC_HAS_TXLINE_IDLE_DETECTION) && (UART_SOC_HAS_TXLINE_IDLE_DETECTION == 1) + uart_intr_tx_line_idle = UART_IER_ETXIDLE_MASK, +#endif +#if defined(UART_SOC_HAS_ADDR_MATCH) && (UART_SOC_HAS_ADDR_MATCH == 1) + uart_intr_addr_match = UART_IER_EADDRM_MASK, + uart_intr_addr_match_and_rxidle = UART_IER_EADDRM_IDLE_MASK, + uart_intr_addr_datalost = UART_IER_EDATLOST_MASK, +#endif } uart_intr_enable_t; /* @brief UART interrupt IDs */ @@ -145,13 +160,16 @@ typedef struct uart_modem_config { #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) /** - * @brief UART RX Line Idle detection conditions + * @brief UART Idle detection conditions， suitable for RX and TX */ typedef enum hpm_uart_rxline_idle_cond { uart_rxline_idle_cond_rxline_logic_one = 0, /**< Treat as idle if the RX Line high duration exceeds threshold */ uart_rxline_idle_cond_state_machine_idle = 1 /**< Treat as idle if the RX state machine idle state duration exceeds threshold */ } uart_rxline_idle_cond_t; +/** + * @brief UART Idle config， suitable for RX and TX + */ typedef struct hpm_uart_rxline_idle_detect_config { bool detect_enable; /**< RX Line Idle detection flag */ bool detect_irq_enable; /**< Enable RX Line Idle detection interrupt */ @@ -171,21 +189,21 @@ typedef struct hpm_uart_config { uint8_t parity; /**< Parity */ uint8_t tx_fifo_level; /**< TX Fifo level */ uint8_t rx_fifo_level; /**< RX Fifo level */ -#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) - bool using_new_fifo_thr; -#endif bool dma_enable; /**< DMA Enable flag */ bool fifo_enable; /**< Fifo Enable flag */ uart_modem_config_t modem_config; /**< Modem config */ #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) uart_rxline_idle_config_t rxidle_config; /**< RX Idle configuration */ #endif +#if defined(UART_SOC_HAS_TXLINE_IDLE_DETECTION) && (UART_SOC_HAS_TXLINE_IDLE_DETECTION == 1) + uart_rxline_idle_config_t txidle_config; /**< TX Idle configuration */ +#endif #if defined(UART_SOC_HAS_RXEN_CFG) && (UART_SOC_HAS_RXEN_CFG == 1) bool rx_enable; /**< RX Enable configuration */ #endif } uart_config_t; -#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) +#if defined(UART_SOC_HAS_TRIG_MODE) && (UART_SOC_HAS_TRIG_MODE == 1) typedef struct { uint16_t stop_bit_len; bool en_stop_bit_insert; @@ -222,7 +240,7 @@ static inline uint8_t uart_get_fifo_size(UART_Type *ptr) /** * @brief uart config fifo control * - * @note fifo control register is WO access, prepare all bitfiled value to write + * @note fifo control register(FCR) is WO access, if support FCCR register, it is RW access. * * @param [in] ptr UART base address * @param [in] ctrl uart_fifo_ctrl_t @@ -247,37 +265,43 @@ static inline void uart_clear_rx_fifo(UART_Type *ptr) /** * @brief Reset TX Fifo * - * @note this API may modify other bit fields in FIFO control register - * * @param [in] ptr UART base address */ static inline void uart_reset_tx_fifo(UART_Type *ptr) { - ptr->FCR = UART_FCR_TFIFORST_MASK; +#if defined(UART_SOC_HAS_FCCR_REG) && (UART_SOC_HAS_FCCR_REG == 1) + ptr->FCRR |= UART_FCRR_TFIFORST_MASK; +#else + ptr->FCR = UART_FCR_TFIFORST_MASK | (ptr->GPR); +#endif } /** * @brief Reset RX Fifo * - * @note this API may modify other bit fields in FIFO control register - * * @param [in] ptr UART base address */ static inline void uart_reset_rx_fifo(UART_Type *ptr) { - ptr->FCR = UART_FCR_RFIFORST_MASK; +#if defined(UART_SOC_HAS_FCCR_REG) && (UART_SOC_HAS_FCCR_REG == 1) + ptr->FCRR |= UART_FCRR_RFIFORST_MASK; +#else + ptr->FCR = UART_FCR_RFIFORST_MASK | (ptr->GPR); +#endif } /** * @brief [in] Reset both TX and RX Fifo * - * @note this API may modify other bit fields in FIFO control register - * * @param [in] ptr UART base address */ static inline void uart_reset_all_fifo(UART_Type *ptr) { - ptr->FCR = UART_FCR_RFIFORST_MASK | UART_FCR_TFIFORST_MASK; +#if defined(UART_SOC_HAS_FCCR_REG) && (UART_SOC_HAS_FCCR_REG == 1) + ptr->FCRR |= UART_FCRR_TFIFORST_MASK | UART_FCRR_RFIFORST_MASK; +#else + ptr->FCR = UART_FCR_RFIFORST_MASK | UART_FCR_TFIFORST_MASK | (ptr->GPR); +#endif } /** @@ -426,6 +450,9 @@ static inline uint8_t uart_get_irq_id(UART_Type *ptr) } #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) + +/* if UART_SOC_HAS_IIR2_REG = 1, the IIR2 register exists, should use IIR2 to get/clear rx idle status */ +#if !defined(UART_SOC_HAS_IIR2_REG) || (UART_SOC_HAS_IIR2_REG == 0) /** * @brief Determine whether UART RX Line is idle * @param [in] ptr UART base address @@ -442,7 +469,9 @@ static inline bool uart_is_rxline_idle(UART_Type *ptr) static inline void uart_clear_rxline_idle_flag(UART_Type *ptr) { ptr->IIR = UART_IIR_RXIDLE_FLAG_MASK; /* Write-1-Clear Logic */ + ptr->FCR = ptr->GPR; } +#endif /** * @brief Enable UART RX Idle Line detection logic @@ -473,6 +502,76 @@ hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_conf #endif +#if defined(UART_SOC_HAS_IIR2_REG) && (UART_SOC_HAS_IIR2_REG == 1) +/** + * @brief Determine whether UART TX Line is idle + * @param [in] ptr UART base address + */ +static inline bool uart_is_txline_idle(UART_Type *ptr) +{ + return ((ptr->IIR2 & UART_IIR2_TXIDLE_FLAG_MASK) != 0U) ? true : false; +} + +/** + * @brief Clear UART TX Line Idle Flag + * @param [in] ptr UART base address + */ +static inline void uart_clear_txline_idle_flag(UART_Type *ptr) +{ + ptr->IIR2 = UART_IIR2_TXIDLE_FLAG_MASK; /* Write-1-Clear Logic */ +} + +/** + * @brief Determine whether UART RX Line is idle + * @param [in] ptr UART base address + */ +static inline bool uart_is_rxline_idle(UART_Type *ptr) +{ + return ((ptr->IIR2 & UART_IIR2_RXIDLE_FLAG_MASK) != 0U) ? true : false; +} + +/** + * @brief Clear UART RX Line Idle Flag + * @param [in] ptr UART base address + */ +static inline void uart_clear_rxline_idle_flag(UART_Type *ptr) +{ + ptr->IIR2 = UART_IIR2_RXIDLE_FLAG_MASK; /* Write-1-Clear Logic */ +} +#endif + +#if defined(UART_SOC_HAS_TXLINE_IDLE_DETECTION) && (UART_SOC_HAS_TXLINE_IDLE_DETECTION == 1) +/** + * @brief Enable UART TX Idle Line detection logic + * @param [in] ptr UART base address + */ +static inline void uart_enable_txline_idle_detection(UART_Type *ptr) +{ + ptr->IDLE_CFG |= UART_IDLE_CFG_TX_IDLE_EN_MASK; +} + +/** + * @brief Disable UART TX Idle Line detection logic + * + * @param [in] ptr UART base address + */ +static inline void uart_disable_txline_idle_detection(UART_Type *ptr) +{ + ptr->IDLE_CFG &= ~UART_IDLE_CFG_TX_IDLE_EN_MASK; +} + +/** + * @brief Configure UART TX Line detection + * @param [in] ptr UART base address + * @param [in] txidle_config TXLine IDLE detection configuration + * @retval status_success if no error occurs + */ +hpm_stat_t uart_init_txline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t txidle_config); + +#endif + + + /** * @brief Get status * @@ -586,26 +685,25 @@ hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *buf, uint32_t size_in_byte); hpm_stat_t uart_set_baudrate(UART_Type *ptr, uint32_t baudrate, uint32_t src_clock_hz); -#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) +#if defined(UART_SOC_HAS_TRIG_MODE) && (UART_SOC_HAS_TRIG_MODE == 1) /** - * @brief Config uart trigger mode for communication + * @brief uart configure transfer trigger mode * - * This function is used to tomagawa communication, uart sent out data in fifo then generate interrupt after - * received specify count of data into fifo. + * This function can configure uart to send data in fifo after being triggered * * @param ptr UART base address * @param uart_trig_config_t config */ -void uart_config_trig_mode(UART_Type *ptr, uart_trig_config_t *config); +void uart_config_transfer_trig_mode(UART_Type *ptr, uart_trig_config_t *config); /** - * @brief uart trigger communication + * @brief uart software trigger transmit * - * This function triggers uart communication, the communication configed by uart_config_trig_mode() + * This function immediately triggers the transfer, the transfer configed by uart_config_transfer_trig_mode() * * @param ptr UART base address */ -static inline void uart_trigger_communication(UART_Type *ptr) +static inline void uart_software_trig_transfer(UART_Type *ptr) { ptr->MOTO_CFG &= ~UART_MOTO_CFG_HWTRG_EN_MASK; ptr->MOTO_CFG |= UART_MOTO_CFG_SWTRG_MASK; @@ -614,12 +712,12 @@ static inline void uart_trigger_communication(UART_Type *ptr) /** * @brief uart enable hardware trigger mode * - * This function configures uart start communication by hardware trigger from motor periphrals + * This function enable hardware trigger the transfer, the transfer start when hardware event occured * * @param ptr UART base address - * @param bool enable + * @param enable true for enable, false for disable */ -static inline void uart_enable_hardware_trigger_mode(UART_Type *ptr, bool enable) +static inline void uart_enable_hardware_trig_transfer(UART_Type *ptr, bool enable) { if (enable) { ptr->MOTO_CFG |= UART_MOTO_CFG_HWTRG_EN_MASK; @@ -627,6 +725,104 @@ static inline void uart_enable_hardware_trigger_mode(UART_Type *ptr, bool enable ptr->MOTO_CFG &= ~UART_MOTO_CFG_HWTRG_EN_MASK; } } + +/** + * @brief UART get data count in rx fifo + * + * @param ptr UART base address + * @retval data count + */ +static inline uint8_t uart_get_data_count_in_rx_fifo(UART_Type *ptr) +{ + return UART_LSR_RFIFO_NUM_GET(ptr->LSR); +} + +/** + * @brief UART get data count in tx fifo + * + * @param ptr UART base address + * @retval data count + */ +static inline uint8_t uart_get_data_count_in_tx_fifo(UART_Type *ptr) +{ + return UART_LSR_TFIFO_NUM_GET(ptr->LSR); +} +#endif + +#if defined(UART_SOC_HAS_ADDR_MATCH) && (UART_SOC_HAS_ADDR_MATCH == 1) +/** + * @brief uart enable 9bit transmit mode + * + * @param ptr UART base address + * @param enable true for enable, false for disable + */ +static inline void uart_enable_9bit_transmit_mode(UART_Type *ptr, bool enable) +{ + if (enable) { + ptr->ADDR_CFG |= UART_ADDR_CFG_TXEN_9BIT_MASK + | UART_ADDR_CFG_RXEN_ADDR_MSB_MASK + | UART_ADDR_CFG_RXEN_9BIT_MASK; + } else { + ptr->ADDR_CFG &= ~(UART_ADDR_CFG_TXEN_9BIT_MASK + | UART_ADDR_CFG_RXEN_ADDR_MSB_MASK + | UART_ADDR_CFG_RXEN_9BIT_MASK); + } +} + +/** + * @brief uart enable address0 match + * + * @param ptr UART base address + * @param addr address value + */ +static inline void uart_enable_address0_match(UART_Type *ptr, uint8_t addr) +{ + ptr->ADDR_CFG &= ~UART_ADDR_CFG_ADDR0_MASK; + ptr->ADDR_CFG |= UART_ADDR_CFG_A0_EN_MASK | UART_ADDR_CFG_ADDR0_SET(addr); +} + +/** + * @brief uart enable address1 match + * + * @param ptr UART base address + * @param addr address value + */ +static inline void uart_enable_address1_match(UART_Type *ptr, uint8_t addr) +{ + ptr->ADDR_CFG &= ~UART_ADDR_CFG_ADDR1_MASK; + ptr->ADDR_CFG |= UART_ADDR_CFG_A1_EN_MASK | UART_ADDR_CFG_ADDR1_SET(addr); +} + +/** + * @brief uart disable address0 match + * + * @param ptr UART base address + */ +static inline void uart_disable_address0_match(UART_Type *ptr) +{ + ptr->ADDR_CFG &= ~UART_ADDR_CFG_A0_EN_MASK; +} + +/** + * @brief uart disable address1 match + * + * @param ptr UART base address + */ +static inline void uart_disable_address1_match(UART_Type *ptr) +{ + ptr->ADDR_CFG &= ~UART_ADDR_CFG_A1_EN_MASK; +} + +/** + * @brief uart disable address match(address0 and address1) + * + * @param ptr UART base address + */ +static inline void uart_disable_address_match(UART_Type *ptr) +{ + ptr->ADDR_CFG &= ~(UART_ADDR_CFG_A0_EN_MASK | UART_ADDR_CFG_A1_EN_MASK); +} + #endif #ifdef __cplusplus diff --git a/common/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h b/common/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h index fb47ca34..9c683cde 100644 --- a/common/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h +++ b/common/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h @@ -210,11 +210,6 @@ static inline uint8_t usb_get_port_speed(USB_Type *ptr) return USB_PORTSC1_PSPD_GET(ptr->PORTSC1); } -/*--------------------------------------------------------------------- - * Device API - *--------------------------------------------------------------------- - */ - /** * @brief Initialize USB phy * @@ -222,6 +217,53 @@ static inline uint8_t usb_get_port_speed(USB_Type *ptr) */ void usb_phy_init(USB_Type *ptr); +/** + * @brief USB phy using internal vbus + * + * @param[in] ptr A USB peripheral base address + */ +static inline void usb_phy_using_internal_vbus(USB_Type *ptr) +{ + ptr->PHY_CTRL0 |= (USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK | USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) + | (USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK | USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK); +} + +/** + * @brief USB phy using external vbus + * + * @param[in] ptr A USB peripheral base address + */ +static inline void usb_phy_using_external_vbus(USB_Type *ptr) +{ + ptr->PHY_CTRL0 &= ~((USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK | USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) + | (USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK | USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK)); +} + +/** + * @brief USB phy disconnect dp/dm pins pulldown resistance + * + * @param[in] ptr A USB peripheral base address + */ +static inline void usb_phy_disable_dp_dm_pulldown(USB_Type *ptr) +{ + ptr->PHY_CTRL0 |= 0x001000E0u; +} + +/** + * @brief USB phy connect dp/dm pins pulldown resistance + * + * @param[in] ptr A USB peripheral base address + */ +static inline void usb_phy_enable_dp_dm_pulldown(USB_Type *ptr) +{ + ptr->PHY_CTRL0 &= ~0x001000E0u; +} + +/*--------------------------------------------------------------------- + * Device API + *--------------------------------------------------------------------- + */ + /** * @brief USB device bus reset * @@ -443,6 +485,21 @@ static inline bool usb_hcd_get_port_csc(USB_Type *ptr) return USB_PORTSC1_CSC_GET(ptr->PORTSC1); } +/** + * @brief Set power ctrl polarity + * + * @param[in] ptr A USB peripheral base address + * @param[in] high true - vbus high level enable, false - vbus low level enable + */ +static inline void usb_hcd_set_power_ctrl_polarity(USB_Type *ptr, bool high) +{ + if (high) { + ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_POWER_MASK_MASK; + } else { + ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_POWER_MASK_MASK; + } +} + /** * @brief Enable port power * diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c index 10f4f9ab..5b1f24e4 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -24,8 +24,9 @@ void adc12_get_channel_default_config(adc12_channel_config_t *config) config->diff_sel = adc12_sample_signal_single_ended; config->sample_cycle = 10; config->sample_cycle_shift = 0; - config->thshdh = 0; - config->thshdl = 0; + config->thshdh = 0xfff; + config->thshdl = 0x000; + config->wdog_int_en = false; } static hpm_stat_t adc12_do_calibration(ADC12_Type *ptr, adc12_sample_signal_t diff_sel) @@ -80,6 +81,14 @@ static hpm_stat_t adc12_do_calibration(ADC12_Type *ptr, adc12_sample_signal_t di return status_success; } +hpm_stat_t adc12_deinit(ADC12_Type *ptr) +{ + /* disable all interrupts */ + ptr->INT_EN = 0; + + return status_success; +} + hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config) { uint32_t adc_clk_div; @@ -115,10 +124,7 @@ hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config) | ADC12_ADC_CFG0_ADC_AHB_EN_SET(config->adc_ahb_en); /* Set wait_dis */ - if (config->conv_mode == adc12_conv_mode_oneshot) { - /* Set wait_dis */ - ptr->BUF_CFG0 = ADC12_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); - } + ptr->BUF_CFG0 = ADC12_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); /*------------------------------------------------------------------------------- * Calibration @@ -177,9 +183,30 @@ hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config) | ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(config->sample_cycle_shift) | ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(config->sample_cycle); + /* Enable watchdog interrupt */ + if (config->wdog_int_en) { + ptr->INT_EN |= 1 << config->ch; + } + + + return status_success; +} + +hpm_stat_t adc12_get_channel_threshold(ADC12_Type *ptr, uint8_t ch, adc12_channel_threshold_t *config) +{ + /* Check the specified channel number */ + if (ADC12_IS_CHANNEL_INVALID(ch)) { + return status_invalid_argument; + } + + config->ch = ch; + config->thshdh = ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(ptr->PRD_CFG[ch].PRD_THSHD_CFG); + config->thshdl = ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(ptr->PRD_CFG[ch].PRD_THSHD_CFG); + return status_success; } + hpm_stat_t adc12_init_seq_dma(ADC12_Type *ptr, adc12_dma_config_t *dma_config) { /* Check the DMA buffer length */ diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c index fb725eff..994b9c8e 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,12 +10,13 @@ void adc16_get_default_config(adc16_config_t *config) { + config->res = adc16_res_16_bits; config->conv_mode = adc16_conv_mode_oneshot; config->adc_clk_div = adc16_clock_divider_1; config->conv_duration = 0; config->wait_dis = true; config->sel_sync_ahb = true; - config->port3_rela_time = false; + config->port3_realtime = false; config->adc_ahb_en = false; } @@ -24,8 +25,9 @@ void adc16_get_channel_default_config(adc16_channel_config_t *config) config->ch = 0; config->sample_cycle = 10; config->sample_cycle_shift = 0; - config->thshdh = 0; - config->thshdl = 0; + config->thshdh = 0xffff; + config->thshdl = 0x0000; + config->wdog_int_en = false; } static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) @@ -142,6 +144,14 @@ static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) return status_success; } +hpm_stat_t adc16_deinit(ADC16_Type *ptr) +{ + /* disable all interrupts */ + ptr->INT_EN = 0; + + return status_success; +} + hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config) { uint32_t clk_div_temp; @@ -159,13 +169,11 @@ hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config) /* Set the duration of the conversion */ ptr->ADC_CFG0 = ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(config->sel_sync_ahb) | ADC16_ADC_CFG0_ADC_AHB_EN_SET(config->adc_ahb_en) - | ADC16_ADC_CFG0_CONVERT_DURATION_SET(config->conv_duration); + | ADC16_ADC_CFG0_CONVERT_DURATION_SET(config->conv_duration) + | ADC16_ADC_CFG0_PORT3_REALTIME_SET(config->port3_realtime); /* Set wait_dis */ - if (config->conv_mode == adc16_conv_mode_oneshot) { - /* Set wait_dis */ - ptr->BUF_CFG0 = ADC16_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); - } + ptr->BUF_CFG0 = ADC16_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); /* Get input clock divider */ clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(ptr->CONV_CFG1); @@ -210,9 +218,41 @@ hpm_stat_t adc16_init_channel(ADC16_Type *ptr, adc16_channel_config_t *config) ptr->SAMPLE_CFG[config->ch] = ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(config->sample_cycle_shift) | ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(config->sample_cycle); + /* Enable watchdog interrupt */ + if (config->wdog_int_en) { + ptr->INT_EN |= 1 << config->ch; + } + + + return status_success; +} + +hpm_stat_t adc16_get_channel_threshold(ADC16_Type *ptr, uint8_t ch, adc16_channel_threshold_t *config) +{ + /* Check the specified channel number */ + if (ADC16_IS_CHANNEL_INVALID(ch)) { + return status_invalid_argument; + } + + config->ch = ch; + config->thshdh = ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(ptr->PRD_CFG[ch].PRD_THSHD_CFG); + config->thshdl = ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(ptr->PRD_CFG[ch].PRD_THSHD_CFG); + return status_success; } +#if defined(ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT) && ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT +void adc16_enable_oneshot_mode(ADC16_Type *ptr) +{ + ptr->BUF_CFG0 |= ADC16_BUF_CFG0_BUS_MODE_EN_MASK; +} + +void adc16_disable_oneshot_mode(ADC16_Type *ptr) +{ + ptr->BUF_CFG0 &= ~ADC16_BUF_CFG0_BUS_MODE_EN_MASK; +} +#endif + hpm_stat_t adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *dma_config) { /* Check the DMA buffer length */ @@ -236,11 +276,22 @@ hpm_stat_t adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *dma_config) ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) | ADC16_SEQ_DMA_CFG_BUF_LEN_SET(dma_config->buff_len_in_4bytes - 1); + #if defined(ADC_SOC_SEQ_HCFG_EN) && ADC_SOC_SEQ_HCFG_EN + /* Set high-half buffer length */ + ptr->SEQ_HIGH_CFG = (ptr->SEQ_HIGH_CFG & ~ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) + | ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SET(((dma_config->buff_len_in_4bytes - 1) >> 12)); + #endif + /* Set stop_en and stop_pos */ if (dma_config->stop_en) { ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC16_SEQ_DMA_CFG_STOP_POS_MASK) | ADC16_SEQ_DMA_CFG_STOP_EN_MASK | ADC16_SEQ_DMA_CFG_STOP_POS_SET(dma_config->stop_pos); + + #if defined(ADC_SOC_SEQ_HCFG_EN) && ADC_SOC_SEQ_HCFG_EN + ptr->SEQ_HIGH_CFG = (ptr->SEQ_HIGH_CFG & ~ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) + | ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SET(((dma_config->stop_pos) >> 12)); + #endif } return status_success; diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c index 0357803b..c43881ef 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -102,9 +102,6 @@ hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config) ptr->IDEAL_WN_SIZE = CAM_IDEAL_WN_SIZE_HEIGHT_SET(config->height) | CAM_IDEAL_WN_SIZE_WIDTH_SET(width); - ptr->MAX_WN_CYCLE = CAM_MAX_WN_CYCLE_ROW_SET(1200) - | CAM_MAX_WN_CYCLE_COL_SET(2090); - ptr->CR2 = CAM_CR2_DMA_REQ_EN_RFF_MASK | CAM_CR2_RXFF_LEVEL_SET(CAM_RX_FIFO_THRESHOLD); ptr->DMASA_FB1 = config->buffer1; diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_can_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_can_drv.c index a2361a8c..89c15361 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_can_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_can_drv.c @@ -730,3 +730,11 @@ hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq) return status; } + +void can_deinit(CAN_Type *base) +{ + do { + HPM_BREAK_IF(base == NULL); + can_reset(base, true); + } while (false); +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c index 075866b3..c6fdb034 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c @@ -16,7 +16,7 @@ void dac_get_default_config(dac_config_t *config) hpm_stat_t dac_init(DAC_Type *ptr, dac_config_t *config) { - if (config->dac_mode > dac_mode_buffer) { + if (config->dac_mode > dac_mode_trig) { return status_invalid_argument; } @@ -42,7 +42,7 @@ hpm_stat_t dac_init(DAC_Type *ptr, dac_config_t *config) ptr->CFG1 &= ~DAC_CFG1_ANA_DIV_CFG_MASK; ptr->CFG1 |= DAC_CFG1_ANA_DIV_CFG_SET(config->ana_div); - if (config->dac_mode == dac_mode_direct) { + if (config->dac_mode == dac_mode_direct || config->dac_mode == dac_mode_trig) { /* set ANA_CLK_EN */ ptr->CFG1 |= DAC_CFG1_ANA_CLK_EN_MASK; } @@ -264,7 +264,7 @@ uint32_t dac_get_status_flags(DAC_Type *ptr) void dac_set_status_flags(DAC_Type *ptr, uint32_t mask) { - ptr->IRQ_STS |= mask; + ptr->IRQ_STS = mask; } uint8_t dac_get_current_buffer_index(DAC_Type *ptr) diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c index d84926e2..45aa07ea 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c @@ -60,7 +60,7 @@ hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint8_t ch_num, dma_channel_config_t void dma_default_channel_config(DMA_Type *ptr, dma_channel_config_t *ch) { - ch->priority = 0; + ch->priority = DMA_CHANNEL_PRIORITY_LOW; ch->src_mode = DMA_HANDSHAKE_MODE_NORMAL; ch->dst_mode = DMA_HANDSHAKE_MODE_NORMAL; ch->src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_dmav2_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_dmav2_drv.c new file mode 100644 index 00000000..a9d7f58b --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_dmav2_drv.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_dmav2_drv.h" + +hpm_stat_t dma_setup_channel(DMAV2_Type *ptr, uint8_t ch_num, dma_channel_config_t *ch, bool start_transfer) +{ + uint32_t tmp; + + if ((ch->dst_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) + || (ch->src_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) + || (ch_num >= DMA_SOC_CHANNEL_NUM) + || (ch->en_infiniteloop && (ch->linked_ptr != 0))) { + return status_invalid_argument; + } + if ((ch->size_in_byte & ((1 << ch->dst_width) - 1)) + || (ch->src_addr & ((1 << ch->src_width) - 1)) + || (ch->dst_addr & ((1 << ch->dst_width) - 1)) + || ((1 << ch->src_width) & ((1 << ch->dst_width) - 1)) + || ((ch->linked_ptr & 0x7))) { + return status_dma_alignment_error; + } + ptr->CHCTRL[ch_num].SRCADDR = DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(ch->src_addr); + ptr->CHCTRL[ch_num].DSTADDR = DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(ch->dst_addr); + ptr->CHCTRL[ch_num].TRANSIZE = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(ch->size_in_byte >> ch->src_width); + ptr->CHCTRL[ch_num].LLPOINTER = DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(ch->linked_ptr >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT); + ptr->CHCTRL[ch_num].CHANREQCTRL = DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(ch_num) | DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(ch_num); + + dma_clear_transfer_status(ptr, ch_num); + tmp = DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(ch->en_infiniteloop) + | DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(ch->handshake_opt) + | DMAV2_CHCTRL_CTRL_BURSTOPT_SET(ch->burst_opt) + | DMAV2_CHCTRL_CTRL_PRIORITY_SET(ch->priority) + | DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(ch->src_burst_size) + | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(ch->src_width) + | DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(ch->dst_width) + | DMAV2_CHCTRL_CTRL_SRCMODE_SET(ch->src_mode) + | DMAV2_CHCTRL_CTRL_DSTMODE_SET(ch->dst_mode) + | DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(ch->src_addr_ctrl) + | DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(ch->dst_addr_ctrl) + | ch->interrupt_mask; + + if (start_transfer) { + tmp |= DMAV2_CHCTRL_CTRL_ENABLE_MASK; + } + ptr->CHCTRL[ch_num].CTRL = tmp; + + return status_success; +} + +void dma_default_channel_config(DMAV2_Type *ptr, dma_channel_config_t *ch) +{ + ch->en_infiniteloop = false; + ch->handshake_opt = DMA_HANDSHAKE_OPT_ONE_BURST; + ch->burst_opt = DMA_SRC_BURST_OPT_STANDAND_SIZE; + ch->priority = DMA_CHANNEL_PRIORITY_LOW; + ch->src_mode = DMA_HANDSHAKE_MODE_NORMAL; + ch->dst_mode = DMA_HANDSHAKE_MODE_NORMAL; + ch->src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; + ch->src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + ch->dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; + ch->interrupt_mask = DMA_INTERRUPT_MASK_HALF_TC; /* disable half complete interrupt to keep align with dma */ + ch->linked_ptr = 0; +} + +hpm_stat_t dma_config_linked_descriptor(DMAV2_Type *ptr, dma_linked_descriptor_t *descriptor, uint8_t ch_num, dma_channel_config_t *config) +{ + uint32_t tmp; + + if ((config->dst_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) + || (config->src_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) + || (ch_num >= DMA_SOC_CHANNEL_NUM) + || (config->en_infiniteloop)) { + return status_invalid_argument; + } + if ((config->size_in_byte & ((1 << config->dst_width) - 1)) + || (config->src_addr & ((1 << config->src_width) - 1)) + || (config->dst_addr & ((1 << config->dst_width) - 1)) + || ((1 << config->src_width) & ((1 << config->dst_width) - 1)) + || ((config->linked_ptr & 0x7))) { + return status_dma_alignment_error; + } + descriptor->src_addr = DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(config->src_addr); + descriptor->dst_addr = DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(config->dst_addr); + descriptor->trans_size = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(config->size_in_byte >> config->src_width); + descriptor->linked_ptr = DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(config->linked_ptr >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT); + descriptor->req_ctrl = DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(ch_num) | DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(ch_num); + + tmp = DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(false) + | DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(config->handshake_opt) + | DMAV2_CHCTRL_CTRL_BURSTOPT_SET(config->burst_opt) + | DMAV2_CHCTRL_CTRL_PRIORITY_SET(config->priority) + | DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(config->src_burst_size) + | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(config->src_width) + | DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(config->dst_width) + | DMAV2_CHCTRL_CTRL_SRCMODE_SET(config->src_mode) + | DMAV2_CHCTRL_CTRL_DSTMODE_SET(config->dst_mode) + | DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(config->src_addr_ctrl) + | DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(config->dst_addr_ctrl) + | config->interrupt_mask + | DMAV2_CHCTRL_CTRL_ENABLE_MASK; + descriptor->ctrl = tmp; + + return status_success; +} + +hpm_stat_t dma_start_memcpy(DMAV2_Type *ptr, uint8_t ch_num, + uint32_t dst, uint32_t src, + uint32_t size, uint32_t burst_len_in_byte) +{ + hpm_stat_t stat = status_success; + uint32_t width, count; + int32_t burst_size; + dma_channel_config_t config = {0}; + dma_default_channel_config(ptr, &config); + + /* burst size checking (1-byte burst length will cause heavy overhead */ + if (!burst_len_in_byte || burst_len_in_byte == 1 || burst_len_in_byte > size + || burst_len_in_byte > + ((1 << DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) << DMA_SOC_TRANSFER_PER_BURST_MAX(ptr))) { + return status_invalid_argument; + } + + count = count_set_bits(burst_len_in_byte); + if ((count > 1) || (burst_len_in_byte & 0x1)) { + /* dma only supports 2^n bytes as burst size */ + return status_invalid_argument; + } + + if ((size & (burst_len_in_byte - 1))) { + return status_dma_alignment_error; + } + burst_size = get_first_set_bit_from_lsb(burst_len_in_byte); + + config.src_width = DMA_TRANSFER_WIDTH_HALF_WORD; + config.dst_width = DMA_TRANSFER_WIDTH_HALF_WORD; + for (width = DMA_SOC_TRANSFER_WIDTH_MAX(ptr); width > DMA_TRANSFER_WIDTH_HALF_WORD; width--) { + if (!(burst_len_in_byte & ((1 << width) - 1)) + && !(dst & ((1 << width) - 1)) + && !(src & ((1 << width) - 1)) + && !(size & ((1 << width) - 1))) { + config.src_width = width; + config.dst_width = width; + break; + } + } + + burst_size -= config.src_width; + do { + if (!(src & (((1 << config.src_width) << burst_size) - 1))) { + break; + } + burst_size--; + } while (burst_size > 0); + + config.src_addr = src; + config.dst_addr = dst; + config.size_in_byte = size; + + config.src_burst_size = burst_size; + stat = dma_setup_channel(ptr, ch_num, &config, true); + if (stat != status_success) { + return stat; + } + + return stat; +} + +void dma_default_handshake_config(DMAV2_Type *ptr, dma_handshake_config_t *config) +{ + memset(config, 0, sizeof(dma_handshake_config_t)); + config->en_infiniteloop = false; + config->interrupt_mask = DMA_INTERRUPT_MASK_HALF_TC; +} + +hpm_stat_t dma_setup_handshake(DMAV2_Type *ptr, dma_handshake_config_t *pconfig, bool start_transfer) +{ + hpm_stat_t stat = status_success; + dma_channel_config_t config = {0}; + dma_default_channel_config(ptr, &config); + + if (true == pconfig->dst_fixed) { + config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + } + if (true == pconfig->src_fixed) { + config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; + config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; + } + + if (pconfig->ch_index >= DMA_SOC_CHANNEL_NUM) { + return status_invalid_argument; + } + + config.en_infiniteloop = pconfig->en_infiniteloop; + config.interrupt_mask = pconfig->interrupt_mask; + config.src_width = pconfig->data_width; + config.dst_width = pconfig->data_width; + config.src_addr = pconfig->src; + config.dst_addr = pconfig->dst; + config.size_in_byte = pconfig->size_in_byte; + /* In DMA handshake case, source burst size must be 1 transfer, that is 0. */ + config.src_burst_size = 0; + stat = dma_setup_channel(ptr, pconfig->ch_index, &config, start_transfer); + if (stat != status_success) { + return stat; + } + return stat; +} diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c new file mode 100644 index 00000000..3a437a03 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_enc_pos_drv.h" + + +float encoder_position_to_deg(uint32_t pos) +{ + double tmp; + + tmp = ((double)pos / (double)0xFFFFFFFF) * (double)360.0; + + return (float)tmp; +} + +uint32_t encoder_deg_to_position(float deg) +{ + double tmp; + + while (deg < 0) { + deg += 360; + } + while (deg > 360) { + deg -= 360; + } + + tmp = ((double)deg / (double)360.0) * (double)0xFFFFFFFF; + + return (uint32_t)tmp; +} + +float encoder_position_to_rad(uint32_t pos) +{ + double tmp; + const double _2pi = 6.283185307179586; + + tmp = ((double)pos / (double)0xFFFFFFFF) * _2pi; + + return (float)tmp; +} + +uint32_t encoder_rad_to_position(float rad) +{ + double tmp; + const double _2pi = 6.283185307179586; + + while (rad < 0) { + rad += _2pi; + } + while (rad > _2pi) { + rad -= _2pi; + } + + tmp = ((double)rad / _2pi) * (double)0xFFFFFFFF; + + return (uint32_t)tmp; +} diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c index 12e54ab4..2fd53632 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -228,7 +228,7 @@ void enet_set_duplex_mode(ENET_Type *ptr, enet_duplex_mode_t mode) ptr->MACCFG |= ENET_MACCFG_DM_SET(mode); } -int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *config, enet_int_config_t *int_config) +hpm_stat_t enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *config, enet_int_config_t *int_config) { /* select an interface */ enet_intf_selection(ptr, inf_type); @@ -248,13 +248,20 @@ int enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t * /* mask the mmc tx interrupts */ enet_mask_mmc_tx_interrupt_event(ptr, int_config->mmc_intr_mask_tx); - return true; + return status_success; } /***************************************************************************** * DMA API - ***************************************************************************** - */ + ****************************************************************************/ +void enet_rx_resume(ENET_Type *ptr) +{ + if (ENET_DMA_STATUS_RU_GET(ptr->DMA_STATUS)) { + ptr->DMA_STATUS = ENET_DMA_STATUS_RU_MASK; + ptr->DMA_RX_POLL_DEMAND = 1; + } +} + uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info) { enet_rx_desc_t *rx_desc_list_cur = *parent_rx_desc_list_cur; diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c new file mode 100644 index 00000000..d18894f9 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c @@ -0,0 +1,486 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_ewdg_drv.h" + +/*********************************************************************************************************************** + * + * Definitions + * + **********************************************************************************************************************/ +#define EWDG_CTRL_REG_PARITY_BIT_MASK (1UL << 31) /*!< Parity bit for Control Register */ + +#ifdef EWDG_SOC_CLK_DIV_VAL_MAX +#define EWDG_CTRL_DIV_VAL_MAX EWDG_SOC_CLK_DIV_VAL_MAX +#else +#define EWDG_CTRL_DIV_VAL_MAX (EWDG_CTRL0_DIV_VALUE_MASK >> EWDG_CTRL0_DIV_VALUE_SHIFT) +#endif +#define EWDG_CTRL_WIN_UPPER_MAX (EWDG_CTRL0_WIN_UPPER_MASK >> EWDG_CTRL0_WIN_UPPER_SHIFT) + +#define EWDG_CTRL_REG_UPDATE_PERIOD_DEFAULT (4UL) /* 512 Bus clock */ + +#define EWDG_RING_LEFT_SHIFT_1(val) (((uint16_t)(val) << 1) | ((uint16_t)(val) >> 15)) + +#define EWDG_REFRESH_PERIOD_DEFAULT (10000U) + +#define EWDG_INTERRUPT_TIMEOUT_TICKS_DEFAULT (0UL) +#define EWDG_RESET_TIMEOUT_TICKS_DEFAULT (65535UL) + +#if defined(EWDG_SOC_OVERTIME_REG_WIDTH) && (EWDG_SOC_OVERTIME_REG_WIDTH == 16) +#define EWDG_TIMEOUT_TICK_MAX (65535) +#else +#define EWDG_TIMEOUT_TICK_MAX (0xFFFFFFFFUL) +#endif + +/*********************************************************************************************************************** + * + * Prototypes + * + **********************************************************************************************************************/ +static bool ewdg_need_set_parity_bit(uint32_t reg_val); + +/*********************************************************************************************************************** + * + * Codes + * + **********************************************************************************************************************/ +static bool ewdg_need_set_parity_bit(uint32_t reg_val) +{ + uint32_t non_zero_bits = 0; + while (reg_val > 0) { + reg_val &= (reg_val - 1UL); + ++non_zero_bits; + } + return ((non_zero_bits & 1UL) != 0); +} + +void ewdg_get_default_config(EWDG_Type *ptr, ewdg_config_t *config) +{ + if ((ptr != NULL) && (config != NULL)) { + + (void) memset(config, 0, sizeof(ewdg_config_t)); + + config->ctrl_config.cnt_clk_sel = ewdg_cnt_clk_src_ext_osc_clk; + config->ctrl_config.use_lowlevel_timeout = true; + + config->ctrl_config.refresh_unlock_method = ewdg_refresh_unlock_method_password; + config->ctrl_config.enable_overtime_self_clear = false; + + config->ctrl_config.timeout_interrupt_val = EWDG_INTERRUPT_TIMEOUT_TICKS_DEFAULT; + config->ctrl_config.timeout_reset_val = EWDG_RESET_TIMEOUT_TICKS_DEFAULT; + config->ctrl_config.clock_div_by_power_of_2 = 0; + + config->ctrl_config.refresh_unlock_password = EWDG_REFRESH_UNLOCK_PASSWORD_DEFAULT; + config->ctrl_config.ctrl_reg_update_password = EWDG_UPDATE_PASSWORD_DEFAULT; + config->ctrl_config.ctrl_reg_update_period_bus_clk_x_128 = EWDG_CTRL_REG_UPDATE_PERIOD_DEFAULT; + + config->ctrl_config.low_power_mode = ewdg_low_power_mode_work_clock_normal; + + config->ctrl_config.refresh_period_in_bus_cycles = EWDG_REFRESH_PERIOD_DEFAULT; + } +} + +hpm_stat_t ewdg_init_ctrl_func(EWDG_Type *ptr, ewdg_func_ctrl_config_t *config, uint32_t cnt_src_freq) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (config == NULL) || (cnt_src_freq == 0)) { + break; + } + if (config->window_lower_limit > ewdg_window_lower_timeout_period_max) { + break; + } + if (config->window_upper_limit > ewdg_window_upper_timeout_period_max) { + break; + } + if (config->refresh_unlock_method > ewdg_refresh_unlock_method_max) { + break; + } + + uint32_t ctrl0 = 0; + + uint32_t ot_int_ticks; + uint32_t ot_reset_ticks; + uint32_t clock_div_by_pwr_2 = 0; + if (!config->use_lowlevel_timeout) { + uint64_t timeout_interrupt_ticks = ewdg_convert_timeout_us_to_timeout_ticks(config->timeout_interrupt_us, + cnt_src_freq); + uint64_t timeout_reset_ticks = ewdg_convert_timeout_us_to_timeout_ticks(config->timeout_reset_us, + cnt_src_freq); + clock_div_by_pwr_2 = 0; + while ((timeout_interrupt_ticks > EWDG_TIMEOUT_TICK_MAX) || (timeout_reset_ticks > EWDG_TIMEOUT_TICK_MAX)) { + ++clock_div_by_pwr_2; + timeout_interrupt_ticks >>= 1; + timeout_reset_ticks >>= 1; + } + if (clock_div_by_pwr_2 > EWDG_SOC_CLK_DIV_VAL_MAX) { + status = status_ewdg_div_out_of_range; + /* Cannot get the expected EWDG setting via the specified timeout input */ + break; + } + ot_int_ticks = (uint32_t) (timeout_interrupt_ticks & 0xFFFFFFFFUL); + ot_reset_ticks = (uint32_t) (timeout_reset_ticks & 0xFFFFFFFFUL); + + } else { + clock_div_by_pwr_2 = config->clock_div_by_power_of_2; + ot_int_ticks = config->timeout_interrupt_val; + ot_reset_ticks = config->timeout_reset_val; + + if (clock_div_by_pwr_2 > EWDG_SOC_CLK_DIV_VAL_MAX) { + status = status_ewdg_div_out_of_range; + /* Cannot get the expected EWDG setting via the specified timeout input */ + break; + } + if ((ot_int_ticks > EWDG_TIMEOUT_TICK_MAX) || (ot_reset_ticks > EWDG_TIMEOUT_TICK_MAX)) { + status = status_ewdg_tick_out_of_range; + break; + } + } + + if (config->cnt_clk_sel == ewdg_cnt_clk_src_ext_osc_clk) { + ctrl0 |= EWDG_CTRL0_CLK_SEL_MASK; + } + ctrl0 |= EWDG_CTRL0_DIV_VALUE_SET(clock_div_by_pwr_2); + if (config->enable_window_mode) { + ctrl0 |= EWDG_CTRL0_WIN_EN_MASK; + + ctrl0 |= EWDG_CTRL0_WIN_LOWER_SET(config->window_lower_limit); + ctrl0 |= EWDG_CTRL0_WIN_UPPER_SET(config->window_upper_limit); + } + + if (config->enable_config_lock) { + ctrl0 |= EWDG_CTRL0_CFG_LOCK_MASK; + } + + if (config->enable_refresh_period) { + ctrl0 |= EWDG_CTRL0_REF_OT_REQ_MASK; + } + if (config->enable_refresh_lock) { + ctrl0 |= EWDG_CTRL0_REF_LOCK_MASK; + } + ctrl0 |= EWDG_CTRL0_REF_UNLOCK_MEC_SET(config->refresh_unlock_method); + + if (config->enable_overtime_self_clear) { + ctrl0 |= EWDG_CTRL0_OT_SELF_CLEAR_MASK; + } + if (config->keep_running_in_debug_mode) { + ctrl0 |= EWDG_CTRL0_EN_DBG_MASK; + } + ctrl0 |= EWDG_CTRL0_EN_LP_SET(config->low_power_mode); + + /* Set Parity bit if necessary */ + if (ewdg_need_set_parity_bit(ctrl0)) { + ctrl0 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL0 = ctrl0; + + ptr->CFG_PROT = EWDG_CFG_PROT_UPD_OT_TIME_SET(config->ctrl_reg_update_period_bus_clk_x_128) | + EWDG_CFG_PROT_UPD_PSD_SET(config->ctrl_reg_update_password); + + ptr->REF_TIME = config->refresh_period_in_bus_cycles; + ptr->REF_PROT = EWDG_REF_PROT_REF_UNL_PSD_SET(config->refresh_unlock_password); + + +#if !defined(EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT) || (EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT == 1) + ptr->OT_INT_VAL = ot_int_ticks; +#endif + ptr->OT_RST_VAL = ot_reset_ticks; + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t ewdg_init_interrupt_reset(EWDG_Type *ptr, ewdg_interrupt_reset_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (config == NULL)) { + break; + } + + uint32_t ctrl1 = 0; + if (config->enable_ctrl_parity_fail_reset) { + ctrl1 |= EWDG_RST_PARITY_FAIL; + } + if (config->enable_ctrl_unlock_fail_reset) { + ctrl1 |= EWDG_RST_CTRL_REG_UNLOCK_FAIL; + } + if (config->enable_refresh_unlock_fail_reset) { + ctrl1 |= EWDG_RST_REFRESH_UNLOCK_FAIL; + } + if (config->enable_ctrl_update_violation_reset) { + ctrl1 |= EWDG_RST_CTRL_REG_UPDATE_FAIL; + } + if (config->enable_timeout_reset) { + ctrl1 |= EWDG_RST_TIMEOUT; + } + if (config->enable_refresh_violation_reset) { + ctrl1 |= EWDG_RST_REFRESH_VIOLATION; + } + +#if defined(EWDG_SOC_SUPPORT_INTERRUPT) && (EWDG_SOC_SUPPORT_INTERRUPT == 0) + if (config->enable_timeout_interrupt) { + status = status_ewdg_feature_unsupported; + break; + } +#else + if (config->enable_timeout_interrupt) { + ctrl1 |= EWDG_INT_TIMEOUT; + } +#endif + if (config->enable_ctrl_parity_fail_interrupt) { + ctrl1 |= EWDG_INT_PARITY_FAIL; + } + if (config->enable_ctrl_unlock_fail_interrupt) { + ctrl1 |= EWDG_INT_CTRL_REG_UNLOCK_FAIL; + } + if (config->enable_refresh_unlock_fail_interrupt) { + ctrl1 |= EWDG_INT_REFRESH_UNLOCK_FAIL; + } + if (config->enable_ctrl_update_violation_interrupt) { + ctrl1 |= EWDG_INT_CTRL_REG_UPDATE_FAIL; + } + if (config->enable_refresh_violation_interrupt) { + ctrl1 |= EWDG_INT_REFRESH_VIOLATION; + } + + /* Set Parity bit if necessary */ + if (ewdg_need_set_parity_bit(ctrl1)) { + ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL1 = ctrl1; + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t ewdg_init(EWDG_Type *ptr, ewdg_config_t *config) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if ((ptr == NULL) || (config == NULL)) { + break; + } + + status = ewdg_init_ctrl_func(ptr, &config->ctrl_config, config->cnt_src_freq); + if (status != status_success) { + break; + } + status = ewdg_init_interrupt_reset(ptr, &config->int_rst_config); + if (status != status_success) { + break; + } + + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->WDT_EN = (config->enable_watchdog) ? 1UL : 0UL; + + } while (false); + + return status; +} + +hpm_stat_t ewdg_unlock_refresh(EWDG_Type *ptr) +{ + hpm_stat_t status = status_invalid_argument; + + do { + if (ptr == NULL) { + break; + } + + if (!ewdg_is_refresh_locked(ptr)) { + status = status_success; + break; + } + + ewdg_refresh_unlock_method_t unlock_method = ewdg_get_refresh_unlock_method(ptr); + uint32_t unlock_password; + uint32_t reg_unlock_password = EWDG_REF_PROT_REF_UNL_PSD_GET(ptr->REF_PROT); + if (unlock_method == ewdg_refresh_unlock_method_password) { + unlock_password = reg_unlock_password; + } else if (unlock_method == ewdg_refresh_unlock_method_fixed_key) { + unlock_password = EWDG_REFRESH_UNLOCK_FIXED_KEY; + } else if (unlock_method == ewdg_refresh_unlock_method_ring_left_shift_password_by_1) { + unlock_password = EWDG_RING_LEFT_SHIFT_1(reg_unlock_password); + } else if (unlock_method == ewdg_refresh_unlock_method_ring_left_shift_password_by_1_bit0_xor_password_bit0) { + uint16_t high_15 = (reg_unlock_password << 1) & 0xFFFFU; + uint16_t low_0 = reg_unlock_password >> 15; + low_0 ^= reg_unlock_password; + unlock_password = high_15 | (low_0 & 0x1UL); + } else { + /* Should never reach this branch */ + break; + } + + ptr->REF_PROT = unlock_password; + + status = status_success; + + } while (false); + + return status; +} + +hpm_stat_t ewdg_refresh(EWDG_Type *ptr) +{ + hpm_stat_t status = ewdg_unlock_refresh(ptr); + if (status == status_success) { + ewdg_write_refresh_reg(ptr); + } + return status; +} + +uint32_t ewdg_get_count_clock_freq(EWDG_Type *ptr, uint32_t src_clk_freq) +{ + uint32_t divided_freq = 0; + if (ptr != NULL) { + uint32_t divider = ewdg_get_count_clk_divider(ptr); + divided_freq = src_clk_freq / divider; + } + return divided_freq; +} + +uint64_t ewdg_convert_timeout_us_to_timeout_ticks(uint32_t src_clk_freq, uint32_t timeout_us) +{ + uint64_t timeout_ticks = 0; + if (src_clk_freq != 0U) { + uint32_t ns_per_tick = 1000000000UL / src_clk_freq; + uint64_t timeout_ns = (uint64_t) timeout_us * 1000UL; + timeout_ticks = (timeout_ns + ns_per_tick - 1U) / ns_per_tick; + } + return timeout_ticks; +} + +uint32_t ewdg_convert_timeout_ticks_to_timeout_us(EWDG_Type *ptr, uint32_t src_clk_freq, uint32_t timeout_ticks) +{ + uint32_t timeout_us; + if (src_clk_freq == 0U) { + timeout_us = 0; + } else { + uint32_t actual_clk_freq = src_clk_freq / ewdg_get_count_clk_divider(ptr); + uint32_t ns_per_tick = 1000000000UL / actual_clk_freq; + uint64_t timeout_ns = (uint64_t) timeout_ticks * ns_per_tick; + timeout_us = timeout_ns / 1000UL; + } + return timeout_us; +} + +void ewdg_enable_interrupt(EWDG_Type *ptr, uint32_t mask) +{ + uint32_t interrupt_mask = mask & EWDG_INT_ALL; + if (ptr != NULL) { + uint32_t ctrl1 = ptr->CTRL1 | interrupt_mask; + /* Set Parity bit if necessary */ + if (ewdg_need_set_parity_bit(ctrl1)) { + ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL1 = ctrl1; + } +} + +void ewdg_disable_interrupt(EWDG_Type *ptr, uint32_t mask) +{ + uint32_t interrupt_mask = mask & EWDG_INT_ALL; + if (ptr != NULL) { + uint32_t ctrl1 = ptr->CTRL1 & ~interrupt_mask; + /* Set Parity bit if necessary */ + if (ewdg_need_set_parity_bit(ctrl1)) { + ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL1 = ctrl1; + } +} + +void ewdg_enable_reset(EWDG_Type *ptr, uint32_t mask) +{ + uint32_t reset_mask = mask & EWDG_RST_ALL; + if (ptr != NULL) { + uint32_t ctrl1 = ptr->CTRL1 | reset_mask; + /* Set Parity bit if necessary */ + if (ewdg_need_set_parity_bit(ctrl1)) { + ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL1 = ctrl1; + } +} + +void ewdg_disable_reset(EWDG_Type *ptr, uint32_t mask) +{ + uint32_t reset_mask = mask & EWDG_RST_ALL; + if (ptr != NULL) { + uint32_t ctrl1 = ptr->CTRL1 & ~reset_mask; + /* Set Parity bit if necessary */ + if (ewdg_need_set_parity_bit(ctrl1)) { + ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL1 = ctrl1; + } +} + +void ewdg_switch_clock_source(EWDG_Type *ptr, ewdg_cnt_clk_sel_t clk_sel) +{ + if (ptr != NULL) { + uint32_t ctrl0 = ptr->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK; + /* Set Parity bit if necessary */ + if (clk_sel == ewdg_cnt_clk_src_ext_osc_clk) { + ctrl0 |= EWDG_CTRL0_CLK_SEL_MASK; + } + if (ewdg_need_set_parity_bit(ctrl0)) { + ctrl0 |= EWDG_CTRL_REG_PARITY_BIT_MASK; + } + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->CTRL0 = ctrl0; + } +} + +void ewdg_enable(EWDG_Type *ptr) +{ + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->WDT_EN = 1; +} + +void ewdg_disable(EWDG_Type *ptr) +{ + if (ewdg_is_ctrl_reg_locked(ptr)) { + ewdg_unlock_ctrl_regs(ptr); + } + ptr->WDT_EN = 0; +} diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c index 8a6f0480..53248c44 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c @@ -43,6 +43,9 @@ void gpio_config_pin_interrupt(GPIO_Type *ptr, uint32_t gpio_index, uint8_t pin_ break; case gpio_interrupt_trigger_edge_falling: case gpio_interrupt_trigger_edge_rising: +#if defined(GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT) && (GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT == 1) + ptr->PD[gpio_index].CLEAR = 1 << pin_index; +#endif ptr->TP[gpio_index].SET = 1 << pin_index; if (trigger == gpio_interrupt_trigger_edge_rising) { ptr->PL[gpio_index].CLEAR = 1 << pin_index; @@ -50,6 +53,12 @@ void gpio_config_pin_interrupt(GPIO_Type *ptr, uint32_t gpio_index, uint8_t pin_ ptr->PL[gpio_index].SET = 1 << pin_index; } break; +#if defined(GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT) && (GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT == 1) + case gpio_interrupt_trigger_edge_both: + ptr->TP[gpio_index].SET = 1 << pin_index; + ptr->PD[gpio_index].SET = 1 << pin_index; + break; +#endif default: return; } diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c new file mode 100644 index 00000000..cde3d8b3 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_gwc_drv.h" + +void gwc_get_default_config(gwc_config_t *cfg) +{ + cfg->clk_pol = gwc_clk_pol_normal; +} + +void gwc_init(GWC_Type *ptr, gwc_config_t *cfg) +{ + ptr->GLB_CTRL = cfg->clk_pol; +} + +void gwc_enable(GWC_Type *ptr) +{ + ptr->GLB_CTRL |= GWC_GLB_CTRL_GWC_EN_MASK; +} + +void gwc_disable(GWC_Type *ptr) +{ + ptr->GLB_CTRL &= ~GWC_GLB_CTRL_GWC_EN_MASK; +} + +void gwc_freeze_interrupt_control(GWC_Type *ptr) +{ + ptr->IRQ_MASK |= GWC_IRQ_MASK_MASK_RREEZ_MASK; +} + +void gwc_ch_init(GWC_Type *ptr, uint8_t ch_index, gwc_ch_config_t *cfg) +{ + assert(ch_index <= GWC_CHANNEL_CH15); + ptr->CHANNEL[ch_index].CFG0 = GWC_CHANNEL_CFG0_START_ROW_SET(cfg->start_row) | + GWC_CHANNEL_CFG0_START_COL_SET(cfg->start_col) | + (cfg->freeze ? GWC_CHANNEL_CFG0_FREEZE_MASK : 0); + ptr->CHANNEL[ch_index].CFG1 = GWC_CHANNEL_CFG1_END_ROW_SET(cfg->end_row) | + GWC_CHANNEL_CFG1_END_COL_SET(cfg->end_col); + ptr->CHANNEL[ch_index].REFCRC = cfg->ref_crc; +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c index 42c19570..a1dbb0cd 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c @@ -165,9 +165,10 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, hpm_stat_t stat = status_success; uint32_t left; uint32_t retry; - - assert(addr_size_in_byte > 0 && addr_size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); - assert(size_in_byte > 0 && size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((addr_size_in_byte == 0) || (addr_size_in_byte > I2C_SOC_TRANSFER_COUNT_MAX)) || + ((size_in_byte == 0) || (size_in_byte > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } retry = 0; while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { @@ -188,6 +189,7 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(addr_size_in_byte) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(addr_size_in_byte)); ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); @@ -218,6 +220,7 @@ hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(addr_size_in_byte) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size_in_byte)); ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; @@ -261,9 +264,11 @@ hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address uint32_t left; uint32_t retry; - assert(addr_size_in_byte > 0 && addr_size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); - assert(size_in_byte > 0 && size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); - assert(addr_size_in_byte + size_in_byte <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((addr_size_in_byte == 0) || (addr_size_in_byte > I2C_SOC_TRANSFER_COUNT_MAX)) || + ((size_in_byte == 0) || (size_in_byte > I2C_SOC_TRANSFER_COUNT_MAX)) || + ((addr_size_in_byte + size_in_byte) > I2C_SOC_TRANSFER_COUNT_MAX)) { + return status_invalid_argument; + } retry = 0; while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { @@ -286,6 +291,7 @@ hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size_in_byte + addr_size_in_byte) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size_in_byte + addr_size_in_byte)); left = addr_size_in_byte; @@ -335,8 +341,9 @@ hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, hpm_stat_t stat = status_success; uint32_t left; uint32_t retry; - - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (size > I2C_SOC_TRANSFER_COUNT_MAX) { + return status_invalid_argument; + } retry = 0; while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { @@ -359,6 +366,7 @@ hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; @@ -410,7 +418,9 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, uint32_t retry; uint32_t left; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (size > I2C_SOC_TRANSFER_COUNT_MAX) { + return status_invalid_argument; + } retry = 0; while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { @@ -433,15 +443,15 @@ hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); - + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; retry = 0; left = size; while (left) { if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { ptr->DATA = *(buf++); left--; - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; retry = 0; } else { if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { @@ -506,7 +516,9 @@ hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size) uint32_t retry; uint32_t left; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } /* wait for address hit */ retry = 0; @@ -571,7 +583,9 @@ hpm_stat_t i2c_slave_read(I2C_Type *ptr, uint32_t retry; uint32_t left; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } /* wait for address hit */ retry = 0; @@ -631,7 +645,9 @@ hpm_stat_t i2c_slave_read(I2C_Type *ptr, hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) { uint32_t retry = 0; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { @@ -652,6 +668,7 @@ hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_a | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; @@ -664,7 +681,9 @@ hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_a hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) { uint32_t retry = 0; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { @@ -684,6 +703,7 @@ hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_ad | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; @@ -695,12 +715,15 @@ hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_ad hpm_stat_t i2c_slave_dma_transfer(I2C_Type *i2c_ptr, uint32_t size) { - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } /* W1C, clear CMPL bit to avoid blocking the transmission */ i2c_ptr->STATUS = I2C_STATUS_CMPL_MASK; - i2c_ptr->CTRL |= I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); + i2c_ptr->CTRL &= ~(I2C_CTRL_DATACNT_HIGH_MASK | I2C_CTRL_DATACNT_MASK); + i2c_ptr->CTRL |= I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; @@ -710,7 +733,9 @@ hpm_stat_t i2c_slave_dma_transfer(I2C_Type *i2c_ptr, uint32_t size) hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size, bool read) { uint32_t retry = 0; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { @@ -730,6 +755,7 @@ hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t devic | I2C_CTRL_PHASE_ADDR_MASK | I2C_CTRL_PHASE_DATA_MASK | I2C_CTRL_DIR_SET(read) + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; @@ -744,7 +770,9 @@ hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, uint32_t retry = 0; uint32_t left = 0; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } /* W1C, clear CMPL bit to avoid blocking the transmission */ ptr->STATUS = I2C_STATUS_CMPL_MASK; @@ -770,9 +798,11 @@ hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, ptr->CTRL = ctrl | I2C_CTRL_PHASE_DATA_SET(true) \ | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) \ + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) \ | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); /* enable auto ack */ ptr->INTEN &= ~I2C_EVENT_BYTE_RECEIVED; + ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; retry = 0; left = size; @@ -780,7 +810,6 @@ hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { ptr->DATA = *(buf++); left--; - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; retry = 0; } else { if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { @@ -818,7 +847,9 @@ hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address, uint32_t retry = 0; uint32_t left = 0; - assert(size > 0 && size <= I2C_SOC_TRANSFER_COUNT_MAX); + if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { + return status_invalid_argument; + } /* W1C, clear CMPL bit to avoid blocking the transmission */ ptr->STATUS = I2C_STATUS_CMPL_MASK; @@ -844,6 +875,7 @@ hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address, ptr->CTRL = ctrl | I2C_CTRL_PHASE_DATA_SET(true) \ | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) \ + | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) \ | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); /* disable auto ack */ diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c index 15632682..48bfe67f 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c @@ -33,25 +33,16 @@ static bool i2s_channel_length_is_valid(uint8_t bits) void i2s_reset_all(I2S_Type *ptr) { + /* disable I2S */ + ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; /* gate off bclk */ ptr->CFGR |= I2S_CFGR_BCLK_GATEOFF_MASK; /* gate off mclk */ ptr->MISC_CFGR |= I2S_MISC_CFGR_MCLK_GATEOFF_MASK; - /* - * clear fifos - */ - ptr->CTRL |= I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK; - ptr->CTRL &= ~(I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK); - /* - * software reset all blocks - */ - ptr->CTRL |= I2S_CTRL_SFTRST_CLKGEN_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK; - ptr->CTRL &= ~(I2S_CTRL_SFTRST_CLKGEN_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); - /* - * disable i2s - */ - ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; + /* reset function block and clear fifo */ + ptr->CTRL |= (I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_CLKGEN_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); + ptr->CTRL &= ~(I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_CLKGEN_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); } void i2s_get_default_config(I2S_Type *ptr, i2s_config_t *config) @@ -173,8 +164,7 @@ static hpm_stat_t _i2s_config_tx(I2S_Type *ptr, i2s_transfer_config_t *config) ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; } ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_TX_EN_MASK)) - | I2S_CTRL_TX_EN_SET(1 << config->data_line) - | I2S_CTRL_I2S_EN_MASK; + | I2S_CTRL_TX_EN_SET(1 << config->data_line); return status_success; } @@ -196,8 +186,7 @@ static hpm_stat_t _i2s_config_rx(I2S_Type *ptr, i2s_transfer_config_t *config) ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; } ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_RX_EN_MASK)) - | I2S_CTRL_RX_EN_SET(1 << config->data_line) - | I2S_CTRL_I2S_EN_MASK; + | I2S_CTRL_RX_EN_SET(1 << config->data_line); return status_success; } @@ -228,8 +217,7 @@ static hpm_stat_t _i2s_config_transfer(I2S_Type *ptr, i2s_transfer_config_t *con } ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_RX_EN_MASK | I2S_CTRL_TX_EN_MASK)) | I2S_CTRL_RX_EN_SET(1 << config->data_line) - | I2S_CTRL_TX_EN_SET(1 << config->data_line) - | I2S_CTRL_I2S_EN_MASK; + | I2S_CTRL_TX_EN_SET(1 << config->data_line); return status_success; } diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c new file mode 100644 index 00000000..5c1fba1c --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c @@ -0,0 +1,373 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_linv2_drv.h" + +#define HPM_LIN_DRV_RETRY_COUNT (50000U) + +hpm_stat_t lin_master_configure_timing(LINV2_Type *ptr, lin_timing_t *timing) +{ + assert(timing->src_freq_in_hz >= 8000000U); + assert((timing->baudrate >= 1000U) && (timing->baudrate <= 20000U)); + + uint8_t prescaler, bt_mul; + uint16_t bt_div; + + /** set master mode */ + ptr->TIMING_CONTROL = LINV2_TIMING_CONTROL_MASTER_MODE_MASK; + ptr->TIMING_CONTROL |= LINV2_TIMING_CONTROL_LIN_INITIAL_MASK; + ptr->TIMING_CONTROL &= ~LINV2_TIMING_CONTROL_LIN_INITIAL_MASK; + + bt_mul = 20000U / timing->baudrate - 1U; + prescaler = log((timing->src_freq_in_hz / ((bt_mul + 1U) * timing->baudrate * 200U))) / log(2U) - 1U; + bt_div = timing->src_freq_in_hz / ((1U << (prescaler + 1U)) * (bt_mul + 1U) * timing->baudrate); + + if ((bt_div < 200) || (bt_div > 512)) { + return status_invalid_argument; + } + + /** src =20MHz baudrate = 19.2KHz */ + /** bt_div = 260, scaler = 1, bt_mul = 0 */ + ptr->TIMING_CONTROL |= LINV2_TIMING_CONTROL_BT_DIV_SET(bt_div) + | LINV2_TIMING_CONTROL_BT_MUL_SET(bt_mul) + | LINV2_TIMING_CONTROL_PRESCL_SET(prescaler); + + return status_success; +} + +hpm_stat_t lin_slave_configure_timing(LINV2_Type *ptr, uint32_t src_freq_in_hz) +{ + assert(src_freq_in_hz >= 8000000U); + + uint8_t prescaler; + uint16_t bt_div; + + /** set slave mode, clean bt_div, bit_mul, prescl */ + ptr->TIMING_CONTROL = 0; + ptr->TIMING_CONTROL |= LINV2_TIMING_CONTROL_LIN_INITIAL_MASK; + ptr->TIMING_CONTROL &= ~LINV2_TIMING_CONTROL_LIN_INITIAL_MASK; + + prescaler = log((src_freq_in_hz / (20000U * 200U))) / log(2U) - 1U; + bt_div = src_freq_in_hz / ((1U << (prescaler + 1U)) * 20000U); + + if ((bt_div < 200) || (bt_div >= 512)) { + return status_invalid_argument; + } + + /** src = 20MHz, prescaler = 1, bt_div = 250 */ + /* TODO： set wakeup_len */ + ptr->TIMING_CONTROL = LINV2_TIMING_CONTROL_BT_DIV_SET(bt_div) + | LINV2_TIMING_CONTROL_PRESCL_SET(prescaler); + + /* disable break_err detect */ + ptr->CONTROL_STATUS = LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK; + + return status_success; +} + +uint8_t lin_get_data_length_from_id(uint8_t id) +{ + switch (LIN_ID_DATA_LEN_GET(id)) { + case id_data_length_2bytes: + return 2; + case id_data_length_2bytes_2: + return 2; + case id_data_length_4bytes: + return 4; + case id_data_length_8bytes: + return 8; + default: + return 8; + } +} + +uint8_t lin_get_data_length(LINV2_Type *ptr) +{ + uint8_t data_length = 0; + if (((ptr->DATA_LEN_ID) & LINV2_DATA_LEN_ID_DATA_LEN_MASK) == LINV2_DATA_LEN_ID_DATA_LEN_MASK) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + } else { + data_length = LINV2_DATA_LEN_ID_DATA_LEN_GET(ptr->DATA_LEN_ID); + } + return data_length; +} + +void lin_master_transfer(LINV2_Type *ptr, lin_trans_config_t *config) +{ + uint8_t data_length; + + /** config id */ + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK | LINV2_DATA_LEN_ID_ID_SET(config->id); + } else { + data_length = config->data_length; + ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length) | LINV2_DATA_LEN_ID_ID_SET(config->id); + } + + /** sent or receive */ + ptr->CONTROL_STATUS = 0U; + if (config->transmit) { + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_TRANSMIT_MASK; + } + + if (config->transmit) { + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATA_BYTE[i] = *((config->data_buff)++); + } + } + + /** start */ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_START_REQ_MASK; +} + +hpm_stat_t lin_master_sent(LINV2_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length = 0; + + /** wait for lin inactive */ + while (lin_is_active(ptr)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + /** config id */ + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK | LINV2_DATA_LEN_ID_ID_SET(config->id); + } else { + data_length = config->data_length; + ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length) | LINV2_DATA_LEN_ID_ID_SET(config->id); + } + + ptr->CONTROL_STATUS = LINV2_CONTROL_STATUS_TRANSMIT_MASK; + + /** load data into registers */ + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATA_BYTE[i] = *((config->data_buff)++); + } + + /** start */ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_START_REQ_MASK; + + /** waiting for lin complete */ + retry = 0; + while (!lin_is_complete(ptr)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_timeout; + } + return status_success; +} + +hpm_stat_t lin_master_receive(LINV2_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length; + + /** waiting for lin inactive */ + while (lin_is_active(ptr)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + /** config id */ + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK | LINV2_DATA_LEN_ID_ID_SET(config->id); + } else { + data_length = config->data_length; + ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length) | LINV2_DATA_LEN_ID_ID_SET(config->id); + } + + /** receive */ + ptr->CONTROL_STATUS = 0U; + /** start */ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_START_REQ_MASK; + + /** waiting for receive complete */ + retry = 0; + while (!lin_is_complete(ptr)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_fail; + } + + /** load register data into buffer */ + for (uint8_t i = 0; i < data_length; i++) { + *((config->data_buff)++) = ptr->DATA_BYTE[i]; + } + + return status_success; +} + +void lin_slave_transfer(LINV2_Type *ptr, lin_trans_config_t *config) +{ + uint8_t data_length; + + /** transmit or receive */ + ptr->CONTROL_STATUS &= ~LINV2_CONTROL_STATUS_TRANSMIT_MASK; + if (config->transmit) { + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_TRANSMIT_MASK; + } + + /* clean enh_check and data_len */ + ptr->DATA_LEN_ID &= ~(LINV2_DATA_LEN_ID_ENH_CHECK_MASK | LINV2_DATA_LEN_ID_DATA_LEN_MASK); + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length); + } + + if (config->transmit) { + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATA_BYTE[i] = *((config->data_buff)++); + } + } + + /** data ack */ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_DATA_ACK_MASK; +} + +hpm_stat_t lin_slave_sent(LINV2_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length; + + /** waiting for lin data_req */ + while (!((ptr->CONTROL_STATUS & LINV2_CONTROL_STATUS_DATA_REQ_MASK) == LINV2_CONTROL_STATUS_DATA_REQ_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + /** transmit */ + ptr->CONTROL_STATUS = LINV2_CONTROL_STATUS_TRANSMIT_MASK; + + /* clean enh_check and data_len */ + ptr->DATA_LEN_ID &= ~(LINV2_DATA_LEN_ID_ENH_CHECK_MASK | LINV2_DATA_LEN_ID_DATA_LEN_MASK); + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length); + } + + for (uint8_t i = 0; i < data_length; i++) { + ptr->DATA_BYTE[i] = *((config->data_buff)++); + } + + /** data ack */ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_DATA_ACK_MASK; + + /** waiting for lin complete */ + retry = 0; + while (!lin_is_complete(ptr)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_timeout; + } + return status_success; +} + +hpm_stat_t lin_slave_receive(LINV2_Type *ptr, lin_trans_config_t *config) +{ + uint32_t retry = 0; + uint8_t data_length; + + /** waiting for lin data_req */ + while (!((ptr->CONTROL_STATUS & LINV2_CONTROL_STATUS_DATA_REQ_MASK) == LINV2_CONTROL_STATUS_DATA_REQ_MASK)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT) { + return status_timeout; + } + + /** receive */ + ptr->CONTROL_STATUS = 0U; + + /* clean enh_check and data_len */ + ptr->DATA_LEN_ID &= ~(LINV2_DATA_LEN_ID_ENH_CHECK_MASK | LINV2_DATA_LEN_ID_DATA_LEN_MASK); + if (config->data_length_from_id) { + data_length = lin_get_data_length_from_id(lin_get_id(ptr)); + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK; + } else { + data_length = config->data_length; + ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length); + } + + /** data ack */ + ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_DATA_ACK_MASK; + + /** waiting for lin complete */ + retry = 0; + while (!lin_is_complete(ptr)) { + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + break; + } + retry++; + } + + if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { + return status_timeout; + } + + for (uint8_t i = 0; i < data_length; i++) { + *((config->data_buff)++) = ptr->DATA_BYTE[i]; + } + + return status_success; +} + +void lin_slave_dma_transfer(LINV2_Type *ptr, lin_trans_config_t *config) +{ + ptr->DMA_CONTROL = LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK + | LINV2_DMA_CONTROL_DMA_REQ_ID_SET(config->id) + | LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SET(config->transmit) + | LINV2_DMA_CONTROL_DMA_REQ_LEN_SET(config->data_length) + | LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SET(config->enhanced_checksum); +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c new file mode 100644 index 00000000..e3d94bfd --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_lvb_drv.h" + +void lvb_get_default_config(lvb_config_t *cfg) +{ + cfg->split_ch_is_reverse = false; + cfg->split_ch_data_is_unaligned = false; + cfg->split_hswhbp_width_is_even = true; + cfg->split_mode_en = false; + cfg->di0_vsync_polarity = lvb_di_vsync_polarity_active_high; + cfg->di1_vsync_polarity = lvb_di_vsync_polarity_active_high; + cfg->txclk_shift = lvb_txclk_shift_1100011; +} + +void lvb_init(LVB_Type *ptr, lvb_config_t *cfg) +{ + ptr->CONTROL[0] = (ptr->CONTROL[0] & ~(LVB_CONTROL_SPLIT_CH_REVERSE_MASK | + LVB_CONTROL_SPLIT_CH_MODE_MASK | + LVB_CONTROL_SPLIT_HSWHBP_WIDTH_MASK | + LVB_CONTROL_SPLIT_MODE_EN_MASK | + LVB_CONTROL_DI1_VSYNC_POLARITY_MASK | + LVB_CONTROL_DI0_VSYNC_POLARITY_MASK | + LVB_CONTROL_LVDS_TXCLK_SHIFT_MASK)) | + LVB_CONTROL_SPLIT_CH_REVERSE_SET(cfg->split_ch_is_reverse) | + LVB_CONTROL_SPLIT_CH_MODE_SET(cfg->split_ch_data_is_unaligned) | + LVB_CONTROL_SPLIT_HSWHBP_WIDTH_SET(cfg->split_hswhbp_width_is_even) | + LVB_CONTROL_SPLIT_MODE_EN_SET(cfg->split_mode_en) | + LVB_CONTROL_DI1_VSYNC_POLARITY_SET(cfg->di1_vsync_polarity) | + LVB_CONTROL_DI0_VSYNC_POLARITY_SET(cfg->di0_vsync_polarity) | + LVB_CONTROL_LVDS_TXCLK_SHIFT_SET(cfg->txclk_shift); +} + +void lvb_get_ch_default_config(lvb_ch_config_t *ch_cfg) +{ + ch_cfg->data_src = lvb_ch_data_source_di0; + ch_cfg->map = lvb_ch_mapping_vesa; +} + +void lvb_ch_config(LVB_Type *ptr, lvb_ch_num_t ch_num, lvb_ch_config_t *ch_cfg) +{ + uint32_t reg_val; + + if (ch_num == lvb_ch_num_0) { + reg_val = (ptr->CONTROL[0] & ~(LVB_CONTROL_CH0_BIT_MAPPING_MASK | LVB_CONTROL_CH0_SEL_MASK)) | + LVB_CONTROL_CH0_BIT_MAPPING_SET(ch_cfg->map) | + LVB_CONTROL_CH0_SEL_SET(ch_cfg->data_src); + } else { + reg_val = (ptr->CONTROL[0] & ~(LVB_CONTROL_CH1_BIT_MAPPING_MASK | LVB_CONTROL_CH1_SEL_MASK)) | + LVB_CONTROL_CH1_BIT_MAPPING_SET(ch_cfg->map) | + LVB_CONTROL_CH1_SEL_SET(ch_cfg->data_src); + } + + ptr->CONTROL[0] = reg_val; +} + +void lvb_ch_enable(LVB_Type *ptr, lvb_ch_num_t ch_num) +{ + if (ch_num == lvb_ch_num_0) { + ptr->CONTROL[0] |= LVB_CONTROL_CH0_EN_MASK; + } else { + ptr->CONTROL[0] |= LVB_CONTROL_CH1_EN_MASK; + } +} + +void lvb_ch_disable(LVB_Type *ptr, lvb_ch_num_t ch_num) +{ + if (ch_num == lvb_ch_num_0) { + ptr->CONTROL[0] &= ~LVB_CONTROL_CH0_EN_MASK; + } else { + ptr->CONTROL[0] &= ~LVB_CONTROL_CH1_EN_MASK; + } +} + +void lvb_lvds_phy_lane_data_get_default_config(lvb_lvds_phy_lane_config_t *cfg) +{ + cfg->tx_idle = false; + cfg->rterm_enable = true; + cfg->phase_sel = lvb_lvds_lane_phase_sel_4_16_ui; + cfg->amp = lvb_lvds_lane_amp_300_mv; + cfg->vcom = lvb_lvds_lane_vcom_1_2_v; + cfg->fvco_div4 = true; +} + +void lvb_lvds_phy_lane_init(LVB_Type *ptr, lvb_lvds_lane_idx_t tx_index, lvb_lvds_phy_lane_config_t *cfg) +{ + ptr->TX_PHY[tx_index].CTL0 = (ptr->TX_PHY[tx_index].CTL0 & ~(LVB_TX_PHY_CTL0_TX_IDLE_MASK | + LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK | + LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK | + LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK | + LVB_TX_PHY_CTL0_TX_VCOM_MASK | + LVB_TX_PHY_CTL0_TX_AMP_MASK)) | + (cfg->tx_idle ? LVB_TX_PHY_CTL0_TX_IDLE_MASK : 0) | + (cfg->rterm_enable ? LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK : 0) | + LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SET(2) | /* only 7bit */ + LVB_TX_PHY_CTL0_TX_PHASE_SEL_SET(cfg->phase_sel) | + LVB_TX_PHY_CTL0_TX_VCOM_SET(cfg->vcom) | + LVB_TX_PHY_CTL0_TX_AMP_SET(cfg->amp); + + if (cfg->fvco_div4) { + ptr->TX_PHY[tx_index].CTL0 |= (1ul<<7); + } else { + ptr->TX_PHY[tx_index].CTL0 &= ~(1ul<<7); + } +} + +void lvb_lvds_phy0_poweron(LVB_Type *ptr) +{ + ptr->PHY_POW_CTRL[0] = (ptr->PHY_POW_CTRL[0] & ~(LVB_PHY_POW_CTRL_TXCK_PD_MASK | + LVB_PHY_POW_CTRL_TX3_PD_MASK | LVB_PHY_POW_CTRL_TX2_PD_MASK | + LVB_PHY_POW_CTRL_TX1_PD_MASK | LVB_PHY_POW_CTRL_TX0_PD_MASK)) | + LVB_PHY_POW_CTRL_PWON_PLL_MASK; +} + +void lvb_lvds_phy1_poweron(LVB_Type *ptr) +{ + ptr->PHY_POW_CTRL[1] = (ptr->PHY_POW_CTRL[1] & ~(LVB_PHY_POW_CTRL_TXCK_PD_MASK | + LVB_PHY_POW_CTRL_TX3_PD_MASK | LVB_PHY_POW_CTRL_TX2_PD_MASK | + LVB_PHY_POW_CTRL_TX1_PD_MASK | LVB_PHY_POW_CTRL_TX0_PD_MASK)) | + LVB_PHY_POW_CTRL_PWON_PLL_MASK; +} + +void lvb_lvds_phy0_powerdown(LVB_Type *ptr) +{ + ptr->PHY_POW_CTRL[0] = (ptr->PHY_POW_CTRL[0] & ~LVB_PHY_POW_CTRL_PWON_PLL_MASK) | + LVB_PHY_POW_CTRL_TXCK_PD_MASK | LVB_PHY_POW_CTRL_TX3_PD_MASK | + LVB_PHY_POW_CTRL_TX2_PD_MASK | LVB_PHY_POW_CTRL_TX1_PD_MASK | + LVB_PHY_POW_CTRL_TX0_PD_MASK; +} + +void lvb_lvds_phy1_powerdown(LVB_Type *ptr) +{ + ptr->PHY_POW_CTRL[1] = (ptr->PHY_POW_CTRL[1] & ~LVB_PHY_POW_CTRL_PWON_PLL_MASK) | + LVB_PHY_POW_CTRL_TXCK_PD_MASK | LVB_PHY_POW_CTRL_TX3_PD_MASK | + LVB_PHY_POW_CTRL_TX2_PD_MASK | LVB_PHY_POW_CTRL_TX1_PD_MASK | + LVB_PHY_POW_CTRL_TX0_PD_MASK; +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c index b3942daf..659aebf1 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c @@ -8,14 +8,24 @@ #include #include -#define MCAN_CAN_BAUDRATE_DEFAULT (500UL * 1000UL) /*!< Default CAN2.0 baudrate:500 kbps */ -#define MCAN_CANFD_BAUDRATE_DEFAULT (2UL * 1000UL * 1000UL) /*!< Default CANFD baudrate: 2 Mbps */ - /*********************************************************************************************************************** * * Definitions * **********************************************************************************************************************/ + +#define MCAN_CAN_BAUDRATE_DEFAULT (500UL * 1000UL) /*!< Default CAN2.0 baudrate:500 kbps */ +#define MCAN_CANFD_BAUDRATE_DEFAULT (2UL * 1000UL * 1000UL) /*!< Default CANFD baudrate: 2 Mbps */ + +/* Hardware restriction of each types of element for MCAN */ +#define MCAN_STD_FILTER_ELEM_CNT_MAX (128U) +#define MCAN_EXT_FILTER_ELEM_CNT_MAX (64U) +#define MCAN_RXFIFO_ELEM_CNT_MAX (64U) +#define MCAN_RXBUF_ELEM_CNT_MAX (64U) +#define MCAN_TXEVT_FIFO_ELEM_CNT_MAX (32U) +#define MCAN_TXBUF_ELEM_CNT_MAX (32U) + + #define NUM_TQ_SYNC_SEG (1U) /** @@ -625,7 +635,12 @@ void mcan_get_default_config(MCAN_Type *ptr, mcan_config_t *config) /* Default TSU configuration */ mcan_tsu_config_t *tsu_config = &config->tsu_config; tsu_config->prescaler = 1U; - tsu_config->ext_timebase_src = MCAN_TSU_EXT_TIMEBASE_SRC_PTP; +#if defined(MCAN_SOC_TSU_SRC_TWO_STAGES) && (MCAN_SOC_TSU_SRC_TWO_STAGES == 1) + tsu_config->ext_timebase_src = MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_0; + tsu_config->tbsel_option = MCAN_TSU_TBSEL_PTPC0; +#else + tsu_config->ext_timebase_src = MCAN_TSU_EXT_TIMEBASE_SRC_PTPC; +#endif tsu_config->use_ext_timebase = false; tsu_config->capture_on_sof = false; tsu_config->enable_tsu = false; @@ -648,6 +663,9 @@ hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) uint32_t elem_count; uint32_t start_addr = mcan_get_ram_offset(ptr); if (config->enable_std_filter) { + if (config->std_filter_elem_count > MCAN_STD_FILTER_ELEM_CNT_MAX) { + break; + } mcan_filter_config_t filter_config = { .reg_val = 0 }; filter_config.list_size = config->std_filter_elem_count; filter_config.list_start_addr = start_addr; @@ -658,6 +676,9 @@ hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) } if (config->enable_ext_filter) { + if (config->ext_filter_elem_count > MCAN_EXT_FILTER_ELEM_CNT_MAX) { + break; + } mcan_filter_config_t filter_config = { .reg_val = 0 }; filter_config.list_size = config->ext_filter_elem_count; filter_config.list_start_addr = start_addr; @@ -671,9 +692,12 @@ hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) for (uint32_t i = 0; i < ARRAY_SIZE(config->rxfifos); i++) { if (config->rxfifos[i].enable) { - elem_bytes = - mcan_get_data_field_size(config->rxfifos[i].data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; + elem_bytes = mcan_get_data_field_size(config->rxfifos[i].data_field_size) + + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; elem_count = config->rxfifos[i].elem_count; + if (elem_count > MCAN_RXFIFO_ELEM_CNT_MAX) { + return status_invalid_argument; + } mcan_rxfifo_config_t rxfifo_config = { .reg_val = 0 }; rxfifo_config.start_addr = start_addr; rxfifo_config.watermark = 1U; @@ -701,10 +725,13 @@ hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) if (config->enable_rxbuf) { elem_bytes = mcan_get_data_field_size(config->rxbuf_data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; elem_count = config->rxbuf_elem_count; + if (elem_count > MCAN_RXFIFO_ELEM_CNT_MAX) { + break; + } ptr->RXBC = start_addr; rx_fifo_buf_elem_config.buf_data_field_size = config->rxbuf_data_field_size; - start_addr += elem_bytes * elem_count;; + start_addr += elem_bytes * elem_count; } else { rx_fifo_buf_elem_config.buf_data_field_size = 0; ptr->RXBC = MCAN_RAM_ADDR_INVALID; @@ -719,6 +746,10 @@ hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) txbuf_config.tx_fifo_queue_mode = config->txfifo_or_txqueue_mode; elem_count = config->txbuf_fifo_or_queue_elem_count + config->txbuf_dedicated_txbuf_elem_count; + if (elem_count > MCAN_TXEVT_FIFO_ELEM_CNT_MAX) { + break; + } + elem_bytes = mcan_get_data_field_size(config->txbuf_data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; start_addr += elem_count * elem_bytes; @@ -733,6 +764,10 @@ hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) if (config->enable_tx_evt_fifo) { elem_bytes = sizeof(mcan_tx_event_fifo_elem_t); elem_count = config->tx_evt_fifo_elem_count; + if (elem_count > MCAN_TXEVT_FIFO_ELEM_CNT_MAX) { + break; + } + txevt_fifo_config.start_addr = start_addr; txevt_fifo_config.fifo_size = elem_count; txevt_fifo_config.fifo_watermark = 1U; @@ -762,30 +797,45 @@ hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexibl hpm_stat_t status = status_invalid_argument; do { if (config->enable_std_filter) { + if (config->std_filter_config.list_size > MCAN_STD_FILTER_ELEM_CNT_MAX) { + break; + } ptr->SIDFC = config->std_filter_config.reg_val; } else { ptr->SIDFC = MCAN_RAM_ADDR_INVALID; } if (config->enable_ext_filter) { + if (config->std_filter_config.list_size > MCAN_EXT_FILTER_ELEM_CNT_MAX) { + break; + } ptr->XIDFC = config->ext_filter_config.reg_val; } else { ptr->XIDFC = MCAN_RAM_ADDR_INVALID; } if (config->enable_rxfifo0) { + if (config->rxfifo0_config.fifo_size > MCAN_RXFIFO_ELEM_CNT_MAX) { + break; + } ptr->RXF0C = config->rxfifo0_config.reg_val; } else { ptr->RXF0C = MCAN_RAM_ADDR_INVALID; } if (config->enable_rxfifo1) { + if (config->rxfifo1_config.fifo_size > MCAN_RXFIFO_ELEM_CNT_MAX) { + break; + } ptr->RXF1C = config->rxfifo1_config.reg_val; } else { ptr->RXF1C = MCAN_RAM_ADDR_INVALID; } if (config->enable_rxbuf) { + /* NOTE: There is no register field for SW to validate the rxbuf element count, + * users should ensure the parameters are in valid range. + */ ptr->RXBC = config->rxbuf_config.start_addr; } else { ptr->RXBC = MCAN_RAM_ADDR_INVALID; @@ -793,6 +843,10 @@ hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexibl ptr->RXESC = config->rx_elem_config.reg_val; if (config->enable_txbuf) { + uint32_t tx_fifo_size = config->txbuf_config.fifo_queue_size + config->txbuf_config.dedicated_tx_buf_size; + if (tx_fifo_size > MCAN_TXBUF_ELEM_CNT_MAX) { + break; + } ptr->TXESC = config->txbuf_elem_config.data_field_size; } else { ptr->TXESC = MCAN_RAM_ADDR_INVALID; @@ -801,6 +855,9 @@ hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexibl ptr->TXBC = config->txbuf_config.reg_val; if (config->enable_tx_evt_fifo) { + if (config->tx_evt_fifo_config.fifo_size > MCAN_TXEVT_FIFO_ELEM_CNT_MAX) { + break; + } ptr->TXEFC = config->tx_evt_fifo_config.reg_val; } else { ptr->TXEFC = MCAN_RAM_ADDR_INVALID; @@ -896,6 +953,9 @@ static hpm_stat_t mcan_set_tsu(MCAN_Type *ptr, mcan_tsu_config_t *config) if (config->use_ext_timebase) { tscfg |= MCAN_TSCFG_TBCS_MASK; mcan_set_tsu_ext_timebase_src(ptr, config->ext_timebase_src); +#if defined(MCAN_SOC_TSU_SRC_TWO_STAGES) && (MCAN_SOC_TSU_SRC_TWO_STAGES == 1) + mcan_set_tsu_tbsel_option(ptr, config->ext_timebase_src, config->tbsel_option); +#endif } if (config->enable_64bit_timestamp) { tscfg |= MCAN_TSCFG_EN64_MASK; @@ -937,10 +997,32 @@ hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_fre break; } - ptr->CCCR |= MCAN_CCCR_INIT_MASK; - while ((ptr->CCCR & MCAN_CCCR_INIT_MASK) == 0) { + mcan_enable_clock(ptr); + uint32_t retry_cnt = 10000UL; + do { + retry_cnt--; + if (retry_cnt == 0UL) { + break; + } + } while (!mcan_is_clock_enabled(ptr)); + if (retry_cnt == 0UL) { + status = status_timeout; + break; + } + ptr->CCCR |= MCAN_CCCR_INIT_MASK; + retry_cnt = 10000UL; + while ((ptr->CCCR & MCAN_CCCR_INIT_MASK) == 0U) { + retry_cnt--; + if (retry_cnt == 0UL) { + break; + } + } + if (retry_cnt == 0UL) { + status = status_timeout; + break; } + ptr->CCCR |= MCAN_CCCR_CCE_MASK; if (!config->use_lowlevel_timing_setting) { @@ -1027,6 +1109,18 @@ hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_fre ptr->CCCR &= ~MCAN_CCCR_EFBI_MASK; } + if (config->disable_auto_retransmission) { + ptr->CCCR |= MCAN_CCCR_DAR_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_DAR_MASK; + } + + if (config->enable_restricted_operation_mode) { + ptr->CCCR |= MCAN_CCCR_ASM_MASK; + } else { + ptr->CCCR &= ~MCAN_CCCR_ASM_MASK; + } + /* Configure Transmitter Delay Compensation */ if (config->enable_tdc) { ptr->DBTP |= MCAN_DBTP_TDC_MASK; @@ -1070,6 +1164,15 @@ hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_fre status = mcan_config_all_filters(ptr, &config->all_filters_config); HPM_BREAK_IF(status != status_success); + /* Disable all interrupts by default */ + mcan_disable_interrupts(ptr, ~0UL); + mcan_disable_txbuf_transmission_interrupt(ptr, ~0UL); + mcan_disable_txbuf_cancel_finish_interrupt(ptr, ~0UL); + /* Enable interrupts on demand */ + mcan_enable_interrupts(ptr, config->interrupt_mask); + mcan_enable_txbuf_transmission_interrupt(ptr, config->txbuf_trans_interrupt_mask); + mcan_enable_txbuf_cancel_finish_interrupt(ptr, config->txbuf_cancel_finish_interrupt_mask); + /* Clear all Interrupt Flags */ mcan_clear_interrupt_flags(ptr, ~0UL); @@ -1084,6 +1187,42 @@ hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_fre return status; } +void mcan_deinit(MCAN_Type *ptr) +{ + if (ptr != NULL) { + + mcan_enter_init_mode(ptr); /* Stop MCAN function */ + + /* Enable write access to protected configuration registers */ + mcan_enable_write_to_prot_config_registers(ptr); + + /* Restore critical registers to default values */ + ptr->RWD = 0UL; + ptr->TSCC = 0UL; + ptr->GFC = 0UL; + ptr->SIDFC = 0UL; + ptr->XIDAM = 0UL; + ptr->XIDAM = 0x1FFFFFFFUL; + ptr->RXBC = 0UL; + ptr->RXF1C = 0UL; + ptr->RXESC = 0UL; + ptr->TXBC = 0UL; + ptr->TXESC = 0UL; + ptr->TXEFC = 0UL; + + ptr->TSCFG = 0UL; + + /* Disable all interrupts and clear all flags */ + mcan_disable_interrupts(ptr, ~0UL); + mcan_clear_interrupt_flags(ptr, ~0UL); + mcan_disable_txbuf_transmission_interrupt(ptr, ~0UL); + mcan_disable_txbuf_cancel_finish_interrupt(ptr, ~0UL); + + /* Restore CCCR to default value */ + ptr->CCCR = MCAN_CCCR_INIT_MASK; + } +} + hpm_stat_t mcan_set_filter_element(MCAN_Type *ptr, const mcan_filter_elem_t *filter_elem, uint32_t index) { hpm_stat_t status = status_invalid_argument; @@ -1463,20 +1602,12 @@ hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame) { hpm_stat_t status = status_invalid_argument; do { - if ((ptr == NULL) || (tx_frame == NULL)) { - break; - } - if (mcan_is_txfifo_full(ptr)) { - status = status_mcan_txfifo_full; + uint32_t put_index = 0; + status = mcan_transmit_via_txfifo_nonblocking(ptr, tx_frame, &put_index); + if (status != status_success) { break; } - status = mcan_write_txfifo(ptr, tx_frame); - HPM_BREAK_IF(status != status_success); - - uint32_t put_index = mcan_get_txfifo_put_index(ptr); - mcan_send_add_request(ptr, put_index); - uint32_t retry_cnt = 0; while (!mcan_is_transmit_occurred(ptr, put_index)) { retry_cnt++; @@ -1493,6 +1624,35 @@ hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame) return status; } +hpm_stat_t mcan_transmit_via_txfifo_nonblocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame, uint32_t *fifo_index) +{ + hpm_stat_t status = status_invalid_argument; + do { + if ((ptr == NULL) || (tx_frame == NULL)) { + break; + } + if (mcan_is_txfifo_full(ptr)) { + status = status_mcan_txfifo_full; + break; + } + + status = mcan_write_txfifo(ptr, tx_frame); + HPM_BREAK_IF(status != status_success); + + uint32_t put_index = mcan_get_txfifo_put_index(ptr); + mcan_send_add_request(ptr, put_index); + + if (fifo_index != NULL) { + *fifo_index = put_index; + } + + status = status_success; + + } while (false); + + return status; +} + hpm_stat_t mcan_receive_from_buf_blocking(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame) { hpm_stat_t status = status_invalid_argument; @@ -1683,3 +1843,55 @@ hpm_stat_t mcan_get_timestamp_from_received_message(MCAN_Type *ptr, return status; } + +hpm_stat_t mcan_parse_protocol_status(uint32_t psr, mcan_protocol_status_t *protocol_status) +{ + if (protocol_status == NULL) { + return status_invalid_argument; + } + memset(protocol_status, 0, sizeof(mcan_protocol_status_t)); + uint32_t psr_val = psr; + if (MCAN_PSR_PXE_GET(psr_val) != 0U) { + protocol_status->protocol_exception_evt_occurred = true; + } + if (MCAN_PSR_RFDF_GET(psr_val) != 0U) { + protocol_status->canfd_msg_received = true; + } + if (MCAN_PSR_RBRS_GET(psr_val) != 0U) { + protocol_status->brs_flag_set_in_last_rcv_canfd_msg = true; + } + if (MCAN_PSR_RESI_GET(psr_val) != 0U) { + protocol_status->esi_flag_set_in_last_rcv_canfd_msg = true; + } + if (MCAN_PSR_BO_GET(psr_val) != 0U) { + protocol_status->in_bus_off_state = true; + } + if (MCAN_PSR_EW_GET(psr_val) != 0U) { + protocol_status->in_warning_state = true; + } + if (MCAN_PSR_EP_GET(psr_val) != 0U) { + protocol_status->in_error_passive_state = true; + } + protocol_status->activity = (mcan_activity_state_t) MCAN_PSR_ACT_GET(psr_val); + protocol_status->tdc_val = MCAN_PSR_TDCV_GET(psr_val); + + if (protocol_status->brs_flag_set_in_last_rcv_canfd_msg) { + protocol_status->last_error_code = (mcan_last_err_code_t) MCAN_PSR_DLEC_GET(psr_val); + } else { + protocol_status->last_error_code = (mcan_last_err_code_t) MCAN_PSR_LEC_GET(psr_val); + } + return status_success; +} + +hpm_stat_t mcan_get_protocol_status(MCAN_Type *ptr, mcan_protocol_status_t *protocol_status) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF((ptr == NULL) || (protocol_status == NULL)); + status = mcan_parse_protocol_status(ptr->PSR, protocol_status); + + } while (false); + + return status; +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c new file mode 100644 index 00000000..1e98e636 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_mmc_drv.h" + +void mmc_track_config_pos_mode(MMC_Type *base, mmc_track_pos_mode_t *mode) +{ + if (mode->discrete_pos_mode) { + base->CR |= MMC_CR_DISCRETETRC_MASK; + base->DISCRETECFG0 = MMC_DISCRETECFG0_POSMAX_SET(mode->discrete_line); + uint32_t inv_line = (uint32_t)(100000000UL / mode->discrete_line); + base->DISCRETECFG1 = MMC_DISCRETECFG1_INV_POSMAX_SET(inv_line); + } else { + base->CR &= ~MMC_CR_DISCRETETRC_MASK; + base->DISCRETECFG1 = MMC_DISCRETECFG1_INV_POSMAX_SET(mode->continuous_step_thr); + base->CONTCFG0 = MMC_CONTCFG0_HALF_CIRC_THETA_SET(mode->continuous_circ_thr); + } + + base->OOSYNC_THETA_THR = MMC_OOSYNC_THETA_THR_VAL_SET(mode->oosync_theta_thr); +} + +void mmc_track_get_default_mode_config(MMC_Type *base, mmc_track_mode_t *config) +{ + config->force_accel_to_zero = false; + config->en_ms_coef = false; + config->open_loop_mode = false; + config->pos_16bit_type = false; + config->sync_new_pos = false; + + config->pos_mode.discrete_pos_mode = false; + config->pos_mode.discrete_line = 0x10000; + config->pos_mode.continuous_step_thr = 0x1000000; + config->pos_mode.continuous_circ_thr = 0x1000000; + config->pos_mode.oosync_theta_thr = 0x1000000; +} + +void mmc_track_config_mode(MMC_Type *base, mmc_track_mode_t *config) +{ + base->CR &= ~(MMC_CR_FRCACCELZERO_MASK + | MMC_CR_MS_COEF_EN_MASK + | MMC_CR_OPEN_LOOP_MODE_MASK + | MMC_CR_POS_TYPE_MASK + | MMC_CR_ADJOP_MASK); + + base->CR |= MMC_CR_FRCACCELZERO_SET(config->force_accel_to_zero) + | MMC_CR_MS_COEF_EN_SET(config->en_ms_coef) + | MMC_CR_OPEN_LOOP_MODE_SET(config->open_loop_mode) + | MMC_CR_POS_TYPE_SET(config->pos_16bit_type) + | MMC_CR_ADJOP_SET(config->sync_new_pos); + + mmc_track_config_pos_mode(base, &config->pos_mode); +} + +void mmc_get_default_pos_or_delta_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para) +{ + para->pos_time = 0; + para->position = 0; + para->revolution = 0; + para->speed = 0; + para->accel = 0; + para->cmd_mask = mmc_pos_update_all; + para->trigger = mmc_pos_update_by_timestamp; +} + +void mmc_track_config_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para) +{ + /* speed and accel has 19bit decimal */ + int32_t speed = (int32_t)(para->speed * (1 << 19U)); + int32_t accel = (int32_t)(para->accel * (1 << 19U)); + + base->INI_SPEED = speed; + base->INI_ACCEL = accel; + base->INI_POS = para->position; + base->INI_REV = para->revolution; + base->INI_POS_TIME = para->pos_time; + + base->CR &= ~(MMC_CR_INI_POS_TRG_TYPE_MASK | MMC_CR_INI_POS_CMD_MSK_MASK | MMC_CR_INI_POS_REQ_MASK); + base->CR |= MMC_CR_INI_POS_TRG_TYPE_SET((para->trigger)) + | MMC_CR_INI_POS_CMD_MSK_SET(para->cmd_mask) + | MMC_CR_INI_POS_REQ_MASK; +} + +void mmc_track_config_delta_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para) +{ + int32_t speed = (int32_t)(para->speed * (1 << 19U)); + int32_t accel = (int32_t)(para->accel * (1 << 19U)); + + base->INI_DELTA_SPEED = speed; + base->INI_DELTA_ACCEL = accel; + base->INI_DELTA_POS = para->position; + base->INI_DELTA_REV = para->revolution; + base->INI_DELTA_POS_TIME = para->pos_time; + + base->CR &= ~(MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK | MMC_CR_INI_DELTA_POS_CMD_MSK_MASK | MMC_CR_INI_DELTA_POS_REQ_MASK); + base->CR |= MMC_CR_INI_DELTA_POS_TRG_TYPE_SET((para->trigger)) + | MMC_CR_INI_DELTA_POS_CMD_MSK_SET(para->cmd_mask) + | MMC_CR_INI_DELTA_POS_REQ_MASK; +} + +void mmc_track_config_coef_para(MMC_Type *base, mmc_coef_input_t *para) +{ + int32_t coef_p = (int32_t)(para->coef_p * (1 << 15U)); + int32_t coef_i = (int32_t)(para->coef_i * (1 << 21U)); + int32_t coef_a = (int32_t)(para->coef_a * (1 << 19U)); + + base->INI_PCOEF = coef_p; + base->INI_ICOEF = coef_i; + base->INI_ACOEF = coef_a; + base->INI_COEF_TIME = para->coef_time; + + base->CR &= ~(MMC_CR_INI_COEFS_CMD_MSK_MASK | MMC_CR_INI_COEFS_CMD_MASK); + base->CR |= MMC_CR_INI_COEFS_CMD_MSK_SET(para->cmd_mask) + | MMC_CR_INI_COEFS_CMD_MASK; +} + +void mmc_track_config_coef_trig(MMC_Type *base, uint8_t index, mmc_coef_trig_config_t *config) +{ + int32_t coef_p = (int32_t)(config->coef_p * (1 << 15U)); + int32_t coef_i = (int32_t)(config->coef_i * (1 << 21U)); + int32_t coef_a = (int32_t)(config->coef_a * (1 << 19U)); + + base->COEF_TRG_CFG[index].P = coef_p; + base->COEF_TRG_CFG[index].I = coef_i; + base->COEF_TRG_CFG[index].A = coef_a; + base->COEF_TRG_CFG[index].TIME = config->hold_time; + base->COEF_TRG_CFG[index].ERR_THR = config->err_thr; +} + +void mmc_track_get_result(MMC_Type *base, mmc_pos_out_t *pos_out, mmc_coef_out_t *coef_out) +{ + /* mmc_track_enable_shadow_read(base); */ + + base->CR |= MMC_CR_SHADOW_RD_REQ_MASK; + while ((base->CR & MMC_CR_SHADOW_RD_REQ_MASK) == MMC_CR_SHADOW_RD_REQ_MASK) { + } + + if (pos_out != NULL) { + pos_out->time = base->ESTM_TIM; + pos_out->position = base->ESTM_POS; + pos_out->revolution = (int32_t)base->ESTM_REV; + + int32_t speed = base->ESTM_SPEED; + int32_t accel = base->ESTM_ACCEL; + + pos_out->speed = (double)speed / (1 << 19U); + pos_out->accel = (double)accel / (1 << 19U); + } + + if (coef_out != NULL) { + int32_t coef_p = base->CUR_PCOEF; + int32_t coef_i = base->CUR_ICOEF; + int32_t coef_a = base->CUR_ACOEF; + + coef_out->coef_p = (double)coef_p / (1 << 15U); + coef_out->coef_i = (double)coef_i / (1 << 21U); + coef_out->coef_a = (double)coef_a / (1 << 19U); + } +} + + +void mmc_pred_get_default_mode_config(MMC_Type *base, mmc_pred_mode_t *config) +{ + config->speed_trig_int = false; + config->position_trig_int = false; + config->delta_pos_done_trig_int = false; + + + config->open_loop_mode = false; + config->pred_mode = 0; + config->not_first_pred_trig_type = 0; + config->first_pred_trig_type = 0; +} + +void mmc_pred_config_mode(MMC_Type *base, uint8_t index, mmc_pred_mode_t *config) +{ + base->BR[index].BR_CTRL &= ~(MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK + | MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK + | MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK + | MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK + | MMC_BR_BR_CTRL_PRED_MODE_MASK + | MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK + | MMC_BR_BR_CTRL_F_TRG_TYPE_MASK); + + base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SET(config->speed_trig_int) + | MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SET(config->position_trig_int) + | MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SET(config->delta_pos_done_trig_int) + | MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SET(config->open_loop_mode) + | MMC_BR_BR_CTRL_PRED_MODE_SET(config->pred_mode) + | MMC_BR_BR_CTRL_NF_TRG_TYPE_SET(config->not_first_pred_trig_type) + | MMC_BR_BR_CTRL_F_TRG_TYPE_SET(config->first_pred_trig_type); +} + +void mmc_pred_config_pos_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para, bool req_reload) +{ + /* speed and accel has 19bit decimal */ + int32_t speed = (int32_t)(para->speed * (1 << 19U)); + int32_t accel = (int32_t)(para->accel * (1 << 19U)); + + base->BR[index].BR_INI_SPEED = speed; + base->BR[index].BR_INI_ACCEL = accel; + base->BR[index].BR_INI_POS = para->position; + base->BR[index].BR_INI_REV = para->revolution; + base->BR[index].BR_INI_POS_TIME = para->pos_time; + + base->BR[index].BR_CTRL &= ~(MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK | MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK); + base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SET((para->trigger)) + | MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SET(para->cmd_mask); + + if (req_reload) { + base->CR |= (1U << (MMC_CR_INI_BR0_POS_REQ_SHIFT - index)); + } +} + +void mmc_pred_config_delta_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para) +{ + int32_t speed = (int32_t)(para->speed * (1 << 19U)); + int32_t accel = (int32_t)(para->accel * (1 << 19U)); + + base->BR[index].BR_INI_DELTA_SPEED = speed; + base->BR[index].BR_INI_DELTA_ACCEL = accel; + base->BR[index].BR_INI_DELTA_POS = para->position; + base->BR[index].BR_INI_DELTA_REV = para->revolution; + base->BR[index].BR_INI_DELTA_POS_TIME = para->pos_time; + + base->BR[index].BR_CTRL &= ~(MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK + | MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK + | MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK); + + base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SET(para->trigger) + | MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SET(para->cmd_mask) + | MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK; +} + +/* 不需要shadow吗 */ +void mmc_pred_get_result(MMC_Type *base, uint8_t index, mmc_pos_out_t *pos_out) +{ + pos_out->time = base->BR[index].BR_CUR_POS_TIME; + pos_out->position = base->BR[index].BR_CUR_POS; + pos_out->revolution = (int32_t)base->BR[index].BR_CUR_REV; + + int32_t speed = base->BR[index].BR_CUR_SPEED; + int32_t accel = base->BR[index].BR_CUR_ACCEL; + + pos_out->speed = (double)speed / (1 << 19U); + pos_out->accel = (double)accel / (1 << 19U); +} + +void mmc_pred_config_period_time(MMC_Type *base, uint8_t index, mmc_pred_period_time_t *time) +{ + base->BR[index].BR_TIMEOFF = time->offset_time; + base->BR[index].BR_TRG_PERIOD = time->period_time; + base->BR[index].BR_TRG_F_TIME = time->first_time; +} + +void mmc_pred_config_position_trig(MMC_Type *base, uint8_t index, mmc_pos_trig_t *trig) +{ + base->BR[index].BR_TRG_POS_THR = trig->position_thr; + base->BR[index].BR_TRG_REV_THR = trig->revolution_thr; + + base->BR[index].BR_TRG_POS_CFG = MMC_BR_BR_TRG_POS_CFG_EDGE_SET(trig->less_than) + | MMC_BR_BR_TRG_POS_CFG_EN_SET(trig->enable); +} + +void mmc_pred_config_speed_trig(MMC_Type *base, uint8_t index, mmc_speed_trig_t *trig) +{ + /* speed has 19bit decimal */ + int32_t speed = (int32_t)(trig->speed_thr * (1 << 19U)); + + base->BR[index].BR_TRG_SPEED_THR = speed; + base->BR[index].BR_TRG_SPEED_CFG = MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SET(trig->absolute_compare) + | MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SET(trig->less_than) + | MMC_BR_BR_TRG_SPEED_CFG_EN_SET(trig->enable); +} + +void mmc_track_config_position_trig(MMC_Type *base, mmc_pos_trig_t *trig) +{ + base->POS_TRG_POS_THR = trig->position_thr; + base->POS_TRG_REV_THR = trig->revolution_thr; + + base->POS_TRG_CFG = MMC_POS_TRG_CFG_EDGE_SET(trig->less_than) + | MMC_POS_TRG_CFG_EN_SET(trig->enable); +} + +void mmc_track_config_speed_trig(MMC_Type *base, mmc_speed_trig_t *trig) +{ + /* speed has 19bit decimal */ + int32_t speed = (int32_t)(trig->speed_thr * (1 << 19U)); + base->SPEED_TRG_THR = speed; + base->SPEED_TRG_CFG = MMC_SPEED_TRG_CFG_COMP_TYPE_SET(trig->absolute_compare) + | MMC_SPEED_TRG_CFG_EDGE_SET(trig->less_than) + | MMC_SPEED_TRG_CFG_EN_SET(trig->enable); +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c new file mode 100644 index 00000000..39b9fd70 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c @@ -0,0 +1,218 @@ +#include "hpm_opamp_drv.h" + +hpm_stat_t opamp_init(OPAMP_Type *opamp, opamp_cfg_t *cfg) +{ + opamp_disable(opamp); + opamp->CTRL0 = 0; + opamp_inn_pad_select(opamp, cfg->negative_input_pin); + opamp_inp_pad_select(opamp, cfg->positive_input_pin); + opamp_gain_select(opamp, cfg->gain); + opamp_miller_cap_select(opamp, cfg->miller_cap); + if (cfg->enable_phase_margin_cap) { + opamp_phase_margin_cap_enable(opamp); + } else { + opamp_phase_margin_cap_disable(opamp); + } + switch (cfg->mode) { + case mode_follow: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) == 0) { + return status_invalid_argument; + } + opamp_disconnect_vssa(opamp); + opamp_phase_margin_cap_enable(opamp); + opamp_mode_set(opamp, OPAMP_MODE_FOLLOW_KEY); + break; + case mode_invert_intern_vol: + if ((cfg->positive_input_pin & 0x04) == 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_disconnect_vssa(opamp); + opamp_phase_margin_cap_disable(opamp); + opamp_mode_set(opamp, OPAMP_MODE_INVERT_INDEX0_KEY); + break; + case mode_invert_extern_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if (cfg->enable_extern_filter_cap) { + opamp_mode_set(opamp, OPAMP_MODE_INVERT_INDEX1_KEY); + } else { + opamp_mode_set(opamp, OPAMP_MODE_INVERT_INDEX0_KEY); + } + break; + case mode_invert_dac_vol: + opamp_inp_pad_select(opamp, 0x02); + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_disconnect_vssa(opamp); + opamp_mode_set(opamp, OPAMP_MODE_INVERT_INDEX0_KEY); + break; + case mode_non_invert_gnd_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_disconnect_vssa(opamp); + if (!cfg->enable_extern_filter_cap) { + if ((cfg->negative_input_pin & 0x04) == 0) { + return status_invalid_argument; + } + opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX0_KEY); + } else { + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX2_KEY); + } + break; + case mode_non_invert_extern_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_disconnect_vssa(opamp); + if (!cfg->enable_extern_filter_cap) { + opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX1_KEY); + } else { + opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX3_KEY); + } + break; + case mode_non_invert_dac_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_inn_pad_select(opamp, 0x02); + opamp_disconnect_vssa(opamp); + opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX4_KEY); + break; + case mode_user: + return status_success; + break; + default: + return status_invalid_argument; + break; + } + return status_success; +} + + +hpm_stat_t opamp_set_preset_cfg(OPAMP_Type *opamp, uint8_t preset_chn, opamp_cfg_t *cfg) +{ + if (preset_chn > OPAMP_SOC_HAS_MAX_PRESET_CHN_NUM) { + return status_invalid_argument; + } + opamp->CFG[preset_chn].CFG0 = 0; + opamp->CFG[preset_chn].CFG1 = 0; + opamp_preset_inn_pad_select(opamp, preset_chn, cfg->negative_input_pin); + opamp_preset_inp_pad_select(opamp, preset_chn, cfg->positive_input_pin); + opamp_preset_gain_select(opamp, preset_chn, cfg->gain); + opamp_preset_miller_cap_select(opamp, preset_chn, cfg->miller_cap); + if (cfg->enable_phase_margin_cap) { + opamp_preset_phase_margin_cap_enable(opamp, preset_chn); + } else { + opamp_preset_phase_margin_cap_disable(opamp, preset_chn); + } + switch (cfg->mode) { + case mode_follow: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) == 0) { + return status_invalid_argument; + } + opamp_preset_disconnect_vssa(opamp, preset_chn); + opamp_preset_phase_margin_cap_enable(opamp, preset_chn); + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_FOLLOW_KEY); + break; + case mode_invert_intern_vol: + if ((cfg->positive_input_pin & 0x04) == 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_preset_disconnect_vssa(opamp, preset_chn); + opamp_preset_phase_margin_cap_disable(opamp, preset_chn); + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_INVERT_INDEX0_KEY); + break; + case mode_invert_extern_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if (cfg->enable_extern_filter_cap) { + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_INVERT_INDEX1_KEY); + } else { + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_INVERT_INDEX0_KEY); + } + break; + case mode_invert_dac_vol: + opamp_preset_inp_pad_select(opamp, preset_chn, 0x02); + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_preset_disconnect_vssa(opamp, preset_chn); + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_INVERT_INDEX0_KEY); + break; + case mode_non_invert_gnd_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_preset_disconnect_vssa(opamp, preset_chn); + if (!cfg->enable_extern_filter_cap) { + if ((cfg->negative_input_pin & 0x04) == 0) { + return status_invalid_argument; + } + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX0_KEY); + } else { + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX2_KEY); + } + break; + case mode_non_invert_extern_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + if ((cfg->negative_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_preset_disconnect_vssa(opamp, preset_chn); + if (!cfg->enable_extern_filter_cap) { + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX1_KEY); + } else { + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX3_KEY); + } + break; + case mode_non_invert_dac_vol: + if ((cfg->positive_input_pin & 0x04) != 0) { + return status_invalid_argument; + } + opamp_preset_inn_pad_select(opamp, preset_chn, 0x02); + opamp_preset_disconnect_vssa(opamp, preset_chn); + opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX4_KEY); + break; + case mode_user: + return status_success; + break; + default: + return status_invalid_argument; + break; + } + return status_success; +} + diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c new file mode 100644 index 00000000..6a26cb22 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_soc_feature.h" +#include "hpm_plb_drv.h" + +void plb_type_b_set_lut(PLB_Type *plb, plb_chn_t chn, plb_type_b_lut_slice_t slice, plb_type_b_slice_opt_t opt) +{ + if (opt >= plb_slice_opt_shift_left) { + opt = opt >> 8; + plb->TYPE_B[chn].MODE |= PLB_TYPE_B_MODE_OPT_SEL_SET(1); + } else { + plb->TYPE_B[chn].MODE &= ~PLB_TYPE_B_MODE_OPT_SEL_MASK; + } + if (slice >= plb_type_b_slice_8) { + plb->TYPE_B[chn].LUT[1] = (plb->TYPE_B[chn].LUT[1] & (~((uint32_t)0xf))) | PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(opt << ((slice - plb_type_b_slice_8) << 2)); + } else { + plb->TYPE_B[chn].LUT[0] = (plb->TYPE_B[chn].LUT[0] & (~((uint32_t)0xf))) | PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(opt << (slice << 2)); + } +} diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c index 7dd7cc7b..778d4bd1 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c @@ -22,6 +22,28 @@ #define PLLCTL_FRAC_PLL_MIN_REF (10000000U) #define PLLCTL_INT_PLL_MIN_REF (1000000U) + +hpm_stat_t pllctl_set_pll_work_mode(PLLCTL_Type *ptr, uint8_t pll, bool int_mode) +{ + if (int_mode) { + if (!(ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK)) { + /* it was at frac mode, then it needs to be power down */ + pllctl_pll_powerdown(ptr, pll); + ptr->PLL[pll].CFG0 |= PLLCTL_PLL_CFG0_DSMPD_MASK; + pllctl_pll_poweron(ptr, pll); + } + } else { + if (ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK) { + /* pll has to be powered down to configure frac mode */ + pllctl_pll_powerdown(ptr, pll); + ptr->PLL[pll].CFG0 &= ~PLLCTL_PLL_CFG0_DSMPD_MASK; + pllctl_pll_poweron(ptr, pll); + } + } + + return status_success; +} + hpm_stat_t pllctl_set_refdiv(PLLCTL_Type *ptr, uint8_t pll, uint8_t div) { uint32_t min_ref; @@ -47,6 +69,7 @@ hpm_stat_t pllctl_set_refdiv(PLLCTL_Type *ptr, uint8_t pll, uint8_t div) pllctl_pll_powerdown(ptr, pll); ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 & ~PLLCTL_PLL_CFG0_REFDIV_MASK) | PLLCTL_PLL_CFG0_REFDIV_SET(div); + pllctl_pll_poweron(ptr, pll); } return status_success; } @@ -204,7 +227,7 @@ uint32_t pllctl_get_pll_freq_in_hz(PLLCTL_Type *ptr, uint8_t pll) /* pll frac mode */ fbdiv = PLLCTL_PLL_FREQ_FBDIV_FRAC_GET(ptr->PLL[pll].FREQ); frac = PLLCTL_PLL_FREQ_FRAC_GET(ptr->PLL[pll].FREQ); - freq = refclk * (fbdiv + ((double) frac / (1 << 24))); + freq = (refclk * (fbdiv + ((double) frac / (1 << 24)))) + 0.5; } return freq; } diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c index 124e2df9..641f6ec1 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c @@ -4,9 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause * */ -#include "riscv/riscv_core.h" #include "hpm_pmp_drv.h" -#include "hpm_csr_regs.h" +#include "hpm_csr_drv.h" uint32_t read_pmp_cfg(uint32_t idx) { @@ -31,29 +30,6 @@ uint32_t read_pmp_cfg(uint32_t idx) return pmp_cfg; } -uint32_t read_pma_cfg(uint32_t idx) -{ - uint32_t pma_cfg = 0; - switch (idx) { - case 0: - pma_cfg = read_csr(CSR_PMACFG0); - break; - case 1: - pma_cfg = read_csr(CSR_PMACFG1); - break; - case 2: - pma_cfg = read_csr(CSR_PMACFG2); - break; - case 3: - pma_cfg = read_csr(CSR_PMACFG3); - break; - default: - /* Do nothing */ - break; - } - return pma_cfg; -} - void write_pmp_cfg(uint32_t value, uint32_t idx) { switch (idx) { @@ -75,27 +51,6 @@ void write_pmp_cfg(uint32_t value, uint32_t idx) } } -void write_pma_cfg(uint32_t value, uint32_t idx) -{ - switch (idx) { - case 0: - write_csr(CSR_PMACFG0, value); - break; - case 1: - write_csr(CSR_PMACFG1, value); - break; - case 2: - write_csr(CSR_PMACFG2, value); - break; - case 3: - write_csr(CSR_PMACFG3, value); - break; - default: - /* Do nothing */ - break; - } -} - void write_pmp_addr(uint32_t value, uint32_t idx) { switch (idx) { @@ -153,120 +108,164 @@ void write_pmp_addr(uint32_t value, uint32_t idx) } } -void write_pma_addr(uint32_t value, uint32_t idx) +uint32_t read_pmp_addr(uint32_t idx) { + uint32_t ret_val = 0; switch (idx) { case 0: - write_csr(CSR_PMAADDR0, value); + ret_val = read_csr(CSR_PMPADDR0); break; case 1: - write_csr(CSR_PMAADDR1, value); + ret_val = read_csr(CSR_PMPADDR1); break; case 2: - write_csr(CSR_PMAADDR2, value); + ret_val = read_csr(CSR_PMPADDR2); break; case 3: - write_csr(CSR_PMAADDR3, value); + ret_val = read_csr(CSR_PMPADDR3); break; case 4: - write_csr(CSR_PMAADDR4, value); + ret_val = read_csr(CSR_PMPADDR4); break; case 5: - write_csr(CSR_PMAADDR5, value); + ret_val = read_csr(CSR_PMPADDR5); break; case 6: - write_csr(CSR_PMAADDR6, value); + ret_val = read_csr(CSR_PMPADDR6); break; case 7: - write_csr(CSR_PMAADDR7, value); + ret_val = read_csr(CSR_PMPADDR7); break; case 8: - write_csr(CSR_PMAADDR8, value); + ret_val = read_csr(CSR_PMPADDR8); break; case 9: - write_csr(CSR_PMAADDR9, value); + ret_val = read_csr(CSR_PMPADDR9); break; case 10: - write_csr(CSR_PMAADDR10, value); + ret_val = read_csr(CSR_PMPADDR10); break; case 11: - write_csr(CSR_PMAADDR11, value); + ret_val = read_csr(CSR_PMPADDR11); break; case 12: - write_csr(CSR_PMAADDR12, value); + ret_val = read_csr(CSR_PMPADDR12); break; case 13: - write_csr(CSR_PMAADDR13, value); + ret_val = read_csr(CSR_PMPADDR13); break; case 14: - write_csr(CSR_PMAADDR14, value); + ret_val = read_csr(CSR_PMPADDR14); break; case 15: - write_csr(CSR_PMAADDR15, value); + ret_val = read_csr(CSR_PMPADDR15); break; default: /* Do nothing */ break; } + return ret_val; } -uint32_t read_pmp_addr(uint32_t idx) +#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) +uint32_t read_pma_cfg(uint32_t idx) { - uint32_t ret_val = 0; + uint32_t pma_cfg = 0; switch (idx) { case 0: - ret_val = read_csr(CSR_PMPADDR0); + pma_cfg = read_csr(CSR_PMACFG0); break; case 1: - ret_val = read_csr(CSR_PMPADDR1); + pma_cfg = read_csr(CSR_PMACFG1); break; case 2: - ret_val = read_csr(CSR_PMPADDR2); + pma_cfg = read_csr(CSR_PMACFG2); break; case 3: - ret_val = read_csr(CSR_PMPADDR3); + pma_cfg = read_csr(CSR_PMACFG3); + break; + default: + /* Do nothing */ + break; + } + return pma_cfg; +} + +void write_pma_cfg(uint32_t value, uint32_t idx) +{ + switch (idx) { + case 0: + write_csr(CSR_PMACFG0, value); + break; + case 1: + write_csr(CSR_PMACFG1, value); + break; + case 2: + write_csr(CSR_PMACFG2, value); + break; + case 3: + write_csr(CSR_PMACFG3, value); + break; + default: + /* Do nothing */ + break; + } +} +void write_pma_addr(uint32_t value, uint32_t idx) +{ + switch (idx) { + case 0: + write_csr(CSR_PMAADDR0, value); + break; + case 1: + write_csr(CSR_PMAADDR1, value); + break; + case 2: + write_csr(CSR_PMAADDR2, value); + break; + case 3: + write_csr(CSR_PMAADDR3, value); break; case 4: - ret_val = read_csr(CSR_PMPADDR4); + write_csr(CSR_PMAADDR4, value); break; case 5: - ret_val = read_csr(CSR_PMPADDR5); + write_csr(CSR_PMAADDR5, value); break; case 6: - ret_val = read_csr(CSR_PMPADDR6); + write_csr(CSR_PMAADDR6, value); break; case 7: - ret_val = read_csr(CSR_PMPADDR7); + write_csr(CSR_PMAADDR7, value); break; case 8: - ret_val = read_csr(CSR_PMPADDR8); + write_csr(CSR_PMAADDR8, value); break; case 9: - ret_val = read_csr(CSR_PMPADDR9); + write_csr(CSR_PMAADDR9, value); break; case 10: - ret_val = read_csr(CSR_PMPADDR10); + write_csr(CSR_PMAADDR10, value); break; case 11: - ret_val = read_csr(CSR_PMPADDR11); + write_csr(CSR_PMAADDR11, value); break; case 12: - ret_val = read_csr(CSR_PMPADDR12); + write_csr(CSR_PMAADDR12, value); break; case 13: - ret_val = read_csr(CSR_PMPADDR13); + write_csr(CSR_PMAADDR13, value); break; case 14: - ret_val = read_csr(CSR_PMPADDR14); + write_csr(CSR_PMAADDR14, value); break; case 15: - ret_val = read_csr(CSR_PMPADDR15); + write_csr(CSR_PMAADDR15, value); break; default: /* Do nothing */ break; } - return ret_val; } uint32_t read_pma_addr(uint32_t idx) @@ -327,6 +326,7 @@ uint32_t read_pma_addr(uint32_t idx) } return ret_val; } +#endif /* #if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) */ hpm_stat_t pmp_config_entry(const pmp_entry_t *entry, uint32_t entry_index) { @@ -340,15 +340,15 @@ hpm_stat_t pmp_config_entry(const pmp_entry_t *entry, uint32_t entry_index) uint32_t pmp_cfg = read_pmp_cfg(idx); pmp_cfg &= ~(0xFFUL << offset); pmp_cfg |= ((uint32_t) entry->pmp_cfg.val) << offset; + write_pmp_addr(entry->pmp_addr, entry_index); + write_pmp_cfg(pmp_cfg, idx); +#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) uint32_t pma_cfg = read_pma_cfg(idx); pma_cfg &= ~(0xFFUL << offset); pma_cfg |= ((uint32_t) entry->pma_cfg.val) << offset; - - write_pmp_addr(entry->pmp_addr, entry_index); - write_pma_addr(entry->pma_addr, entry_index); - write_pma_cfg(pma_cfg, idx); - write_pmp_cfg(pmp_cfg, idx); + write_pma_addr(entry->pma_addr, entry_index); +#endif fencei(); status = status_success; @@ -367,20 +367,18 @@ hpm_stat_t pmp_config(const pmp_entry_t *entry, uint32_t num_of_entries) for (uint32_t i = 0; i < num_of_entries; i++) { uint32_t idx = i / 4; uint32_t offset = (i * 8) & 0x1F; - uint32_t pmp_cfg = read_pmp_cfg(idx); pmp_cfg &= ~(0xFFUL << offset); pmp_cfg |= ((uint32_t) entry->pmp_cfg.val) << offset; + write_pmp_addr(entry->pmp_addr, i); + write_pmp_cfg(pmp_cfg, idx); +#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) uint32_t pma_cfg = read_pma_cfg(idx); pma_cfg &= ~(0xFFUL << offset); pma_cfg |= ((uint32_t) entry->pma_cfg.val) << offset; - - write_pmp_addr(entry->pmp_addr, i); - write_pma_addr(entry->pma_addr, i); - write_pma_cfg(pma_cfg, idx); - write_pmp_cfg(pmp_cfg, idx); - + write_pma_addr(entry->pma_addr, i); +#endif ++entry; } fencei(); @@ -399,15 +397,32 @@ void pmp_disable(void) uint32_t mcache_ctl = read_csr(CSR_MCACHE_CTL); write_csr(CSR_MCACHE_CTL, 0x0); fencei(); - write_csr(CSR_PMACFG0, 0); - write_csr(CSR_PMACFG1, 0); - write_csr(CSR_PMACFG2, 0); - write_csr(CSR_PMACFG3, 0); + write_csr(CSR_PMPCFG0, 0); write_csr(CSR_PMPCFG1, 0); write_csr(CSR_PMPCFG2, 0); write_csr(CSR_PMPCFG3, 0); - + write_csr(CSR_PMPADDR0, 0); + write_csr(CSR_PMPADDR1, 0); + write_csr(CSR_PMPADDR2, 0); + write_csr(CSR_PMPADDR3, 0); + write_csr(CSR_PMPADDR4, 0); + write_csr(CSR_PMPADDR5, 0); + write_csr(CSR_PMPADDR6, 0); + write_csr(CSR_PMPADDR7, 0); + write_csr(CSR_PMPADDR8, 0); + write_csr(CSR_PMPADDR9, 0); + write_csr(CSR_PMPADDR10, 0); + write_csr(CSR_PMPADDR11, 0); + write_csr(CSR_PMPADDR12, 0); + write_csr(CSR_PMPADDR13, 0); + write_csr(CSR_PMPADDR14, 0); + write_csr(CSR_PMPADDR15, 0); +#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) + write_csr(CSR_PMACFG0, 0); + write_csr(CSR_PMACFG1, 0); + write_csr(CSR_PMACFG2, 0); + write_csr(CSR_PMACFG3, 0); write_csr(CSR_PMAADDR0, 0); write_csr(CSR_PMAADDR1, 0); write_csr(CSR_PMAADDR2, 0); @@ -424,6 +439,7 @@ void pmp_disable(void) write_csr(CSR_PMAADDR13, 0); write_csr(CSR_PMAADDR14, 0); write_csr(CSR_PMAADDR15, 0); +#endif fencei(); write_csr(CSR_MCACHE_CTL, mcache_ctl); fencei(); diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c new file mode 100644 index 00000000..349355c2 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_qeiv2_drv.h" +#include "hpm_enc_pos_drv.h" + +hpm_stat_t qeiv2_config_phcnt_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config) +{ + if (qeiv2_check_spd_tmr_as_pos_angle(qeiv2_x)) { + return status_fail; + } + qeiv2_set_phcnt_cmp_value(qeiv2_x, config->phcnt_cmp_value); + qeiv2_set_spd_pos_cmp_value(qeiv2_x, 0); + qeiv2_set_z_cmp_value(qeiv2_x, config->zcmp_value); + qeiv2_set_cmp_match_option(qeiv2_x, config->ignore_zcmp, false, false, config->ignore_rotate_dir, config->rotate_dir, true, qeiv2_pos_dir_decrease); + return status_success; +} + +hpm_stat_t qeiv2_config_position_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config) +{ + if (!qeiv2_check_spd_tmr_as_pos_angle(qeiv2_x)) { + return status_fail; + } + qeiv2_set_spd_pos_cmp_value(qeiv2_x, config->pos_cmp_value); + qeiv2_set_cmp_match_option(qeiv2_x, true, true, false, true, qeiv2_rotate_dir_forward, config->ignore_pos_dir, config->pos_dir); + return status_success; +} + +hpm_stat_t qeiv2_config_phcnt_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config) +{ + if (qeiv2_check_spd_tmr_as_pos_angle(qeiv2_x)) { + return status_fail; + } + qeiv2_set_phcnt_cmp2_value(qeiv2_x, config->phcnt_cmp_value); + qeiv2_set_spd_pos_cmp2_value(qeiv2_x, 0); + qeiv2_set_z_cmp2_value(qeiv2_x, config->zcmp_value); + qeiv2_set_cmp2_match_option(qeiv2_x, config->ignore_zcmp, false, false, config->ignore_rotate_dir, config->rotate_dir, true, qeiv2_pos_dir_decrease); + return status_success; +} + +hpm_stat_t qeiv2_config_position_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config) +{ + if (!qeiv2_check_spd_tmr_as_pos_angle(qeiv2_x)) { + return status_fail; + } + qeiv2_set_spd_pos_cmp2_value(qeiv2_x, config->pos_cmp_value); + qeiv2_set_cmp2_match_option(qeiv2_x, true, true, false, true, qeiv2_rotate_dir_forward, config->ignore_pos_dir, config->pos_dir); + return status_success; +} + +void qeiv2_get_uvw_position_defconfig(qeiv2_uvw_config_t *config) +{ + config->pos_opt = qeiv2_uvw_pos_opt_current; + + config->u_pos_sel[0] = qeiv2_uvw_pos_sel_high; + config->v_pos_sel[0] = qeiv2_uvw_pos_sel_low; + config->w_pos_sel[0] = qeiv2_uvw_pos_sel_high; + + config->u_pos_sel[1] = qeiv2_uvw_pos_sel_high; + config->v_pos_sel[1] = qeiv2_uvw_pos_sel_low; + config->w_pos_sel[1] = qeiv2_uvw_pos_sel_low; + + config->u_pos_sel[2] = qeiv2_uvw_pos_sel_high; + config->v_pos_sel[2] = qeiv2_uvw_pos_sel_high; + config->w_pos_sel[2] = qeiv2_uvw_pos_sel_low; + + config->u_pos_sel[3] = qeiv2_uvw_pos_sel_low; + config->v_pos_sel[3] = qeiv2_uvw_pos_sel_high; + config->w_pos_sel[3] = qeiv2_uvw_pos_sel_low; + + config->u_pos_sel[4] = qeiv2_uvw_pos_sel_low; + config->v_pos_sel[4] = qeiv2_uvw_pos_sel_high; + config->w_pos_sel[4] = qeiv2_uvw_pos_sel_high; + + config->u_pos_sel[5] = qeiv2_uvw_pos_sel_low; + config->v_pos_sel[5] = qeiv2_uvw_pos_sel_low; + config->w_pos_sel[5] = qeiv2_uvw_pos_sel_high; + + config->pos_cfg[0] = encoder_deg_to_position(30); + config->pos_cfg[1] = encoder_deg_to_position(90); + config->pos_cfg[2] = encoder_deg_to_position(150); + config->pos_cfg[3] = encoder_deg_to_position(210); + config->pos_cfg[4] = encoder_deg_to_position(270); + config->pos_cfg[5] = encoder_deg_to_position(330); +} + +hpm_stat_t qeiv2_config_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_config_t *config) +{ + qeiv2_set_uvw_position_opt(qeiv2_x, config->pos_opt); + for (uint8_t i = 0; i < 6; i++) { + if (config->pos_opt == qeiv2_uvw_pos_opt_next) { + if (config->u_pos_sel[i] == qeiv2_uvw_pos_sel_edge) { + return status_invalid_argument; + } + } + } + + for (uint8_t i = 0; i < 6; i++) { + if (config->pos_opt == qeiv2_uvw_pos_opt_next) { + qeiv2_set_uvw_position_sel(qeiv2_x, i, + (config->u_pos_sel[i] == qeiv2_uvw_pos_sel_high) ? QEIV2_UVW_POS_OPT_NEX_SEL_HIGH : QEIV2_UVW_POS_OPT_NEX_SEL_LOW, + (config->v_pos_sel[i] == qeiv2_uvw_pos_sel_high) ? QEIV2_UVW_POS_OPT_NEX_SEL_HIGH : QEIV2_UVW_POS_OPT_NEX_SEL_LOW, + (config->w_pos_sel[i] == qeiv2_uvw_pos_sel_high) ? QEIV2_UVW_POS_OPT_NEX_SEL_HIGH : QEIV2_UVW_POS_OPT_NEX_SEL_LOW, + true); + } else { + qeiv2_set_uvw_position_sel(qeiv2_x, i, config->u_pos_sel[i], config->v_pos_sel[i], config->w_pos_sel[i], true); + } + qeiv2_set_uvw_position(qeiv2_x, i, config->pos_cfg[i]); + } + + return status_success; +} diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c new file mode 100644 index 00000000..766f0e84 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_qeo_drv.h" + +void qeo_wave_get_default_mode_config(QEO_Type *base, qeo_wave_mode_t *config) +{ + config->wave0.above_max_limit = qeo_wave_above_max_limit_max_val; + config->wave0.high_area0_limit = qeo_wave_high_area_limit_max_val; + config->wave0.high_area1_limit = qeo_wave_high_area_limit_max_val; + config->wave0.low_area0_limit = qeo_wave_low_area_limit_zero; + config->wave0.low_area1_limit = qeo_wave_low_area_limit_zero; + config->wave0.below_min_limit = qeo_wave_below_min_limit_zero; + + config->wave1.above_max_limit = qeo_wave_above_max_limit_max_val; + config->wave1.high_area0_limit = qeo_wave_high_area_limit_max_val; + config->wave1.high_area1_limit = qeo_wave_high_area_limit_max_val; + config->wave1.low_area0_limit = qeo_wave_low_area_limit_zero; + config->wave1.low_area1_limit = qeo_wave_low_area_limit_zero; + config->wave1.below_min_limit = qeo_wave_below_min_limit_zero; + + config->wave2.above_max_limit = qeo_wave_above_max_limit_max_val; + config->wave2.high_area0_limit = qeo_wave_high_area_limit_max_val; + config->wave2.high_area1_limit = qeo_wave_high_area_limit_max_val; + config->wave2.low_area0_limit = qeo_wave_low_area_limit_zero; + config->wave2.low_area1_limit = qeo_wave_low_area_limit_zero; + config->wave2.below_min_limit = qeo_wave_below_min_limit_zero; + + config->saddle_type = 0; + config->wave_type = qeo_wave_cosine; +} + +void qeo_wave_config_mode(QEO_Type *base, qeo_wave_mode_t *config) +{ + /* clear other bit except EN_WAVEx_VD_VQ_INJECT in MODE register */ + base->WAVE.MODE &= QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK + | QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK + | QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK; + + base->WAVE.MODE |= QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET(config->wave2.above_max_limit) + | QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET(config->wave2.high_area1_limit) + | QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET(config->wave2.high_area0_limit) + | QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET(config->wave2.low_area1_limit) + | QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET(config->wave2.low_area0_limit) + | QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET(config->wave2.below_min_limit) + + | QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET(config->wave1.above_max_limit) + | QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET(config->wave1.high_area1_limit) + | QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET(config->wave1.high_area0_limit) + | QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET(config->wave1.low_area1_limit) + | QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET(config->wave1.low_area0_limit) + | QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET(config->wave1.below_min_limit) + + | QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET(config->wave0.above_max_limit) + | QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET(config->wave0.high_area1_limit) + | QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET(config->wave0.high_area0_limit) + | QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET(config->wave0.low_area1_limit) + | QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET(config->wave0.low_area0_limit) + | QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET(config->wave0.below_min_limit) + | QEO_WAVE_MODE_SADDLE_TYPE_SET(config->saddle_type) + | QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(config->wave_type); +} + +void qeo_abz_get_default_mode_config(QEO_Type *base, qeo_abz_mode_t *config) +{ + config->a_inv_pol = false; + config->b_inv_pol = false; + config->z_inv_pol = false; + config->output_type = qeo_abz_output_abz; + config->z_pulse_period = qeo_z_pulse_100_percent; +} + +void qeo_abz_config_mode(QEO_Type *base, qeo_abz_mode_t *config) +{ + base->ABZ.MODE &= ~(QEO_ABZ_MODE_Z_POLARITY_MASK + | QEO_ABZ_MODE_B_POLARITY_MASK + | QEO_ABZ_MODE_A_POLARITY_MASK + | QEO_ABZ_MODE_Z_TYPE_MASK + | QEO_ABZ_MODE_B_TYPE_MASK + | QEO_ABZ_MODE_A_TYPE_MASK); + + base->ABZ.MODE = QEO_ABZ_MODE_Z_POLARITY_SET(config->z_inv_pol) + | QEO_ABZ_MODE_B_POLARITY_SET(config->b_inv_pol) + | QEO_ABZ_MODE_A_POLARITY_SET(config->a_inv_pol); + + if ((config->output_type == qeo_abz_output_pulse_revise) || (config->output_type == qeo_abz_output_up_down)) { + base->ABZ.MODE |= QEO_ABZ_MODE_B_TYPE_SET(config->output_type) + | QEO_ABZ_MODE_A_TYPE_SET(config->output_type); + } else if (config->output_type == qeo_abz_output_three_phase) { + base->ABZ.MODE |= QEO_ABZ_MODE_Z_TYPE_SET(config->output_type) + | QEO_ABZ_MODE_B_TYPE_SET(config->output_type) + | QEO_ABZ_MODE_A_TYPE_SET(config->output_type); + } else { + base->ABZ.MODE |= QEO_ABZ_MODE_Z_TYPE_SET(config->z_pulse_period) + | QEO_ABZ_MODE_B_TYPE_SET(config->output_type) + | QEO_ABZ_MODE_A_TYPE_SET(config->output_type); + } +} + +hpm_stat_t qeo_abz_set_max_frequency(QEO_Type *base, uint32_t src_freq, uint32_t freq) +{ + uint32_t count; + + if ((freq > 0xffffffffU / 4U) || ((src_freq % (freq * 4U)) != 0)) { + return status_invalid_argument; + } + count = src_freq / (freq * 4U); + base->ABZ.LINE_WIDTH = QEO_ABZ_LINE_WIDTH_LINE_SET(count); + + return status_success; +} + +hpm_stat_t qeo_abz_set_wdog_frequency(QEO_Type *base, uint32_t src_freq, uint32_t freq) +{ + uint32_t count; + + if ((src_freq % freq) != 0) { + return status_invalid_argument; + } + count = src_freq / freq; + base->ABZ.WDOG_WIDTH = QEO_ABZ_WDOG_WIDTH_WIDTH_SET(count); + base->ABZ.MODE |= QEO_ABZ_MODE_EN_WDOG_MASK; + + return status_success; +} + +void qeo_pwm_get_default_safety_table_config(QEO_Type *base, qeo_pwm_safety_output_table_t *table) +{ + table->pwm7_output = qeo_pwm_safety_output_highz; + table->pwm6_output = qeo_pwm_safety_output_highz; + table->pwm5_output = qeo_pwm_safety_output_highz; + table->pwm4_output = qeo_pwm_safety_output_highz; + table->pwm3_output = qeo_pwm_safety_output_highz; + table->pwm2_output = qeo_pwm_safety_output_highz; + table->pwm1_output = qeo_pwm_safety_output_highz; + table->pwm0_output = qeo_pwm_safety_output_highz; +} + +void qeo_pwm_get_default_phase_table_config(QEO_Type *base, qeo_pwm_phase_output_table_t *table) +{ + table->pwm7_output = qeo_pwm_output_force_0; + table->pwm6_output = qeo_pwm_output_force_0; + table->pwm5_output = qeo_pwm_output_force_0; + table->pwm4_output = qeo_pwm_output_force_0; + table->pwm3_output = qeo_pwm_output_force_0; + table->pwm2_output = qeo_pwm_output_force_0; + table->pwm1_output = qeo_pwm_output_force_0; + table->pwm0_output = qeo_pwm_output_force_0; +} + +void qeo_pwm_get_default_mode_config(QEO_Type *base, qeo_pwm_mode_t *config) +{ + config->phase_num = 4; + config->shield_hardware_trig_safety = false; + config->revise_pairs_output = false; +} + +void qeo_pwm_config_mode(QEO_Type *base, qeo_pwm_mode_t *config) +{ + base->PWM.MODE &= ~(QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK + | QEO_PWM_MODE_REVISE_UP_DN_MASK + | QEO_PWM_MODE_PHASE_NUM_MASK); + base->PWM.MODE |= QEO_PWM_MODE_PWM_SAFETY_BYPASS_SET(config->shield_hardware_trig_safety) + | QEO_PWM_MODE_REVISE_UP_DN_SET(config->revise_pairs_output) + | QEO_PWM_MODE_PHASE_NUM_SET(config->phase_num); +} + +void qeo_pwm_config_phase_table(QEO_Type *base, uint8_t index, qeo_pwm_phase_output_table_t *table) +{ + base->PWM.PHASE_TABLE[index] = QEO_PWM_PHASE_TABLE_PWM7_SET(table->pwm7_output) + | QEO_PWM_PHASE_TABLE_PWM6_SET(table->pwm6_output) + | QEO_PWM_PHASE_TABLE_PWM5_SET(table->pwm5_output) + | QEO_PWM_PHASE_TABLE_PWM4_SET(table->pwm4_output) + | QEO_PWM_PHASE_TABLE_PWM3_SET(table->pwm3_output) + | QEO_PWM_PHASE_TABLE_PWM2_SET(table->pwm2_output) + | QEO_PWM_PHASE_TABLE_PWM1_SET(table->pwm1_output) + | QEO_PWM_PHASE_TABLE_PWM0_SET(table->pwm0_output); +} + +void qeo_pwm_config_safety_table(QEO_Type *base, qeo_pwm_safety_output_table_t *table) +{ + /*< clear safety table */ + base->PWM.MODE &= ~(QEO_PWM_MODE_PWM7_SAFETY_MASK + | QEO_PWM_MODE_PWM6_SAFETY_MASK + | QEO_PWM_MODE_PWM5_SAFETY_MASK + | QEO_PWM_MODE_PWM4_SAFETY_MASK + | QEO_PWM_MODE_PWM3_SAFETY_MASK + | QEO_PWM_MODE_PWM2_SAFETY_MASK + | QEO_PWM_MODE_PWM1_SAFETY_MASK + | QEO_PWM_MODE_PWM0_SAFETY_MASK); + /*< set safety table */ + base->PWM.MODE |= QEO_PWM_MODE_PWM7_SAFETY_SET(table->pwm7_output) + | QEO_PWM_MODE_PWM6_SAFETY_SET(table->pwm6_output) + | QEO_PWM_MODE_PWM5_SAFETY_SET(table->pwm5_output) + | QEO_PWM_MODE_PWM4_SAFETY_SET(table->pwm4_output) + | QEO_PWM_MODE_PWM3_SAFETY_SET(table->pwm3_output) + | QEO_PWM_MODE_PWM2_SAFETY_SET(table->pwm2_output) + | QEO_PWM_MODE_PWM1_SAFETY_SET(table->pwm1_output) + | QEO_PWM_MODE_PWM0_SAFETY_SET(table->pwm0_output); +} + +/** + * If the line step of the position to be synchronized after position value + * to ABZ value conversion is the same as the current position, will hang the ABZ. + * ABZ value = m lines + n line_steps(0 <= m <= 3) + * This API will check the sync_pos and shift it if needed + */ +void qeo_abz_position_sync(QEO_Type *base, uint32_t lines, uint32_t sync_pos) +{ + uint32_t line_width; + uint32_t line_step_width; + uint32_t shift_pos; + uint32_t current_line_step; + uint32_t temp; + + line_width = (uint32_t)(0x100000000UL / lines); + line_step_width = line_width / 4U; + current_line_step = base->DEBUG2 & 0x3; /* get the lowest two bits */ + temp = (sync_pos % line_width) / line_step_width; + if (temp == current_line_step) { + shift_pos = sync_pos - line_step_width; + } else { + shift_pos = sync_pos; + } + + base->ABZ.POSTION_SYNC = QEO_ABZ_POSTION_SYNC_POSTION_MASK; + qeo_enable_software_position_inject(base); + qeo_software_position_inject(base, shift_pos); + qeo_disable_software_position_inject(base); +} \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c new file mode 100644 index 00000000..065ee894 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_rdc_drv.h" + +void rdc_output_config(RDC_Type *ptr, rdc_output_cfg_t *cfg) +{ + uint32_t rate; + + rate = cfg->excitation_period_cycle >> (cfg->excitation_precision + 2); + ptr->EXC_TIMMING = RDC_EXC_TIMMING_SMP_RATE_SET(rate) | + RDC_EXC_TIMMING_SMP_NUM_SET(cfg->excitation_precision) | + RDC_EXC_TIMMING_PWM_PRD_SET(cfg->pwm_period)| + RDC_EXC_TIMMING_SWAP_SET(cfg->output_swap); + if (cfg->mode == rdc_output_dac) { + ptr->EXC_SCALING = RDC_EXC_SCALING_AMP_MAN_SET(cfg->amp_man) | + RDC_EXC_SCALING_AMP_EXP_SET(cfg->amp_exp); + ptr->EXC_OFFSET = RDC_EXC_OFFSET_AMP_OFFSET_SET(cfg->amp_offset + 0x800000); + ptr->OUT_CTL = RDC_OUT_CTL_CH_I_SEL_SET(cfg->dac_chn_i_sel) | + RDC_OUT_CTL_CH_Q_SEL_SET(cfg->dac_chn_q_sel); + } else if (cfg->mode == rdc_output_pwm) { + ptr->PWM_SCALING = RDC_EXC_SCALING_AMP_MAN_SET(cfg->amp_man) | + RDC_EXC_SCALING_AMP_EXP_SET(cfg->amp_exp) | + RDC_PWM_SCALING_DITHER_SET(cfg->pwm_dither_enable) | + RDC_PWM_SCALING_P_POL_SET(cfg->pwm_exc_p_low_active) | + RDC_PWM_SCALING_N_POL_SET(cfg->pwm_exc_n_low_active); + ptr->PWM_OFFSET = RDC_PWM_OFFSET_AMP_OFFSET_SET(cfg->amp_offset + (rate >> 1)); + ptr->PWM_DZ = RDC_PWM_DZ_DZ_N_SET(cfg->pwm_deadzone_n) | + RDC_PWM_DZ_DZ_P_SET(cfg->pwm_deadzone_p); + } + if (cfg->trig_by_hw) { + ptr->EXC_SYNC_DLY = RDC_EXC_SYNC_DLY_DELAY_SET(cfg->hw_trig_delay); + } else { + ptr->EXC_SYNC_DLY = RDC_EXC_SYNC_DLY_DISABLE_MASK; + } +} + + +void rdc_input_config(RDC_Type *ptr, rdc_input_cfg_t *cfg) +{ + ptr->RDC_CTL = (ptr->RDC_CTL & (~(RDC_RDC_CTL_RECTIFY_SEL_MASK | RDC_RDC_CTL_ACC_LEN_MASK | RDC_RDC_CTL_TS_SEL_MASK))) + | RDC_RDC_CTL_RECTIFY_SEL_SET(cfg->rectify_signal_sel) + | RDC_RDC_CTL_ACC_LEN_SET(cfg->acc_cycle_len) + | RDC_RDC_CTL_TS_SEL_SET(cfg->acc_stamp); + ptr->IN_CTL = RDC_IN_CTL_PORT_I_SEL_SET(cfg->acc_input_port_i) | + RDC_IN_CTL_CH_I_SEL_SET(cfg->acc_input_chn_i) | + RDC_IN_CTL_PORT_Q_SEL_SET(cfg->acc_input_port_q) | + RDC_IN_CTL_CH_Q_SEL_SET(cfg->acc_input_chn_q); +} + +uint32_t rdc_get_acc_avl(RDC_Type *ptr, rdc_input_acc_chn_t chn) +{ + if (chn == rdc_acc_chn_i) { + return RDC_ACC_I_ACC_GET(ptr->ACC_I); + } else { + return RDC_ACC_Q_ACC_GET(ptr->ACC_Q); + } +} + +void rdc_output_trig_offset_config(RDC_Type *ptr, rdc_output_trig_chn_t chn, int32_t offset) +{ + if (chn == trigger_out_0) { + ptr->TRIG_OUT0_CFG = (ptr->TRIG_OUT0_CFG & (~RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK)) | + RDC_TRIG_OUT0_CFG_LEAD_TIM_SET(offset + RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK + 1); + } else if (chn == trigger_out_1) { + ptr->TRIG_OUT1_CFG = (ptr->TRIG_OUT1_CFG & (~RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK)) | + RDC_TRIG_OUT1_CFG_LEAD_TIM_SET(offset + RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK + 1); + } +} + +void rdc_output_trig_enable(RDC_Type *ptr, rdc_output_trig_chn_t chn) +{ + if (chn == trigger_out_0) { + ptr->TRIG_OUT0_CFG |= RDC_TRIG_OUT0_CFG_ENABLE_MASK; + } else if (chn == trigger_out_1) { + ptr->TRIG_OUT1_CFG |= RDC_TRIG_OUT1_CFG_ENABLE_MASK; + } +} + +void rdc_output_trig_disable(RDC_Type *ptr, rdc_output_trig_chn_t chn) +{ + if (chn == trigger_out_0) { + ptr->TRIG_OUT0_CFG &= ~RDC_TRIG_OUT0_CFG_ENABLE_MASK; + } else if (chn == trigger_out_1) { + ptr->TRIG_OUT1_CFG &= ~RDC_TRIG_OUT1_CFG_ENABLE_MASK; + } +} + +int32_t rdc_get_i_maxval(RDC_Type *ptr) +{ + uint32_t val; + + val = ptr->MAX_I; + if (RDC_MAX_I_VALID_GET(val)) { + return RDC_MAX_I_MAX_GET(val); + } else { + return -1; + } + +} + +int32_t rdc_get_i_minval(RDC_Type *ptr) +{ + uint32_t val; + + val = ptr->MIN_I; + if (RDC_MIN_I_VALID_GET(val)) { + return RDC_MIN_I_MIN_GET(val); + } else { + return -1; + } +} + +int32_t rdc_get_q_maxval(RDC_Type *ptr) +{ + uint32_t val; + + val = ptr->MAX_Q; + if (RDC_MAX_Q_VALID_GET(val)) { + return RDC_MAX_Q_MAX_GET(val); + } else { + return -1; + } +} + +int32_t rdc_get_q_minval(RDC_Type *ptr) +{ + uint32_t val; + + val = ptr->MIN_Q; + if (RDC_MIN_Q_VALID_GET(val)) { + return RDC_MIN_Q_MIN_GET(val); + } else { + return -1; + } +} + +void rdc_set_edge_detection_offset(RDC_Type *ptr, rdc_input_acc_chn_t chn, int32_t offset) +{ + if (chn == rdc_acc_chn_i) { + ptr->THRS_I = RDC_THRS_I_THRS_SET(offset); + } else { + ptr->THRS_Q = RDC_THRS_Q_THRS_SET(offset); + } +} + +void rdc_set_acc_config(RDC_Type *ptr, rdc_acc_cfg_t *cfg) +{ + ptr->EDG_DET_CTL = RDC_EDG_DET_CTL_FILTER_SET(cfg->continue_edge_num) | + RDC_EDG_DET_CTL_HOLD_SET(cfg->edge_distance); + if (cfg->right_shift_without_sign < 9) { + ptr->ACC_SCALING = RDC_ACC_SCALING_ACC_SHIFT_SET(8 - cfg->right_shift_without_sign); + } else { + ptr->ACC_SCALING = RDC_ACC_SCALING_ACC_SHIFT_SET(cfg->right_shift_without_sign); + } + if (cfg->error_data_remove) { + ptr->ACC_SCALING |= RDC_ACC_SCALING_TOXIC_LK_MASK; + } else { + ptr->ACC_SCALING &= ~RDC_ACC_SCALING_TOXIC_LK_MASK; + } + ptr->EXC_PERIOD = RDC_EXC_PERIOD_EXC_PERIOD_SET(cfg->exc_carrier_period); + ptr->SYNC_DELAY_I = RDC_SYNC_DELAY_I_DELAY_SET(cfg->sync_delay_i); + ptr->SYNC_DELAY_Q = RDC_SYNC_DELAY_Q_DELAY_SET(cfg->sync_delay_q); + ptr->AMP_MAX = RDC_AMP_MAX_MAX_SET(cfg->amp_max); + ptr->AMP_MIN = RDC_AMP_MIN_MIN_SET(cfg->amp_min); +} + +void rdc_set_acc_sync_delay(RDC_Type *ptr, rdc_input_acc_chn_t chn, uint32_t delay) +{ + if (chn == rdc_acc_chn_i) { + ptr->SYNC_DELAY_I = RDC_SYNC_DELAY_I_DELAY_SET(delay); + } else { + ptr->SYNC_DELAY_Q = RDC_SYNC_DELAY_Q_DELAY_SET(delay); + } +} diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c index 0562e3b4..79ece0fd 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c @@ -21,6 +21,21 @@ time_t rtc_get_time(RTC_Type *base) return time; } +struct timeval rtc_get_timeval(RTC_Type *base) +{ + struct timeval tm; + + base->SUB_SNAP = 0; /* Lock shadow registers first */ + + /* Convert sub-second ticks into micro-second */ + uint32_t sub_sec = (uint32_t)((base->SUB_SNAP >> 17) * 1.0 * 1000000 / 32768); + + tm.tv_sec = base->SEC_SNAP; + tm.tv_usec = sub_sec; + + return tm; +} + hpm_stat_t rtc_config_alarm(RTC_Type *base, rtc_alarm_config_t *config) { hpm_stat_t status = status_invalid_argument; diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c index 1eb52ade..3be5af7f 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c @@ -14,8 +14,8 @@ void sdm_get_default_module_control(SDM_Type *ptr, sdm_control_t *control) { - control->clk_signal_sync = true; - control->data_signal_sync = true; + control->clk_signal_sync = 0xf; /*!< configure clk sync for all channels */ + control->data_signal_sync = 0xf; /*!< configure data sync for all channels */ control->interrupt_en = false; } @@ -102,7 +102,7 @@ void sdm_config_channel_filter(SDM_Type *ptr, uint8_t ch_index, sdm_filter_confi ptr->CH[ch_index].SDCTRLE = SDM_CH_SDCTRLE_SGD_ORDR_SET(filter_config->filter_type) | SDM_CH_SDCTRLE_PWMSYNC_SET(filter_config->pwm_signal_sync) | SDM_CH_SDCTRLE_CIC_SCL_SET(filter_config->output_offset) - | SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(filter_config->oversampling_rate - 1) + | SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(filter_config->oversampling_rate) | SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET(filter_config->ignore_invalid_samples); ptr->CH[ch_index].SDCTRLP = SDM_CH_SDCTRLP_MANCH_THR_SET(filter_config->manchester_threshold) diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c new file mode 100644 index 00000000..5caf2d78 --- /dev/null +++ b/common/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c @@ -0,0 +1,380 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sei_drv.h" + +hpm_stat_t sei_tranceiver_config_init(SEI_Type *ptr, uint8_t idx, sei_tranceiver_config_t *config) +{ + uint32_t tmp; + uint32_t baudrate; + uint32_t baud_div; + uint32_t sync_point; + uint8_t data_len; + uint32_t ck0_point; + uint32_t ck1_point; + uint32_t txd_point; + uint32_t rxd_point; + + tmp = SEI_CTRL_XCVR_CTRL_TRISMP_SET(config->tri_sample) + | SEI_CTRL_XCVR_CTRL_MODE_SET(config->mode); + ptr->CTRL[idx].XCVR.CTRL = tmp; + + switch (config->mode) { + case sei_synchronous_master_mode: + tmp = SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(config->synchronous_master_config.data_idle_high_z) + | SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(config->synchronous_master_config.data_idle_state) + | SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(config->synchronous_master_config.clock_idle_high_z) + | SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(config->synchronous_master_config.clock_idle_state); + ptr->CTRL[idx].XCVR.TYPE_CFG = tmp; + + baud_div = (config->src_clk_freq + (config->synchronous_master_config.baudrate >> 1u)) / config->synchronous_master_config.baudrate; + sync_point = baud_div >> 1u; + tmp = SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(sync_point) + | SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(baud_div - 1u); + ptr->CTRL[idx].XCVR.BAUD_CFG = tmp; + + ck0_point = baud_div >> 2u; + ck1_point = ck0_point * 3u; + tmp = SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(ck0_point) + | SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(ck1_point); + ptr->CTRL[idx].XCVR.CLK_CFG = tmp; + break; + + case sei_synchronous_slave_mode: + tmp = SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(config->synchronous_slave_config.data_idle_high_z) + | SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(config->synchronous_slave_config.data_idle_state) + | SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(config->synchronous_slave_config.clock_idle_high_z) + | SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(config->synchronous_slave_config.clock_idle_state); + ptr->CTRL[idx].XCVR.TYPE_CFG = tmp; + + baud_div = (config->src_clk_freq + (config->synchronous_slave_config.max_baudrate >> 1u)) / config->synchronous_slave_config.max_baudrate; + sync_point = (baud_div * 3u) >> 3u; + tmp = SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(sync_point) + | SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(baud_div - 1u); + ptr->CTRL[idx].XCVR.BAUD_CFG = tmp; + + ck0_point = config->synchronous_slave_config.ck0_timeout_us * (config->src_clk_freq / 1000000u); + if (ck0_point > 0x7FFFu) { + ck0_point = 0x7FFFu; + } + ck1_point = config->synchronous_slave_config.ck1_timeout_us * (config->src_clk_freq / 1000000u); + if (ck1_point > 0x7FFFu) { + ck1_point = 0x7FFFu; + } + ck1_point += 0x8000u; + tmp = SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(ck0_point) + | SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(ck1_point); + ptr->CTRL[idx].XCVR.CLK_CFG = tmp; + break; + + case sei_asynchronous_mode: + default: + data_len = config->asynchronous_config.data_len; + if (data_len > 0u) { + data_len--; + } + tmp = SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(config->asynchronous_config.wait_len) + | SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(data_len) + | SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(config->asynchronous_config.parity) + | SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(config->asynchronous_config.parity_enable) + | SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(config->asynchronous_config.data_idle_high_z) + | SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(config->asynchronous_config.data_idle_state); + ptr->CTRL[idx].XCVR.TYPE_CFG = tmp; + + baudrate = (config->asynchronous_config.baudrate / 100) * 102; + baud_div = (config->src_clk_freq + (baudrate >> 1u)) / baudrate; + sync_point = (baud_div + 2u); + tmp = SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(sync_point) + | SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(baud_div - 1u); + ptr->CTRL[idx].XCVR.BAUD_CFG = tmp; + + txd_point = 0; + rxd_point = baud_div >> 1u; + tmp = SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(txd_point) + | SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(rxd_point); + ptr->CTRL[idx].XCVR.DATA_CFG = tmp; + break; + } + + return status_success; +} + +hpm_stat_t sei_cmd_data_format_config_init(SEI_Type *ptr, bool cmd_data_select, uint8_t idx, sei_data_format_config_t *config) +{ + uint32_t tmp; + uint8_t word_len; + uint8_t crc_len; + + word_len = config->word_len; + if (word_len > 0u) { + word_len--; + } + crc_len = config->crc_len; + if (crc_len > 0u) { + crc_len--; + } + tmp = SEI_DAT_MODE_MODE_SET(config->mode) + | SEI_DAT_MODE_SIGNED_SET(config->signed_flag) + | SEI_DAT_MODE_BORDER_SET(config->bit_order) + | SEI_DAT_MODE_WORDER_SET(config->word_order) + | SEI_DAT_MODE_CRC_INV_SET(config->crc_invert) + | SEI_DAT_MODE_CRC_SHIFT_SET(config->crc_shift_mode) + | SEI_DAT_MODE_WLEN_SET(word_len) + | SEI_DAT_MODE_CRC_LEN_SET(crc_len); + if (cmd_data_select) { + ptr->CTRL[idx].CMD.MODE = tmp; + } else { + ptr->DAT[idx].MODE = tmp; + } + + tmp = SEI_DAT_IDX_LAST_BIT_SET(config->last_bit) + | SEI_DAT_IDX_FIRST_BIT_SET(config->first_bit) + | SEI_DAT_IDX_MAX_BIT_SET(config->max_bit) + | SEI_DAT_IDX_MIN_BIT_SET(config->min_bit); + if (cmd_data_select) { + ptr->CTRL[idx].CMD.IDX = tmp; + } else { + ptr->DAT[idx].IDX = tmp; + } + + tmp = SEI_DAT_GOLD_GOLD_VALUE_SET(config->gold_value); + if (cmd_data_select) { + ptr->CTRL[idx].CMD.GOLD = tmp; + } else { + ptr->DAT[idx].GOLD = tmp; + } + + tmp = SEI_DAT_CRCINIT_CRC_INIT_SET(config->crc_init_value); + if (cmd_data_select) { + ptr->CTRL[idx].CMD.CRCINIT = tmp; + } else { + ptr->DAT[idx].CRCINIT = tmp; + } + + tmp = SEI_DAT_CRCPOLY_CRC_POLY_SET(config->crc_poly); + if (cmd_data_select) { + ptr->CTRL[idx].CMD.CRCPOLY = tmp; + } else { + ptr->DAT[idx].CRCPOLY = tmp; + } + + if (cmd_data_select) { + ptr->CTRL[idx].CMD.MODE |= SEI_CTRL_CMD_MODE_REWIND_MASK; + } else { + ptr->DAT[idx].MODE |= SEI_DAT_MODE_REWIND_MASK; + } + + return status_success; +} + +hpm_stat_t sei_cmd_table_config_init(SEI_Type *ptr, uint8_t idx, uint8_t table_idx, sei_command_table_config_t *config) +{ + uint32_t tmp; + + tmp = SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(config->cmd_min_value); + ptr->CTRL[idx].CMD_TABLE[table_idx].MIN = tmp; + + tmp = SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(config->cmd_max_value); + ptr->CTRL[idx].CMD_TABLE[table_idx].MAX = tmp; + + tmp = SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(config->cmd_mask_value); + ptr->CTRL[idx].CMD_TABLE[table_idx].MSK = tmp; + + tmp = SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(config->instr_idx[3]) + | SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(config->instr_idx[2]) + | SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(config->instr_idx[1]) + | SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(config->instr_idx[0]); + ptr->CTRL[idx].CMD_TABLE[table_idx].PTA = tmp; + + tmp = SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(config->instr_idx[7]) + | SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(config->instr_idx[6]) + | SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(config->instr_idx[5]) + | SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(config->instr_idx[4]); + ptr->CTRL[idx].CMD_TABLE[table_idx].PTB = tmp; + + tmp = SEI_CTRL_CMD_TABLE_PTC_PTR11_SET(config->instr_idx[11]) + | SEI_CTRL_CMD_TABLE_PTC_PTR10_SET(config->instr_idx[10]) + | SEI_CTRL_CMD_TABLE_PTC_PTR9_SET(config->instr_idx[9]) + | SEI_CTRL_CMD_TABLE_PTC_PTR8_SET(config->instr_idx[8]); + ptr->CTRL[idx].CMD_TABLE[table_idx].PTC = tmp; + + tmp = SEI_CTRL_CMD_TABLE_PTD_PTR15_SET(config->instr_idx[15]) + | SEI_CTRL_CMD_TABLE_PTD_PTR14_SET(config->instr_idx[14]) + | SEI_CTRL_CMD_TABLE_PTD_PTR13_SET(config->instr_idx[13]) + | SEI_CTRL_CMD_TABLE_PTD_PTR12_SET(config->instr_idx[12]); + ptr->CTRL[idx].CMD_TABLE[table_idx].PTD = tmp; + + return status_success; +} + +hpm_stat_t sei_state_transition_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, uint8_t state, sei_state_transition_config_t *config) +{ + uint32_t tmp = 0x08u; + + tmp |= SEI_CTRL_LATCH_TRAN_POINTER_SET(config->instr_ptr_value) + | SEI_CTRL_LATCH_TRAN_CFG_TM_SET(config->timeout_cfg) + | SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(config->txd_cfg) + | SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(config->clk_cfg) + | SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(config->instr_ptr_cfg) + | SEI_CTRL_LATCH_TRAN_OV_TM_SET(config->disable_timeout_check) + | SEI_CTRL_LATCH_TRAN_OV_TXD_SET(config->disable_txd_check) + | SEI_CTRL_LATCH_TRAN_OV_CLK_SET(config->disable_clk_check) + | SEI_CTRL_LATCH_TRAN_OV_PTR_SET(config->disable_instr_ptr_check); + ptr->CTRL[idx].LATCH[latch_idx].TRAN[state] = tmp; + + return status_success; +} + +hpm_stat_t sei_state_transition_latch_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, sei_state_transition_latch_config_t *config) +{ + uint32_t tmp; + + tmp = SEI_CTRL_LATCH_CFG_DELAY_SET(config->delay) + | SEI_CTRL_LATCH_CFG_SELECT_SET(config->output_select) + | SEI_CTRL_LATCH_CFG_EN_SET(config->enable); + ptr->CTRL[idx].LATCH[latch_idx].CFG = tmp; + + return status_success; +} + +hpm_stat_t sei_sample_config_init(SEI_Type *ptr, uint8_t idx, sei_sample_config_t *config) +{ + uint32_t tmp; + + tmp = SEI_CTRL_POS_SMP_CFG_ONCE_SET(config->sample_once) + | SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(config->latch_select) + | SEI_CTRL_POS_SMP_CFG_WINDOW_SET(config->sample_window); + ptr->CTRL[idx].POS.SMP_CFG = tmp; + + ptr->CTRL[idx].POS.SMP_DAT = SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(config->data_register_select); + + tmp = SEI_CTRL_POS_SMP_EN_ACC_EN_SET(config->acc_data_use_rx) + | SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(config->acc_data_idx) + | SEI_CTRL_POS_SMP_EN_SPD_EN_SET(config->spd_data_use_rx) + | SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(config->spd_data_idx) + | SEI_CTRL_POS_SMP_EN_REV_EN_SET(config->rev_data_use_rx) + | SEI_CTRL_POS_SMP_EN_REV_SEL_SET(config->rev_data_idx) + | SEI_CTRL_POS_SMP_EN_POS_EN_SET(config->pos_data_use_rx) + | SEI_CTRL_POS_SMP_EN_POS_SEL_SET(config->pos_data_idx); + ptr->CTRL[idx].POS.SMP_EN = tmp; + + return status_success; +} + +hpm_stat_t sei_update_config_init(SEI_Type *ptr, uint8_t idx, sei_update_config_t *config) +{ + uint32_t tmp; + + tmp = SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(config->time_use_override) + | SEI_CTRL_POS_UPD_CFG_ONERR_SET(config->update_on_err) + | SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(config->latch_select); + ptr->CTRL[idx].POS.UPD_CFG = tmp; + + ptr->CTRL[idx].POS.UPD_DAT = SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(config->data_register_select); + + tmp = SEI_CTRL_POS_UPD_EN_ACC_EN_SET(config->acc_data_use_rx) + | SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(config->acc_data_idx) + | SEI_CTRL_POS_UPD_EN_SPD_EN_SET(config->spd_data_use_rx) + | SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(config->spd_data_idx) + | SEI_CTRL_POS_UPD_EN_REV_EN_SET(config->rev_data_use_rx) + | SEI_CTRL_POS_UPD_EN_REV_SEL_SET(config->rev_data_idx) + | SEI_CTRL_POS_UPD_EN_POS_EN_SET(config->pos_data_use_rx) + | SEI_CTRL_POS_UPD_EN_POS_SEL_SET(config->pos_data_idx); + ptr->CTRL[idx].POS.UPD_EN = tmp; + + return status_success; +} + +hpm_stat_t sei_trigger_input_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_input_config_t *config) +{ + uint32_t tmp; + uint32_t period; + + tmp = SEI_CTRL_TRG_PRD_CFG_ARMING_SET(config->trig_period_arming_mode) + | SEI_CTRL_TRG_PRD_CFG_SYNC_SET(config->trig_period_sync_enable); + ptr->CTRL[idx].TRG.PRD_CFG = tmp; + + period = config->trig_period_time; + if (period > 0) { + period--; + } + ptr->CTRL[idx].TRG.PRD = SEI_CTRL_TRG_PRD_PERIOD_SET(period); + + tmp = SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(config->trig_period_enable) + | SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(config->trig_period_sync_select) + | SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(config->trig_in1_enable) + | SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(config->trig_in1_select) + | SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(config->trig_in0_enable) + | SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(config->trig_in0_select); + ptr->CTRL[idx].TRG.IN_CFG = tmp; + + return status_success; +} + +hpm_stat_t sei_trigger_output_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_output_config_t *config) +{ + uint32_t tmp; + + tmp = ptr->CTRL[idx].TRG.OUT_CFG; + if (config->src_latch_select == SEI_LATCH_0) { + tmp &= ~(SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK | SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK); + tmp |= SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(config->trig_out_enable) | SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(config->trig_out_select); + } else if (config->src_latch_select == SEI_LATCH_1) { + tmp &= ~(SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK | SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK); + tmp |= SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(config->trig_out_enable) | SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(config->trig_out_select); + } else if (config->src_latch_select == SEI_LATCH_2) { + tmp &= ~(SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK | SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK); + tmp |= SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(config->trig_out_enable) | SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(config->trig_out_select); + } else if (config->src_latch_select == SEI_LATCH_3) { + tmp &= ~(SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK | SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK); + tmp |= SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(config->trig_out_enable) | SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(config->trig_out_select); + } else { + return status_invalid_argument; + } + ptr->CTRL[idx].TRG.OUT_CFG = tmp; + + return status_success; +} + +hpm_stat_t sei_engine_config_init(SEI_Type *ptr, uint8_t idx, sei_engine_config_t *config) +{ + uint32_t tmp; + + tmp = SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(config->data_cdm_idx) + | SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(config->data_base_idx) + | SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(config->wdg_instr_idx) + | SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(config->init_instr_idx); + ptr->CTRL[idx].ENGINE.PTR_CFG = tmp; + + ptr->CTRL[idx].ENGINE.WDG_CFG = SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(config->wdg_time); + + tmp = SEI_CTRL_ENGINE_CTRL_WATCH_SET(config->wdg_enable) + | SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(config->wdg_action) + | SEI_CTRL_ENGINE_CTRL_ARMING_SET(config->arming_mode); + ptr->CTRL[idx].ENGINE.CTRL = tmp; + + return status_success; +} + +void sei_set_instr(SEI_Type *ptr, uint8_t idx, uint8_t op, uint8_t ck, uint8_t crc, uint8_t data, uint8_t opr) +{ + uint32_t tmp; + + if ((op != SEI_INSTR_OP_HALT) && (op != SEI_INSTR_OP_JUMP) && (opr > 0)) { + opr--; + } + if (opr > 0x1F) { + opr = 0x1F; + } + tmp = SEI_INSTR_OP_SET(op) + | SEI_INSTR_CK_SET(ck) + | SEI_INSTR_CRC_SET(crc) + | SEI_INSTR_DAT_SET(data) + | SEI_INSTR_OPR_SET(opr); + + ptr->INSTR[idx] = tmp; +} diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c index 08114939..9b34a638 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c @@ -304,6 +304,9 @@ void spi_master_get_default_control_config(spi_control_config_t *config) config->common_config.trans_mode = spi_trans_write_only; config->common_config.data_phase_fmt = spi_single_io_mode; config->common_config.dummy_cnt = spi_dummy_count_2; +#if defined(SPI_SOC_HAS_CS_SELECT) && (SPI_SOC_HAS_CS_SELECT == 1) + config->common_config.cs_index = spi_cs_0; +#endif } void spi_slave_get_default_control_config(spi_control_config_t *config) @@ -314,18 +317,27 @@ void spi_slave_get_default_control_config(spi_control_config_t *config) config->common_config.trans_mode = spi_trans_read_only; config->common_config.data_phase_fmt = spi_single_io_mode; config->common_config.dummy_cnt = spi_dummy_count_2; +#if defined(SPI_SOC_HAS_CS_SELECT) && (SPI_SOC_HAS_CS_SELECT == 1) + config->common_config.cs_index = spi_cs_0; +#endif } hpm_stat_t spi_master_timing_init(SPI_Type *ptr, spi_timing_config_t *config) { uint8_t sclk_div; - + uint8_t div_remainder; + uint8_t div_integer; if (config->master_config.sclk_freq_in_hz == 0) { return status_invalid_argument; } if (config->master_config.clk_src_freq_in_hz > config->master_config.sclk_freq_in_hz) { - sclk_div = (config->master_config.clk_src_freq_in_hz / config->master_config.sclk_freq_in_hz) / 2 - 1; + div_remainder = (config->master_config.clk_src_freq_in_hz % config->master_config.sclk_freq_in_hz); + div_integer = (config->master_config.clk_src_freq_in_hz / config->master_config.sclk_freq_in_hz); + if ((div_remainder != 0) || ((div_integer % 2) != 0)) { + return status_invalid_argument; + } + sclk_div = (div_integer / 2) - 1; } else { sclk_div = 0xff; } @@ -372,6 +384,15 @@ hpm_stat_t spi_control_init(SPI_Type *ptr, spi_control_config_t *config, uint32_ SPI_TRANSCTRL_DUMMYCNT_SET(config->common_config.dummy_cnt) | SPI_TRANSCTRL_RDTRANCNT_SET(rcount - 1); +#if defined(SPI_SOC_HAS_CS_SELECT) && (SPI_SOC_HAS_CS_SELECT == 1) + ptr->CTRL = (ptr->CTRL & ~SPI_CTRL_CS_EN_MASK) | SPI_CTRL_CS_EN_SET(config->common_config.cs_index); +#endif + +#if defined(SPI_SOC_HAS_NEW_TRANS_COUNT) && (SPI_SOC_HAS_NEW_TRANS_COUNT == 1) + ptr->WR_TRANS_CNT = wcount - 1; + ptr->RD_TRANS_CNT = rcount - 1; +#endif + /* reset txfifo, rxfifo and control */ ptr->CTRL |= SPI_CTRL_TXFIFORST_MASK | SPI_CTRL_RXFIFORST_MASK | SPI_CTRL_SPIRST_MASK; @@ -481,3 +502,120 @@ hpm_stat_t spi_setup_dma_transfer(SPI_Type *ptr, return stat; } + +#if defined(SPI_SOC_SUPPORT_DIRECTIO) && (SPI_SOC_SUPPORT_DIRECTIO == 1) +hpm_stat_t spi_directio_enable_output(SPI_Type *ptr, spi_directio_pin_t pin) +{ + hpm_stat_t stat = status_success; + switch (pin) { + case hold_pin: + ptr->DIRECTIO |= SPI_DIRECTIO_HOLD_OE_MASK; + break; + case wp_pin: + ptr->DIRECTIO |= SPI_DIRECTIO_WP_OE_MASK; + break; + case miso_pin: + ptr->DIRECTIO |= SPI_DIRECTIO_MISO_OE_MASK; + break; + case mosi_pin: + ptr->DIRECTIO |= SPI_DIRECTIO_MOSI_OE_MASK; + break; + case sclk_pin: + ptr->DIRECTIO |= SPI_DIRECTIO_SCLK_OE_MASK; + break; + case cs_pin: + ptr->DIRECTIO |= SPI_DIRECTIO_CS_OE_MASK; + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t spi_directio_disable_output(SPI_Type *ptr, spi_directio_pin_t pin) +{ + hpm_stat_t stat = status_success; + switch (pin) { + case hold_pin: + ptr->DIRECTIO &= ~SPI_DIRECTIO_HOLD_OE_MASK; + break; + case wp_pin: + ptr->DIRECTIO &= ~SPI_DIRECTIO_WP_OE_MASK; + break; + case miso_pin: + ptr->DIRECTIO &= ~SPI_DIRECTIO_MISO_OE_MASK; + break; + case mosi_pin: + ptr->DIRECTIO &= ~SPI_DIRECTIO_MOSI_OE_MASK; + break; + case sclk_pin: + ptr->DIRECTIO &= ~SPI_DIRECTIO_SCLK_OE_MASK; + break; + case cs_pin: + ptr->DIRECTIO &= ~SPI_DIRECTIO_CS_OE_MASK; + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t spi_directio_write(SPI_Type *ptr, spi_directio_pin_t pin, bool high) +{ + hpm_stat_t stat = status_success; + switch (pin) { + case hold_pin: + (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_HOLD_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_HOLD_O_MASK); + break; + case wp_pin: + (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_WP_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_WP_O_MASK); + break; + case miso_pin: + (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_MISO_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_MISO_O_MASK); + break; + case mosi_pin: + (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_MOSI_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_MOSI_O_MASK); + break; + case sclk_pin: + (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_SCLK_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_SCLK_O_MASK); + break; + case cs_pin: + (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_CS_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_CS_O_MASK); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +uint8_t spi_directio_read(SPI_Type *ptr, spi_directio_pin_t pin) +{ + uint8_t io_sta = 0; + switch (pin) { + case hold_pin: + io_sta = SPI_DIRECTIO_HOLD_I_GET(ptr->DIRECTIO); + break; + case wp_pin: + io_sta = SPI_DIRECTIO_WP_I_GET(ptr->DIRECTIO); + break; + case miso_pin: + io_sta = SPI_DIRECTIO_MISO_I_GET(ptr->DIRECTIO); + break; + case mosi_pin: + io_sta = SPI_DIRECTIO_MOSI_I_GET(ptr->DIRECTIO); + break; + case sclk_pin: + io_sta = SPI_DIRECTIO_SCLK_I_GET(ptr->DIRECTIO); + break; + case cs_pin: + io_sta = SPI_DIRECTIO_CS_I_GET(ptr->DIRECTIO); + break; + default: + break; + } + return io_sta; +} +#endif diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c index 79195940..ce297996 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c @@ -39,6 +39,12 @@ void uart_default_config(UART_Type *ptr, uart_config_t *config) config->rxidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one; config->rxidle_config.threshold = 10; /* 10-bit for typical UART configuration (8-N-1) */ #endif +#if defined(UART_SOC_HAS_TXLINE_IDLE_DETECTION) && (UART_SOC_HAS_TXLINE_IDLE_DETECTION == 1) + config->txidle_config.detect_enable = false; + config->txidle_config.detect_irq_enable = false; + config->txidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one; + config->txidle_config.threshold = 10; /* 10-bit for typical UART configuration (8-N-1) */ +#endif #if defined(UART_SOC_HAS_RXEN_CFG) && (UART_SOC_HAS_RXEN_CFG == 1) config->rx_enable = true; #endif @@ -156,32 +162,27 @@ hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config) ptr->LCR = tmp | UART_LCR_WLS_SET(config->word_length); -#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) +#if defined(UART_SOC_HAS_FINE_FIFO_THR) && (UART_SOC_HAS_FINE_FIFO_THR == 1) + /* reset TX and RX fifo */ ptr->FCRR = UART_FCRR_TFIFORST_MASK | UART_FCRR_RFIFORST_MASK; - if (config->fifo_enable) { - /* Enable FIFO, reset TX and RX. */ - if (config->using_new_fifo_thr) { - ptr->FCRR = UART_FCRR_FIFOT4EN_MASK - | UART_FCRR_FIFOE_MASK - | UART_FCRR_TFIFOT4_SET(config->tx_fifo_level) - | UART_FCRR_RFIFOT4_SET(config->rx_fifo_level) - | UART_FCRR_DMAE_SET(config->dma_enable); - } else { - ptr->FCR = UART_FCRR_FIFOE_MASK - | UART_FCRR_TFIFOT_SET(config->tx_fifo_level) - | UART_FCRR_RFIFOT_SET(config->rx_fifo_level) - | UART_FCRR_DMAE_SET(config->dma_enable); - } - } + /* Enable FIFO */ + ptr->FCRR = UART_FCRR_FIFOT4EN_MASK + | UART_FCRR_FIFOE_SET(config->fifo_enable) + | UART_FCRR_TFIFOT4_SET(config->tx_fifo_level) + | UART_FCRR_RFIFOT4_SET(config->rx_fifo_level) + | UART_FCRR_DMAE_SET(config->dma_enable); + #else + /* reset TX and RX fifo */ ptr->FCR = UART_FCR_TFIFORST_MASK | UART_FCR_RFIFORST_MASK; - if (config->fifo_enable) { - /* Enable FIFO, reset TX and RX. */ - ptr->FCR = UART_FCR_FIFOE_MASK - | UART_FCR_TFIFOT_SET(config->tx_fifo_level) - | UART_FCR_RFIFOT_SET(config->rx_fifo_level) - | UART_FCR_DMAE_SET(config->dma_enable); - } + /* Enable FIFO */ + tmp = UART_FCR_FIFOE_SET(config->fifo_enable) + | UART_FCR_TFIFOT_SET(config->tx_fifo_level) + | UART_FCR_RFIFOT_SET(config->rx_fifo_level) + | UART_FCR_DMAE_SET(config->dma_enable); + ptr->FCR = tmp; + /* store FCR register value */ + ptr->GPR = tmp; #endif uart_modem_config(ptr, &config->modem_config); @@ -307,9 +308,12 @@ hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *source, uint32_t size_in_byte #if defined(UART_SOC_HAS_RXLINE_IDLE_DETECTION) && (UART_SOC_HAS_RXLINE_IDLE_DETECTION == 1) hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t rxidle_config) { - ptr->IDLE_CFG = UART_IDLE_CFG_RX_IDLE_EN_SET(rxidle_config.detect_enable) - | UART_IDLE_CFG_RX_IDLE_THR_SET(rxidle_config.threshold) - | UART_IDLE_CFG_RX_IDLE_COND_SET(rxidle_config.idle_cond); + ptr->IDLE_CFG &= ~(UART_IDLE_CFG_RX_IDLE_EN_MASK + | UART_IDLE_CFG_RX_IDLE_THR_MASK + | UART_IDLE_CFG_RX_IDLE_COND_MASK); + ptr->IDLE_CFG |= UART_IDLE_CFG_RX_IDLE_EN_SET(rxidle_config.detect_enable) + | UART_IDLE_CFG_RX_IDLE_THR_SET(rxidle_config.threshold) + | UART_IDLE_CFG_RX_IDLE_COND_SET(rxidle_config.idle_cond); if (rxidle_config.detect_irq_enable) { uart_enable_irq(ptr, uart_intr_rx_line_idle); @@ -321,11 +325,29 @@ hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_conf } #endif -#if defined(UART_SOC_HAS_NEW_FIFO_THR) && (UART_SOC_HAS_NEW_FIFO_THR == 1) -void uart_config_trig_mode(UART_Type *ptr, uart_trig_config_t *config) +#if defined(UART_SOC_HAS_TXLINE_IDLE_DETECTION) && (UART_SOC_HAS_TXLINE_IDLE_DETECTION == 1) +hpm_stat_t uart_init_txline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t txidle_config) { - ptr->MOTO_CFG &= ~UART_MOTO_CFG_TXSTP_BITS_MASK; + ptr->IDLE_CFG &= ~(UART_IDLE_CFG_TX_IDLE_EN_MASK + | UART_IDLE_CFG_TX_IDLE_THR_MASK + | UART_IDLE_CFG_TX_IDLE_COND_MASK); + ptr->IDLE_CFG |= UART_IDLE_CFG_TX_IDLE_EN_SET(txidle_config.detect_enable) + | UART_IDLE_CFG_TX_IDLE_THR_SET(txidle_config.threshold) + | UART_IDLE_CFG_TX_IDLE_COND_SET(txidle_config.idle_cond); + + if (txidle_config.detect_irq_enable) { + uart_enable_irq(ptr, uart_intr_tx_line_idle); + } else { + uart_disable_irq(ptr, uart_intr_tx_line_idle); + } + + return status_success; +} +#endif +#if defined(UART_SOC_HAS_TRIG_MODE) && (UART_SOC_HAS_TRIG_MODE == 1) +void uart_config_transfer_trig_mode(UART_Type *ptr, uart_trig_config_t *config) +{ ptr->MOTO_CFG = UART_MOTO_CFG_TXSTP_BITS_SET(config->stop_bit_len) | UART_MOTO_CFG_HWTRG_EN_SET(config->hardware_trig) | UART_MOTO_CFG_TRG_MODE_SET(config->trig_mode) @@ -334,13 +356,28 @@ void uart_config_trig_mode(UART_Type *ptr, uart_trig_config_t *config) } #endif -/* FCR is WO register, preprae all bit field to write */ +/* fifo control register(FCR) is WO access, if support FCCR register, it is RW access. */ void uart_config_fifo_ctrl(UART_Type *ptr, uart_fifo_ctrl_t *ctrl) { +#if defined(UART_SOC_HAS_FINE_FIFO_THR) && (UART_SOC_HAS_FINE_FIFO_THR == 1) + ptr->FCRR = UART_FCRR_FIFOT4EN_MASK + | UART_FCRR_TFIFOT4_SET(ctrl->tx_fifo_level) + | UART_FCRR_RFIFOT4_SET(ctrl->rx_fifo_level) + | UART_FCRR_DMAE_SET(ctrl->dma_enable) + | UART_FCRR_TFIFORST_SET(ctrl->reset_tx_fifo) + | UART_FCRR_RFIFORST_SET(ctrl->reset_rx_fifo) + | UART_FCRR_FIFOE_SET(ctrl->fifo_enable); +#else ptr->FCR = UART_FCR_TFIFOT_SET(ctrl->tx_fifo_level) | UART_FCR_RFIFOT_SET(ctrl->rx_fifo_level) | UART_FCR_TFIFORST_SET(ctrl->reset_tx_fifo) | UART_FCR_RFIFORST_SET(ctrl->reset_rx_fifo) | UART_FCR_DMAE_SET(ctrl->dma_enable) | UART_FCR_FIFOE_SET(ctrl->fifo_enable); + /* store FCR to GPR */ + ptr->GPR = UART_FCR_TFIFOT_SET(ctrl->tx_fifo_level) + | UART_FCR_RFIFOT_SET(ctrl->rx_fifo_level) + | UART_FCR_DMAE_SET(ctrl->dma_enable) + | UART_FCR_FIFOE_SET(ctrl->fifo_enable); +#endif } \ No newline at end of file diff --git a/common/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c b/common/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c index cf94890f..74c0bea3 100644 --- a/common/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c +++ b/common/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c @@ -58,6 +58,7 @@ void usb_phy_init(USB_Type *ptr) { uint32_t status; + usb_phy_enable_dp_dm_pulldown(ptr); ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* set otg_utmi_reset_sw for naneng usbphy */ ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* clr otg_utmi_suspend_m for naneng usbphy */ ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK; /* clr cfg_rst_n */ @@ -68,8 +69,8 @@ void usb_phy_init(USB_Type *ptr) ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* set otg_utmi_suspend_m for naneng usbphy */ - for (int i = 0; i < USB_PHY_INIT_DELAY_COUNT; i++) { - ptr->PHY_CTRL0 = USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(0); /* used for delay */ + for (volatile int i = 0; i < USB_PHY_INIT_DELAY_COUNT; i++) { + (void)ptr->PHY_CTRL1; /* used for delay */ } ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* clear otg_utmi_reset_sw for naneng usbphy */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/CMakeLists.txt b/common/libraries/hpm_sdk/soc/HPM5361/CMakeLists.txt new file mode 100644 index 00000000..4aa8c60a --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/CMakeLists.txt @@ -0,0 +1,59 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +sdk_inc(toolchains) + +if(NOT DEFINED USE_CUSTOM_STARTUP) + sdk_gcc_src(toolchains/gcc/start.S) + sdk_ses_src(toolchains/segger/startup.s) +endif() + +sdk_src( + toolchains/reset.c + toolchains/trap.c + system.c +) + +sdk_gcc_src(toolchains/gcc/initfini.c) + +# soc drivers +sdk_src ( + hpm_sysctl_drv.c + hpm_l1c_drv.c + hpm_clock_drv.c + hpm_otp_drv.c +) + +if(${INCLUDE_BOOTHEADER}) + sdk_inc(boot) + sdk_src(boot/hpm_bootheader.c) +endif() + +sdk_nds_compile_options(-mcpu=d25) + +set(SOC_LINKER_SCRIPT "" PARENT_SCOPE) +if(NOT DEFINED USE_CUSTOM_LINKER) + if(${LINK_TO_FLASH}) + if(${INCLUDE_BOOTHEADER}) + if(${FLASH_XIP}) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/flash_xip.ld PARENT_SCOPE) + else() + if(${FLASH_SDRAM_XIP}) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/flash_sdram_xip.ld PARENT_SCOPE) + endif() + endif() + else() + if(${FLASH_UF2}) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/flash_uf2.ld PARENT_SCOPE) + else() + if(${FLASH_SDRAM_UF2}) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/flash_sdram_uf2.ld PARENT_SCOPE) + else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/flash.ld PARENT_SCOPE) + endif() + endif() + endif() + else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/toolchains/gcc/ram.ld PARENT_SCOPE) + endif() +endif() diff --git a/common/libraries/hpm_sdk/soc/HPM5361/HPM5361_svd.xml b/common/libraries/hpm_sdk/soc/HPM5361/HPM5361_svd.xml new file mode 100644 index 00000000..352f41bd --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/HPM5361_svd.xml @@ -0,0 +1,29609 @@ + + + HPMICRO + HPM5361 + HPM5300 + 1.0 + HPM5300 device + + /* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + + + other + r0p0 + little + false + true + true + 7 + false + + + + 8 + 32 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + + + FGPIO + FGPIO + GPIO + 0xc0000 + + 0x0 + 0x8f0 + registers + + + + 15 + 0x10 + gpioa,gpiob,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy + DI[%s] + no description available + 0x0 + + VALUE + GPIO input value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INPUT + GPIO input bus value, each bit represents a bus bit +0: low level presents on chip pin +1: high level presents on chip pin + 0 + 32 + read-only + + + + + + 15 + 0x10 + gpioa,gpiob,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy + DO[%s] + no description available + 0x100 + + VALUE + GPIO output value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + SET + GPIO output set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + CLEAR + GPIO output clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + TOGGLE + GPIO output toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + OUTPUT + GPIO output register value, each bit represents a bus bit +0: chip pin output low level when direction is output +1: chip pin output high level when direction is output + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy + OE[%s] + no description available + 0x200 + + VALUE + GPIO direction value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + SET + GPIO direction set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + CLEAR + GPIO direction clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + TOGGLE + GPIO direction toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + DIRECTION + GPIO direction, each bit represents a bus bit +0: input +1: output + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy + IF[%s] + no description available + 0x300 + + VALUE + GPIO interrupt flag value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_FLAG + GPIO interrupt flag, write 1 to clear this flag +0: no irq +1: irq pending + 0 + 32 + write-only + + + + + + 15 + 0x10 + gpioa,gpiob,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy + IE[%s] + no description available + 0x400 + + VALUE + GPIO interrupt enable value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + SET + GPIO interrupt enable set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt enable clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt enable toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_EN + GPIO interrupt enable, each bit represents a bus bit +0: irq is disabled +1: irq is enable + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy + PL[%s] + no description available + 0x500 + + VALUE + GPIO interrupt polarity value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt polarity set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt polarity clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt polarity toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_POL + GPIO interrupt polarity, each bit represents a bus bit +0: irq is high level or rising edge +1: irq is low level or falling edge + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy + TP[%s] + no description available + 0x600 + + VALUE + GPIO interrupt type value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + SET + GPIO interrupt type set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt type clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt type toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_TYPE + GPIO interrupt type, each bit represents a bus bit +0: irq is triggered by level +1: irq is triggered by edge + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy + AS[%s] + no description available + 0x700 + + VALUE + GPIO interrupt asynchronous value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + SET + GPIO interrupt asynchronous set + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + CLEAR + GPIO interrupt asynchronous clear + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + TOGGLE + GPIO interrupt asynchronous toggle + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + IRQ_ASYNC + GPIO interrupt asynchronous, each bit represents a bus bit +0: irq is triggered base on system clock +1: irq is triggered combinational +Note: combinational interrupt is sensitive to environment noise + 0 + 32 + read-write + + + + + + 15 + 0x10 + gpioa,gpiob,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy + PD[%s] + no description available + 0x800 + + VALUE + GPIO dual edge interrupt enable value + 0x0 + 32 + 0x00000000 + 0x00000001 + + + IRQ_DUAL + GPIO dual edge interrupt enable +0: single edge interrupt +1: dual edge interrupt enable + 0 + 1 + read-write + + + + + SET + GPIO dual edge interrupt enable set + 0x4 + 32 + 0x00000000 + 0x00000001 + + + IRQ_DUAL + GPIO dual edge interrupt enable set +0: keep original edge interrupt type +1: dual edge interrupt enable + 0 + 1 + read-write + + + + + CLEAR + GPIO dual edge interrupt enable clear + 0x8 + 32 + 0x00000000 + 0x00000001 + + + IRQ_DUAL + GPIO dual edge interrupt enable clear +0: keep original edge interrupt type +1: single edge interrupt enable + 0 + 1 + read-write + + + + + TOGGLE + GPIO dual edge interrupt enable toggle + 0xc + 32 + 0x00000000 + 0x00000001 + + + IRQ_DUAL + GPIO dual edge interrupt enable toggle +0: keep original edge interrupt type +1: change original edge interrupt type to another one. + 0 + 1 + read-write + + + + + + + + GPIO0 + GPIO0 + GPIO + 0xf00d0000 + + + PGPIO + PGPIO + GPIO + 0xf411c000 + + + PLIC + PLIC + PLIC + 0xe4000000 + + 0x0 + 0x201000 + registers + + + + feature + Feature enable register + 0x0 + 32 + 0x00000000 + 0x00000003 + + + VECTORED + Vector mode enable +0: Disabled +1: Enabled + 1 + 1 + read-write + + + PREEMPT + Preemptive priority interrupt enable +0: Disabled +1: Enabled + 0 + 1 + read-write + + + + + 127 + 0x4 + PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 + PRIORITY[%s] + no description available + 0x4 + 32 + 0x00000001 + 0xFFFFFFFF + + + PRIORITY + Interrupt source priority. The valid range of this field is 0-7. +0: Never interrupt +1-7: Interrupt source priority. The larger the value, the higher the priority. + 0 + 32 + read-write + + + + + 4 + 0x4 + PENDING0,PENDING1,PENDING2,PENDING3 + PENDING[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + 4 + 0x4 + TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 + TRIGGER[%s] + no description available + 0x1080 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. +0: Level-triggered interrupt +1: Edge-triggered interrupt + 0 + 32 + read-only + + + + + NUMBER + Number of supported interrupt sources and targets + 0x1100 + 32 + 0xFFFFFFFF + + + NUM_TARGET + The number of supported targets + 16 + 16 + read-only + + + NUM_INTERRUPT + The number of supported interrupt sources + 0 + 16 + read-only + + + + + INFO + Version and the maximum priority + 0x1104 + 32 + 0xFFFFFFFF + + + MAX_PRIORITY + The maximum priority supported + 16 + 16 + read-only + + + VERSION + The version of the PLIC design + 0 + 16 + read-only + + + + + 1 + 0x80 + target0 + TARGETINT[%s] + no description available + 0x2000 + + 4 + 0x4 + INTEN0,INTEN1,INTEN2,INTEN3 + INTEN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + INTERRUPT + The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. + 0 + 32 + read-write + + + + + + 1 + 0x1000 + target0 + TARGETCONFIG[%s] + no description available + 0x200000 + + THRESHOLD + Target0 priority threshold + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + THRESHOLD + Interrupt priority threshold. + 0 + 32 + read-write + + + + + CLAIM + Target claim and complete + 0x4 + 32 + 0x00000000 + 0x000003FF + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 10 + read-write + + + + + PPS + Preempted priority stack + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRIORITY_PREEMPTED + Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. + 0 + 32 + read-write + + + + + + + + MCHTMR + MCHTMR + MCHTMR + 0xe6000000 + + 0x0 + 0x10 + registers + + + + MTIME + Machine Time + 0x0 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIME + Machine time + 0 + 64 + read-write + + + + + MTIMECMP + Machine Time Compare + 0x8 + 64 + 0x0000000000020210 + 0xFFFFFFFFFFFFFFFF + + + MTIMECMP + Machine time compare + 0 + 64 + read-write + + + + + + + PLICSW + PLICSW + PLIC_SW + 0xe6400000 + + 0x1000 + 0x1ff008 + registers + + + + PENDING + Pending status + 0x1000 + 32 + 0x00000000 + 0x00000002 + + + INTERRUPT + writing 1 to trigger software interrupt + 1 + 1 + read-write + + + + + INTEN + Interrupt enable + 0x2000 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT + enable software interrupt + 0 + 1 + read-write + + + + + CLAIM + Claim and complete. + 0x200004 + 32 + 0x00000000 + 0x00000001 + + + INTERRUPT_ID + On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). + 0 + 1 + read-write + + + + + + + GPTMR0 + GPTMR0 + TMR + 0xf0000000 + + 0x0 + 0x20c + registers + + + + 4 + 0x40 + ch0,ch1,ch2,ch3 + CHANNEL[%s] + no description available + 0x0 + + CR + Control Register + 0x0 + 32 + 0x00000000 + 0xFFFC7FFF + + + CNTUPT + 1- update counter to new value as CNTUPTVAL +This bit will be auto cleared after 1 cycle + 31 + 1 + write-only + + + CNTRST + 1- reset counter + 14 + 1 + read-write + + + SYNCFLW + 1- enable this channel to reset counter to reload(RLD) together with its previous channel. +This bit is not valid for channel 0. + 13 + 1 + read-write + + + SYNCIFEN + 1- SYNCI is valid on its falling edge + 12 + 1 + read-write + + + SYNCIREN + 1- SYNCI is valid on its rising edge + 11 + 1 + read-write + + + CEN + 1- counter enable + 10 + 1 + read-write + + + CMPINIT + Output compare initial poliarity +1- The channel output initial level is high +0- The channel output initial level is low +User should set this bit before set CMPEN to 1. + 9 + 1 + read-write + + + CMPEN + 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. + 8 + 1 + read-write + + + DMASEL + select one of DMA request: +00- CMP0 flag +01- CMP1 flag +10- Input signal toggle captured +11- RLD flag, counter reload; + 6 + 2 + read-write + + + DMAEN + 1- enable dma + 5 + 1 + read-write + + + SWSYNCIEN + 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set + 4 + 1 + read-write + + + DBGPAUSE + 1- counter will pause if chip is in debug mode + 3 + 1 + read-write + + + CAPMODE + This bitfield define the input capture mode +100: width measure mode, timer will calculate the input signal period and duty cycle +011: capture at both rising edge and falling edge +010: capture at falling edge +001: capture at rising edge +000: No capture + 0 + 3 + read-write + + + + + 2 + 0x4 + CMP0,CMP1 + CMP[%s] + no description available + 0x4 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + CMP + compare value 0 + 0 + 32 + read-write + + + + + RLD + Reload register + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + RLD + reload value + 0 + 32 + read-write + + + + + CNTUPTVAL + Counter update value register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTUPTVAL + counter will be set to this value when software write cntupt bit in CR + 0 + 32 + read-write + + + + + CAPPOS + Capture rising edge register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPOS + This register contains the counter value captured at input signal rising edge + 0 + 32 + read-only + + + + + CAPNEG + Capture falling edge register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + This register contains the counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + CAPPRD + PWM period measure register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPPRD + This register contains the input signal period when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CAPDTY + PWM duty cycle measure register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + MEAS_HIGH + This register contains the input signal duty cycle when channel is configured to input capture measure mode. + 0 + 32 + read-only + + + + + CNT + Counter + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + 32 bit counter value + 0 + 32 + read-only + + + + + + SR + Status register + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1F + channel 3 compare value 1 match flag + 15 + 1 + write-only + + + CH3CMP0F + channel 3 compare value 1 match flag + 14 + 1 + write-only + + + CH3CAPF + channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 13 + 1 + write-only + + + CH3RLDF + channel 3 counter reload flag + 12 + 1 + write-only + + + CH2CMP1F + channel 2 compare value 1 match flag + 11 + 1 + write-only + + + CH2CMP0F + channel 2 compare value 1 match flag + 10 + 1 + write-only + + + CH2CAPF + channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 9 + 1 + write-only + + + CH2RLDF + channel 2 counter reload flag + 8 + 1 + write-only + + + CH1CMP1F + channel 1 compare value 1 match flag + 7 + 1 + write-only + + + CH1CMP0F + channel 1 compare value 1 match flag + 6 + 1 + write-only + + + CH1CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 5 + 1 + write-only + + + CH1RLDF + channel 1 counter reload flag + 4 + 1 + write-only + + + CH0CMP1F + channel 1 compare value 1 match flag + 3 + 1 + write-only + + + CH0CMP0F + channel 1 compare value 1 match flag + 2 + 1 + write-only + + + CH0CAPF + channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. + 1 + 1 + write-only + + + CH0RLDF + channel 1 counter reload flag + 0 + 1 + write-only + + + + + IRQEN + Interrupt request enable register + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + CH3CMP1EN + 1- generate interrupt request when ch3cmp1f flag is set + 15 + 1 + read-write + + + CH3CMP0EN + 1- generate interrupt request when ch3cmp0f flag is set + 14 + 1 + read-write + + + CH3CAPEN + 1- generate interrupt request when ch3capf flag is set + 13 + 1 + read-write + + + CH3RLDEN + 1- generate interrupt request when ch3rldf flag is set + 12 + 1 + read-write + + + CH2CMP1EN + 1- generate interrupt request when ch2cmp1f flag is set + 11 + 1 + read-write + + + CH2CMP0EN + 1- generate interrupt request when ch2cmp0f flag is set + 10 + 1 + read-write + + + CH2CAPEN + 1- generate interrupt request when ch2capf flag is set + 9 + 1 + read-write + + + CH2RLDEN + 1- generate interrupt request when ch2rldf flag is set + 8 + 1 + read-write + + + CH1CMP1EN + 1- generate interrupt request when ch1cmp1f flag is set + 7 + 1 + read-write + + + CH1CMP0EN + 1- generate interrupt request when ch1cmp0f flag is set + 6 + 1 + read-write + + + CH1CAPEN + 1- generate interrupt request when ch1capf flag is set + 5 + 1 + read-write + + + CH1RLDEN + 1- generate interrupt request when ch1rldf flag is set + 4 + 1 + read-write + + + CH0CMP1EN + 1- generate interrupt request when ch0cmp1f flag is set + 3 + 1 + read-write + + + CH0CMP0EN + 1- generate interrupt request when ch0cmp0f flag is set + 2 + 1 + read-write + + + CH0CAPEN + 1- generate interrupt request when ch0capf flag is set + 1 + 1 + read-write + + + CH0RLDEN + 1- generate interrupt request when ch0rldf flag is set + 0 + 1 + read-write + + + + + GCR + Global control register + 0x208 + 32 + 0x00000000 + 0x0000000F + + + SWSYNCT + set this bitfield to trigger software coutner sync event + 0 + 4 + read-write + + + + + + + GPTMR1 + GPTMR1 + TMR + 0xf0004000 + + + GPTMR2 + GPTMR2 + TMR + 0xf0008000 + + + GPTMR3 + GPTMR3 + TMR + 0xf000c000 + + + PTMR + PTMR + TMR + 0xf4120000 + + + LIN0 + LIN0 + LINV2 + 0xf0020000 + + 0x0 + 0x18 + registers + + + + 2 + 0x4 + data0,data1 + DATA[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data + 0 + 32 + read-write + + + + + 8 + 0x1 + data_byte0,data_byte1,data_byte2,data_byte3,data_byte4,data_byte5,data_byte6,data_byte7 + DATA_BYTE[%s] + no description available + 0x0 + 8 + 0x00 + 0xFF + + + DATA_BYTE + data byte + 0 + 8 + read-write + + + + + data_len_id + data length and ID register + 0x8 + 32 + 0x00000000 + 0x00FFFF8F + + + CHECKSUM + No description avaiable + 16 + 8 + read-only + + + ID_PARITY + No description avaiable + 14 + 2 + read-only + + + ID + ID register + 8 + 6 + read-write + + + ENH_CHECK + 1:enhance check mode 0:classical check mode + 7 + 1 + read-write + + + DATA_LEN + payload data length control register。The data length will decoded from ID[5:4] when all 1 is configured: 00-2 01-2 10-4 11-8 + 0 + 4 + read-write + + + + + control_status + control and status register + 0xc + 32 + 0x00000000 + 0x003FFFFF + + + BREAK_ERR_DIS + No description avaiable + 21 + 1 + read-write + + + BREAK_ERR + No description avaiable + 20 + 1 + read-only + + + PARITY_ERROR + slave only. identifier parity error + 19 + 1 + read-only + + + TIME_OUT + timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms + 18 + 1 + read-only + + + CHK_ERROR + checksum error + 17 + 1 + read-only + + + BIT_ERROR + bit error + 16 + 1 + read-only + + + LIN_ACTIVE + The bit indicates whether the LIN bus is active or not + 15 + 1 + read-only + + + BUS_IDLE_TIMEOUT + slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s + 14 + 1 + read-only + + + ABORTED + slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error. + 13 + 1 + read-only + + + DATA_REQ + slave only. Sets after receiving the identifier and requests an interrupt to the host controller. + 12 + 1 + read-only + + + INT + set when request an interrupt. Reset by reset_int + 11 + 1 + read-only + + + ERROR + set when detecte an error, clear by reset_error + 10 + 1 + read-only + + + WAKEUP + set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1 + 9 + 1 + read-only + + + COMPLETE + set after a transmission has been successful finished and it will reset at the start of a transmission. + 8 + 1 + read-only + + + STOP + slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID + 7 + 1 + write-only + + + SLEEP + The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core. + 6 + 1 + read-write + + + TRANSMIT + 1: transmit operation 0: receive operation + 5 + 1 + read-write + + + DATA_ACK + slave only. Write 1 after handling a data request interrupt + 4 + 1 + read-write + + + RESET_INT + set 1 will clear the int register + 3 + 1 + write-only + + + RESET_ERROR + set 1 will clear the error register, and also the timeout/complete/wakeup register + 2 + 1 + write-only + + + WAKEUP_REQ + set 1 will make LIN bus exit sleep mode, the bit auto cleared after a wakeup signal has been complete + 1 + 1 + read-write + + + START_REQ + master only. Set 1 will start lin transmission, the bit will be auto cleared when an error occur or the trasmission complete + 0 + 1 + read-write + + + + + timing_control + timing control register + 0x10 + 32 + 0x00400000 + 0x3F7FFFFF + + + WAKE_LEN + No description avaiable + 27 + 3 + read-write + + + BRK_LEN + No description avaiable + 24 + 3 + read-write + + + LINBUSDISABLE + 1：lin rx is disable + 22 + 1 + read-write + + + LIN_INITIAL + 1:initial lin controller + 21 + 1 + read-write + + + MASTER_MODE + 1：master mode + 20 + 1 + read-write + + + BUS_INACTIVE_TIME + slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s + 18 + 2 + read-write + + + WUP_REPEAT_TIME + slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms + 16 + 2 + read-write + + + PRESCL + prescl register + 14 + 2 + read-write + + + BT_MUL + bt_mul register + 9 + 5 + read-write + + + BT_DIV + bt_div register + 0 + 9 + read-write + + + + + dma_control + dma control register + 0x14 + 32 + 0x00000000 + 0x00001FFF + + + DMA_REQ_ENH_CHK + payload data checksum type for dma operation + 12 + 1 + read-write + + + DMA_REQ_LEN + paylaod length for dma request + 8 + 4 + read-write + + + DMA_REQ_ID_TYPE + 1：transmite 0：receive + 7 + 1 + read-write + + + DMA_REQ_ID + dma_req_id register + 1 + 6 + read-write + + + DMA_REQ_ENABLE + slave mode only. 1: enable dma request for data request ID equal dma_req_id + 0 + 1 + read-write + + + + + + + LIN1 + LIN1 + LINV2 + 0xf0024000 + + + LIN2 + LIN2 + LINV2 + 0xf0028000 + + + LIN3 + LIN3 + LINV2 + 0xf002c000 + + + UART0 + UART0 + UART + 0xf0040000 + + 0x4 + 0x3c + registers + + + + IDLE_CFG + Idle Configuration Register + 0x4 + 32 + 0x00000000 + 0x03FF0BFF + + + TX_IDLE_COND + IDLE Detection Condition +0 - Treat as idle if TX pin is logic one +1 - Treat as idle if UART state machine state is idle + 25 + 1 + read-write + + + TX_IDLE_EN + UART TX Idle Detect Enable +0 - Disable +1 - Enable + 24 + 1 + read-write + + + TX_IDLE_THR + Threshold for UART transmit Idle detection (in terms of bits) + 16 + 8 + read-write + + + RXEN + UART receive enable. +0 - hold RX input to high, avoide wrong data input when config pinmux +1 - bypass RX input from PIN +software should set it after config pinmux + 11 + 1 + read-write + + + RX_IDLE_COND + IDLE Detection Condition +0 - Treat as idle if RX pin is logic one +1 - Treat as idle if UART state machine state is idle + 9 + 1 + read-write + + + RX_IDLE_EN + UART Idle Detect Enable +0 - Disable +1 - Enable +it should be enabled if enable address match feature + 8 + 1 + read-write + + + RX_IDLE_THR + Threshold for UART Receive Idle detection (in terms of bits) + 0 + 8 + read-write + + + + + ADDR_CFG + address match config register + 0x8 + 32 + 0x00000000 + 0x001FFFFF + + + TXEN_9BIT + set to use 9bit mode for transmitter, +will set the MSB for the first character as address flag, keep 0 for others. + 20 + 1 + read-write + + + RXEN_ADDR_MSB + set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). +Clr to use first character as address. +Only needed if enable address match feature + 19 + 1 + read-write + + + RXEN_9BIT + set to use 9bit mode for receiver, only valid if rxen_addr_msb is set + 18 + 1 + read-write + + + A1_EN + enable addr1 compare for the first character. +If a1_en OR a0_en, then do not receive data if address not match. +If ~a1_en AND ~a0_en, the receive all data like before. +NOTE: should set idle_tmout_en if enable address match feature + 17 + 1 + read-write + + + A0_EN + enable addr0 compare for the first character + 16 + 1 + read-write + + + ADDR1 + address 1 fileld. +in 9bit mode, this is the full address byte. +For other mode(8/7/6/5bit), MSB should be set for address flag. +If want address==0 to be matched at 8bit mode, should set addr1=0x80 + 8 + 8 + read-write + + + ADDR0 + address 0 field. + 0 + 8 + read-write + + + + + IIR2 + Interrupt Identification Register2 + 0xc + 32 + 0x00000001 + 0xF80000CF + + + RXIDLE_FLAG + UART RX IDLE Flag, assert after rxd low and then rx idle timeout, write one clear +0 - UART RX is busy +1 - UART RX is idle + 31 + 1 + write-only + + + TXIDLE_FLAG + UART TX IDLE Flag, assert after txd low and then tx idle timeout, write one clear +0 - UART TX is busy +1 - UART TX is idle + 30 + 1 + write-only + + + ADDR_MATCH + address match irq status, assert if either address match(and enabled). Write one clear +NOTE: the address byte may not moved by DMA at this point. +User can wait next addr_match_idle irq for the whole data include address + 29 + 1 + write-only + + + ADDR_MATCH_IDLE + address match and idle irq status, assert at rx bus idle if address match event triggered. +Write one clear; + 28 + 1 + write-only + + + DATA_LOST + assert if data lost before address match status, write one clear; +It will not assert if no address match occurs + 27 + 1 + write-only + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID, see IIR2 for detail decoding + 0 + 4 + read-only + + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FIFOSIZE + The depth of RXFIFO and TXFIFO +0: 16-byte FIFO +1: 32-byte FIFO +2: 64-byte FIFO +3: 128-byte FIFO + 0 + 2 + read-only + + + + + OSCR + Over Sample Control Register + 0x14 + 32 + 0x00000010 + 0x0000001F + + + OSC + Over-sample control +The value must be an even number; any odd value +writes to this field will be converted to an even value. +OSC=0: The over-sample ratio is 32 +OSC<=8: The over-sample ratio is 8 +8 < OSC< 32: The over sample ratio is OSC + 0 + 5 + read-write + + + + + FCRR + FIFO Control Register config + 0x18 + 32 + 0x00000000 + 0x008F0FFF + + + FIFOT4EN + set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) +clr to use 2bit(TFIFOT and RFIFOT) + 23 + 1 + read-write + + + TFIFOT4 + txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold. + 16 + 4 + read-write + + + RFIFOT4 + rxfifo threshold(0 for 1byte, 0xF for 16bytes). +Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled + 8 + 4 + read-write + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + read-write + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + read-write + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + read-write + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + read-write + + + + + MOTO_CFG + moto system control register + 0x1c + 32 + 0x00000000 + 0x8000FFF0 + + + SWTRG + software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. +Hardware auto reset. + 31 + 1 + write-only + + + TXSTP_BITS + if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits + 8 + 8 + read-write + + + HWTRG_EN + set to enable hardware trigger(trigger from moto is shared by other UART) + 7 + 1 + read-write + + + TRG_MODE + set to enable trigger mode. +software should push needed data into txbuffer frist, uart will not start transmission at this time. +User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty +NOTE: the hw_trigger should be pulse signal from trig mux. + 6 + 1 + read-write + + + TRG_CLR_RFIFO + set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo. + 5 + 1 + read-write + + + TXSTOP_INSERT + set to insert STOP bits between each tx byte till tx fifo empty. +NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set + 4 + 1 + read-write + + + + + RBR + Receiver Buffer Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + RBR + Receive data read port + 0 + 8 + read-only + + + + + THR + Transmitter Holding Register (when DLAB = 0) + UNION_20 + 0x20 + 32 + 0x00000000 + 0x000000FF + + + THR + Transmit data write port + 0 + 8 + write-only + + + + + DLL + Divisor Latch LSB (when DLAB = 1) + UNION_20 + 0x20 + 32 + 0x00000001 + 0x000000FF + + + DLL + Least significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IER + Interrupt Enable Register (when DLAB = 0) + UNION_24 + 0x24 + 32 + 0x00000000 + 0xF800000F + + + ERXIDLE + Enable Receive Idle interrupt +0 - Disable Idle interrupt +1 - Enable Idle interrupt + 31 + 1 + read-write + + + ETXIDLE + enable transmit idle interrupt + 30 + 1 + read-write + + + EADDRM + enable ADDR_MATCH interrupt + 29 + 1 + read-write + + + EADDRM_IDLE + enable ADDR_MATCH_IDLE interrupt + 28 + 1 + read-write + + + EDATLOST + enable DATA_LOST interrupt + 27 + 1 + read-write + + + EMSI + Enable modem status interrupt +The interrupt asserts when the status of one of the +following occurs: +The status of modem_rin, modem_dcdn, +modem_dsrn or modem_ctsn (If the auto-cts mode is +disabled) has been changed. +If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), +modem_ctsn would be used to control the transmitter. + 3 + 1 + read-write + + + ELSI + Enable receiver line status interrupt + 2 + 1 + read-write + + + ETHEI + Enable transmitter holding register interrupt + 1 + 1 + read-write + + + ERBI + Enable received data available interrupt and the +character timeout interrupt +0: Disable +1: Enable + 0 + 1 + read-write + + + + + DLM + Divisor Latch MSB (when DLAB = 1) + UNION_24 + 0x24 + 32 + 0x00000000 + 0x000000FF + + + DLM + Most significant byte of the Divisor Latch + 0 + 8 + read-write + + + + + IIR + Interrupt Identification Register + UNION_28 + 0x28 + 32 + 0x00000001 + 0x800000CF + + + RXIDLE_FLAG + UART IDLE Flag +0 - UART is busy +1 - UART is idle +NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR + 31 + 1 + write-only + + + FIFOED + FIFOs enabled +These two bits are 1 when bit 0 of the FIFO Control +Register (FIFOE) is set to 1. + 6 + 2 + read-only + + + INTRID + Interrupt ID, see IIR2 for detail decoding + 0 + 4 + read-only + + + + + FCR + FIFO Control Register + UNION_28 + 0x28 + 32 + 0x00000000 + 0x000000FF + + + RFIFOT + Receiver FIFO trigger level + 6 + 2 + write-only + + + TFIFOT + Transmitter FIFO trigger level + 4 + 2 + write-only + + + DMAE + DMA enable +0: Disable +1: Enable + 3 + 1 + write-only + + + TFIFORST + Transmitter FIFO reset +Write 1 to clear all bytes in the TXFIFO and resets its +counter. The Transmitter Shift Register is not cleared. +This bit will automatically be cleared. + 2 + 1 + write-only + + + RFIFORST + Receiver FIFO reset +Write 1 to clear all bytes in the RXFIFO and resets its +counter. The Receiver Shift Register is not cleared. +This bit will automatically be cleared. + 1 + 1 + write-only + + + FIFOE + FIFO enable +Write 1 to enable both the transmitter and receiver +FIFOs. +The FIFOs are reset when the value of this bit toggles. + 0 + 1 + write-only + + + + + LCR + Line Control Register + 0x2c + 32 + 0x00000000 + 0x000000FF + + + DLAB + Divisor latch access bit + 7 + 1 + read-write + + + BC + Break control + 6 + 1 + read-write + + + SPS + Stick parity +1: Parity bit is constant 0 or 1, depending on bit4 (EPS). +0: Disable the sticky bit parity. + 5 + 1 + read-write + + + EPS + Even parity select +1: Even parity (an even number of logic-1 is in the data +and parity bits) +0: Old parity. + 4 + 1 + read-write + + + PEN + Parity enable +When this bit is set, a parity bit is generated in +transmitted data before the first STOP bit and the parity +bit would be checked for the received data. + 3 + 1 + read-write + + + STB + Number of STOP bits +0: 1 bits +1: The number of STOP bit is based on the WLS setting +When WLS = 0, STOP bit is 1.5 bits +When WLS = 1, 2, 3, STOP bit is 2 bits + 2 + 1 + read-write + + + WLS + Word length setting +0: 5 bits +1: 6 bits +2: 7 bits +3: 8 bits + 0 + 2 + read-write + + + + + MCR + Modem Control Register ( + 0x30 + 32 + 0x00000000 + 0x00000032 + + + AFE + Auto flow control enable +0: Disable +1: The auto-CTS and auto-RTS setting is based on the +RTS bit setting: +When RTS = 0, auto-CTS only +When RTS = 1, auto-CTS and auto-RTS + 5 + 1 + read-write + + + LOOP + Enable loopback mode +0: Disable +1: Enable + 4 + 1 + read-write + + + RTS + Request to send +This bit controls the modem_rtsn output. +0: The modem_rtsn output signal will be driven HIGH +1: The modem_rtsn output signal will be driven LOW + 1 + 1 + read-write + + + + + LSR + Line Status Register + 0x34 + 32 + 0x00000000 + 0xC01F1FFF + + + RXIDLE + rxidle after timeout, clear after rx idle condition not match + 31 + 1 + read-only + + + TXIDLE + txidle after timeout, clear after tx idle condition not match + 30 + 1 + read-only + + + RFIFO_NUM + data bytes in rxfifo not read + 16 + 5 + read-only + + + TFIFO_NUM + data bytes in txfifo not sent + 8 + 5 + read-only + + + ERRF + Error in RXFIFO +In the FIFO mode, this bit is set when there is at least +one parity error, framing error, or line break +associated with data in the RXFIFO. It is cleared when +this register is read and there is no more error for the +rest of data in the RXFIFO. + 7 + 1 + read-only + + + TEMT + Transmitter empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) and the Transmitter Shift Register (TSR) are +both empty. Otherwise, it is zero. + 6 + 1 + read-only + + + THRE + Transmitter Holding Register empty +This bit is 1 when the THR (TXFIFO in the FIFO +mode) is empty. Otherwise, it is zero. +If the THRE interrupt is enabled, an interrupt is +triggered when THRE becomes 1. + 5 + 1 + read-only + + + LBREAK + Line break +This bit is set when the uart_sin input signal was held +LOWfor longer than the time for a full-word +transmission. A full-word transmission is the +transmission of the START, data, parity, and STOP +bits. It is cleared when this register is read. +In the FIFO mode, this bit indicates the line break for +the received data at the top of the RXFIFO. + 4 + 1 + read-only + + + FE + Framing error +This bit is set when the received STOP bit is not +HIGH. It is cleared when this register is read. +In the FIFO mode, this bit indicates the framing error +for the received data at the top of the RXFIFO. + 3 + 1 + read-only + + + PE + Parity error +This bit is set when the received parity does not match +with the parity selected in the LCR[5:4]. It is cleared +when this register is read. +In the FIFO mode, this bit indicates the parity error +for the received data at the top of the RXFIFO. + 2 + 1 + read-only + + + OE + Overrun error +This bit indicates that data in the Receiver Buffer +Register (RBR) is overrun. + 1 + 1 + read-only + + + DR + Data ready. +This bit is set when there are incoming received data +in the Receiver Buffer Register (RBR). It is cleared +when all of the received data are read. + 0 + 1 + read-only + + + + + MSR + Modem Status Register + 0x38 + 32 + 0x00000000 + 0x00000011 + + + CTS + Clear to send +0: The modem_ctsn input signal is HIGH. +1: The modem_ctsn input signal is LOW. + 4 + 1 + read-only + + + DCTS + Delta clear to send +This bit is set when the state of the modem_ctsn input +signal has been changed since the last time this +register is read. + 0 + 1 + read-only + + + + + GPR + GPR Register + 0x3c + 32 + 0x00000000 + 0x000000FF + + + DATA + An one-byte storage register + 0 + 8 + read-write + + + + + + + UART1 + UART1 + UART + 0xf0044000 + + + UART2 + UART2 + UART + 0xf0048000 + + + UART3 + UART3 + UART + 0xf004c000 + + + UART4 + UART4 + UART + 0xf0050000 + + + UART5 + UART5 + UART + 0xf0054000 + + + UART6 + UART6 + UART + 0xf0058000 + + + UART7 + UART7 + UART + 0xf005c000 + + + PUART + PUART + UART + 0xf4124000 + + + I2C0 + I2C0 + I2C + 0xf0060000 + + 0x4 + 0x30 + registers + + + + Cfg + Configuration Register + 0x10 + 32 + 0x00000001 + 0xFFFFFFFF + + + FIFOSIZE + FIFO Size: +0: 2 bytes +1: 4 bytes +2: 8 bytes +3: 16 bytes + 0 + 2 + read-only + + + + + IntEn + Interrupt Enable Register + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMPL + Set to enable the Completion Interrupt. +Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. +Slave: interrupts when a transaction addressing the controller is completed. + 9 + 1 + read-write + + + BYTERECV + Set to enable the Byte Receive Interrupt. +Interrupts when a byte of data is received +Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. + 8 + 1 + read-write + + + BYTETRANS + Set to enable the Byte Transmit Interrupt. +Interrupts when a byte of data is transmitted. + 7 + 1 + read-write + + + START + Set to enable the START Condition Interrupt. +Interrupts when a START condition/repeated START condition is detected. + 6 + 1 + read-write + + + STOP + Set to enable the STOP Condition Interrupt +Interrupts when a STOP condition is detected. + 5 + 1 + read-write + + + ARBLOSE + Set to enable the Arbitration Lose Interrupt. +Master: interrupts when the controller loses the bus arbitration +Slave: not available in this mode. + 4 + 1 + read-write + + + ADDRHIT + Set to enable the Address Hit Interrupt. +Master: interrupts when the addressed slave returned an ACK. +Slave: interrupts when the controller is addressed. + 3 + 1 + read-write + + + FIFOHALF + Set to enable the FIFO Half Interrupt. +Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. +Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. +This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. + 2 + 1 + read-write + + + FIFOFULL + Set to enable the FIFO Full Interrupt. +Interrupts when the FIFO is full. + 1 + 1 + read-write + + + FIFOEMPTY + Set to enabled the FIFO Empty Interrupt +Interrupts when the FIFO is empty. + 0 + 1 + read-write + + + + + Status + Status Register + 0x18 + 32 + 0x00000001 + 0xFFFFFFFF + + + LINESDA + Indicates the current status of the SDA line on the bus +1: high +0: low + 14 + 1 + read-only + + + LINESCL + Indicates the current status of the SCL line on the bus +1: high +0: low + 13 + 1 + read-only + + + GENCALL + Indicates that the address of the current transaction is a general call address: +1: General call +0: Not general call + 12 + 1 + read-only + + + BUSBUSY + Indicates that the bus is busy +The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus +1: Busy +0: Not busy + 11 + 1 + read-only + + + ACK + Indicates the type of the last received/transmitted acknowledgement bit: +1: ACK +0: NACK + 10 + 1 + read-only + + + CMPL + Transaction Completion +Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration +Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. + 9 + 1 + write-only + + + BYTERECV + Indicates that a byte of data has been received. + 8 + 1 + write-only + + + BYTETRANS + Indicates that a byte of data has been transmitted. + 7 + 1 + write-only + + + START + Indicates that a START Condition or a repeated START condition has been transmitted/received. + 6 + 1 + write-only + + + STOP + Indicates that a STOP Condition has been transmitted/received. + 5 + 1 + write-only + + + ARBLOSE + Indicates that the controller has lost the bus arbitration. + 4 + 1 + write-only + + + ADDRHIT + Master: indicates that a slave has responded to the transaction. +Slave: indicates that a transaction is targeting the controller (including the General Call). + 3 + 1 + write-only + + + FIFOHALF + Transmitter: Indicates that the FIFO is half-empty. + 2 + 1 + read-only + + + FIFOFULL + Indicates that the FIFO is full. + 1 + 1 + read-only + + + FIFOEMPTY + Indicates that the FIFO is empty. + 0 + 1 + read-only + + + + + Addr + Address Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + The slave address. +For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid + 0 + 10 + read-write + + + + + Data + Data Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Write this register to put one byte of data to the FIFO. +Read this register to get one byte of data from the FIFO. + 0 + 8 + read-write + + + + + Ctrl + Control Register + 0x24 + 32 + 0x00905E00 + 0xFFFFFFFF + + + DATACNT_HIGH + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 24 + 8 + read-write + + + RESET_LEN + reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. + 20 + 4 + read-write + + + RESET_HOLD_SCKIN + set to hold input clock to high when reset is active + 14 + 1 + read-write + + + RESET_ON + set to send reset signals(just toggle clock bus defined by reset_len). +this register is clered when reset is end, can't be cleared by software + 13 + 1 + read-write + + + PHASE_START + Enable this bit to send a START condition at the beginning of transaction. +Master mode only. + 12 + 1 + read-write + + + PHASE_ADDR + Enable this bit to send the address after START condition. +Master mode only. + 11 + 1 + read-write + + + PHASE_DATA + Enable this bit to send the data after Address phase. +Master mode only. + 10 + 1 + read-write + + + PHASE_STOP + Enable this bit to send a STOP condition at the end of a transaction. +Master mode only. + 9 + 1 + read-write + + + DIR + Transaction direction +Master: Set this bit to determine the direction for the next transaction. +0: Transmitter +1: Receiver +Slave: The direction of the last received transaction. +0: Receiver +1: Transmitter + 8 + 1 + read-write + + + DATACNT + Data counts in bytes. +Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. +Slave: the meaning of DataCnt depends on the DMA mode: +If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. +If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. + 0 + 8 + read-write + + + + + Cmd + Command Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + Write this register with the following values to perform the corresponding actions: +0x0: no action +0x1: issue a data transaction (Master only) +0x2: respond with an ACK to the received byte +0x3: respond with a NACK to the received byte +0x4: clear the FIFO +0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) +When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. +Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. + 0 + 3 + read-write + + + + + Setup + Setup Register + 0x2c + 32 + 0x05252100 + 0xFFFFFFFF + + + T_SUDAT + T_SUDAT defines the data setup time before releasing the SCL. +Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) +tpclk = PCLK period +TPM = The multiplier value in Timing Parameter Multiplier Register + 24 + 5 + read-write + + + T_SP + T_SP defines the pulse width of spikes that must be suppressed by the input filter. +Pulse width = T_SP * tpclk* (TPM+1) + 21 + 3 + read-write + + + T_HDDAT + T_HDDAT defines the data hold time after SCL goes LOW +Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) + 16 + 5 + read-write + + + T_SCLRADIO + The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. +SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) +1: ratio = 2 +0: ratio = 1 +This field is only valid when the controller is in the master mode. + 13 + 1 + read-write + + + T_SCLHI + The HIGH period of generated SCL clock is defined by T_SCLHi. +SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) +The T_SCLHi value must be greater than T_SP and T_HDDAT values. +This field is only valid when the controller is in the master mode. + 4 + 9 + read-write + + + DMAEN + Enable the direct memory access mode data transfer. +1: Enable +0: Disable + 3 + 1 + read-write + + + MASTER + Configure this device as a master or a slave. +1: Master mode +0: Slave mode + 2 + 1 + read-write + + + ADDRESSING + I2C addressing mode: +1: 10-bit addressing mode +0: 7-bit addressing mode + 1 + 1 + read-write + + + IICEN + Enable the I2C controller. +1: Enable +0: Disable + 0 + 1 + read-write + + + + + TPM + I2C Timing Paramater Multiplier + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + TPM + A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). + 0 + 5 + read-write + + + + + + + I2C1 + I2C1 + I2C + 0xf0064000 + + + I2C2 + I2C2 + I2C + 0xf0068000 + + + I2C3 + I2C3 + I2C + 0xf006c000 + + + SPI0 + SPI0 + SPI + 0xf0070000 + + 0x4 + 0x7c + registers + + + + wr_trans_cnt + Transfer count for write data + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 0 + 32 + read-write + + + + + rd_trans_cnt + Transfer count for read data + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 32 + read-write + + + + + TransFmt + Transfer Format Register + 0x10 + 32 + 0x00020780 + 0xFFFF1F9F + + + ADDRLEN + Address length in bytes +0x0: 1 byte +0x1: 2 bytes +0x2: 3 bytes +0x3: 4 bytes + 16 + 2 + read-write + + + DATALEN + The length of each data unit in bits +The actual bit number of a data unit is (DataLen + 1) + 8 + 5 + read-write + + + DATAMERGE + Enable Data Merge mode, which does automatic data split on write and data coalescing on read. +This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. +When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. + 7 + 1 + read-write + + + MOSIBIDIR + Bi-directional MOSI in regular (single) mode +0x0: MOSI is uni-directional signal in regular mode. +0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two + 4 + 1 + read-write + + + LSB + Transfer data with the least significant bit first +0x0: Most significant bit first +0x1: Least significant bit first + 3 + 1 + read-write + + + SLVMODE + SPI Master/Slave mode selection +0x0: Master mode +0x1: Slave mode + 2 + 1 + read-write + + + CPOL + SPI Clock Polarity +0x0: SCLK is LOW in the idle states +0x1: SCLK is HIGH in the idle states + 1 + 1 + read-write + + + CPHA + SPI Clock Phase +0x0: Sampling data at odd SCLK edges +0x1: Sampling data at even SCLK edges + 0 + 1 + read-write + + + + + DirectIO + Direct IO Control Register + 0x14 + 32 + 0x00003100 + 0x013F3F3F + + + DIRECTIOEN + Enable Direct IO +0x0: Disable +0x1: Enable + 24 + 1 + read-write + + + HOLD_OE + Output enable for the SPI Flash hold signal + 21 + 1 + read-write + + + WP_OE + Output enable for the SPI Flash write protect signal + 20 + 1 + read-write + + + MISO_OE + Output enable fo the SPI MISO signal + 19 + 1 + read-write + + + MOSI_OE + Output enable for the SPI MOSI signal + 18 + 1 + read-write + + + SCLK_OE + Output enable for the SPI SCLK signal + 17 + 1 + read-write + + + CS_OE + Output enable for SPI CS (chip select) signal + 16 + 1 + read-write + + + HOLD_O + Output value for the SPI Flash hold signal + 13 + 1 + read-write + + + WP_O + Output value for the SPI Flash write protect signal + 12 + 1 + read-write + + + MISO_O + Output value for the SPI MISO signal + 11 + 1 + read-write + + + MOSI_O + Output value for the SPI MOSI signal + 10 + 1 + read-write + + + SCLK_O + Output value for the SPI SCLK signal + 9 + 1 + read-write + + + CS_O + Output value for the SPI CS (chip select) signal + 8 + 1 + read-write + + + HOLD_I + Status of the SPI Flash hold signal + 5 + 1 + read-only + + + WP_I + Status of the SPI Flash write protect signal + 4 + 1 + read-only + + + MISO_I + Status of the SPI MISO signal + 3 + 1 + read-only + + + MOSI_I + Status of the SPI MOSI signal + 2 + 1 + read-only + + + SCLK_I + Status of the SPI SCLK signal + 1 + 1 + read-only + + + CS_I + Status of the SPI CS (chip select) signal + 0 + 1 + read-only + + + + + TransCtrl + Transfer Control Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SLVDATAONLY + Data-only mode (slave mode only) +0x0: Disable the data-only mode +0x1: Enable the data-only mode +Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. + 31 + 1 + read-write + + + CMDEN + SPI command phase enable (Master mode only) +0x0: Disable the command phase +0x1: Enable the command phase + 30 + 1 + read-write + + + ADDREN + SPI address phase enable (Master mode only) +0x0: Disable the address phase +0x1: Enable the address phase + 29 + 1 + read-write + + + ADDRFMT + SPI address phase format (Master mode only) +0x0: Address phase is the regular (single) mode +0x1: The format of the address phase is the same as the data phase (DualQuad). + 28 + 1 + read-write + + + TRANSMODE + Transfer mode +The transfer sequence could be +0x0: Write and read at the same time +0x1: Write only +0x2: Read only +0x3: Write, Read +0x4: Read, Write +0x5: Write, Dummy, Read +0x6: Read, Dummy, Write +0x7: None Data (must enable CmdEn or AddrEn in master mode) +0x8: Dummy, Write +0x9: Dummy, Read +0xa~0xf: Reserved + 24 + 4 + read-write + + + DUALQUAD + SPI data phase format +0x0: Regular (Single) mode +0x1: Dual I/O mode +0x2: Quad I/O mode +0x3: Reserved + 22 + 2 + read-write + + + TOKENEN + Token transfer enable (Master mode only) +Append an one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. +0x0: Disable the one-byte special token +0x1: Enable the one-byte special token + 21 + 1 + read-write + + + WRTRANCNT + Transfer count for write data +WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). +WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must be equal to RdTranCnt. + 12 + 9 + read-write + + + TOKENVALUE + Token value (Master mode only) +The value of the one-byte special token following the address phase for SPI read transfers. +0x0: token value = 0x00 +0x1: token value = 0x69 + 11 + 1 + read-write + + + DUMMYCNT + Dummy data count. The actual dummy count is (DummyCnt +1). +The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) +The Data pins are put into the high impedance during the dummy data phase. +DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. + 9 + 2 + read-write + + + RDTRANCNT + Transfer count for read data +RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). +RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. +The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. +For TransMode 0, WrTranCnt must equal RdTranCnt. + 0 + 9 + read-write + + + + + Cmd + Command Register + 0x24 + 32 + 0x00000000 + 0x000000FF + + + CMD + SPI Command + 0 + 8 + read-write + + + + + Addr + Address Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDR + SPI Address +(Master mode only) + 0 + 32 + read-write + + + + + Data + Data Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + Data to transmit or the received data +For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. +The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. +If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. + 0 + 32 + read-write + + + + + Ctrl + Control Register + 0x30 + 32 + 0x00000000 + 0x0FFFFF1F + + + CS_EN + No description avaiable + 24 + 4 + read-write + + + TXTHRES + Transmit (TX) FIFO Threshold +The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. + 16 + 8 + read-write + + + RXTHRES + Receive (RX) FIFO Threshold +The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. + 8 + 8 + read-write + + + TXDMAEN + TX DMA enable + 4 + 1 + read-write + + + RXDMAEN + RX DMA enable + 3 + 1 + read-write + + + TXFIFORST + Transmit FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 2 + 1 + read-write + + + RXFIFORST + Receive FIFO reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 1 + 1 + read-write + + + SPIRST + SPI reset +Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. + 0 + 1 + read-write + + + + + Status + Status Register + 0x34 + 32 + 0x00000000 + 0x33FFFF01 + + + TXNUM_7_6 + Number of valid entries in the Transmit FIFO + 28 + 2 + read-only + + + RXNUM_7_6 + Number of valid entries in the Receive FIFO + 24 + 2 + read-only + + + TXFULL + Transmit FIFO Full flag + 23 + 1 + read-only + + + TXEMPTY + Transmit FIFO Empty flag + 22 + 1 + read-only + + + TXNUM_5_0 + Number of valid entries in the Transmit FIFO + 16 + 6 + read-only + + + RXFULL + Receive FIFO Full flag + 15 + 1 + read-only + + + RXEMPTY + Receive FIFO Empty flag + 14 + 1 + read-only + + + RXNUM_5_0 + Number of valid entries in the Receive FIFO + 8 + 6 + read-only + + + SPIACTIVE + SPI register programming is in progress. +In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. +In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. +Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. +Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. + 0 + 1 + read-only + + + + + IntrEn + Interrupt Enable Register + 0x38 + 32 + 0x00000000 + 0x0000003F + + + SLVCMDEN + Enable the Slave Command Interrupt. +Control whether interrupts are triggered whenever slave commands are received. +(Slave mode only) + 5 + 1 + read-write + + + ENDINTEN + Enable the End of SPI Transfer interrupt. +Control whether interrupts are triggered when SPI transfers end. +(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) + 4 + 1 + read-write + + + TXFIFOINTEN + Enable the SPI Transmit FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. + 3 + 1 + read-write + + + RXFIFOINTEN + Enable the SPI Receive FIFO Threshold interrupt. +Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. + 2 + 1 + read-write + + + TXFIFOURINTEN + Enable the SPI Transmit FIFO Underrun interrupt. +Control whether interrupts are triggered when the Transmit FIFO run out of data. +(Slave mode only) + 1 + 1 + read-write + + + RXFIFOORINTEN + Enable the SPI Receive FIFO Overrun interrupt. +Control whether interrupts are triggered when the Receive FIFO overflows. +(Slave mode only) + 0 + 1 + read-write + + + + + IntrSt + Interrupt Status Register + 0x3c + 32 + 0x00000000 + 0x0000003F + + + SLVCMDINT + Slave Command Interrupt. +This bit is set when Slave Command interrupts occur. +(Slave mode only) + 5 + 1 + write-only + + + ENDINT + End of SPI Transfer interrupt. +This bit is set when End of SPI Transfer interrupts occur. + 4 + 1 + write-only + + + TXFIFOINT + TX FIFO Threshold interrupt. +This bit is set when TX FIFO Threshold interrupts occur. + 3 + 1 + write-only + + + RXFIFOINT + RX FIFO Threshold interrupt. +This bit is set when RX FIFO Threshold interrupts occur. + 2 + 1 + write-only + + + TXFIFOURINT + TX FIFO Underrun interrupt. +This bit is set when TX FIFO Underrun interrupts occur. +(Slave mode only) + 1 + 1 + write-only + + + RXFIFOORINT + RX FIFO Overrun interrupt. +This bit is set when RX FIFO Overrun interrupts occur. +(Slave mode only) + 0 + 1 + write-only + + + + + Timing + Interface Timing Register + 0x40 + 32 + 0x00000000 + 0x00003FFF + + + CS2SCLK + The minimum time between the edges of SPI CS and the edges of SCLK. +SCLK_period * (CS2SCLK + 1) / 2 + 12 + 2 + read-write + + + CSHT + The minimum time that SPI CS should stay HIGH. +SCLK_period * (CSHT + 1) / 2 + 8 + 4 + read-write + + + SCLK_DIV + The clock frequency ratio between the clock source and SPI interface SCLK. +SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) +The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. + 0 + 8 + read-write + + + + + SlvSt + Slave Status Register + 0x60 + 32 + 0x00000000 + 0x0007FFFF + + + UNDERRUN + Data underrun occurs in the last transaction + 18 + 1 + write-only + + + OVERRUN + Data overrun occurs in the last transaction + 17 + 1 + read-write + + + READY + Set this bit to indicate that the ATCSPI200 is ready for data transaction. +When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. + 16 + 1 + read-write + + + USR_STATUS + User defined status flags + 0 + 16 + read-write + + + + + SlvDataCnt + Slave Data Count Register + 0x64 + 32 + 0x00000000 + 0x03FF03FF + + + WCNT + Slave transmitted data count + 16 + 10 + read-only + + + RCNT + Slave received data count + 0 + 10 + read-only + + + + + SlvDataWCnt + WCnt + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + No description avaiable + 0 + 32 + read-only + + + + + SlvDataRCnt + RCnt + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + No description avaiable + 0 + 32 + read-only + + + + + Config + Configuration Register + 0x7c + 32 + 0x00004311 + 0x000043FF + + + SLAVE + Support for SPI Slave mode + 14 + 1 + read-only + + + QUADSPI + Support for Quad I/O SPI + 9 + 1 + read-only + + + DUALSPI + Support for Dual I/O SPI + 8 + 1 + read-only + + + TXFIFOSIZE + Depth of TX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 4 + 4 + read-only + + + RXFIFOSIZE + Depth of RX FIFO +0x0: 2 words +0x1: 4 words +0x2: 8 words +0x3: 16 words +0x4: 32 words +0x5: 64 words +0x6: 128 words + 0 + 4 + read-only + + + + + + + SPI1 + SPI1 + SPI + 0xf0074000 + + + SPI2 + SPI2 + SPI + 0xf0078000 + + + SPI3 + SPI3 + SPI + 0xf007c000 + + + CRC + CRC + CRC + 0xf0080000 + + 0x0 + 0x200 + registers + + + + 8 + 0x40 + 0,1,2,3,4,5,6,7 + CHN[%s] + no description available + 0x0 + + pre_set + &index0 pre set for crc setting + 0x0 + 32 + 0x00000000 + 0x000000FF + + + PRE_SET + 0: no pre set +1: CRC32 +2: CRC32-AUTOSAR +3: CRC16-CCITT +4: CRC16-XMODEM +5: CRC16-MODBUS +1: CRC32 +2: CRC32-autosar +3: CRC16-ccitt +4: CRC16-xmodem +5: CRC16-modbus +6: crc16_dnp +7: crc16_x25 +8: crc16_usb +9: crc16_maxim +10: crc16_ibm +11: crc8_maxim +12: crc8_rohc +13: crc8_itu +14: crc8 +15: crc5_usb + 0 + 8 + read-write + + + + + clr + chn&index0 clear crc result and setting + 0x4 + 32 + 0x00000000 + 0x00000001 + + + CLR + write 1 to clr crc setting and result for its channel. +always read 0. + 0 + 1 + read-write + + + + + poly + chn&index0 poly + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POLY + poly setting + 0 + 32 + read-write + + + + + init_data + chn&index0 init_data + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + INIT_DATA + initial data of CRC + 0 + 32 + read-write + + + + + xorout + chn&index0 xorout + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + XOROUT + XOR for CRC result + 0 + 32 + read-write + + + + + misc_setting + chn&index0 misc_setting + 0x14 + 32 + 0x00000000 + 0x0101013F + + + BYTE_REV + 0: no wrap input byte order +1: wrap input byte order + 24 + 1 + read-write + + + REV_OUT + 0: no wrap output bit order +1: wrap output bit order + 16 + 1 + read-write + + + REV_IN + 0: no wrap input bit order +1: wrap input bit order + 8 + 1 + read-write + + + POLY_WIDTH + crc data length + 0 + 6 + read-write + + + + + data + chn&index0 data + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data for crc + 0 + 32 + read-write + + + + + result + chn&index0 result + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + RESULT + crc result + 0 + 32 + read-write + + + + + + + + TSNS + TSNS + TSNS + 0xf0090000 + + 0x0 + 0x3c + registers + + + + T + Temperature + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Signed number of temperature in 256 x celsius degree + 0 + 32 + read-only + + + + + TMAX + Maximum Temperature + 0x4 + 32 + 0xFF800000 + 0xFFFFFFFF + + + T + maximum temperature ever found + 0 + 32 + read-only + + + + + TMIN + Minimum Temperature + 0x8 + 32 + 0x007FFFFF + 0xFFFFFFFF + + + T + minimum temperature ever found + 0 + 32 + read-only + + + + + AGE + Sample age + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + AGE + age of T register in 24MHz clock cycles + 0 + 32 + read-only + + + + + STATUS + Status + 0x10 + 32 + 0x00000000 + 0x80000001 + + + VALID + indicate value in T is valid or not +0: not valid +1:valid + 31 + 1 + read-only + + + TRIGGER + Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode + 0 + 1 + write-only + + + + + CONFIG + Configuration + 0x14 + 32 + 0x00600300 + 0xC3FF0713 + + + IRQ_EN + Enable interrupt + 31 + 1 + read-write + + + RST_EN + Enable reset + 30 + 1 + read-write + + + COMPARE_MIN_EN + Enable compare for minimum temperature + 25 + 1 + read-write + + + COMPARE_MAX_EN + Enable compare for maximum temperature + 24 + 1 + read-write + + + SPEED + cycles of a progressive step in 24M clock, valide from 24-255, default 96 +24: 24 cycle for a step +25: 25 cycle for a step +26: 26 cycle for a step +... +255: 255 cycle for a step + 16 + 8 + read-write + + + AVERAGE + Average time, default in 3 +0: measure and return +1: twice and average +2: 4 times and average +. . . +7: 128 times and average + 8 + 3 + read-write + + + CONTINUOUS + continuous mode that keep sampling temperature peridically +0: trigger mode +1: continuous mode + 4 + 1 + read-write + + + ASYNC + Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value +0: active mode +1: Async mode + 1 + 1 + read-write + + + ENABLE + Enable temperature +0: disable, temperature sensor is shut down +1: enable. Temperature sensor enabled + 0 + 1 + read-write + + + + + VALIDITY + Sample validity + 0x18 + 32 + 0x016E3600 + 0xFFFFFFFF + + + VALIDITY + time for temperature values to expire in 24M clock cycles + 0 + 32 + read-write + + + + + FLAG + Temperature flag + 0x1c + 32 + 0x00000000 + 0x00330001 + + + RECORD_MIN_CLR + Clear minimum recorder of temerature, write 1 to clear + 21 + 1 + read-write + + + RECORD_MAX_CLR + Clear maximum recorder of temerature, write 1 to clear + 20 + 1 + read-write + + + UNDER_TEMP + Clear under temperature status, write 1 to clear + 17 + 1 + read-write + + + OVER_TEMP + Clear over temperature status, write 1 to clear + 16 + 1 + read-write + + + IRQ + IRQ flag, write 1 to clear + 0 + 1 + read-write + + + + + UPPER_LIM_IRQ + Maximum temperature to interrupt + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_IRQ + Minimum temperature to interrupt + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + UPPER_LIM_RST + Maximum temperature to reset + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Maximum temperature for compare + 0 + 32 + read-write + + + + + LOWER_LIM_RST + Minimum temperature to reset + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + T + Minimum temperature for compare + 0 + 32 + read-write + + + + + ASYNC + Configuration in asynchronous mode + 0x30 + 32 + 0x00000000 + 0x010107FF + + + ASYNC_TYPE + Compare hotter than or colder than in asynchoronous mode +0: hotter than +1: colder than + 24 + 1 + read-write + + + POLARITY + Polarity of internal comparator + 16 + 1 + read-write + + + VALUE + Value of async mode to compare + 0 + 11 + read-write + + + + + ADVAN + Advance configuration + 0x38 + 32 + 0x00000000 + 0x03010003 + + + ASYNC_IRQ + interrupt status of asynchronous mode + 25 + 1 + read-only + + + ACTIVE_IRQ + interrupt status of active mode + 24 + 1 + read-only + + + SAMPLING + temperature sampling is working + 16 + 1 + read-only + + + NEG_ONLY + use negative compare polarity only + 1 + 1 + read-write + + + POS_ONLY + use positive compare polarity only + 0 + 1 + read-write + + + + + + + MBX0A + MBX0A + MBX + 0xf00a0000 + + 0x0 + 0x24 + registers + + + + CR + Command Registers + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXRESET + Reset TX Fifo and word. + 31 + 1 + read-write + + + BARCTL + Bus Acccess Response Control, when bit 15:14= +00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. + 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. +10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. +11: reserved. + 14 + 2 + read-write + + + BEIE + Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. +1, enable the bus access error interrupt. +0, disable the bus access error interrupt. + 8 + 1 + read-write + + + TFMAIE + TX FIFO message available interrupt enable. +1, enable the TX FIFO massage available interrupt. +0, disable the TX FIFO message available interrupt. + 7 + 1 + read-write + + + TFMEIE + TX FIFO message empty interrupt enable. +1, enable the TX FIFO massage empty interrupt. +0, disable the TX FIFO message empty interrupt. + 6 + 1 + read-write + + + RFMAIE + RX FIFO message available interrupt enable. +1, enable the RX FIFO massage available interrupt. +0, disable the RX FIFO message available interrupt. + 5 + 1 + read-write + + + RFMFIE + RX fifo message full interrupt enable. +1, enable the RX fifo message full interrupt. +0, disable the RX fifo message full interrupt. + 4 + 1 + read-write + + + TWMEIE + TX word message empty interrupt enable. +1, enable the TX word massage empty interrupt. +0, disable the TX word message empty interrupt. + 1 + 1 + read-write + + + RWMVIE + RX word message valid interrupt enable. +1, enable the RX word massage valid interrupt. +0, disable the RX word message valid interrupt. + 0 + 1 + read-write + + + + + SR + Status Registers + 0x4 + 32 + 0x000000E2 + 0xFFFF3FFF + + + RFVC + RX FIFO valid message count + 20 + 4 + read-only + + + TFEC + TX FIFO empty message word count + 16 + 4 + read-only + + + ERRRE + bus Error for read when rx word message are still invalid, this bit is W1C bit. +1, read from word message when the word message are still invalid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 13 + 1 + write-only + + + EWTRF + bus Error for write when tx word message are still valid, this bit is W1C bit. +1, write to word message when the word message are still valid will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 12 + 1 + write-only + + + ERRFE + bus Error for read when rx fifo empty, this bit is W1C bit. +1, read from a empty rx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 11 + 1 + write-only + + + EWTFF + bus Error for write when tx fifo full, this bit is W1C bit. +1, write to a fulled tx fifo will cause this error bit set. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 10 + 1 + write-only + + + EAIVA + bus Error for Accessing Invalid Address; this bit is W1C bit. +1, read and write to invalid address in the bus of this block, will set this bit. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 9 + 1 + write-only + + + EW2RO + bus Error for Write to Read Only address; this bit is W1C bit. +1, write to read only address happened in the bus of this block. +0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. + 8 + 1 + write-only + + + TFMA + TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. +1, TXFIFO message buffer has slot available +0, no slot available (fifo full) + 7 + 1 + read-write + + + TFME + TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. +1, no any message data in TXFIFO from other core. +0, there are some data in the 4x32 TX FIFO from other core yet. + 6 + 1 + read-write + + + RFMA + RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, no any data in the 4x32 TXFIFO message buffer. +0, there are some data in the the 4x32 TXFIFO message buffer already. + 5 + 1 + read-only + + + RFMF + RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written 4x32 message in the RXFIFO. +0, no 4x32 RX FIFO message from other core yet. + 4 + 1 + read-only + + + TWME + TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, means this core had write word message to TXREG. +0, means no valid word message in the TXREG yet. + 1 + 1 + read-only + + + RWMV + RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. +1, the other core had written word message in the RXREG. +0, no valid word message yet in the RXREG. + 0 + 1 + read-only + + + + + TXREG + Transmit word message to other core. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXREG + Transmit word message to other core. + 0 + 32 + write-only + + + + + RXREG + Receive word message from other core. + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + RXREG + Receive word message from other core. + 0 + 32 + read-only + + + + + 1 + 0x4 + TXFIFO0 + TXWRD[%s] + no description available + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TXFIFO + TXFIFO for sending message to other core, FIFO size, 4x32 +can write one of the word address to push data to the FIFO; +can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. + 0 + 32 + write-only + + + + + 1 + 0x4 + RXFIFO0 + RXWRD[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + RXFIFO + RXFIFO for receiving message from other core, FIFO size, 4x32 +can read one of the word address to pop data to the FIFO; +can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. + 0 + 32 + read-only + + + + + + + MBX0B + MBX0B + MBX + 0xf00a4000 + + + WDG0 + WDG0 + EWDG + 0xf00b0000 + + 0x0 + 0x28 + registers + + + + CTRL0 + wdog ctrl register 0 +Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits + 0x0 + 32 + 0x00000000 + 0x2FE2F03F + + + CLK_SEL + clock select +0：bus clock +1：ext clock + 29 + 1 + read-write + + + DIV_VALUE + clock divider, the clock divider works as 2 ^ div_value for wdt counter + 25 + 3 + read-write + + + WIN_EN + window mode enable + 24 + 1 + read-write + + + WIN_LOWER + Once window mode is opened, the lower counter value to refresh wdt +00: 4/8 overtime value +01: 5/8 of overtime value +10: 6/8 of overtime value +11: 7/8 of overtime value + 22 + 2 + read-write + + + CFG_LOCK + The register is locked and unlock is needed before re-config registers +Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. +The register update needs to be finished in the required period defined by UPD_OT_TIME register + 21 + 1 + read-write + + + OT_SELF_CLEAR + overtime reset can be self released after 32 function cycles + 17 + 1 + read-write + + + REF_OT_REQ + If refresh event has to be limited into a period after refresh unlocked. +Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter + 15 + 1 + read-write + + + WIN_UPPER + The upper threshold of window value +The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value +If this register value is zero, then no upper level limitation + 12 + 3 + read-write + + + REF_LOCK + WDT refresh has to be unlocked firstly once refresh lock is enable. + 5 + 1 + read-write + + + REF_UNLOCK_MEC + Unlock refresh mechanism +00: the required unlock password is the same with refresh_psd_register +01: the required unlock password is a ring shift left value of refresh_psd_register +10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is +11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 + 3 + 2 + read-write + + + EN_DBG + WTD enable or not in debug mode + 2 + 1 + read-write + + + EN_LP + WDT enable or not in low power mode +2'b00: wdt is halted once in low power mode +2'b01: wdt will work with 1/4 normal clock freq in low power mode +2'b10: wdt will work with 1/2 normal clock freq in low power mode +2'b11: wdt will work with normal clock freq in low power mode + 0 + 2 + read-write + + + + + CTRL1 + wdog ctrl register 1 +Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits + 0x4 + 32 + 0x00000000 + 0x00F300FC + + + REF_FAIL_RST_EN + Refresh violation will trigger an reset. +These event will be taken as a refresh violation: +1) Not refresh in the window once window mode is enabled +2) Not unlock refresh firstly if unlock is required +3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. +4) Not write the required word to refresh wdt. + 23 + 1 + read-write + + + REF_FAIL_INT_EN + Refresh violation will trigger an interrupt + 22 + 1 + read-write + + + UNL_REF_FAIL_RST_EN + Refresh unlock fail will trigger a reset + 21 + 1 + read-write + + + UNL_REF_FAIL_INT_EN + Refresh unlock fail will trigger a interrupt + 20 + 1 + read-write + + + OT_RST_EN + WDT overtime will generate a reset + 17 + 1 + read-write + + + OT_INT_EN + WDT can generate an interrupt warning before timeout + 16 + 1 + read-write + + + CTL_VIO_RST_EN + Ctrl update violation will trigger a reset +The violation event is to try updating the locked register before unlock them + 7 + 1 + read-write + + + CTL_VIO_INT_EN + Ctrl update violation will trigger a interrupt + 6 + 1 + read-write + + + UNL_CTL_FAIL_RST_EN + Unlock register update failure will trigger a reset + 5 + 1 + read-write + + + UNL_CTL_FAIL_INT_EN + Unlock register update failure will trigger a interrupt + 4 + 1 + read-write + + + PARITY_FAIL_RST_EN + Parity error will trigger a reset +A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits + 3 + 1 + read-write + + + PARITY_FAIL_INT_EN + Parity error will trigger a interrupt + 2 + 1 + read-write + + + + + OT_INT_VAL + wdog timeout interrupt counter value + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + OT_INT_VAL + WDT timeout interrupt value + 0 + 16 + read-write + + + + + OT_RST_VAL + wdog timeout reset counter value + 0xc + 32 + 0x00000000 + 0x0000FFFF + + + OT_RST_VAL + WDT timeout reset value + 0 + 16 + read-write + + + + + WDT_REFRESH_REG + wdog refresh register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDT_REFRESH_REG + Write this register by 32'h5A45_524F to refresh wdog +Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose + 0 + 32 + write-only + + + + + WDT_STATUS + wdog status register + 0x14 + 32 + 0x00000000 + 0x0000007F + + + PARITY_ERROR + parity error +Write one to clear the bit + 6 + 1 + read-write + + + OT_RST + Timeout happens, a reset will happen once enable bit set +This bit can be cleared only by refreshing wdt or reset + 5 + 1 + read-only + + + OT_INT + Timeout happens, a interrupt will happen once enable bit set +This bit can be cleared only by refreshing wdt or reset + 4 + 1 + read-only + + + CTL_UNL_FAIL + Unlock ctrl reg update protection fail +Write one to clear the bit + 3 + 1 + read-write + + + CTL_VIO + Violate register update protection mechanism +Write one to clear the bit + 2 + 1 + read-write + + + REF_UNL_FAIL + Refresh unlock fail +Write one to clear the bit + 1 + 1 + read-write + + + REF_VIO + Refresh fail +Write one to clear the bit + 0 + 1 + read-write + + + + + CFG_PROT + ctrl register protection register + 0x18 + 32 + 0x00000000 + 0x000FFFFF + + + UPD_OT_TIME + The period in which register update has to be in after unlock +The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle + 16 + 4 + read-write + + + UPD_PSD + The password of unlocking register update + 0 + 16 + read-write + + + + + REF_PROT + refresh protection register + 0x1c + 32 + 0x00000000 + 0x0000FFFF + + + REF_UNL_PSD + The password to unlock refreshing + 0 + 16 + read-write + + + + + WDT_EN + Wdog enable + 0x20 + 32 + 0x00000000 + 0x00000001 + + + WDOG_EN + Wdog is enabled, the re-written of this register is impacted by enable lock function + 0 + 1 + read-write + + + + + REF_TIME + Refresh period value + 0x24 + 32 + 0x00000000 + 0x0000FFFF + + + REFRESH_PERIOD + The refresh period after refresh unlocked +Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter + 0 + 16 + read-write + + + + + + + WDG1 + WDG1 + EWDG + 0xf00b4000 + + + PWDG + PWDG + EWDG + 0xf4128000 + + + DMAMUX + DMAMUX + DMAMUX + 0xf00c4000 + + 0x0 + 0x80 + registers + + + + 32 + 0x4 + HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,HDMA_MUX8,HDMA_MUX9,HDMA_MUX10,HDMA_MUX11,HDMA_MUX12,HDMA_MUX13,HDMA_MUX14,HDMA_MUX15,HDMA_MUX16,HDMA_MUX17,HDMA_MUX18,HDMA_MUX19,HDMA_MUX20,HDMA_MUX21,HDMA_MUX22,HDMA_MUX23,HDMA_MUX24,HDMA_MUX25,HDMA_MUX26,HDMA_MUX27,HDMA_MUX28,HDMA_MUX29,HDMA_MUX30,HDMA_MUX31 + MUXCFG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x8000007F + + + ENABLE + DMA Mux Channel Enable +Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be +used to disable or reconfigure a DMA channel. +0b - DMA Mux channel is disabled +1b - DMA Mux channel is enabled + 31 + 1 + read-write + + + SOURCE + DMA Channel Source +Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + 0 + 7 + read-write + + + + + + + HDMA + HDMA + DMAV2 + 0xf00c8000 + + 0x4 + 0x43c + registers + + + + IDMisc + ID Misc + 0x4 + 32 + 0x00000000 + 0x0000FF00 + + + DMASTATE + DMA state machine +localparam ST_IDLE = 3'b000; +localparam ST_READ = 3'b001; +localparam ST_READ_ACK = 3'b010; +localparam ST_WRITE = 3'b011; +localparam ST_WRITE_ACK = 3'b100; +localparam ST_LL = 3'b101; +localparam ST_END = 3'b110; +localparam ST_END_WAIT = 3'b111; + 13 + 3 + read-only + + + CURCHAN + current channel in used + 8 + 5 + read-only + + + + + DMACfg + DMAC Configuration Register + 0x10 + 32 + 0x00000000 + 0xC3FFFFFF + + + CHAINXFR + Chain transfer +0x0: Chain transfer is not configured +0x1: Chain transfer is configured + 31 + 1 + read-only + + + REQSYNC + DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, +which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. +0x0: Request synchronization is not configured +0x1: Request synchronization is configured + 30 + 1 + read-only + + + DATAWIDTH + AXI bus data width +0x0: 32 bits +0x1: 64 bits +0x2: 128 bits +0x3: 256 bits + 24 + 2 + read-only + + + ADDRWIDTH + AXI bus address width +0x18: 24 bits +0x19: 25 bits +... +0x40: 64 bits +Others: Invalid + 17 + 7 + read-only + + + CORENUM + DMA core number +0x0: 1 core +0x1: 2 cores + 16 + 1 + read-only + + + BUSNUM + AXI bus interface number +0x0: 1 AXI bus +0x1: 2 AXI busses + 15 + 1 + read-only + + + REQNUM + Request/acknowledge pair number +0x0: 0 pair +0x1: 1 pair +0x2: 2 pairs +... +0x10: 16 pairs + 10 + 5 + read-only + + + FIFODEPTH + FIFO depth +0x4: 4 entries +0x8: 8 entries +0x10: 16 entries +0x20: 32 entries +Others: Invalid + 4 + 6 + read-only + + + CHANNELNUM + Channel number +0x1: 1 channel +0x2: 2 channels +... +0x8: 8 channels +Others: Invalid + 0 + 4 + read-only + + + + + DMACtrl + DMAC Control Register + 0x14 + 32 + 0x00000000 + 0x00000001 + + + RESET + Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. +Note: The software reset may cause the in-completion of AXI transaction. + 0 + 1 + write-only + + + + + ChAbort + Channel Abort Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHABORT + Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. +Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + 0 + 32 + write-only + + + + + INTHALFSTS + Harlf Complete Interrupt Status + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + half transfer done irq status + 0 + 32 + read-write + + + + + INTTCSTS + Trans Complete Interrupt Status Register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. +0x0: Channel n has no terminal count status +0x1: Channel n has terminal count status + 0 + 32 + write-only + + + + + INTABORTSTS + Abort Interrupt Status Register + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. +0x0: Channel n has no abort status +0x1: Channel n has abort status + 0 + 32 + write-only + + + + + INTERRSTS + Error Interrupt Status Register + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + STS + The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: +- Bus error +- Unaligned address +- Unaligned transfer width +- Reserved configuration +0x0: Channel n has no error status +0x1: Channel n has error status + 0 + 32 + write-only + + + + + ChEN + Channel Enable Register + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CHEN + Alias of the Enable field of all ChnCtrl registers + 0 + 32 + read-only + + + + + 32 + 0x20 + ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8,ch9,ch10,ch11,ch12,ch13,ch14,ch15,ch16,ch17,ch18,ch19,ch20,ch21,ch22,ch23,ch24,ch25,ch26,ch27,ch28,ch29,ch30,ch31 + CHCTRL[%s] + no description available + 0x40 + + Ctrl + Channel &index0 Control Register + 0x0 + 32 + 0x00000000 + 0xFFFFF01F + + + INFINITELOOP + set to loop current config infinitely + 31 + 1 + read-write + + + HANDSHAKEOPT + 0: one request to transfer one burst +1: one request to transfer all the data defined in ch_tts + 30 + 1 + read-write + + + PRIORITY + Channel priority level +0x0: Lower priority +0x1: Higher priority + 29 + 1 + read-write + + + BURSTOPT + set to change burst_size definition + 28 + 1 + read-write + + + SRCBURSTSIZE + Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. +The burst transfer byte number is (SrcBurstSize * SrcWidth). +0x0: 1 transfer +0x1: 2 transfers +0x2: 4 transfers +0x3: 8 transfers +0x4: 16 transfers +0x5: 32 transfers +0x6: 64 transfers +0x7: 128 transfers +0x8: 256 transfers +0x9:512 transfers +0xa: 1024 transfers +0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception + 24 + 4 + read-write + + + SRCWIDTH + Source transfer width +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception + 21 + 3 + read-write + + + DSTWIDTH + Destination transfer width. +Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. +For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. +See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. +0x0: Byte transfer +0x1: Half-word transfer +0x2: Word transfer +0x3: Double word transfer +0x4: Quad word transfer +0x5: Eight word transfer +0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception + 18 + 3 + read-write + + + SRCMODE + Source DMA handshake mode +0x0: Normal mode +0x1: Handshake mode +Normal mode is enabled and started by software set Enable bit; +Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block + 17 + 1 + read-write + + + DSTMODE + Destination DMA handshake mode +0x0: Normal mode +0x1: Handshake mode +the difference bewteen Source/Destination handshake mode is: +the dma block will response hardware request after read in Source handshake mode; +the dma block will response hardware request after write in Destination handshake mode; +NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. + 16 + 1 + read-write + + + SRCADDRCTRL + Source address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 14 + 2 + read-write + + + DSTADDRCTRL + Destination address control +0x0: Increment address +0x1: Decrement address +0x2: Fixed address +0x3: Reserved, setting the field with this value triggers the error exception + 12 + 2 + read-write + + + INTHALFCNTMASK + Channel half interrupt mask +0x0: Allow the half interrupt to be triggered +0x1: Disable the half interrupt + 4 + 1 + read-write + + + INTABTMASK + Channel abort interrupt mask +0x0: Allow the abort interrupt to be triggered +0x1: Disable the abort interrupt + 3 + 1 + read-write + + + INTERRMASK + Channel error interrupt mask +0x0: Allow the error interrupt to be triggered +0x1: Disable the error interrupt + 2 + 1 + read-write + + + INTTCMASK + Channel terminal count interrupt mask +0x0: Allow the terminal count interrupt to be triggered +0x1: Disable the terminal count interrupt + 1 + 1 + read-write + + + ENABLE + Channel enable bit +0x0: Disable +0x1: Enable + 0 + 1 + read-write + + + + + TranSize + Channel &index0Transfer Size Register + 0x4 + 32 + 0x00000000 + 0x0FFFFFFF + + + TRANSIZE + Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. +If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + 0 + 28 + read-write + + + + + SrcAddr + Channel &index0 Source Address Low Part Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SRCADDRL + Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. +This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + 0 + 32 + read-write + + + + + ChanReqCtrl + Channel &index0 DMA Request Control Register + 0xc + 32 + 0x00000000 + 0x1F1F0000 + + + SRCREQSEL + Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + 24 + 5 + read-write + + + DSTREQSEL + Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + 16 + 5 + read-write + + + + + DstAddr + Channel &index0 Destination Address Low Part Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + DSTADDRL + Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. +This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + 0 + 32 + read-write + + + + + LLPointer + Channel &index0 Linked List Pointer Low Part Register + 0x18 + 32 + 0x00000000 + 0xFFFFFFF8 + + + LLPOINTERL + Low part of the pointer to the next descriptor. The pointer must be double word aligned. + 3 + 29 + read-write + + + + + + + + GPIOM + GPIOM + GPIOM + 0xf00d8000 + + 0x0 + 0x780 + registers + + + + 15 + 0x80 + gpioa,gpiob,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy + ASSIGN[%s] + no description available + 0x0 + + 32 + 0x4 + PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 + PIN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x80000F03 + + + LOCK + lock fields in this register, lock can only be cleared by soc reset +0: fields can be changed +1: fields locked to current value, not changeable + 31 + 1 + read-write + + + HIDE + pin value visibility to gpios, +bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 +bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + 8 + 4 + read-write + + + SELECT + select which gpio controls chip pin, +0: soc gpio0; +2: cpu0 fastgpio + 0 + 2 + read-write + + + + + + + + MCAN0 + MCAN0 + MCAN + 0xf0280000 + + 0x4 + 0x408 + registers + + + + ENDN + endian register + 0x4 + 32 + 0x87654321 + 0xFFFFFFFF + + + EVT + Endianness Test Value +The endianness test value is 0x87654321. + 0 + 32 + read-only + + + + + DBTP + data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set + 0xc + 32 + 0x00000A33 + 0x009F1FFF + + + TDC + transmitter delay compensation enable +0= Transmitter Delay Compensation disabled +1= Transmitter Delay Compensation enabled + 23 + 1 + read-write + + + DBRP + Data Bit Rate Prescaler +The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. +When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 16 + 5 + read-write + + + DTSEG1 + Data time segment before sample point +Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 8 + 5 + read-write + + + DTSEG2 + Data time segment after sample point +Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 4 + 4 + read-write + + + DSJW + Data (Re)Synchronization Jump Width +Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 0 + 4 + read-write + + + + + TEST + test register + 0x10 + 32 + 0x00000000 + 0x003F3FF0 + + + SVAL + Started Valid +0= Value of TXBNS not valid +1= Value of TXBNS valid + 21 + 1 + read-only + + + TXBNS + Tx Buffer Number Started +Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. + 16 + 5 + read-only + + + PVAL + Prepared Valid +0= Value of TXBNP not valid +1= Value of TXBNP valid + 13 + 1 + read-only + + + TXBNP + Tx Buffer Number Prepared +Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. + 8 + 5 + read-only + + + RX + Receive Pin +Monitors the actual value of pin m_can_rx +0= The CAN bus is dominant (m_can_rx = ‘0’) +1= The CAN bus is recessive (m_can_rx = ‘1’) + 7 + 1 + read-only + + + TX + Control of Transmit Pin +00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time +01 Sample Point can be monitored at pin m_can_tx +10 Dominant (‘0’) level at pin m_can_tx +11 Recessive (‘1’) at pin m_can_tx + 5 + 2 + read-write + + + LBCK + Loop Back Mode +0= Reset value, Loop Back Mode is disabled +1= Loop Back Mode is enabled + 4 + 1 + read-write + + + + + RWD + ram watchdog + 0x14 + 32 + 0x00000000 + 0x0000FFFF + + + WDV + Watchdog Value +Actual Message RAM Watchdog Counter Value. + 8 + 8 + read-only + + + WDC + Watchdog Configuration +Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. + 0 + 8 + read-write + + + + + CCCR + CC control register + 0x18 + 32 + 0x00000001 + 0x0000FFFF + + + NISO + Non ISO Operation +If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD +Specification V1.0. +0= CAN FD frame format according to ISO 11898-1:2015 +1= CAN FD frame format according to Bosch CAN FD Specification V1.0 +Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. + 15 + 1 + read-write + + + TXP + Transmit Pause +If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after +itself has successfully transmitted a frame (see Section 3.5). +0= Transmit pause disabled +1= Transmit pause enabled + 14 + 1 + read-write + + + EFBI + Edge Filtering during Bus Integration +0= Edge filtering disabled +1= Two consecutive dominant tq required to detect an edge for hard synchronization + 13 + 1 + read-write + + + PXHD + Protocol Exception Handling Disable +0= Protocol exception handling enabled +1= Protocol exception handling disabled +Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. + 12 + 1 + read-write + + + WMM + Wide Message Marker +Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. +0= 8-bit Message Marker used +1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO + 11 + 1 + read-write + + + UTSU + Use Timestamping Unit +When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. +0= Internal time stamping +1= External time stamping by TSU +Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. +In this case bit UTSU is fixed to zero by synthesis. + 10 + 1 + read-write + + + BRSE + Bit Rate Switch Enable +0= Bit rate switching for transmissions disabled +1= Bit rate switching for transmissions enabled +Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. + 9 + 1 + read-write + + + FDOE + FD Operation Enable +0= FD operation disabled +1= FD operation enabled + 8 + 1 + read-write + + + TEST + Test Mode Enable +0= Normal operation, register TEST holds reset values +1= Test Mode, write access to register TEST enabled + 7 + 1 + read-write + + + DAR + Disable Automatic Retransmission +0= Automatic retransmission of messages not transmitted successfully enabled +1= Automatic retransmission disabled + 6 + 1 + read-write + + + MON + Bus Monitoring Mode +Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. +0= Bus Monitoring Mode is disabled +1= Bus Monitoring Mode is enabled + 5 + 1 + read-write + + + CSR + Clock Stop Request +0= No clock stop is requested +1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. + 4 + 1 + read-write + + + CSA + Clock Stop Acknowledge +0= No clock stop acknowledged +1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk + 3 + 1 + read-only + + + ASM + Restricted Operation Mode +Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. +0= Normal CAN operation +1= Restricted Operation Mode active + 2 + 1 + read-write + + + CCE + Configuration Change Enable +0= The CPU has no write access to the protected configuration registers +1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) + 1 + 1 + read-write + + + INIT + Initialization +0= Normal Operation +1= Initialization is started + 0 + 1 + read-write + + + + + NBTP + nominal bit timing and prescaler register + 0x1c + 32 + 0x06000A03 + 0xFFFFFF7F + + + NSJW + Nominal (Re)Synchronization Jump Width +Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 25 + 7 + read-write + + + NBRP + Nominal Bit Rate Prescaler +The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is +such that one more than the value programmed here is used. + 16 + 9 + read-write + + + NTSEG1 + Nominal Time segment before sample point +Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 8 + 8 + read-write + + + NTSEG2 + Nominal Time segment after sample point +Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + 0 + 7 + read-write + + + + + TSCC + timestamp counter configuration + 0x20 + 32 + 0x00000000 + 0x000F0003 + + + TCP + Timestamp Counter Prescaler +Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + 16 + 4 + read-write + + + TSS + timestamp Select +00= Timestamp counter value always 0x0000 +01= Timestamp counter value incremented according to TCP +10= External timestamp counter value used +11= Same as “00” + 0 + 2 + read-write + + + + + TSCV + timestamp counter value + 0x24 + 32 + 0x00000000 + 0x0000FFFF + + + TSC + Timestamp Counter +The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. +A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. + 0 + 16 + read-only + + + + + TOCC + timeout counter configuration + 0x28 + 32 + 0xFFFF0000 + 0xFFFF0007 + + + TOP + Timeout Period +Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + 16 + 16 + read-write + + + TOS + Timeout Select +When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. +When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. +00= Continuous operation +01= Timeout controlled by Tx Event FIFO +10= Timeout controlled by Rx FIFO 0 +11= Timeout controlled by Rx FIFO 1 + 1 + 2 + read-write + + + RP + Enable Timeout Counter +0= Timeout Counter disabled +1= Timeout Counter enabled + 0 + 1 + read-write + + + + + TOCV + timeout counter value + 0x2c + 32 + 0x0000FFFF + 0x0000FFFF + + + TOC + Timeout Counter +The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. +When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. +Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. + 0 + 16 + read-only + + + + + ECR + error counter register + 0x40 + 32 + 0x00000000 + 0x00FFFFFF + + + CEL + CAN Error Logging +The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. +The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. +The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. +Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. + 16 + 8 + read-only + + + RP + Receive Error Passive +0= The Receive Error Counter is below the error passive level of 128 +1= The Receive Error Counter has reached the error passive level of 128 + 15 + 1 + read-only + + + REC + Receive Error Counter +Actual state of the Receive Error Counter, values between 0 and 127 + 8 + 7 + read-only + + + TEC + Transmit Error Counter +Actual state of the Transmit Error Counter, values between 0 and 255 +Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. + 0 + 8 + read-only + + + + + PSR + protocol status register + 0x44 + 32 + 0x00000707 + 0x007F7FFF + + + TDCV + Transmitter Delay Compensation Value +Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. +The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + 16 + 7 + read-only + + + PXE + Protocol Exception Event +0= No protocol exception event occurred since last read access +1= Protocol exception event occurred +Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. + 14 + 1 + read-only + + + RFDF + Received a CAN FD Message +This bit is set independent of acceptance filtering. +0= Since this bit was reset by the CPU, no CAN FD message has been received +1= Message in CAN FD format with FDF flag set has been received +Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. + 13 + 1 + read-only + + + RBRS + BRS flag of last received CAN FD Message +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its BRS flag set +1= Last received CAN FD message had its BRS flag set +Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. + 12 + 1 + read-only + + + RESI + ESI flag of last received CAN FD Message +This bit is set together with RFDF, independent of acceptance filtering. +0= Last received CAN FD message did not have its ESI flag set +1= Last received CAN FD message had its ESI flag set +Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. + 11 + 1 + read-only + + + DLEC + Data Phase Last Error Code +Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with +its BRS flag set has been transferred (reception or transmission) without error. +Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. + 8 + 3 + read-only + + + BO + Bus_Off Status +0= The M_CAN is not Bus_Off +1= The M_CAN is in Bus_Off state + 7 + 1 + read-only + + + EW + Warning Status +0= Both error counters are below the Error_Warning limit of 96 +1= At least one of error counter has reached the Error_Warning limit of 96 + 6 + 1 + read-only + + + EP + Error Passive +0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected +1= The M_CAN is in the Error_Passive state + 5 + 1 + read-only + + + ACT + Activity +Monitors the module’s CAN communication state. +00= Synchronizing - node is synchronizing on CAN communication +01= Idle - node is neither receiver nor transmitter +10= Receiver - node is operating as receiver +11= Transmitter - node is operating as transmitter +Note: ACT is set to “00” by a Protocol Exception Event. + 3 + 2 + read-only + + + LEC + Last Error Code +The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. +0= No Error: No error occurred since LEC has been reset by successful reception or transmission. +1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. +2= Form Error: A fixed format part of a received frame has the wrong format. +3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. +4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), +the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus +value was dominant. +5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. + During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at +dominant or continuously disturbed). +6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. +7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. +Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. +Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. + Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. +At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, +enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. +Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. + 0 + 3 + read-only + + + + + TDCR + transmitter delay compensation + 0x48 + 32 + 0x00000000 + 0x00007F7F + + + TDCO + Transmitter Delay Compensation SSP Offset +Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. + 8 + 7 + read-write + + + TDCF + Transmitter Delay Compensation Filter Window Length +Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. +The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. + 0 + 7 + read-write + + + + + IR + interrupt register + 0x50 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARA + Access to Reserved Address +0= No access to reserved address occurred +1= Access to reserved address occurred + 29 + 1 + read-write + + + PED + Protocol Error in Data Phase (Data Bit Time is used) +0= No protocol error in data phase +1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) + 28 + 1 + read-write + + + PEA + Protocol Error in Arbitration Phase (Nominal Bit Time is used) +0= No protocol error in arbitration phase +1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) + 27 + 1 + read-write + + + WDI + Watchdog Interrupt +0= No Message RAM Watchdog event occurred +1= Message RAM Watchdog event due to missing READY + 26 + 1 + read-write + + + BO + Bus_Off Status +0= Bus_Off status unchanged +1= Bus_Off status changed + 25 + 1 + read-write + + + EW + Warning Status +0= Error_Warning status unchanged +1= Error_Warning status changed + 24 + 1 + read-write + + + EP + Error Passive +0= Error_Passive status unchanged +1= Error_Passive status changed + 23 + 1 + read-write + + + ELO + Error Logging Overflow +0= CAN Error Logging Counter did not overflow +1= Overflow of CAN Error Logging Counter occurred + 22 + 1 + read-write + + + BEU + Bit Error Uncorrected +Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. +An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. +0= No bit error detected when reading from Message RAM +1= Bit error detected, uncorrected (e.g. parity logic) + 21 + 1 + read-write + + + BEC + Bit Error Corrected +Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. +0= No bit error detected when reading from Message RAM +1= Bit error detected and corrected (e.g. ECC) + 20 + 1 + read-write + + + DRX + Message stored to Dedicated Rx Buffer +The flag is set whenever a received message has been stored into a dedicated Rx Buffer. +0= No Rx Buffer updated +1= At least one received message stored into an Rx Buffer + 19 + 1 + read-write + + + TOO + Timeout Occurred +0= No timeout +1= Timeout reached + 18 + 1 + read-write + + + MRAF + Message RAM Access Failure +The flag is set, when the Rx Handler +.has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message +storage is aborted and the Rx Handler starts processing of the following message. +.was not able to write a message to the Message RAM. In this case message storage is aborted. +In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. +The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the +M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. +0= No Message RAM access failure occurred +1= Message RAM access failure occurred + 17 + 1 + read-write + + + TSW + Timestamp Wraparound +0= No timestamp counter wrap-around +1= Timestamp counter wrapped around + 16 + 1 + read-write + + + TEFL + Tx Event FIFO Element Lost +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero + 15 + 1 + read-write + + + TEFF + Tx Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + 14 + 1 + read-write + + + TEFW + Tx Event FIFO Watermark Reached +0= Tx Event FIFO fill level below watermark +1= Tx Event FIFO fill level reached watermark + 13 + 1 + read-write + + + TEFN + Tx Event FIFO New Entry +0= Tx Event FIFO unchanged +1= Tx Handler wrote Tx Event FIFO element + 12 + 1 + read-write + + + TFE + Tx FIFO Empty +0= Tx FIFO non-empty +1= Tx FIFO empty + 11 + 1 + read-write + + + TCF + Transmission Cancellation Finished +0= No transmission cancellation finished +1= Transmission cancellation finished + 10 + 1 + read-write + + + TC + Transmission Completed +0= No transmission completed +1= Transmission completed + 9 + 1 + read-write + + + HPM + High Priority Message +0= No high priority message received +1= High priority message received + 8 + 1 + read-write + + + RF1L + Rx FIFO 1 Message Lost +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero + 7 + 1 + read-write + + + RF1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + 6 + 1 + read-write + + + RF1W + Rx FIFO 1 Watermark Reached +0= Rx FIFO 1 fill level below watermark +1= Rx FIFO 1 fill level reached watermark + 5 + 1 + read-write + + + RF1N + Rx FIFO 1 New Message +0= No new message written to Rx FIFO 1 +1= New message written to Rx FIFO 1 + 4 + 1 + read-write + + + RF0L + Rx FIFO 0 Message Lost +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero + 3 + 1 + read-write + + + RF0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + 2 + 1 + read-write + + + RF0W + Rx FIFO 0 Watermark Reached +0= Rx FIFO 0 fill level below watermark +1= Rx FIFO 0 fill level reached watermark + 1 + 1 + read-write + + + RF0N + Rx FIFO 0 New Message +0= No new message written to Rx FIFO 0 +1= New message written to Rx FIFO 0 + 0 + 1 + read-write + + + + + IE + interrupt enable + 0x54 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARAE + Access to Reserved Address Enable + 29 + 1 + read-write + + + PEDE + Protocol Error in Data Phase Enable + 28 + 1 + read-write + + + PEAE + Protocol Error in Arbitration Phase Enable + 27 + 1 + read-write + + + WDIE + Watchdog Interrupt Enable + 26 + 1 + read-write + + + BOE + Bus_Off Status Interrupt Enable + 25 + 1 + read-write + + + EWE + Warning Status Interrupt Enable + 24 + 1 + read-write + + + EPE + Error Passive Interrupt Enable + 23 + 1 + read-write + + + ELOE + Error Logging Overflow Interrupt Enable + 22 + 1 + read-write + + + BEUE + Bit Error Uncorrected Interrupt Enable + 21 + 1 + read-write + + + BECE + Bit Error Corrected Interrupt Enable + 20 + 1 + read-write + + + DRXE + Message stored to Dedicated Rx Buffer Interrupt Enable + 19 + 1 + read-write + + + TOOE + Timeout Occurred Interrupt Enable + 18 + 1 + read-write + + + MRAFE + Message RAM Access Failure Interrupt Enable + 17 + 1 + read-write + + + TSWE + Timestamp Wraparound Interrupt Enable + 16 + 1 + read-write + + + TEFLE + Tx Event FIFO Event Lost Interrupt Enable + 15 + 1 + read-write + + + TEFFE + Tx Event FIFO Full Interrupt Enable + 14 + 1 + read-write + + + TEFWE + Tx Event FIFO Watermark Reached Interrupt Enable + 13 + 1 + read-write + + + TEFNE + Tx Event FIFO New Entry Interrupt Enable + 12 + 1 + read-write + + + TFEE + Tx FIFO Empty Interrupt Enable + 11 + 1 + read-write + + + TCFE + Transmission Cancellation Finished Interrupt Enable + 10 + 1 + read-write + + + TCE + Transmission Completed Interrupt Enable + 9 + 1 + read-write + + + HPME + High Priority Message Interrupt Enable + 8 + 1 + read-write + + + RF1LE + Rx FIFO 1 Message Lost Interrupt Enable + 7 + 1 + read-write + + + RF1FE + Rx FIFO 1 Full Interrupt Enable + 6 + 1 + read-write + + + RF1WE + Rx FIFO 1 Watermark Reached Interrupt Enable + 5 + 1 + read-write + + + RF1NE + Rx FIFO 1 New Message Interrupt Enable + 4 + 1 + read-write + + + RF0LE + Rx FIFO 0 Message Lost Interrupt Enable + 3 + 1 + read-write + + + RF0FE + Rx FIFO 0 Full Interrupt Enable + 2 + 1 + read-write + + + RF0WE + Rx FIFO 0 Watermark Reached Interrupt Enable + 1 + 1 + read-write + + + RF0NE + Rx FIFO 0 New Message Interrupt Enable + 0 + 1 + read-write + + + + + ILS + interrupt line select + 0x58 + 32 + 0x00000000 + 0x3FFFFFFF + + + ARAL + Access to Reserved Address Line + 29 + 1 + read-write + + + PEDL + Protocol Error in Data Phase Line + 28 + 1 + read-write + + + PEAL + Protocol Error in Arbitration Phase Line + 27 + 1 + read-write + + + WDIL + Watchdog Interrupt Line + 26 + 1 + read-write + + + BOL + Bus_Off Status Interrupt Line + 25 + 1 + read-write + + + EWL + Warning Status Interrupt Line + 24 + 1 + read-write + + + EPL + Error Passive Interrupt Line + 23 + 1 + read-write + + + ELOL + Error Logging Overflow Interrupt Line + 22 + 1 + read-write + + + BEUL + Bit Error Uncorrected Interrupt Line + 21 + 1 + read-write + + + BECL + Bit Error Corrected Interrupt Line + 20 + 1 + read-write + + + DRXL + Message stored to Dedicated Rx Buffer Interrupt Line + 19 + 1 + read-write + + + TOOL + Timeout Occurred Interrupt Line + 18 + 1 + read-write + + + MRAFL + Message RAM Access Failure Interrupt Line + 17 + 1 + read-write + + + TSWL + Timestamp Wraparound Interrupt Line + 16 + 1 + read-write + + + TEFLL + Tx Event FIFO Event Lost Interrupt Line + 15 + 1 + read-write + + + TEFFL + Tx Event FIFO Full Interrupt Line + 14 + 1 + read-write + + + TEFWL + Tx Event FIFO Watermark Reached Interrupt Line + 13 + 1 + read-write + + + TEFNL + Tx Event FIFO New Entry Interrupt Line + 12 + 1 + read-write + + + TFEL + Tx FIFO Empty Interrupt Line + 11 + 1 + read-write + + + TCFL + Transmission Cancellation Finished Interrupt Line + 10 + 1 + read-write + + + TCL + Transmission Completed Interrupt Line + 9 + 1 + read-write + + + HPML + High Priority Message Interrupt Line + 8 + 1 + read-write + + + RF1LL + Rx FIFO 1 Message Lost Interrupt Line + 7 + 1 + read-write + + + RF1FL + Rx FIFO 1 Full Interrupt Line + 6 + 1 + read-write + + + RF1WL + Rx FIFO 1 Watermark Reached Interrupt Line + 5 + 1 + read-write + + + RF1NL + Rx FIFO 1 New Message Interrupt Line + 4 + 1 + read-write + + + RF0LL + Rx FIFO 0 Message Lost Interrupt Line + 3 + 1 + read-write + + + RF0FL + Rx FIFO 0 Full Interrupt Line + 2 + 1 + read-write + + + RF0WL + Rx FIFO 0 Watermark Reached Interrupt Line + 1 + 1 + read-write + + + RF0NL + Rx FIFO 0 New Message Interrupt Line + 0 + 1 + read-write + + + + + ILE + interrupt line enable + 0x5c + 32 + 0x00000000 + 0x00000003 + + + EINT1 + Enable Interrupt Line 1 +0= Interrupt line m_can_int1 disabled +1= Interrupt line m_can_int1 enabled + 1 + 1 + read-write + + + EINT0 + Enable Interrupt Line 0 +0= Interrupt line m_can_int0 disabled +1= Interrupt line m_can_int0 enabled + 0 + 1 + read-write + + + + + GFC + global filter configuration + 0x80 + 32 + 0x00000000 + 0x0000003F + + + ANFS + Accept Non-matching Frames Standard +Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + 4 + 2 + read-write + + + ANFE + Accept Non-matching Frames Extended +Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. +00= Accept in Rx FIFO 0 +01= Accept in Rx FIFO 1 +10= Reject +11= Reject + 2 + 2 + read-write + + + RRFS + Reject Remote Frames Standard +0= Filter remote frames with 11-bit standard IDs +1= Reject all remote frames with 11-bit standard IDs + 1 + 1 + read-write + + + RRFE + Reject Remote Frames Extended +0= Filter remote frames with 29-bit extended IDs +1= Reject all remote frames with 29-bit extended IDs + 0 + 1 + read-write + + + + + SIDFC + standard ID filter configuration + 0x84 + 32 + 0x00000000 + 0x00FFFFFC + + + LSS + List Size Standard +0= No standard Message ID filter +1-128= Number of standard Message ID filter elements +>128= Values greater than 128 are interpreted as 128 + 16 + 8 + read-write + + + FLSSA + Filter List Standard Start Address +Start address of standard Message ID filter list (32-bit word address) + 2 + 14 + read-write + + + + + XIDFC + extended ID filter configuration + 0x88 + 32 + 0x00000000 + 0x007FFFFC + + + LSE + List Size Extended +0= No extended Message ID filter +1-64= Number of extended Message ID filter elements +>64= Values greater than 64 are interpreted as 64 + 16 + 7 + read-write + + + FLESA + Filter List Extended Start Address +Start address of extended Message ID filter list (32-bit word address). + 2 + 14 + read-write + + + + + XIDAM + extended id and mask + 0x90 + 32 + 0x1FFFFFFF + 0x1FFFFFFF + + + EIDM + Extended ID Mask +For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. + Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. + 0 + 29 + read-write + + + + + HPMS + high priority message status + 0x94 + 32 + 0x00000000 + 0x0000FFFF + + + FLST + Filter List +Indicates the filter list of the matching filter element. +0= Standard Filter List +1= Extended Filter List + 15 + 1 + read-only + + + FIDX + Filter Index +Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. + 8 + 7 + read-only + + + MSI + Message Storage Indicator +00= No FIFO selected +01= FIFO message lost +10= Message stored in FIFO 0 +11= Message stored in FIFO 1 + 6 + 2 + read-only + + + BIDX + Buffer Index +Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. + 0 + 6 + read-only + + + + + NDAT1 + new data1 + 0x98 + 32 + 0x00000000 + 0xFFFFFFFF + + + ND1 + New Data[31:0] +The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. +The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + 0 + 32 + read-write + + + + + NDAT2 + new data2 + 0x9c + 32 + 0x00000000 + 0xFFFFFFFF + + + ND2 + New Data[63:32] +The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. +The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. +0= Rx Buffer not updated +1= Rx Buffer updated from new message + 0 + 32 + read-write + + + + + RXF0C + rx fifo 0 configuration + 0xa0 + 32 + 0x00000000 + 0xFF7FFFFC + + + F0OM + FIFO 0 Operation Mode +FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 0 blocking mode +1= FIFO 0 overwrite mode + 31 + 1 + read-write + + + F0WM + Rx FIFO 0 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) +>64= Watermark interrupt disabled + 24 + 7 + read-write + + + F0S + Rx FIFO 0 Size +0= No Rx FIFO 0 +1-64= Number of Rx FIFO 0 elements +>64= Values greater than 64 are interpreted as 64 +The Rx FIFO 0 elements are indexed from 0 to F0S-1 + 16 + 7 + read-write + + + F0SA + Rx FIFO 0 Start Address +Start address of Rx FIFO 0 in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + RXF0S + rx fifo 0 status + 0xa4 + 32 + 0x00000000 + 0x033F3F7F + + + RF0L + Rx FIFO 0 Message Lost +This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. +0= No Rx FIFO 0 message lost +1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero +Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. + 25 + 1 + read-only + + + F0F + Rx FIFO 0 Full +0= Rx FIFO 0 not full +1= Rx FIFO 0 full + 24 + 1 + read-only + + + F0PI + Rx FIFO 0 Put Index +Rx FIFO 0 write index pointer, range 0 to 63. + 16 + 6 + read-only + + + F0GI + Rx FIFO 0 Get Index +Rx FIFO 0 read index pointer, range 0 to 63. + 8 + 6 + read-only + + + F0FL + Rx FIFO 0 Fill Level +Number of elements stored in Rx FIFO 0, range 0 to 64. + 0 + 7 + read-only + + + + + RXF0A + rx fifo0 acknowledge + 0xa8 + 32 + 0x00000000 + 0x0000003F + + + F0AI + Rx FIFO 0 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. +This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + 0 + 6 + read-write + + + + + RXBC + rx buffer configuration + 0xac + 32 + 0x00000000 + 0x0000FFFC + + + RBSA + Rx Buffer Start Address +Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. + 2 + 14 + read-write + + + + + RXF1C + rx fifo1 configuration + 0xb0 + 32 + 0x00000000 + 0xFF7FFFFC + + + F1OM + FIFO 1 Operation Mode +FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). +0= FIFO 1 blocking mode +1= FIFO 1 overwrite mode + 31 + 1 + read-write + + + F1WM + Rx FIFO 1 Watermark +0= Watermark interrupt disabled +1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) +>64= Watermark interrupt disabled + 24 + 7 + read-write + + + F1S + Rx FIFO 1 Size +0= No Rx FIFO 1 +1-64= Number of Rx FIFO 1 elements +>64= Values greater than 64 are interpreted as 64 +The Rx FIFO 1 elements are indexed from 0 to F1S - 1 + 16 + 7 + read-write + + + F1SA + Rx FIFO 1 Start Address +Start address of Rx FIFO 1 in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + RXF1S + rx fifo1 status + 0xb4 + 32 + 0x00000000 + 0xC33F3F7F + + + DMS + Debug Message Status +00= Idle state, wait for reception of debug messages, DMA request is cleared +01= Debug message A received +10= Debug messages A, B received +11= Debug messages A, B, C received, DMA request is set + 30 + 2 + read-only + + + RF1L + Rx FIFO 1 Message Lost +This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. +0= No Rx FIFO 1 message lost +1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero +Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. + 25 + 1 + read-only + + + F1F + Rx FIFO 1 Full +0= Rx FIFO 1 not full +1= Rx FIFO 1 full + 24 + 1 + read-only + + + F1PI + Rx FIFO 1 Put Index +Rx FIFO 1 write index pointer, range 0 to 63. + 16 + 6 + read-only + + + F1GI + Rx FIFO 1 Get Index +Rx FIFO 1 read index pointer, range 0 to 63. + 8 + 6 + read-only + + + F1FL + Rx FIFO 1 Fill Level +Number of elements stored in Rx FIFO 1, range 0 to 64. + 0 + 7 + read-only + + + + + RXF1A + rx fifo 1 acknowledge + 0xb8 + 32 + 0x00000000 + 0x0000003F + + + F1AI + Rx FIFO 1 Acknowledge Index +After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. +This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + 0 + 6 + read-write + + + + + RXESC + rx buffer/fifo element size configuration + 0xbc + 32 + 0x00000000 + 0x00000777 + + + RBDS + Rx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + 8 + 3 + read-write + + + F1DS + Rx FIFO 1 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field + 4 + 3 + read-write + + + F0DS + Rx FIFO 0 Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field +Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, +only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. + 0 + 3 + read-write + + + + + TXBC + tx buffer configuration + 0xc0 + 32 + 0x00000000 + 0x7F3FFFFC + + + TFQM + Tx FIFO/Queue Mode +0= Tx FIFO operation +1= Tx Queue operation + 30 + 1 + read-write + + + TFQS + Transmit FIFO/Queue Size +0= No Tx FIFO/Queue +1-32= Number of Tx Buffers used for Tx FIFO/Queue +>32= Values greater than 32 are interpreted as 32 + 24 + 6 + read-write + + + NDTB + Number of Dedicated Transmit Buffers +0= No Dedicated Tx Buffers +1-32= Number of Dedicated Tx Buffers +>32= Values greater than 32 are interpreted as 32 + 16 + 6 + read-write + + + TBSA + Tx Buffers Start Address +Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). +Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. + 2 + 14 + read-write + + + + + TXFQS + tx fifo/queue status + 0xc4 + 32 + 0x00000000 + 0x003F1F3F + + + TFQF + Tx FIFO/Queue Full +0= Tx FIFO/Queue not full +1= Tx FIFO/Queue full + 21 + 1 + read-only + + + TFQPI + Tx FIFO/Queue Put Index +Tx FIFO/Queue write index pointer, range 0 to 31. + 16 + 5 + read-only + + + TFGI + Tx FIFO Get Index +Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured +(TXBC.TFQM = ‘1’). + 8 + 5 + read-only + + + TFFL + Tx FIFO Free Level +Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) +Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with +the first dedicated Tx Buffers. +Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. + 0 + 6 + read-only + + + + + TXESC + tx buffer element size configuration + 0xc8 + 32 + 0x00000000 + 0x00000007 + + + TBDS + Tx Buffer Data Field Size +000= 8 byte data field +001= 12 byte data field +010= 16 byte data field +011= 20 byte data field +100= 24 byte data field +101= 32 byte data field +110= 48 byte data field +111= 64 byte data field +Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). + 0 + 3 + read-write + + + + + TXBRP + tx buffer request pending + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + TRP + Transmission Request Pending +Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register +TXBCR. +TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the +highest priority (Tx Buffer with lowest Message ID). +A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, +this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. +After a cancellation has been requested, a finished cancellation is signalled via TXBCF +? after successful transmission together with the corresponding TXBTO bit +? when the transmission has not yet been started at the point of cancellation +? when the transmission has been aborted due to lost arbitration +? when an error occurred during frame transmission +In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. +0= No transmission request pending +1= Transmission request pending +Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. + 0 + 32 + read-only + + + + + TXBAR + tx buffer add request + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + AR + Add Request +Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx +Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. +When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. +0= No transmission request added +1= Transmission requested added +Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. + 0 + 32 + read-write + + + + + TXBCR + tx buffer cancellation request + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CR + Cancellation Request +Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. +This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. +0= No cancellation pending +1= Cancellation pending + 0 + 32 + read-write + + + + + TXBTO + tx buffer transmission occurred + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TO + Transmission Occurred +Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. +0= No transmission occurred +1= Transmission occurred + 0 + 32 + read-only + + + + + TXBCF + tx buffer cancellation finished + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + CF + Cancellation Finished +Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. +In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. +0= No transmit buffer cancellation +1= Transmit buffer cancellation finished + 0 + 32 + read-only + + + + + TXBTIE + tx buffer transmission interrupt enable + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIE + Transmission Interrupt Enable +Each Tx Buffer has its own Transmission Interrupt Enable bit. +0= Transmission interrupt disabled +1= Transmission interrupt enable + 0 + 32 + read-write + + + + + TXBCIE + tx buffer cancellation finished interrupt enable + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CFIE + Cancellation Finished Interrupt Enable +Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. +0= Cancellation finished interrupt disabled +1= Cancellation finished interrupt enabled + 0 + 32 + read-write + + + + + TXEFC + tx event fifo configuration + 0xf0 + 32 + 0x00000000 + 0x3F3FFFFC + + + EFWM + Event FIFO Watermark +0= Watermark interrupt disabled +1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) +>32= Watermark interrupt disabled + 24 + 6 + read-write + + + EFS + Event FIFO Size +0= Tx Event FIFO disabled +1-32= Number of Tx Event FIFO elements +>32= Values greater than 32 are interpreted as 32 +The Tx Event FIFO elements are indexed from 0 to EFS - 1 + 16 + 6 + read-write + + + EFSA + Event FIFO Start Address +Start address of Tx Event FIFO in Message RAM (32-bit word address) + 2 + 14 + read-write + + + + + TXEFS + tx event fifo status + 0xf4 + 32 + 0x00000000 + 0x031F1F3F + + + TEFL + Tx Event FIFO Element Lost +This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. +0= No Tx Event FIFO element lost +1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + 25 + 1 + read-only + + + EFF + Event FIFO Full +0= Tx Event FIFO not full +1= Tx Event FIFO full + 24 + 1 + read-only + + + EFPI + Event FIFO Put Index +Tx Event FIFO write index pointer, range 0 to 31. + 16 + 5 + read-only + + + EFGI + Event FIFO Get Index +Tx Event FIFO read index pointer, range 0 to 31. + 8 + 5 + read-only + + + EFFL + Event FIFO Fill Level +Number of elements stored in Tx Event FIFO, range 0 to 32. + 0 + 6 + read-only + + + + + TXEFA + tx event fifo acknowledge + 0xf8 + 32 + 0x00000000 + 0x0000001F + + + EFAI + Event FIFO Acknowledge Index +After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get +Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. + 0 + 5 + read-write + + + + + 16 + 0x4 + TS_SEL0,TS_SEL1,TS_SEL2,TS_SEL3,TS_SEL4,TS_SEL5,TS_SEL6,TS_SEL7,TS_SEL8,TS_SEL9,TS_SEL10,TS_SEL11,TS_SEL12,TS_SEL13,TS_SEL14,TS_SEL15 + TS_SEL[%s] + no description available + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + TS + Timestamp Word TS +default can save 16 timestamps with 32bit; +if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. + 0 + 32 + read-only + + + + + CREL + core release register + 0x240 + 32 + 0x00000000 + 0xFFFFFFFF + + + REL + Core Release +One digit, BCD-coded + 28 + 4 + read-only + + + STEP + Step of Core Release +One digit, BCD-coded. + 24 + 4 + read-only + + + SUBSTEP + Sub-step of Core Release +One digit, BCD-coded + 20 + 4 + read-only + + + YEAR + Timestamp Year +One digit, BCD-coded. This field is set by generic parameter on +synthesis. + 16 + 4 + read-only + + + MON + Timestamp Month +Two digits, BCD-coded. This field is set by generic parameter +on synthesis. + 8 + 8 + read-only + + + DAY + Timestamp Day +Two digits, BCD-coded. This field is set by generic parameter +on synthesis. + 0 + 8 + read-only + + + + + TSCFG + timestamp configuration + 0x244 + 32 + 0x00000000 + 0x0000FF0F + + + TBPRE + Timebase Prescaler +0x00 to 0xFF +The value by which the oscillator frequency is divided for +generating the timebase counter clock. Valid values for the +Timebase Prescaler are 0 to 255. The actual interpretation by +the hardware of this value is such that one more than the value +programmed here is used. Affects only the TSU internal +timebase. When the internal timebase is excluded by synthesis, +TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not +used. + 8 + 8 + read-write + + + EN64 + set to use 64bit timestamp. +when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. +TSP can be used to select different one + 3 + 1 + read-write + + + SCP + Select Capturing Position +0: Capture Timestamp at EOF +1: Capture Timestamp at SOF + 2 + 1 + read-write + + + TBCS + Timebase Counter Select +When the internal timebase is excluded by synthesis, TBCS is +fixed to ‘1’. +0: Timestamp value captured from internal timebase counter, + ATB.TB[31:0] is the internal timbase counter +1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] + 1 + 1 + read-write + + + TSUE + Timestamp Unit Enable +0: TSU disabled +1: TSU enabled + 0 + 1 + read-write + + + + + TSS1 + timestamp status1 + 0x248 + 32 + 0x00000000 + 0xFFFFFFFF + + + TSL + Timestamp Lost +Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. +Reading a Timestamp register resets the related bit. + 16 + 16 + read-only + + + TSN + Timestamp New +Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related +Timestamp register. Reading a Timestamp register resets the related bit. + 0 + 16 + read-only + + + + + TSS2 + timestamp status2 + 0x24c + 32 + 0x00000000 + 0x0000000F + + + TSP + Timestamp Pointer +The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 +depending on number_ts_g), it is incremented to 0. +Value also signalled on output m_can_tsp[3:0]. + 0 + 4 + read-only + + + + + ATB + actual timebase + 0x250 + 32 + 0x00000000 + 0xFFFFFFFF + + + TB + timebase for timestamp generation 31-0 + 0 + 32 + read-only + + + + + ATBH + actual timebase high + 0x254 + 32 + 0x00000000 + 0xFFFFFFFF + + + TBH + timebase for timestamp generation 63-32 + 0 + 32 + read-only + + + + + GLB_CTL + global control + 0x400 + 32 + 0x00000000 + 0xE0000003 + + + M_CAN_STBY + m_can standby control + 31 + 1 + read-write + + + STBY_CLR_EN + m_can standby clear control +0:controlled by software by standby bit[bit31] +1:auto clear standby by hardware when rx data is 0 + 30 + 1 + read-write + + + STBY_POL + standby polarity selection + 29 + 1 + read-write + + + TSU_TBIN_SEL + external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 + 0 + 2 + read-write + + + + + GLB_STATUS + global status + 0x404 + 32 + 0x00000000 + 0x0000000C + + + M_CAN_INT1 + m_can interrupt status1 + 3 + 1 + read-only + + + M_CAN_INT0 + m_can interrupt status0 + 2 + 1 + read-only + + + + + + + MCAN1 + MCAN1 + MCAN + 0xf0284000 + + + MCAN2 + MCAN2 + MCAN + 0xf0288000 + + + MCAN3 + MCAN3 + MCAN + 0xf028c000 + + + PTPC + PTPC + PTPC + 0xf02fc000 + + 0x0 + 0x3004 + registers + + + + 2 + 0x1000 + 0,1 + PTPC[%s] + no description available + 0x0 + + Ctrl0 + Control Register 0 + 0x0 + 32 + 0x00000000 + 0x000003FF + + + SUBSEC_DIGITAL_ROLLOVER + Format for ns counter rollover, +1-digital, overflow time 1000000000/0x3B9ACA00 +0-binary, overflow time 0x7FFFFFFF + 9 + 1 + read-write + + + CAPT_SNAP_KEEP + set will keep capture snap till software read capt_snapl. +If this bit is set, software should read capt_snaph first to avoid wrong result. +If this bit is cleared, capture result will be updated at each capture event + 8 + 1 + read-write + + + CAPT_SNAP_POS_EN + set will use posege of input capture signal to latch timestamp value + 7 + 1 + read-write + + + CAPT_SNAP_NEG_EN + No description avaiable + 6 + 1 + read-write + + + COMP_EN + set to enable compare, will be cleared by HW when compare event triggered + 4 + 1 + read-write + + + UPDATE_TIMER + update timer with +/- ts_updt, pulse, clear after set + 3 + 1 + write-only + + + INIT_TIMER + initial timer with ts_updt, pulse, clear after set + 2 + 1 + write-only + + + FINE_COARSE_SEL + 0: coarse update, ns counter add ss_incr[7:0] each clk +1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow + 1 + 1 + read-write + + + TIMER_ENABLE + No description avaiable + 0 + 1 + read-write + + + + + ctrl1 + Control Register 1 + 0x4 + 32 + 0x00000000 + 0x000000FF + + + SS_INCR + constant value used to add ns counter; +such as for 50MHz timer clock, set it to 8'd20 + 0 + 8 + read-write + + + + + timeh + timestamp high + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_HIGH + No description avaiable + 0 + 32 + read-only + + + + + timel + timestamp low + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIMESTAMP_LOW + No description avaiable + 0 + 32 + read-only + + + + + ts_updth + timestamp update high + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + SEC_UPDATE + together with ts_updtl, used to initial or update timestamp + 0 + 32 + read-write + + + + + ts_updtl + timestamp update low + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADD_SUB + 1 for sub; 0 for add, used only at update + 31 + 1 + read-write + + + NS_UPDATE + No description avaiable + 0 + 31 + read-write + + + + + addend + No description avaiable + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADDEND + used in fine update mode only + 0 + 32 + read-write + + + + + tarh + No description avaiable + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_HIGH + used for generate compare signal if enabled + 0 + 32 + read-write + + + + + tarl + No description avaiable + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + TARGET_TIME_LOW + No description avaiable + 0 + 32 + read-write + + + + + pps_ctrl + No description avaiable + 0x2c + 32 + 0x00000000 + 0x0000000F + + + PPS_CTRL + No description avaiable + 0 + 4 + read-write + + + + + capt_snaph + No description avaiable + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_HIGH + take snapshot for input capture signal, at pos or neg or both; +the result can be kept or updated at each event according to cfg0.bit8 + 0 + 32 + read-only + + + + + capt_snapl + No description avaiable + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPT_SNAP_LOW + No description avaiable + 0 + 32 + read-write + + + + + + time_sel + No description avaiable + 0x2000 + 32 + 0x00000000 + 0x0000000F + + + CAN3_TIME_SEL + No description avaiable + 3 + 1 + read-write + + + CAN2_TIME_SEL + No description avaiable + 2 + 1 + read-write + + + CAN1_TIME_SEL + No description avaiable + 1 + 1 + read-write + + + CAN0_TIME_SEL + set to use ptpc1 for canx +clr to use ptpc0 for canx + 0 + 1 + read-write + + + + + int_sts + No description avaiable + 0x2004 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description avaiable + 18 + 1 + write-only + + + CAPTURE_INT_STS1 + No description avaiable + 17 + 1 + write-only + + + PPS_INT_STS1 + No description avaiable + 16 + 1 + write-only + + + COMP_INT_STS0 + No description avaiable + 2 + 1 + write-only + + + CAPTURE_INT_STS0 + No description avaiable + 1 + 1 + write-only + + + PPS_INT_STS0 + No description avaiable + 0 + 1 + write-only + + + + + int_en + No description avaiable + 0x2008 + 32 + 0x00000000 + 0x00070007 + + + COMP_INT_STS1 + No description avaiable + 18 + 1 + read-write + + + CAPTURE_INT_STS1 + No description avaiable + 17 + 1 + read-write + + + PPS_INT_STS1 + No description avaiable + 16 + 1 + read-write + + + COMP_INT_STS0 + No description avaiable + 2 + 1 + read-write + + + CAPTURE_INT_STS0 + No description avaiable + 1 + 1 + read-write + + + PPS_INT_STS0 + No description avaiable + 0 + 1 + read-write + + + + + ptpc_can_ts_sel + No description avaiable + 0x3000 + 32 + 0x00000000 + 0xFFFFFF00 + + + TSU_TBIN3_SEL + No description avaiable + 26 + 6 + read-write + + + TSU_TBIN2_SEL + No description avaiable + 20 + 6 + read-write + + + TSU_TBIN1_SEL + No description avaiable + 14 + 6 + read-write + + + TSU_TBIN0_SEL + No description avaiable + 8 + 6 + read-write + + + + + + + QEI0 + QEI0 + QEIV2 + 0xf0300000 + + 0x0 + 0x298 + registers + + + + cr + Control register + 0x0 + 32 + 0x00000000 + 0x807FFF7F + + + READ + 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + 31 + 1 + write-only + + + ZCNTCFG + 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 +0- zcnt will increment or decrement when Z input assert + 22 + 1 + read-write + + + PHCALIZ + 1- phcnt will set to phidx when Z input assert(for abz digital signsl) + 21 + 1 + read-write + + + Z_ONLY_EN + 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz) + 20 + 1 + read-write + + + H2FDIR0 + No description avaiable + 19 + 1 + read-write + + + H2FDIR1 + No description avaiable + 18 + 1 + read-write + + + H2RDIR0 + No description avaiable + 17 + 1 + read-write + + + H2RDIR1 + No description avaiable + 16 + 1 + read-write + + + PAUSEPOS + 1- pause position output valid when PAUSE assert + 15 + 1 + read-write + + + PAUSESPD + 1- pause spdcnt when PAUSE assert + 14 + 1 + read-write + + + PAUSEPH + 1- pause phcnt when PAUSE assert + 13 + 1 + read-write + + + PAUSEZ + 1- pause zcnt when PAUSE assert + 12 + 1 + read-write + + + HFDIR0 + 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) + 11 + 1 + read-write + + + HFDIR1 + 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) + 10 + 1 + read-write + + + HRDIR0 + 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) + 9 + 1 + read-write + + + HRDIR1 + 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) + 8 + 1 + read-write + + + FAULTPOS + No description avaiable + 6 + 1 + read-write + + + SNAPEN + 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert + 5 + 1 + read-write + + + RSTCNT + 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx + 4 + 1 + read-write + + + RD_SEL + define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, width_snap0,width_snap1, timer_snap0, timer_snap1) +0 : same as hpm1000/500/500s; +1: use width for position; use timer for angle + 3 + 1 + read-write + + + ENCTYP + 000-abz; 001-pd; 010-ud; 011-UVW(hal) +100-single A; 101-single sin; 110: sin&cos + 0 + 3 + read-write + + + + + phcfg + Phase configure register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + PHMAX + maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + 0 + 32 + read-write + + + + + wdgcfg + Watchdog configure register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + WDGEN + 1- enable wdog counter + 31 + 1 + read-write + + + WDOG_CFG + define as stop if phase_cnt change is less than it +if 0, then each change of phase_cnt will clear wdog counter; +if 2, then phase_cnt change larger than 2 will clear wdog counter + 28 + 3 + read-write + + + WDGTO + watch dog timeout value + 0 + 28 + read-write + + + + + phidx + Phase index register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + PHIDX + phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 + 0 + 32 + read-write + + + + + trgoen + Tigger output enable register + 0x10 + 32 + 0x00000000 + 0xFFFC0000 + + + WDGFEN + 1- enable trigger output when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- enable trigger output when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- enable trigger output when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- enable trigger output when zphf flag set + 28 + 1 + read-write + + + ZMISSFEN + No description avaiable + 27 + 1 + read-write + + + WIDTHTMFEN + No description avaiable + 26 + 1 + read-write + + + POS2CMPFEN + No description avaiable + 25 + 1 + read-write + + + DIRCHGFEN + No description avaiable + 24 + 1 + read-write + + + CYCLE0FEN + No description avaiable + 23 + 1 + read-write + + + CYCLE1FEN + No description avaiable + 22 + 1 + read-write + + + PULSE0FEN + No description avaiable + 21 + 1 + read-write + + + PULSE1FEN + No description avaiable + 20 + 1 + read-write + + + HOME2FEN + No description avaiable + 19 + 1 + read-write + + + FAULTFEN + No description avaiable + 18 + 1 + read-write + + + + + readen + Read event enable register + 0x14 + 32 + 0x00000000 + 0xFFFC0000 + + + WDGFEN + 1- load counters to their read registers when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- load counters to their read registers when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- load counters to their read registers when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- load counters to their read registers when zphf flag set + 28 + 1 + read-write + + + ZMISSFEN + No description avaiable + 27 + 1 + read-write + + + WIDTHTMFEN + No description avaiable + 26 + 1 + read-write + + + POS2CMPFEN + No description avaiable + 25 + 1 + read-write + + + DIRCHGFEN + No description avaiable + 24 + 1 + read-write + + + CYCLE0FEN + No description avaiable + 23 + 1 + read-write + + + CYCLE1FEN + No description avaiable + 22 + 1 + read-write + + + PULSE0FEN + No description avaiable + 21 + 1 + read-write + + + PULSE1FEN + No description avaiable + 20 + 1 + read-write + + + HOME2FEN + No description avaiable + 19 + 1 + read-write + + + FAULTFEN + No description avaiable + 18 + 1 + read-write + + + + + zcmp + Z comparator + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCMP + zcnt postion compare value + 0 + 32 + read-write + + + + + phcmp + Phase comparator + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + PHCMP + phcnt position compare value + 0 + 32 + read-write + + + + + spdcmp + Speed comparator + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDCMP + spdcnt position compare value + 0 + 32 + read-write + + + + + dmaen + DMA request enable register + 0x24 + 32 + 0x00000000 + 0xFFFC0000 + + + WDGFEN + 1- generate dma request when wdg flag set + 31 + 1 + read-write + + + HOMEFEN + 1- generate dma request when homef flag set + 30 + 1 + read-write + + + POSCMPFEN + 1- generate dma request when poscmpf flag set + 29 + 1 + read-write + + + ZPHFEN + 1- generate dma request when zphf flag set + 28 + 1 + read-write + + + ZMISSFEN + No description avaiable + 27 + 1 + read-write + + + WIDTHTMFEN + No description avaiable + 26 + 1 + read-write + + + POS2CMPFEN + No description avaiable + 25 + 1 + read-write + + + DIRCHGFEN + No description avaiable + 24 + 1 + read-write + + + CYCLE0FEN + No description avaiable + 23 + 1 + read-write + + + CYCLE1FEN + No description avaiable + 22 + 1 + read-write + + + PULSE0FEN + No description avaiable + 21 + 1 + read-write + + + PULSE1FEN + No description avaiable + 20 + 1 + read-write + + + HOME2FEN + No description avaiable + 19 + 1 + read-write + + + FAULTFEN + No description avaiable + 18 + 1 + read-write + + + + + sr + Status register + 0x28 + 32 + 0x00000000 + 0xFFFC0000 + + + WDGF + watchdog flag + 31 + 1 + read-write + + + HOMEF + home flag + 30 + 1 + read-write + + + POSCMPF + postion compare match flag + 29 + 1 + read-write + + + ZPHF + z input flag + 28 + 1 + read-write + + + ZMISSF + No description avaiable + 27 + 1 + read-write + + + WIDTHTMF + No description avaiable + 26 + 1 + read-write + + + POS2CMPF + No description avaiable + 25 + 1 + read-write + + + DIRCHGF + No description avaiable + 24 + 1 + read-write + + + CYCLE0F + No description avaiable + 23 + 1 + read-write + + + CYCLE1F + No description avaiable + 22 + 1 + read-write + + + PULSE0F + No description avaiable + 21 + 1 + read-write + + + PULSE1F + No description avaiable + 20 + 1 + read-write + + + HOME2F + No description avaiable + 19 + 1 + read-write + + + FAULTF + No description avaiable + 18 + 1 + read-write + + + + + irqen + Interrupt request register + 0x2c + 32 + 0x00000000 + 0xFFFC0000 + + + WDGIE + 1- generate interrupt when wdg flag set + 31 + 1 + read-write + + + HOMEIE + 1- generate interrupt when homef flag set + 30 + 1 + read-write + + + POSCMPIE + 1- generate interrupt when poscmpf flag set + 29 + 1 + read-write + + + ZPHIE + 1- generate interrupt when zphf flag set + 28 + 1 + read-write + + + ZMISSE + No description avaiable + 27 + 1 + read-write + + + WIDTHTME + No description avaiable + 26 + 1 + read-write + + + POS2CMPE + No description avaiable + 25 + 1 + read-write + + + DIRCHGE + No description avaiable + 24 + 1 + read-write + + + CYCLE0E + No description avaiable + 23 + 1 + read-write + + + CYCLE1E + No description avaiable + 22 + 1 + read-write + + + PULSE0E + No description avaiable + 21 + 1 + read-write + + + PULSE1E + No description avaiable + 20 + 1 + read-write + + + HOME2E + No description avaiable + 19 + 1 + read-write + + + FAULTE + No description avaiable + 18 + 1 + read-write + + + + + 4 + 0x10 + current,read,snap0,snap1 + COUNT[%s] + no description available + 0x30 + + z + Z counter + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCNT + zcnt value + 0 + 32 + read-write + + + + + ph + Phase counter + 0x4 + 32 + 0x00000000 + 0x461FFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 30 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 26 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 25 + 1 + read-only + + + PHCNT + phcnt value + 0 + 21 + read-only + + + + + spd + Speed counter + 0x8 + 32 + 0x00000000 + 0xEFFFFFFF + + + DIR + 1- reverse rotation +0- forward rotation + 31 + 1 + read-only + + + ASTAT + 1- a input is high +0- a input is low + 30 + 1 + read-only + + + BSTAT + 1- b input is high +0- b input is low + 29 + 1 + read-write + + + SPDCNT + spdcnt value + 0 + 28 + read-only + + + + + tmr + Timer counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TMRCNT + 32 bit free run timer + 0 + 32 + read-only + + + + + + zcmp2 + Z comparator + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + ZCMP2 + No description avaiable + 0 + 32 + read-write + + + + + phcmp2 + Phase comparator + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + PHCMP2 + No description avaiable + 0 + 32 + read-write + + + + + spdcmp2 + Speed comparator + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPDCMP2 + No description avaiable + 0 + 32 + read-write + + + + + match_cfg + No description avaiable + 0x8c + 32 + 0x00000000 + 0xFE00FE00 + + + ZCMPDIS + 1- postion compare not include zcnt + 31 + 1 + read-write + + + DIRCMPDIS + 1- postion compare not include rotation direction + 30 + 1 + read-write + + + DIRCMP + 0- position compare need positive rotation +1- position compare need negative rotation + 29 + 1 + read-write + + + SPDCMPDIS + No description avaiable + 28 + 1 + read-write + + + PHASE_MATCH_DIS + No description avaiable + 27 + 1 + read-write + + + POS_MATCH_DIR + No description avaiable + 26 + 1 + read-write + + + POS_MATCH_OPT + No description avaiable + 25 + 1 + read-write + + + ZCMP2DIS + No description avaiable + 15 + 1 + read-write + + + DIRCMP2DIS + No description avaiable + 14 + 1 + read-write + + + DIRCMP2 + No description avaiable + 13 + 1 + read-write + + + SPDCMP2DIS + No description avaiable + 12 + 1 + read-write + + + PHASE_MATCH_DIS2 + No description avaiable + 11 + 1 + read-write + + + POS_MATCH2_DIR + No description avaiable + 10 + 1 + read-write + + + POS_MATCH2_OPT + No description avaiable + 9 + 1 + read-write + + + + + 6 + 0x4 + filt_cfg_a,filt_cfg_b,filt_cfg_z,filt_cfg_h,filt_cfg_h2,filt_cfg_f + FILT_CFG[%s] + no description available + 0x90 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stable low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + qei_cfg + qei config register + 0x100 + 32 + 0x00000000 + 0x0000103F + + + SPEED_DIR_CHG_EN + clear counter if detect direction change + 12 + 1 + read-write + + + UVW_POS_OPT0 + set to output next area position for QEO use; +clr to output exact point position for MMC use + 5 + 1 + read-write + + + NEGEDGE_EN + bit4: negedge enable +bit3: posedge enable +bit2: W in hal enable +bit1: signal b(or V in hal) enable +bit0: signal a(or U in hal) enable +such as: +01001: use posedge A +11010: use both edge of signal B +11111: use both edge of all HAL siganls + 4 + 1 + read-write + + + POSIDGE_EN + No description avaiable + 3 + 1 + read-write + + + SIGZ_EN + No description avaiable + 2 + 1 + read-write + + + SIGB_EN + No description avaiable + 1 + 1 + read-write + + + SIGA_EN + No description avaiable + 0 + 1 + read-write + + + + + pulse0_num + pulse0_num + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0_NUM + for speed detection, will count the cycle number for configed pulse_num + 0 + 32 + read-write + + + + + pulse1_num + pulse1_num + 0x114 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1_NUM + No description avaiable + 0 + 32 + read-write + + + + + cycle0_cnt + cycle0_cnt + 0x118 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE0_CNT + No description avaiable + 0 + 32 + read-only + + + + + cycle0pulse_cnt + cycle0pulse_cnt + 0x11c + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE0PULSE_CNT + No description avaiable + 0 + 32 + read-only + + + + + cycle1_cnt + cycle1_cnt + 0x120 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE1_CNT + No description avaiable + 0 + 32 + read-only + + + + + cycle1pulse_cnt + cycle1pulse_cnt + 0x124 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE1PULSE_CNT + No description avaiable + 0 + 32 + read-only + + + + + cycle0_snap0 + cycle0_snap0 + 0x128 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE0_SNAP0 + No description avaiable + 0 + 32 + read-only + + + + + cycle0_snap1 + cycle0_snap1 + 0x12c + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE0_SNAP1 + No description avaiable + 0 + 32 + read-only + + + + + cycle1_snap0 + cycle1_snap0 + 0x130 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE1_SNAP0 + No description avaiable + 0 + 32 + read-only + + + + + cycle1_snap1 + cycle1_snap1 + 0x134 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE1_SNAP1 + No description avaiable + 0 + 32 + read-only + + + + + cycle0_num + cycle0_num + 0x140 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE0_NUM + No description avaiable + 0 + 32 + read-write + + + + + cycle1_num + cycle1_num + 0x144 + 32 + 0x00000000 + 0xFFFFFFFF + + + CYCLE1_NUM + No description avaiable + 0 + 32 + read-write + + + + + pulse0_cnt + pulse0_cnt + 0x148 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0_CNT + No description avaiable + 0 + 32 + read-only + + + + + pulse0cycle_cnt + pulse0cycle_cnt + 0x14c + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0CYCLE_CNT + No description avaiable + 0 + 32 + read-only + + + + + pulse1_cnt + pulse1_cnt + 0x150 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1_CNT + No description avaiable + 0 + 32 + read-only + + + + + pulse1cycle_cnt + pulse1cycle_cnt + 0x154 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1CYCLE_CNT + No description avaiable + 0 + 32 + read-only + + + + + pulse0_snap0 + pulse0_snap0 + 0x158 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0_SNAP0 + No description avaiable + 0 + 32 + read-only + + + + + pulse0cycle_snap0 + pulse0cycle_snap0 + 0x15c + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0CYCLE_SNAP0 + No description avaiable + 0 + 32 + read-only + + + + + pulse0_snap1 + pulse0_snap1 + 0x160 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0_SNAP1 + No description avaiable + 0 + 32 + read-only + + + + + pulse0cycle_snap1 + pulse0cycle_snap1 + 0x164 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE0CYCLE_SNAP1 + No description avaiable + 0 + 32 + read-only + + + + + pulse1_snap0 + pulse1_snap0 + 0x168 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1_SNAP0 + No description avaiable + 0 + 32 + read-only + + + + + pulse1cycle_snap0 + pulse1cycle_snap0 + 0x16c + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1CYCLE_SNAP0 + No description avaiable + 0 + 32 + read-only + + + + + pulse1_snap1 + pulse1_snap1 + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1_SNAP1 + No description avaiable + 0 + 32 + read-only + + + + + pulse1cycle_snap1 + pulse1cycle_snap1 + 0x174 + 32 + 0x00000000 + 0xFFFFFFFF + + + PULSE1CYCLE_SNAP1 + No description avaiable + 0 + 32 + read-only + + + + + adcx_cfg0 + adcx_cfg0 + 0x200 + 32 + 0x00000000 + 0x0000019F + + + X_ADCSEL + No description avaiable + 8 + 1 + read-write + + + X_ADC_ENABLE + No description avaiable + 7 + 1 + read-write + + + X_CHAN + No description avaiable + 0 + 5 + read-write + + + + + adcx_cfg1 + adcx_cfg1 + 0x204 + 32 + 0x00000000 + 0xFFFFFFFF + + + X_PARAM1 + No description avaiable + 16 + 16 + read-write + + + X_PARAM0 + No description avaiable + 0 + 16 + read-write + + + + + adcx_cfg2 + adcx_cfg2 + 0x208 + 32 + 0x00000000 + 0xFFFFFFFF + + + X_OFFSET + No description avaiable + 0 + 32 + read-write + + + + + adcy_cfg0 + adcy_cfg0 + 0x210 + 32 + 0x00000000 + 0x0000019F + + + Y_ADCSEL + No description avaiable + 8 + 1 + read-write + + + Y_ADC_ENABLE + No description avaiable + 7 + 1 + read-write + + + Y_CHAN + No description avaiable + 0 + 5 + read-write + + + + + adcy_cfg1 + adcy_cfg1 + 0x214 + 32 + 0x00000000 + 0xFFFFFFFF + + + Y_PARAM1 + No description avaiable + 16 + 16 + read-write + + + Y_PARAM0 + No description avaiable + 0 + 16 + read-write + + + + + adcy_cfg2 + adcy_cfg2 + 0x218 + 32 + 0x00000000 + 0xFFFFFFFF + + + Y_OFFSET + No description avaiable + 0 + 32 + read-write + + + + + cal_cfg + cal_cfg + 0x220 + 32 + 0x00000000 + 0x00FFFFFF + + + XY_DELAY + valid x/y delay, larger than this delay will be treated as invalid data. +Default 1.25us@200MHz; max 80ms; + 0 + 24 + read-write + + + + + phase_param + phase_param + 0x230 + 32 + 0x00000000 + 0xFFFFFFFF + + + PHASE_PARAM + No description avaiable + 0 + 32 + read-write + + + + + angle_adj + angle_adj + 0x234 + 32 + 0x00000000 + 0xFFFFFFFF + + + ANGLE_ADJ + No description avaiable + 0 + 32 + read-write + + + + + pos_threshold + pos_threshold + 0x238 + 32 + 0x00000000 + 0xFFFFFFFF + + + POS_THRESHOLD + No description avaiable + 0 + 32 + read-write + + + + + 6 + 0x4 + uvw_pos0,uvw_pos1,uvw_pos2,uvw_pos3,uvw_pos4,uvw_pos5 + UVW_POS[%s] + no description available + 0x240 + 32 + 0x00000000 + 0xFFFFFFFF + + + UVW_POS0 + No description avaiable + 0 + 32 + read-write + + + + + 6 + 0x4 + uvw_pos0_cfg,uvw_pos1_cfg,uvw_pos2_cfg,uvw_pos3_cfg,uvw_pos4_cfg,uvw_pos5_cfg + UVW_POS_CFG[%s] + no description available + 0x258 + 32 + 0x00000000 + 0x0000007F + + + POS_EN + No description avaiable + 6 + 1 + read-write + + + U_POS_SEL + No description avaiable + 4 + 2 + read-write + + + V_POS_SEL + No description avaiable + 2 + 2 + read-write + + + W_POS_SEL + No description avaiable + 0 + 2 + read-write + + + + + phase_cnt + phase_cnt + 0x280 + 32 + 0x00000000 + 0xFFFFFFFF + + + PHASE_CNT + No description avaiable + 0 + 32 + read-write + + + + + phase_update + phase_update + 0x284 + 32 + 0x00000000 + 0xFFFFFFFF + + + INC + set to add value to phase_cnt + 31 + 1 + write-only + + + DEC + set to minus value from phase_cnt(set inc and dec same time willl act inc) + 30 + 1 + write-only + + + VALUE + value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation + 0 + 30 + write-only + + + + + position + position + 0x288 + 32 + 0x00000000 + 0xFFFFFFFF + + + POSITION + No description avaiable + 0 + 32 + read-write + + + + + position_update + position_update + 0x28c + 32 + 0x00000000 + 0xFFFFFFFF + + + INC + set to add value to position + 31 + 1 + write-only + + + DEC + set to minus value from position(set inc and dec same time willl act inc) + 30 + 1 + write-only + + + VALUE + value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation + 0 + 30 + write-only + + + + + angle + No description avaiable + 0x290 + 32 + 0x00000000 + 0xFFFFFFFF + + + ANGLE + No description avaiable + 0 + 32 + read-only + + + + + pos_timeout + pos_timeout + 0x294 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + enable position timeout feature, if timeout, send valid again + 31 + 1 + read-write + + + TIMEOUT + postion timeout value + 0 + 31 + read-write + + + + + + + QEI1 + QEI1 + QEIV2 + 0xf0304000 + + + QEO0 + QEO0 + QEO + 0xf0308000 + + 0x0 + 0x114 + registers + + + + mode + analog waves mode + 0x0 + 32 + 0x00000000 + 0xFFFFFFF3 + + + WAVE2_ABOVE_MAX_LIMIT + wave2 above max limit mode. +0: output 0xffff. +1: output 0x0. +2: output as level_max_limit2.level0_max_limit + 30 + 2 + read-write + + + WAVE2_HIGH_AREA1_LIMIT + wave2 high area1 limit mode. +0: output 0xffff. +1: output as level_max_limit2.level0_max_limit + 29 + 1 + read-write + + + WAVE2_HIGH_AREA0_LIMIT + wave2 high area0 limit mode. +0: output 0xffff. +1: output as level_max_limit2.level0_max_limit + 28 + 1 + read-write + + + WAVE2_LOW_AREA1_LIMIT + wave2 low area1 limit mode. +0: output 0. +1: output as level_min_limit2.level1_min_limit + 27 + 1 + read-write + + + WAVE2_LOW_AREA0_LIMIT + wave2 low area0 limit mode. +0: output 0. +1: output as level_min_limit2.level1_min_limit + 26 + 1 + read-write + + + WAVE2_BELOW_MIN_LIMIT + wave2 below min limit mode. +0: output 0. +1: output 0xffff. +2: output as level_min_limit2.level1_min_limit + 24 + 2 + read-write + + + WAVE1_ABOVE_MAX_LIMIT + wave1 above max limit mode. +0: output 0xffff. +1: output 0x0. +2: output as level_max_limit1.level0_max_limit + 22 + 2 + read-write + + + WAVE1_HIGH_AREA1_LIMIT + wave1 high area1 limit mode. +0: output 0xffff. +1: output as level_max_limit1.level0_max_limit + 21 + 1 + read-write + + + WAVE1_HIGH_AREA0_LIMIT + wave1 high area0 limit mode. +0: output 0xffff. +1: output as level_max_limit1.level0_max_limit + 20 + 1 + read-write + + + WAVE1_LOW_AREA1_LIMIT + wave1 low area1 limit mode. +0: output 0. +1: output as level_min_limit1.level1_min_limit + 19 + 1 + read-write + + + WAVE1_LOW_AREA0_LIMIT + wave1 low area0 limit mode. +0: output 0. +1: output as level_min_limit1.level1_min_limit + 18 + 1 + read-write + + + WAVE1_BELOW_MIN_LIMIT + wave1 below min limit mode. +0: output 0. +1: output 0xffff. +2: output as level_min_limit1.level1_min_limit + 16 + 2 + read-write + + + WAVE0_ABOVE_MAX_LIMIT + wave0 above max limit mode. +0: output 0xffff. +1: output 0x0. +2: output as level_max_limit0.level0_max_limit + 14 + 2 + read-write + + + WAVE0_HIGH_AREA1_LIMIT + wave0 high area1 limit mode. +0: output 0xffff. +1: output as level_max_limit0.level0_max_limit + 13 + 1 + read-write + + + WAVE0_HIGH_AREA0_LIMIT + wave0 high area0 limit mode. +0: output 0xffff. +1: output as level_max_limit0.level0_max_limit + 12 + 1 + read-write + + + WAVE0_LOW_AREA1_LIMIT + wave0 low area1 limit mode. +0: output 0. +1: output as level_min_limit0.level1_min_limit + 11 + 1 + read-write + + + WAVE0_LOW_AREA0_LIMIT + wave0 low area0 limit mode. +0: output 0. +1: output as level_min_limit0.level1_min_limit + 10 + 1 + read-write + + + WAVE0_BELOW_MIN_LIMIT + wave0 below min limit mode. +0: output 0. +1: output 0xffff. +2: output as level_min_limit0.level1_min_limit + 8 + 2 + read-write + + + SADDLE_TYPE + saddle type seclect; +0:standard saddle. +1: triple-cos saddle. + 7 + 1 + read-write + + + EN_WAVE2_VD_VQ_INJECT + wave2 VdVq inject enable. +0: disable VdVq inject. +1: enable VdVq inject. + 6 + 1 + read-write + + + EN_WAVE1_VD_VQ_INJECT + wave1 VdVq inject enable. +0: disable VdVq inject. +1: enable VdVq inject. + 5 + 1 + read-write + + + EN_WAVE0_VD_VQ_INJECT + wave0 VdVq inject enable. +0: disable VdVq inject. +1: enable VdVq inject. + 4 + 1 + read-write + + + WAVES_OUTPUT_TYPE + wave0/1/2 output mode. +0: cosine wave. +1: saddle wave. +2. abs cosine wave. +3. saw wave + 0 + 2 + read-write + + + + + resolution + resolution of wave0/1/2 + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINES + wave0/1/2 resolution + 0 + 32 + read-write + + + + + 3 + 0x4 + wave0,wave1,wave2 + PHASE_SHIFT[%s] + no description available + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + VAL + wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period + 0 + 16 + read-write + + + + + 3 + 0x4 + wave0,wave1,wave2 + VD_VQ_INJECT[%s] + no description available + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + VQ_VAL + Vq inject value + 16 + 16 + read-write + + + VD_VAL + Vd inject value + 0 + 16 + read-write + + + + + vd_vq_load + load wave0/1/2 vd vq value + 0x20 + 32 + 0x00000000 + 0x00000001 + + + LOAD + load wave0/1/2 vd vq value. always read 0 +0: vd vq keep previous value. +1: load wave0/1/2 vd vq value at sametime. + 0 + 1 + write-only + + + + + 3 + 0x4 + wave0,wave1,wave2 + AMPLITUDE[%s] + no description available + 0x24 + 32 + 0x00000000 + 0x0001FFFF + + + EN_SCAL + enable wave amplitude scaling. 0: disable; 1: enable + 16 + 1 + read-write + + + AMP_VAL + amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value. + 0 + 16 + read-write + + + + + 3 + 0x4 + wave0,wave1,wave2 + MID_POINT[%s] + no description available + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value. + 0 + 32 + read-write + + + + + 3 + 0x8 + wave0,wave1,wave2 + LIMIT[%s] + no description available + 0x3c + + min + wave0 low area limit value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + LIMIT1 + low area limit level1 + 16 + 16 + read-write + + + LIMIT0 + low area limit level0 + 0 + 16 + read-write + + + + + max + wave0 high area limit value + 0x4 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + LIMIT1 + high area limit level1 + 16 + 16 + read-write + + + LIMIT0 + high area limit level0 + 0 + 16 + read-write + + + + + + 3 + 0x4 + wave0,wave1,wave2 + DEADZONE_SHIFT[%s] + no description available + 0x54 + 32 + 0x00000000 + 0x0000FFFF + + + VAL + wave0 deadzone shifter value + 0 + 16 + read-write + + + + + mode + wave_a/b/z output mode + 0x60 + 32 + 0x00000000 + 0x11111333 + + + REVERSE_EDGE_TYPE + pulse reverse wave，reverse edge point: +0: between pulse's posedge and negedge, min period dedicated by the num line_width +1: edge change point flow pulse's negedge. + 28 + 1 + read-write + + + EN_WDOG + enable abz wdog: +0: disable abz wdog. +1: enable abz wdog. + 24 + 1 + read-write + + + Z_POLARITY + wave_z polarity. +0: normal output. +1: invert normal output + 20 + 1 + read-write + + + B_POLARITY + wave_b polarity. +0: normal output. +1: invert normal output + 16 + 1 + read-write + + + A_POLARITY + wave_a polarity. +0: normal output. +1: invert normal output + 12 + 1 + read-write + + + Z_TYPE + wave_z type: +0: zero pulse and output high at both wave_a and wave_b are high. mantain about 25% period. +1: zero pulse output high about 75% period. start from 0 to 75% period. +2: zero pulse output high about 100% period. +3: wave_z output as tree-phase wave same as wave_a/wave_b + 8 + 2 + read-write + + + B_TYPE + wave_b type: +0: Two-phase orthogonality wave_b. +1: reverse wave of pulse/reverse type. +2: down wave of up/down type. +3: Three-phase orthogonality wave_b. + 4 + 2 + read-write + + + A_TYPE + wave_a type: +0: Two-phase orthogonality wave_a. +1: pulse wave of pulse/reverse type. +2: up wave of up/down type. +3: Three-phase orthogonality wave_a. + 0 + 2 + read-write + + + + + resolution + resolution of wave_a/b/z + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINES + wave_a/b/z resolution + 0 + 32 + read-write + + + + + 3 + 0x4 + a,b,z + PHASE_SHIFT[%s] + no description available + 0x68 + 32 + 0x00000000 + 0x0000FFFF + + + VAL + wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period. + 0 + 16 + read-write + + + + + line_width + Two-phase orthogonality wave 1/4 period + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINE + the num of system clk by 1/4 period when using as Two-phase orthogonality. + 0 + 32 + read-write + + + + + wdog_width + wdog width of qeo + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + WIDTH + wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk. + 0 + 32 + read-write + + + + + postion_sync + sync abz owned postion + 0x7c + 32 + 0x00000000 + 0x00000001 + + + POSTION + load next valid postion into abz owned postion. always read 0 +0: sync abz owned postion with next valid postion. +1: not sync. + 0 + 1 + write-only + + + + + mode + pwm mode + 0x80 + 32 + 0x00000000 + 0xFFFF031F + + + PWM7_SAFETY + PWM safety mode phase table + 30 + 2 + read-write + + + PWM6_SAFETY + PWM safety mode phase table + 28 + 2 + read-write + + + PWM5_SAFETY + PWM safety mode phase table + 26 + 2 + read-write + + + PWM4_SAFETY + PWM safety mode phase table + 24 + 2 + read-write + + + PWM3_SAFETY + PWM safety mode phase table + 22 + 2 + read-write + + + PWM2_SAFETY + PWM safety mode phase table + 20 + 2 + read-write + + + PWM1_SAFETY + PWM safety mode phase table + 18 + 2 + read-write + + + PWM0_SAFETY + PWM safety mode phase table + 16 + 2 + read-write + + + PWM_ENTER_SAFETY_MODE + PWM enter safety mode +0: not enter +1: enter + 9 + 1 + read-write + + + PWM_SAFETY_BYPASS + PWM safety mode bypass +0: not bypass +1: bypass + 8 + 1 + read-write + + + REVISE_UP_DN + exchange PWM pairs’ output +0: not exchange. +1: exchange. + 4 + 1 + read-write + + + PHASE_NUM + pwm force phase number. + 0 + 4 + read-write + + + + + resolution + resolution of pwm + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINES + pwm resolution + 0 + 32 + read-write + + + + + 4 + 0x4 + a,b,c,d + PHASE_SHIFT[%s] + no description available + 0x88 + 32 + 0x00000000 + 0x0000FFFF + + + VAL + pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period + 0 + 16 + read-write + + + + + 24 + 0x4 + posedge0,posedge1,posedge2,posedge3,posedge4,posedge5,posedge6,posedge7,posedge8,posedge9,posedge10,posedge11,negedge0,negedge1,negedge2,negedge3,negedge4,negedge5,negedge6,negedge7,negedge8,negedge9,negedge10,negedge11 + PHASE_TABLE[%s] + no description available + 0x98 + 32 + 0x00000000 + 0x0000FFFF + + + PWM7 + pwm phase table value + 14 + 2 + read-write + + + PWM6 + pwm phase table value + 12 + 2 + read-write + + + PWM5 + pwm phase table value + 10 + 2 + read-write + + + PWM4 + pwm phase table value + 8 + 2 + read-write + + + PWM3 + pwm phase table value + 6 + 2 + read-write + + + PWM2 + pwm phase table value + 4 + 2 + read-write + + + PWM1 + pwm phase table value + 2 + 2 + read-write + + + PWM0 + pwm phase table value + 0 + 2 + read-write + + + + + postion_software + softwave inject postion + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + POSTION_SOFTWAVE + softwave inject postion + 0 + 32 + read-write + + + + + postion_sel + select softwave inject postion + 0xfc + 32 + 0x00000000 + 0x00000001 + + + POSTION_SEL + enable softwave inject postion. +0: disable. +1: enable. + 0 + 1 + read-write + + + + + status + qeo status + 0x100 + 32 + 0x00000000 + 0xFFFF0001 + + + PWM_FOURCE + qeo_pwm_force observe + 16 + 16 + read-only + + + PWM_SAFETY + pwm_fault status + 0 + 1 + read-only + + + + + debug0 + qeo debug 0 + 0x104 + 32 + 0x00000000 + 0xFFFFFFFF + + + WAVE1 + wave1 observe + 16 + 16 + read-only + + + WAVE0 + wave0 observe + 0 + 16 + read-only + + + + + debug1 + qeo debug 1 + 0x108 + 32 + 0x00000000 + 0x1111FFFF + + + QEO_FINISH + qeo finish observe + 28 + 1 + read-only + + + WAVE_Z + wave_z observe + 24 + 1 + read-only + + + WAVE_B + wave_b observe + 20 + 1 + read-only + + + WAVE_A + wave_a observe + 16 + 1 + read-only + + + WAVE2 + wave2 observe + 0 + 16 + read-only + + + + + debug2 + qeo debug 2 + 0x10c + 32 + 0x00000000 + 0xFFFFFFFF + + + ABZ_OWN_POSTION + abz_own_postion observe + 0 + 32 + read-only + + + + + debug3 + qeo debug 3 + 0x110 + 32 + 0x00000000 + 0xFFFFFFFF + + + ABZ_OWN_POSTION + abz_own_postion observe + 0 + 32 + read-only + + + + + + + QEO1 + QEO1 + QEO + 0xf030c000 + + + MMC0 + MMC0 + MMC + 0xf0310000 + + 0x0 + 0x334 + registers + + + + CR + Control Register + 0x0 + 32 + 0x00000000 + 0xBFFFFFFF + + + SFTRST + Software reset, high active. When write 1 ,all internal logical will be reset. +0b - No action +1b - All MMC internal registers are forced into their reset state. Interface registers are not affected. + 31 + 1 + read-write + + + INI_BR0_POS_REQ + Auto clear. Only effective in open_loop mode. + 29 + 1 + read-write + + + INI_BR1_POS_REQ + Auto clear. Only effective in open_loop mode. + 28 + 1 + read-write + + + FRCACCELZERO + Zeroise the accelerator calculation. + 27 + 1 + read-write + + + MS_COEF_EN + Multiple Coefficients Enable + 26 + 1 + read-write + + + INI_DELTA_POS_TRG_TYPE + 0: Time Stamp in the configuration +1: Risedge of In Trg[0] +2: Risedge of In Trg[1] +3: Risedge of out trg[0] +4: Risedge of out trg[1] +5: triggered by self position trigger +6: triggered by self speed trigger +Otherser: no function + 23 + 3 + read-write + + + INI_POS_TRG_TYPE + 0: Time Stamp in the configuration +1: Risedge of In Trg[0] +2: Risedge of In Trg[1] +3: Risedge of out trg[0] +4: Risedge of out trg[1] +5: triggered by self position trigger +6: triggered by self speed trigger +Otherser: no function + 20 + 3 + read-write + + + INI_DELTA_POS_CMD_MSK + 1: change +0: won't change +bit 3: for delta accel +bit 2: for delta speed +bit 1: for delta revolution +bit 0: for delta position + 16 + 4 + read-write + + + INI_DELTA_POS_REQ + 1: Command to reload the delta pos. Auto clear +0: + 15 + 1 + read-write + + + OPEN_LOOP_MODE + 1: in open loop mode +0: not in open loop mode + 14 + 1 + read-write + + + POS_TYPE + 1: 32-bit for rev+pos, with each element occupying 16 bits +0: 32-bit for rev, and 32 bit for pos +When CR[MANUAL_IO]==1, +1: means that the INI_POS is acting as INI_POS cmds +0: means that the INI_POS is simulating the input of iposition and itimestamp + 13 + 1 + read-write + + + INI_POS_CMD_MSK + 1: change +0: won't change +bit 3: for accel +bit 2: for speed +bit 1: for revolution +bit 0: for position + 9 + 4 + read-write + + + INI_POS_REQ + 1: Command to reload the positions. Auto clear +0: + 8 + 1 + read-write + + + INI_COEFS_CMD_MSK + 1: change +0: won't change +bit 2: for ACOEF +bit 1: for ICOEF +bit 0: for PCOEF + 5 + 3 + read-write + + + INI_COEFS_CMD + 1: Command to reload the coefs. Auto clear +0: + 4 + 1 + read-write + + + SHADOW_RD_REQ + 1: Shadow Request for read of tracking parameters. Auto clear +0: + 3 + 1 + read-write + + + ADJOP + 1: use the input iposition whenever a new iposition comes, and force the predicted output stop at the boundaries. +0: Continuous tracking mode, without any boundary check + 2 + 1 + read-write + + + DISCRETETRC + 1: Discrete position input +0: Continuous position input + 1 + 1 + read-write + + + MOD_EN + Module Enable + 0 + 1 + read-write + + + + + STA + Status Register + 0x4 + 32 + 0x00000020 + 0xF00007F7 + + + ERR_ID + Tracking ERR_ID + 28 + 4 + read-only + + + SPEED_TRG_VALID + W1C + 10 + 1 + write-only + + + POS_TRG_VALID + W1C + 9 + 1 + write-only + + + INI_DELTA_POS_REQ_CMD_DONE + W1C + 8 + 1 + write-only + + + INI_BR0_POS_REQ_CMD_DONE + W1C + 7 + 1 + write-only + + + INI_BR1_POS_REQ_CMD_DONE + W1C + 6 + 1 + write-only + + + IDLE + Tracking Module in Idle status + 5 + 1 + read-only + + + OOSYNC + Tracking module out-of sync. W1C + 4 + 1 + write-only + + + INI_POS_REQ_CMD_DONE + W1C + 2 + 1 + write-only + + + INI_COEFS_CMD_DONE + W1C + 1 + 1 + write-only + + + SHADOW_RD_DONE + Shadow ready for read. Auto cleared by setting CR[SHADOW_RD_REQ] as 1 + 0 + 1 + read-only + + + + + INT_EN + Interrupt Enable Register + 0x8 + 32 + 0x00000000 + 0x000007D7 + + + SPEED_TRG_VLD_IE + Interrupt Enable for SPEED_TRG_VALID + 10 + 1 + read-write + + + POS_TRG_VLD_IE + Interrupt Enable for POS_TRG_VALID + 9 + 1 + read-write + + + INI_DELTA_POS_REQ_CMD_DONE_IE + Interrupt Enable for INI_DELTA_POS_REQ_CMD_DONE + 8 + 1 + read-write + + + INI_BR0_POS_REQ_CMD_DONE_IE + Interrupt Enable for INI_BR0_POS_REQ_CMD_DONE + 7 + 1 + read-write + + + INI_BR1_POS_REQ_CMD_DONE_IE + Interrupt Enable for INI_BR1_POS_REQ_CMD_DONE + 6 + 1 + read-write + + + OOSYNC_IE + Interrupt Enable for OOSYNC + 4 + 1 + read-write + + + INI_POS_REQ_CMD_DONE_IE + Interrupt Enable for INI_POS_REQ_CMD_DONE + 2 + 1 + read-write + + + INI_COEFS_CMD_DONE_IE + Interrupt Enable for INI_COEFS_CMD_DONE + 1 + 1 + read-write + + + SHADOW_RD_DONE_IE + Interrupt Enable for SHADOW_RD_DONE + 0 + 1 + read-write + + + + + SYSCLK_FREQ + System Clock Frequency Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + system clock frequency, ufix<32, 0> + 0 + 32 + read-write + + + + + SYSCLK_PERIOD + System Clock Period Register + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + round( the value of clock period * (2^24)*(2^20) ), ufix<32, 0> + 0 + 32 + read-write + + + + + OOSYNC_THETA_THR + Position Out-Of-Sync Threshold Regster + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the threshold of theta difference between actual and prediction for out-of-sync determination，ufix<32, 32> + 0 + 32 + read-write + + + + + DiscreteCfg0 + Discrete Mode Configuration 0 Register + 0x18 + 32 + 0x00000000 + 0x000FFFFF + + + POSMAX + Max ID Of Lines. For example-1, for 512 lines, it is 511. ufix<32, 0> + 0 + 20 + read-write + + + + + DiscreteCfg1 + Discrete Mode Configuration 1 Register + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + INV_POSMAX + discrete mode: ufix<32, 0> of 1/(Number Of Lines) +continuous mode: the max delta for tracking from the last received position, ufix<32, 32> + 0 + 32 + read-write + + + + + ContCfg0 + Continuous Mode Configuration 0 Register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + HALF_CIRC_THETA + the theta for cal the clockwise or anticlockwise rotation between two adjacent inputs, ufix<32, 32> + 0 + 32 + read-write + + + + + INI_POS_TIME + The destined timestamp register for position initialization + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + indicate the time to change the values. +0: instant change + 0 + 32 + read-write + + + + + INI_POS + The destined position register for position initialization + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value； +continuous mode: ufix<32, 32> + 0 + 32 + read-write + + + + + INI_REV + The destined revolution register for position initialization + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value； +continuous mode: ufix<32, 0> + 0 + 32 + read-write + + + + + INI_SPEED + The destined speed register for position initialization + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value; +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + INI_ACCEL + The destined accelerator register for position initialization + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + INI_COEF_TIME + The destined timestamp register for coefficients initialization + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + indicate the time to change the values. +0: instant change + 0 + 32 + read-write + + + + + INI_PCOEF + The destined coefficient P register for coefficients initialization + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value, fix<32, 15> + 0 + 32 + read-write + + + + + INI_ICOEF + The destined coefficient I register for coefficients initialization + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value, fix<32, 21> + 0 + 32 + read-write + + + + + INI_ACOEF + The destined coefficient A register for coefficients initialization + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value, fix<32, 19> + 0 + 32 + read-write + + + + + ESTM_TIM + The timestamp register for internal estimation + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + ESTM_POS + The position register for the internal estimation + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + ESTM_REV + The revolution register for the internal estimation + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + ESTM_SPEED + The speed register for the internal estimation + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + ESTM_ACCEL + The accelerator register for theinternal estimation + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + CUR_PCOEF + The coefficient P register for the internal estimation + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + CUR_ICOEF + The coefficient I register for the internal estimation + 0x60 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + CUR_ACOEF + The coefficient A register for the internal estimation + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + INI_DELTA_POS_TIME + The destined timestamp register for delta position initialization + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + indicate the time to change the values. +0: instant change + 0 + 32 + read-write + + + + + INI_DELTA_POS + The destined delta position register for delta position initialization + 0x6c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: ufix <32, 32> + 0 + 32 + read-write + + + + + INI_DELTA_REV + The destined delta revolution register for delta position initialization + 0x70 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 0> + 0 + 32 + read-write + + + + + INI_DELTA_SPEED + The destined delta speed register for delta position initialization + 0x74 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value； +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + INI_DELTA_ACCEL + The destined delta accelerator register for delta position initialization + 0x78 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + pos_trg_cfg + Tracking Configuration pos trigger cfg + 0x80 + 32 + 0x00000000 + 0x00000003 + + + EDGE + 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than + 1 + 1 + read-write + + + EN + 1-trigger valid; 0-Trigger not valid" + 0 + 1 + read-write + + + + + pos_trg_pos_thr + Tracking Configuration position threshold + 0x84 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + For pos out trigger (pos). +ufix<32, 32> + 0 + 32 + read-write + + + + + pos_trg_rev_thr + Tracking Configuration revolution threshold + 0x88 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + For pos out trigger (rev) +fix<32, 0> + 0 + 32 + read-write + + + + + speed_trg_cfg + Tracking Configuration speed trigger cfg + 0x8c + 32 + 0x00000000 + 0x00000007 + + + COMP_TYPE + 1: Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) + 2 + 1 + read-write + + + EDGE + 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than + 1 + 1 + read-write + + + EN + 1-trigger valid; 0-Trigger not valid +Normally it means either the max pos speed, or the min negative speed. + 0 + 1 + read-write + + + + + speed_trg_thr + Tracking Configuration speed threshold + 0x90 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + For speed trigger. +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + 3 + 0x14 + 0,1,2 + COEF_TRG_CFG[%s] + no description available + 0xa0 + + err_thr + Tracking Configuration coef trigger cfg&index0 + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + ErrThr0: Error Threshold 0, (abs(tracking error)>= will choose the coefs as below) +Note: ErrThr0>ErrThr1>ErrThr2 +ufix<31, 28> + 0 + 32 + read-write + + + + + P + Tracking Configuration coef trigger cfg&index0 P + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + P0_Coef, fix<32, 15> + 0 + 32 + read-write + + + + + I + Tracking Configuration coef trigger cfg&index0 I + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + I0_Coef, fix<32, 21> + 0 + 32 + read-write + + + + + A + Tracking Configuration coef trigger cfg&index0 A + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + A0_Coef，fix<32, 19> + 0 + 32 + read-write + + + + + TIME + Tracking Configuration coef trigger cfg&index0 time + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + CoefTime0: Time Stayed using this coefs (counted in input samples). Ideal value of tracing cycles should +1. ufix<32,0> + 0 + 32 + read-write + + + + + + 2 + 0x100 + 0,1 + BR[%s] + no description available + 0x100 + + BR_CTRL + Prediction Control Register + 0x0 + 32 + 0x00000000 + 0x63BDFFB7 + + + SPEED_TRG_VALID_IE + Interrupt Enable for SPEED_TRG_VALID + 30 + 1 + read-write + + + POS_TRG_VALID_IE + Interrupt Enable for POS_TRG_VALID + 29 + 1 + read-write + + + INI_POS_TRG_TYPE + 0: Time Stamp in the configuration +1: Risedge of In Trg[0] +2: Risedge of In Trg[1] +3: Risedge of out trg[0] +4: Risedge of out trg[1] +5: Risedge of self pos trigger +6: Risedge of self speed trigger +Others: no function + 23 + 3 + read-write + + + INI_POS_CMD_MSK + 1: change +0: won't change +bit 3: for accel +bit 2: for speed +bit 1: for revolution +bit 0: for position + 18 + 4 + read-write + + + INI_DELTA_POS_TRG_TYPE + 0: Time Stamp in the configuration +1: Risedge of In Trg[0] +2: Risedge of In Trg[1] +3: Risedge of out trg[0] +4: Risedge of out trg[1] +5: Risedge of self pos trigger +6: Risedge of self speed trigger +Others: no function + 14 + 3 + read-write + + + INI_DELTA_POS_DONE_IE + Interrupt Enable for INI_DELTA_POS_DONE + 13 + 1 + read-write + + + INI_DELTA_POS_CMD_MSK + 1: change +0: won't change +bit 3: for delta accel +bit 2: for delta speed +bit 1: for delta revolution +bit 0: for delta position + 9 + 4 + read-write + + + INI_DELTA_POS_REQ + 1: Command to reload the delta pos. Auto clear +0: + 8 + 1 + read-write + + + OPEN_LOOP_MODE + 1: in open loop mode +0: not in open loop mode + 7 + 1 + read-write + + + PRED_MODE + 1:continuously repeat pred, +0:cal the pred based on a definite time-stamp offset, +2:programed one-shot prediction mode + 4 + 2 + read-write + + + NF_TRG_TYPE + 1. Each non-first trigger by external trigger pin +0. Each non-first trigger by the timer + 2 + 1 + read-write + + + F_TRG_TYPE + 1. First trigger by external trigger pin +0. First trigger by the timer +When in CR[MANUAL_IO]=1 mode, it is the prediction trigger + 1 + 1 + read-write + + + BR_EN + Branch Enable + 0 + 1 + read-write + + + + + BR_TIMEOFF + Prediction Timing Offset Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + ufix<32, 0> time offset incycles from the trigger time + 0 + 32 + read-write + + + + + BR_TRG_PERIOD + Prediction Triggering Period Offset Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + uifx<32, 0>, time offset incycles between each trigger time + 0 + 32 + read-write + + + + + BR_TRG_F_TIME + Prediction Triggering First Offset Register + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + uifx<32, 0> the time for the first trigger + 0 + 32 + read-write + + + + + BR_ST + Prediction Status Register + 0x10 + 32 + 0x00000000 + 0x0000076F + + + OPEN_LOOP_ST + 1：in open loop mode +0：in closed loop mode + 10 + 1 + read-only + + + SPEED_TRG_VLD + 1：self speed trigger event found +0：self speed trigger event not found yet + 9 + 1 + write-only + + + POS_TRG_VLD + 1：self position trigger event found +0：self position trigger event not found yet + 8 + 1 + write-only + + + INI_DELTA_POS_DONE + 1: the initialization of delta position command is done +0: the initialization of delta position command is not done + 6 + 1 + write-only + + + IDLE + 1: The prediction module is idle. +0: The prediction module is not idle. + 5 + 1 + read-only + + + ERR_ID + The module's error ID output + 0 + 4 + read-only + + + + + BR_TRG_pos_cfg + Prediction Configuration postion trigger cfg + 0x40 + 32 + 0x00000000 + 0x00000003 + + + EDGE + bit1: 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than + 1 + 1 + read-write + + + EN + 1-trigger valid; 0-Trigger not valid + 0 + 1 + read-write + + + + + BR_TRG_pos_thr + Prediction Configuration postion threshold + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + For pos out trigger (pos). +ufix<32, 32> + 0 + 32 + read-write + + + + + BR_TRG_rev_thr + Prediction Configuration revolutiom threshold + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + For pos out trigger (rev) +ufix<32, 0> + 0 + 32 + read-write + + + + + BR_TRG_speed_cfg + Prediction Configuration speed trigger cfg + 0x4c + 32 + 0x00000000 + 0x00000007 + + + COMP_TYPE + Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) + 2 + 1 + read-write + + + EDGE_SEL + 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than + 1 + 1 + read-write + + + EN + 1-trigger valid; 0-Trigger not valid +Normally it means either the max pos speed, or the min negative speed. + 0 + 1 + read-write + + + + + BR_TRG_speed_thr + Prediction Configuration speed threshold + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + For speed trigger. +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + BR_INI_POS_TIME + Initialization timestamp for open-loop mode + 0xc0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + indicate the time to change the values. +0: instant change + 0 + 32 + read-write + + + + + BR_INI_POS + Initialization position for open-loop mode + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +ufix<32, 32> + 0 + 32 + read-write + + + + + BR_INI_REV + Initialization revolution for open-loop mode + 0xc8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +ufix<32, 0> + 0 + 32 + read-write + + + + + BR_INI_SPEED + Initialization speed for open-loop mode + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +fix<32, 19> + 0 + 32 + read-write + + + + + BR_INI_ACCEL + Initialization acceleration for open-loop mode + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + BR_INI_DELTA_POS_TIME + Initialization timestamp for delta mode in prediction mode + 0xd4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + indicate the time to change the values. +0: instant change + 0 + 32 + read-write + + + + + BR_INI_DELTA_POS + Initialization delta position for delta mode in prediction mode + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: ufix<32, 32> + 0 + 32 + read-write + + + + + BR_INI_DELTA_REV + Initialization delta revolution for delta mode in prediction mode + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 0> + 0 + 32 + read-write + + + + + BR_INI_DELTA_SPEED + Initialization delta speed for delta mode in prediction mode + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + BR_INI_DELTA_ACCEL + Initialization delta acceleration for delta mode in prediction mode + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value +continuous mode: fix<32, 19> + 0 + 32 + read-write + + + + + BR_CUR_POS_TIME + Monitor of the output timestamp + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BR_CUR_POS + Monitor of the output position + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BR_CUR_REV + Monitor of the output revolution + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BR_CUR_SPEED + Monitor of the output speed + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BR_CUR_ACCEL + Monitor of the output acceleration + 0xfc + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + + BK0_TIMESTAMP + Monitor of the just received input timestamp for tracing logic + 0x300 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK0_POSITION + Monitor of the just received input position for tracing logic + 0x304 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK0_REVOLUTION + Monitor of the just received input revolution for tracing logic + 0x308 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK0_SPEED + Monitor of the just received input speed for tracing logic + 0x30c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK0_ACCELERATOR + Monitor of the just received input acceleration for tracing logic + 0x310 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK1_TIMESTAMP + Monitor of the previous received input timestamp for tracing logic + 0x320 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK1_POSITION + Monitor of the previous received input position for tracing logic + 0x324 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK1_REVOLUTION + Monitor of the previous received input revolution for tracing logic + 0x328 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK1_SPEED + Monitor of the previous received input speed for tracing logic + 0x32c + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + BK1_ACCELERATOR + Monitor of the previous received input acceleration for tracing logic + 0x330 + 32 + 0x00000000 + 0xFFFFFFFF + + + VAL + the value + 0 + 32 + read-only + + + + + + + MMC1 + MMC1 + MMC + 0xf0314000 + + + PWM0 + PWM0 + PWM + 0xf0318000 + + 0x0 + 0x290 + registers + + + + unlk + Shadow registers unlock register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHUNLK + write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, +otherwise the shadow registers can not be written. + 0 + 32 + read-write + + + + + sta + Counter start register + UNION_STA + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + XSTA + pwm timer counter extended start point, should back to this value after reach xrld + 28 + 4 + read-write + + + STA + pwm timer counter start value + sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk + 4 + 24 + read-write + + + + + rld + Counter reload register + UNION_RLD + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + XRLD + timeout counter extended reload point, counter will reload to xsta after reach this point + 28 + 4 + read-write + + + RLD + pwm timer counter reload value + 4 + 24 + read-write + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CMP[%s] + no description available + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + XCMP + extended counter compare value + 28 + 4 + read-write + + + CMP + clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, +and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. + 4 + 24 + read-write + + + CMPHLF + half clock counter compare value + 3 + 1 + read-write + + + CMPJIT + jitter counter compare value + 0 + 3 + read-write + + + + + frcmd + Force output mode register + 0x78 + 32 + 0x00000000 + 0x0000FFFF + + + FRCMD + 2bit for each PWM output channel (0-7); +00: force output 0 +01: force output 1 +10: output highz +11: no force + 0 + 16 + read-write + + + + + shlk + Shadow registers lock register + 0x7c + 32 + 0x00000000 + 0x80000000 + + + SHLK + write 1 to lock all shawdow register, wirte access is not permitted + 31 + 1 + read-write + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CHCFG[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFF0003 + + + CMPSELEND + assign the last comparator for this output channel + 24 + 5 + read-write + + + CMPSELBEG + assign the first comparator for this output channel + 16 + 5 + read-write + + + OUTPOL + output polarity, set to 1 will invert the output + 1 + 1 + read-write + + + + + gcr + Global control register + 0xf0 + 32 + 0x00000000 + 0xFDFFFFEF + + + FAULTI3EN + 1- enable the internal fault input 3 + 31 + 1 + read-write + + + FAULTI2EN + 1- enable the internal fault input 2 + 30 + 1 + read-write + + + FAULTI1EN + 1- enable the internal fault input 1 + 29 + 1 + read-write + + + FAULTI0EN + 1- enable the internal fault input 0 + 28 + 1 + read-write + + + DEBUGFAULT + 1- enable debug mode output protection + 27 + 1 + read-write + + + FRCPOL + polarity of input pwm_force, +1- active low +0- active high + 26 + 1 + read-write + + + HWSHDWEDG + When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. +This bit assign its which edge is used as compare shadow register hardware load event. +1- Falling edge +0- Rising edge + 24 + 1 + read-write + + + CMPSHDWSEL + This bitfield select one of the comparators as hardware event time to load comparator shadow registers + 19 + 5 + read-write + + + FAULTRECEDG + When hardware load is selected as output fault recover trigger and the selected channel is capture mode. +This bit assign its effective edge of fault recover trigger. +1- Falling edge +0- Rising edge + 18 + 1 + read-write + + + FAULTRECHWSEL + Selec one of the 24 comparators as fault output recover trigger. + 13 + 5 + read-write + + + FAULTE1EN + 1- enable the external fault input 1 + 12 + 1 + read-write + + + FAULTE0EN + 1- enable the external fault input 0 + 11 + 1 + read-write + + + FAULTEXPOL + external fault polarity +1-active low +0-active high + 9 + 2 + read-write + + + RLDSYNCEN + 1- pwm timer counter reset to reload value (rld) by synci is enabled + 8 + 1 + read-write + + + CEN + 1- enable the pwm timer counter +0- stop the pwm timer counter + 7 + 1 + read-write + + + FAULTCLR + 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. +User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. + 6 + 1 + read-write + + + XRLDSYNCEN + 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled + 5 + 1 + read-write + + + TIMERRESET + set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear + 3 + 1 + read-write + + + FRCTIME + This bit field select the force effective time +00: force immediately +01: force at main counter reload time +10: force at FRCSYNCI +11: no force + 1 + 2 + write-only + + + SWFRC + 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect + 0 + 1 + read-write + + + + + shcr + Shadow register control register + 0xf4 + 32 + 0x00000000 + 0x00001FFF + + + FRCSHDWSEL + This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers + 8 + 5 + read-write + + + CNTSHDWSEL + This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) + 3 + 5 + read-write + + + CNTSHDWUPT + This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 1 + 2 + read-write + + + SHLKEN + 1- enable shadow registers lock feature, +0- disable shadow registers lock, shlk bit will always be 0 + 0 + 1 + read-write + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CAPPOS[%s] + no description available + 0x100 + 32 + 0x00000000 + 0xFFFFFFF0 + + + CAPPOS + counter value captured at input posedge + 4 + 28 + read-only + + + + + cnt + Counter + 0x170 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + + + 24 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CAPNEG[%s] + no description available + 0x180 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAPNEG + counter value captured at input signal falling edge + 0 + 32 + read-only + + + + + cntcopy + Counter copy + 0x1f0 + 32 + 0x00000000 + 0xFFFFFFFF + + + XCNT + current extended counter value + 28 + 4 + read-only + + + CNT + current clock counter value + 4 + 24 + read-only + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + PWMCFG[%s] + no description available + 0x200 + 32 + 0x00000000 + 0x1FFFFFFF + + + OEN + PWM output enable +1- output is enabled +0- output is disabled + 28 + 1 + read-write + + + FRCSHDWUPT + This bitfield select when the FRCMD shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 26 + 2 + read-write + + + FAULTMODE + This bitfield defines the PWM output status when fault condition happen +00: force output 0 +01: force output 1 +1x: output highz + 24 + 2 + read-write + + + FAULTRECTIME + This bitfield select when to recover PWM output after fault condition removed. +00: immediately +01: after pwm timer counter reload time +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after software write faultclr bit in GCR register + 22 + 2 + read-write + + + FRCSRCSEL + Select sources for force output +0- force output is enabled when FRCI assert +1- force output is enabled by software write swfrc to 1 + 21 + 1 + read-write + + + PAIR + 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. +0- PWM output is in indepandent mode. + 20 + 1 + read-write + + + DEADAREA + This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. +Note: user should configure pair bit and this bitfield before PWM output is enabled. + 0 + 20 + read-write + + + + + sr + Status register + 0x220 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTF + fault condition flag + 27 + 1 + write-only + + + XRLDF + extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert + 26 + 1 + write-only + + + HALFRLDF + half reload flag, this flag set when cnt count to rld/2 + 25 + 1 + write-only + + + RLDF + reload flag, this flag set when cnt count to rld value or when SYNCI assert + 24 + 1 + write-only + + + CMPFX + comparator output compare or input capture flag + 0 + 24 + write-only + + + + + irqen + Interrupt request enable register + 0x224 + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTIRQE + fault condition interrupt enable + 27 + 1 + read-write + + + XRLDIRQE + extended reload flag interrupt enable + 26 + 1 + read-write + + + HALFRLDIRQE + half reload flag interrupt enable + 25 + 1 + read-write + + + RLDIRQE + reload flag interrupt enable + 24 + 1 + read-write + + + CMPIRQEX + comparator output compare or input capture flag interrupt enable + 0 + 24 + read-write + + + + + dmaen + DMA request enable register + 0x22c + 32 + 0x00000000 + 0x0FFFFFFF + + + FAULTEN + fault condition DMA request enable + 27 + 1 + read-write + + + XRLDEN + extended reload flag DMA request enable + 26 + 1 + read-write + + + HALFRLDEN + half reload flag DMA request enable + 25 + 1 + read-write + + + RLDEN + reload flag DMA request enable + 24 + 1 + read-write + + + CMPENX + comparator output compare or input capture flag DMA request enable + 0 + 24 + read-write + + + + + 24 + 0x4 + cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + CMPCFG[%s] + no description available + 0x230 + 32 + 0x00000000 + 0x000000FF + + + XCNTCMPEN + This bitfield enable the comparator to compare xcmp with xcnt. + 4 + 4 + read-write + + + CMPSHDWUPT + This bitfield select when the comparator shadow register will be loaded to its work register +00: after software set shlk bit of shlk register +01: immediately after the register being modified +10: after hardware event assert, user can select one of the comparators to generate this hardware event. + The comparator can be either output compare mode or input capture mode. +11: after SHSYNCI assert + 2 + 2 + read-write + + + CMPMODE + comparator mode +0- output compare mode +1- input capture mode + 1 + 1 + read-write + + + + + + + PWM1 + PWM1 + PWM + 0xf031c000 + + + RDC + RDC + RDC + 0xf0320000 + + 0x0 + 0xf0 + registers + + + + rdc_ctl + rdc control + 0x0 + 32 + 0x00000000 + 0x003FF077 + + + TS_SEL + Time stamp selection for accumulation +0: end of accumulation +1: start of accumulation +2: center of accumulation + 20 + 2 + read-write + + + ACC_LEN + Accumulate time, support on the fly change +0：1 cycle +1：2 cycles +… +255: 256 cycles + 12 + 8 + read-write + + + RECTIFY_SEL + Select reference point of rectify signal +0: 0 phase of internal exciting signal +1: 90 phase of internal exciting signal +2: 180 phase of internal exciting signal +3: 270 phase of internal exciting signal +4: use value on external pin +5: use invert value on external pin + 4 + 3 + read-write + + + ACC_EN + Enable rdc accumulate +0: rdc disable +1: rdc enable + 2 + 1 + read-write + + + EXC_START + Write 1 start excite signal, always read 0 +0: no effect +1: start excite signal + 1 + 1 + read-write + + + EXC_EN + Enable rdc excite signal +0: rdc disable +1: rdc enable + 0 + 1 + read-write + + + + + acc_i + accumulate result of i_channel + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC + accumulate result of i_channel, this is a signed number + 0 + 32 + read-only + + + + + acc_q + accumulate result of q_channel + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC + accumulate result of q_channel, this is a signed number + 0 + 32 + read-only + + + + + in_ctl + input channel selection + 0xc + 32 + 0x00000000 + 0x0011F11F + + + PORT_Q_SEL + Input port selection for q_channel, +0:sel port0 +1:sel port1 + 20 + 1 + read-write + + + CH_Q_SEL + Input channel selection for q_channel +0: channel 0 selected +1: channel 1 selected +… +31: channel 31 selected + 12 + 5 + read-write + + + PORT_I_SEL + Input port selection for i_channel, +0:sel port0 +1:sel port1 + 8 + 1 + read-write + + + CH_I_SEL + Input channel selection for i_channel +0: channel 0 selected +1: channel 1 selected +… +31: channel 31 selected + 0 + 5 + read-write + + + + + out_ctl + output channel selection + 0x10 + 32 + 0x00000000 + 0x00001F1F + + + CH_Q_SEL + Output channel selection for q_channel + 8 + 5 + read-write + + + CH_I_SEL + Output channel selection for i_channel + 0 + 5 + read-write + + + + + exc_timming + excitation signal timming setting + 0x34 + 32 + 0x000400C8 + 0x01FFFFFF + + + SWAP + Swap output of PWM and DAC +0: disable swap +1: swap output + 24 + 1 + read-write + + + PWM_PRD + Pwm period in samples， +0：1 sample period +1: 2 sample period +... +15: 16 sample period + 20 + 4 + read-write + + + SMP_NUM + Number of sample every excitation period +0: 4 point +1: 8 point +… +8: 1024 point + 16 + 4 + read-write + + + SMP_RATE + The period for excitation sample in clock cycle， +0: not allowed +1: 1 cycle +2: 2 cycles +… +65535 : 65535 cycles + 0 + 16 + read-write + + + + + exc_scaling + amplitude scaling for excitation + 0x38 + 32 + 0x00000011 + 0x000000FF + + + AMP_EXP + Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + 4 + 4 + read-write + + + AMP_MAN + Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + 0 + 4 + read-write + + + + + exc_offset + amplitude offset setting + 0x3c + 32 + 0x00800000 + 0x00FFFFFF + + + AMP_OFFSET + Offset for excitation + 0 + 24 + read-write + + + + + pwm_scaling + amplitude scaling for excitation + 0x40 + 32 + 0x00000111 + 0x000031FF + + + N_POL + Polarity of exc_n signal +0: high active +1: low active + 13 + 1 + read-write + + + P_POL + Polarity of exc_p signal +0: high active +1: low active + 12 + 1 + read-write + + + DITHER + Enable dither of pwm +0: disable +1: enable + 8 + 1 + read-write + + + AMP_EXP + Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + 4 + 4 + read-write + + + AMP_MAN + Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + 0 + 4 + read-write + + + + + pwm_offset + amplitude offset setting + 0x44 + 32 + 0x00000064 + 0x00FFFFFF + + + AMP_OFFSET + Offset for excitation + 0 + 24 + read-write + + + + + trig_out0_cfg + Configuration for trigger out 0 in clock cycle + 0x48 + 32 + 0x00100019 + 0x001FFFFF + + + ENABLE + Enable trigger out0 +0: disable +1: enable + 20 + 1 + read-write + + + LEAD_TIM + Lead time for trigger out0 from center of low level , this is a signed value +… +2: 2 cycle befor center of low level +1: 1 cycle before center of low level +0: center of low level +-1: 1cycle after center of low level +-2: 2cycle after center of low level + 0 + 20 + read-write + + + + + trig_out1_cfg + Configuration for trigger out 1 in clock cycle + 0x4c + 32 + 0x0010004B + 0x001FFFFF + + + ENABLE + Enable trigger out1 +0: disable +1: enable + 20 + 1 + read-write + + + LEAD_TIM + Lead time for trigger out0 from center of hight level , this is a signed value +… +2: 2 cycle befor center of hight level +1: 1 cycle before center of hight level +0: center of hight level +-1: 1cycle after center of hight level +-2: 2cycle after center of hight level + 0 + 20 + read-write + + + + + pwm_dz + pwm dead zone control in clock cycle + 0x50 + 32 + 0x00000000 + 0x0000FFFF + + + DZ_N + Exc_n dead zone in clock cycle before swap +0: no dead zone +1: 1 cycle dead zone +2: 2 cycle dead zone +… + 8 + 8 + read-write + + + DZ_P + Exc_p dead zone in clock cycle before swap +0: no dead zone +1: 1 cycle dead zone +2: 2 cycle dead zone +… + 0 + 8 + read-write + + + + + sync_out_ctrl + synchronize output signal control + 0x54 + 32 + 0x00000000 + 0xFFFF0033 + + + PWM_OUT_DLY + Delay bettween the delyed trigger and the first pwm pulse in clock cycle +1: 1 cycle +2: 2 cycle +… + 16 + 16 + read-only + + + MIN2TRIG_EN + Enable trigger out from the min point of exciting signal +1: enable +0: disable + 5 + 1 + read-write + + + MAX2TRIG_EN + Enable trigger out from the max point of exciting signal +1: enable +0: disable + 4 + 1 + read-write + + + SYNC_OUT_SEL + Select output synchornize signal +0: 0 phase of internal exciting signal +1: 90 phase of internal exciting signal +2: 180 phase of internal exciting signal +3: 270 phase of internal exciting signal + 0 + 2 + read-write + + + + + exc_sync_dly + trigger in delay timming in soc bus cycle + 0x58 + 32 + 0x01000001 + 0x01FFFFFF + + + DISABLE + Disable hardware trigger input +0: enable +1: disable + 24 + 1 + read-write + + + DELAY + Trigger in delay timming in bus cycle from rising edge of trigger signal +0: 1 cycle +1: 2 cycle +… +0xffffff: 2^24 cycle + 0 + 24 + read-write + + + + + max_i + max value of i_channel + 0x70 + 32 + 0x00000000 + 0xFFFFFF01 + + + MAX + Max value of i_channel, write clear + 8 + 24 + read-write + + + VALID + Max value valid, write clear +0: max value is not valid +1: max value is valid + 0 + 1 + read-write + + + + + min_i + min value of i_channel + 0x74 + 32 + 0x00000000 + 0xFFFFFF01 + + + MIN + Min value of i_channel, write clear + 8 + 24 + read-write + + + VALID + Min value valid, write clear +0: min value is not valid +1: min value is valid + 0 + 1 + read-write + + + + + max_q + max value of q_channel + 0x78 + 32 + 0x00000000 + 0xFFFFFF01 + + + MAX + Max value of q_channel, write clear + 8 + 24 + read-write + + + VALID + Max value valid, write clear +0: max value is not valid +1: max value is valid + 0 + 1 + read-write + + + + + min_q + min value of q_channel + 0x7c + 32 + 0x00000000 + 0xFFFFFF01 + + + MIN + Min value of q_channel, write clear + 8 + 24 + read-write + + + VALID + Min value valid, write clear +0: min value is not valid +1: min value is valid + 0 + 1 + read-write + + + + + thrs_i + the offset setting for edge detection of the i_channel + 0x80 + 32 + 0x00000000 + 0xFFFFFF00 + + + THRS + The offset setting for edge detection of the i_channel, signed number +… +2: the offset is 0x800000+2 +1: the offset is 0x800000+1 +0: the offset is 0x800000 +-1: the offset is 0x800000-1 +-2: the offset is 0x800000-2 +… + 8 + 24 + read-write + + + + + thrs_q + the offset setting for edge detection of the q_channel + 0x84 + 32 + 0x00000000 + 0xFFFFFF00 + + + THRS + The offset setting for edge detection of the q_channel, signed number +… +2: the offset is 0x800000+2 +1: the offset is 0x800000+1 +0: the offset is 0x800000 +-1: the offset is 0x800000-1 +-2: the offset is 0x800000-2 +… + 8 + 24 + read-write + + + + + edg_det_ctl + the control for edge detection + 0x88 + 32 + 0x00000080 + 0x000003F7 + + + HOLD + The minimum edge distance in sample +0:1 sample +1:2 sample +2:3 samples +… +63:64 samples + 4 + 6 + read-write + + + FILTER + The continuous positive or negative number for edge detection +0: 1 +1: 2 +… +7: 8 + 0 + 3 + read-write + + + + + acc_scaling + scaling for accumulation result + 0x8c + 32 + 0x00000000 + 0x0000010F + + + TOXIC_LK + Toxic accumulation data be removed control +1: enable +0: disable + 8 + 1 + read-write + + + ACC_SHIFT + Accumulation value shift control, this is a sign number. +0: {acc[39],acc[38:8]} +1: {acc[39],acc[37:7]} +2: {acc[39],acc[36:6]} +… +7: {acc[39],acc[31:1]} +8: {acc[39],acc[30:0]} +9: acc/2^9 +10: acc/2^10 +… +15:acc/2^15 + 0 + 4 + read-write + + + + + exc_period + period of excitation + 0x90 + 32 + 0x00001770 + 0xFFFFFFFF + + + EXC_PERIOD + The num in clock cycle for period of excitation +0: invalid value +1:1 cycle +2:2 cycles +… + 0 + 32 + read-write + + + + + sync_delay_i + delay setting in clock cycle for synchronous signal + 0xa0 + 32 + 0x00000008 + 0xFFFFFFFF + + + DELAY + Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. +0: invalid value +1: 1 cycles +2: 2 cycles +... + 0 + 32 + read-write + + + + + rise_delay_i + delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data + 0xa8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RISE_DELAY + Delay value on rising edge of i_channel data +0: 1 cycle +1: 2 cycles +… + 0 + 32 + read-only + + + + + fall_delay_i + delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data + 0xac + 32 + 0x00000000 + 0xFFFFFFFF + + + FALL_DELAY + Delay value on falling edge of i_channel data +0: 1 cycle +1: 2 cycles +… + 0 + 32 + read-only + + + + + sample_rise_i + sample value on rising edge of rectify signal + 0xb0 + 32 + 0x00000000 + 0xFFFFFF00 + + + VALUE + sample value on rising edge of rectify signal + 8 + 24 + read-only + + + + + sample_fall_i + sample value on falling edge of rectify signal + 0xb4 + 32 + 0x00000000 + 0xFFFFFF00 + + + VALUE + sample value on falling edge of rectify signal + 8 + 24 + read-only + + + + + acc_cnt_i + number of accumulation + 0xb8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT_NEG + sample number during the negtive of rectify signal +1: 1 +2: 2 +… + 16 + 16 + read-only + + + CNT_POS + sample number during the positive of rectify signal +1: 1 +2: 2 +… + 0 + 16 + read-only + + + + + sign_cnt_i + sample counter of opposite sign with rectify signal + 0xbc + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT_NEG + Positive sample counter during negative rectify signal + 16 + 16 + read-only + + + CNT_POS + Negative sample counter during positive rectify signal + 0 + 16 + read-only + + + + + sync_delay_q + delay setting in clock cycle for synchronous signal + 0xc0 + 32 + 0x00000008 + 0xFFFFFFFF + + + DELAY + Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. +0: invalid value +1: 1 cycles +2: 2 cycles +... + 0 + 32 + read-write + + + + + rise_delay_q + delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data + 0xc8 + 32 + 0x00000000 + 0xFFFFFFFF + + + RISE_DELAY + Delay value on rising edge of q_channel data +0: 1 cycle +1: 2 cycles +… + 0 + 32 + read-only + + + + + fall_delay_q + delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + FALL_DELAY + Delay value on falling edge of q_channel data +0: 1 cycle +1: 2 cycles +… + 0 + 32 + read-only + + + + + sample_rise_q + sample value on rising edge of rectify signal + 0xd0 + 32 + 0x00000000 + 0xFFFFFF00 + + + VALUE + sample value on rising edge of rectify signal + 8 + 24 + read-only + + + + + sample_fall_q + sample value on falling edge of rectify signal + 0xd4 + 32 + 0x00000000 + 0xFFFFFF00 + + + VALUE + sample value on falling edge of rectify signal + 8 + 24 + read-only + + + + + acc_cnt_q + number of accumulation + 0xd8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT_NEG + sample number during the negtive of rectify signal +1: 1 +2: 2 +… + 16 + 16 + read-only + + + CNT_POS + sample number during the positive of rectify signal +1: 1 +2: 2 +… + 0 + 16 + read-only + + + + + sign_cnt_q + sample counter of opposite sign with rectify signal + 0xdc + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT_NEG + Positive sample counter during negative rectify signal + 16 + 16 + read-only + + + CNT_POS + Negative sample counter during positive rectify signal + 0 + 16 + read-only + + + + + amp_max + the maximum of acc amplitude + 0xe0 + 32 + 0x01000000 + 0xFFFFFFFF + + + MAX + the maximum of acc amplitude + 0 + 32 + read-write + + + + + amp_min + the minimum of acc amplitude + 0xe4 + 32 + 0x00400000 + 0xFFFFFFFF + + + MIN + the minimum of acc amplitude + 0 + 32 + read-write + + + + + int_en + the interrupt mask control + 0xe8 + 32 + 0x00000000 + 0x8000FFFF + + + INT_EN + enable interrupt output + 31 + 1 + read-write + + + ACC_VLD_I_EN + i_channel accumulate valid interrupt enable for i_channel + 15 + 1 + read-write + + + ACC_VLD_Q_EN + q_channel accumulate valid interrupt enable for i_channel + 14 + 1 + read-write + + + RISING_DELAY_I_EN + i_channel delayed rectify signal rising edge interrupt enable + 13 + 1 + read-write + + + FALLING_DELAY_I_EN + i_channel delayed rectify signal falling edge interrupt enable + 12 + 1 + read-write + + + RISING_DELAY_Q_EN + q_channel delayed rectify signal rising edge interrupt enable + 11 + 1 + read-write + + + FALLING_DELAY_Q_EN + q_channel delayed rectify signal falling edge interrupt enable + 10 + 1 + read-write + + + SAMPLE_RISING_I_EN + i_channel rising edge interrupt enable + 9 + 1 + read-write + + + SAMPLE_FALLING_I_EN + i_channel falling edge interrupt enable + 8 + 1 + read-write + + + SAMPLE_RISING_Q_EN + q_channel rising edge interrupt enable + 7 + 1 + read-write + + + SAMPLE_FALLING_Q_EN + q_channel falling edge interrupt enable + 6 + 1 + read-write + + + ACC_VLD_I_OVH_EN + i_channel accumulate overflow interrupt enable + 5 + 1 + read-write + + + ACC_VLD_Q_OVH_EN + q_channel accumulate overflow interrupt enable + 4 + 1 + read-write + + + ACC_VLD_I_OVL_EN + i_channel accumulate underflow interrupt enable + 3 + 1 + read-write + + + ACC_VLD_Q_OVL_EN + q_channel accumulate underflow interrupt enable + 2 + 1 + read-write + + + ACC_AMP_OVH_EN + accumulate ample overflow interrupt enable + 1 + 1 + read-write + + + ACC_AMP_OVL_EN + accumulate ample underflow interrupt enable + 0 + 1 + read-write + + + + + adc_int_state + the interrupt state + 0xec + 32 + 0x00000000 + 0x0000FFFF + + + ACC_VLD_I_STA + i_channel accumulate valid interrupt status for i_channel + 15 + 1 + write-only + + + ACC_VLD_Q_STA + q_channel accumulate valid interrupt status for i_channel + 14 + 1 + write-only + + + RISING_DELAY_I_STA + i_channel delayed rectify signal rising edge interrupt status + 13 + 1 + write-only + + + FALLING_DELAY_I_STA + i_channel delayed rectify signal falling edge interrupt status + 12 + 1 + write-only + + + RISING_DELAY_Q_STA + q_channel delayed rectify signal rising edge interrupt status + 11 + 1 + write-only + + + FALLING_DELAY_Q_STA + q_channel delayed rectify signal falling edge interrupt status + 10 + 1 + write-only + + + SAMPLE_RISING_I_STA + i_channel rising edge interrupt status + 9 + 1 + write-only + + + SAMPLE_FALLING_I_STA + i_channel falling edge interrupt status + 8 + 1 + write-only + + + SAMPLE_RISING_Q_STA + q_channel rising edge interrupt status + 7 + 1 + write-only + + + SAMPLE_FALLING_Q_STA + q_channel falling edge interrupt status + 6 + 1 + write-only + + + ACC_VLD_I_OVH_STA + i_channel accumulate overflow interrupt status + 5 + 1 + write-only + + + ACC_VLD_Q_OVH_STA + q_channel accumulate overflow interrupt status + 4 + 1 + write-only + + + ACC_VLD_I_OVL_STA + i_channel accumulate underflow interrupt status + 3 + 1 + write-only + + + ACC_VLD_Q_OVL_STA + q_channel accumulate underflow interrupt status + 2 + 1 + write-only + + + ACC_AMP_OVH_STA + accumulate ample overflow interrupt status + 1 + 1 + write-only + + + ACC_AMP_OVL_STA + accumulate ample underflow interrupt status + 0 + 1 + write-only + + + + + + + PLB + PLB + PLB + 0xf0324000 + + 0x0 + 0x480 + registers + + + + 4 + 0x20 + 0,1,2,3 + TYPE_A[%s] + no description available + 0x0 + + 4 + 0x4 + 0,1,2,3 + LOOKUP_TABLE[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x0000FFFF + + + LOOKUP_TABLE + using 4 bit trig_in as lookup index. software can program this register as trig_in's true table. + 0 + 16 + read-write + + + + + sw_inject + TYPE A CHN&index0 software inject + 0x10 + 32 + 0x00000000 + 0x0000000F + + + SW_INJECT + software can inject value to TYPEA's output + 0 + 4 + read-write + + + + + + 4 + 0x20 + 0,1,2,3 + TYPE_B[%s] + no description available + 0x400 + + 2 + 0x4 + 0,1 + LUT[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOOKUP_TABLE + lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in + 0 + 32 + read-write + + + + + 4 + 0x4 + 0,1,2,3 + CMP[%s] + no description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP_VALUE + cmp value, using as data unit operation + 0 + 32 + read-write + + + + + mode + TYPE B CHN&index0 mode ctrl + 0x18 + 32 + 0x00000000 + 0x0001FFFF + + + OPT_SEL + operation selection in data unit. + 16 + 1 + read-write + + + OUT3_SEL + trig out 3 output type in current channel + 12 + 4 + read-write + + + OUT2_SEL + trig out 2 output type in current channel + 8 + 4 + read-write + + + OUT1_SEL + trig out 1 output type in current channel + 4 + 4 + read-write + + + OUT0_SEL + trig out 0 output type in current channel + 0 + 4 + read-write + + + + + sw_inject + TYPE B CHN&index0 software inject + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + SOFTWARE_INJECT + data unit value can be changed if program this register + 0 + 32 + read-write + + + + + + + + SYNT + SYNT + SYNT + 0xf0328000 + + 0x0 + 0x30 + registers + + + + gcr + Global control register + 0x0 + 32 + 0x00000000 + 0xF0000037 + + + TIMESTAMP_INC_NEW + set to increase the timesamp with new value, auto clr + 31 + 1 + write-only + + + TIMESTAMP_DEC_NEW + set to decrease the timesamp with new value, auto clr + 30 + 1 + write-only + + + TIMESTAMP_SET_NEW + set the timesamp to new value, auto clr + 29 + 1 + write-only + + + TIMESTAMP_RESET + reset timesamp to 0, auto clr + 28 + 1 + write-only + + + TIMESTAMP_DEBUG_EN + set to enable cpu_debug_mode to stop the timesamp + 5 + 1 + read-write + + + TIMESTAMP_ENABLE + set to enable the timesamp , clr to stop + 4 + 1 + read-write + + + COUNTER_DEBUG_EN + set to enable cpu_debug_mode to stop the counter + 2 + 1 + read-write + + + CRST + 1- Reset counter + 1 + 1 + read-write + + + CEN + 1- Enable counter + 0 + 1 + read-write + + + + + rld + Counter reload register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + RLD + counter reload value + 0 + 32 + read-write + + + + + timestamp_new + timestamp new value register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + VALUE + new value for timesamp , can be used as set/inc/dec + 0 + 32 + read-write + + + + + cnt + Counter + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CNT + counter + 0 + 32 + read-only + + + + + timestamp_sav + timestamp trig save value + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + VALUE + use the trigger to save timesamp here + 0 + 32 + read-only + + + + + timestamp_cur + timestamp read value + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + VALUE + current timesamp value + 0 + 32 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + CMP[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMP + comparator value, the output will assert when counter count to this value + 0 + 32 + read-write + + + + + + + SEI + SEI + SEI + 0xf032c000 + + 0x0 + 0x3a80 + registers + + + + 2 + 0x400 + 0,1 + CTRL[%s] + no description available + 0x0 + + CTRL + Engine control register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + WATCH + Enable watch dog +0: Watch dog disabled +1: Watch dog enabled + 24 + 1 + read-write + + + ARMING + Wait for trigger before excuting +0: Execute on enable +1: Wait trigger before exection after enabled + 16 + 1 + read-write + + + EXCEPT + Explain timout as exception +0: when timeout, pointer move to next instruction +1: when timeout, pointer jump to timeout vector + 8 + 1 + read-write + + + REWIND + Rewind execution pointer +0: run +1: clean status and rewind + 4 + 1 + read-write + + + ENABLE + Enable +0: disable +1: enable + 0 + 1 + read-write + + + + + PTR_CFG + Pointer configuration register + 0x4 + 32 + 0x00000000 + 0xFF1FFFFF + + + DAT_CDM + Select DATA register to receive CDM bit in BiSSC slave mode +0: ignore +1: command +2: data register 2 +3: data register 3 +... +29:data register 29 +30: value 0 when send, ignore in receive +31: value1 when send, ignore in receive + 24 + 5 + read-write + + + DAT_BASE + Bias for data register access, if calculated index bigger than 32, index will wrap around +0: real data index +1: access index is 1 greater than instruction address +2: access index is 2 greater than instruction address +... +31: access index is 31 greater than instruction address + 16 + 5 + read-write + + + POINTER_WDOG + Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME + 8 + 8 + read-write + + + POINTER_INIT + Initial execute pointer + 0 + 8 + read-write + + + + + WDG_CFG + Watch dog configuration register + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + WDOG_TIME + Time out count for each instruction, counter in bit time. + 0 + 16 + read-write + + + + + EXE_STA + Execution status + 0x10 + 32 + 0x00000000 + 0x00110101 + + + TRIGERED + Execution has been triggered +0: Execution not triggered +1: Execution triggered + 20 + 1 + read-only + + + ARMED + Waiting for trigger for execution +0: Not in waiting status +1: In waiting status + 16 + 1 + read-only + + + EXPIRE + Watchdog timer expired +0: Not expired +1: Expired + 8 + 1 + read-only + + + STALL + Program finished +0: Program is executing +1: Program finished + 0 + 1 + read-only + + + + + EXE_PTR + Execution pointer + 0x14 + 32 + 0x00000000 + 0x1F1F00FF + + + HALT_CNT + Halt count in halt instrution + 24 + 5 + read-only + + + BIT_CNT + Bit count in send and receive instruction execution + 16 + 5 + read-only + + + POINTER + Current program pointer + 0 + 8 + read-only + + + + + EXE_INST + Execution instruction + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + INST + Current instruction + 0 + 32 + read-only + + + + + WDG_STA + Watch dog status + 0x1c + 32 + 0x00000000 + 0x0000FFFF + + + WDOG_CNT + Current watch dog counter value + 0 + 16 + read-only + + + + + CTRL + Transceiver control register + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRISMP + Tipple sampe +0: sample 1 time for data transition +1: sample 3 times in receive and result in 2oo3 + 12 + 1 + read-write + + + PAR_CLR + Clear parity error, this is a self clear bit +0: no effect +1: clear parity error + 8 + 1 + write-only + + + RESTART + Restart tranceiver, this is a self clear bit +0: no effect +1: reset tranceiver + 4 + 1 + write-only + + + MODE + Tranceiver mode +0: synchronous maaster +1: synchronous slave +2: asynchronous mode +3: asynchronous mode + 0 + 2 + read-write + + + + + TYPE_CFG + Transceiver configuration register + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + WAIT_LEN + Number of extra stop bit for asynchronous mode +0: 1 bit +1: 2 bit +... +255: 256 bit + 24 + 8 + read-write + + + DATA_LEN + Number of data bit for asynchronous mode +0: 1 bit +1: 2 bit +... +31: 32 bit + 16 + 5 + read-write + + + PAR_POL + Polarity of parity for asynchronous mode +0: even +1: odd + 9 + 1 + read-write + + + PAR_EN + enable parity check for asynchronous mode +0: disable +1: enable + 8 + 1 + read-write + + + DA_IDLEZ + Idle state driver of data line +0: output +1: high-Z + 3 + 1 + read-write + + + CK_IDLEZ + Idle state driver of clock line +0: output +1: high-Z + 2 + 1 + read-write + + + DA_IDLEV + Idle state value of data line +0: data'0' +1: data'1' + 1 + 1 + read-write + + + CK_IDLEV + Idle state value of clock line +0: data'0' +1: data'1' + 0 + 1 + read-write + + + + + BAUD_CFG + Transceiver baud rate register + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + SYNC_POINT + Baud synchronous time, minmum bit time + 16 + 16 + read-write + + + BAUD_DIV + Baud rate, bit time in system clock cycle + 0 + 16 + read-write + + + + + DATA_CFG + Transceiver data timing configuration + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + TXD_POINT + data transmit point in system clcok cycle + 16 + 16 + read-write + + + RXD_POINT + data receive point in system clcok cycle + 0 + 16 + read-write + + + + + CLK_CFG + Transceiver clock timing configuration + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + CK1_POINT + clock point 1 in system clcok cycle + 16 + 16 + read-write + + + CK0_POINT + clock point 0 in system clcok cycle + 0 + 16 + read-write + + + + + PIN + Transceiver pin status + 0x38 + 32 + 0x00000000 + 0x07070707 + + + OE_CK + CK drive state +0: input +1: output + 26 + 1 + read-only + + + DI_CK + CK state +0: data 0 +1: data 1 + 25 + 1 + read-only + + + DO_CK + CK output +0: data 0 +1: data 1 + 24 + 1 + read-only + + + OE_RX + RX drive state +0: input +1: output + 18 + 1 + read-only + + + DI_RX + RX state +0: data 0 +1: data 1 + 17 + 1 + read-only + + + DO_RX + RX output +0: data 0 +1: data 1 + 16 + 1 + read-only + + + OE_DE + DE drive state +0: input +1: output + 10 + 1 + read-only + + + DI_DE + DE state +0: data 0 +1: data 1 + 9 + 1 + read-only + + + DO_DE + DE output +0: data 0 +1: data 1 + 8 + 1 + read-only + + + OE_TX + TX drive state +0: input +1: output + 2 + 1 + read-only + + + DI_TX + TX state +0: data 0 +1: data 1 + 1 + 1 + read-only + + + DO_TX + TX output +0: data 0 +1: data 1 + 0 + 1 + read-only + + + + + STATE + FSM of asynchronous + 0x3c + 32 + 0x00000000 + 0x07070000 + + + RECV_STATE + FSM of asynchronous receive + 24 + 3 + read-only + + + SEND_STATE + FSM of asynchronous transmit + 16 + 3 + read-only + + + + + IN_CFG + Trigger input configuration + 0x40 + 32 + 0x00000000 + 0x00878787 + + + PRD_EN + Enable period trigger (tigger 2) +0: periodical trigger disabled +1: periodical trigger enabled + 23 + 1 + read-write + + + SYNC_SEL + Synchronize sigal selection (tigger 2) +0: trigger in 0 +1: trigger in 1 +... +7: trigger in 7 + 16 + 3 + read-write + + + IN1_EN + Enable trigger 1 +0: disable trigger 1 +1: enable trigger 1 + 15 + 1 + read-write + + + IN1_SEL + Trigger 1 sigal selection +0: trigger in 0 +1: trigger in 1 +... +7: trigger in 7 + 8 + 3 + read-write + + + IN0_EN + Enable trigger 0 +0: disable trigger 1 +1: enable trigger 1 + 7 + 1 + read-write + + + IN0_SEL + Trigger 0 sigal selection +0: trigger in 0 +1: trigger in 1 +... +7: trigger in 7 + 0 + 3 + read-write + + + + + SW + Software trigger + 0x44 + 32 + 0x00000000 + 0x00000001 + + + SOFT + Software trigger (tigger 3). this bit is self-clear +0: trigger source disabled +1: trigger source enabled + 0 + 1 + write-only + + + + + PRD_CFG + Period trigger configuration + 0x48 + 32 + 0x00000000 + 0xFFFF0001 + + + ARMING + Wait for trigger synchronous before trigger +0: Trigger directly +1: Wait trigger source before period trigger + 16 + 1 + read-write + + + SYNC + Synchronous +0: Not synchronous +1: Synchronous every trigger source + 0 + 1 + read-write + + + + + PRD + Trigger period + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + PERIOD + Trigger period + 0 + 32 + read-write + + + + + OUT_CFG + Trigger output configuration + 0x50 + 32 + 0x00000000 + 0x87878787 + + + OUT3_EN + Enable trigger 3 +0: disable trigger 3 +1: enable trigger 3 + 31 + 1 + read-write + + + OUT3_SEL + Trigger 3 sigal selection +0: trigger out 0 +1: trigger out 1 +... +7: trigger out 7 + 24 + 3 + read-write + + + OUT2_EN + Enable trigger 2 +0: disable trigger 2 +1: enable trigger 2 + 23 + 1 + read-write + + + OUT2_SEL + Trigger 2 sigal selection +0: trigger out 0 +1: trigger out 1 +... +7: trigger out 7 + 16 + 3 + read-write + + + OUT1_EN + Enable trigger 1 +0: disable trigger 1 +1: enable trigger 1 + 15 + 1 + read-write + + + OUT1_SEL + Trigger 1 sigal selection +0: trigger out 0 +1: trigger out 1 +... +7: trigger out 7 + 8 + 3 + read-write + + + OUT0_EN + Enable trigger 0 +0: disable trigger 1 +1: enable trigger 1 + 7 + 1 + read-write + + + OUT0_SEL + Trigger 0 sigal selection +0: trigger out 0 +1: trigger out 1 +... +7: trigger out 7 + 0 + 3 + read-write + + + + + PRD_STS + Period trigger status + 0x60 + 32 + 0x00000000 + 0x00110000 + + + TRIGERED + Period has been triggered +0: Not triggered +1: Triggered + 20 + 1 + read-only + + + ARMED + Waiting for trigger +0: Not in waiting status +1: In waiting status + 16 + 1 + read-only + + + + + PRD_CNT + Period trigger counter + 0x64 + 32 + 0x00000000 + 0xFFFFFFFF + + + PERIOD_CNT + Trigger period counter + 0 + 32 + read-only + + + + + 4 + 0x4 + 0,1,2,3 + CMD[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_TRIGGER0 + Trigger command + 0 + 32 + read-write + + + + + 4 + 0x4 + 0,1,2,3 + TIME[%s] + no description available + 0xa0 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRIGGER0_TIME + Trigger time + 0 + 32 + read-only + + + + + MODE + command register mode + 0xc0 + 32 + 0x00000000 + 0xE0FFCFFF + + + WLEN + word length +0: 1 bit +1: 2 bit +... +31: 32 bit + 16 + 5 + read-write + + + WORDER + word order +0: sample as bit order +1: different from bit order + 11 + 1 + read-write + + + BORDER + bit order +0: LSB first +1: MSB first + 10 + 1 + read-write + + + SIGNED + Signed +0: unsigned value +1: signed value + 9 + 1 + read-write + + + REWIND + Write 1 to rewind read/write pointer, this is a self clear bit + 8 + 1 + write-only + + + MODE + Data mode +0: data mode +1: check mode +2: CRC mode + 0 + 2 + read-write + + + + + IDX + command register configuration + 0xc4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LAST_BIT + Last bit index for tranceive + 24 + 5 + read-write + + + FIRST_BIT + First bit index for tranceive + 16 + 5 + read-write + + + MAX_BIT + Highest bit index + 8 + 5 + read-write + + + MIN_BIT + Lowest bit index + 0 + 5 + read-write + + + + + GOLD + Command gold value + 0xc8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GOLD_VALUE + Gold value for check mode + 0 + 32 + read-write + + + + + CRCINIT + Command Initial value + 0xcc + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC_INIT + CRC initial value + 0 + 32 + read-write + + + + + CRCPOLY + Command CRC polymial + 0xd0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC_POLY + CRC polymonial + 0 + 32 + read-write + + + + + CMD + command + 0xe0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + DATA + 0 + 32 + read-write + + + + + SET + command bit set register + 0xe4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_SET + DATA bit set + 0 + 32 + read-write + + + + + CLR + command bit clear register + 0xe8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_CLR + DATA bit clear + 0 + 32 + read-write + + + + + INV + command bit invert register + 0xec + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_TGL + DATA bit toggle + 0 + 32 + read-write + + + + + IN + Commad input + 0xf0 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_IN + Commad input + 0 + 32 + read-only + + + + + OUT + Command output + 0xf4 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_OUT + Command output + 0 + 32 + read-only + + + + + STS + Command status + 0xf8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC_IDX + CRC index + 24 + 5 + read-only + + + WORD_IDX + Word index + 16 + 5 + read-only + + + WORD_CNT + Word counter + 8 + 5 + read-only + + + BIT_IDX + Bit index + 0 + 5 + read-only + + + + + 8 + 0x20 + 0,1,2,3,4,5,6,7 + CMD_TABLE[%s] + no description available + 0x100 + + MIN + command start value + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_MIN + minimum command value + 0 + 32 + read-write + + + + + MAX + command end value + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_MAX + maximum command value + 0 + 32 + read-write + + + + + MSK + command compare bit enable + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD_MASK + compare mask + 0 + 32 + read-write + + + + + PTA + command pointer 0 - 3 + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR3 + pointer3 + 24 + 8 + read-write + + + PTR2 + pointer2 + 16 + 8 + read-write + + + PTR1 + pointer1 + 8 + 8 + read-write + + + PTR0 + pointer0 + 0 + 8 + read-write + + + + + PTB + command pointer 4 - 7 + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + PTR7 + pointer7 + 24 + 8 + read-write + + + PTR6 + pointer6 + 16 + 8 + read-write + + + PTR5 + pointer5 + 8 + 8 + read-write + + + PTR4 + pointer4 + 0 + 8 + read-write + + + + + + 4 + 0x20 + 0,1,2,3 + LATCH[%s] + no description available + 0x200 + + 4 + 0x4 + 0_1,1_2,2_3,3_0 + TRAN[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFF0F3FF7 + + + POINTER + pointer + 24 + 8 + read-write + + + CFG_TM + timeout +0: high +1: low +2: rise +3: fall + 16 + 2 + read-write + + + CFG_TXD + data send +0: high +1: low +2: rise +3: fall + 12 + 2 + read-write + + + CFG_CLK + clock +0: high +1: low +2: rise +3: fall + 10 + 2 + read-write + + + CFG_PTR + pointer +0: match +1: not match +2:entry +3:leave + 8 + 2 + read-write + + + OV_TM + override timeout check + 4 + 1 + read-write + + + OV_TXD + override TX data check + 2 + 1 + read-write + + + OV_CLK + override clock check + 1 + 1 + read-write + + + OV_PTR + override pointer check + 0 + 1 + read-write + + + + + CFG + Latch configuration + 0x10 + 32 + 0x00000000 + 0x8700FFFF + + + EN + Enable latch +0: disable +1: enable + 31 + 1 + read-write + + + SELECT + Output select +0: state0-state1 +1: state1-state2 +2: state2-state3 +3: state3-state0 + 24 + 3 + read-write + + + DELAY + Delay in system clock cycle, for state transition + 0 + 16 + read-write + + + + + TIME + Latch time + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + LAT_TIME + Latch time + 0 + 32 + read-only + + + + + STS + Latch status + 0x1c + 32 + 0x00000000 + 0x0700FFFF + + + STATE + State + 24 + 3 + read-only + + + LAT_CNT + Latch counter + 0 + 16 + read-only + + + + + + SMP_EN + Sample selection register + 0x280 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC_EN + Position include acceleration + 31 + 1 + read-write + + + ACC_SEL + Data register for acceleration transfer + 24 + 5 + read-write + + + SPD_EN + Position include speed + 23 + 1 + read-write + + + SPD_SEL + Data register for speed transfer + 16 + 5 + read-write + + + REV_EN + Position include revolution + 15 + 1 + read-write + + + REV_SEL + Data register for revolution transfer + 8 + 5 + read-write + + + POS_EN + Position include position + 7 + 1 + read-write + + + POS_SEL + Data register for position transfer + 0 + 5 + read-write + + + + + SMP_CFG + Sample configuration + 0x284 + 32 + 0x00000000 + 0x0103FFFF + + + ONCE + Sample one time +0: Sample during windows time +1: Close sample window after first sample + 24 + 1 + read-write + + + LAT_SEL + Latch selection +0: latch 0 +1: latch 1 +2: latch 2 +3: latch 3 + 16 + 2 + read-write + + + WINDOW + Sample window, in clock cycle + 0 + 16 + read-write + + + + + SMP_DAT + Sample data + 0x288 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT_SEL + Data register sampled, each bit represent a data register + 0 + 32 + read-write + + + + + SMP_POS + Sample override position + 0x290 + 32 + 0x00000000 + 0xFFFFFFFF + + + POS + Sample override position + 0 + 32 + read-write + + + + + SMP_REV + Sample override revolution + 0x294 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV + Sample override revolution + 0 + 32 + read-write + + + + + SMP_SPD + Sample override speed + 0x298 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPD + Sample override speed + 0 + 32 + read-write + + + + + SMP_ACC + Sample override accelerate + 0x29c + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC + Sample override accelerate + 0 + 32 + read-write + + + + + UPD_EN + Update configuration + 0x2a0 + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC_EN + Position include acceleration + 31 + 1 + read-write + + + ACC_SEL + Data register for acceleration transfer + 24 + 5 + read-write + + + SPD_EN + Position include speed + 23 + 1 + read-write + + + SPD_SEL + Data register for speed transfer + 16 + 5 + read-write + + + REV_EN + Position include revolution + 15 + 1 + read-write + + + REV_SEL + Data register for revolution transfer + 8 + 5 + read-write + + + POS_EN + Position include position + 7 + 1 + read-write + + + POS_SEL + Data register for position transfer + 0 + 5 + read-write + + + + + UPD_CFG + Update configuration + 0x2a4 + 32 + 0x00000000 + 0x81030000 + + + TIME_OVRD + Use override time +0: use time sample from motor group +1: use override time + 31 + 1 + read-write + + + ONERR + Sample one time +0: Sample during windows time +1: Close sample window after first sample + 24 + 1 + read-write + + + LAT_SEL + Latch selection +0: latch 0 +1: latch 1 +2: latch 2 +3: latch 3 + 16 + 2 + read-write + + + + + UPD_DAT + Update data + 0x2a8 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAT_SEL + Data register sampled, each bit represent a data register + 0 + 32 + read-write + + + + + UPD_TIME + Update overide time + 0x2ac + 32 + 0x00000000 + 0xFFFFFFFF + + + TIME + Update override time + 0 + 32 + read-write + + + + + UPD_POS + Update override position + 0x2b0 + 32 + 0x00000000 + 0xFFFFFFFF + + + POS + Update override position + 0 + 32 + read-write + + + + + UPD_REV + Update override revolution + 0x2b4 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV + Update override revolution + 0 + 32 + read-write + + + + + UPD_SPD + Update override speed + 0x2b8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPD + Update override speed + 0 + 32 + read-write + + + + + UPD_ACC + Update override accelerate + 0x2bc + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC + Update override accelerate + 0 + 32 + read-write + + + + + SMP_VAL + Sample valid + 0x2c0 + 32 + 0x00000000 + 0x80808080 + + + ACC + Position include acceleration + 31 + 1 + read-only + + + SPD + Position include speed + 23 + 1 + read-only + + + REV + Position include revolution + 15 + 1 + read-only + + + POS + Position include position + 7 + 1 + read-only + + + + + SMP_STS + Sample status + 0x2c4 + 32 + 0x00000000 + 0x0100FFFF + + + OCCUR + Sample occured +0: Sample not happened +1: Sample occured + 24 + 1 + read-only + + + WIN_CNT + Sample window counter + 0 + 16 + read-only + + + + + TIME_IN + input time + 0x2cc + 32 + 0x00000000 + 0xFFFFFFFF + + + TIME + input time + 0 + 32 + read-only + + + + + POS_IN + Input position + 0x2d0 + 32 + 0x00000000 + 0xFFFFFFFF + + + POS + Input position + 0 + 32 + read-only + + + + + REV_IN + Input revolution + 0x2d4 + 32 + 0x00000000 + 0xFFFFFFFF + + + REV + Input revolution + 0 + 32 + read-only + + + + + SPD_IN + Input speed + 0x2d8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SPD + Input speed + 0 + 32 + read-only + + + + + ACC_IN + Input accelerate + 0x2dc + 32 + 0x00000000 + 0xFFFFFFFF + + + ACC + Input accelerate + 0 + 32 + read-only + + + + + UPD_STS + Update status + 0x2e4 + 32 + 0x00000000 + 0x01000000 + + + UPD_ERR + Update error +0: data receive normally +1: data receive error + 24 + 1 + read-only + + + + + INT_EN + Interrupt Enable + 0x300 + 32 + 0x00000000 + 0xFF1F3FF7 + + + TRG_ERR3 + Trigger3 failed + 31 + 1 + read-write + + + TRG_ERR2 + Trigger2 failed + 30 + 1 + read-write + + + TRG_ERR1 + Trigger1 failed + 29 + 1 + read-write + + + TRG_ERR0 + Trigger0 failed + 28 + 1 + read-write + + + TRIGER3 + Trigger3 + 27 + 1 + read-write + + + TRIGER2 + Trigger2 + 26 + 1 + read-write + + + TRIGER1 + Trigger1 + 25 + 1 + read-write + + + TRIGER0 + Trigger0 + 24 + 1 + read-write + + + SMP_ERR + Sample error + 20 + 1 + read-write + + + LATCH3 + Latch3 + 19 + 1 + read-write + + + LATCH2 + Latch2 + 18 + 1 + read-write + + + LATCH1 + Latch1 + 17 + 1 + read-write + + + LATCH0 + Latch0 + 16 + 1 + read-write + + + TIMEOUT + Timeout + 13 + 1 + read-write + + + TRX_ERR + Transfer error + 12 + 1 + read-write + + + INSTR1_END + Instruction 1 end + 11 + 1 + read-write + + + INSTR0_END + Instruction 0 end + 10 + 1 + read-write + + + PTR1_END + Pointer 1 end + 9 + 1 + read-write + + + PTR0_END + Pointer 0 end + 8 + 1 + read-write + + + INSTR1_ST + Instruction 1 start + 7 + 1 + read-write + + + INSTR0_ST + Instruction 0 start + 6 + 1 + read-write + + + PTR1_ST + Pointer 1 start + 5 + 1 + read-write + + + PTR0_ST + Pointer 0 start + 4 + 1 + read-write + + + WDOG + Watch dog + 2 + 1 + read-write + + + EXECPT + Exception + 1 + 1 + read-write + + + STALL + Stall + 0 + 1 + read-write + + + + + INT_FLAG + Interrupt flag + 0x304 + 32 + 0x00000000 + 0xFF1F3FF7 + + + TRG_ERR3 + Trigger3 failed + 31 + 1 + write-only + + + TRG_ERR2 + Trigger2 failed + 30 + 1 + write-only + + + TRG_ERR1 + Trigger1 failed + 29 + 1 + write-only + + + TRG_ERR0 + Trigger0 failed + 28 + 1 + write-only + + + TRIGER3 + Trigger3 + 27 + 1 + write-only + + + TRIGER2 + Trigger2 + 26 + 1 + write-only + + + TRIGER1 + Trigger1 + 25 + 1 + write-only + + + TRIGER0 + Trigger0 + 24 + 1 + write-only + + + SMP_ERR + Sample error + 20 + 1 + write-only + + + LATCH3 + Latch3 + 19 + 1 + write-only + + + LATCH2 + Latch2 + 18 + 1 + write-only + + + LATCH1 + Latch1 + 17 + 1 + write-only + + + LATCH0 + Latch0 + 16 + 1 + write-only + + + TIMEOUT + Timeout + 13 + 1 + write-only + + + TRX_ERR + Transfer error + 12 + 1 + write-only + + + INSTR1_END + Instruction 1 end + 11 + 1 + write-only + + + INSTR0_END + Instruction 0 end + 10 + 1 + write-only + + + PTR1_END + Pointer 1 end + 9 + 1 + write-only + + + PTR0_END + Pointer 0 end + 8 + 1 + write-only + + + INSTR1_ST + Instruction 1 start + 7 + 1 + write-only + + + INSTR0_ST + Instruction 0 start + 6 + 1 + write-only + + + PTR1_ST + Pointer 1 start + 5 + 1 + write-only + + + PTR0_ST + Pointer 0 start + 4 + 1 + write-only + + + WDOG + Watch dog + 2 + 1 + write-only + + + EXECPT + Exception + 1 + 1 + write-only + + + STALL + Stall + 0 + 1 + write-only + + + + + INT_STS + Interrupt status + 0x308 + 32 + 0x00000000 + 0xFF1F3FF7 + + + TRG_ERR3 + Trigger3 failed + 31 + 1 + read-only + + + TRG_ERR2 + Trigger2 failed + 30 + 1 + read-only + + + TRG_ERR1 + Trigger1 failed + 29 + 1 + read-only + + + TRG_ERR0 + Trigger0 failed + 28 + 1 + read-only + + + TRIGER3 + Trigger3 + 27 + 1 + read-only + + + TRIGER2 + Trigger2 + 26 + 1 + read-only + + + TRIGER1 + Trigger1 + 25 + 1 + read-only + + + TRIGER0 + Trigger0 + 24 + 1 + read-only + + + SMP_ERR + Sample error + 20 + 1 + read-only + + + LATCH3 + Latch3 + 19 + 1 + read-only + + + LATCH2 + Latch2 + 18 + 1 + read-only + + + LATCH1 + Latch1 + 17 + 1 + read-only + + + LATCH0 + Latch0 + 16 + 1 + read-only + + + TIMEOUT + Timeout + 13 + 1 + read-only + + + TRX_ERR + Transfer error + 12 + 1 + read-only + + + INSTR1_END + Instruction 1 end + 11 + 1 + read-only + + + INSTR0_END + Instruction 0 end + 10 + 1 + read-only + + + PTR1_END + Pointer 1 end + 9 + 1 + read-only + + + PTR0_END + Pointer 0 end + 8 + 1 + read-only + + + INSTR1_ST + Instruction 1 start + 7 + 1 + read-only + + + INSTR0_ST + Instruction 0 start + 6 + 1 + read-only + + + PTR1_ST + Pointer 1 start + 5 + 1 + read-only + + + PTR0_ST + Pointer 0 start + 4 + 1 + read-only + + + WDOG + Watch dog + 2 + 1 + read-only + + + EXECPT + Exception + 1 + 1 + read-only + + + STALL + Stall + 0 + 1 + read-only + + + + + POINTER0 + Match pointer 0 + 0x310 + 32 + 0x00000000 + 0x000000FF + + + POINTER + Match pointer 0 + 0 + 8 + read-write + + + + + POINTER1 + Match pointer 1 + 0x314 + 32 + 0x00000000 + 0x000000FF + + + POINTER + Match pointer 1 + 0 + 8 + read-write + + + + + INSTR0 + Match instruction 0 + 0x318 + 32 + 0x00000000 + 0xFFFFFFFF + + + INSTR + Match instruction 0 + 0 + 32 + read-write + + + + + INSTR1 + Match instruction 1 + 0x31c + 32 + 0x00000000 + 0xFFFFFFFF + + + INSTR + Match instruction 1 + 0 + 32 + read-write + + + + + + 64 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 + INSTR[%s] + no description available + 0x3400 + 32 + 0x00000000 + 0xFFFFFFFF + + + OP + operation +0: halt +1: jump +2: send with timeout check +3: send without timout check +4: wait with timeout check +5: wait without timout check +6: receive with timeout check +7: receive without timout check + 26 + 3 + read-write + + + CK + clock +0: low +1: rise-fall +2: fall-rise +3: high + 24 + 2 + read-write + + + CRC + CRC register +0: don't calculate CRC +1: do not set this value +2: data register 2 +3: data register 3 +... +29: data register 29 +30: value 0 when send, wait 0 in receive +31: value1 when send, wait 1 in receive + 16 + 5 + read-write + + + DAT + DATA register +0: ignore data +1: command +2: data register 2 +3: data register 3 +... +29: data register 29 +30: value 0 when send, wait 0 in receive +31: value1 when send, wait 1 in receive + 8 + 5 + read-write + + + OPR + [1] When OP is 0, this area is the halt time in baudrate, 0 represents infinite time. +[2] When OP is 1, this area is the the pointer to the command table. +OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer; +OPR[4]=0, OPR[3:0]=0 is INIT_POINTER; +OPR[4]=0, OPR[3:0]=1 is WDG_POINTER. +[3] When OP is 2-7, this area is the data length as fellow: +0: 1 bit +1: 2 bit + ... +31: 32 bit + 0 + 5 + read-write + + + + + 10 + 0x40 + 0,1,2,3,4,5,6,7,8,9 + DAT[%s] + no description available + 0x3800 + + MODE + No description avaiable + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC_LEN + CRC length +0: 1 bit +1: 2 bit +... +31: 32 bit + 24 + 5 + read-write + + + WLEN + word length +0: 1 bit +1: 2 bit +... +31: 32 bit + 16 + 5 + read-write + + + CRC_SHIFT + CRC shift mode, this mode is used to perform repeat code check +0: CRC +1: shift mode + 13 + 1 + read-write + + + CRC_INV + CRC invert +0: use CRC +1: use inverted CRC + 12 + 1 + read-write + + + WORDER + word order +0: sample as bit order +1: different from bit order + 11 + 1 + read-write + + + BORDER + bit order +0: LSB first +1: MSB first + 10 + 1 + read-write + + + SIGNED + Signed +0: unsigned value +1: signed value + 9 + 1 + read-write + + + REWIND + Write 1 to rewind read/write pointer, this is a self clear bit + 8 + 1 + read-write + + + MODE + Data mode +0: data mode +1: check mode +2: CRC mode + 0 + 2 + read-write + + + + + IDX + Data register bit index + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LAST_BIT + Last bit index for tranceive + 24 + 5 + read-write + + + FIRST_BIT + First bit index for tranceive + 16 + 5 + read-write + + + MAX_BIT + Highest bit index + 8 + 5 + read-write + + + MIN_BIT + Lowest bit index + 0 + 5 + read-write + + + + + GOLD + Gold data for data check + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GOLD_VALUE + Gold value for check mode + 0 + 32 + read-write + + + + + CRCINIT + CRC calculation initial vector + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC_INIT + CRC initial value + 0 + 32 + read-write + + + + + CRCPOLY + CRC calculation polynomial + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC_POLY + CRC polymonial + 0 + 32 + read-write + + + + + DATA + Data value + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + DATA + 0 + 32 + read-write + + + + + SET + Data bit set + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_SET + DATA bit set + 0 + 32 + read-write + + + + + CLR + Data bit clear + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_CLR + DATA bit clear + 0 + 32 + read-write + + + + + INV + Data bit invert + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_INV + DATA bit toggle + 0 + 32 + read-write + + + + + IN + Data input + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_IN + Data input + 0 + 32 + read-only + + + + + OUT + Data output + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA_OUT + Data output + 0 + 32 + read-only + + + + + STS + Data status + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + CRC_IDX + CRC index + 24 + 5 + read-only + + + WORD_IDX + Word index + 16 + 5 + read-only + + + WORD_CNT + Word counter + 8 + 5 + read-only + + + BIT_IDX + Bit index + 0 + 5 + read-only + + + + + + + + TRGM0 + TRGM0 + TRGM + 0xf033c000 + + 0x0 + 0x634 + registers + + + + 28 + 0x4 + PWM0_IN0,PWM0_IN1,PWM0_IN2,PWM0_IN3,PWM0_IN4,PWM0_IN5,PWM0_IN6,PWM0_IN7,PWM1_IN0,PWM1_IN1,PWM1_IN2,PWM1_IN3,PWM1_IN4,PWM1_IN5,PWM1_IN6,PWM1_IN7,MOTO_GPIO_IN0,MOTO_GPIO_IN1,MOTO_GPIO_IN2,MOTO_GPIO_IN3,MOTO_GPIO_IN4,MOTO_GPIO_IN5,MOTO_GPIO_IN6,MOTO_GPIO_IN7,PWM0_FAULT0,PWM0_FAULT1,PWM1_FAULT0,PWM1_FAULT1 + FILTCFG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0x0001FFFF + + + OUTINV + 1- Filter will invert the output +0- Filter will not invert the output + 16 + 1 + read-write + + + MODE + This bitfields defines the filter mode +000-bypass; +100-rapid change mode; +101-delay filter mode; +110-stalbe low mode; +111-stable high mode + 13 + 3 + read-write + + + SYNCEN + set to enable sychronization input signal with TRGM clock + 12 + 1 + read-write + + + FILTLEN + This bitfields defines the filter counter length. + 0 + 12 + read-write + + + + + 137 + 0x4 + MOT2OPAMP0_0,MOT2OPAMP0_1,MOT2OPAMP0_2,MOT2OPAMP0_3,MOT2OPAMP0_4,MOT2OPAMP0_5,MOT2OPAMP0_6,MOT2OPAMP0_7,MOT2OPAMP1_0,MOT2OPAMP1_1,MOT2OPAMP1_2,MOT2OPAMP1_3,MOT2OPAMP1_4,MOT2OPAMP1_5,MOT2OPAMP1_6,MOT2OPAMP1_7,GPTMR0_IN2,GPTMR0_IN3,GPTMR0_SYNCI,GPTMR1_IN2,GPTMR1_IN3,GPTMR1_SYNCI,GPTMR2_IN2,GPTMR2_IN3,GPTMR2_SYNCI,GPTMR3_IN2,GPTMR3_IN3,GPTMR3_SYNCI,CMP0_WIN,CMP1_WIN,DAC0_BUFTRG,DAC1_BUFTRG,ADC0_STRGI,ADC1_STRGI,ADCx_PTRGI0A,ADCx_PTRGI0B,ADCx_PTRGI0C,ADCx_PTRGI1A,ADCx_PTRGI1B,ADCx_PTRGI1C,ADCx_PTRGI2A,ADCx_PTRGI2B,ADCx_PTRGI2C,ADCx_PTRGI3A,ADCx_PTRGI3B,ADCx_PTRGI3C,CAN_PTPC0_CAP,CAN_PTPC1_CAP,QEO0_TRIG_IN0,QEO0_TRIG_IN1,QEO1_TRIG_IN0,QEO1_TRIG_IN1,SEI_TRIG_IN0,SEI_TRIG_IN1,SEI_TRIG_IN2,SEI_TRIG_IN3,SEI_TRIG_IN4,SEI_TRIG_IN5,SEI_TRIG_IN6,SEI_TRIG_IN7,MMC0_TRIG_IN0,MMC0_TRIG_IN1,MMC1_TRIG_IN0,MMC1_TRIG_IN1,PLB_IN_00,PLB_IN_01,PLB_IN_02,PLB_IN_03,PLB_IN_04,PLB_IN_05,PLB_IN_06,PLB_IN_07,PLB_IN_08,PLB_IN_09,PLB_IN_10,PLB_IN_11,PLB_IN_12,PLB_IN_13,PLB_IN_14,PLB_IN_15,PLB_IN_16,PLB_IN_17,PLB_IN_18,PLB_IN_19,PLB_IN_20,PLB_IN_21,PLB_IN_22,PLB_IN_23,PLB_IN_24,PLB_IN_25,PLB_IN_26,PLB_IN_27,PLB_IN_28,PLB_IN_29,PLB_IN_30,PLB_IN_31,MOT_GPIO0,MOT_GPIO1,MOT_GPIO2,MOT_GPIO3,MOT_GPIO4,MOT_GPIO5,MOT_GPIO6,MOT_GPIO7,PWM_IN8,PWM_IN9,PWM_IN10,PWM_IN11,PWM_IN12,PWM_IN13,PWM_IN14,PWM_IN15,PWM0_FRCI,PWM0_FRCSYNCI,PWM0_SYNCI,PWM0_SHRLDSYNCI,PWM0_FAULTI0,PWM0_FAULTI1,PWM1_FRCI,PWM1_FRCSYNCI,PWM1_SYNCI,PWM1_SHRLDSYNCI,PWM1_FAULTI0,PWM1_FAULTI1,RDC_TRIG_IN0,RDC_TRIG_IN1,SYNCTIMER_TRIG,QEI0_TRIG_IN,QEI1_TRIG_IN,QEI0_PAUSE,QEI1_PAUSE,UART_TRIG0,UART_TRIG1,TRGM_IRQ0,TRGM_IRQ1,TRGM_DMA0,TRGM_DMA1 + TRGOCFG[%s] + no description available + 0x100 + 32 + 0x00000000 + 0x00000E7F + + + OUTINV + 1- Invert the output + 11 + 1 + read-write + + + FEDG2PEN + 1- The selected input signal falling edge will be convert to an pulse on output. + 10 + 1 + read-write + + + REDG2PEN + 1- The selected input signal rising edge will be convert to an pulse on output. + 9 + 1 + read-write + + + TRIGOSEL + This bitfield selects one of the TRGM inputs as output. + 0 + 7 + read-write + + + + + 8 + 0x4 + 0,1,2,3,4,5,6,7 + DMACFG[%s] + no description available + 0x400 + 32 + 0x00000000 + 0x8000003F + + + DMAMUX_EN + No description avaiable + 31 + 1 + read-write + + + DMASRCSEL + This field selects one of the DMA requests as the DMA request output. + 0 + 6 + read-write + + + + + GCR + General Control Register + 0x500 + 32 + 0x00000000 + 0x000000FF + + + TRGOPEN + The bitfield enable the TRGM outputs. + 0 + 8 + read-write + + + + + ADC_MATRIX_SEL + adc matrix select register + 0x510 + 32 + 0x00000000 + 0xFFFFFFFF + + + QEI1_ADC1_SEL + 0-adc0; 1-adc1; 2-rdc_adc0; 3-rdc_adc1; +bit7 is used to invert adc_value; +others reserved + 24 + 8 + read-write + + + QEI1_ADC0_SEL + No description avaiable + 16 + 8 + read-write + + + QEI0_ADC1_SEL + No description avaiable + 8 + 8 + read-write + + + QEI0_ADC0_SEL + No description avaiable + 0 + 8 + read-write + + + + + DAC_MATRIX_SEL + dac matrix select register + 0x514 + 32 + 0x00000000 + 0xFFFFFFFF + + + DAC1_DAC_SEL + 0-qeo0_dac0; 1-qeo0_dac1; 2-qeo0_dac2; +3-qeo1_dac0; 4-qeo1_dac1; 5-qeo1_dac2; +6-rdc_dac0; 7-rdc_dac1; +bit7 is used to invert dac_value; +others reserved + 24 + 8 + read-write + + + DAC0_DAC_SEL + No description avaiable + 16 + 8 + read-write + + + ACMP1_DAC_SEL + No description avaiable + 8 + 8 + read-write + + + ACMP0_DAC_SEL + No description avaiable + 0 + 8 + read-write + + + + + POS_MATRIX_SEL0 + position matrix select register0 + 0x518 + 32 + 0x00000000 + 0xFFFFFFFF + + + MMC1_POSIN_SEL + 0-sei_pos_out0; 1-sei_pos_out1; +2-qei0_pos; 3-qei1_pos; +4-mmc0_pos_out0; 5-mmc0_pos_out1; +6-mmc1_pos_out0; 7-mmc1_pos_out1; +bit7 is used to invert position value; + others reserved + 24 + 8 + read-write + + + MMC0_POSIN_SEL + No description avaiable + 16 + 8 + read-write + + + SEI_POSIN1_SEL + No description avaiable + 8 + 8 + read-write + + + SEI_POSIN0_SEL + No description avaiable + 0 + 8 + read-write + + + + + POS_MATRIX_SEL1 + position matrix select register1 + 0x51c + 32 + 0x00000000 + 0x0000FFFF + + + QEO1_POS_SEL + No description avaiable + 8 + 8 + read-write + + + QEO0_POS_SEL + No description avaiable + 0 + 8 + read-write + + + + + 4 + 0x4 + 0,1,2,3 + TRGM_IN[%s] + no description available + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGM_IN + mmc1_trig_out[1:0], mmc0_trig_out[1:0],sync_pulse[3:0],moto_gpio_in_sync[7:0],//31:16 + gtmr3_to_motor_sync[1:0],gtmr2_to_motor_sync[1:0],gtmr1_to_motor_sync[1:0],gtmr0_to_motor_sync[1:0], //15:8 + acmp_out_sync[1:0],can2mot_event_sync[1:0],usb0_sof_tog_sync,pwm_debug,1'b1,1'b0 //7:0 + 0 + 32 + read-only + + + + + 5 + 0x4 + 0,1,2,3,4 + TRGM_OUT[%s] + no description available + 0x620 + 32 + 0x00000000 + 0xFFFFFFFF + + + TRGM_OUT + motor_to_opamp0[7:0] = trig_mux_out[7:0]; +motor_to_opamp1[7:0] = trig_mux_out[15:8]; +motor_to_gtmr0_capt[1:0] = trig_mux_out[17:16]; +motor_to_gtmr0_sync = trig_mux_out[18]; +motor_to_gtmr1_capt[1:0] = trig_mux_out[20:19]; +motor_to_gtmr1_sync = trig_mux_out[21]; +motor_to_gtmr2_capt[1:0] = trig_mux_out[23:22]; +motor_to_gtmr2_sync = trig_mux_out[24]; +motor_to_gtmr3_capt[1:0] = trig_mux_out[26:25]; +motor_to_gtmr3_sync = trig_mux_out[27]; +acmp_window[1:0] = trig_mux_out[29:28]; +dac0_buf_trigger = trig_mux_out[30]; +dac1_buf_trigger = trig_mux_out[31]; +dac0_step_trigger[3:0] = {trig_mux_out[24:22],trig_mux_out[30]};//use same buf_trig, and gtmr2 +dac1_step_trigger[3:0] = {trig_mux_out[27:25],trig_mux_out[31]}; //use same buf_trig, and gtmr3 + 0 + 32 + read-only + + + + + + + USB0 + USB0 + USB + 0xf300c000 + + 0x80 + 0x1a8 + registers + + + + GPTIMER0LD + General Purpose Timer #0 Load Register + 0x80 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller Register + 0x84 + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in n_GPTIMER0LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software; +In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the +counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + GPTIMER1LD + General Purpose Timer #1 Load Register + 0x88 + 32 + 0x00000000 + 0x00FFFFFF + + + GPTLD + GPTLD +General Purpose Timer Load Value +These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. +This value represents the time in microseconds minus 1 for the timer duration. +Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. +NOTE: Max value is 0xFFFFFF or 16.777215 seconds. + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller Register + 0x8c + 32 + 0x00000000 + 0xC1FFFFFF + + + GPTRUN + GPTRUN +General Purpose Timer Run +GPTCNT bits are not effected when setting or clearing this bit. +0 - Stop counting +1 - Run + 31 + 1 + read-write + + + GPTRST + GPTRST +General Purpose Timer Reset +0 - No action +1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD + 30 + 1 + write-only + + + GPTMODE + GPTMODE +General Purpose Timer Mode +In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is +reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and +automatically reload the counter value from GPTLD bits to start again. +0 - One Shot Mode +1 - Repeat Mode + 24 + 1 + read-write + + + GPTCNT + GPTCNT +General Purpose Timer Counter. +This field is the count value of the countdown timer. + 0 + 24 + read-only + + + + + SBUSCFG + System Bus Config Register + 0x90 + 32 + 0x00000000 + 0x00000007 + + + AHBBRST + AHBBRST +AHB master interface Burst configuration +These bits control AHB master transfer type sequence (or priority). +NOTE: This register overrides n_BURSTSIZE register when its value is not zero. +000 - Incremental burst of unspecified length only +001 - INCR4 burst, then single transfer +010 - INCR8 burst, INCR4 burst, then single transfer +011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer +100 - Reserved, don't use +101 - INCR4 burst, then incremental burst of unspecified length +110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length +111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0 + 3 + read-write + + + + + USBCMD + USB Command Register + 0x140 + 32 + 0x00080000 + 0x00FFEB7F + + + ITC + ITC +Interrupt Threshold Control -Read/Write. +The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are +shown below. +Value Maximum Interrupt Interval +00000000 - Immediate (no threshold) +00000001 - 1 micro-frame +00000010 - 2 micro-frames +00000100 - 4 micro-frames +00001000 - 8 micro-frames +00010000 - 16 micro-frames +00100000 - 32 micro-frames +01000000 - 64 micro-frames + 16 + 8 + read-write + + + FS_2 + FS_2 +Frame List Size - (Read/Write or Read Only). [host mode only] +This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. +This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. +NOTE: This field is made up from USBCMD bits 15, 3 and 2. +Value Meaning +0b000 - 1024 elements (4096 bytes) Default value +0b001 - 512 elements (2048 bytes) +0b010 - 256 elements (1024 bytes) +0b011 - 128 elements (512 bytes) +0b100 - 64 elements (256 bytes) +0b101 - 32 elements (128 bytes) +0b110 - 16 elements (64 bytes) +0b111 - 8 elements (32 bytes) + 15 + 1 + read-write + + + ATDTW + ATDTW +Add dTD TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's +linked list. This bit is set and cleared by software. +This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD +to a primed endpoint may go unrecognized. + 14 + 1 + read-write + + + SUTW + SUTW +Setup TripWire - Read/Write. [device mode only] +This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. +If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. +This bit would also be cleared by hardware when a hazard detected. + 13 + 1 + read-write + + + ASPE + ASPE +Asynchronous Schedule Park Mode Enable - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. +NOTE: ASPE bit reset value: '0b' for OTG controller . + 11 + 1 + read-write + + + ASP + ASP +Asynchronous Schedule Park Mode Count - Read/Write. +If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. +It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. +Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. +This field is set to 3h in all controller core. + 8 + 2 + read-write + + + IAA + IAA +Interrupt on Async Advance Doorbell - Read/Write. +This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. +When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. +The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. +This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. + 6 + 1 + read-write + + + ASE + ASE +Asynchronous Schedule Enable - Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Asynchronous Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Asynchronous Schedule. +1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 5 + 1 + read-write + + + PSE + PSE +Periodic Schedule Enable- Read/Write. Default 0b. +This bit controls whether the host controller skips processing the Periodic Schedule. +Only the host controller uses this bit. +Values Meaning +0 - Do not process the Periodic Schedule +1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. + 4 + 1 + read-write + + + FS_1 + FS_1 +See description at bit 15 + 2 + 2 + read-write + + + RST + RST +Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. +Host operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. +Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. +Attempting to reset an actively running host controller will result in undefined behavior. +Device operation mode: +When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. +Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. + 1 + 1 + read-write + + + RS + RS +Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. +Host operation mode: +When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. +Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). +Device operation mode: +Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. +This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. + 0 + 1 + read-write + + + + + USBSTS + USB Status Register + 0x144 + 32 + 0x00000000 + 0x030DF1FF + + + TI1 + TI1 +General Purpose Timer Interrupt 1(GPTINT1)--R/WC. +This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this +bit will clear it. + 25 + 1 + read-write + + + TI0 + TI0 +General Purpose Timer Interrupt 0(GPTINT0)--R/WC. +This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this +bit clears it. + 24 + 1 + read-write + + + UPI + USB Host Periodic Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. +This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero. + 19 + 1 + read-write + + + UAI + USB Host Asynchronous Interrupt – RWC. Default = 0b. +This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. +This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. +This bit is not used by the device controller and will always be zero + 18 + 1 + read-write + + + NAKI + NAKI +NAK Interrupt Bit--RO. +This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and +corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware +when all Enabled TX/RX Endpoint NAK bits are cleared. + 16 + 1 + read-only + + + AS + AS +Asynchronous Schedule Status - Read Only. +This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. +The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. +When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 15 + 1 + read-only + + + PS + PS +Periodic Schedule Status - Read Only. +This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). +Only used in the host operation mode. + 14 + 1 + read-only + + + RCL + RCL +Reclamation - Read Only. +This is a read-only status bit used to detect an empty asynchronous schedule. +Only used in the host operation mode. + 13 + 1 + read-only + + + HCH + HCH +HCHaIted - Read Only. +This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). +Only used in the host operation mode. +Default value is '0b' for OTG core . +This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE +register. +NOTE: HCH bit reset value: '0b' for OTG controller core . + 12 + 1 + read-only + + + SLI + SLI +DCSuspend - R/WC. +When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. +Only used in device operation mode. + 8 + 1 + read-write + + + SRI + SRI +SOF Received - R/WC. +When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. +Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. +Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. +In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. +Software writes a 1 to this bit to clear it. + 7 + 1 + read-write + + + URI + URI +USB Reset Received - R/WC. +When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. +Software can write a 1 to this bit to clear the USB Reset Received status bit. +Only used in device operation mode. + 6 + 1 + read-write + + + AAI + AAI +Interrupt on Async Advance - R/WC. +System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. +Only used in host operation mode. + 5 + 1 + read-write + + + SEI + System Error – RWC. Default = 0b. +In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) + 4 + 1 + read-write + + + FRI + FRI +Frame List Rollover - R/WC. +The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to +zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the +frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the +Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host +Controller sets this bit to a one every time FHINDEX [12] toggles. +Only used in host operation mode. + 3 + 1 + read-write + + + PCI + PCI +Port Change Detect - R/WC. +The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. +The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. + 2 + 1 + read-write + + + UEI + UEI +USB Error Interrupt (USBERRINT) - R/WC. +When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. + 1 + 1 + read-write + + + UI + UI +USB Interrupt (USBINT) - R/WC. +This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB +transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. +This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when +the actual number of bytes received was less than the expected number of bytes. + 0 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + 0x00000000 + 0x030D01FF + + + TIE1 + TIE1 +General Purpose Timer #1 Interrupt Enable +When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. + 25 + 1 + read-write + + + TIE0 + TIE0 +General Purpose Timer #0 Interrupt Enable +When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. + 24 + 1 + read-write + + + UPIE + UPIE +USB Host Periodic Interrupt Enable +When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 19 + 1 + read-write + + + UAIE + UAIE +USB Host Asynchronous Interrupt Enable +When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an +interrupt at the next interrupt threshold. + 18 + 1 + read-write + + + NAKE + NAKE +NAK Interrupt Enable +When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. + 16 + 1 + read-only + + + SLE + SLE +Sleep Interrupt Enable +When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 8 + 1 + read-write + + + SRE + SRE +SOF Received Interrupt Enable +When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. + 7 + 1 + read-write + + + URE + URE +USB Reset Interrupt Enable +When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in device operation mode. + 6 + 1 + read-write + + + AAE + AAE +Async Advance Interrupt Enable +When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 5 + 1 + read-write + + + SEE + SEE +System Error Interrupt Enable +When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 4 + 1 + read-write + + + FRE + FRE +Frame List Rollover Interrupt Enable +When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. +Only used in host operation mode. + 3 + 1 + read-write + + + PCE + PCE +Port Change Detect Interrupt Enable +When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. + 2 + 1 + read-write + + + UEE + UEE +USB Error Interrupt Enable +When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. + 1 + 1 + read-write + + + UE + UE +USB Interrupt Enable +When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. + 0 + 1 + read-write + + + + + FRINDEX + USB Frame Index Register + 0x14c + 32 + 0x00000000 + 0x00003FFF + + + FRINDEX + FRINDEX +Frame Index. +The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. +The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. +USBCMD [Frame List Size] Number Elements N +In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. +In either mode bits 2:0 indicate the current microframe. +The bit field values description below is represented as (Frame List Size) Number Elements N. +00000000000000 - (1024) 12 +00000000000001 - (512) 11 +00000000000010 - (256) 10 +00000000000011 - (128) 9 +00000000000100 - (64) 8 +00000000000101 - (32) 7 +00000000000110 - (16) 6 +00000000000111 - (8) 5 + 0 + 14 + read-write + + + + + DEVICEADDR + Device Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFF000000 + + + USBADR + USBADR +Device Address. +These bits correspond to the USB device address + 25 + 7 + read-write + + + USBADRA + USBADRA +Device Address Advance. Default=0. +When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. +After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. +Hardware will automatically clear this bit on the following conditions: +1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). +2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). +3) Device Reset occurs (USBADR is reset to 0). +NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. +If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. + 24 + 1 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address Register + UNION_154 + 0x154 + 32 + 0x00000000 + 0xFFFFF000 + + + BASEADR + BASEADR +Base Address (Low). +These bits correspond to memory address signals [31:12], respectively. +Only used by the host controller. + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFFFE0 + + + ASYBASE + ASYBASE +Link Pointer Low (LPL). +These bits correspond to memory address signals [31:5], respectively. This field may only reference a +Queue Head (QH). +Only used by the host controller. + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address Register + UNION_158 + 0x158 + 32 + 0x00000000 + 0xFFFFF800 + + + EPBASE + EPBASE +Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size Register + 0x160 + 32 + 0x00000000 + 0x0000FFFF + + + TXPBURST + TXPBURST +Programmable TX Burst Size. +Default value is determined by TXBURST bits in n_HWTXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from system +memory to the USB bus. + 8 + 8 + read-write + + + RXPBURST + RXPBURST +Programmable RX Burst Size. +Default value is determined by TXBURST bits in n_HWRXBUF. +This register represents the maximum length of a the burst in 32-bit words while moving data from the +USB bus to system memory. + 0 + 8 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning Register + 0x164 + 32 + 0x00000000 + 0x003F1F7F + + + TXFIFOTHRES + TXFIFOTHRES +FIFO Burst Threshold. (Read/Write) +This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. +The minimum value is 2 and this value should be a low as possible to maximize USB performance. +A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. +This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. + 16 + 6 + read-write + + + TXSCHHEALTH + TXSCHHEALTH +Scheduler Health Counter. (Read/Write To Clear) +Table continues on the next page +This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. + 8 + 5 + read-write + + + TXSCHOH + TXSCHOH +Scheduler Overhead. (Read/Write) [Default = 0] +This register adds an additional fixed offset to the schedule time estimator described above as Tff. +As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. +Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. +The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. +The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. +Default value is '08h' for OTG controller core . + 0 + 7 + read-write + + + + + ENDPTNAK + Endpoint NAK Register + 0x178 + 32 + 0x00000000 + 0x00FF00FF + + + EPTN + EPTN +TX Endpoint NAK - R/WC. +Each TX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received IN token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 8 + read-write + + + EPRN + EPRN +RX Endpoint NAK - R/WC. +Each RX endpoint has 1 bit in this field. The bit is set when the +device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 8 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable Register + 0x17c + 32 + 0x00000000 + 0x00FF00FF + + + EPTNE + EPTNE +TX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the +corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 16 + 8 + read-write + + + EPRNE + EPRNE +RX Endpoint NAK Enable - R/W. +Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the +corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. +Bit [N] - Endpoint #[N], N is 0-7 + 0 + 8 + read-write + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + 0x00000000 + 0x3DFF1FFF + + + STS + STS +Serial Transceiver Select +1 Serial Interface Engine is selected +0 Parallel Interface signals is selected +Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. +When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. + 29 + 1 + read-write + + + PTW + PTW +Parallel Transceiver Width +This bit has no effect if serial interface engine is used. +0 - Select the 8-bit UTMI interface [60MHz] +1 - Select the 16-bit UTMI interface [30MHz] + 28 + 1 + read-write + + + PSPD + PSPD +Port Speed - Read Only. +This register field indicates the speed at which the port is operating. +00 - Full Speed +01 - Low Speed +10 - High Speed +11 - Undefined + 26 + 2 + read-only + + + PFSC + PFSC +Port Force Full Speed Connect - Read/Write. Default = 0b. +When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp +sequence that allows the port to identify itself as High Speed. +0 - Normal operation +1 - Forced to full speed + 24 + 1 + read-write + + + PHCD + PHCD +PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. +When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY +clock. +NOTE: The PHY clock cannot be disabled if it is being used as the system clock. +In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD +Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend +will be cleared automatically when the host initials resume. Before forcing a resume from the device, the +device controller driver must clear this bit. +In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put +into suspend mode or when no downstream device is connected. Low power suspend is completely +under the control of software. +0 - Enable PHY clock +1 - Disable PHY clock + 23 + 1 + read-write + + + WKOC + WKOC +Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. +Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. +This field is zero if Port Power(PORTSC1) is zero. + 22 + 1 + read-write + + + WKDC + WKDC +Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables +the port to be sensitive to device disconnects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 21 + 1 + read-write + + + WKCN + WKCN +Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. +Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. +This field is zero if Port Power(PORTSC1) is zero or in device mode. + 20 + 1 + read-write + + + PTC + PTC +Port Test Control - Read/Write. Default = 0000b. +Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. +The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. +NOTE: Low speed operations are not supported as a peripheral device. +Any other value than zero indicates that the port is operating in test mode. +Value Specific Test +0000 - TEST_MODE_DISABLE +0001 - J_STATE +0010 - K_STATE +0011 - SE0 (host) / NAK (device) +0100 - Packet +0101 - FORCE_ENABLE_HS +0110 - FORCE_ENABLE_FS +0111 - FORCE_ENABLE_LS +1000-1111 - Reserved + 16 + 4 + read-write + + + PP + PP +Port Power (PP)-Read/Write or Read Only. +The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: +PPC +PP Operation +0 +1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. +1 +1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. +When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). +This feature is implemented in all controller cores (PPC = 1). + 12 + 1 + read-write + + + LS + LS +Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal +lines. +In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because +the port controller state machine and the port routing manage the connection of LS and FS. +In device mode, the use of linestate by the device controller driver is not necessary. +The encoding of the bits are: +Bits [11:10] Meaning +00 - SE0 +01 - K-state +10 - J-state +11 - Undefined + 10 + 2 + read-only + + + HSP + HSP +High-Speed Port - Read Only. Default = 0b. +When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the +host/device connected to the port is not in a high-speed mode. +NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. + 9 + 1 + read-only + + + PR + PR +Port Reset - Read/Write or Read Only. Default = 0b. +In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. +When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. +In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. + 8 + 1 + read-write + + + SUSP + SUSP +Suspend - Read/Write or Read Only. Default = 0b. +1=Port in suspend state. 0=Port not in suspend state. +In Host Mode: Read/Write. +Port Enabled Bit and Suspend bit of this register define the port states as follows: +Bits [Port Enabled, Suspend] Port State +0x Disable +10 Enable +11 Suspend +When in suspend state, downstream propagation of data is blocked on this port, except for port reset. +The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. +The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. +If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: Read Only. +In device mode this bit is a read only status bit. + 7 + 1 + read-write + + + FPR + FPR +Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. +In Host Mode: +Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. +This bit will automatically change to zero after the resume sequence is complete. +This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. +Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. +The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. +Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. +This field is zero if Port Power(PORTSC1) is zero in host mode. +This bit is not-EHCI compatible. +In Device mode: +After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. +The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. +The bit will be cleared when the device returns to normal operation. + Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. + 6 + 1 + read-write + + + OCC + OCC +Over-current Change-R/WC. Default=0. +This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. + 5 + 1 + read-write + + + OCA + OCA +Over-current Active-Read Only. Default 0. +This bit will automatically transition from one to zero when the over current condition is removed. +0 - This port does not have an over-current condition. +1 - This port currently has an over-current condition + 4 + 1 + read-only + + + PEC + PEC +Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. +In Host Mode: +For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). +Software clears this by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero. +In Device mode: +The device port is always enabled, so this bit is always '0b'. + 3 + 1 + read-write + + + PE + PE +Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. +In Host Mode: +Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. +Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. +Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. +When the port is disabled, (0b) downstream propagation of data is blocked except for reset. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +The device port is always enabled, so this bit is always '1b'. + 2 + 1 + read-write + + + CSC + CSC +Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. +In Host Mode: +Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. +For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +This bit is undefined in device controller mode. + 1 + 1 + read-write + + + CCS + CCS +Current Connect Status-Read Only. +In Host Mode: +1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. +This field is zero if Port Power(PORTSC1) is zero in host mode. +In Device Mode: +1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended. + 0 + 1 + read-write + + + + + OTGSC + On-The-Go Status & control Register + 0x1a4 + 32 + 0x00000000 + 0x07070723 + + + ASVIE + ASVIE +A Session Valid Interrupt Enable - Read/Write. + 26 + 1 + read-write + + + AVVIE + AVVIE +A VBus Valid Interrupt Enable - Read/Write. +Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + IDIE + IDIE +USB ID Interrupt Enable - Read/Write. +Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + ASVIS + ASVIS +A Session Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the A session valid threshold. +Software must write a one to clear this bit. + 18 + 1 + read-write + + + AVVIS + AVVIS +A VBus Valid Interrupt Status - Read/Write to Clear. +This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. +Software must write a one to clear this bit. + 17 + 1 + read-write + + + IDIS + IDIS +USB ID Interrupt Status - Read/Write. +This bit is set when a change on the ID input has been detected. +Software must write a one to clear this bit. + 16 + 1 + read-write + + + ASV + ASV +A Session Valid - Read Only. +Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + AVV + AVV +A VBus Valid - Read Only. +Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ID + ID +USB ID - Read Only. +0 = A device, 1 = B device + 8 + 1 + read-only + + + IDPU + IDPU +ID Pullup - Read/Write +This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input +will not be sampled. + 5 + 1 + read-write + + + VC + VC +VBUS Charge - Read/Write. +Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. + 1 + 1 + read-write + + + VD + VD +VBUS_Discharge - Read/Write. +Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + + + USBMODE + USB Device Mode Register + 0x1a8 + 32 + 0x00000000 + 0x0000001F + + + SDIS + SDIS +Stream Disable Mode. (0 - Inactive [default]; 1 - Active) +Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. +This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. +Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. +Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. +NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for +the scheduler when using this feature. +NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. + 4 + 1 + read-write + + + SLOM + SLOM +Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . +0 - Setup Lockouts On (default); +1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. + 3 + 1 + read-write + + + ES + ES +Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the +host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected +by the value of this bit because they are based upon the 32-bit word. +Bit Meaning +0 - Little Endian [Default] +1 - Big Endian + 2 + 1 + read-write + + + CM + CM +Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only +implementations. For those designs that contain both host & device capability, the controller defaults to +an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ +device controllers, this register can only be written once after reset. If it is necessary to switch modes, +software must reset the controller by writing to the RESET bit in the USBCMD register before +reprogramming this register. +For OTG controller core, reset value is '00b'. +00 - Idle [Default for combination host/device] +01 - Reserved +10 - Device Controller [Default for device only controller] +11 - Host Controller [Default for host only controller] + 0 + 2 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status Register + 0x1ac + 32 + 0x00000000 + 0x000000FF + + + ENDPTSETUPSTAT + ENDPTSETUPSTAT +Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. +Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. +The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. +This register is only used in device mode. + 0 + 8 + read-write + + + + + ENDPTPRIME + Endpoint Prime Register + 0x1b0 + 32 + 0x00000000 + 0x00FF00FF + + + PETB + PETB +Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a +buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. +Software should write a one to the corresponding bit when posting a new transfer descriptor to an +endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor +from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated +endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PETB[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write + + + PERB + PERB +Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. +Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. +Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. +Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. +NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD +is retired, and the dQH is updated. +PERB[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-write + + + + + ENDPTFLUSH + Endpoint Flush Register + 0x1b4 + 32 + 0x00000000 + 0x00FF00FF + + + FETB + FETB +Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. +If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FETB[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write + + + FERB + FERB +Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. + If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. +Hardware clears this register after the endpoint flush operation is successful. +FERB[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-write + + + + + ENDPTSTAT + Endpoint Status Register + 0x1b8 + 32 + 0x00000000 + 0x00FF00FF + + + ETBR + ETBR +Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. +This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. +There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. +This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. +Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. +ETBR[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-only + + + ERBR + ERBR +Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective +endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a +corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the +ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB +traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the +USB DMA system, or through the ENDPTFLUSH register. +NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations +when a dTD is retired, and the dQH is updated. +ERBR[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete Register + 0x1bc + 32 + 0x00000000 + 0x00FF00FF + + + ETCE + ETCE +Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. +If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. +ETCE[N] - Endpoint #N, N is in 0..7 + 16 + 8 + read-write + + + ERCE + ERCE +Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred +and software should read the corresponding endpoint queue to determine the transfer status. If the +corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the +USBINT . Writing one clears the corresponding bit in this register. +ERCE[N] - Endpoint #N, N is in 0..7 + 0 + 8 + read-write + + + + + 8 + 0x4 + ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7 + ENDPTCTRL[%s] + no description available + 0x1c0 + 32 + 0x00000000 + 0x00CD00CD + + + TXE + TXE +TX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 23 + 1 + read-write + + + TXR + TXR +TX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the Host and device. + 22 + 1 + write-only + + + TXT + TXT +TX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 18 + 2 + read-write + + + TXS + TXS +TX Endpoint Stall - Read/Write +0 End Point OK +1 End Point Stalled +This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. +This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. +In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: +continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. + 16 + 1 + read-write + + + RXE + RXE +RX Endpoint Enable +0 Disabled [Default] +1 Enabled +An Endpoint should be enabled only after it has been configured. + 7 + 1 + read-write + + + RXR + RXR +RX Data Toggle Reset (WS) +Write 1 - Reset PID Sequence +Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order +to synchronize the data PID's between the host and device. + 6 + 1 + write-only + + + RXT + RXT +RX Endpoint Type - Read/Write +00 Control +01 Isochronous +10 Bulk +11 Interrupt + 2 + 2 + read-write + + + RXS + RXS +RX Endpoint Stall - Read/Write +0 End Point OK. [Default] +1 End Point Stalled +This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control +Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit +is cleared. +Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This +control will continue to STALL until this bit is either cleared by software or automatically cleared as above +for control endpoints. +NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the +ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it +is unlikely the DCD software will observe this delay. However, should the DCD observe that the +stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit +until it is set or until a new setup has been received by checking the associated endptsetupstat +Bit. + 0 + 1 + read-write + + + + + OTG_CTRL0 + No description avaiable + 0x200 + 32 + 0x00000000 + 0x020B3F90 + + + OTG_WKDPDMCHG_EN + No description avaiable + 25 + 1 + read-write + + + AUTORESUME_EN + No description avaiable + 19 + 1 + read-write + + + OTG_VBUS_WAKEUP_EN + No description avaiable + 17 + 1 + read-write + + + OTG_ID_WAKEUP_EN + No description avaiable + 16 + 1 + read-write + + + OTG_VBUS_SOURCE_SEL + No description avaiable + 13 + 1 + read-write + + + OTG_UTMI_SUSPENDM_SW + default 0 for naneng usbphy + 12 + 1 + read-write + + + OTG_UTMI_RESET_SW + default 1 for naneng usbphy + 11 + 1 + read-write + + + OTG_WAKEUP_INT_ENABLE + No description avaiable + 10 + 1 + read-write + + + OTG_POWER_MASK + No description avaiable + 9 + 1 + read-write + + + OTG_OVER_CUR_POL + No description avaiable + 8 + 1 + read-write + + + OTG_OVER_CUR_DIS + No description avaiable + 7 + 1 + read-write + + + SER_MODE_SUSPEND_EN + for naneng usbphy, only switch to serial mode when suspend + 4 + 1 + read-write + + + + + PHY_CTRL0 + No description avaiable + 0x210 + 32 + 0x00000000 + 0x02007007 + + + GPIO_ID_SEL_N + No description avaiable + 25 + 1 + read-write + + + ID_DIG_OVERRIDE + No description avaiable + 14 + 1 + read-write + + + SESS_VALID_OVERRIDE + No description avaiable + 13 + 1 + read-write + + + VBUS_VALID_OVERRIDE + No description avaiable + 12 + 1 + read-write + + + ID_DIG_OVERRIDE_EN + No description avaiable + 2 + 1 + read-write + + + SESS_VALID_OVERRIDE_EN + No description avaiable + 1 + 1 + read-write + + + VBUS_VALID_OVERRIDE_EN + No description avaiable + 0 + 1 + read-write + + + + + PHY_CTRL1 + No description avaiable + 0x214 + 32 + 0x00000000 + 0x00100002 + + + UTMI_CFG_RST_N + No description avaiable + 20 + 1 + read-write + + + UTMI_OTG_SUSPENDM + OTG suspend, not utmi_suspendm + 1 + 1 + read-write + + + + + TOP_STATUS + No description avaiable + 0x220 + 32 + 0x00000000 + 0x80000000 + + + WAKEUP_INT_STATUS + No description avaiable + 31 + 1 + read-write + + + + + PHY_STATUS + No description avaiable + 0x224 + 32 + 0x00000000 + 0x800000F5 + + + UTMI_CLK_VALID + No description avaiable + 31 + 1 + read-write + + + LINE_STATE + No description avaiable + 6 + 2 + read-write + + + HOST_DISCONNECT + No description avaiable + 5 + 1 + read-write + + + ID_DIG + No description avaiable + 4 + 1 + read-write + + + UTMI_SESS_VALID + No description avaiable + 2 + 1 + read-write + + + VBUS_VALID + No description avaiable + 0 + 1 + read-write + + + + + + + SDP + SDP + SDP + 0xf3040000 + + 0x0 + 0x60 + registers + + + + SDPCR + SDP control register + 0x0 + 32 + 0x30000000 + 0xFFFE0101 + + + SFTRST + soft reset. +Write 1 then 0, to reset the SDP block. + 31 + 1 + read-write + + + CLKGAT + Clock Gate for the SDP main logic. +Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. + 30 + 1 + read-write + + + CIPDIS + Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. +1, Cipher is disabled in this chip. +0, Cipher is enabled in this chip. + 29 + 1 + read-only + + + HASDIS + HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. +1, HASH is disabled in this chip. +0, HASH is enabled in this chip. + 28 + 1 + read-only + + + CIPHEN + Cipher Enablement, controlled by SW. +1, Cipher is Enabled. +0, Cipher is Disabled. + 23 + 1 + read-write + + + HASHEN + HASH Enablement, controlled by SW. +1, HASH is Enabled. +0, HASH is Disabled. + 22 + 1 + read-write + + + MCPEN + Memory Copy Enablement, controlled by SW. +1, Memory copy is Enabled. +0, Memory copy is Disabled. + 21 + 1 + read-write + + + CONFEN + Constant Fill to memory, controlled by SW. +1, Constant fill is Enabled. +0, Constant fill is Disabled. + 20 + 1 + read-write + + + DCRPDI + Decryption Disable bit, Write to 1 to disable the decryption. + 19 + 1 + read-write + + + TSTPKT0IRQ + Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. + 17 + 1 + read-write + + + RDSCEN + when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) +when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) + 8 + 1 + read-write + + + INTEN + Interrupt Enablement, controlled by SW. +1, SDP interrupt is enabled. +0, SDP interrupt is disabled. + 0 + 1 + read-write + + + + + MODCTRL + Mod control register. + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + AESALG + AES algorithem selection. +0x0 = AES 128; +0x1 = AES 256; +0x8 = SM4； +Others, reserved. + 28 + 4 + read-write + + + AESMOD + AES mode selection. +0x0 = ECB; +0x1 = CBC; +Others, reserved. + 24 + 4 + read-write + + + AESKS + AES Key Selection. +These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: +0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. +0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +.... +0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. +0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. +0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. +0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. +0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. +0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. +0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. +0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. +0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. +0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. +0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. +0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. +0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. +0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. +Other values, reserved. + 18 + 6 + read-write + + + AESDIR + AES direction +1x1, AES Decryption +1x0, AES Encryption. + 16 + 1 + read-write + + + HASALG + HASH Algorithem selection. +0x0 SHA1 — +0x1 CRC32 — +0x2 SHA256 — + 12 + 4 + read-write + + + CRCEN + CRC enable. +1x1, CRC is enabled. +1x0, CRC is disabled. + 11 + 1 + read-write + + + HASCHK + HASH Check Enable Bit. +1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; +1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. +For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. + 10 + 1 + read-write + + + HASOUT + When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. +0 INPUT HASH +1 OUTPUT HASH + 9 + 1 + read-write + + + DINSWP + Decide whether the SDP byteswaps the input data (big-endian data); +When all bits are set, the data is assumed to be in the big-endian format + 4 + 2 + read-write + + + DOUTSWP + Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format + 2 + 2 + read-write + + + KEYSWP + Decide whether the SDP byteswaps the Key (big-endian data). +When all bits are set, the data is assumed to be in the big-endian format + 0 + 2 + read-write + + + + + PKTCNT + packet counter registers. + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + CNTVAL + This read-only field shows the current (instantaneous) value of the packet counter + 16 + 8 + read-only + + + CNTINCR + The value written to this field is added to the spacket count. + 0 + 8 + read-write + + + + + STA + Status Registers + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + TAG + packet tag. + 24 + 8 + read-only + + + IRQ + interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. + 23 + 1 + write-only + + + CHN1PKT0 + the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. + 20 + 1 + write-only + + + AESBSY + AES Busy + 19 + 1 + read-only + + + HASBSY + Hashing Busy + 18 + 1 + read-only + + + PKTCNT0 + Packet Counter registers reachs to ZERO now. + 17 + 1 + write-only + + + PKTDON + Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. + 16 + 1 + write-only + + + ERRSET + Working mode setup error. + 5 + 1 + write-only + + + ERRPKT + Packet head access error, or status update error. + 4 + 1 + write-only + + + ERRSRC + Source Buffer Access Error + 3 + 1 + write-only + + + ERRDST + Destination Buffer Error + 2 + 1 + write-only + + + ERRHAS + Hashing Check Error + 1 + 1 + write-only + + + ERRCHAIN + buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. + 0 + 1 + write-only + + + + + KEYADDR + Key Address + 0x10 + 32 + 0x00000040 + 0xFFFFFFFF + + + INDEX + To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. +Key index pointer. The valid indices are 0-[number_keys]. +In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. + 16 + 8 + read-write + + + SUBWRD + Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field +increments; To write a key, the software must first write the desired key index/subword to this register. + 0 + 2 + read-write + + + + + KEYDAT + Key Data + 0x14 + 32 + 0x00000030 + 0xFFFFFFFF + + + KEYDAT + This register provides the write access to the key/key subword specified by the key index register. +Writing this location updates the selected subword for the key located at the index +specified by the key index register. The write also triggers the SUBWORD field of the +KEY register to increment to the next higher word in the key + 0 + 32 + read-write + + + + + 4 + 0x4 + CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 + CIPHIV[%s] + no description available + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + CIPHIV + cipher initialization vector. + 0 + 32 + read-write + + + + + 8 + 0x4 + HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 + HASWRD[%s] + no description available + 0x28 + 32 + 0x00000030 + 0xFFFFFFFF + + + HASWRD + Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. +If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. + 0 + 32 + read-write + + + + + CMDPTR + Command Pointer + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + CMDPTR + current command addresses the register points to the multiword +descriptor that is to be executed (or is currently being executed) + 0 + 32 + read-write + + + + + NPKTPTR + Next Packet Address Pointer + 0x4c + 32 + 0x00000000 + 0xFFFFFFFF + + + NPKTPTR + Next Packet Address Pointer + 0 + 32 + read-write + + + + + PKTCTL + Packet Control Registers + 0x50 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTTAG + packet tag + 24 + 8 + read-write + + + CIPHIV + Load Initial Vector for the AES in this packet. + 6 + 1 + read-write + + + HASFNL + Hash Termination packet + 5 + 1 + read-write + + + HASINI + Hash Initialization packat + 4 + 1 + read-write + + + CHAIN + whether the next command pointer register must be loaded into the channel's current descriptor +pointer. + 3 + 1 + read-write + + + DCRSEMA + whether the channel's semaphore must be decremented at the end of the current operation. +When the semaphore reaches a value of zero, no more operations are issued from the channel. + 2 + 1 + read-write + + + PKTINT + Reflects whether the channel must issue an interrupt upon the completion of the packet + 1 + 1 + read-write + + + + + PKTSRC + Packet Memory Source Address + 0x54 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTSRC + Packet Memory Source Address + 0 + 32 + read-write + + + + + PKTDST + Packet Memory Destination Address + 0x58 + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTDST + Packet Memory Destination Address + 0 + 32 + read-write + + + + + PKTBUF + Packet buffer size. + 0x5c + 32 + 0x00000000 + 0xFFFFFFFF + + + PKTBUF + No description avaiable + 0 + 32 + read-write + + + + + + + SEC + SEC + SEC + 0xf3044000 + + 0x0 + 0x18 + registers + + + + SECURE_STATE + Secure state + 0x0 + 32 + 0x00000000 + 0x000300F0 + + + ALLOW_NSC + Non-secure state allow +0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter non-secure state + 17 + 1 + read-only + + + ALLOW_SEC + Secure state allow +0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state +1: system is healthy to enter secure state + 16 + 1 + read-only + + + PMIC_FAIL + PMIC secure state one hot indicator +0: secure state is not in fail state +1: secure state is in fail state + 7 + 1 + read-write + + + PMIC_NSC + PMIC secure state one hot indicator +0: secure state is not in non-secure state +1: secure state is in non-secure state + 6 + 1 + read-write + + + PMIC_SEC + PMIC secure state one hot indicator +0: secure state is not in secure state +1: secure state is in secure state + 5 + 1 + read-write + + + PMIC_INS + PMIC secure state one hot indicator +0: secure state is not in inspect state +1: secure state is in inspect state + 4 + 1 + read-write + + + + + SECURE_STATE_CONFIG + secure state configuration + 0x4 + 32 + 0x00000000 + 0x00000009 + + + LOCK + Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset +0: not locked, register can be modified +1: register locked, write access to the register is ignored + 3 + 1 + read-write + + + ALLOW_RESTART + allow secure state restart from fail state +0: restart is not allowed, only hardware reset can recover secure state +1: software is allowed to switch to inspect state from fail state + 0 + 1 + read-write + + + + + VIOLATION_CONFIG + Security violation config + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state violations, each bit represents one security event +0: event is not a security violation +1: event is a security violation + 0 + 15 + read-write + + + + + ESCALATE_CONFIG + Escalate behavior on security event + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK_NSC + Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 31 + 1 + read-write + + + NSC_VIO_CFG + configuration of non-secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 16 + 15 + read-write + + + LOCK_SEC + Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset +0: not locked, configuration can be modified +1: register locked, write access to the configuration is ignored + 15 + 1 + read-write + + + SEC_VIO_CFG + configuration of secure state escalates, each bit represents one security event +0: event is not a security escalate +1: event is a security escalate + 0 + 15 + read-write + + + + + EVENT + Event and escalate status + 0x10 + 32 + 0x00000000 + 0xFFFF000C + + + EVENT + local event statue, each bit represents one security event + 16 + 16 + read-only + + + PMIC_ESC_NSC + PMIC is escalating non-secure event + 3 + 1 + read-only + + + PMIC_ESC_SEC + PMIC is escalting secure event + 2 + 1 + read-only + + + + + LIFECYCLE + Lifecycle + 0x14 + 32 + 0x00000000 + 0x000000FF + + + LIFECYCLE + lifecycle status, +bit7: lifecycle_debate, +bit6: lifecycle_scribe, +bit5: lifecycle_no_ret, +bit4: lifecycle_return, +bit3: lifecycle_secure, +bit2: lifecycle_nonsec, +bit1: lifecycle_create, +bit0: lifecycle_unknow + 0 + 8 + read-only + + + + + + + MON + MON + MON + 0xf3048000 + + 0x0 + 0x48 + registers + + + + 4 + 0x8 + glitch0,glitch1,clock0,clock1 + MONITOR[%s] + no description available + 0x0 + + CONTROL + Glitch and clock monitor control + 0x0 + 32 + 0x00000000 + 0x00000011 + + + ACTIVE + select glitch works in active mode or passve mode. +0: passive mode, depends on power glitch destory DFF value +1: active mode, check glitch by DFF chain + 4 + 1 + read-write + + + ENABLE + enable glitch detector +0: detector disabled +1: detector enabled + 0 + 1 + read-write + + + + + STATUS + Glitch and clock monitor status + 0x4 + 32 + 0x00000000 + 0x00000001 + + + FLAG + flag for glitch detected, write 1 to clear this flag +0: glitch not detected +1: glitch detected + 0 + 1 + read-write + + + + + + IRQ_FLAG + No description avaiable + 0x40 + 32 + 0x00000000 + 0x0000000F + + + FLAG + interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag +0: no monitor interrupt +1: monitor interrupt happened + 0 + 4 + read-write + + + + + IRQ_ENABLE + No description avaiable + 0x44 + 32 + 0x00000000 + 0x0000000F + + + ENABLE + interrupt enable, each bit represents for one monitor +0: monitor interrupt disabled +1: monitor interrupt enabled + 0 + 4 + read-write + + + + + + + RNG + RNG + RNG + 0xf304c000 + + 0x0 + 0x40 + registers + + + + CMD + Command Register + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SFTRST + Soft Reset, Perform a software reset of the RNG This bit is self-clearing. +0 Do not perform a software reset. +1 Software reset + 6 + 1 + read-write + + + CLRERR + Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. +0 Do not clear the errors and the interrupt. +1 Clear the errors and the interrupt. + 5 + 1 + read-write + + + CLRINT + Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. +0 Do not clear the interrupt. +1 Clear the interrupt + 4 + 1 + read-write + + + GENSD + Generate Seed, when both ST and GS triggered, ST first and GS next. + 1 + 1 + read-write + + + SLFCHK + Self Test, when both ST and GS triggered, ST first and GS next. + 0 + 1 + read-write + + + + + CTRL + Control Register + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + MIRQERR + Mask Interrupt Request for Error + 6 + 1 + read-write + + + MIRQDN + Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: +• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). +• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. + 5 + 1 + read-write + + + AUTRSD + Auto Reseed + 4 + 1 + read-write + + + FUFMOD + FIFO underflow response mode +00 Return all zeros and set the ESR[FUFE]. +01 Return all zeros and set the ESR[FUFE]. +10 Generate the bus transfer error +11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). + 0 + 2 + read-write + + + + + STA + Status Register + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + SCPF + Self Check Pass Fail + 21 + 3 + read-only + + + FUNCERR + Error was detected, check ESR register for details + 16 + 1 + read-only + + + FSIZE + Fifo Size, it is 5 in this design. + 12 + 4 + read-only + + + FRNNU + Fifo Level, Indicates the number of random words currently in the output FIFO + 8 + 4 + read-only + + + NSDDN + New seed done. + 6 + 1 + read-only + + + FSDDN + 1st Seed done +When "1", Indicates that the RNG generated the first seed. + 5 + 1 + read-only + + + SCDN + Self Check Done +Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is +initiated by setting the CMD[ST]. +0 Self test not completed +1 Completed a self test since the last reset. + 4 + 1 + read-only + + + RSDREQ + Reseed needed +Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or +automatically if the CTRL[ARS] is set. + 3 + 1 + read-only + + + IDLE + Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. + 2 + 1 + read-only + + + BUSY + when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. + 1 + 1 + read-only + + + + + ERR + Error Registers + 0xc + 32 + 0x00000000 + 0xFFFFFF3F + + + FUFE + FIFO access error(underflow) + 5 + 1 + read-only + + + SCKERR + Self-test error +Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a +hardware reset or by writing 1 to the CMD[CE] + 3 + 1 + read-only + + + + + FO2B + FIFO out to bus/cpu + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2B + SW read the FIFO output. + 0 + 32 + read-only + + + + + 8 + 0x4 + FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 + R2SK[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + FO2S0 + FIFO out to KMAN, will be SDP engine key. + 0 + 32 + read-only + + + + + + + OTP + OTP + OTP + 0xf3050000 + + 0x0 + 0xc08 + registers + + + + 128 + 0x4 + SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 + SHADOW[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + SHADOW + shadow register of fuse for pmic area +for PMIC, index valid for 0-15, for SOC index valid for 16-128 + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + SHADOW_LOCK[%s] + no description available + 0x200 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + 128 + 0x4 + FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 + FUSE[%s] + no description available + 0x400 + 32 + 0x00000000 + 0xFFFFFFFF + + + FUSE + fuse array, valid in PMIC part only +read operation will read out value in fuse array +write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) + 0 + 32 + read-write + + + + + 8 + 0x4 + LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 + FUSE_LOCK[%s] + no description available + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + LOCK + lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types +00: not locked +01: soft locked +10: not locked, and cannot lock in furture +11: double locked + 0 + 32 + read-write + + + + + UNLOCK + UNLOCK + 0x800 + 32 + 0x00000000 + 0xFFFFFFFF + + + UNLOCK + unlock word for fuse array operation +write "OPEN" to unlock fuse array, write any other value will lock write to fuse. +Please make sure 24M crystal is running and 2.5V LDO working properly + 0 + 32 + read-write + + + + + DATA + DATA + 0x804 + 32 + 0x00000000 + 0xFFFFFFFF + + + DATA + data register for non-blocking access +this register hold dat read from fuse array or data to by programmed to fuse array + 0 + 32 + read-write + + + + + ADDR + ADDR + 0x808 + 32 + 0x00000000 + 0x0000007F + + + ADDR + word address to be read or write + 0 + 7 + read-write + + + + + CMD + CMD + 0x80c + 32 + 0x00000000 + 0xFFFFFFFF + + + CMD + command to access fure array +"BLOW" will update fuse word at ADDR to value hold in DATA +"READ" will fetch fuse value in at ADDR to DATA register + 0 + 32 + read-write + + + + + LOAD_REQ + LOAD Request + 0xa00 + 32 + 0x00000007 + 0x0000000F + + + REQUEST + reload request for 4 regions +bit0: region0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + LOAD_COMP + LOAD complete + 0xa04 + 32 + 0x00000007 + 0x0000000F + + + COMPLETE + reload complete sign for 4 regions +bit0: region 0 +bit1: region1 +bit2: region2 +bit3: region3 + 0 + 4 + read-write + + + + + 4 + 0x4 + LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 + REGION[%s] + no description available + 0xa20 + 32 + 0x00000800 + 0x00007F7F + + + STOP + stop address of load region, fuse word at end address will NOT be reloaded +region0: fixed at 8 +region1: fixed at 16 +region2: fixed at 0, +region3: usrer configurable + 8 + 7 + read-write + + + START + start address of load region, fuse word at start address will be reloaded +region0: fixed at 0 +region1: fixed at 8 +region2: fixed at 16, +region3: usrer configurable + 0 + 7 + read-write + + + + + INT_FLAG + interrupt flag + 0xc00 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write flag, write 1 to clear +0: fuse is not written or writing +1: value in DATA register is programmed into fuse + 2 + 1 + read-write + + + READ + fuse read flag, write 1 to clear +0: fuse is not read or reading +1: fuse value is put in DATA register + 1 + 1 + read-write + + + LOAD + fuse load flag, write 1 to clear +0: fuse is not loaded or loading +1: fuse loaded + 0 + 1 + read-write + + + + + INT_EN + interrupt enable + 0xc04 + 32 + 0x00000000 + 0x00000007 + + + WRITE + fuse write interrupt enable +0: fuse write interrupt is not enable +1: fuse write interrupt is enable + 2 + 1 + read-write + + + READ + fuse read interrupt enable +0: fuse read interrupt is not enable +1: fuse read interrupt is enable + 1 + 1 + read-write + + + LOAD + fuse load interrupt enable +0: fuse load interrupt is not enable +1: fuse load interrupt is enable + 0 + 1 + read-write + + + + + + + KEYM + KEYM + KEYM + 0xf3054000 + + 0x0 + 0x50 + registers + + + + 8 + 0x4 + SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 + SOFTMKEY[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software symmetric key +key will be scambled to 4 variants for software to use, and replicable on same chip. +scramble keys are chip different, and not replicable on different chip +must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 + 0 + 32 + read-write + + + + + 8 + 0x4 + SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 + SOFTPKEY[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + KEY + software asymmetric key +key is derived from scrambles of fuse private key, software input key, SRK, and system security status. +This key os read once, sencondary read will read out 0 + 0 + 32 + read-write + + + + + SEC_KEY_CTL + secure key generation + 0x40 + 32 + 0x00000000 + 0x80011117 + + + LOCK_SEC_CTL + block secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use origin value in software symmetric key +1: use scramble version of software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use alnertave scramble of fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + secure symmtric key synthesize setting, key is a XOR of followings +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + NSC_KEY_CTL + non-secure key generation + 0x44 + 32 + 0x00000000 + 0x80011117 + + + LOCK_NSC_CTL + block non-secure state key setting being changed + 31 + 1 + read-write + + + SK_VAL + session key valid +0: session key is all 0's and not usable +1: session key is valid + 16 + 1 + read-only + + + SMK_SEL + software symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 12 + 1 + read-write + + + ZMK_SEL + batt symmetric key selection +0: use scramble version of software symmetric key +1: use origin value in software symmetric key + 8 + 1 + read-write + + + FMK_SEL + fuse symmetric key selection +0: use scramble version of fuse symmetric key +1: use origin value in fuse symmetric key + 4 + 1 + read-write + + + KEY_SEL + non-secure symmtric key synthesize setting, key is a XOR of followings +bit0: fuse mk, 0: not selected, 1:selected +bit1: zmk from batt, 0: not selected, 1:selected +bit2: software key 0: not selected, 1:selected + 0 + 3 + read-write + + + + + RNG + Random number interface behavior + 0x48 + 32 + 0x00000000 + 0x00010001 + + + BLOCK_RNG_XOR + block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset +0: RNG_XOR can be changed by software +1: RNG_XOR ignore software change from software + 16 + 1 + read-write + + + RNG_XOR + control how SFK is accepted from random number generator +0: SFK value replaced by random number input +1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG + 0 + 1 + read-write + + + + + READ_CONTROL + key read out control + 0x4c + 32 + 0x00000000 + 0x00010001 + + + BLOCK_PK_READ + asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 16 + 1 + read-write + + + BLOCK_SMK_READ + symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset +0: key can be read out +1: key cannot be read out + 0 + 1 + read-write + + + + + + + ADC0 + ADC0 + ADC16 + 0xf3080000 + + 0x0 + 0x1464 + registers + + + + 12 + 0x4 + trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c + CONFIG[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xFF3F3F7F + + + TRIG_LEN + length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 + 30 + 2 + write-only + + + INTEN3 + interupt enable for 4th conversion + 29 + 1 + read-write + + + CHAN3 + channel number for 4th conversion + 24 + 5 + read-write + + + INTEN2 + interupt enable for 3rd conversion + 21 + 1 + read-write + + + CHAN2 + channel number for 3rd conversion + 16 + 5 + read-write + + + INTEN1 + interupt enable for 2nd conversion + 13 + 1 + read-write + + + CHAN1 + channel number for 2nd conversion + 8 + 5 + read-write + + + QUEUE_EN + preemption queue enable control + 6 + 1 + read-write + + + INTEN0 + interupt enable for 1st conversion + 5 + 1 + read-write + + + CHAN0 + channel number for 1st conversion + 0 + 5 + read-write + + + + + trg_dma_addr + No description avaiable + 0x30 + 32 + 0x00000000 + 0xFFFFFFFC + + + TRG_DMA_ADDR + buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) + 2 + 30 + read-write + + + + + trg_sw_sta + No description avaiable + 0x34 + 32 + 0x00000000 + 0x0000001F + + + TRG_SW_STA + SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. + 4 + 1 + read-write + + + TRIG_SW_INDEX + which trigger for the SW trigger +0 for trig0a, 1 for trig0b… +3 for trig1a, …11 for trig3c + 0 + 4 + read-write + + + + + 16 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + BUS_RESULT[%s] + no description available + 0x400 + 32 + 0x00000000 + 0x0001FFFF + + + VALID + set after conversion finished if wait_dis is set, cleared after software read. +The first time read with 0 will trigger one new conversion. +If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. +the result may not realtime if software read once and wait long time to read again + 16 + 1 + read-only + + + CHAN_RESULT + read this register will trigger one adc conversion. +If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result +If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long + 0 + 16 + read-only + + + + + buf_cfg0 + No description avaiable + 0x500 + 32 + 0x00000000 + 0x00000003 + + + BUS_MODE_EN + bus mode enable + 1 + 1 + read-write + + + WAIT_DIS + set to disable read waiting, get result immediately but maybe not current conversion result. + 0 + 1 + read-write + + + + + seq_cfg0 + No description avaiable + 0x800 + 32 + 0x00000000 + 0x80000F1F + + + CYCLE + current dma write cycle bit + 31 + 1 + read-only + + + SEQ_LEN + sequence queue length, 0 for one, 0xF for 16 + 8 + 4 + read-write + + + RESTART_EN + if set together with cont_en, HW will continue process the whole queue after trigger once. +If cont_en is 0, this bit is not used + 4 + 1 + read-write + + + CONT_EN + if set, HW will continue process the queue till end(seq_len) after trigger once + 3 + 1 + read-write + + + SW_TRIG + SW trigger, pulse signal, cleared by HW one cycle later + 2 + 1 + write-only + + + SW_TRIG_EN + set to enable SW trigger + 1 + 1 + read-write + + + HW_TRIG_EN + set to enable external HW trigger, only trigger on posedge + 0 + 1 + read-write + + + + + seq_dma_addr + No description avaiable + 0x804 + 32 + 0x00000000 + 0xFFFFFFFC + + + TAR_ADDR + dma target address, should be 4-byte aligned + 2 + 30 + read-write + + + + + seq_wr_addr + No description avaiable + 0x808 + 32 + 0x00000000 + 0x00FFFFFF + + + SEQ_WR_POINTER + HW update this field after each dma write, it indicate the next dma write pointer. +dma write address is (tar_addr+seq_wr_pointer)*4 + 0 + 24 + read-only + + + + + seq_dma_cfg + No description avaiable + 0x80c + 32 + 0x00000000 + 0x0FFF3FFF + + + STOP_POS + if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet + 16 + 12 + read-write + + + DMA_RST + set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. +SW should clear all cycle bit in buffer to 0 before clear dma_rst + 13 + 1 + read-write + + + STOP_EN + set to stop dma if reach the stop_pos + 12 + 1 + read-write + + + BUF_LEN + dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 +0 for 4byte; +0xFFF for 16kbyte. + 0 + 12 + read-write + + + + + 16 + 0x4 + cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 + SEQ_QUE[%s] + no description available + 0x810 + 32 + 0x00000000 + 0x0000003F + + + SEQ_INT_EN + interrupt enable for current conversion + 5 + 1 + read-write + + + CHAN_NUM_4_0 + channel number for current conversion + 0 + 5 + read-write + + + + + seq_high_cfg + No description avaiable + 0x850 + 32 + 0x00000000 + 0x00FFFFFF + + + STOP_POS_HIGH + No description avaiable + 12 + 12 + read-write + + + BUF_LEN_HIGH + No description avaiable + 0 + 12 + read-write + + + + + 16 + 0x10 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + PRD_CFG[%s] + no description available + 0xc00 + + prd_cfg + No description avaiable + 0x0 + 32 + 0x00000000 + 0x00001FFF + + + PRESCALE + 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx + 8 + 5 + read-write + + + PRD + conver period, with prescale. +Set to 0 means disable current channel + 0 + 8 + read-write + + + + + prd_thshd_cfg + No description avaiable + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + THSHDH + threshold high, assert interrupt(if enabled) if result exceed high or low. + 16 + 16 + read-write + + + THSHDL + threshold low + 0 + 16 + read-write + + + + + prd_result + No description avaiable + 0x8 + 32 + 0x00000000 + 0x0000FFFF + + + CHAN_RESULT + adc convert result, update after each valid conversion. +it may be updated period according to config, also may be updated due to other queue convert the same channel + 0 + 16 + read-only + + + + + + 16 + 0x4 + chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 + SAMPLE_CFG[%s] + no description available + 0x1000 + 32 + 0x00000000 + 0x00000FFF + + + SAMPLE_CLOCK_NUMBER_SHIFT + shift for sample clock number + 9 + 3 + read-write + + + SAMPLE_CLOCK_NUMBER + sample clock number, base on clock_period, default one period + 0 + 9 + read-write + + + + + conv_cfg1 + No description avaiable + 0x1104 + 32 + 0x00000000 + 0x000001FF + + + CONVERT_CLOCK_NUMBER + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); +user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. +Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz). + 4 + 5 + read-write + + + CLOCK_DIVIDER + clock_period, N half clock cycle per half adc cycle +0 for same adc_clk and bus_clk, +1 for 1:2, +2 for 1:3, +... +15 for 1:16 +Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk + 0 + 4 + read-write + + + + + adc_cfg0 + No description avaiable + 0x1108 + 32 + 0x00000000 + 0xAFFFF001 + + + SEL_SYNC_AHB + set to 1 will enable sync AHB bus, to get better bus performance. +Adc_clk must to be set to same as bus clock at this mode + 31 + 1 + read-write + + + ADC_AHB_EN + set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; + 29 + 1 + read-write + + + CONVERT_DURATION + for trigger queue, from trg_sample_req to trg_convert_req + 12 + 16 + read-write + + + PORT3_REALTIME + set to enable trg queue stop other queues + 0 + 1 + read-write + + + + + int_sts + No description avaiable + 0x1110 + 32 + 0x00000000 + 0xFFE03FFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description avaiable + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description avaiable + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrup, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description avaiable + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 14 + read-write + + + + + int_en + No description avaiable + 0x1114 + 32 + 0x00000000 + 0xFFE03FFF + + + TRIG_CMPT + interrupt for one trigger conversion complete if enabled + 31 + 1 + read-write + + + TRIG_SW_CFLCT + No description avaiable + 30 + 1 + read-write + + + TRIG_HW_CFLCT + No description avaiable + 29 + 1 + read-write + + + READ_CFLCT + read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel + 28 + 1 + read-write + + + SEQ_SW_CFLCT + sequence queue conflict interrup, set if HW or SW trigger received during conversion + 27 + 1 + read-write + + + SEQ_HW_CFLCT + No description avaiable + 26 + 1 + read-write + + + SEQ_DMAABT + dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set + 25 + 1 + read-write + + + SEQ_CMPT + the whole sequence complete interrupt + 24 + 1 + read-write + + + SEQ_CVC + one conversion complete in seq_queue if related seq_int_en is set + 23 + 1 + read-write + + + DMA_FIFO_FULL + DMA fifo full interrupt, user need to check clock frequency if it's set. + 22 + 1 + read-write + + + AHB_ERR + set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr + 21 + 1 + read-write + + + WDOG + set if one chanel watch dog event triggered + 0 + 14 + read-write + + + + + ana_ctrl0 + No description avaiable + 0x1200 + 32 + 0x00000000 + 0x80001004 + + + MOTO_EN + "set to enable moto_soc and moto_valid. +Should use AHB clock for adc, this bit can be used avoid async output" + 31 + 1 + read-write + + + ADC_CLK_ON + set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. +MUST set clock_period to 0 or 1 for adc16 reg access + 12 + 1 + read-write + + + STARTCAL + set to start the offset calibration cycle (Active H). user need to clear it after setting it. + 2 + 1 + read-write + + + + + ana_status + No description avaiable + 0x1210 + 32 + 0x00000000 + 0x00000080 + + + CALON + Indicates if the ADC is in calibration mode (Active H). + 7 + 1 + read-write + + + + + 34 + 0x2 + adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 + ADC16_PARAMS[%s] + no description available + 0x1400 + 16 + 0x0000 + 0xFFFF + + + PARAM_VAL + No description avaiable + 0 + 16 + read-write + + + + + adc16_config0 + No description avaiable + 0x1444 + 32 + 0x00000000 + 0x01F07FFF + + + REG_EN + set to enable regulator + 24 + 1 + read-write + + + BANDGAP_EN + set to enable bandgap. user should set reg_en and bandgap_en before use adc16. + 23 + 1 + read-write + + + CAL_AVG_CFG + for average the calibration result. +0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; +4- 16 loops; 5-32 loops; others reserved + 20 + 3 + read-write + + + PREEMPT_EN + set to enable preemption feature + 14 + 1 + read-write + + + CONV_PARAM + convertion parameter + 0 + 14 + read-write + + + + + adc16_config1 + No description avaiable + 0x1460 + 32 + 0x00000000 + 0x00001F00 + + + COV_END_CNT + used for faster conversion, user can change it to get higher convert speed(but less accuracy). +should set to (21-convert_clock_number+1). + 8 + 5 + read-write + + + + + + + ADC1 + ADC1 + ADC16 + 0xf3084000 + + + DAC0 + DAC0 + DAC + 0xf3090000 + + 0x0 + 0x4c + registers + + + + cfg0 + No description avaiable + 0x0 + 32 + 0x00000000 + 0x0FFF03FF + + + SW_DAC_DATA + dac data used in direct mode(dac_mode==2'b10) + 16 + 12 + write-only + + + DMA_AHB_EN + set to enable internal DMA, it will read one burst if enough space in FIFO. +Should only be used in buffer mode. + 9 + 1 + write-only + + + SYNC_MODE + 1: sync dac clock and ahb clock. + all HW trigger signals are pulse in sync mode, can get faster response; +0: async dac clock and ahb_clock + all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + 8 + 1 + write-only + + + TRIG_MODE + 0: single mode, one trigger pulse will send one 12bit data to DAC analog; +1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + 7 + 1 + write-only + + + HW_TRIG_EN + set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + 6 + 1 + write-only + + + DAC_MODE + 00: direct mode, DAC output the fixed configured data(from sw_dac_data) +01: step mode, DAC output from start_point to end point, with configured step, can step up or step down +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; +11: trigger mode, DAC output from external trigger signals +Note: +Trigger mode is not supported in hpm63xx and hpm62xx families. + 4 + 2 + write-only + + + BUF_DATA_MODE + data structure for buffer mode, +0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. +1: each 32-bit data contains 1 point, b11:0 for first + 3 + 1 + write-only + + + HBURST_CFG + DAC support following fixed burst only +000-SINGLE; 011-INCR4; 101: INCR8 +others are reserved + 0 + 3 + write-only + + + + + cfg1 + No description avaiable + 0x4 + 32 + 0x00010000 + 0x0007FFFF + + + ANA_CLK_EN + set to enable analog clock(divided by ana_div_cfg) +need to be set in direct mode and trigger mode + 18 + 1 + read-write + + + ANA_DIV_CFG + clock divider config for ana_clk to dac analog; +00: div2 +01: div4 +10: div6 +11: div8 + 16 + 2 + read-write + + + DIV_CFG + step mode and buffer mode: + defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. +Direct mode and trigger mode: + defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. +Note: +For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. + 0 + 16 + read-write + + + + + cfg2 + No description avaiable + 0x8 + 32 + 0x00000000 + 0x000000FF + + + DMA_RST1 + set to reset dma read pointer to buf1_start_addr; +if set both dma_rst0&dma_rst1, will set to buf0_start_addr +user can set fifo_clr bit when use dma_rst* + 7 + 1 + write-only + + + DMA_RST0 + set to reset dma read pointer to buf0_start_addr + 6 + 1 + write-only + + + FIFO_CLR + set to clear FIFO content(set both read/write pointer to 0) + 5 + 1 + write-only + + + BUF_SW_TRIG + software trigger for buffer mode, +W1C in single mode. +RW in continual mode + 4 + 1 + read-write + + + STEP_SW_TRIG3 + No description avaiable + 3 + 1 + read-write + + + STEP_SW_TRIG2 + No description avaiable + 2 + 1 + read-write + + + STEP_SW_TRIG1 + No description avaiable + 1 + 1 + read-write + + + STEP_SW_TRIG0 + software trigger0 for step mode, +W1C in single mode. +RW in continual mode + 0 + 1 + read-write + + + + + 4 + 0x4 + step0,step1,step2,step3 + STEP_CFG[%s] + no description available + 0x10 + 32 + 0x00000000 + 0x3FFFFFFF + + + ROUND_MODE + 0: stop at end point; +1: reload start point, step again + 29 + 1 + read-write + + + UP_DOWN + 0 for up, 1 for down + 28 + 1 + read-write + + + END_POINT + No description avaiable + 16 + 12 + read-write + + + STEP_NUM + output data change step_num each DAC clock cycle. +Ex: if step_num=3, output data sequence is 0,3,6,9 +NOTE: user should make sure end_point can be reached if step_num is not 1 +if step_num is 0, output data will always at start point + 12 + 4 + read-write + + + START_POINT + No description avaiable + 0 + 12 + read-write + + + + + 2 + 0x4 + buf0,buf1 + BUF_ADDR[%s] + no description available + 0x20 + 32 + 0x00000000 + 0xFFFFFFFD + + + BUF_START_ADDR + buffer start address, should be 4-byte aligned +AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. + 2 + 30 + read-write + + + BUF_STOP + set to stop read point at end of bufffer0 + 0 + 1 + read-write + + + + + buf_length + No description avaiable + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + BUF1_LEN + buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer + 16 + 16 + read-write + + + BUF0_LEN + No description avaiable + 0 + 16 + read-write + + + + + irq_sts + No description avaiable + 0x30 + 32 + 0x00000000 + 0x0000001F + + + STEP_CMPT + No description avaiable + 4 + 1 + write-only + + + AHB_ERROR + set if hresp==2'b01(ERROR) + 3 + 1 + write-only + + + FIFO_EMPTY + No description avaiable + 2 + 1 + write-only + + + BUF1_CMPT + No description avaiable + 1 + 1 + write-only + + + BUF0_CMPT + No description avaiable + 0 + 1 + write-only + + + + + irq_en + No description avaiable + 0x34 + 32 + 0x00000000 + 0x0000001F + + + STEP_CMPT + No description avaiable + 4 + 1 + read-write + + + AHB_ERROR + No description avaiable + 3 + 1 + read-write + + + FIFO_EMPTY + No description avaiable + 2 + 1 + read-write + + + BUF1_CMPT + No description avaiable + 1 + 1 + read-write + + + BUF0_CMPT + No description avaiable + 0 + 1 + read-write + + + + + dma_en + No description avaiable + 0x38 + 32 + 0x00000000 + 0x00000013 + + + STEP_CMPT + No description avaiable + 4 + 1 + read-write + + + BUF1_CMPT + No description avaiable + 1 + 1 + read-write + + + BUF0_CMPT + No description avaiable + 0 + 1 + read-write + + + + + ana_cfg0 + No description avaiable + 0x40 + 32 + 0x00000030 + 0x000001FF + + + DAC12BIT_LP_MODE + No description avaiable + 8 + 1 + read-write + + + DAC_CONFIG + No description avaiable + 4 + 4 + read-write + + + CALI_DELTA_V_CFG + No description avaiable + 2 + 2 + read-write + + + BYPASS_CALI_GM + No description avaiable + 1 + 1 + read-write + + + DAC12BIT_EN + No description avaiable + 0 + 1 + read-write + + + + + cfg0_bak + No description avaiable + 0x44 + 32 + 0x00000000 + 0x0FFF03FF + + + SW_DAC_DATA + dac data used in direct mode(dac_mode==2'b10) + 16 + 12 + read-write + + + DMA_AHB_EN + set to enable internal DMA, it will read one burst if enough space in FIFO. +Should only be used in buffer mode. + 9 + 1 + read-write + + + SYNC_MODE + 1: sync dac clock and ahb clock. + all HW trigger signals are pulse in sync mode, can get faster response; +0: async dac clock and ahb_clock + all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) + 8 + 1 + read-write + + + TRIG_MODE + 0: single mode, one trigger pulse will send one 12bit data to DAC analog; +1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. + 7 + 1 + read-write + + + HW_TRIG_EN + set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode + 6 + 1 + read-write + + + DAC_MODE + 00: direct mode, DAC output the fixed configured data(from sw_dac_data) +01: step mode, DAC output from start_point to end point, with configured step, can step up or step down +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; + 4 + 2 + read-write + + + BUF_DATA_MODE + data structure for buffer mode, +0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. +1: each 32-bit data contains 1 point, b11:0 for first + 3 + 1 + read-write + + + HBURST_CFG + DAC support following fixed burst only +000-SINGLE; 011-INCR4; 101: INCR8 +others are reserved + 0 + 3 + read-write + + + + + status0 + No description avaiable + 0x48 + 32 + 0x00000000 + 0x00FFFF80 + + + CUR_BUF_OFFSET + No description avaiable + 8 + 16 + read-write + + + CUR_BUF_INDEX + No description avaiable + 7 + 1 + read-write + + + + + + + DAC1 + DAC1 + DAC + 0xf3094000 + + + OPAMP0 + OPAMP0 + OPAMP + 0xf30a0000 + + 0x0 + 0x90 + registers + + + + ctrl0 + control reg + 0x0 + 32 + 0x00000000 + 0x07FFFFFF + + + EN_LV + No description avaiable + 26 + 1 + read-write + + + OPAOUT_SEL + No description avaiable + 24 + 2 + read-write + + + VSWITCH_SEL + No description avaiable + 21 + 3 + read-write + + + ISEL + No description avaiable + 19 + 2 + read-write + + + VIM_SEL + No description avaiable + 16 + 3 + read-write + + + GPA_SEL + No description avaiable + 8 + 8 + read-write + + + CSEL + No description avaiable + 4 + 4 + read-write + + + VBYPASS + No description avaiable + 3 + 1 + read-write + + + VIP_SEL + No description avaiable + 0 + 3 + read-write + + + + + status + status reg + 0x4 + 32 + 0x00000000 + 0x0FFF0000 + + + TRIG_CONFLICT + if more than one hardware trigger is set, will put all trigger input here; +write any value to clear + 20 + 8 + read-write + + + PRESET_ACT + 1 for preset active; one of cur_preset is selected for OPAMP; +0 for no preset, OPAMP use cfg0 parameters + 19 + 1 + read-only + + + CUR_PRESET + current selected preset + 16 + 3 + read-only + + + + + ctrl1 + control reg1 + 0x8 + 32 + 0x00000000 + 0x80000007 + + + SW_PRESET + set to use preset defined by sw_sel. +NOTE: when set, the hardware trigger will not be used + 31 + 1 + read-write + + + SW_SEL + No description avaiable + 0 + 3 + read-write + + + + + 8 + 0x10 + preset0,preset1,preset2,preset3,preset4,preset5,preset6,preset7 + CFG[%s] + no description available + 0x10 + + cfg0 + No description avaiable + 0x0 + 32 + 0x00000000 + 0x0F070707 + + + CSEL + No description avaiable + 24 + 4 + read-write + + + VSWITCH_SEL + No description avaiable + 16 + 3 + read-write + + + VIM_SEL + No description avaiable + 8 + 3 + read-write + + + VIP_SEL + No description avaiable + 0 + 3 + read-write + + + + + cfg1 + No description avaiable + 0x4 + 32 + 0x00000000 + 0xE30300FF + + + HW_TRIG_EN + set to enable hardware trigger from moto system. +NOTE: when sw_preset is enabled, this bit will not take effert + 31 + 1 + read-write + + + EN_LV + No description avaiable + 30 + 1 + read-write + + + VBYPASS_LV + No description avaiable + 29 + 1 + read-write + + + OPAOUT_SEL + No description avaiable + 24 + 2 + read-write + + + ISEL + No description avaiable + 16 + 2 + read-write + + + PGA_SEL + No description avaiable + 0 + 8 + read-write + + + + + cfg2 + No description avaiable + 0x8 + 32 + 0x00000000 + 0x07000000 + + + CHANNEL + No description avaiable + 24 + 3 + read-write + + + + + + + + OPAMP1 + OPAMP1 + OPAMP + 0xf30a4000 + + + ACMP + ACMP + ACMP + 0xf30b0000 + + 0x0 + 0x80 + registers + + + + 4 + 0x20 + chn0,chn1,chn2,chn3 + CHANNEL[%s] + no description available + 0x0 + + cfg + Configure Register + 0x0 + 32 + 0x00000000 + 0xFF7FFFFF + + + HYST + This bitfield configure the comparator hysteresis. +00: Hysteresis level 0 +01: Hysteresis level 1 +10: Hysteresis level 2 +11: Hysteresis level 3 + 30 + 2 + read-write + + + DACEN + This bit enable the comparator internal DAC +0: DAC disabled +1: DAC enabled + 29 + 1 + read-write + + + HPMODE + This bit enable the comparator high performance mode. +0: HP mode disabled +1: HP mode enabled + 28 + 1 + read-write + + + CMPEN + This bit enable the comparator. +0: ACMP disabled +1: ACMP enabled + 27 + 1 + read-write + + + MINSEL + PIN select, from pad_ai_acmp[7:1] and dac_out + 24 + 3 + read-write + + + PINSEL + MIN select, from pad_ai_acmp[7:1] and dac_out + 20 + 3 + read-write + + + CMPOEN + This bit enable the comparator output on pad. +0: ACMP output disabled +1: ACMP output enabled + 19 + 1 + read-write + + + FLTBYPS + This bit bypass the comparator output digital filter. +0: The ACMP output need pass digital filter +1: The ACMP output digital filter is bypassed. + 18 + 1 + read-write + + + WINEN + This bit enable the comparator window mode. +0: Window mode is disabled +1: Window mode is enabled + 17 + 1 + read-write + + + OPOL + The output polarity control bit. +0: The ACMP output remain un-changed. +1: The ACMP output is inverted. + 16 + 1 + read-write + + + FLTMODE + This bitfield define the ACMP output digital filter mode: +000-bypass +100-change immediately; +101-change after filter; +110-stalbe low; +111-stable high + 13 + 3 + read-write + + + SYNCEN + This bit enable the comparator output synchronization. +0: ACMP output not synchronized with ACMP clock. +1: ACMP output synchronized with ACMP clock. + 12 + 1 + read-write + + + FLTLEN + This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. + 0 + 12 + read-write + + + + + daccfg + DAC configure register + 0x4 + 32 + 0x00000000 + 0x000000FF + + + DACCFG + 8bit DAC digital value + 0 + 8 + read-write + + + + + sr + Status register + 0x10 + 32 + 0x00000000 + 0x00000003 + + + FEDGF + Output falling edge flag. Write 1 to clear this flag. + 1 + 1 + read-write + + + REDGF + Output rising edge flag. Write 1 to clear this flag. + 0 + 1 + read-write + + + + + irqen + Interrupt request enable register + 0x14 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag interrupt enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag interrupt enable bit. + 0 + 1 + read-write + + + + + dmaen + DMA request enable register + 0x18 + 32 + 0x00000000 + 0x00000003 + + + FEDGEN + Output falling edge flag DMA request enable bit. + 1 + 1 + read-write + + + REDGEN + Output rising edge flag DMA request enable bit. + 0 + 1 + read-write + + + + + + + + SYSCTL + SYSCTL + SYSCTL + 0xf4000000 + + 0x0 + 0x2c00 + registers + + + + 113 + 0x4 + cpu0,cpx0,pow_cpu0,rst_soc,rst_cpu0,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_clk2_pll1,clk_src_clk3_pll1,clk_src_pll0_ref,clk_src_pll1_ref,clk_top_cpu0,clk_top_mct0,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_xpi0,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ref0,clk_top_ref1,clk_top_adc0,clk_top_adc1,clk_top_dac0,clk_top_dac1,ahb0,lmm0,mct0,rom0,can0,can1,can2,can3,ptpc,lin0,lin1,lin2,lin3,tmr0,tmr1,tmr2,tmr3,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,wdg0,wdg1,mbx0,tsns,crc0,adc0,adc1,dac0,dac1,acmp,opa0,opa1,mot0,rng0,sdp0,kman,gpio,hdma,xpi0,usb0,ref0,ref1 + RESOURCE[%s] + no description available + 0x0 + 32 + 0x00000000 + 0xC0000003 + + + GLB_BUSY + global busy +0: no changes pending to any nodes +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: no change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + MODE + resource work mode +0:auto turn on and off as system required(recommended) +1:always on +2:always off +3:reserved + 0 + 2 + read-write + + + + + 2 + 0x10 + link0,link1 + GROUP0[%s] + no description available + 0x800 + + VALUE + Group setting + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: peripheral is not needed +1: periphera is needed + 0 + 32 + read-write + + + + + SET + Group setting + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: add periphera into this group，periphera is needed + 0 + 32 + read-write + + + + + CLEAR + Group setting + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: delete periphera in this group，periphera is not needed + 0 + 32 + read-write + + + + + TOGGLE + Group setting + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + LINK + denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral +0: no effect +1: toggle the result that whether periphera is needed before + 0 + 32 + read-write + + + + + + 1 + 0x10 + cpu0 + AFFILIATE[%s] + no description available + 0x900 + + VALUE + Affiliate of Group + 0x0 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +bit0: cpu0 depends on group0 +bit1: cpu0 depends on group1 +bit2: cpu0 depends on group2 +bit3: cpu0 depends on group3 + 0 + 4 + read-write + + + + + SET + Affiliate of Group + 0x4 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0，each bit represents a group +0: no effect +1: the group is assigned to CPU0 + 0 + 4 + read-write + + + + + CLEAR + Affiliate of Group + 0x8 + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: the group is not assigned to CPU0 + 0 + 4 + read-write + + + + + TOGGLE + Affiliate of Group + 0xc + 32 + 0x00000000 + 0x0000000F + + + LINK + Affiliate groups of cpu0, each bit represents a group +0: no effect +1: toggle the result that whether the group is assigned to CPU0 before + 0 + 4 + read-write + + + + + + 1 + 0x10 + cpu0 + RETENTION[%s] + no description available + 0x920 + + VALUE + Retention Contol + 0x0 + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +bit00: soc_mem is kept on while cpu0 stop +bit01: soc_ctx is kept on while cpu0 stop +bit02: cpu0_mem is kept on while cpu0 stop +bit03: cpu0_ctx is kept on while cpu0 stop +bit04: xtal_hold is kept on while cpu0 stop +bit05: pll0_hold is kept on while cpu0 stop +bit06: pll1_hold is kept on while cpu0 stop + 0 + 15 + read-write + + + + + SET + Retention Contol + 0x4 + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: keep + 0 + 15 + read-write + + + + + CLEAR + Retention Contol + 0x8 + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: no keep + 0 + 15 + read-write + + + + + TOGGLE + Retention Contol + 0xc + 32 + 0x00000000 + 0x00007FFF + + + LINK + retention setting while CPU0 enter stop mode, each bit represents a resource +0: no effect +1: toggle the result that whether the resource is kept on while CPU0 stop before + 0 + 15 + read-write + + + + + + 1 + 0x14 + cpu0 + POWER[%s] + no description available + 0x1000 + + status + Power Setting + 0x0 + 32 + 0x80000000 + 0xC0031100 + + + FLAG + flag represents power cycle happened from last clear of this bit +0: power domain did not edurance power cycle since last clear of this bit +1: power domain enduranced power cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup power cycle happened from last clear of this bit +0: power domain did not edurance wakeup power cycle since last clear of this bit +1: power domain enduranced wakeup power cycle since last clear of this bit + 30 + 1 + read-write + + + MEM_RET_N + memory info retention control signal +0: memory enter retention mode +1: memory exit retention mode + 17 + 1 + read-only + + + MEM_RET_P + memory info retention control signal +0: memory not enterexitretention mode +1: memory enter retention mode + 16 + 1 + read-only + + + LF_DISABLE + low fanout power switch disable +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 12 + 1 + read-only + + + LF_ACK + low fanout power switch feedback +0: low fanout power switches are turned on +1: low fanout power switches are truned off + 8 + 1 + read-only + + + + + lf_wait + Power Setting + 0x4 + 32 + 0x000000FF + 0x000FFFFF + + + WAIT + wait time for low fan out power switch turn on, default value is 255 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + off_wait + Power Setting + 0xc + 32 + 0x0000000F + 0x000FFFFF + + + WAIT + wait time for power switch turn off, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + ret_wait + Power Setting + 0x10 + 32 + 0x0000000F + 0x000FFFFF + + + WAIT + wait time for memory retention mode transition, default value is 15 +0: 0 clock cycle +1: 1 clock cycles +. . . +clock cycles count on 24MHz + 0 + 20 + read-write + + + + + + 2 + 0x10 + soc,cpu0 + RESET[%s] + no description available + 0x1400 + + control + Reset Setting + 0x0 + 32 + 0x80000000 + 0xC0000011 + + + FLAG + flag represents reset happened from last clear of this bit +0: domain did not edurance reset cycle since last clear of this bit +1: domain enduranced reset cycle since last clear of this bit + 31 + 1 + read-write + + + FLAG_WAKE + flag represents wakeup reset happened from last clear of this bit +0: domain did not edurance wakeup reset cycle since last clear of this bit +1: domain enduranced wakeup reset cycle since last clear of this bit + 30 + 1 + read-write + + + HOLD + perform reset and hold in reset, until ths bit cleared by software +0: reset is released for function +1: reset is assert and hold + 4 + 1 + read-write + + + RESET + perform reset and release imediately +0: reset is released +1 reset is asserted and will release automaticly + 0 + 1 + read-write + + + + + config + Reset Setting + 0x4 + 32 + 0x00402003 + 0x00FFFFFF + + + PRE_WAIT + wait cycle numbers before assert reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 16 + 8 + read-write + + + RSTCLK_NUM + reset clock number(must be even number) +0: 0 cycle +1: 0 cycles +2: 2 cycles +3: 2 cycles +. . . +Note, clock cycle is base on 24M + 8 + 8 + read-write + + + POST_WAIT + time guard band for reset release +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 8 + read-write + + + + + counter + Reset Setting + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + COUNTER + self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset +0: wait 0 cycle +1: wait 1 cycles +. . . +Note, clock cycle is base on 24M + 0 + 20 + read-write + + + + + + 1 + 0x4 + clk_top_cpu0 + CLOCK_CPU[%s] + no description available + 0x1800 + 32 + 0x00000000 + 0xD00F07FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + SUB0_DIV + ahb bus divider, the bus clock is generated by cpu_clock/div +0: divider by 1 +1: divider by 2 +… + 16 + 4 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll1_clk2 +7:pll1_clk3 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + 36 + 0x4 + clk_top_mct0,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_xpi0,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ref0,clk_top_ref1 + CLOCK[%s] + no description available + 0x1804 + 32 + 0x00000000 + 0xD00007FF + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux in clock component +0:osc0_clk0 +1:pll0_clk0 +2:pll0_clk1 +3:pll0_clk2 +4:pll1_clk0 +5:pll1_clk1 +6:pll1_clk2 +7:pll1_clk3 + 8 + 3 + read-write + + + DIV + clock divider +0: divider by 1 +1: divider by 2 +2: divider by 3 +. . . +255: divider by 256 + 0 + 8 + read-write + + + + + 2 + 0x4 + clk_top_adc0,clk_top_adc1 + ADCCLK[%s] + no description available + 0x1c00 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ahb0 clock N +1: ana clock + 8 + 1 + read-write + + + + + 2 + 0x4 + clk_top_dac0,clk_top_dac1 + DACCLK[%s] + no description available + 0x1c08 + 32 + 0x00000000 + 0xD0000100 + + + GLB_BUSY + global busy +0: no changes pending to any clock +1: any of nodes is changing status + 31 + 1 + read-only + + + LOC_BUSY + local busy +0: a change is pending for current node +1: current node is changing status + 30 + 1 + read-only + + + PRESERVE + preserve function against global select +0: select global clock setting +1: not select global clock setting + 28 + 1 + read-write + + + MUX + current mux +0: ahb0 clock N +1: ana clock + 8 + 1 + read-write + + + + + global00 + Clock senario + 0x2000 + 32 + 0x00000000 + 0x000000FF + + + MUX + global clock override request +bit0: override to preset0 +bit1: override to preset1 +bit2: override to preset2 +bit3: override to preset3 +bit4: override to preset4 +bit5: override to preset5 +bit6: override to preset6 +bit7: override to preset7 + 0 + 8 + read-write + + + + + 4 + 0x20 + slice0,slice1,slice2,slice3 + MONITOR[%s] + no description available + 0x2400 + + control + Clock measure and monitor control + 0x0 + 32 + 0x00000000 + 0x89FFD7FF + + + VALID + result is ready for read +0: not ready +1: result is ready + 31 + 1 + read-write + + + DIV_BUSY + divider is applying new setting + 27 + 1 + read-only + + + OUTEN + enable clock output + 24 + 1 + read-write + + + DIV + output divider + 16 + 8 + read-write + + + HIGH + clock frequency higher than upper limit + 15 + 1 + read-write + + + LOW + clock frequency lower than lower limit + 14 + 1 + read-write + + + START + start measurement + 12 + 1 + read-write + + + MODE + work mode, +0: register value will be compared to measurement +1: upper and lower value will be recordered in register + 10 + 1 + read-write + + + ACCURACY + measurement accuracy, +0: resolution is 1kHz +1: resolution is 1Hz + 9 + 1 + read-write + + + REFERENCE + refrence clock selection, +0: 32k +1: 24M + 8 + 1 + read-write + + + SELECTION + clock measurement selection + 0 + 8 + read-write + + + + + current + Clock measure result + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + self updating measure result + 0 + 32 + read-only + + + + + low_limit + Clock lower limit + 0x8 + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + FREQUENCY + lower frequency + 0 + 32 + read-write + + + + + high_limit + Clock upper limit + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + FREQUENCY + upper frequency + 0 + 32 + read-write + + + + + + 1 + 0x400 + cpu0 + CPU[%s] + no description available + 0x2800 + + LP + CPU0 LP control + 0x0 + 32 + 0x00001000 + 0xFF013703 + + + WAKE_CNT + CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + 24 + 8 + read-write + + + HALT + halt request for CPU0, +0: CPU0 will start to execute after reset or receive wakeup request +1: CPU0 will not start after reset, or wakeup after WFI + 16 + 1 + read-write + + + WAKE + CPU0 is waking up +0: CPU0 wake up not asserted +1: CPU0 wake up asserted + 13 + 1 + read-only + + + EXEC + CPU0 is executing +0: CPU0 is not executing +1: CPU0 is executing + 12 + 1 + read-only + + + WAKE_FLAG + CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit +0: CPU0 wakeup not happened +1: CPU0 wake up happened + 10 + 1 + read-write + + + SLEEP_FLAG + CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit +0: CPU0 sleep not happened +1: CPU0 sleep happened + 9 + 1 + read-write + + + RESET_FLAG + CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit +0: CPU0 reset not happened +1: CPU0 reset happened + 8 + 1 + read-write + + + MODE + Low power mode, system behavior after WFI +00: CPU clock stop after WFI +01: System enter low power mode after WFI +10: Keep running after WFI +11: reserved + 0 + 2 + read-write + + + + + LOCK + CPU0 Lock GPR + 0x4 + 32 + 0x00000000 + 0x0000FFFE + + + GPR + Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + 2 + 14 + read-write + + + LOCK + Lock bit for CPU_LOCK + 1 + 1 + read-write + + + + + 14 + 0x4 + GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 + GPR[%s] + no description available + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + register for software to handle resume, can save resume address or status + 0 + 32 + read-write + + + + + 4 + 0x4 + STATUS0,STATUS1,STATUS2,STATUS3 + WAKEUP_STATUS[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + IRQ values + 0 + 32 + read-only + + + + + 4 + 0x4 + ENABLE0,ENABLE1,ENABLE2,ENABLE3 + WAKEUP_ENABLE[%s] + no description available + 0x80 + 32 + 0x00000000 + 0xFFFFFFFF + + + ENABLE + IRQ wakeup enable + 0 + 32 + read-write + + + + + + + + IOC + IOC + IOC + 0xf4040000 + + 0x0 + 0xe40 + registers + + + + 456 + 0x8 + pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,rsv64,rsv65,rsv66,rsv67,rsv68,rsv69,rsv70,rsv71,rsv72,rsv73,rsv74,rsv75,rsv76,rsv77,rsv78,rsv79,rsv80,rsv81,rsv82,rsv83,rsv84,rsv85,rsv86,rsv87,rsv88,rsv89,rsv90,rsv91,rsv92,rsv93,rsv94,rsv95,rsv96,rsv97,rsv98,rsv99,rsv100,rsv101,rsv102,rsv103,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,rsv416,px00,px01,px02,px03,px04,px05,px06,px07,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,rsv448,py00,py01,py02,py03,py04,py05,py06,py07 + PAD[%s] + no description available + 0x0 + + FUNC_CTL + ALT SELECT + 0x0 + 32 + 0x00000000 + 0x0001011F + + + LOOP_BACK + force input on +0: disable +1: enable + 16 + 1 + read-write + + + ANALOG + select analog pin in pad +0: disable +1: enable + 8 + 1 + read-write + + + ALT_SELECT + alt select +0: ALT0 +1: ALT1 +... +31:ALT31 + 0 + 5 + read-write + + + + + PAD_CTL + PAD SETTINGS + 0x4 + 32 + 0x01010056 + 0x01370177 + + + HYS + schmitt trigger enable +0: disable +1: enable + 24 + 1 + read-write + + + PRS + select pull up/down internal resistance strength: +For pull down, only have 100 Kohm resistance +For pull up: +00: 100 KOhm +01: 47 KOhm +10: 22 KOhm +11: 22 KOhm + 20 + 2 + read-write + + + PS + pull select +0: pull down +1: pull up + 18 + 1 + read-write + + + PE + pull enable +0: pull disable +1: pull enable + 17 + 1 + read-write + + + KE + keeper capability enable +0: keeper disable +1: keeper enable + 16 + 1 + read-write + + + OD + open drain +0: open drain disable +1: open drain enable + 8 + 1 + read-write + + + SR + slew rate +0: Slow slew rate +1: Fast slew rate + 6 + 1 + read-write + + + SPD + additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise +00: Slow frequency slew rate(50Mhz) +01: Medium frequency slew rate(100 Mhz) +10: Fast frequency slew rate(150 Mhz) +11: Max frequency slew rate(200Mhz) + 4 + 2 + read-write + + + DS + drive strength +1.8V Mode: +000: 260 Ohm +001: 260 Ohm +010: 130 Ohm +011: 88 Ohm +100: 65 Ohm +101: 52 Ohm +110: 43 Ohm +111: 37 Ohm +3.3V Mode: +000: 157 Ohm +001: 157 Ohm +010: 78 Ohm +011: 53 Ohm +100: 39 Ohm +101: 32 Ohm +110: 26 Ohm +111: 23 Ohm + 0 + 3 + read-write + + + + + + + + PIOC + PIOC + IOC + 0xf4118000 + + + PLLCTLV2 + PLLCTLV2 + PLLCTLV2 + 0xf40c0000 + + 0x0 + 0x200 + registers + + + + XTAL + OSC configuration + 0x0 + 32 + 0x0001FFFF + 0xB00FFFFF + + + BUSY + Busy flag +0: Oscillator is working or shutdown +1: Oscillator is changing status + 31 + 1 + read-only + + + RESPONSE + Crystal oscillator status +0: Oscillator is not stable +1: Oscillator is stable for use + 29 + 1 + read-only + + + ENABLE + Crystal oscillator enable status +0: Oscillator is off +1: Oscillator is on + 28 + 1 + read-only + + + RAMP_TIME + Rampup time of XTAL oscillator in cycles of RC24M clock +0: 0 cycle +1: 1 cycle +2: 2 cycle +1048575: 1048575 cycles + 0 + 20 + read-write + + + + + 3 + 0x80 + pll0,pll1,pll2 + PLL[%s] + no description available + 0x80 + + MFI + PLL0 multiple register + 0x0 + 32 + 0x00000010 + 0xB000007F + + + BUSY + Busy flag +0: PLL is stable or shutdown +1: PLL is changing status + 31 + 1 + read-only + + + RESPONSE + PLL status +0: PLL is not stable +1: PLL is stable for use + 29 + 1 + read-only + + + ENABLE + PLL enable status +0: PLL is off +1: PLL is on + 28 + 1 + read-only + + + MFI + loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) +0-15: invalid +16: divide by 16 +17: divide by17 +. . . +42: divide by 42 +43~:invalid + 0 + 7 + read-write + + + + + MFN + PLL0 fraction numerator register + 0x4 + 32 + 0x09896800 + 0x3FFFFFFF + + + MFN + Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. + 0 + 30 + read-write + + + + + MFD + PLL0 fraction demoninator register + 0x8 + 32 + 0x0E4E1C00 + 0x3FFFFFFF + + + MFD + Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. + 0 + 30 + read-write + + + + + SS_STEP + PLL0 spread spectrum step register + 0xc + 32 + 0x00000000 + 0x3FFFFFFF + + + STEP + Step of spread spectrum modulator. +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + SS_STOP + PLL0 spread spectrum stop register + 0x10 + 32 + 0x00000000 + 0x3FFFFFFF + + + STOP + Stop point of spread spectrum modulator +This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. + 0 + 30 + read-write + + + + + CONFIG + PLL0 confguration register + 0x14 + 32 + 0x00000000 + 0x00000101 + + + SPREAD + Enable spread spectrum function. This field supports changing during PLL running. + 8 + 1 + read-write + + + REFSEL + Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. +0: XTAL24M +1: IRC24M + 0 + 1 + read-write + + + + + LOCKTIME + PLL0 lock time register + 0x18 + 32 + 0x000009C4 + 0x0000FFFF + + + LOCKTIME + Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. + 0 + 16 + read-write + + + + + STEPTIME + PLL0 step time register + 0x1c + 32 + 0x000009C4 + 0x0000FFFF + + + STEPTIME + Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. + 0 + 16 + read-write + + + + + ADVANCED + PLL0 advance configuration register + 0x20 + 32 + 0x00000000 + 0x11000000 + + + SLOW + Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. +0: fast lock enabled, lock time is 100us +1: fast lock disabled, lock time is 400us + 28 + 1 + read-write + + + DITHER + Enable dither function + 24 + 1 + read-write + + + + + 3 + 0x4 + DIV0,DIV1,DIV2 + DIV[%s] + no description available + 0x40 + 32 + 0x00000000 + 0xB000003F + + + BUSY + Busy flag +0: divider is working +1: divider is changing status + 31 + 1 + read-only + + + RESPONSE + Divider response status +0: Divider is not stable +1: Divider is stable for use + 29 + 1 + read-only + + + ENABLE + Divider enable status +0: Divider is off +1: Divider is on + 28 + 1 + read-only + + + DIV + Divider factor, divider factor is DIV/5 + 1 +0: divide by 1 +1: divide by 1.2 +2: divide by 1.4 +. . . +63: divide by 13.6 + 0 + 6 + read-write + + + + + + + + PPOR + PPOR + PPOR + 0xf4100000 + + 0x0 + 0x20 + registers + + + + RESET_FLAG + flag indicate reset source + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + FLAG + reset reason of last hard reset, write 1 to clear each bit +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + write-only + + + + + RESET_STATUS + reset source status + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + STATUS + current status of reset sources +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-only + + + + + RESET_HOLD + reset hold attribute + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + HOLD + hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-write + + + + + RESET_ENABLE + reset source enable + 0xc + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + ENABLE + enable of reset sources +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-write + + + + + RESET_TYPE + reset type triggered by reset + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + TYPE + reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem +0: brownout +1: temperature +4: debug reset +5: jtag soft reset +8: cpu0 lockup(not available) +9: cpu1 lockup(not available) +10: cpu0 request(not available) +11: cpu1 request(not available) +16: watch dog 0 +17: watch dog 1 +18: watch dog 2(not available) +19: watch dog 3(not available) +24: pmic watch dog +30: jtag ieee reset +31: software + 0 + 32 + read-write + + + + + SOFTWARE_RESET + Software reset counter + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + 0 + 32 + read-write + + + + + + + PCFG + PCFG + PMU + 0xf4104000 + + 0x0 + 0x70 + registers + + + + BANDGAP + BANGGAP control + 0x0 + 32 + 0x00101010 + 0x801F1F1F + + + VBG_TRIMMED + Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: bandgap is not trimmed +1: bandgap is trimmed + 31 + 1 + read-write + + + VBG_1P0_TRIM + Banggap 1.0V output trim value + 16 + 5 + read-write + + + VBG_P65_TRIM + Banggap 1.0V output trim value + 8 + 5 + read-write + + + VBG_P50_TRIM + Banggap 1.0V output trim value + 0 + 5 + read-write + + + + + LDO1P1 + 1V LDO config + 0x4 + 32 + 0x0001044C + 0x00010FFF + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. +700: 700mV +720: 720mV +. . . +1320:1320mV + 0 + 12 + read-write + + + + + LDO2P5 + 2.5V LDO config + 0x8 + 32 + 0x000009C4 + 0x10010FFF + + + READY + Ready flag, will set 1ms after enabled or voltage change +0: LDO is not ready for use +1: LDO is ready + 28 + 1 + read-only + + + ENABLE + LDO enable +0: turn off LDO +1: turn on LDO + 16 + 1 + read-write + + + VOLT + LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. +2125: 2125mV +2150: 2150mV +. . . +2900:2900mV + 0 + 12 + read-write + + + + + DCDC_MODE + DCDC mode select + 0x10 + 32 + 0x0001047E + 0x10070FFF + + + READY + Ready flag +0: DCDC is applying new change +1: DCDC is ready + 28 + 1 + read-only + + + MODE + DCDC work mode +XX0: trun off +001: basic mode +011: generic mode +101: automatic mode +111: expert mode + 16 + 3 + read-write + + + VOLT + DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_LPMODE + DCDC low power mode + 0x14 + 32 + 0x00000384 + 0x00000FFF + + + STBY_VOLT + DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. +600: 600mV +625: 625mV +. . . +1375:1375mV + 0 + 12 + read-write + + + + + DCDC_PROT + DCDC protection + 0x18 + 32 + 0x00000010 + 0x11018191 + + + ILIMIT_LP + over current setting for low power mode +0:250mA +1:200mA + 28 + 1 + read-write + + + OVERLOAD_LP + over current in low power mode +0: current is below setting +1: overcurrent happened in low power mode + 24 + 1 + read-only + + + POWER_LOSS_FLAG + power loss +0: input power is good +1: input power is too low + 16 + 1 + read-only + + + DISABLE_OVERVOLTAGE + ouput over voltage protection +0: protection enabled, DCDC will shut down is output voltage is unexpected high +1: protection disabled, DCDC continue to adjust output voltage + 15 + 1 + read-write + + + OVERVOLT_FLAG + output over voltage flag +0: output is normal +1: output is unexpected high + 8 + 1 + read-only + + + DISABLE_SHORT + disable output short circuit protection +0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected +1: short circuit protection disabled + 7 + 1 + read-write + + + SHORT_CURRENT + short circuit current setting +0: 2.0A, +1: 1.3A + 4 + 1 + read-write + + + SHORT_FLAG + short circuit flag +0: current is within limit +1: short circuits detected + 0 + 1 + read-only + + + + + DCDC_CURRENT + DCDC current estimation + 0x1c + 32 + 0x00000000 + 0x0000811F + + + ESTI_EN + enable current measure + 15 + 1 + read-write + + + VALID + Current level valid +0: data is invalid +1: data is valid + 8 + 1 + read-only + + + LEVEL + DCDC current level, current level is num * 50mA + 0 + 5 + read-only + + + + + DCDC_ADVMODE + DCDC advance setting + 0x20 + 32 + 0x03120040 + 0x073F007F + + + EN_RCSCALE + Enable RC scale + 24 + 3 + read-write + + + DC_C + Loop C number + 20 + 2 + read-write + + + DC_R + Loop R number + 16 + 4 + read-write + + + EN_FF_DET + enable feed forward detect +0: feed forward detect is disabled +1: feed forward detect is enabled + 6 + 1 + read-write + + + EN_FF_LOOP + enable feed forward loop +0: feed forward loop is disabled +1: feed forward loop is enabled + 5 + 1 + read-write + + + EN_AUTOLP + enable auto enter low power mode +0: do not enter low power mode +1: enter low power mode if current is detected low + 4 + 1 + read-write + + + EN_DCM_EXIT + avoid over voltage +0: stay in DCM mode when voltage excess +1: change to CCM mode when voltage excess + 3 + 1 + read-write + + + EN_SKIP + enable skip on narrow pulse +0: do not skip narrow pulse +1: skip narrow pulse + 2 + 1 + read-write + + + EN_IDLE + enable skip when voltage is higher than threshold +0: do not skip +1: skip if voltage is excess + 1 + 1 + read-write + + + EN_DCM + DCM mode +0: CCM mode +1: DCM mode + 0 + 1 + read-write + + + + + DCDC_ADVPARAM + DCDC advance parameter + 0x24 + 32 + 0x00006E1C + 0x00007F7F + + + MIN_DUT + minimum duty cycle + 8 + 7 + read-write + + + MAX_DUT + maximum duty cycle + 0 + 7 + read-write + + + + + DCDC_MISC + DCDC misc parameter + 0x28 + 32 + 0x00070100 + 0x13170317 + + + EN_HYST + hysteres enable + 28 + 1 + read-write + + + HYST_SIGN + hysteres sign + 25 + 1 + read-write + + + HYST_THRS + hysteres threshold + 24 + 1 + read-write + + + RC_SCALE + Loop RC scale threshold + 20 + 1 + read-write + + + DC_FF + Loop feed forward number + 16 + 3 + read-write + + + OL_THRE + overload for threshold for lod power mode + 8 + 2 + read-write + + + OL_HYST + current hysteres range +0: 12.5mV +1: 25mV + 4 + 1 + read-write + + + DELAY + enable delay +0: delay disabled, +1: delay enabled + 2 + 1 + read-write + + + CLK_SEL + clock selection +0: select DCDC internal oscillator +1: select RC24M oscillator + 1 + 1 + read-write + + + EN_STEP + enable stepping in voltage change +0: stepping disabled, +1: steping enabled + 0 + 1 + read-write + + + + + DCDC_DEBUG + DCDC Debug + 0x2c + 32 + 0x00005DBF + 0x000FFFFF + + + UPDATE_TIME + DCDC voltage change time in 24M clock cycles, default value is 1mS + 0 + 20 + read-write + + + + + DCDC_START_TIME + DCDC ramp time + 0x30 + 32 + 0x0001193F + 0x000FFFFF + + + START_TIME + Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + 0 + 20 + read-write + + + + + DCDC_RESUME_TIME + DCDC resume time + 0x34 + 32 + 0x00008C9F + 0x000FFFFF + + + RESUME_TIME + Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + 0 + 20 + read-write + + + + + POWER_TRAP + SOC power trap + 0x40 + 32 + 0x00000000 + 0x80010001 + + + TRIGGERED + Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. +0: low power trap is not triggered +1: low power trap triggered + 31 + 1 + read-write + + + RETENTION + DCDC enter standby mode, which will reduce voltage for memory content retention +0: Shutdown DCDC +1: reduce DCDC voltage + 16 + 1 + read-write + + + TRAP + Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered +0: trap not enabled, pmic side low power function disabled +1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + 0 + 1 + read-write + + + + + WAKE_CAUSE + Wake up source + 0x44 + 32 + 0x00000000 + 0xFFFFFFFF + + + CAUSE + wake up cause, each bit represents one wake up source, write 1 to clear the register bit +0: wake up source is not active during last wakeup +1: wake up source is active furing last wakeup +bit 0: pmic_enable +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit31: pin wakeup + 0 + 32 + read-write + + + + + WAKE_MASK + Wake up mask + 0x48 + 32 + 0x00000000 + 0xFFFFFFFF + + + MASK + mask for wake up sources, each bit represents one wakeup source +0: allow source to wake up system +1: disallow source to wakeup system +bit 0: pmic_enable +bit 7: UART interrupt +bit 8: TMR interrupt +bit 9: WDG interrupt +bit10: GPIO in PMIC interrupt +bit31: pin wakeup + 0 + 32 + read-write + + + + + SCG_CTRL + Clock gate control in PMIC + 0x4c + 32 + 0xFFFFFFFF + 0xFFFFFFFF + + + SCG + control whether clock being gated during PMIC low power flow, 2 bits for each peripheral +00,01: reserved +10: clock is always off +11: clock is always on +bit6-7:gpio +bit8-9:ioc +bit10-11: timer +bit12-13:wdog +bit14-15:uart + 0 + 32 + read-write + + + + + RC24M + RC 24M config + 0x60 + 32 + 0x00000310 + 0x8000071F + + + RC_TRIMMED + RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: RC is not trimmed +1: RC is trimmed + 31 + 1 + read-write + + + TRIM_C + Coarse trim for RC24M, bigger value means faster + 8 + 3 + read-write + + + TRIM_F + Fine trim for RC24M, bigger value means faster + 0 + 5 + read-write + + + + + RC24M_TRACK + RC 24M track mode + 0x64 + 32 + 0x00000000 + 0x00010011 + + + SEL24M + Select track reference +0: select 32K as reference +1: select 24M XTAL as reference + 16 + 1 + read-write + + + RETURN + Retrun default value when XTAL loss +0: remain last tracking value +1: switch to default value + 4 + 1 + read-write + + + TRACK + track mode +0: RC24M free running +1: track RC24M to external XTAL + 0 + 1 + read-write + + + + + TRACK_TARGET + RC 24M track target + 0x68 + 32 + 0x00000000 + 0xFFFFFFFF + + + PRE_DIV + Divider for reference source + 16 + 16 + read-write + + + TARGET + Target frequency multiplier of divided source + 0 + 16 + read-write + + + + + STATUS + RC 24M track status + 0x6c + 32 + 0x00000000 + 0x0011871F + + + SEL32K + track is using XTAL32K +0: track is not using XTAL32K +1: track is using XTAL32K + 20 + 1 + read-only + + + SEL24M + track is using XTAL24M +0: track is not using XTAL24M +1: track is using XTAL24M + 16 + 1 + read-only + + + EN_TRIM + default value takes effect +0: default value is invalid +1: default value is valid + 15 + 1 + read-only + + + TRIM_C + default coarse trim value + 8 + 3 + read-only + + + TRIM_F + default fine trim value + 0 + 5 + read-only + + + + + + + PGPR0 + PGPR0 + PGPR + 0xf4110000 + + 0x0 + 0x40 + registers + + + + PMIC_GPR00 + Generic control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR01 + Generic control + 0x4 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR02 + Generic control + 0x8 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR03 + Generic control + 0xc + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR04 + Generic control + 0x10 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR05 + Generic control + 0x14 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR06 + Generic control + 0x18 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR07 + Generic control + 0x1c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR08 + Generic control + 0x20 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR09 + Generic control + 0x24 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR10 + Generic control + 0x28 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR11 + Generic control + 0x2c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR12 + Generic control + 0x30 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR13 + Generic control + 0x34 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR14 + Generic control + 0x38 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + PMIC_GPR15 + Generic control + 0x3c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + + + PGPR1 + PGPR1 + PGPR + 0xf4114000 + + + PDGO + PDGO + PDGO + 0xf4134000 + + 0x0 + 0x714 + registers + + + + DGO_TURNOFF + trunoff control + 0x0 + 32 + 0x00000000 + 0xFFFFFFFF + + + COUNTER + trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1. + 0 + 32 + write-only + + + + + DGO_RC32K_CFG + RC32K CLOCK + 0x4 + 32 + 0x00000000 + 0x80C001FF + + + IRC_TRIMMED + IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value +0: irc is not trimmed +1: irc is trimmed + 31 + 1 + read-write + + + CAPEX7_TRIM + IRC32K bit 7 + 23 + 1 + read-write + + + CAPEX6_TRIM + IRC32K bit 6 + 22 + 1 + read-write + + + CAP_TRIM + capacitor trim bits + 0 + 9 + read-write + + + + + DGO_GPR00 + Generic control 0 + 0x600 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + DGO_GPR01 + Generic control 1 + 0x604 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + DGO_GPR02 + Generic control 2 + 0x608 + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + DGO_GPR03 + Generic control 3 + 0x60c + 32 + 0x00000000 + 0xFFFFFFFF + + + GPR + Generic control + 0 + 32 + read-write + + + + + DGO_CTR0 + control register 0 + 0x700 + 32 + 0x00000000 + 0x00010000 + + + RETENTION + dgo register status retenion + 16 + 1 + read-write + + + + + DGO_CTR1 + control register 1 + 0x704 + 32 + 0x00000000 + 0x80010001 + + + AOTO_SYS_WAKEUP + software wakeup： 0 : wakeup once； 1：auto wakeup Continuously + 31 + 1 + read-write + + + WAKEUP_EN + permit wakeup pin or software wakeup + 16 + 1 + read-write + + + PIN_WAKEUP_STATUS + wakeup pin status + 0 + 1 + read-only + + + + + DGO_CTR2 + control register 2 + 0x708 + 32 + 0x00000000 + 0x01010000 + + + RESETN_PULLUP_DISABLE + resetn pin pull up disable + 24 + 1 + read-write + + + WAKEUP_PULLDN_DISABLE + wakeup pin pull down disable + 16 + 1 + read-write + + + + + DGO_CTR3 + control register 3 + 0x70c + 32 + 0x00000000 + 0xFFFFFFFF + + + WAKEUP_COUNTER + software wakeup counter + 0 + 32 + read-write + + + + + DGO_CTR4 + control register 4 + 0x710 + 32 + 0x00000000 + 0x00000003 + + + BANDGAP_LESS_POWER + Banggap work in power save mode, banggap function normally +0: banggap works in high performance mode +1: banggap works in power saving mode + 1 + 1 + read-write + + + BANDGAP_LP_MODE + Banggap work in low power mode, banggap function limited +0: banggap works in normal mode +1: banggap works in low power mode + 0 + 1 + read-write + + + + + + + diff --git a/common/libraries/hpm_sdk/soc/HPM5361/SConscript b/common/libraries/hpm_sdk/soc/HPM5361/SConscript new file mode 100644 index 00000000..22afd968 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/SConscript @@ -0,0 +1,26 @@ +import os +import sys +Import('rtconfig') +from building import * + +#get current directory +cwd = GetCurrentDir() + +# Update include path +path = [ cwd, cwd + '/boot' ] + +# The set of source files associated with this SConscript file. +src = Split(''' + system.c + hpm_l1c_drv.c + hpm_sysctl_drv.c + hpm_clock_drv.c + hpm_otp_drv.c + boot/hpm_bootheader.c +''') + +CPPDEFINES = ['CONFIG_HAS_HPMSDK_DMAV2'] + +group = DefineGroup('SoC', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return ('group') diff --git a/common/libraries/hpm_sdk/soc/HPM5361/boot/hpm_bootheader.c b/common/libraries/hpm_sdk/soc/HPM5361/boot/hpm_bootheader.c new file mode 100644 index 00000000..57cdf5aa --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/boot/hpm_bootheader.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_bootheader.h" + +/* symbol exported from startup.S */ +extern uint32_t _start[]; + +/* following symbols exported from linker script */ +extern uint32_t __app_load_addr__[]; +extern uint32_t __app_offset__[]; +extern uint32_t __fw_size__[]; + +#define FW_SIZE (32768) +__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { + (uint32_t)__app_offset__, /* offset */ + (uint32_t)__fw_size__, /* size */ + 0, /* flags */ + 0, /* reserved0 */ + (uint32_t) &__app_load_addr__, /* load_addr */ + 0, /* reserved1 */ + (uint32_t) _start, /* entry_point */ + 0, /* reserved2 */ + {0}, /* hash */ + {0}, /* iv */ +}; + +__attribute__ ((section(".boot_header"))) const boot_header_t header = { + HPM_BOOTHEADER_TAG, /* tag */ + 0x10, /* version*/ + sizeof(header) + sizeof(fw_info), + 0, /* flags */ + 0, /* sw_version */ + 0, /* fuse_version */ + 1, /* fw_count */ + 0, + 0, /* sig_block_offset */ +}; diff --git a/common/libraries/hpm_sdk/soc/HPM5361/boot/hpm_bootheader.h b/common/libraries/hpm_sdk/soc/HPM5361/boot/hpm_bootheader.h new file mode 100644 index 00000000..d7f22fd8 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/boot/hpm_bootheader.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_BOOT_HEADER_H +#define HPM_BOOT_HEADER_H + +#include "hpm_common.h" + +#define HPM_BOOTHEADER_TAG (0xBFU) +#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) + +#ifndef HPM_BOOT_FW_COUNT +#define HPM_BOOT_FW_COUNT 1 +#endif + +#if HPM_BOOT_FW_COUNT < 1 +#error "HPM_BOOT_FW_COUNT can't be less than 1" +#endif + +typedef struct { + uint32_t offset; /* 0x0: offset to boot_header start */ + uint32_t size; /* 0x4: size in bytes */ + uint32_t flags; /* 0x8: [3:0] fw type: */ + /* 0 - executable */ + /* 1 - cmd container */ + /* [11:8] - hash type */ + /* 0 - none */ + /* 1 - sha256 */ + /* 2 - sm3 */ + uint32_t reserved0; /* 0xC */ + uint32_t load_addr; /* 0x10: load address */ + uint32_t reserved1; /* 0x14 */ + uint32_t entry_point; /* 0x18: application entry */ + uint32_t reserved2; /* 0x1C */ + uint8_t hash[64]; /* 0x20: hash value */ + uint8_t iv[32]; /* 0x60: initial vector */ +} fw_info_table_t; + +typedef struct { + uint8_t tag; /* 0x0: must be '0xbf' */ + uint8_t version; /* 0x1: header version */ + uint16_t length; /* 0x2: header length, max 8KB */ + uint32_t flags; /* 0x4: [3:0] SRK set */ + /* [7:4] SRK index */ + /* [15:8] SRK_REVOKE_MASK */ + /* [19:16] Signature Type */ + /* 1: ECDSA */ + /* 2: SM2 */ + uint16_t sw_version; /* 0x8: software version */ + uint8_t fuse_version; /* 0xA: fuse version */ + uint8_t fw_count; /* 0xB: number of fw */ + uint16_t dc_block_offset; /* 0xC: device config block offset*/ + uint16_t sig_block_offset; /* 0xE: signature block offset */ + /* + * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] + * uint32_t dc_info[]; [> <] + */ +} boot_header_t; + +#endif /* HPM_BOOT_HEADER_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_clock_drv.c b/common/libraries/hpm_sdk/soc/HPM5361/hpm_clock_drv.c new file mode 100644 index 00000000..4c59a9a4 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_clock_drv.c @@ -0,0 +1,523 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_soc.h" +#include "hpm_common.h" +#include "hpm_pllctlv2_drv.h" +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/* Clock preset values */ +#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) +#define FREQ_PRESET1_PLL0_CLK0 (720000000UL) +#define FREQ_PRESET1_PLL0_CLK1 (600000000UL) +#define FREQ_PRESET1_PLL0_CLK2 (400000000UL) +#define FREQ_PRESET1_PLL1_CLK0 (800000000UL) +#define FREQ_PRESET1_PLL1_CLK1 (666000000UL) +#define FREQ_PRESET1_PLL1_CLK2 (500000000UL) +#define FREQ_PRESET1_PLL1_CLK3 (266000000UL) +#define FREQ_32KHz (32768UL) +#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) +#define DAC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->DACCLK) +#define WDG_INSTANCE_NUM (2U) +#define BUS_FREQ_MAX (200000000UL) +#define FREQ_1MHz (1000000UL) + +/* Clock On/Off definitions */ +#define CLOCK_ON (true) +#define CLOCK_OFF (false) + + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ + +/** + * @brief Get Clock frequency for IP in common group + */ +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); + +/** + * @brief Get Clock frequency for ADC + */ +static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance); + +/** + * @brief Get Clock frequency for DAC + */ +static uint32_t get_frequency_for_dac(uint32_t instance); + +/** + * @brief Get Clock frequency for WDG + */ +static uint32_t get_frequency_for_wdg(uint32_t instance); + +/** + * @brief Get Clock frequency for PWDG + */ +static uint32_t get_frequency_for_pwdg(void); + +/** + * @brief Turn on/off the IP clock + */ +static void switch_ip_clock(clock_name_t clock_name, bool on); + +static uint32_t get_frequency_for_cpu(void); +static uint32_t get_frequency_for_ahb(void); + + +/*********************************************************************************************************************** + * Variables + **********************************************************************************************************************/ +static const clock_node_t s_adc_clk_mux_node[] = { + clock_node_ahb, + clock_node_ana0 +}; + +static const clock_node_t s_dac_clk_mux_node[] = { + clock_node_ahb, + clock_node_ana2 +}; + +static EWDG_Type *const s_wdgs[] = { HPM_WDG0, HPM_WDG1}; + +uint32_t hpm_core_clock; + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +uint32_t clock_get_frequency(clock_name_t clock_name) +{ + uint32_t clk_freq = 0UL; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); + break; + case CLK_SRC_GROUP_ADC: + clk_freq = get_frequency_for_adc(CLK_SRC_GROUP_ADC, node_or_instance); + break; + case CLK_SRC_GROUP_DAC: + clk_freq = get_frequency_for_dac(node_or_instance); + break; + case CLK_SRC_GROUP_WDG: + clk_freq = get_frequency_for_wdg(node_or_instance); + break; + case CLK_SRC_GROUP_PWDG: + clk_freq = get_frequency_for_pwdg(); + break; + case CLK_SRC_GROUP_PMIC: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case CLK_SRC_GROUP_CPU0: + clk_freq = get_frequency_for_cpu(); + break; + case CLK_SRC_GROUP_AHB: + clk_freq = get_frequency_for_ahb(); + break; + case CLK_SRC_GROUP_SRC: + clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); + break; + default: + clk_freq = 0UL; + break; + } + return clk_freq; +} + +uint32_t get_frequency_for_source(clock_source_t source) +{ + uint32_t clk_freq = 0UL; + switch (source) { + case clock_source_osc0_clk0: + clk_freq = FREQ_PRESET1_OSC0_CLK0; + break; + case clock_source_pll0_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); + break; + case clock_source_pll0_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 1U); + break; + case clock_source_pll0_clk2: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 2U); + break; + case clock_source_pll1_clk0: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); + break; + case clock_source_pll1_clk1: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); + break; + case clock_source_pll1_clk2: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 2U); + break; + case clock_source_pll1_clk3: + clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 3U); + break; + default: + clk_freq = 0UL; + break; + } + + return clk_freq; +} + +static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) +{ + uint32_t clk_freq = 0UL; + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); + + if (node_or_instance < clock_node_end) { + uint32_t clk_node = (uint32_t) node_or_instance; + + uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); + clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); + clk_freq = get_frequency_for_source(clk_mux) / clk_div; + } + return clk_freq; +} + +static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance) +{ + uint32_t clk_freq = 0UL; + bool is_mux_valid = false; + clock_node_t node = clock_node_end; + uint32_t adc_index = instance; + + (void) clk_src_type; + + if (adc_index < ADC_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[adc_index]); + if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { + node = s_adc_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + + if (is_mux_valid) { + if (node != clock_node_ahb) { + node += instance; + clk_freq = get_frequency_for_ip_in_common_group(node); + } else { + clk_freq = get_frequency_for_ahb(); + } + } + return clk_freq; +} + +static uint32_t get_frequency_for_dac(uint32_t instance) +{ + uint32_t clk_freq = 0UL; + bool is_mux_valid = false; + clock_node_t node = clock_node_end; + if (instance < DAC_INSTANCE_NUM) { + uint32_t mux_in_reg = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[instance]); + if (mux_in_reg < ARRAY_SIZE(s_dac_clk_mux_node)) { + node = s_dac_clk_mux_node[mux_in_reg]; + is_mux_valid = true; + } + } + + if (is_mux_valid) { + if (node == clock_node_ahb) { + clk_freq = get_frequency_for_ahb(); + } else { + node += instance; + clk_freq = get_frequency_for_ip_in_common_group(node); + } + } + + return clk_freq; +} + +static uint32_t get_frequency_for_wdg(uint32_t instance) +{ + uint32_t freq_in_hz; + if (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[instance]->CTRL0) == 0) { + freq_in_hz = get_frequency_for_ahb(); + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + +static uint32_t get_frequency_for_pwdg(void) +{ + uint32_t freq_in_hz; + if (EWDG_CTRL0_CLK_SEL_GET(HPM_PWDG->CTRL0) == 0) { + freq_in_hz = FREQ_PRESET1_OSC0_CLK0; + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + +static uint32_t get_frequency_for_cpu(void) +{ + uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); + uint32_t div = SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_source(mux) / div); +} + +static uint32_t get_frequency_for_ahb(void) +{ + uint32_t div = SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; + return (get_frequency_for_cpu() / div); +} + +clk_src_t clock_get_source(clock_name_t clock_name) +{ + uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; + uint8_t clk_src_index = 0xFU; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); + break; + case CLK_SRC_GROUP_ADC: + if (node_or_instance < ADC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_ADC; + clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_DAC: + if (node_or_instance < DAC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_DAC; + clk_src_index = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[node_or_instance]); + } + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_WDG; + clk_src_index = (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[node_or_instance]->CTRL0) == 0); + } + break; + case CLK_SRC_GROUP_PWDG: + clk_src_group = CLK_SRC_GROUP_PWDG; + clk_src_index = (EWDG_CTRL0_CLK_SEL_GET(HPM_PWDG->CTRL0) == 0); + break; + case CLK_SRC_GROUP_PMIC: + clk_src_group = CLK_SRC_GROUP_COMMON; + clk_src_index = clock_source_osc0_clk0; + break; + case CLK_SRC_GROUP_CPU0: + case CLK_SRC_GROUP_AHB: + clk_src_group = CLK_SRC_GROUP_CPU0; + clk_src_index = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); + break; + case CLK_SRC_GROUP_SRC: + clk_src_index = (clk_src_t) node_or_instance; + break; + default: + clk_src_group = CLK_SRC_GROUP_INVALID; + break; + } + + clk_src_t clk_src; + if (clk_src_group != CLK_SRC_GROUP_INVALID) { + clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); + } else { + clk_src = clk_src_invalid; + } + + return clk_src; +} + +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src < clk_adc_src_ahb0) || (src > clk_adc_src_ana1)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->ADCCLK[node_or_instance] = + (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src) +{ + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + + if ((clk_src_type != CLK_SRC_GROUP_DAC) || (node_or_instance >= DAC_INSTANCE_NUM)) { + return status_clk_invalid; + } + + if ((src < clk_dac_src_ahb0) || (src > clk_dac_src_ana3)) { + return status_clk_src_invalid; + } + + uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); + HPM_SYSCTL->DACCLK[node_or_instance] = + (HPM_SYSCTL->DACCLK[node_or_instance] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(clk_src_index); + + return status_success; +} + +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) +{ + hpm_stat_t status = status_success; + uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); + uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); + switch (clk_src_type) { + case CLK_SRC_GROUP_COMMON: + if ((div < 1U) || (div > 256U)) { + status = status_clk_div_invalid; + } else { + sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, (clock_source_t) src, div); + } + break; + case CLK_SRC_GROUP_ADC: + status = status_clk_operation_unsupported; + break; + case CLK_SRC_GROUP_WDG: + if (node_or_instance < WDG_INSTANCE_NUM) { + if (src == clk_wdg_src_ahb0) { + s_wdgs[node_or_instance]->CTRL0 &= ~EWDG_CTRL0_CLK_SEL_MASK; + } else if (src == clk_wdg_src_osc32k) { + s_wdgs[node_or_instance]->CTRL0 |= EWDG_CTRL0_CLK_SEL_MASK; + } else { + status = status_clk_src_invalid; + } + } + break; + case CLK_SRC_GROUP_PWDG: + if (src == clk_pwdg_src_osc24m) { + HPM_PWDG->CTRL0 &= ~EWDG_CTRL0_CLK_SEL_MASK; + } else if (src == clk_pwdg_src_osc32k) { + HPM_PWDG->CTRL0 |= EWDG_CTRL0_CLK_SEL_MASK; + } else { + status = status_clk_src_invalid; + } + break; + case CLK_SRC_GROUP_PMIC: + status = status_clk_fixed; + break; + case CLK_SRC_GROUP_AHB: + status = status_clk_shared_cpu0; + break; + case CLK_SRC_GROUP_CPU0: + if (node_or_instance == clock_node_cpu0) { + /* Note: the AXI and AHB BUS share the same CPU clock, once the CPU clock frequency + * changes, the AXI and AHB clock changes accordingly, here the driver ensures the + * AXI and AHB bus clock frequency is in valid range. + */ + uint32_t expected_freq = get_frequency_for_source((clock_source_t) src) / div; + uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, (clock_source_t) src, div, ahb_sub_div); + } else { + status = status_clk_shared_cpu0; + } + break; + case CLK_SRC_GROUP_SRC: + status = status_clk_operation_unsupported; + break; + default: + status = status_clk_src_invalid; + break; + } + + return status; +} + +void switch_ip_clock(clock_name_t clock_name, bool on) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + uint32_t mode = on ? 1UL : 2UL; + HPM_SYSCTL->RESOURCE[resource] = + (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); + } +} + + +void clock_enable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_ON); +} + +void clock_disable(clock_name_t clock_name) +{ + switch_ip_clock(clock_name, CLOCK_OFF); +} + +void clock_add_to_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); + } +} + +void clock_remove_from_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); + } +} + +bool clock_check_in_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + return sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); +} + +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu == 0U) { + HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); + } +} + +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) +{ + if (cpu == 0U) { + HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); + } +} + +void clock_cpu_delay_us(uint32_t us) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; + while (hpm_csr_get_core_cycle() < expected_ticks) { + } +} + +void clock_cpu_delay_ms(uint32_t ms) +{ + uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; + uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * ms; + while (hpm_csr_get_core_cycle() < expected_ticks) { + } +} + +void clock_update_core_clock(void) +{ + hpm_core_clock = clock_get_frequency(clock_cpu0); +} diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_clock_drv.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_clock_drv.h new file mode 100644 index 00000000..bbf296b6 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_clock_drv.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_CLOCK_DRV_H +#define HPM_CLOCK_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_drv.h" +#include "hpm_csr_drv.h" + + +/** + * @brief Error codes for clock driver + */ +enum { + status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), + status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), + status_clk_invalid = MAKE_STATUS(status_group_clk, 2), + status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), + status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), + status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), + status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), + status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), + status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), + status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), + status_clk_fixed = MAKE_STATUS(status_group_clk, 10), +}; + +/** + * @brief Clock source group definitions + */ +#define CLK_SRC_GROUP_COMMON (0U) +#define CLK_SRC_GROUP_ADC (1U) +#define CLK_SRC_GROUP_WDG (3U) +#define CLK_SRC_GROUP_PMIC (4U) +#define CLK_SRC_GROUP_AHB (5U) +#define CLK_SRC_GROUP_DAC (7U) +#define CLK_SRC_GROUP_CPU0 (9U) +#define CLK_SRC_GROUP_SRC (10U) +#define CLK_SRC_GROUP_PWDG (11U) +#define CLK_SRC_GROUP_INVALID (15U) + +#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) +#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) +#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) + +/** + * @brief Clock source definitions + */ +typedef enum _clock_sources { + clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), + clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), + clk_src_pll0_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), + clk_src_pll0_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), + clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), + clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), + clk_src_pll1_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), + clk_src_pll1_clk3 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), + clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), + + clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + + clk_dac_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), + clk_dac_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), + clk_dac_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), + + clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), + clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), + + clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 0), + clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 1), + + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), +} clk_src_t; + + +#define RESOURCE_INVALID (0xFFFFU) +#define RESOURCE_SHARED_CPU0 (0xFFFDU) + +/* Clock NAME related Macros */ +#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)(node))) +#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) +#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) +#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) + +/** + * @brief Peripheral Clock Type Description + */ +typedef enum _clock_name { + clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_CPU0, clock_node_cpu0), + + clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), + clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), + clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), + clock_can2 = MAKE_CLOCK_NAME(sysctl_resource_can2, CLK_SRC_GROUP_COMMON, clock_node_can2), + clock_can3 = MAKE_CLOCK_NAME(sysctl_resource_can3, CLK_SRC_GROUP_COMMON, clock_node_can3), + clock_lin0 = MAKE_CLOCK_NAME(sysctl_resource_lin0, CLK_SRC_GROUP_COMMON, clock_node_lin0), + clock_lin1 = MAKE_CLOCK_NAME(sysctl_resource_lin1, CLK_SRC_GROUP_COMMON, clock_node_lin1), + clock_lin2 = MAKE_CLOCK_NAME(sysctl_resource_lin2, CLK_SRC_GROUP_COMMON, clock_node_lin2), + clock_lin3 = MAKE_CLOCK_NAME(sysctl_resource_lin3, CLK_SRC_GROUP_COMMON, clock_node_lin3), + clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), + clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), + clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), + clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), + clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), + clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), + clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), + clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), + clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), + clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), + clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), + clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), + clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), + clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), + clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), + clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), + clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), + clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), + clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), + clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), + clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), + clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), + clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref0), + + clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AHB, clock_node_ahb), + + clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), + clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PWDG, 0), + + clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), + + clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 0), + clock_crc0 = MAKE_CLOCK_NAME(sysctl_resource_crc0, CLK_SRC_GROUP_AHB, 1), + clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 2), + clock_opa0 = MAKE_CLOCK_NAME(sysctl_resource_opa0, CLK_SRC_GROUP_AHB, 3), + clock_opa1 = MAKE_CLOCK_NAME(sysctl_resource_opa1, CLK_SRC_GROUP_AHB, 4), + clock_mot0 = MAKE_CLOCK_NAME(sysctl_resource_mot0, CLK_SRC_GROUP_AHB, 5), + clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AHB, 6), + clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AHB, 7), + clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 8), + clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 9), + clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_hdma, CLK_SRC_GROUP_AHB, 10), + clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AHB, 11), + clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_AHB, 12), + clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AHB, 13), + clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_AHB, 14), + + clock_ptmr = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), + clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_pgpio = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 2), + + /* For ADC, there are 2-stage clock source and divider configurations */ + clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), + clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), + clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), + clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), + + /* For DAC, there are 2-stage clock source and divider configurations */ + clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), + clock_ana3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana3), + clock_dac0 = MAKE_CLOCK_NAME(sysctl_resource_dac0, CLK_SRC_GROUP_DAC, 0), + clock_dac1 = MAKE_CLOCK_NAME(sysctl_resource_dac1, CLK_SRC_GROUP_DAC, 1), + + /* Clock sources */ + clk_osc0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 0), + clk_pll0clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 1), + clk_pll0clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 2), + clk_pll0clk2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 3), + clk_pll1clk0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 4), + clk_pll1clk1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 5), + clk_pll1clk2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 6), + clk_pll1clk3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_SRC, 7), +} clock_name_t; + +extern uint32_t hpm_core_clock; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get specified IP frequency + * @param[in] clock_name IP clock name + * + * @return IP clock frequency in Hz + */ +uint32_t clock_get_frequency(clock_name_t clock_name); + +/** + * @brief Get Clock frequency for selected clock source + * @param [in] source clock source + * @return clock frequency for selected clock source + */ +uint32_t get_frequency_for_source(clock_source_t source); + +/** + * @brief Get the IP clock source + * Note: This API return the direct clock source + * @param [in] clock_name clock name + * @return IP clock source + */ +clk_src_t clock_get_source(clock_name_t clock_name); + +/** + * @brief Set ADC clock source + * @param[in] clock_name ADC clock name + * @param[in] src ADC clock source + * + * @return #status_success Setting ADC clock source is successful + * #status_clk_invalid Invalid ADC clock + * #status_clk_src_invalid Invalid ADC clock source + */ +hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set DAC clock source + * @param[in] clock_name DAC clock name + * @param[in] src DAC clock source + * + * @return #status_success Setting DAC clock source is successful + * #status_clk_invalid Invalid DAC clock + * #status_clk_src_invalid Invalid DAC clock source + */ +hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src); + +/** + * @brief Set the IP clock source and divider + * @param[in] clock_name clock name + * @param[in] src clock source + * @param[in] div clock divider, valid range (1 - 256) + * + * @return #status_success Setting Clock source and divider is successful. + * #status_clk_src_invalid clock source is invalid. + * #status_clk_fixed clock source and divider is a fixed value + * #status_clk_shared_ahb Clock is shared with the AHB clock + * #status_clk_shared_axi0 Clock is shared with the AXI0 clock + * #status_clk_shared_axi1 CLock is shared with the AXI1 clock + * #status_clk_shared_axi2 Clock is shared with the AXI2 clock + * #status_clk_shared_cpu0 Clock is shared with the CPU0 clock + * #status_clk_shared_cpu1 Clock is shared with the CPU1 clock + */ +hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); + +/** + * @brief Enable IP clock + * @param[in] clock_name IP clock name + */ +void clock_enable(clock_name_t clock_name); + +/** + * @brief Disable IP clock + * @param[in] clock_name IP clock name + */ +void clock_disable(clock_name_t clock_name); + +/** + * @brief Add IP to specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_add_to_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Remove IP from specified group + * @param[in] clock_name IP clock name + * @param[in] group resource group index, valid value: 0/1/2/3 + */ +void clock_remove_from_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Check IP in specified group + * @param[in] clock_name IP clock name + * @return true if in group, false if not in group + */ +bool clock_check_in_group(clock_name_t clock_name, uint32_t group); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Disconnect the clock group from specified CPU + * @param[in] group clock group index, value value is 0/1/2/3 + * @param[in] cpu CPU index, valid value is 0/1 + */ +void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); + +/** + * @brief Delay specified microseconds + * + * @param [in] us expected delay interval in microseconds + */ +void clock_cpu_delay_us(uint32_t us); + +/** + * @brief Delay specified milliseconds + * + * @param [in] ms expected delay interval in milliseconds + */ +void clock_cpu_delay_ms(uint32_t ms); + +/** + * @brief Update the Core clock frequency + */ +void clock_update_core_clock(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* HPM_CLOCK_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_csr_regs.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_csr_regs.h new file mode 100644 index 00000000..1be84a02 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_csr_regs.h @@ -0,0 +1,4276 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_CSR_H +#define HPM_CSR_H + +/* STANDARD CRS address definition */ +#define CSR_USTATUS (0x0) +#define CSR_UIE (0x4) +#define CSR_UTVEC (0x5) +#define CSR_USCRATCH (0x40) +#define CSR_UEPC (0x41) +#define CSR_UCAUSE (0x42) +#define CSR_UTVAL (0x43) +#define CSR_UIP (0x44) +#define CSR_MSTATUS (0x300) +#define CSR_MISA (0x301) +#define CSR_MIE (0x304) +#define CSR_MTVEC (0x305) +#define CSR_MCOUNTEREN (0x306) +#define CSR_MHPMEVENT3 (0x323) +#define CSR_MHPMEVENT4 (0x324) +#define CSR_MHPMEVENT5 (0x325) +#define CSR_MHPMEVENT6 (0x326) +#define CSR_MSCRATCH (0x340) +#define CSR_MEPC (0x341) +#define CSR_MCAUSE (0x342) +#define CSR_MTVAL (0x343) +#define CSR_MIP (0x344) +#define CSR_PMPCFG0 (0x3A0) +#define CSR_PMPCFG1 (0x3A1) +#define CSR_PMPCFG2 (0x3A2) +#define CSR_PMPCFG3 (0x3A3) +#define CSR_PMPADDR0 (0x3B0) +#define CSR_PMPADDR1 (0x3B1) +#define CSR_PMPADDR2 (0x3B2) +#define CSR_PMPADDR3 (0x3B3) +#define CSR_PMPADDR4 (0x3B4) +#define CSR_PMPADDR5 (0x3B5) +#define CSR_PMPADDR6 (0x3B6) +#define CSR_PMPADDR7 (0x3B7) +#define CSR_PMPADDR8 (0x3B8) +#define CSR_PMPADDR9 (0x3B9) +#define CSR_PMPADDR10 (0x3BA) +#define CSR_PMPADDR11 (0x3BB) +#define CSR_PMPADDR12 (0x3BC) +#define CSR_PMPADDR13 (0x3BD) +#define CSR_PMPADDR14 (0x3BE) +#define CSR_PMPADDR15 (0x3BF) +#define CSR_TSELECT (0x7A0) +#define CSR_TDATA1 (0x7A1) +#define CSR_MCONTROL (0x7A1) +#define CSR_ICOUNT (0x7A1) +#define CSR_ITRIGGER (0x7A1) +#define CSR_ETRIGGER (0x7A1) +#define CSR_TDATA2 (0x7A2) +#define CSR_TDATA3 (0x7A3) +#define CSR_TEXTRA (0x7A3) +#define CSR_TINFO (0x7A4) +#define CSR_TCONTROL (0x7A5) +#define CSR_MCONTEXT (0x7A8) +#define CSR_SCONTEXT (0x7AA) +#define CSR_DCSR (0x7B0) +#define CSR_DPC (0x7B1) +#define CSR_DSCRATCH0 (0x7B2) +#define CSR_DSCRATCH1 (0x7B3) +#define CSR_MCYCLE (0xB00) +#define CSR_MINSTRET (0xB02) +#define CSR_MHPMCOUNTER3 (0xB03) +#define CSR_MHPMCOUNTER4 (0xB04) +#define CSR_MHPMCOUNTER5 (0xB05) +#define CSR_MHPMCOUNTER6 (0xB06) +#define CSR_MCYCLEH (0xB80) +#define CSR_MINSTRETH (0xB82) +#define CSR_MHPMCOUNTER3H (0xB83) +#define CSR_MHPMCOUNTER4H (0xB84) +#define CSR_MHPMCOUNTER5H (0xB85) +#define CSR_MHPMCOUNTER6H (0xB86) +#define CSR_CYCLE (0xC00) +#define CSR_CYCLEH (0xC80) +#define CSR_MVENDORID (0xF11) +#define CSR_MARCHID (0xF12) +#define CSR_MIMPID (0xF13) +#define CSR_MHARTID (0xF14) + +/* NON-STANDARD CRS address definition */ +#define CSR_MCOUNTINHIBIT (0x320) +#define CSR_MILMB (0x7C0) +#define CSR_MDLMB (0x7C1) +#define CSR_MECC_CODE (0x7C2) +#define CSR_MNVEC (0x7C3) +#define CSR_MXSTATUS (0x7C4) +#define CSR_MPFT_CTL (0x7C5) +#define CSR_MHSP_CTL (0x7C6) +#define CSR_MSP_BOUND (0x7C7) +#define CSR_MSP_BASE (0x7C8) +#define CSR_MDCAUSE (0x7C9) +#define CSR_MCACHE_CTL (0x7CA) +#define CSR_MCCTLBEGINADDR (0x7CB) +#define CSR_MCCTLCOMMAND (0x7CC) +#define CSR_MCCTLDATA (0x7CD) +#define CSR_MCOUNTERWEN (0x7CE) +#define CSR_MCOUNTERINTEN (0x7CF) +#define CSR_MMISC_CTL (0x7D0) +#define CSR_MCOUNTERMASK_M (0x7D1) +#define CSR_MCOUNTERMASK_S (0x7D2) +#define CSR_MCOUNTERMASK_U (0x7D3) +#define CSR_MCOUNTEROVF (0x7D4) +#define CSR_DEXC2DBG (0x7E0) +#define CSR_DDCAUSE (0x7E1) +#define CSR_UITB (0x800) +#define CSR_UCODE (0x801) +#define CSR_UDCAUSE (0x809) +#define CSR_UCCTLBEGINADDR (0x80B) +#define CSR_UCCTLCOMMAND (0x80C) +#define CSR_MICM_CFG (0xFC0) +#define CSR_MDCM_CFG (0xFC1) +#define CSR_MMSC_CFG (0xFC2) +#define CSR_MMSC_CFG2 (0xFC3) + +/* STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: USTATUS */ +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_USTATUS_UPIE_MASK (0x10U) +#define CSR_USTATUS_UPIE_SHIFT (4U) +#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) +#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_USTATUS_UIE_MASK (0x1U) +#define CSR_USTATUS_UIE_SHIFT (0U) +#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) +#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) + +/* Bitfield definition for register: UIE */ +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UEIE_MASK (0x100U) +#define CSR_UIE_UEIE_SHIFT (8U) +#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) +#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_UTIE_MASK (0x10U) +#define CSR_UIE_UTIE_SHIFT (4U) +#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) +#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_UIE_USIE_MASK (0x1U) +#define CSR_UIE_USIE_SHIFT (0U) +#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) +#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) + +/* Bitfield definition for register: UTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. + */ +#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_UTVEC_BASE_31_2_SHIFT (2U) +#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) +#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: USCRATCH */ +/* + * USCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_USCRATCH_USCRATCH_SHIFT (0U) +#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) +#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) + +/* Bitfield definition for register: UEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_UEPC_EPC_SHIFT (1U) +#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) +#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) + +/* Bitfield definition for register: UCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt. + */ +#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) +#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception Code. + * When interrupt is 1: + * 0:User software interrupt + * 4:User timer interrupt + * 8:User external interrupt + * When interrupt is 0: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9-11:Reserved + * 12:Instruction page fault + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 32：Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) +#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) +#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: UTVAL */ +/* + * UTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) +#define CSR_UTVAL_UTVAL_SHIFT (0U) +#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) +#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) + +/* Bitfield definition for register: UIP */ +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UEIP_MASK (0x100U) +#define CSR_UIP_UEIP_SHIFT (8U) +#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) +#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_UTIP_MASK (0x10U) +#define CSR_UIP_UTIP_SHIFT (4U) +#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) +#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_UIP_USIP_MASK (0x1U) +#define CSR_UIP_USIP_SHIFT (0U) +#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) +#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) + +/* Bitfield definition for register: MSTATUS */ +/* + * SD (RO) + * + * SD summarizes whether either the FS field or XS field is dirty. + */ +#define CSR_MSTATUS_SD_MASK (0x80000000UL) +#define CSR_MSTATUS_SD_SHIFT (31U) +#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) + +/* + * MXR (RW) + * + * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect + * 0:Execute-only pages are not readable + * 1:Execute-only pages are readable + */ +#define CSR_MSTATUS_MXR_MASK (0x80000UL) +#define CSR_MSTATUS_MXR_SHIFT (19U) +#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) +#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) + +/* + * MPRV (RW) + * + * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. + */ +#define CSR_MSTATUS_MPRV_MASK (0x20000UL) +#define CSR_MSTATUS_MPRV_SHIFT (17U) +#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) +#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) + +/* + * XS (RO) + * + * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: + * Illegal instruction exceptions are triggered when XS is Off. + * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_XS_MASK (0x18000UL) +#define CSR_MSTATUS_XS_SHIFT (15U) +#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) + +/* + * FS (RW) + * + * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state + * managements in two regards: + * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. + * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. + * 0:Off + * 1:Initial + * 2:Clean + * 3:Dirty + */ +#define CSR_MSTATUS_FS_MASK (0x6000U) +#define CSR_MSTATUS_FS_SHIFT (13U) +#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) +#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) + +/* + * MPP (RW) + * + * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. + */ +#define CSR_MSTATUS_MPP_MASK (0x1800U) +#define CSR_MSTATUS_MPP_SHIFT (11U) +#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) +#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) + +/* + * MPIE (RW) + * + * MPIE holds the value of the MIE bit prior to a trap. + */ +#define CSR_MSTATUS_MPIE_MASK (0x80U) +#define CSR_MSTATUS_MPIE_SHIFT (7U) +#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) +#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) + +/* + * UPIE (RW) + * + * UPIE holds the value of the UIE bit prior to a trap. + */ +#define CSR_MSTATUS_UPIE_MASK (0x10U) +#define CSR_MSTATUS_UPIE_SHIFT (4U) +#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) +#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) + +/* + * MIE (RW) + * + * M mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_MIE_MASK (0x8U) +#define CSR_MSTATUS_MIE_SHIFT (3U) +#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) +#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) + +/* + * UIE (RW) + * + * U mode interrupt enable bit. + * 0: Disabled + * 1: Enabled + */ +#define CSR_MSTATUS_UIE_MASK (0x1U) +#define CSR_MSTATUS_UIE_SHIFT (0U) +#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) +#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) + +/* Bitfield definition for register: MISA */ +/* + * BASE (RO) + * + * The general-purpose register width of the native base integer ISA. + * 0:Reserved + * 1:32 + * 2:64 + * 3:128 + */ +#define CSR_MISA_BASE_MASK (0xC0000000UL) +#define CSR_MISA_BASE_SHIFT (30U) +#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) + +/* + * Z (RO) + * + * Reserved + */ +#define CSR_MISA_Z_MASK (0x2000000UL) +#define CSR_MISA_Z_SHIFT (25U) +#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) + +/* + * Y (RO) + * + * Reserved + */ +#define CSR_MISA_Y_MASK (0x1000000UL) +#define CSR_MISA_Y_SHIFT (24U) +#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) + +/* + * X (RO) + * + * Non-standard extensions present + */ +#define CSR_MISA_X_MASK (0x800000UL) +#define CSR_MISA_X_SHIFT (23U) +#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) + +/* + * W (RO) + * + * Reserved + */ +#define CSR_MISA_W_MASK (0x400000UL) +#define CSR_MISA_W_SHIFT (22U) +#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) + +/* + * V (RO) + * + * Tentatively reserved for Vector extension + */ +#define CSR_MISA_V_MASK (0x200000UL) +#define CSR_MISA_V_SHIFT (21U) +#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) + +/* + * U (RO) + * + * User mode implemented + * 0:Machine + * 1:Machine + User / Machine + Supervisor + User + */ +#define CSR_MISA_U_MASK (0x100000UL) +#define CSR_MISA_U_SHIFT (20U) +#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) + +/* + * T (RO) + * + * Tentatively reserved for Transactional Memory extension + */ +#define CSR_MISA_T_MASK (0x80000UL) +#define CSR_MISA_T_SHIFT (19U) +#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) + +/* + * S (RO) + * + * Supervisor mode implemented + * 0:Machine / Machine + User + * 1:Machine + Supervisor + User + */ +#define CSR_MISA_S_MASK (0x40000UL) +#define CSR_MISA_S_SHIFT (18U) +#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) + +/* + * R (RO) + * + * Reserved + */ +#define CSR_MISA_R_MASK (0x20000UL) +#define CSR_MISA_R_SHIFT (17U) +#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) + +/* + * Q (RO) + * + * Quad-precision floating-point extension + */ +#define CSR_MISA_Q_MASK (0x10000UL) +#define CSR_MISA_Q_SHIFT (16U) +#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) + +/* + * P (RO) + * + * Tentatively reserved for Packed-SIMD extension + */ +#define CSR_MISA_P_MASK (0x8000U) +#define CSR_MISA_P_SHIFT (15U) +#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) + +/* + * O (RO) + * + * Reserved + */ +#define CSR_MISA_O_MASK (0x4000U) +#define CSR_MISA_O_SHIFT (14U) +#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) + +/* + * N (RO) + * + * User-level interrupts supported + * 0:no + * 1:yes + */ +#define CSR_MISA_N_MASK (0x2000U) +#define CSR_MISA_N_SHIFT (13U) +#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) + +/* + * M (RO) + * + * Integer Multiply/Divide extension + */ +#define CSR_MISA_M_MASK (0x1000U) +#define CSR_MISA_M_SHIFT (12U) +#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) + +/* + * L (RO) + * + * Tentatively reserved for Decimal Floating-Point extension + */ +#define CSR_MISA_L_MASK (0x800U) +#define CSR_MISA_L_SHIFT (11U) +#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) + +/* + * K (RO) + * + * Reserved + */ +#define CSR_MISA_K_MASK (0x400U) +#define CSR_MISA_K_SHIFT (10U) +#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) + +/* + * J (RO) + * + * Tentatively reserved for Dynamically Translated Languages extension + */ +#define CSR_MISA_J_MASK (0x200U) +#define CSR_MISA_J_SHIFT (9U) +#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) + +/* + * I (RO) + * + * RV32I/64I/128I base ISA + */ +#define CSR_MISA_I_MASK (0x100U) +#define CSR_MISA_I_SHIFT (8U) +#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) + +/* + * H (RO) + * + * Reserved + */ +#define CSR_MISA_H_MASK (0x80U) +#define CSR_MISA_H_SHIFT (7U) +#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) + +/* + * G (RO) + * + * Additional standard extensions present + */ +#define CSR_MISA_G_MASK (0x40U) +#define CSR_MISA_G_SHIFT (6U) +#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) + +/* + * F (RO) + * + * Single-precision floating-point extension + * 0:none + * 1:double+single precision / single precision + */ +#define CSR_MISA_F_MASK (0x20U) +#define CSR_MISA_F_SHIFT (5U) +#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) + +/* + * E (RO) + * + * RV32E base ISA + */ +#define CSR_MISA_E_MASK (0x10U) +#define CSR_MISA_E_SHIFT (4U) +#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) + +/* + * D (RO) + * + * Double-precision floating-point extension + * 0:single precision / none + * 1:double+single precision + */ +#define CSR_MISA_D_MASK (0x8U) +#define CSR_MISA_D_SHIFT (3U) +#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) + +/* + * C (RO) + * + * Compressed extension + */ +#define CSR_MISA_C_MASK (0x4U) +#define CSR_MISA_C_SHIFT (2U) +#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) + +/* + * B (RO) + * + * Tentatively reserved for Bit operations extension + */ +#define CSR_MISA_B_MASK (0x2U) +#define CSR_MISA_B_SHIFT (1U) +#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) + +/* + * A (RO) + * + * Atomic extension + * 0:no + * 1:yes + */ +#define CSR_MISA_A_MASK (0x1U) +#define CSR_MISA_A_SHIFT (0U) +#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) + +/* Bitfield definition for register: MIE */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_PMOVI_MASK (0x40000UL) +#define CSR_MIE_PMOVI_SHIFT (18U) +#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) +#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_BWEI_MASK (0x20000UL) +#define CSR_MIE_BWEI_SHIFT (17U) +#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) +#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_IMECCI_MASK (0x10000UL) +#define CSR_MIE_IMECCI_SHIFT (16U) +#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) +#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) + +/* + * MEIE (RW) + * + * M mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MEIE_MASK (0x800U) +#define CSR_MIE_MEIE_SHIFT (11U) +#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) +#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) + +/* + * UEIE (RW) + * + * U mode external interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UEIE_MASK (0x100U) +#define CSR_MIE_UEIE_SHIFT (8U) +#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) +#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) + +/* + * MTIE (RW) + * + * M mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MTIE_MASK (0x80U) +#define CSR_MIE_MTIE_SHIFT (7U) +#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) +#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) + +/* + * UTIE (RW) + * + * U mode timer interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_UTIE_MASK (0x10U) +#define CSR_MIE_UTIE_SHIFT (4U) +#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) +#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) + +/* + * MSIE (RW) + * + * M mode software interrupt enable bit + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_MSIE_MASK (0x8U) +#define CSR_MIE_MSIE_SHIFT (3U) +#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) +#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) + +/* + * USIE (RW) + * + * U mode software interrupt enable bit. + * 0:Disabled + * 1:Enabled + */ +#define CSR_MIE_USIE_MASK (0x1U) +#define CSR_MIE_USIE_SHIFT (0U) +#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) +#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) + +/* Bitfield definition for register: MTVEC */ +/* + * BASE_31_2 (RW) + * + * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode + */ +#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) +#define CSR_MTVEC_BASE_31_2_SHIFT (2U) +#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) +#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) + +/* Bitfield definition for register: MCOUNTEREN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) +#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) +#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) +#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) +#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) +#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) +#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) +#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) +#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) +#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) +#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) +#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) +#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_IR_MASK (0x4U) +#define CSR_MCOUNTEREN_IR_SHIFT (2U) +#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) +#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) + +/* + * TM (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_TM_MASK (0x2U) +#define CSR_MCOUNTEREN_TM_SHIFT (1U) +#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) +#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEREN_CY_MASK (0x1U) +#define CSR_MCOUNTEREN_CY_SHIFT (0U) +#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) +#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) + +/* Bitfield definition for register: MHPMEVENT3 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT3_SEL_SHIFT (4U) +#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) +#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) +#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT4 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT4_SEL_SHIFT (4U) +#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) +#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) +#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT5 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT5_SEL_SHIFT (4U) +#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) +#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) +#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) + +/* Bitfield definition for register: MHPMEVENT6 */ +/* + * SEL (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) +#define CSR_MHPMEVENT6_SEL_SHIFT (4U) +#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) +#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) + +/* + * TYPE (RW) + * + * See Event Selectors table + */ +#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) +#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) +#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) +#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) + +/* Bitfield definition for register: MSCRATCH */ +/* + * MSCRATCH (RW) + * + * Scratch register storage. + */ +#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) +#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) +#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) + +/* Bitfield definition for register: MEPC */ +/* + * EPC (RW) + * + * Exception program counter. + */ +#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) +#define CSR_MEPC_EPC_SHIFT (1U) +#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) +#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) + +/* Bitfield definition for register: MCAUSE */ +/* + * INTERRUPT (RW) + * + * Interrupt + */ +#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) +#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) +#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) +#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) + +/* + * EXCEPTION_CODE (RW) + * + * Exception code + * When interrupt is 1, the value means: + * 0:User software interrupt + * 1:Supervisor software interrupt + * 3:Machine software interrupt + * 4:User timer interrupt + * 5:Supervisor timer interrupt + * 7:Machine timer interrupt + * 8:User external interrupt + * 9:Supervisor external interrupt + * 11:Machine external interrupt + * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) + * 17:Bus read/write transaction error interrupt (M-mode) + * 18:Performance monitor overflow interrupt (M-mode) + * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) + * 256+17:Bus write transaction error interrupt (S-mode) + * 256+18:Performance monitor overflow interrupt (S-mode) + * When interrupt bit is 0, the value means: + * 0:Instruction address misaligned + * 1:Instruction access fault + * 2:Illegal instruction + * 3:Breakpoint + * 4:Load address misaligned + * 5:Load access fault + * 6:Store/AMO address misaligned + * 7:Store/AMO access fault + * 8:Environment call from U-mode + * 9:Environment call from S-mode + * 11:Environment call from M-mode + * 32:Stack overflow exception + * 33:Stack underflow exception + * 40-47:Reserved + */ +#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) +#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) +#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) +#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) + +/* Bitfield definition for register: MTVAL */ +/* + * MTVAL (RW) + * + * Exception-specific information for software trap handling. + */ +#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) +#define CSR_MTVAL_MTVAL_SHIFT (0U) +#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) +#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) + +/* Bitfield definition for register: MIP */ +/* + * PMOVI (RW) + * + * Performance monitor overflow local interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_PMOVI_MASK (0x40000UL) +#define CSR_MIP_PMOVI_SHIFT (18U) +#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) +#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) + +/* + * BWEI (RW) + * + * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_BWEI_MASK (0x20000UL) +#define CSR_MIP_BWEI_SHIFT (17U) +#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) +#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) + +/* + * IMECCI (RW) + * + * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_IMECCI_MASK (0x10000UL) +#define CSR_MIP_IMECCI_SHIFT (16U) +#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) +#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) + +/* + * MEIP (RW) + * + * M mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MEIP_MASK (0x800U) +#define CSR_MIP_MEIP_SHIFT (11U) +#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) +#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) + +/* + * SEIP (RW) + * + * S mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SEIP_MASK (0x200U) +#define CSR_MIP_SEIP_SHIFT (9U) +#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) +#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) + +/* + * UEIP (RW) + * + * U mode external interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UEIP_MASK (0x100U) +#define CSR_MIP_UEIP_SHIFT (8U) +#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) +#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) + +/* + * MTIP (RW) + * + * M mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MTIP_MASK (0x80U) +#define CSR_MIP_MTIP_SHIFT (7U) +#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) +#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) + +/* + * STIP (RW) + * + * S mode timer interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_STIP_MASK (0x20U) +#define CSR_MIP_STIP_SHIFT (5U) +#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) +#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) + +/* + * UTIP (RW) + * + * U mode timer interrupt pending bit + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_UTIP_MASK (0x10U) +#define CSR_MIP_UTIP_SHIFT (4U) +#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) +#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) + +/* + * MSIP (RW) + * + * M mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_MSIP_MASK (0x8U) +#define CSR_MIP_MSIP_SHIFT (3U) +#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) +#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) + +/* + * SSIP (RW) + * + * S mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_SSIP_MASK (0x2U) +#define CSR_MIP_SSIP_SHIFT (1U) +#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) +#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) + +/* + * USIP (RW) + * + * U mode software interrupt pending bit. + * 0:Not pending + * 1:Pending + */ +#define CSR_MIP_USIP_MASK (0x1U) +#define CSR_MIP_USIP_SHIFT (0U) +#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) +#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) + +/* Bitfield definition for register: PMPCFG0 */ +/* + * PMP3CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) +#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) +#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) + +/* + * PMP2CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) +#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) +#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) + +/* + * PMP1CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) +#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) +#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) +#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) + +/* + * PMP0CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) +#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) +#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) +#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG1 */ +/* + * PMP7CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) +#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) +#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) + +/* + * PMP6CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) +#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) +#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) + +/* + * PMP5CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) +#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) +#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) +#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) + +/* + * PMP4CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) +#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) +#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) +#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG2 */ +/* + * PMP11CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) +#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) +#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) + +/* + * PMP10CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) +#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) +#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) + +/* + * PMP9CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) +#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) +#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) +#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) + +/* + * PMP8CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) +#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) +#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) +#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) + +/* Bitfield definition for register: PMPCFG3 */ +/* + * PMP15CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) +#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) +#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) +#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) + +/* + * PMP14CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) +#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) +#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) +#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) + +/* + * PMP13CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) +#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) +#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) +#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) + +/* + * PMP12CFG (RW) + * + * See PMPCFG Table + */ +#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) +#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) +#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) +#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * Register Content : Match Size(Byte) + * aaaa. . . aaa0 8 + * aaaa. . . aa01 16 + * aaaa. . . a011 32 + * . . . . . . + * aa01. . . 1111 2^{XLEN} + * a011. . . 1111 2^{XLEN+1} + * 0111. . . 1111 2^{XLEN+2} + * 1111. . . 1111 2^{XLEN+3*1} + */ +#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) +#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) +#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) +#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) +#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) +#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) +#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) +#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) +#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) +#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) +#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) +#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) +#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) +#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) +#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) +#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register array: PMPADDR */ +/* + * PMPADDR_31_2 (RW) + * + * same as pmpaddr0 + */ +#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) +#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) +#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) +#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) + +/* Bitfield definition for register: TSELECT */ +/* + * TRIGGER_INDEX (RW) + * + * This register determines which trigger is accessible through other trigger registers. + */ +#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) +#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) +#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) +#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) + +/* Bitfield definition for register: TDATA1 */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + * 3:The selected trigger is an instruction count trigger + * 4:The selected trigger is an interrupt trigger. + * 5:The selected trigger is an exception trigger. + */ +#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) +#define CSR_TDATA1_TYPE_SHIFT (28U) +#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) +#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_TDATA1_DMODE_MASK (0x8000000UL) +#define CSR_TDATA1_DMODE_SHIFT (27U) +#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) +#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) + +/* + * DATA (RW) + * + * Trigger-specific data + */ +#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) +#define CSR_TDATA1_DATA_SHIFT (0U) +#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) +#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) + +/* Bitfield definition for register: MCONTROL */ +/* + * TYPE (RW) + * + * Indicates the trigger type. + * 0:The selected trigger is invalid. + * 2:The selected trigger is an address/data match trigger. + */ +#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) +#define CSR_MCONTROL_TYPE_SHIFT (28U) +#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) +#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) +#define CSR_MCONTROL_DMODE_SHIFT (27U) +#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) +#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) + +/* + * MASKMAX (RO) + * + * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. + */ +#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) +#define CSR_MCONTROL_MASKMAX_SHIFT (21U) +#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_MCONTROL_ACTION_MASK (0xF000U) +#define CSR_MCONTROL_ACTION_SHIFT (12U) +#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) +#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) + +/* + * CHAIN (RW) + * + * Setting this field to enable trigger chain. + * 0:When this trigger matches, the configured action is taken. + * 1:While this trigger does not match, it prevents the trigger with the next index from matching. + * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). + * If Number of Triggers is 4, this field is hardwired + * to 0 on trigger 3 (tselect = 3). + * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). + */ +#define CSR_MCONTROL_CHAIN_MASK (0x800U) +#define CSR_MCONTROL_CHAIN_SHIFT (11U) +#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) +#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) + +/* + * MATCH (RW) + * + * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. + * 2:Matches when the value is greater than (unsigned) or equal to tdata2. + * 3:Matches when the value is less than (unsigned) tdata2 + */ +#define CSR_MCONTROL_MATCH_MASK (0x780U) +#define CSR_MCONTROL_MATCH_SHIFT (7U) +#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) +#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_MCONTROL_M_MASK (0x40U) +#define CSR_MCONTROL_M_SHIFT (6U) +#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) +#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_MCONTROL_U_MASK (0x8U) +#define CSR_MCONTROL_U_SHIFT (3U) +#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) +#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) + +/* + * EXECUTE (RW) + * + * Setting this field to enable this trigger to compare virtual address of an instruction. + */ +#define CSR_MCONTROL_EXECUTE_MASK (0x4U) +#define CSR_MCONTROL_EXECUTE_SHIFT (2U) +#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) +#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) + +/* + * STORE (RW) + * + * Setting this field to enable this trigger to compare virtual address of a store. + */ +#define CSR_MCONTROL_STORE_MASK (0x2U) +#define CSR_MCONTROL_STORE_SHIFT (1U) +#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) +#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) + +/* + * LOAD (RW) + * + * Setting this field to enable this trigger to compare virtual address of a load. + */ +#define CSR_MCONTROL_LOAD_MASK (0x1U) +#define CSR_MCONTROL_LOAD_SHIFT (0U) +#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) +#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) + +/* Bitfield definition for register: ICOUNT */ +/* + * TYPE (RW) + * + * The selected trigger is an instruction count trigger. + */ +#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) +#define CSR_ICOUNT_TYPE_SHIFT (28U) +#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) +#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) +#define CSR_ICOUNT_DMODE_SHIFT (27U) +#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) +#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) + +/* + * COUNT (RO) + * + * This field is hardwired to 1 for single-stepping support + */ +#define CSR_ICOUNT_COUNT_MASK (0x400U) +#define CSR_ICOUNT_COUNT_SHIFT (10U) +#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ICOUNT_M_MASK (0x200U) +#define CSR_ICOUNT_M_SHIFT (9U) +#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) +#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ICOUNT_U_MASK (0x40U) +#define CSR_ICOUNT_U_SHIFT (6U) +#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) +#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ICOUNT_ACTION_MASK (0x3FU) +#define CSR_ICOUNT_ACTION_SHIFT (0U) +#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) +#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) + +/* Bitfield definition for register: ITRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an interrupt trigger. + */ +#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ITRIGGER_TYPE_SHIFT (28U) +#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) +#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ITRIGGER_DMODE_SHIFT (27U) +#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) +#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ITRIGGER_M_MASK (0x200U) +#define CSR_ITRIGGER_M_SHIFT (9U) +#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) +#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ITRIGGER_U_MASK (0x40U) +#define CSR_ITRIGGER_U_SHIFT (6U) +#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) +#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception. + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ITRIGGER_ACTION_MASK (0x3FU) +#define CSR_ITRIGGER_ACTION_SHIFT (0U) +#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) +#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: ETRIGGER */ +/* + * TYPE (RW) + * + * The selected trigger is an exception trigger. + */ +#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) +#define CSR_ETRIGGER_TYPE_SHIFT (28U) +#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) +#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) + +/* + * DMODE (RW) + * + * Setting this field to indicate the trigger is used by Debug Mode. + * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. + * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. + */ +#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) +#define CSR_ETRIGGER_DMODE_SHIFT (27U) +#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) +#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) + +/* + * NMI (RW) + * + * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. + */ +#define CSR_ETRIGGER_NMI_MASK (0x400U) +#define CSR_ETRIGGER_NMI_SHIFT (10U) +#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) +#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) + +/* + * M (RW) + * + * Setting this field to enable this trigger in M-mode. + */ +#define CSR_ETRIGGER_M_MASK (0x200U) +#define CSR_ETRIGGER_M_SHIFT (9U) +#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) +#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) + +/* + * U (RW) + * + * Setting this field to enable this trigger in U-mode. + */ +#define CSR_ETRIGGER_U_MASK (0x40U) +#define CSR_ETRIGGER_U_SHIFT (6U) +#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) +#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) + +/* + * ACTION (RW) + * + * Setting this field to select what happens when this trigger matches. + * 0:Raise a breakpoint exception + * 1:Enter Debug Mode. (Only supported when DMODE is 1.) + */ +#define CSR_ETRIGGER_ACTION_MASK (0x3FU) +#define CSR_ETRIGGER_ACTION_SHIFT (0U) +#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) +#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) + +/* Bitfield definition for register: TDATA2 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA2_DATA_SHIFT (0U) +#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) +#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) + +/* Bitfield definition for register: TDATA3 */ +/* + * DATA (RW) + * + * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. + */ +#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) +#define CSR_TDATA3_DATA_SHIFT (0U) +#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) +#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) + +/* Bitfield definition for register: TEXTRA */ +/* + * MVALUE (RW) + * + * Data used together with MSELECT. + */ +#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) +#define CSR_TEXTRA_MVALUE_SHIFT (26U) +#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) +#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) + +/* + * MSELECT (RW) + * + * 0:Ignore MVALUE. + * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. + */ +#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) +#define CSR_TEXTRA_MSELECT_SHIFT (25U) +#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) +#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) + +/* + * SVALUE (RW) + * + * Data used together with SSELECT. + */ +#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) +#define CSR_TEXTRA_SVALUE_SHIFT (2U) +#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) +#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) + +/* + * SSELECT (RW) + * + * 0:Ignore MVALUE + * 1:This trigger will only match if the lower bits of scontext equal SVALUE + * 2This trigger will only match if satp.ASID equals SVALUE. + */ +#define CSR_TEXTRA_SSELECT_MASK (0x3U) +#define CSR_TEXTRA_SSELECT_SHIFT (0U) +#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) +#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) + +/* Bitfield definition for register: TINFO */ +/* + * INFO (RO) + * + * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that + * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. + * 0:When this bit is set, there is no trigger at this tselect + * 1:Reserved and hardwired to 0. + * 2：When this bit is set, the selected trigger supports type of address/data match trigger + * 3:When this bit is set, the selected trigger supports type of instruction count trigger. + * 4:When this bit is set, the selected trigger supports type of interrupt trigger + * 5:When this bit is set, the selected trigger supports type of exception trigger + * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. + * Others:Reserved for future use. + */ +#define CSR_TINFO_INFO_MASK (0xFFFFU) +#define CSR_TINFO_INFO_SHIFT (0U) +#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) + +/* Bitfield definition for register: TCONTROL */ +/* + * MPTE (RW) + * + * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. + */ +#define CSR_TCONTROL_MPTE_MASK (0x80U) +#define CSR_TCONTROL_MPTE_SHIFT (7U) +#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) +#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) + +/* + * MTE (RW) + * + * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. + * 0:Triggers do not match/fire while the hart is in M-mode. + * 1:Triggers do match/fire while the hart is in M-mode. + */ +#define CSR_TCONTROL_MTE_MASK (0x8U) +#define CSR_TCONTROL_MTE_SHIFT (3U) +#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) +#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) + +/* Bitfield definition for register: MCONTEXT */ +/* + * MCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) +#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) +#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) +#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) + +/* Bitfield definition for register: SCONTEXT */ +/* + * SCONTEXT (RW) + * + * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. + */ +#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) +#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) +#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) +#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) + +/* Bitfield definition for register: DCSR */ +/* + * XDEBUGVER (RO) + * + * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 + */ +#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) +#define CSR_DCSR_XDEBUGVER_SHIFT (28U) +#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) + +/* + * EBREAKM (RW) + * + * This bit controls the behavior of EBREAK instructions in Machine Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKM_MASK (0x8000U) +#define CSR_DCSR_EBREAKM_SHIFT (15U) +#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) +#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) + +/* + * EBREAKU (RW) + * + * This bit controls the behavior of EBREAK instructions in User/Application Mode + * 0:Generate a regular breakpoint exception + * 1:Enter Debug Mode + */ +#define CSR_DCSR_EBREAKU_MASK (0x1000U) +#define CSR_DCSR_EBREAKU_SHIFT (12U) +#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) +#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) + +/* + * STEPIE (RW) + * + * This bit controls whether interrupts are enabled during single stepping + * 0:Disable interrupts during single stepping + * 1:Allow interrupts in single stepping + */ +#define CSR_DCSR_STEPIE_MASK (0x800U) +#define CSR_DCSR_STEPIE_SHIFT (11U) +#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) +#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) + +/* + * STOPCOUNT (RW) + * + * This bit controls whether performance counters are stopped in Debug Mode. + * 0:Do not stop counters in Debug Mode + * 1:Stop counters in Debug Mode + */ +#define CSR_DCSR_STOPCOUNT_MASK (0x400U) +#define CSR_DCSR_STOPCOUNT_SHIFT (10U) +#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) +#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) + +/* + * STOPTIME (RW) + * + * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. + * 0:Do not stop timers in Debug Mode + * 1:Stop timers in Debug Mode + */ +#define CSR_DCSR_STOPTIME_MASK (0x200U) +#define CSR_DCSR_STOPTIME_SHIFT (9U) +#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) +#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) + +/* + * CAUSE (RO) + * + * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger + * 0:Reserved + * 1:EBREAK + * 2:Trigger module + * 3:Halt request + * 4:Single step + * 5:Halt-on-reset + * 6-7:Reserved + */ +#define CSR_DCSR_CAUSE_MASK (0x1C0U) +#define CSR_DCSR_CAUSE_SHIFT (6U) +#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) + +/* + * MPRVEN (RW) + * + * This bit controls whether mstatus.MPRV takes effect in Debug Mode. + * 0:MPRV in mstatus is ignored in Debug Mode. + * 1:MPRV in mstatus takes effect in Debug Mode. + */ +#define CSR_DCSR_MPRVEN_MASK (0x10U) +#define CSR_DCSR_MPRVEN_SHIFT (4U) +#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) +#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) + +/* + * NMIP (RO) + * + * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. + */ +#define CSR_DCSR_NMIP_MASK (0x8U) +#define CSR_DCSR_NMIP_SHIFT (3U) +#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) + +/* + * STEP (RW) + * + * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. + * 0:Single Step Mode is off + * 1:Single Step Mode is on + */ +#define CSR_DCSR_STEP_MASK (0x4U) +#define CSR_DCSR_STEP_SHIFT (2U) +#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) +#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) + +/* + * PRV (RW) + * + * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. + * 0:User/Application + * 1:Supervisor + * 2:Reserved + * 3:Machine + */ +#define CSR_DCSR_PRV_MASK (0x3U) +#define CSR_DCSR_PRV_SHIFT (0U) +#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) +#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) + +/* Bitfield definition for register: DPC */ +/* + * DPC (RW) + * + * Debug Program Counter. Bit 0 is hardwired to 0. + */ +#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) +#define CSR_DPC_DPC_SHIFT (0U) +#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) +#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) + +/* Bitfield definition for register: DSCRATCH0 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) + +/* Bitfield definition for register: DSCRATCH1 */ +/* + * DSCRATCH (RO) + * + * A scratch register that is reserved for use by Debug Module. + */ +#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) +#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) +#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) + +/* Bitfield definition for register: MCYCLE */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLE_COUNTER_SHIFT (0U) +#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) +#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRET */ +/* + * COUNTER (RW) + * + * the lower 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRET_COUNTER_SHIFT (0U) +#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) +#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) +#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) +#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) +#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6 */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) +#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) + +/* Bitfield definition for register: MCYCLEH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Cycle Counter + */ +#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MCYCLEH_COUNTER_SHIFT (0U) +#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) +#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) + +/* Bitfield definition for register: MINSTRETH */ +/* + * COUNTER (RW) + * + * the higher 32 bits of Machine Instruction-Retired Counter + */ +#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MINSTRETH_COUNTER_SHIFT (0U) +#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) +#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER3H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent3 + */ +#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) +#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER4H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent4 + */ +#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) +#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER5H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent5 + */ +#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) +#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) + +/* Bitfield definition for register: MHPMCOUNTER6H */ +/* + * COUNTER (RW) + * + * count the num- ber of events selected by mhpmevent6 + */ +#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) +#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) +#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) +#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) + +/* Bitfield definition for register: CYCLE */ +/* + * CYCLE (RW) + * + * Cycle Counter + */ +#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) +#define CSR_CYCLE_CYCLE_SHIFT (0U) +#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) +#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) + +/* Bitfield definition for register: CYCLEH */ +/* + * CYCLEH (RW) + * + * Cycle Counter Higher 32-bit + */ +#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) +#define CSR_CYCLEH_CYCLEH_SHIFT (0U) +#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) +#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) + +/* Bitfield definition for register: MVENDORID */ +/* + * MVENDORID (RO) + * + * The manufacturer ID + */ +#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) +#define CSR_MVENDORID_MVENDORID_SHIFT (0U) +#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) + +/* Bitfield definition for register: MARCHID */ +/* + * CPU_ID (RO) + * + * CPU ID + */ +#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) +#define CSR_MARCHID_CPU_ID_SHIFT (0U) +#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) + +/* Bitfield definition for register: MIMPID */ +/* + * MAJOR (RO) + * + * Revision major + */ +#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) +#define CSR_MIMPID_MAJOR_SHIFT (8U) +#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) + +/* + * MINOR (RO) + * + * Revision minor + */ +#define CSR_MIMPID_MINOR_MASK (0xF0U) +#define CSR_MIMPID_MINOR_SHIFT (4U) +#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) + +/* + * EXTENSION (RO) + * + * Revision extension + */ +#define CSR_MIMPID_EXTENSION_MASK (0xFU) +#define CSR_MIMPID_EXTENSION_SHIFT (0U) +#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) + +/* Bitfield definition for register: MHARTID */ +/* + * MHARTID (RO) + * + * Hart ID + */ +#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) +#define CSR_MHARTID_MHARTID_SHIFT (0U) +#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) + +/* NON-STANDARD CRS register bitfiled definitions */ + +/* Bitfield definition for register: MCOUNTINHIBIT */ +/* + * HPM6 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) +#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) +#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) +#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) +#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) +#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) +#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) +#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) +#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) +#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) +#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) +#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) +#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) +#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) +#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) +#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) + +/* + * TM (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) +#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) +#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) +#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) + +/* + * CY (RW) + * + * See register description. + */ +#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) +#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) +#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) +#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) + +/* Bitfield definition for register: MILMB */ +/* + * IBPA (RO) + * + * The base physical address of ILM. It has to be an integer multiple of the ILM size + */ +#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) +#define CSR_MILMB_IBPA_SHIFT (10U) +#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MILMB_RWECC_MASK (0x8U) +#define CSR_MILMB_RWECC_SHIFT (3U) +#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) +#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MILMB_ECCEN_MASK (0x6U) +#define CSR_MILMB_ECCEN_SHIFT (1U) +#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) +#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) + +/* + * IEN (RO) + * + * ILM enable control: + * 0:ILM is disabled + * 1:ILM is enabled + */ +#define CSR_MILMB_IEN_MASK (0x1U) +#define CSR_MILMB_IEN_SHIFT (0U) +#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) + +/* Bitfield definition for register: MDLMB */ +/* + * DBPA (RO) + * + * The base physical address of DLM. It has to be an integer multiple of the DLM size + */ +#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) +#define CSR_MDLMB_DBPA_SHIFT (10U) +#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) + +/* + * RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MDLMB_RWECC_MASK (0x8U) +#define CSR_MDLMB_RWECC_SHIFT (3U) +#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) +#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) + +/* + * ECCEN (RW) + * + * Parity/ECC enable control: + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MDLMB_ECCEN_MASK (0x6U) +#define CSR_MDLMB_ECCEN_SHIFT (1U) +#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) +#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) + +/* + * DEN (RO) + * + * DLM enable control: + * 0:DLM is disabled + * 1:DLM is enabled + */ +#define CSR_MDLMB_DEN_MASK (0x1U) +#define CSR_MDLMB_DEN_SHIFT (0U) +#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) + +/* Bitfield definition for register: MECC_CODE */ +/* + * INSN (RO) + * + * Indicates if the parity/ECC error is caused by instruction fetch or data access. + * 0:Data access + * 1:Instruction fetch + */ +#define CSR_MECC_CODE_INSN_MASK (0x400000UL) +#define CSR_MECC_CODE_INSN_SHIFT (22U) +#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) + +/* + * RAMID (RO) + * + * The ID of RAM that caused parity/ECC errors. + * This bit is updated on parity/ECC error exceptions. + * 0–1:Reserved + * 2:Tag RAM of I-Cache + * 3:Data RAM of I-Cache + * 4:Tag RAM of D-Cache + * 5:Data RAM of D-Cache + * 6:Tag RAM of TLB + * 7:Data RAM of TLB + * 8:ILM + * 9:DLM + * 10–15:Reserved + */ +#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) +#define CSR_MECC_CODE_RAMID_SHIFT (18U) +#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) + +/* + * P (RO) + * + * Precise error. This bit is updated on parity/ECC error exceptions. + * 0:Imprecise error + * 1:Precise error + */ +#define CSR_MECC_CODE_P_MASK (0x20000UL) +#define CSR_MECC_CODE_P_SHIFT (17U) +#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) + +/* + * C (RO) + * + * Correctable error. This bit is updated on parity/ECC error exceptions. + * 0:Uncorrectable error + * 1:Correctable error + */ +#define CSR_MECC_CODE_C_MASK (0x10000UL) +#define CSR_MECC_CODE_C_SHIFT (16U) +#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) + +/* + * CODE (RW) + * + * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). + */ +#define CSR_MECC_CODE_CODE_MASK (0x7FU) +#define CSR_MECC_CODE_CODE_SHIFT (0U) +#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) +#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) + +/* Bitfield definition for register: MNVEC */ +/* + * MNVEC (RO) + * + * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. + */ +#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) +#define CSR_MNVEC_MNVEC_SHIFT (0U) +#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) + +/* Bitfield definition for register: MXSTATUS */ +/* + * PDME (RW) + * + * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. + */ +#define CSR_MXSTATUS_PDME_MASK (0x20U) +#define CSR_MXSTATUS_PDME_SHIFT (5U) +#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) +#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) + +/* + * DME (RW) + * + * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. + */ +#define CSR_MXSTATUS_DME_MASK (0x10U) +#define CSR_MXSTATUS_DME_SHIFT (4U) +#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) +#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) + +/* + * PIME (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_PIME_MASK (0x8U) +#define CSR_MXSTATUS_PIME_SHIFT (3U) +#define CSR_MXSTATUS_PIME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PIME_SHIFT) & CSR_MXSTATUS_PIME_MASK) +#define CSR_MXSTATUS_PIME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PIME_MASK) >> CSR_MXSTATUS_PIME_SHIFT) + +/* + * IME (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_IME_MASK (0x4U) +#define CSR_MXSTATUS_IME_SHIFT (2U) +#define CSR_MXSTATUS_IME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_IME_SHIFT) & CSR_MXSTATUS_IME_MASK) +#define CSR_MXSTATUS_IME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_IME_MASK) >> CSR_MXSTATUS_IME_SHIFT) + +/* + * PPFT_EN (RW) + * + * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding + * is defined as follows: + * 0: User mode + * 1: Supervisor mode + * 2: Reserved + * 3: Machine mode + */ +#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) +#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) +#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) +#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) + +/* + * PFT_EN (RW) + * + * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: + * PPFT_EN <= PFT_EN; + * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; + * On executing an MRET instruction: + * PFT_EN <= PPFT_EN; + * This field is hardwired to 0 if the PowerBrake feature is not supported. + */ +#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) +#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) +#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) +#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) + +/* Bitfield definition for register: MPFT_CTL */ +/* + * FAST_INT (RW) + * + * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. + */ +#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) +#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) +#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) +#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) + +/* + * T_LEVEL (RW) + * + * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest + * performance at throttling level 15. + * 0:Level 0 (the highest performance) + * 1-14:Level 1-14 + * 15:Level 15 (the lowest performance) + */ +#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) +#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) +#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) +#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) + +/* Bitfield definition for register: MHSP_CTL */ +/* + * M (RW) + * + * Enables the SP protection and recording mechanism in Machine mode + * 0:The mechanism is disabled in Machine mode. + * 1: The mechanism is enabled in Machine mode. + */ +#define CSR_MHSP_CTL_M_MASK (0x20U) +#define CSR_MHSP_CTL_M_SHIFT (5U) +#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) +#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) + +/* + * S (RW) + * + * Enables the SP protection and recording mechanism in Supervisor mode + * 0:The mechanism is disabled in Supervisor mode + * 1:The mechanism is enabled in Supervisor mode + */ +#define CSR_MHSP_CTL_S_MASK (0x10U) +#define CSR_MHSP_CTL_S_SHIFT (4U) +#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) +#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) + +/* + * U (RW) + * + * Enables the SP protection and recording mechanism in User mode + * 0:The mechanism is disabled in User mode + * 1:The mechanism is enabled in User mode. + */ +#define CSR_MHSP_CTL_U_MASK (0x8U) +#define CSR_MHSP_CTL_U_SHIFT (3U) +#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) +#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) + +/* + * SCHM (RW) + * + * Selects the operating scheme of the stack protection and recording mechanism + * 0:Stack overflow/underflow detection + * 1:Top-of-stack recording + */ +#define CSR_MHSP_CTL_SCHM_MASK (0x4U) +#define CSR_MHSP_CTL_SCHM_SHIFT (2U) +#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) +#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) + +/* + * UDF_EN (RW) + * + * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack underflow protection is disabled + * 1:The stack underflow protection is enabled. + */ +#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) +#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) +#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) +#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) + +/* + * OVF_EN (RW) + * + * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. + * 0:The stack overflow protection and recording mechanism are disabled. + * 1:The stack overflow protection and recording mechanism are enabled. + */ +#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) +#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) +#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) +#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) + +/* Bitfield definition for register: MSP_BOUND */ +/* + * MSP_BOUND (RW) + * + * Machine SP Bound + */ +#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) +#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) +#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) + +/* Bitfield definition for register: MSP_BASE */ +/* + * SP_BASE (RW) + * + * Machine SP base + */ +#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) +#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) +#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) +#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) + +/* Bitfield definition for register: MDCAUSE */ +/* + * MDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the mcause register. + * The value of MDCAUSE for precise exception: + * When mcause == 1 (Instruction access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access + * When mcause == 2 (Illegal instruction): + * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception + * When mcause == 5 (Load access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * When mcause == 7 (Store access fault): + * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception + * The value of MDCAUSE for imprecise exception: + * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) + * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error + * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) + * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions + */ +#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) +#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) +#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) +#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) + +/* Bitfield definition for register: MCACHE_CTL */ +/* + * IC_FIRST_WORD (RO) + * + * Cache miss allocation filling policy + * 0:Cache line data is returned critical (double) word first + * 1:Cache line data is returned the lowest address (double) word first + */ +#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) +#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) + +/* + * CCTL_SUEN (RW) + * + * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs + * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) +#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) +#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) + +/* + * DC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) +#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) +#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) +#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) + +/* + * IC_RWECC (RW) + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. + * 0:Disable diagnostic accesses of ECC codes + * 1:Enable diagnostic accesses of ECC codes + */ +#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) +#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) +#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) +#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) + +/* + * DC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * data cache. + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) +#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) +#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) +#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) + +/* + * IC_ECCEN (RW) + * + * Parity/ECC error checking enable control for the + * instruction cache + * 0:Disable parity/ECC + * 1:Reserved + * 2:Generate exceptions only on uncorrectable parity/ECC errors + * 3:Generate exceptions on any type of parity/ECC errors + */ +#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) +#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) +#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) +#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) + +/* + * DC_EN (RW) + * + * Controls if the data cache is enabled or not. + * 0:D-Cache is disabled + * 1:D-Cache is enabled + */ +#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) +#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) +#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) +#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) + +/* + * IC_EN (RW) + * + * Controls if the instruction cache is enabled or not. + * 0:I-Cache is disabled + * 1:I-Cache is enabled + */ +#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) +#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) +#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) +#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) + +/* Bitfield definition for register: MCCTLBEGINADDR */ +/* + * VA (RW) + * + * This register holds the address information required by CCTL operations + */ +#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) +#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: MCCTLCOMMAND */ +/* + * VA (RW) + * + * See CCTL Command Definition Table + */ +#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) +#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: MCCTLDATA */ +/* + * VA (RW) + * + * See CCTL Commands Which Access mcctldata Table + */ +#define CSR_MCCTLDATA_VA_MASK (0x1FU) +#define CSR_MCCTLDATA_VA_SHIFT (0U) +#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) +#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) + +/* Bitfield definition for register: MCOUNTERWEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) +#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) +#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) +#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) +#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_IR_MASK (0x4U) +#define CSR_MCOUNTERWEN_IR_SHIFT (2U) +#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) +#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERWEN_CY_MASK (0x1U) +#define CSR_MCOUNTERWEN_CY_SHIFT (0U) +#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) +#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERINTEN */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) +#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) +#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) +#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) +#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) +#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) +#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) +#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) +#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) +#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) +#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) +#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) +#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) +#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) +#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) +#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) +#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) +#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) +#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) + +/* Bitfield definition for register: MMISC_CTL */ +/* + * MSA_UNA (RW) + * + * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. + * Supported instructions: LW/LH/LHU/SW/SH + * 0:Misaligned accesses generate Address Misaligned exceptions. + * 1:Misaligned accesses generate Address Misaligned exceptions. + */ +#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) +#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) +#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) +#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) + +/* + * BRPE (RW) + * + * Branch prediction enable bit. This bit controls all branch prediction structures. + * 0:Disabled + * 1:Enabled + * This bit is hardwired to 0 if branch prediction structure is not supported. + */ +#define CSR_MMISC_CTL_BRPE_MASK (0x8U) +#define CSR_MMISC_CTL_BRPE_SHIFT (3U) +#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) +#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) + +/* + * RVCOMPM (RW) + * + * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions + * 0:Disabled + * 1:Enabled + */ +#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) +#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) +#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) +#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) + +/* + * VEC_PLIC (RW) + * + * Selects the operation mode of PLIC: + * 0:Regular mode + * 1:Vector mode + * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. + */ +#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) +#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) +#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) +#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_M */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) +#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) +#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) +#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) +#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) +#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) +#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_S */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) +#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) +#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) +#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) +#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) +#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) +#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTERMASK_U */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) +#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) +#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) +#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) +#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) +#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) +#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) +#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) +#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) +#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) +#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) +#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) +#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) +#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) +#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) +#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) +#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) +#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) +#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) + +/* Bitfield definition for register: MCOUNTEROVF */ +/* + * HPM6 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) +#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) +#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) +#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) + +/* + * HPM5 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) +#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) +#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) +#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) + +/* + * HPM4 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) +#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) +#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) +#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) + +/* + * HPM3 (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) +#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) +#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) +#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) + +/* + * IR (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_IR_MASK (0x4U) +#define CSR_MCOUNTEROVF_IR_SHIFT (2U) +#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) +#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) + +/* + * CY (RW) + * + * See register description + */ +#define CSR_MCOUNTEROVF_CY_MASK (0x1U) +#define CSR_MCOUNTEROVF_CY_SHIFT (0U) +#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) +#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) + +/* Bitfield definition for register: DEXC2DBG */ +/* + * PMOV (RW) + * + * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) +#define CSR_DEXC2DBG_PMOV_SHIFT (19U) +#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) +#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) + +/* + * BWE (RW) + * + * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_BWE_MASK (0x8000U) +#define CSR_DEXC2DBG_BWE_SHIFT (15U) +#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) +#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) + +/* + * SLPECC (RW) + * + * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) +#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) +#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) +#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) + +/* + * ACE (RW) + * + * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_ACE_MASK (0x2000U) +#define CSR_DEXC2DBG_ACE_SHIFT (13U) +#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) +#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) + +/* + * HSP (RW) + * + * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_HSP_MASK (0x1000U) +#define CSR_DEXC2DBG_HSP_SHIFT (12U) +#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) +#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) + +/* + * MEC (RW) + * + * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_MEC_MASK (0x800U) +#define CSR_DEXC2DBG_MEC_SHIFT (11U) +#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) +#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) + +/* + * UEC (RW) + * + * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_UEC_MASK (0x100U) +#define CSR_DEXC2DBG_UEC_SHIFT (8U) +#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) +#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) + +/* + * SAF (RW) + * + * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAF_MASK (0x80U) +#define CSR_DEXC2DBG_SAF_SHIFT (7U) +#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) +#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) + +/* + * SAM (RW) + * + * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_SAM_MASK (0x40U) +#define CSR_DEXC2DBG_SAM_SHIFT (6U) +#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) +#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) + +/* + * LAF (RW) + * + * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAF_MASK (0x20U) +#define CSR_DEXC2DBG_LAF_SHIFT (5U) +#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) +#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) + +/* + * LAM (RW) + * + * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_LAM_MASK (0x10U) +#define CSR_DEXC2DBG_LAM_SHIFT (4U) +#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) +#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) + +/* + * NMI (RW) + * + * Indicates whether Non-Maskable Interrupt + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_NMI_MASK (0x8U) +#define CSR_DEXC2DBG_NMI_SHIFT (3U) +#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) +#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) + +/* + * II (RW) + * + * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_II_MASK (0x4U) +#define CSR_DEXC2DBG_II_SHIFT (2U) +#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) +#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) + +/* + * IAF (RW) + * + * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAF_MASK (0x2U) +#define CSR_DEXC2DBG_IAF_SHIFT (1U) +#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) +#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) + +/* + * IAM (RW) + * + * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. + * 0:Do not redirect + * 1:Redirect + */ +#define CSR_DEXC2DBG_IAM_MASK (0x1U) +#define CSR_DEXC2DBG_IAM_SHIFT (0U) +#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) +#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) + +/* Bitfield definition for register: DDCAUSE */ +/* + * SUBTYPE (RO) + * + * Subtypes for main type. + * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. + * 0:Illegal instruction + * 1:Privileged instruction + * 2:Non-existent CSR + * 3:Privilege CSR access + * 4:Read-only CSR update + */ +#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) +#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) +#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) + +/* + * MAINTYPE (RO) + * + * Cause for redirection to Debug Mode. + * 0:Software Breakpoint (EBREAK) + * 1:Instruction Access Misaligned (IAM) + * 2:Instruction Access Fault (IAF) + * 3:Illegal Instruction (II) + * 4:Non-Maskable Interrupt (NMI) + * 5:Load Access Misaligned (LAM) + * 6:Load Access Fault (LAF) + * 7:Store Access Misaligned (SAM) + * 8:Store Access Fault (SAF) + * 9:U-mode Environment Call (UEC) + * 10:S-mode Environment Call (SEC) + * 11:Instruction page fault + * 12:M-mode Environment Call (MEC) + * 13:Load page fault + * 14:Reserved + * 15:Store/AMO page fault + * 16:Imprecise ECC error + * 17;Bus write transaction error + * 18:Performance Counter overflow + * 19–31:Reserved + * 32:Stack overflow exception + * 33:Stack underflow exception + * 34:ACE disabled exception + * 35–39:Reserved + * 40–47:ACE exception + * ≥48:Reserved + */ +#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) +#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) +#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) + +/* Bitfield definition for register: UITB */ +/* + * ADDR (RW) + * + * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. + */ +#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) +#define CSR_UITB_ADDR_SHIFT (2U) +#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) +#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) + +/* + * HW (RO) + * + * This bit specifies if the CoDense instruction table is hardwired. + * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. + * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. + */ +#define CSR_UITB_HW_MASK (0x1U) +#define CSR_UITB_HW_SHIFT (0U) +#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) + +/* Bitfield definition for register: UCODE */ +/* + * OV (RW) + * + * Overflow flag. It will be set by DSP instructions with a saturated result. + * 0:A saturated result is not generated + * 1:A saturated result is generated + */ +#define CSR_UCODE_OV_MASK (0x1U) +#define CSR_UCODE_OV_SHIFT (0U) +#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) +#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) + +/* Bitfield definition for register: UDCAUSE */ +/* + * UDCAUSE (RW) + * + * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. + * The value of UDCAUSE for precise exception: + * When ucause == 1 (Instruction access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP instruction access violation + * 3:Bus error + * 4:PMA empty hole access + * When ucause == 2 (Illegal instruction) + * 0:Please parse the utval CSR + * 1:FP disabled exception + * 2:ACE disabled exception + * When ucause == 5 (Load access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP load access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + * When ucause == 7 (Store access fault) + * 0:Reserved + * 1:ECC/Parity error + * 2:PMP store access violation + * 3:Bus error + * 4:Misaligned address + * 5:PMA empty hole access + * 6:PMA attribute inconsistency + * 7:PMA NAMO exception + */ +#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) +#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) +#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) +#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) + +/* Bitfield definition for register: UCCTLBEGINADDR */ +/* + * VA (RW) + * + * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. + */ +#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) +#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) +#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) +#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) + +/* Bitfield definition for register: UCCTLCOMMAND */ +/* + * VA (RW) + * + * See User CCTL Command Definition Table + */ +#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) +#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) +#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) +#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) + +/* Bitfield definition for register: MICM_CFG */ +/* + * SETH (RO) + * + * This bit extends the ISET field. + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MICM_CFG_SETH_SHIFT (24U) +#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) + +/* + * ILM_ECC (RO) + * + * ILM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) +#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) +#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) + +/* + * ILMSZ (RO) + * + * ILM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) +#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) +#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) + +/* + * ILMB (RW) + * + * Number of ILM base registers present + * 0:No ILM base register present + * 1:One ILM base register present + * 2-7:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILMB_MASK (0x7000U) +#define CSR_MICM_CFG_ILMB_SHIFT (12U) +#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) +#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) + +/* + * IC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) +#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) +#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) + +/* + * ILCK (RO) + * + * I-Cache locking support + * 0:No locking support + * 1:With locking support + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ILCK_MASK (0x200U) +#define CSR_MICM_CFG_ILCK_SHIFT (9U) +#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) + +/* + * ISZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) +#define CSR_MICM_CFG_ISZ_SHIFT (6U) +#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) + +/* + * IWAY (RO) + * + * Associativity of I-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MICM_CFG_IWAY_MASK (0x38U) +#define CSR_MICM_CFG_IWAY_SHIFT (3U) +#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) + +/* + * ISET (RO) + * + * I-Cache sets (# of cache lines per way): + * When micm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When micm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + */ +#define CSR_MICM_CFG_ISET_MASK (0x7U) +#define CSR_MICM_CFG_ISET_SHIFT (0U) +#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) + +/* Bitfield definition for register: MDCM_CFG */ +/* + * SETH (RO) + * + * This bit extends the DSET field. + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) +#define CSR_MDCM_CFG_SETH_SHIFT (24U) +#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) + +/* + * DLM_ECC (RO) + * + * DLM soft-error protection scheme + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + * When DLM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) +#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) +#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) + +/* + * DLMSZ (RO) + * + * DLM Size + * 0:0 Byte + * 1:1 KiB + * 2:2 KiB + * 3:4 KiB + * 4:8 KiB + * 5:16 KiB + * 6:32 KiB + * 7:64 KiB + * 8:128 KiB + * 9:256 KiB + * 10:512 KiB + * 11:1 MiB + * 12:2 MiB + * 13:4 MiB + * 14:8 MiB + * 15:16 MiB + * 16-31:Reserved + * When ILM is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) +#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) +#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) + +/* + * DLMB (RO) + * + * Number of DLM base registers present + * 0:No DLM base register present + * 1:One DLM base register present + * 2-7:Reserved + * When DLM is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) +#define CSR_MDCM_CFG_DLMB_SHIFT (12U) +#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) + +/* + * DC_ECC (RO) + * + * Cache soft-error protection scheme + * 0:No parity/ECC support + * 1:Has parity support + * 2:Has ECC support + * 3:Reserved + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) +#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) +#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) + +/* + * DLCK (RO) + * + * D-Cache locking support + * 0:No locking support + * 1:With locking support + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DLCK_MASK (0x200U) +#define CSR_MDCM_CFG_DLCK_SHIFT (9U) +#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) + +/* + * DSZ (RO) + * + * Cache block (line) size + * 0:No I-Cache + * 1:8 bytes + * 2:16 bytes + * 3:32 bytes + * 4:64 bytes + * 5:128 bytes + * 6-7:Reserved + * When instruction cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) +#define CSR_MDCM_CFG_DSZ_SHIFT (6U) +#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) + +/* + * DWAY (RO) + * + * Associativity of D-Cache + * 0:Direct-mapped + * 1:2-way + * 2:3-way + * 3:4-way + * 4:5-way + * 5:6-way + * 6:7-way + * 7:8-way + * When data cache is not configured, this field should be ignored. + */ +#define CSR_MDCM_CFG_DWAY_MASK (0x38U) +#define CSR_MDCM_CFG_DWAY_SHIFT (3U) +#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) + +/* + * DSET (RO) + * + * D-Cache sets (# of cache lines per way): + * When mdcm_cfg.SETH==0: + * 0:64 + * 1:128 + * 2:256 + * 3:512 + * 4:1024 + * 5:2048 + * 6:4096 + * 7:Reserved + * When mdcm_cfg.SETH==1: + * 0:32 + * 1:16 + * 2:8 + * 3-7:Reserved + * When data cache is not configured, this field should be ignored + */ +#define CSR_MDCM_CFG_DSET_MASK (0x7U) +#define CSR_MDCM_CFG_DSET_SHIFT (0U) +#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) + +/* Bitfield definition for register: MMSC_CFG */ +/* + * MSC_EXT (RO) + * + * Indicates if the mmsc_cfg2 CSR is present or not. + * 0:The mmsc_cfg2 CSR is not present. + * 1:The mmsc_cfg2 CSR is present + */ +#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) +#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) +#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) + +/* + * PPMA (RO) + * + * Indicates if programmable PMA setup with PMA region CSRs is supported or not + * 0:Programmable PMA setup is not supported. + * 1:Programmable PMA setup is supported. + */ +#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) +#define CSR_MMSC_CFG_PPMA_SHIFT (30U) +#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) + +/* + * EDSP (RO) + * + * Indicates if the DSP extension is supported or not + * 0:The DSP extension is not supported. + * 1:The DSP extension is supported. + */ +#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) +#define CSR_MMSC_CFG_EDSP_SHIFT (29U) +#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) + +/* + * VCCTL (RO) + * + * Indicates the version number of CCTL command operation scheme supported by an implementation + * 0:instruction cache and data cache are not configured. + * 1:instruction cache or data cache is configured. + */ +#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) +#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) +#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) + +/* + * EFHW (RO) + * + * Indicates the support of FLHW and FSHW instructions + * 0:FLHW and FSHW instructions are not supported + * 1:FLHW and FSHW instructions are supported. + */ +#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) +#define CSR_MMSC_CFG_EFHW_SHIFT (17U) +#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) + +/* + * CCTLCSR (RO) + * + * Indicates the presence of CSRs for CCTL operations. + * 0:Feature of CSRs for CCTL operations is not supported. + * 1:Feature of CSRs for CCTL operations is supported. + */ +#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) +#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) +#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) + +/* + * PMNDS (RO) + * + * Indicates if Andes-enhanced performance monitoring feature is present or no. + * 0:Andes-enhanced performance monitoring feature is not supported. + * 1:Andes-enhanced performance monitoring feature is supported. + */ +#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) +#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) +#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) + +/* + * LMSLVP (RO) + * + * Indicates if local memory slave port is present or not. + * 0:Local memory slave port is not present. + * 1:Local memory slave port is implemented. + */ +#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) +#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) +#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) + +/* + * EV5PE (RO) + * + * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) +#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) +#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) + +/* + * VPLIC (RO) + * + * Indicates whether the Andes Vectored PLIC Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) +#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) +#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) + +/* + * ACE (RO) + * + * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ACE_MASK (0x40U) +#define CSR_MMSC_CFG_ACE_SHIFT (6U) +#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) + +/* + * HSP (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_HSP_MASK (0x20U) +#define CSR_MMSC_CFG_HSP_SHIFT (5U) +#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) + +/* + * PFT (RO) + * + * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_PFT_MASK (0x10U) +#define CSR_MMSC_CFG_PFT_SHIFT (4U) +#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) + +/* + * ECD (RO) + * + * Indicates whether the Andes CoDense Extension is implemented or not. + * 0:Not implemented. + * 1:Implemented. + */ +#define CSR_MMSC_CFG_ECD_MASK (0x8U) +#define CSR_MMSC_CFG_ECD_SHIFT (3U) +#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) + +/* + * TLB_ECC (RO) + * + * TLB parity/ECC support configuration. + * 0:No parity/ECC + * 1:Parity + * 2:ECC + * 3:Reserved + */ +#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) +#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) +#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) + +/* + * ECC (RO) + * + * Indicates whether the parity/ECC soft-error protection is implemented or not. + * 0:Not implemented. + * 1:Implemented. + * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. + * micm_cfg.IC_ECC + * micm_cfg.ILM_ECC + * mdcm_cfg.DC_ECC + * mdcm_cfg.DLM_ECC + * mmsc_cfg.TLB_ECC + */ +#define CSR_MMSC_CFG_ECC_MASK (0x1U) +#define CSR_MMSC_CFG_ECC_SHIFT (0U) +#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) + +/* Bitfield definition for register: MMSC_CFG2 */ +/* + * FINV (RO) + * + * Indicates if scalar FPU is implemented in VPU + * 0:Scalar FPU is not implemented in VPU + * 1:Scalar FPU is implemented in VPU + */ +#define CSR_MMSC_CFG2_FINV_MASK (0x20U) +#define CSR_MMSC_CFG2_FINV_SHIFT (5U) +#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) + +/* + * ZFH (RO) + * + * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. + * 0:The FP16 extension is not supported. + * 1:The FP16 extension is supported + */ +#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) +#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) +#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) + +/* + * BF16CVT (RO) + * + * Indicates if the BFLOAT16 conversion extension + * is supported or not. + * 0:The BFLOAT16 conversion extension is not supported + * 1:The BFLOAT16 conversion extension is supported + */ +#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) +#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) +#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) + + +#endif /* HPM_CSR_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_dmamux_regs.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_dmamux_regs.h new file mode 100644 index 00000000..eeb4b039 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_dmamux_regs.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_H +#define HPM_DMAMUX_H + +typedef struct { + __RW uint32_t MUXCFG[32]; /* 0x0 - 0x7C: HDMA MUX0 Configuration */ +} DMAMUX_Type; + + +/* Bitfield definition for register array: MUXCFG */ +/* + * ENABLE (RW) + * + * DMA Mux Channel Enable + * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be + * used to disable or reconfigure a DMA channel. + * 0b - DMA Mux channel is disabled + * 1b - DMA Mux channel is enabled + */ +#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) +#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) +#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) +#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) + +/* + * SOURCE (RW) + * + * DMA Channel Source + * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" + */ +#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) +#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) +#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) +#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) + + + +/* MUXCFG register group index macro definition */ +#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) +#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) +#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) +#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) +#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) +#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) +#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) +#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) +#define DMAMUX_MUXCFG_HDMA_MUX8 (8UL) +#define DMAMUX_MUXCFG_HDMA_MUX9 (9UL) +#define DMAMUX_MUXCFG_HDMA_MUX10 (10UL) +#define DMAMUX_MUXCFG_HDMA_MUX11 (11UL) +#define DMAMUX_MUXCFG_HDMA_MUX12 (12UL) +#define DMAMUX_MUXCFG_HDMA_MUX13 (13UL) +#define DMAMUX_MUXCFG_HDMA_MUX14 (14UL) +#define DMAMUX_MUXCFG_HDMA_MUX15 (15UL) +#define DMAMUX_MUXCFG_HDMA_MUX16 (16UL) +#define DMAMUX_MUXCFG_HDMA_MUX17 (17UL) +#define DMAMUX_MUXCFG_HDMA_MUX18 (18UL) +#define DMAMUX_MUXCFG_HDMA_MUX19 (19UL) +#define DMAMUX_MUXCFG_HDMA_MUX20 (20UL) +#define DMAMUX_MUXCFG_HDMA_MUX21 (21UL) +#define DMAMUX_MUXCFG_HDMA_MUX22 (22UL) +#define DMAMUX_MUXCFG_HDMA_MUX23 (23UL) +#define DMAMUX_MUXCFG_HDMA_MUX24 (24UL) +#define DMAMUX_MUXCFG_HDMA_MUX25 (25UL) +#define DMAMUX_MUXCFG_HDMA_MUX26 (26UL) +#define DMAMUX_MUXCFG_HDMA_MUX27 (27UL) +#define DMAMUX_MUXCFG_HDMA_MUX28 (28UL) +#define DMAMUX_MUXCFG_HDMA_MUX29 (29UL) +#define DMAMUX_MUXCFG_HDMA_MUX30 (30UL) +#define DMAMUX_MUXCFG_HDMA_MUX31 (31UL) + + +#endif /* HPM_DMAMUX_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_dmamux_src.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_dmamux_src.h new file mode 100644 index 00000000..7cffbbd9 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_dmamux_src.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAMUX_SRC_H +#define HPM_DMAMUX_SRC_H + +/* dma mux definitions */ +#define HPM_DMA_SRC_GPTMR0_0 (0x0UL) +#define HPM_DMA_SRC_GPTMR0_1 (0x1UL) +#define HPM_DMA_SRC_GPTMR0_2 (0x2UL) +#define HPM_DMA_SRC_GPTMR0_3 (0x3UL) +#define HPM_DMA_SRC_GPTMR1_0 (0x4UL) +#define HPM_DMA_SRC_GPTMR1_1 (0x5UL) +#define HPM_DMA_SRC_GPTMR1_2 (0x6UL) +#define HPM_DMA_SRC_GPTMR1_3 (0x7UL) +#define HPM_DMA_SRC_GPTMR2_0 (0x8UL) +#define HPM_DMA_SRC_GPTMR2_1 (0x9UL) +#define HPM_DMA_SRC_GPTMR2_2 (0xAUL) +#define HPM_DMA_SRC_GPTMR2_3 (0xBUL) +#define HPM_DMA_SRC_GPTMR3_0 (0xCUL) +#define HPM_DMA_SRC_GPTMR3_1 (0xDUL) +#define HPM_DMA_SRC_GPTMR3_2 (0xEUL) +#define HPM_DMA_SRC_GPTMR3_3 (0xFUL) +#define HPM_DMA_SRC_LIN0 (0x10UL) +#define HPM_DMA_SRC_LIN1 (0x11UL) +#define HPM_DMA_SRC_LIN2 (0x12UL) +#define HPM_DMA_SRC_LIN3 (0x13UL) +#define HPM_DMA_SRC_UART0_RX (0x14UL) +#define HPM_DMA_SRC_UART0_TX (0x15UL) +#define HPM_DMA_SRC_UART1_RX (0x16UL) +#define HPM_DMA_SRC_UART1_TX (0x17UL) +#define HPM_DMA_SRC_UART2_RX (0x18UL) +#define HPM_DMA_SRC_UART2_TX (0x19UL) +#define HPM_DMA_SRC_UART3_RX (0x1AUL) +#define HPM_DMA_SRC_UART3_TX (0x1BUL) +#define HPM_DMA_SRC_UART4_RX (0x1CUL) +#define HPM_DMA_SRC_UART4_TX (0x1DUL) +#define HPM_DMA_SRC_UART5_RX (0x1EUL) +#define HPM_DMA_SRC_UART5_TX (0x1FUL) +#define HPM_DMA_SRC_UART6_RX (0x20UL) +#define HPM_DMA_SRC_UART6_TX (0x21UL) +#define HPM_DMA_SRC_UART7_RX (0x22UL) +#define HPM_DMA_SRC_UART7_TX (0x23UL) +#define HPM_DMA_SRC_I2C0 (0x24UL) +#define HPM_DMA_SRC_I2C1 (0x25UL) +#define HPM_DMA_SRC_I2C2 (0x26UL) +#define HPM_DMA_SRC_I2C3 (0x27UL) +#define HPM_DMA_SRC_SPI0_RX (0x28UL) +#define HPM_DMA_SRC_SPI0_TX (0x29UL) +#define HPM_DMA_SRC_SPI1_RX (0x2AUL) +#define HPM_DMA_SRC_SPI1_TX (0x2BUL) +#define HPM_DMA_SRC_SPI2_RX (0x2CUL) +#define HPM_DMA_SRC_SPI2_TX (0x2DUL) +#define HPM_DMA_SRC_SPI3_RX (0x2EUL) +#define HPM_DMA_SRC_SPI3_TX (0x2FUL) +#define HPM_DMA_SRC_CAN0 (0x30UL) +#define HPM_DMA_SRC_CAN1 (0x31UL) +#define HPM_DMA_SRC_CAN2 (0x32UL) +#define HPM_DMA_SRC_CAN3 (0x33UL) +#define HPM_DMA_SRC_MOT_0 (0x34UL) +#define HPM_DMA_SRC_MOT_1 (0x35UL) +#define HPM_DMA_SRC_MOT_2 (0x36UL) +#define HPM_DMA_SRC_MOT_3 (0x37UL) +#define HPM_DMA_SRC_MOT_4 (0x38UL) +#define HPM_DMA_SRC_MOT_5 (0x39UL) +#define HPM_DMA_SRC_MOT_6 (0x3AUL) +#define HPM_DMA_SRC_MOT_7 (0x3BUL) +#define HPM_DMA_SRC_XPI0_RX (0x3CUL) +#define HPM_DMA_SRC_XPI0_TX (0x3DUL) +#define HPM_DMA_SRC_DAC0 (0x3EUL) +#define HPM_DMA_SRC_DAC1 (0x3FUL) +#define HPM_DMA_SRC_ACMP0 (0x40UL) +#define HPM_DMA_SRC_ACMP1 (0x41UL) + + + +#endif /* HPM_DMAMUX_SRC_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_gpiom_regs.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_gpiom_regs.h new file mode 100644 index 00000000..d6ae080e --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_gpiom_regs.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_GPIOM_H +#define HPM_GPIOM_H + +typedef struct { + struct { + __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ + } ASSIGN[15]; +} GPIOM_Type; + + +/* Bitfield definition for register of struct array ASSIGN: PIN00 */ +/* + * LOCK (RW) + * + * lock fields in this register, lock can only be cleared by soc reset + * 0: fields can be changed + * 1: fields locked to current value, not changeable + */ +#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) +#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) +#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) +#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) + +/* + * HIDE (RW) + * + * pin value visibility to gpios, + * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 + * bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio + */ +#define GPIOM_ASSIGN_PIN_HIDE_MASK (0xF00U) +#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) +#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) +#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) + +/* + * SELECT (RW) + * + * select which gpio controls chip pin, + * 0: soc gpio0; + * 2: cpu0 fastgpio + */ +#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U) +#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) +#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) +#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) + + + +/* PIN register group index macro definition */ +#define GPIOM_ASSIGN_PIN_PIN00 (0UL) +#define GPIOM_ASSIGN_PIN_PIN01 (1UL) +#define GPIOM_ASSIGN_PIN_PIN02 (2UL) +#define GPIOM_ASSIGN_PIN_PIN03 (3UL) +#define GPIOM_ASSIGN_PIN_PIN04 (4UL) +#define GPIOM_ASSIGN_PIN_PIN05 (5UL) +#define GPIOM_ASSIGN_PIN_PIN06 (6UL) +#define GPIOM_ASSIGN_PIN_PIN07 (7UL) +#define GPIOM_ASSIGN_PIN_PIN08 (8UL) +#define GPIOM_ASSIGN_PIN_PIN09 (9UL) +#define GPIOM_ASSIGN_PIN_PIN10 (10UL) +#define GPIOM_ASSIGN_PIN_PIN11 (11UL) +#define GPIOM_ASSIGN_PIN_PIN12 (12UL) +#define GPIOM_ASSIGN_PIN_PIN13 (13UL) +#define GPIOM_ASSIGN_PIN_PIN14 (14UL) +#define GPIOM_ASSIGN_PIN_PIN15 (15UL) +#define GPIOM_ASSIGN_PIN_PIN16 (16UL) +#define GPIOM_ASSIGN_PIN_PIN17 (17UL) +#define GPIOM_ASSIGN_PIN_PIN18 (18UL) +#define GPIOM_ASSIGN_PIN_PIN19 (19UL) +#define GPIOM_ASSIGN_PIN_PIN20 (20UL) +#define GPIOM_ASSIGN_PIN_PIN21 (21UL) +#define GPIOM_ASSIGN_PIN_PIN22 (22UL) +#define GPIOM_ASSIGN_PIN_PIN23 (23UL) +#define GPIOM_ASSIGN_PIN_PIN24 (24UL) +#define GPIOM_ASSIGN_PIN_PIN25 (25UL) +#define GPIOM_ASSIGN_PIN_PIN26 (26UL) +#define GPIOM_ASSIGN_PIN_PIN27 (27UL) +#define GPIOM_ASSIGN_PIN_PIN28 (28UL) +#define GPIOM_ASSIGN_PIN_PIN29 (29UL) +#define GPIOM_ASSIGN_PIN_PIN30 (30UL) +#define GPIOM_ASSIGN_PIN_PIN31 (31UL) + +/* ASSIGN register group index macro definition */ +#define GPIOM_ASSIGN_GPIOA (0UL) +#define GPIOM_ASSIGN_GPIOB (1UL) +#define GPIOM_ASSIGN_GPIOX (13UL) +#define GPIOM_ASSIGN_GPIOY (14UL) + + +#endif /* HPM_GPIOM_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_gpiom_soc_drv.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_gpiom_soc_drv.h new file mode 100644 index 00000000..01e0f0a5 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_gpiom_soc_drv.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_GPIOM_SOC_DRV_H +#define HPM_GPIOM_SOC_DRV_H + +/** + * @addtogroup gpiom_interface GPIOM driver APIs + * @{ + */ + +/* @brief gpiom control module */ +typedef enum gpiom_gpio { + gpiom_soc_gpio0 = 0, + gpiom_core0_fast = 2, +} gpiom_gpio_t; + +/** + * @} + */ + +#endif /* HPM_GPIOM_SOC_DRV_H */ + diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_interrupt.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_interrupt.h new file mode 100644 index 00000000..7d45e56c --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_interrupt.h @@ -0,0 +1,695 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_INTERRUPT_H +#define HPM_INTERRUPT_H +#include "hpm_common.h" +#include "hpm_csr_drv.h" +#include "hpm_plic_drv.h" + +/** + * @brief INTERRUPT driver APIs + * @defgroup irq_interface INTERRUPT driver APIs + * @{ + */ + +#define M_MODE 0 /*!< Machine mode */ +#define S_MODE 1 /*!< Supervisor mode */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Machine mode API: these APIs are supposed to be called at machine mode */ + +/** + * @brief Enable global IRQ with mask + * + * @param[in] mask interrupt mask to be enabaled + */ +ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Disable global IRQ with mask and return mstatus + * + * @param[in] mask interrupt mask to be disabled + * @retval current mstatus value before irq mask is disabled + */ +ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) +{ + return read_clear_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Restore global IRQ with mask + * + * @param[in] mask interrupt mask to be restored + */ +ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) +{ + set_csr(CSR_MSTATUS, mask); +} + +/** + * @brief Enable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) +{ + set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Disable IRQ from interrupt controller + * + */ +ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); +} + +/** + * @brief Enable machine timer IRQ + */ +ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) +{ + set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/** + * @brief Disable machine timer IRQ + * + */ +ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); +} + +/* + * CPU Machine SWI control + * + * Machine SWI (MSIP) is connected to PLICSW irq 1. + */ +#define PLICSWI 1 + +/** + * @brief Initialize software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) +{ + __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + + +/** + * @brief Enable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) +{ + set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Disable software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) +{ + clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); +} + + +/** + * @brief Trigger software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) +{ + __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); +} + +/** + * @brief Claim software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) +{ + __plic_claim_irq(HPM_PLICSW_BASE, 0); +} + +/** + * @brief Complete software interrupt + * + */ +ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) +{ + __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); +} + +/* + * @brief Enable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_enable_irq(irq) \ + intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Disable IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_disable_irq(irq) \ + intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) + +#define intc_m_set_threshold(threshold) \ + intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) + +/* + * @brief Complete IRQ for machine mode + * + * @param[in] irq Interrupt number + */ +#define intc_m_complete_irq(irq) \ + intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) + +/* + * @brief Claim IRQ for machine mode + * + */ +#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) + +/* + * @brief Enable IRQ for machine mode with priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +#define intc_m_enable_irq_with_priority(irq, priority) \ + do { \ + intc_set_irq_priority(irq, priority); \ + intc_m_enable_irq(irq); \ + } while (0) + +/* + * @brief Enable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) +{ + __plic_enable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt priority + * + * @param[in] irq Interrupt number + * @param[in] priority Priority of interrupt + */ +ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) +{ + __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); +} + +/** + * @brief Disable specific interrupt + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + */ +ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) +{ + __plic_disable_irq(HPM_PLIC_BASE, target, irq); +} + +/** + * @brief Set interrupt threshold + * + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + */ +ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) +{ + __plic_set_threshold(HPM_PLIC_BASE, target, threshold); +} + +/** + * @brief Claim IRQ + * + * @param[in] target Target to handle specific interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) +{ + return __plic_claim_irq(HPM_PLIC_BASE, target); +} + +/** + * @brief Complete IRQ + * + * @param[in] target Target to handle specific interrupt + * @param[in] irq Specific IRQ to be completed + * + */ +ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) +{ + __plic_complete_irq(HPM_PLIC_BASE, target, irq); +} + +/* + * Vectored based irq install and uninstall + */ +/* Machine mode */ +extern int __vector_table[]; + +extern void default_irq_entry(void); + +/** + * @brief Install ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * @param[in] isr Interrupt service routine + * + */ +ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) +{ + __vector_table[irq] = isr; +} + +/** + * @brief Uninstall ISR for certain IRQ for ram based vector table + * + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) +{ + __vector_table[irq] = (int) default_irq_entry; +} + +/* + * Inline nested irq entry/exit macros + */ +/* + * @brief Save CSR + * @param[in] r Target CSR to be saved + */ +#define SAVE_CSR(r) register long __##r = read_csr(r); + +/* + * @brief Restore macro + * + * @param[in] r Target CSR to be restored + */ +#define RESTORE_CSR(r) write_csr(r, __##r); + +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH +#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) +#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) +#else +#define SAVE_MXSTATUS() +#define RESTORE_MXSTATUS() +#endif + +#ifdef __riscv_flen +#define SAVE_FCSR() register int __fcsr = read_fcsr(); +#define RESTORE_FCSR() write_fcsr(__fcsr); +#else +#define SAVE_FCSR() +#define RESTORE_FCSR() +#endif + +#ifdef __riscv_dsp +#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) +#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) +#else +#define SAVE_UCODE() +#define RESTORE_UCODE() +#endif + +#ifdef __riscv_flen +#if __riscv_flen == 32 +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 FPU caller registers +FCSR + UCODE (DSP) */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) +#else /* __riscv_flen = 64 */ +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 DFPU caller + FCSR registers + UCODE (DSP) */ +#define CONTEXT_REG_NUM (4 * (16 + 4 + 20 * 2)) +#endif + +#else +/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/ +#define CONTEXT_REG_NUM (4 * (16 + 4)) +#endif + +#ifdef __riscv_flen +/* + * Save FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#if __riscv_flen == 32 +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fswsp ft0, 20*4(sp)\n\ + c.fswsp ft1, 21*4(sp) \n\ + c.fswsp ft2, 22*4(sp) \n\ + c.fswsp ft3, 23*4(sp) \n\ + c.fswsp ft4, 24*4(sp) \n\ + c.fswsp ft5, 25*4(sp) \n\ + c.fswsp ft6, 26*4(sp) \n\ + c.fswsp ft7, 27*4(sp) \n\ + c.fswsp fa0, 28*4(sp) \n\ + c.fswsp fa1, 29*4(sp) \n\ + c.fswsp fa2, 30*4(sp) \n\ + c.fswsp fa3, 31*4(sp) \n\ + c.fswsp fa4, 32*4(sp) \n\ + c.fswsp fa5, 33*4(sp) \n\ + c.fswsp fa6, 34*4(sp) \n\ + c.fswsp fa7, 35*4(sp) \n\ + c.fswsp ft8, 36*4(sp) \n\ + c.fswsp ft9, 37*4(sp) \n\ + c.fswsp ft10, 38*4(sp) \n\ + c.fswsp ft11, 39*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.flwsp ft0, 20*4(sp)\n\ + c.flwsp ft1, 21*4(sp) \n\ + c.flwsp ft2, 22*4(sp) \n\ + c.flwsp ft3, 23*4(sp) \n\ + c.flwsp ft4, 24*4(sp) \n\ + c.flwsp ft5, 25*4(sp) \n\ + c.flwsp ft6, 26*4(sp) \n\ + c.flwsp ft7, 27*4(sp) \n\ + c.flwsp fa0, 28*4(sp) \n\ + c.flwsp fa1, 29*4(sp) \n\ + c.flwsp fa2, 30*4(sp) \n\ + c.flwsp fa3, 31*4(sp) \n\ + c.flwsp fa4, 32*4(sp) \n\ + c.flwsp fa5, 33*4(sp) \n\ + c.flwsp fa6, 34*4(sp) \n\ + c.flwsp fa7, 35*4(sp) \n\ + c.flwsp ft8, 36*4(sp) \n\ + c.flwsp ft9, 37*4(sp) \n\ + c.flwsp ft10, 38*4(sp) \n\ + c.flwsp ft11, 39*4(sp) \n");\ +} +#else /*__riscv_flen == 64*/ +#define SAVE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fsdsp ft0, 20*4(sp)\n\ + c.fsdsp ft1, 22*4(sp) \n\ + c.fsdsp ft2, 24*4(sp) \n\ + c.fsdsp ft3, 26*4(sp) \n\ + c.fsdsp ft4, 28*4(sp) \n\ + c.fsdsp ft5, 30*4(sp) \n\ + c.fsdsp ft6, 32*4(sp) \n\ + c.fsdsp ft7, 34*4(sp) \n\ + c.fsdsp fa0, 36*4(sp) \n\ + c.fsdsp fa1, 38*4(sp) \n\ + c.fsdsp fa2, 40*4(sp) \n\ + c.fsdsp fa3, 42*4(sp) \n\ + c.fsdsp fa4, 44*4(sp) \n\ + c.fsdsp fa5, 46*4(sp) \n\ + c.fsdsp fa6, 48*4(sp) \n\ + c.fsdsp fa7, 50*4(sp) \n\ + c.fsdsp ft8, 52*4(sp) \n\ + c.fsdsp ft9, 54*4(sp) \n\ + c.fsdsp ft10, 56*4(sp) \n\ + c.fsdsp ft11, 58*4(sp) \n");\ +} + +/* + * Restore FPU caller registers: + * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack + */ +#define RESTORE_FPU_CONTEXT() { \ + __asm volatile("\n\ + c.fldsp ft0, 20*4(sp)\n\ + c.fldsp ft1, 22*4(sp) \n\ + c.fldsp ft2, 24*4(sp) \n\ + c.fldsp ft3, 26*4(sp) \n\ + c.fldsp ft4, 28*4(sp) \n\ + c.fldsp ft5, 30*4(sp) \n\ + c.fldsp ft6, 32*4(sp) \n\ + c.fldsp ft7, 34*4(sp) \n\ + c.fldsp fa0, 36*4(sp) \n\ + c.fldsp fa1, 38*4(sp) \n\ + c.fldsp fa2, 40*4(sp) \n\ + c.fldsp fa3, 42*4(sp) \n\ + c.fldsp fa4, 44*4(sp) \n\ + c.fldsp fa5, 46*4(sp) \n\ + c.fldsp fa6, 48*4(sp) \n\ + c.fldsp fa7, 50*4(sp) \n\ + c.fldsp ft8, 52*4(sp) \n\ + c.fldsp ft9, 54*4(sp) \n\ + c.fldsp ft10, 56*4(sp) \n\ + c.fldsp ft11, 58*4(sp) \n");\ +} +#endif +#else +#define SAVE_FPU_CONTEXT() +#define RESTORE_FPU_CONTEXT() +#endif + +/** + * @brief Save the caller registers based on the RISC-V ABI specification + */ +#define SAVE_CALLER_CONTEXT() { \ + __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ + __asm volatile("\n\ + c.swsp ra, 0*4(sp) \n\ + c.swsp t0, 1*4(sp) \n\ + c.swsp t1, 2*4(sp) \n\ + c.swsp t2, 3*4(sp) \n\ + c.swsp s0, 4*4(sp) \n\ + c.swsp s1, 5*4(sp) \n\ + c.swsp a0, 6*4(sp) \n\ + c.swsp a1, 7*4(sp) \n\ + c.swsp a2, 8*4(sp) \n\ + c.swsp a3, 9*4(sp) \n\ + c.swsp a4, 10*4(sp) \n\ + c.swsp a5, 11*4(sp) \n\ + c.swsp a6, 12*4(sp) \n\ + c.swsp a7, 13*4(sp) \n\ + c.swsp s2, 14*4(sp) \n\ + c.swsp s3, 15*4(sp) \n\ + c.swsp t3, 16*4(sp) \n\ + c.swsp t4, 17*4(sp) \n\ + c.swsp t5, 18*4(sp) \n\ + c.swsp t6, 19*4(sp)"); \ + SAVE_FPU_CONTEXT(); \ +} + +/** + * @brief Restore the caller registers based on the RISC-V ABI specification + */ +#define RESTORE_CALLER_CONTEXT() { \ + __asm volatile("\n\ + c.lwsp ra, 0*4(sp) \n\ + c.lwsp t0, 1*4(sp) \n\ + c.lwsp t1, 2*4(sp) \n\ + c.lwsp t2, 3*4(sp) \n\ + c.lwsp s0, 4*4(sp) \n\ + c.lwsp s1, 5*4(sp) \n\ + c.lwsp a0, 6*4(sp) \n\ + c.lwsp a1, 7*4(sp) \n\ + c.lwsp a2, 8*4(sp) \n\ + c.lwsp a3, 9*4(sp) \n\ + c.lwsp a4, 10*4(sp) \n\ + c.lwsp a5, 11*4(sp) \n\ + c.lwsp a6, 12*4(sp) \n\ + c.lwsp a7, 13*4(sp) \n\ + c.lwsp s2, 14*4(sp) \n\ + c.lwsp s3, 15*4(sp) \n\ + c.lwsp t3, 16*4(sp) \n\ + c.lwsp t4, 17*4(sp) \n\ + c.lwsp t5, 18*4(sp) \n\ + c.lwsp t6, 19*4(sp) \n");\ + RESTORE_FPU_CONTEXT(); \ + __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ +} + +#ifdef __riscv_flen +#define SAVE_FPU_STATE() { \ + __asm volatile("frsr s1\n"); \ +} + +#define RESTORE_FPU_STATE() { \ + __asm volatile("fssr s1\n"); \ +} +#else +#define SAVE_FPU_STATE() +#define RESTORE_FPU_STATE() +#endif + +#ifdef __riscv_dsp +/* + * Save DSP context + * NOTE: DSP context registers are stored at word offset 41 in the stack + */ +#define SAVE_DSP_CONTEXT() { \ + __asm volatile("rdov s0\n"); \ +} +/* + * @brief Restore DSP context + * @note DSP context registers are stored at word offset 41 in the stack + */ +#define RESTORE_DSP_CONTEXT() {\ + __asm volatile("csrw ucode, s0\n"); \ +} + +#else +#define SAVE_DSP_CONTEXT() +#define RESTORE_DSP_CONTEXT() +#endif + +/* + * @brief Enter Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define ENTER_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrr s2, mepc \n\ + csrr s3, mstatus \n");\ + SAVE_FPU_STATE(); \ + SAVE_DSP_CONTEXT(); \ + __asm volatile("csrsi mstatus, 8"); \ +} + +/* + * @brief Complete IRQ Handling + */ +#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ + __asm volatile("csrci mstatus, 8"); \ + __asm volatile("lui a4, 0xe4200"); \ + __asm volatile("li a3, %0" : : "i" (irq_num) :); \ + __asm volatile("sw a3, 4(a4)"); \ +} + +/* + * @brief Exit Nested IRQ Handling + * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: + * MCAUSE - word offset 16 (not used in the vectored mode) + * EPC - word offset 17 + * MSTATUS = word offset 18 + * MXSTATUS = word offset 19 + */ +#define EXIT_NESTED_IRQ_HANDLING_M() { \ + __asm volatile("\n\ + csrw mstatus, s3 \n\ + csrw mepc, s2 \n");\ + RESTORE_FPU_STATE(); \ + RESTORE_DSP_CONTEXT(); \ +} + +/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ +#define NESTED_IRQ_ENTER() \ + SAVE_CSR(CSR_MEPC) \ + SAVE_CSR(CSR_MSTATUS) \ + SAVE_MXSTATUS() \ + SAVE_FCSR() \ + SAVE_UCODE() \ + set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +/* @brief Nested IRQ exit macro : Restore CSRs */ +#define NESTED_IRQ_EXIT() \ + RESTORE_CSR(CSR_MSTATUS) \ + RESTORE_CSR(CSR_MEPC) \ + RESTORE_MXSTATUS() \ + RESTORE_FCSR() \ + RESTORE_UCODE() + +#ifdef __cplusplus +#define EXTERN_C extern "C" +#else +#define EXTERN_C +#endif + +#define ISR_NAME_M(irq_num) default_isr_##irq_num +/** + * @brief Declare an external interrupt handler for machine mode + * + * @param[in] irq_num - IRQ number index + * @param[in] isr - Application IRQ handler function pointer + */ +#ifndef USE_NONVECTOR_MODE + +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) \ +{ \ + SAVE_CALLER_CONTEXT(); \ + ENTER_NESTED_IRQ_HANDLING_M();\ + __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ + __asm volatile("jalr t1\n");\ + COMPLETE_IRQ_HANDLING_M(irq_num);\ + EXIT_NESTED_IRQ_HANDLING_M();\ + RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ + __asm volatile("mret\n");\ +} +#else + +#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ +void ISR_NAME_M(irq_num)(void) { \ + isr(); \ +} +#endif + + +/** + * @brief Declare machine timer interrupt handler + * + * @param[in] isr - MCHTMR IRQ handler function pointer + */ +#define SDK_DECLARE_MCHTMR_ISR(isr) \ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ +void mchtmr_isr(void) {\ + isr();\ +} + +/** + * @brief Declare machine software interrupt handler + * + * @param[in] isr - SWI IRQ handler function pointer + */ +#define SDK_DECLARE_SWI_ISR(isr)\ +void isr(void) __attribute__((section(".isr_vector")));\ +EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ +void swi_isr(void) {\ + isr();\ +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ +#endif /* HPM_INTERRUPT_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_ioc_regs.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_ioc_regs.h new file mode 100644 index 00000000..d01c77dc --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_ioc_regs.h @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOC_H +#define HPM_IOC_H + +typedef struct { + struct { + __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ + __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ + } PAD[456]; +} IOC_Type; + + +/* Bitfield definition for register of struct array PAD: FUNC_CTL */ +/* + * LOOP_BACK (RW) + * + * force input on + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) +#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) + +/* + * ANALOG (RW) + * + * select analog pin in pad + * 0: disable + * 1: enable + */ +#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) +#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) +#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) +#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) + +/* + * ALT_SELECT (RW) + * + * alt select + * 0: ALT0 + * 1: ALT1 + * ... + * 31:ALT31 + */ +#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) +#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) + +/* Bitfield definition for register of struct array PAD: PAD_CTL */ +/* + * HYS (RW) + * + * schmitt trigger enable + * 0: disable + * 1: enable + */ +#define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) +#define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) +#define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) +#define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) + +/* + * PRS (RW) + * + * select pull up/down internal resistance strength: + * For pull down, only have 100 Kohm resistance + * For pull up: + * 00: 100 KOhm + * 01: 47 KOhm + * 10: 22 KOhm + * 11: 22 KOhm + */ +#define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) +#define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) +#define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) +#define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) + +/* + * PS (RW) + * + * pull select + * 0: pull down + * 1: pull up + */ +#define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) +#define IOC_PAD_PAD_CTL_PS_SHIFT (18U) +#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) +#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) + +/* + * PE (RW) + * + * pull enable + * 0: pull disable + * 1: pull enable + */ +#define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) +#define IOC_PAD_PAD_CTL_PE_SHIFT (17U) +#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) +#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) + +/* + * KE (RW) + * + * keeper capability enable + * 0: keeper disable + * 1: keeper enable + */ +#define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) +#define IOC_PAD_PAD_CTL_KE_SHIFT (16U) +#define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) +#define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) + +/* + * OD (RW) + * + * open drain + * 0: open drain disable + * 1: open drain enable + */ +#define IOC_PAD_PAD_CTL_OD_MASK (0x100U) +#define IOC_PAD_PAD_CTL_OD_SHIFT (8U) +#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) +#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) + +/* + * SR (RW) + * + * slew rate + * 0: Slow slew rate + * 1: Fast slew rate + */ +#define IOC_PAD_PAD_CTL_SR_MASK (0x40U) +#define IOC_PAD_PAD_CTL_SR_SHIFT (6U) +#define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) +#define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) + +/* + * SPD (RW) + * + * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise + * 00: Slow frequency slew rate(50Mhz) + * 01: Medium frequency slew rate(100 Mhz) + * 10: Fast frequency slew rate(150 Mhz) + * 11: Max frequency slew rate(200Mhz) + */ +#define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) +#define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) +#define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) +#define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) + +/* + * DS (RW) + * + * drive strength + * 1.8V Mode: + * 000: 260 Ohm + * 001: 260 Ohm + * 010: 130 Ohm + * 011: 88 Ohm + * 100: 65 Ohm + * 101: 52 Ohm + * 110: 43 Ohm + * 111: 37 Ohm + * 3.3V Mode: + * 000: 157 Ohm + * 001: 157 Ohm + * 010: 78 Ohm + * 011: 53 Ohm + * 100: 39 Ohm + * 101: 32 Ohm + * 110: 26 Ohm + * 111: 23 Ohm + */ +#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) +#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) +#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) +#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) + + + +/* PAD register group index macro definition */ +#define IOC_PAD_PA00 (0UL) +#define IOC_PAD_PA01 (1UL) +#define IOC_PAD_PA02 (2UL) +#define IOC_PAD_PA03 (3UL) +#define IOC_PAD_PA04 (4UL) +#define IOC_PAD_PA05 (5UL) +#define IOC_PAD_PA06 (6UL) +#define IOC_PAD_PA07 (7UL) +#define IOC_PAD_PA08 (8UL) +#define IOC_PAD_PA09 (9UL) +#define IOC_PAD_PA10 (10UL) +#define IOC_PAD_PA11 (11UL) +#define IOC_PAD_PA12 (12UL) +#define IOC_PAD_PA13 (13UL) +#define IOC_PAD_PA14 (14UL) +#define IOC_PAD_PA15 (15UL) +#define IOC_PAD_PA16 (16UL) +#define IOC_PAD_PA17 (17UL) +#define IOC_PAD_PA18 (18UL) +#define IOC_PAD_PA19 (19UL) +#define IOC_PAD_PA20 (20UL) +#define IOC_PAD_PA21 (21UL) +#define IOC_PAD_PA22 (22UL) +#define IOC_PAD_PA23 (23UL) +#define IOC_PAD_PA24 (24UL) +#define IOC_PAD_PA25 (25UL) +#define IOC_PAD_PA26 (26UL) +#define IOC_PAD_PA27 (27UL) +#define IOC_PAD_PA28 (28UL) +#define IOC_PAD_PA29 (29UL) +#define IOC_PAD_PA30 (30UL) +#define IOC_PAD_PA31 (31UL) +#define IOC_PAD_PB00 (32UL) +#define IOC_PAD_PB01 (33UL) +#define IOC_PAD_PB02 (34UL) +#define IOC_PAD_PB03 (35UL) +#define IOC_PAD_PB04 (36UL) +#define IOC_PAD_PB05 (37UL) +#define IOC_PAD_PB06 (38UL) +#define IOC_PAD_PB07 (39UL) +#define IOC_PAD_PB08 (40UL) +#define IOC_PAD_PB09 (41UL) +#define IOC_PAD_PB10 (42UL) +#define IOC_PAD_PB11 (43UL) +#define IOC_PAD_PB12 (44UL) +#define IOC_PAD_PB13 (45UL) +#define IOC_PAD_PB14 (46UL) +#define IOC_PAD_PB15 (47UL) +#define IOC_PAD_PX00 (416UL) +#define IOC_PAD_PX01 (416UL) +#define IOC_PAD_PX02 (417UL) +#define IOC_PAD_PX03 (417UL) +#define IOC_PAD_PX04 (418UL) +#define IOC_PAD_PX05 (418UL) +#define IOC_PAD_PX06 (419UL) +#define IOC_PAD_PX07 (419UL) +#define IOC_PAD_PY00 (448UL) +#define IOC_PAD_PY01 (449UL) +#define IOC_PAD_PY02 (450UL) +#define IOC_PAD_PY03 (451UL) +#define IOC_PAD_PY04 (452UL) +#define IOC_PAD_PY05 (453UL) +#define IOC_PAD_PY06 (454UL) +#define IOC_PAD_PY07 (455UL) + + +#endif /* HPM_IOC_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_iomux.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_iomux.h new file mode 100644 index 00000000..b85aea4d --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_iomux.h @@ -0,0 +1,827 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_IOMUX_H +#define HPM_IOMUX_H + +/* IOC_PA00_FUNC_CTL function mux definitions */ +#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA00_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA00_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA00_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA00_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA00_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA00_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA00_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA01_FUNC_CTL function mux definitions */ +#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA01_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA01_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA01_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA01_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA01_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA01_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA01_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA02_FUNC_CTL function mux definitions */ +#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA02_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA02_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA02_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA02_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA02_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA02_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA02_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA02_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA03_FUNC_CTL function mux definitions */ +#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA03_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA03_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA03_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA03_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA03_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA03_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA03_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA03_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA04_FUNC_CTL function mux definitions */ +#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA04_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA04_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA04_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA04_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA04_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA04_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA04_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA04_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA04_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA04_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA05_FUNC_CTL function mux definitions */ +#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA05_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA05_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA05_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA05_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA05_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA05_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA05_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA05_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA05_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA05_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA05_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA06_FUNC_CTL function mux definitions */ +#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA06_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA06_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA06_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA06_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA06_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA06_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA06_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA06_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA06_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA07_FUNC_CTL function mux definitions */ +#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA07_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA07_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA07_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA07_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA07_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA07_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA07_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA07_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA08_FUNC_CTL function mux definitions */ +#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA08_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA08_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA08_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA08_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA08_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA09_FUNC_CTL function mux definitions */ +#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA09_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA09_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA09_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA09_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA09_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA10_FUNC_CTL function mux definitions */ +#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA10_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA10_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA10_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA10_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA10_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA10_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA10_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA10_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA10_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA11_FUNC_CTL function mux definitions */ +#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA11_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA11_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA11_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA11_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA11_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA11_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA11_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA11_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA11_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA12_FUNC_CTL function mux definitions */ +#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA12_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA12_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA12_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA12_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA12_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA12_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA12_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA12_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA12_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA13_FUNC_CTL function mux definitions */ +#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA13_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA13_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA13_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA13_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA13_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA13_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA13_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA13_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA13_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA14_FUNC_CTL function mux definitions */ +#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA14_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA14_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA14_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA14_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA14_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA14_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA15_FUNC_CTL function mux definitions */ +#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA15_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA15_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA15_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA15_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA15_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA15_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA15_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA16_FUNC_CTL function mux definitions */ +#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA16_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA16_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA16_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA16_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA16_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA16_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA16_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA17_FUNC_CTL function mux definitions */ +#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA17_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA17_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA17_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA17_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA17_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA17_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA17_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA18_FUNC_CTL function mux definitions */ +#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA18_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA18_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA18_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA18_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA18_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA18_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA18_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA18_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA19_FUNC_CTL function mux definitions */ +#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA19_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA19_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA19_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA19_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA19_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA19_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA19_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA20_FUNC_CTL function mux definitions */ +#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA20_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA20_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA20_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA20_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA20_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA20_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA20_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA20_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA21_FUNC_CTL function mux definitions */ +#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA21_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA21_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA21_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA21_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA21_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA21_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA21_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA21_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA21_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA22_FUNC_CTL function mux definitions */ +#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA22_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA22_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA22_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA22_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA22_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA22_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA22_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA22_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA22_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA23_FUNC_CTL function mux definitions */ +#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA23_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA23_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA23_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA23_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA23_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA23_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA23_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PA24_FUNC_CTL function mux definitions */ +#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA24_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA24_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA24_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA24_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA24_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA24_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA24_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA25_FUNC_CTL function mux definitions */ +#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA25_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA25_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA25_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA25_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA25_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA25_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA25_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) + +/* IOC_PA26_FUNC_CTL function mux definitions */ +#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA26_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA26_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA26_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA26_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA26_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA26_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA26_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA26_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA26_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA26_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA27_FUNC_CTL function mux definitions */ +#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA27_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA27_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA27_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA27_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA27_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA27_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA27_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA27_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA27_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA28_FUNC_CTL function mux definitions */ +#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA28_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA28_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA28_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA28_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA28_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA28_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA28_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA28_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PA28_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA28_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PA29_FUNC_CTL function mux definitions */ +#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PA29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PA29_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA29_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA29_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA29_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA29_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA29_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA29_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA29_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PA29_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA29_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PA29_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PA29_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PA30_FUNC_CTL function mux definitions */ +#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA30_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA30_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA30_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA30_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA30_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA30_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA30_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA30_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA30_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PA30_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PA31_FUNC_CTL function mux definitions */ +#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PA31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PA31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PA31_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PA31_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PA31_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PA31_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) +#define IOC_PA31_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PA31_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PA31_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PA31_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PA31_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PB00_FUNC_CTL function mux definitions */ +#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB00_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB00_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB00_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB00_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB00_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PB01_FUNC_CTL function mux definitions */ +#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB01_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB01_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB01_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB01_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB01_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PB02_FUNC_CTL function mux definitions */ +#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB02_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB02_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB02_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB02_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB02_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PB03_FUNC_CTL function mux definitions */ +#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB03_FUNC_CTL_SPI2_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB03_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB03_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB03_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB03_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PB04_FUNC_CTL function mux definitions */ +#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB04_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB04_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB04_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB04_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB04_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB04_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB04_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB05_FUNC_CTL function mux definitions */ +#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB05_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB05_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB05_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB05_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB05_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB05_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB05_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB05_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB06_FUNC_CTL function mux definitions */ +#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB06_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB06_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB06_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB06_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PB06_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB06_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB06_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB07_FUNC_CTL function mux definitions */ +#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB07_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB07_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB07_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB07_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PB07_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB07_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB08_FUNC_CTL function mux definitions */ +#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB08_FUNC_CTL_SPI2_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB08_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB08_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB08_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB08_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB08_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB08_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PB08_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PB09_FUNC_CTL function mux definitions */ +#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB09_FUNC_CTL_SPI2_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB09_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB09_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB09_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB09_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB09_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB09_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PB09_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PB10_FUNC_CTL function mux definitions */ +#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB10_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB10_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB10_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB10_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB10_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB10_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB10_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB10_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) +#define IOC_PB10_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PB11_FUNC_CTL function mux definitions */ +#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB11_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB11_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB11_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB11_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB11_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB11_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB12_FUNC_CTL function mux definitions */ +#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB12_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB12_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB12_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB12_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB12_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB12_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB12_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB12_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB13_FUNC_CTL function mux definitions */ +#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PB13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PB13_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB13_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB13_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB13_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB13_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB13_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB13_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB13_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB13_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB14_FUNC_CTL function mux definitions */ +#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB14_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB14_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB14_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB14_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB14_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB14_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB14_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PB14_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB14_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) +#define IOC_PB14_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PB15_FUNC_CTL function mux definitions */ +#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PB15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PB15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PB15_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PB15_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PB15_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PB15_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PB15_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PB15_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PB15_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PB15_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) +#define IOC_PB15_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) + +/* IOC_PX00_FUNC_CTL function mux definitions */ +#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX00_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX00_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX00_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PX00_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX01_FUNC_CTL function mux definitions */ +#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX01_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX01_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX01_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PX01_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX02_FUNC_CTL function mux definitions */ +#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX02_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX02_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PX02_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX02_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX03_FUNC_CTL function mux definitions */ +#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX03_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX03_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX03_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX04_FUNC_CTL function mux definitions */ +#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX04_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX04_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX04_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX04_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX05_FUNC_CTL function mux definitions */ +#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX05_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PX05_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX05_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PX05_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PX05_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX06_FUNC_CTL function mux definitions */ +#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX06_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX06_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PX06_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PX07_FUNC_CTL function mux definitions */ +#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PX07_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PX07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PX07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PX07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PX07_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PX07_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY00_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY00_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PY00_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY01_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY01_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PY01_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY01_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PY01_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY02_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY02_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY02_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PY02_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY02_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) +#define IOC_PY02_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) +#define IOC_PY02_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY03_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY03_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) +#define IOC_PY03_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY03_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY04_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY04_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) +#define IOC_PY05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY05_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY05_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) +#define IOC_PY05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY05_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY05_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY06_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY06_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) +#define IOC_PY06_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) +#define IOC_PY07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) +#define IOC_PY07_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) +#define IOC_PY07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) +#define IOC_PY07_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) + + +#endif /* HPM_IOMUX_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_l1c_drv.c b/common/libraries/hpm_sdk/soc/HPM5361/hpm_l1c_drv.c new file mode 100644 index 00000000..c55600dc --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_l1c_drv.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_l1c_drv.h" +#include + + +#define ASSERT_ADDR_SIZE(addr, size) do { \ + assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ + assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ + } while (0) + +static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) +{ + register uint32_t i; + register uint32_t next_address; + register uint32_t tmp; + register uint32_t csr; + + csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); + +#define CCTL_VERSION (3U << 18) + + if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { + l1c_cctl_address(address); + next_address = address; + while ((next_address < (address + size)) && (next_address >= address)) { + l1c_cctl_cmd(opcode); + next_address = l1c_cctl_get_address(); + } + } else { + for (i = 0, tmp = 0; tmp < size; i++) { + l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); + tmp += HPM_L1C_CACHELINE_SIZE; + } + } + + write_csr(CSR_MSTATUS, csr); +} + +void l1c_dc_enable(void) +{ + if (!l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); + set_csr(CSR_MCACHE_CTL, +#ifdef L1C_DC_WAROUND_VALUE + HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | +#endif + HPM_MCACHE_CTL_DPREF_EN_MASK + | HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_dc_disable(void) +{ + if (l1c_dc_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); + } +} + +void l1c_ic_enable(void) +{ + if (!l1c_ic_is_enabled()) { + set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK + | HPM_MCACHE_CTL_CCTL_SUEN_MASK + | HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_ic_disable(void) +{ + if (l1c_ic_is_enabled()) { + clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); + } +} + +void l1c_fence_i(void) +{ + __asm("fence.i"); +} + +void l1c_dc_invalidate_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); +} + +void l1c_dc_writeback_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); +} + +void l1c_dc_flush_all(void) +{ + l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); +} + +void l1c_dc_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); +} + +void l1c_dc_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); +} + +void l1c_dc_writeback(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); +} + +void l1c_dc_flush(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); +} + +void l1c_ic_invalidate(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); +} + +void l1c_ic_fill_lock(uint32_t address, uint32_t size) +{ + ASSERT_ADDR_SIZE(address, size); + l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); +} diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_l1c_drv.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_l1c_drv.h new file mode 100644 index 00000000..1f1a2163 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_l1c_drv.h @@ -0,0 +1,485 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_L1_CACHE_H +#define _HPM_L1_CACHE_H +#include "hpm_common.h" +#include "hpm_csr_drv.h" +#include "hpm_soc.h" + +/** + * + * @brief L1CACHE driver APIs + * @defgroup l1cache_interface L1CACHE driver APIs + * @{ + */ + +/* cache size is 32KB */ +#define HPM_L1C_CACHE_SIZE (uint32_t)(32 * SIZE_1KB) +#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) +#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) +/* cache line size is 64B */ +#define HPM_L1C_CACHELINE_SIZE (64) +/* cache way is 128 */ +#define HPM_L1C_CACHELINES_PER_WAY (128) + +/* mcache_ctl register */ +/* + * Controls if the instruction cache is enabled or not. + * + * 0 I-Cache is disabled + * 1 I-Cache is enabled + */ +#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) +#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) +#define HPM_MCACHE_CTL_IC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) + +/* + * Controls if the data cache is enabled or not. + * + * 0 D-Cache is disabled + * 1 D-Cache is enabled + */ +#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) +#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) +#define HPM_MCACHE_CTL_DC_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) + +/* + * Parity/ECC error checking enable control for the instruction cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) +#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_IC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) + +/* + * + * Parity/ECC error checking enable control for the data cache. + * + * 0 Disable parity/ECC + * 1 Reserved + * 2 Generate exceptions only on uncorrectable parity/ECC errors + * 3 Generate exceptions on any type of parity/ECC errors + */ +#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) +#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) +#define HPM_MCACHE_CTL_DC_ECCEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. + * It is set to enable CCTL operations to access the ECC codes. This bit + * can be set for injecting ECC errors to test the ECC handler. + * + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) +#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_IC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) + +/* + * + * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is + * set to enable CCTL operations to access the ECC codes. This bit can be + * set for injecting + * + * ECC errors to test the ECC handler. + * 0 Disable diagnostic accesses of ECC codes + * 1 Enable diagnostic accesses of ECC codes + */ +#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) +#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) +#define HPM_MCACHE_CTL_DC_RWECC(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) + +/* + * Enable bit for Superuser-mode and User-mode software to access + * ucctlbeginaddr and ucctlcommand CSRs. + * + * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode + * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode + */ +#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) +#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) +#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) + +/* + * This bit controls hardware prefetch for instruction fetches to cacheable + * memory regions when I-Cache size is not 0. + * + * 0 Disable hardware prefetch on instruction fetches + * 1 Enable hardware prefetch on instruction fetches + */ +#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) +#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_IPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) + +/* + * This bit controls hardware prefetch for load/store accesses to cacheable + * memory regions when D-Cache size is not 0. + * + * 0 Disable hardware prefetch on load/store memory accesses. + * 1 Enable hardware prefetch on load/store memory accesses. + */ +#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) +#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) +#define HPM_MCACHE_CTL_DPREF_EN(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) + +/* + * I-Cache miss allocation filling policy Value Meaning + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) +#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) + +/* + * D-Cache miss allocation filling policy + * + * 0 Cache line data is returned critical (double) word first + * 1 Cache line data is returned the lowest address (double) word first + */ +#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) +#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) +#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) + +/* + * D-Cache Write-Around threshold + * + * 0 Disables streaming. All cacheable write misses allocate a cache line + * according to PMA settings. + * 1 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 4 cache lines. + * 2 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 64 cache lines. + * 3 Override PMA setting and do not allocate D-Cache entries after + * consecutive stores to 128 cache lines. + */ +#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) +#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) +#define HPM_MCACHE_CTL_DC_WAROUND(x) \ + (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) + +/* CCTL command list */ +#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) +#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) +#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) +#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) + +#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) +#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) + +#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) +#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) + +#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) + +#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) +#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) + +#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) +#define HPM_L1C_CCTL_CMD_FAIL (0UL) + +#ifdef __cplusplus +extern "C" { +#endif +/* get cache control register value */ +__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) +{ + return read_csr(CSR_MCACHE_CTL); +} + +__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; +} + +__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) +{ + return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; +} + +/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ +#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) +#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) +#define HPM_MCCTLBEGINADDR_OFFSET(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) +#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) +#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) +#define HPM_MCCTLBEGINADDR_INDEX(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) +#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) +#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) +#define HPM_MCCTLBEGINADDR_WAY(x) \ + (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) + +/* send IX command */ +__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); +} + +/* send command */ +__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) +{ + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) +{ + return read_csr(CSR_MCCTLBEGINADDR); +} + +/* send IX command */ +__attribute__((always_inline)) static inline + void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); +} + +#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) +#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) +#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) + +#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) +#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) +#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) +#define HPM_MCCTLDATA_I_TAG_VALID(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) + +#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) +#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) +#define HPM_MCCTLDATA_D_TAG_MESI(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) + +#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) +#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) + +#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) +#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) +#define HPM_MCCTLDATA_D_TAG_TAG(x) \ + (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) + +/* + * @brief Cache control command read address + * + * Send IX read tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] ecc_data ECC value + * @return data read + */ +ATTR_ALWAYS_INLINE static inline + uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + *ecc_data = read_csr(CSR_MECC_CODE); + return read_csr(CSR_MCCTLDATA); +} + +/* + * @brief Cache control command write address + * + * Send IX write tag/data cmd + * @param[in] cmd Command code + * @param[in] address Target address + * @param[in] data Data to be written + * @param[in] ecc_data ECC of data + */ +ATTR_ALWAYS_INLINE static inline + void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) +{ + write_csr(CSR_MCCTLBEGINADDR, address); + write_csr(CSR_MCCTLCOMMAND, cmd); + write_csr(CSR_MCCTLDATA, data); + write_csr(CSR_MECC_CODE, ecc_data); +} + +#define HPM_L1C_CFG_SET_SHIFT (0UL) +#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) +#define HPM_L1C_CFG_WAY_SHIFT (3UL) +#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) +#define HPM_L1C_CFG_SIZE_SHIFT (6UL) +#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) +#define HPM_L1C_CFG_LOCK_SHIFT (9UL) +#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) +#define HPM_L1C_CFG_ECC_SHIFT (10UL) +#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) +#define HPM_L1C_CFG_LMB_SHIFT (12UL) +#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) +#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) +#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) +#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) +#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) +#define HPM_L1C_CFG_SETH_SHIFT (24UL) +#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) + +/** + * @brief Align down based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) + +/** + * @brief Align up based on cache line size + */ +#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) + +/** + * @brief Get I-cache configuration + * + * @return I-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) +{ + return read_csr(CSR_MICM_CFG); +} + +/** + * @brief Get D-cache configuration + * + * @return D-cache config register + */ +ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) +{ + return read_csr(CSR_MDCM_CFG); +} + +/* + * @brief D-cache disable + */ +void l1c_dc_disable(void); + +/* + * @brief D-cache enable + */ +void l1c_dc_enable(void); + +/* + * @brief D-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_dc_invalidate(uint32_t address, uint32_t size); + +/* + * @brief D-cache writeback by address + * @param[in] address Start address to be writtenback + * @param[in] size Size of memory to be writtenback + */ +void l1c_dc_writeback(uint32_t address, uint32_t size); + +/* + * @brief D-cache invalidate and writeback by address + * @param[in] address Start address to be invalidated and writtenback + * @param[in] size Size of memory to be invalidted and writtenback + */ +void l1c_dc_flush(uint32_t address, uint32_t size); + +/* + * @brief D-cache fill and lock by address + * @param[in] address Start address to be filled and locked + * @param[in] size Size of memory to be filled and locked + */ +void l1c_dc_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief I-cache disable + */ +void l1c_ic_disable(void); + +/* + * @brief I-cache enable + */ +void l1c_ic_enable(void); + +/* + * @brief I-cache invalidate by address + * @param[in] address Start address to be invalidated + * @param[in] size Size of memory to be invalidated + */ +void l1c_ic_invalidate(uint32_t address, uint32_t size); + +/* + * @brief I-cache fill and lock by address + * @param[in] address Start address to be locked + * @param[in] size Size of memory to be locked + */ +void l1c_ic_fill_lock(uint32_t address, uint32_t size); + +/* + * @brief Invalidate all icache and writeback all dcache + */ +void l1c_fence_i(void); + +/* + * @brief Invalidate all d-cache + */ +void l1c_dc_invalidate_all(void); + +/* + * @brief Writeback all d-cache + */ +void l1c_dc_writeback_all(void); + +/* + * @brief Flush all d-cache + */ +void l1c_dc_flush_all(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _HPM_L1_CACHE_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_mcan_soc.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_mcan_soc.h new file mode 100644 index 00000000..6f2f0fe6 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_mcan_soc.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MCAN_SOC_H +#define HPM_MCAN_SOC_H + +#include +#include "hpm_mcan_regs.h" +#include "hpm_soc.h" + +#define MCAN_SOC_TSU_SRC_TWO_STAGES (1U) + +#define HPM_MCAN_EXT_TBSEL_NUM (4U) +#define HPM_MCAN_TBSEL_BASE (0xF02FF000UL) +#define HPM_MCAN_TBSEL (*(volatile uint32_t *)HPM_MCAN_TBSEL_BASE) +#define HPM_MCAN_TBSEL_BITWDITH (6U) +#define HPM_MCAN_TBSEL_MASK ((1UL << HPM_MCAN_TBSEL_BITWDITH) - 1UL) +#define HPM_MCAN_TBSEL0_SHIFT (8U) + +/** + * @brief MCAN MSG BUF base address (AHB_RAM) + */ +#define MCAN_MSG_BUF_BASE (0xF0400000UL) +#define MCAN_MSG_BUF_SIZE_IN_WORDS (640U) +#define MCAN_IP_SLOT_SIZE (0x4000U) + +/** + * @brief TSU External Timebase Sources + */ +#define MCAN_TSU_EXT_TIMEBASE_SRC_MIN (0U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_0 (MCAN_TSU_EXT_TIMEBASE_SRC_MIN) +#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_1 (1U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_2 (2U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_3 (3U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_3) + +/** + * @brief MCAN TSU timebase option for each External Timebase + */ +#define MCAN_TSU_TBSEL_PTPC0 (0x20) +#define MCAN_TSU_TBSEL_MCAN0 (0x00) +#define MCAN_TSU_TBSEL_MCAN1 (0x01) +#define MCAN_TSU_TBSEL_MCAN2 (0x02) +#define MCAN_TSU_TBSEL_MCAN3 (0x03) + + +#ifdef __cpluspus +extern "C" { +#endif + +/** + * @brief Set External Timebase Source for MCAN TSU + * @param [in] ptr MCAN base + * @param [in] src External Timebase source + */ +static inline void mcan_set_tsu_ext_timebase_src(MCAN_Type *ptr, uint8_t src) +{ + if (src < HPM_MCAN_EXT_TBSEL_NUM) { + ptr->GLB_CTL = (ptr->GLB_CTL & ~MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) | MCAN_GLB_CTL_TSU_TBIN_SEL_SET(src); + } +} + +/** + * @brief Set the Source for specified external timebase + * + * @param [in] ptr MCAN base + * @param [in] ext_tbsel External TBSEL index + * @param [in] tbsel_src Timebase source selection + */ +static inline void mcan_set_tsu_tbsel_option(MCAN_Type *ptr, uint8_t ext_tbsel, uint8_t tbsel_option) +{ + if (ext_tbsel < HPM_MCAN_EXT_TBSEL_NUM) { + uint32_t tbsel_shift = (ext_tbsel * HPM_MCAN_TBSEL_BITWDITH) + HPM_MCAN_TBSEL0_SHIFT; + uint32_t tbsel_mask = HPM_MCAN_TBSEL_MASK << tbsel_shift; + HPM_MCAN_TBSEL = (HPM_MCAN_TBSEL & ~tbsel_mask) | (((uint32_t)tbsel_option << tbsel_shift) & tbsel_mask); + } +} + +/** + * @brief Enable Standby Pin for MCAN + * @param [in] ptr MCAN base + */ +static inline void mcan_enable_standby_pin(MCAN_Type *ptr) +{ + ptr->GLB_CTL |= MCAN_GLB_CTL_M_CAN_STBY_MASK; +} + +/** + * @brief Disable Standby pin for MCAN + * @param [in] ptr MCAN base + */ +static inline void mcan_disable_standby_pin(MCAN_Type *ptr) +{ + ptr->GLB_CTL &= ~MCAN_GLB_CTL_M_CAN_STBY_MASK; +} + +/** + * @brief Get RAM base for MCAN + * @param [in] ptr MCAN base + * @return RAM base for MCAN + */ +static inline uint32_t mcan_get_ram_base(MCAN_Type *ptr) +{ + return MCAN_MSG_BUF_BASE; +} + +/** + * @brief Get the MCAN RAM offset in the dedicated/shared RAM for + * @param [in] ptr MCAN base + * @return RAM offset for MCAN + */ +static inline uint32_t mcan_get_ram_offset(MCAN_Type *ptr) +{ + uint32_t index = ((uint32_t) ptr - HPM_MCAN0_BASE) / MCAN_IP_SLOT_SIZE; + + return (index * MCAN_MSG_BUF_SIZE_IN_WORDS * sizeof(uint32_t)); +} + +/** + * @brief Get MCAN RAM size + * @param [in] ptr MCAN base + * @return RAM size in bytes + */ +static inline uint32_t mcan_get_ram_size(MCAN_Type *ptr) +{ + return (MCAN_MSG_BUF_SIZE_IN_WORDS * sizeof(uint32_t)); +} + +#ifdef __cpluspus +} +#endif + +#endif /* HPM_MCAN_SOC_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_misc.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_misc.h new file mode 100644 index 00000000..55d007b3 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_misc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_MISC_H +#define HPM_MISC_H + +#define ILM_LOCAL_BASE (0x0U) +#define ILM_SIZE_IN_BYTE (0x20000U) +#define DLM_LOCAL_BASE (0x80000U) +#define DLM_SIZE_IN_BYTE (0x20000U) +#define CORE0_ILM_SYSTEM_BASE (0x1040000U) +#define CORE0_DLM_SYSTEM_BASE (0x1060000U) + +#define ADDRESS_IN_ILM(address) \ + ((ILM_LOCAL_BASE) <= (address)) && \ + ((ILM_LOCAL_BASE + ILM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_DLM(address) \ + ((DLM_LOCAL_BASE) <= (address)) && \ + ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address)) +#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ + ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ + ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) + +#define DLM_TO_SYSTEM(address) \ + (CORE0_DLM_SYSTEM_BASE + (address) - (DLM_LOCAL_BASE)) +#define ILM_TO_SYSTEM(address) \ + (CORE0_ILM_SYSTEM_BASE + (address) - (ILM_LOCAL_BASE)) +#define SYSTEM_TO_DLM(address) \ + ((address) - CORE0_DLM_SYSTEM_BASE + (DLM_LOCAL_BASE)) + +#define HPM_CORE0 (0U) + +/* map core local memory(DLM/ILM) to system address */ +static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) +{ + return addr; +} + +/* map system address to core local memory(DLM/ILM) */ +static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) +{ + return addr; +} +#endif /* HPM_MISC_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_otp_drv.c b/common/libraries/hpm_sdk/soc/HPM5361/hpm_otp_drv.c new file mode 100644 index 00000000..a68fc69c --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_otp_drv.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_otp_drv.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) +#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ +#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) +#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ +#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ + + +/*********************************************************************************************************************** + * Codes + **********************************************************************************************************************/ +void otp_init(void) +{ + +} + +void otp_deinit(void) +{ + +} + +uint32_t otp_read_from_shadow(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = HPM_OTP->SHADOW[addr]; + } + + return ret_val; +} + +uint32_t otp_read_from_ip(uint32_t addr) +{ + uint32_t ret_val = 0; + if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { + ret_val = HPM_OTP->FUSE[addr]; + } + return ret_val; +} + +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + do { + uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); + + /* Enable 2.5V LDO for FUSE programming */ + uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); + HPM_PCFG->LDO2P5 = reg_val; + /* Wait until LDO is ready */ + while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { + } + HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; + for (uint32_t i = 0; i < num_of_words; i++) { + HPM_OTP->FUSE[addr++] = *src++; + } + HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; + /* Disable 2.5V LDO after FUSE programming for saving power */ + HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_reload(otp_region_t region) +{ + hpm_stat_t status = status_invalid_argument; + if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { + HPM_OTP->LOAD_REQ = (uint32_t)region; + HPM_OTP->LOAD_COMP = (uint32_t)region; + while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { + + } + status = status_success; + } + + return status; +} + +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = HPM_OTP; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) +{ + hpm_stat_t status = status_invalid_argument; + + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); + + OTP_Type *otp_base = HPM_OTP; + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + + uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; + + otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) +{ + hpm_stat_t status = status_invalid_argument; + + do { + uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); + HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); + + HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) + | OTP_REGION_STOP_SET(start + num_of_words); + + status = status_success; + } while (false); + + return status; +} + +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) +{ + hpm_stat_t status = status_invalid_argument; + do { + HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); + + uint32_t lock_reg_idx = (addr << 1) / 32; + uint32_t lock_reg_offset = (addr << 1) % 32; + uint32_t lock_mask = 3U << lock_reg_offset; + + OTP_Type *otp_base = HPM_OTP; + otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) + >> lock_reg_offset); + + if (lock_opt != otp_no_lock) { + status = otp_write_disallowed; + break; + } + + otp_base->SHADOW[addr] = val; + + status = status_success; + } while (false); + + return status; +} diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_otp_drv.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_otp_drv.h new file mode 100644 index 00000000..8c9559a9 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_otp_drv.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef HPM_OTP_DRV_H +#define HPM_OTP_DRV_H + +/** + * @brief OTP APIs + * @defgroup otp_interface OTP driver APIs + * @{ + */ + +#include "hpm_common.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/** + * @brief OTP region definitions + */ +typedef enum { + otp_region0_mask = 1U, /*!< Address range: [0, 7] */ + otp_region1_mask = 2U, /*!< Address range: [8, 15] */ + otp_region2_mask = 4U, /*!< Address range: [16, 127] */ + otp_region3_mask = 8U, /*!< Address range: user defined */ +} otp_region_t; + +/** + * @brief OTP lock options + */ +typedef enum { + otp_no_lock = 0, + otp_read_only = 1, + otp_permanent_no_lock = 2, + otp_disable_access = 3, + otp_lock_option_max = otp_disable_access, +} otp_lock_option_t; + +enum { + otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), +}; + +/*********************************************************************************************************************** + * Prototypes + **********************************************************************************************************************/ +#ifdef __cpluscplus +extern "C" { +#endif + +/** + * @brief Initialize OTP controller + */ +void otp_init(void); + +/** + * @brief De-initialize OTP controller + */ +void otp_deinit(void); + +/** + * @brief Read the OTP word from shadow register + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_shadow(uint32_t addr); + +/** + * @brief Read the specified OTP word from OTP IP bus + * @param [in] addr OTP word index + * @retval OTP word value + */ +uint32_t otp_read_from_ip(uint32_t addr); + +/** + * @brief Program a word to specified OTP field + * @param [in] addr OTP word index + * @param [in] src Pointer to the data to be programmed + * @param [in] num_of_words Number of words to be programmed, only 1 is allowed + * @return API execution status + */ +hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + +/** + * @brief Reload a OTP region + * @param [in] region OTP region option + * @return API execution status + */ +hpm_stat_t otp_reload(otp_region_t region); + +/** + * @brief Change the Software lock permission + * @param [in] addr OTP word index + * @param [in] lock_option OTP lcok option + * @return API execution status + */ +hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief OTP lock shadow + * @param [in] addr OTP word index + * @param [in] lock_option OTP lock option + * @return API execution status + */ +hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); + +/** + * @brief Set the configurable region range + * @param [in] start OTP word start index + * @param [in] num_of_words Number of words in configuration region + * @retval status_out_of_range Invalid range + * @retval status_success Operation is successful + */ +hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); + +/** + * @return Write data to OTP shadow register + * @param [in] addr OTP word index + * @param [val] val Data to be written + * @return API execution status + */ +hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); + + +#ifdef __cpluscplus +} +#endif +/** + * @} + */ + + + + +#endif diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_pcfg_drv.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_pcfg_drv.h new file mode 100644 index 00000000..4c81632d --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_pcfg_drv.h @@ -0,0 +1,518 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PCFG_DRV_H +#define HPM_PCFG_DRV_H + +#include "hpm_common.h" +#include "hpm_pcfg_regs.h" + +/** + * + * @brief PCFG driver APIs + * @defgroup pcfg_interface PCFG driver APIs + * @ingroup io_interfaces + * @{ + */ +#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) +#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) + +#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) +#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) + +/* @brief PCFG irc24m reference */ +typedef enum { + pcfg_irc24m_reference_32k = 0, + pcfg_irc24m_reference_24m_xtal = 1 +} pcfg_irc24m_reference_t; + +/* @brief PCFG dcdc current limit */ +typedef enum { + pcfg_dcdc_lp_current_limit_250ma = 0, + pcfg_dcdc_lp_current_limit_200ma = 1, +} pcfg_dcdc_lp_current_limit_t; + +/* @brief PCFG dcdc current hys */ +typedef enum { + pcfg_dcdc_current_hys_12_5mv = 0, + pcfg_dcdc_current_hys_25mv = 1, +} pcfg_dcdc_current_hys_t; + +/* @brief PCFG dcdc mode */ +typedef enum { + pcfg_dcdc_mode_off = 0, + pcfg_dcdc_mode_basic = 1, + pcfg_dcdc_mode_general = 3, + pcfg_dcdc_mode_expert = 7, +} pcfg_dcdc_mode_t; + +/* @brief PCFG pmc domain peripherals */ +typedef enum { + pcfg_pmc_periph_gpio = 6, + pcfg_pmc_periph_ioc = 8, + pcfg_pmc_periph_timer = 10, + pcfg_pmc_periph_wdog = 12, + pcfg_pmc_periph_uart = 14, +} pcfg_pmc_periph_t; + +/* @brief PCFG status */ +enum { + status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), +}; + +/* @brief PCFG irc24m config */ +typedef struct { + uint32_t freq_in_hz; + pcfg_irc24m_reference_t reference; + bool return_to_default_on_xtal_loss; + bool free_run; +} pcfg_irc24m_config_t; + + +#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ + ((uint32_t) (mode) << ((module) << 1)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief check if bandgap is trimmed or not + * + * @param[in] ptr base address + * + * @retval true if bandgap is trimmed + */ +static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) +{ + return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief bandgap reload trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) +{ + ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; +} + +/** + * @brief turn off LDO 1V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo1p1_turn_off(PCFG_Type *ptr) +{ + ptr->LDO1P1 &= ~PCFG_LDO1P1_ENABLE_MASK; +} + +/** + * @brief turn of LDO 1V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo1p1_turn_on(PCFG_Type *ptr) +{ + ptr->LDO1P1 |= PCFG_LDO1P1_ENABLE_MASK; +} + +/** + * @brief turn off LDO2P5 + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) +{ + ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief turn on LDO 2.5V + * + * @param[in] ptr base address + */ +static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) +{ + ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; +} + +/** + * @brief check if LDO 2.5V is stable + * + * @param[in] ptr base address + * + * @retval true if LDO2P5 is stable + */ +static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) +{ + return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); +} + +/* + * @brief check if DCDC is stable or not + * @param[in] ptr base address + * @retval true if DCDC is stable + */ +static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) +{ + return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); +} + +/* + * @brief set DCDC work mode + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) +{ + ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); +} + +/** + * @brief set low power current limit + * + * @param[in] ptr base address + * @param[in] limit current limit at low power mode + * @param[in] over_limit set to true means current is greater than limit + */ +static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit) +{ + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) + | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); +} + + +/** + * @brief check if power loss flag is set + * + * @param[in] ptr base address + * + * @retval true if power loss is set + */ +static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); +} + +/** + * @brief disable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief enable over voltage protection + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) +{ + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; +} + +/** + * @brief checkover voltage flag + * + * @param[in] ptr base address + * @retval true if flag is set + */ +static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) +{ + return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; +} + +/** + * @brief disable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief enable current measurement + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) +{ + ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; +} + +/** + * @brief check if measured current is valid + * + * @param[in] ptr base address + * + * @retval true if measured current is valid + */ +static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) +{ + return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; +} + +/** + * @brief get DCDC start time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc start time in cycles + */ +static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); +} + +/** + * @brief get DCDC resume time in number of 24MHz clock cycles + * + * @param[in] ptr base address + * + * @retval dcdc resuem time in cycles + */ +static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) +{ + return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); +} + +/** + * @brief set DCDC start time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles start time in cycles + */ +static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); +} + +/** + * @brief set DCDC resuem time in 24MHz clock cycles + * + * @param[in] ptr base address + * @param[in] cycles resume time in cycles + */ +static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) +{ + ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); +} + +/** + * @brief set dcdc current hysteres range + * + * @param[in] ptr base address + * @param[in] range current hysteres range + */ +static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) +{ + ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); +} + +/** + * @brief disable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief enable power trap + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_power_trap(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; +} + +/** + * @brief check if power trap is triggered + * + * @param[in] ptr base address + * + * @retval true if power trap is triggered + */ +static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) +{ + return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief clear power trap trigger flag + * + * @param[in] ptr base address + */ +static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; +} + +/** + * @brief disable dcdc retention + * + * @param[in] ptr base address + */ +static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief enable dcdc retention to retain soc sram data + * + * @param[in] ptr base address + */ +static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) +{ + ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; +} + +/** + * @brief clear wakeup cause flag + * + * @param[in] ptr base address + * @param[in] mask mask of flags to be cleared + */ +static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_CAUSE |= mask; +} + +/** + * @brief get wakeup cause + * + * @param[in] ptr base address + * + * @retval mask of wake cause + */ +static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) +{ + return ptr->WAKE_CAUSE; +} + +/** + * @brief enable wakeup source + * + * @param[in] ptr base address + * @param[in] mask wakeup source mask + */ +static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK &= ~mask; +} + +/** + * @brief disable wakeup source + * + * @param[in] ptr base address + * @param[in] mask source to be disabled as wakeup source + */ +static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) +{ + ptr->WAKE_MASK |= mask; +} + +/** + * @brief set clock gate mode in vpmc domain + * + * @param[in] ptr base address + * @param[in] mode clock gate mode mask + */ +static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) +{ + ptr->SCG_CTRL = mode; +} + +/** + * @brief check if irc24m is trimmed + * + * @param[in] ptr base address + * + * @retval true if it is trimmed + */ +static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) +{ + return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief reload irc24m trim value + * + * @param[in] ptr base address + */ +static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) +{ + ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; +} + +/** + * @brief config irc24m track + * + * @param[in] ptr base address + * @param[in] config config data + */ +void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); + +/* + * @brief set DCDC voltage at standby mode + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 2.5V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set DCDC voltage + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief set output voltage of LDO 1V in mV + * @param[in] ptr base address + * @param[in] mv target voltage + * @retval status_success if successfully configured + */ +hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); + +/* + * @brief get current DCDC current level in mA + * + * @param[in] ptr base address + * @retval Current level at mA + */ +uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* HPM_PCFG_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_pcfg_regs.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_pcfg_regs.h new file mode 100644 index 00000000..72be5c68 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_pcfg_regs.h @@ -0,0 +1,846 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PCFG_H +#define HPM_PCFG_H + +typedef struct { + __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ + __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ + __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ + __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ + __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ + __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ + __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ + __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ + __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ + __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ + __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ + __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ + __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ + __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ + __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ + __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ + __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ + __R uint8_t RESERVED2[16]; /* 0x50 - 0x5F: Reserved */ + __RW uint32_t RC24M; /* 0x60: RC 24M config */ + __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ + __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ + __R uint32_t STATUS; /* 0x6C: RC 24M track status */ +} PCFG_Type; + + +/* Bitfield definition for register: BANDGAP */ +/* + * VBG_TRIMMED (RW) + * + * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: bandgap is not trimmed + * 1: bandgap is trimmed + */ +#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) +#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) +#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) +#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) + +/* + * VBG_1P0_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) +#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) +#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) + +/* + * VBG_P65_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) +#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) + +/* + * VBG_P50_TRIM (RW) + * + * Banggap 1.0V output trim value + */ +#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) +#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) +#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) +#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) + +/* Bitfield definition for register: LDO1P1 */ +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO1P1_ENABLE_MASK (0x10000UL) +#define PCFG_LDO1P1_ENABLE_SHIFT (16U) +#define PCFG_LDO1P1_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_ENABLE_SHIFT) & PCFG_LDO1P1_ENABLE_MASK) +#define PCFG_LDO1P1_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_ENABLE_MASK) >> PCFG_LDO1P1_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. + * 700: 700mV + * 720: 720mV + * . . . + * 1320:1320mV + */ +#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) +#define PCFG_LDO1P1_VOLT_SHIFT (0U) +#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) +#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) + +/* Bitfield definition for register: LDO2P5 */ +/* + * READY (RO) + * + * Ready flag, will set 1ms after enabled or voltage change + * 0: LDO is not ready for use + * 1: LDO is ready + */ +#define PCFG_LDO2P5_READY_MASK (0x10000000UL) +#define PCFG_LDO2P5_READY_SHIFT (28U) +#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) + +/* + * ENABLE (RW) + * + * LDO enable + * 0: turn off LDO + * 1: turn on LDO + */ +#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) +#define PCFG_LDO2P5_ENABLE_SHIFT (16U) +#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) +#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) + +/* + * VOLT (RW) + * + * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. + * 2125: 2125mV + * 2150: 2150mV + * . . . + * 2900:2900mV + */ +#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) +#define PCFG_LDO2P5_VOLT_SHIFT (0U) +#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) +#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_MODE */ +/* + * READY (RO) + * + * Ready flag + * 0: DCDC is applying new change + * 1: DCDC is ready + */ +#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) +#define PCFG_DCDC_MODE_READY_SHIFT (28U) +#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) + +/* + * MODE (RW) + * + * DCDC work mode + * XX0: trun off + * 001: basic mode + * 011: generic mode + * 101: automatic mode + * 111: expert mode + */ +#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) +#define PCFG_DCDC_MODE_MODE_SHIFT (16U) +#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) +#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) + +/* + * VOLT (RW) + * + * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) +#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) +#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_LPMODE */ +/* + * STBY_VOLT (RW) + * + * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. + * 600: 600mV + * 625: 625mV + * . . . + * 1375:1375mV + */ +#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) +#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) +#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) + +/* Bitfield definition for register: DCDC_PROT */ +/* + * ILIMIT_LP (RW) + * + * over current setting for low power mode + * 0:250mA + * 1:200mA + */ +#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) +#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) +#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) +#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) + +/* + * OVERLOAD_LP (RO) + * + * over current in low power mode + * 0: current is below setting + * 1: overcurrent happened in low power mode + */ +#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) +#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) +#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) + +/* + * POWER_LOSS_FLAG (RO) + * + * power loss + * 0: input power is good + * 1: input power is too low + */ +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) +#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) + +/* + * DISABLE_OVERVOLTAGE (RW) + * + * ouput over voltage protection + * 0: protection enabled, DCDC will shut down is output voltage is unexpected high + * 1: protection disabled, DCDC continue to adjust output voltage + */ +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) +#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) + +/* + * OVERVOLT_FLAG (RO) + * + * output over voltage flag + * 0: output is normal + * 1: output is unexpected high + */ +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) +#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) + +/* + * DISABLE_SHORT (RW) + * + * disable output short circuit protection + * 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected + * 1: short circuit protection disabled + */ +#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) +#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) +#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) + +/* + * SHORT_CURRENT (RW) + * + * short circuit current setting + * 0: 2.0A, + * 1: 1.3A + */ +#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) +#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) +#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) + +/* + * SHORT_FLAG (RO) + * + * short circuit flag + * 0: current is within limit + * 1: short circuits detected + */ +#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) +#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) +#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) + +/* Bitfield definition for register: DCDC_CURRENT */ +/* + * ESTI_EN (RW) + * + * enable current measure + */ +#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) +#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) +#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) + +/* + * VALID (RO) + * + * Current level valid + * 0: data is invalid + * 1: data is valid + */ +#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) +#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) +#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) + +/* + * LEVEL (RO) + * + * DCDC current level, current level is num * 50mA + */ +#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) +#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) +#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) + +/* Bitfield definition for register: DCDC_ADVMODE */ +/* + * EN_RCSCALE (RW) + * + * Enable RC scale + */ +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) +#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) + +/* + * DC_C (RW) + * + * Loop C number + */ +#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) +#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) +#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) +#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) + +/* + * DC_R (RW) + * + * Loop R number + */ +#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) +#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) +#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) +#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) + +/* + * EN_FF_DET (RW) + * + * enable feed forward detect + * 0: feed forward detect is disabled + * 1: feed forward detect is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) + +/* + * EN_FF_LOOP (RW) + * + * enable feed forward loop + * 0: feed forward loop is disabled + * 1: feed forward loop is enabled + */ +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) +#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) + +/* + * EN_AUTOLP (RW) + * + * enable auto enter low power mode + * 0: do not enter low power mode + * 1: enter low power mode if current is detected low + */ +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) +#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) + +/* + * EN_DCM_EXIT (RW) + * + * avoid over voltage + * 0: stay in DCM mode when voltage excess + * 1: change to CCM mode when voltage excess + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) + +/* + * EN_SKIP (RW) + * + * enable skip on narrow pulse + * 0: do not skip narrow pulse + * 1: skip narrow pulse + */ +#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) +#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) +#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) + +/* + * EN_IDLE (RW) + * + * enable skip when voltage is higher than threshold + * 0: do not skip + * 1: skip if voltage is excess + */ +#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) +#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) +#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) + +/* + * EN_DCM (RW) + * + * DCM mode + * 0: CCM mode + * 1: DCM mode + */ +#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) +#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) +#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) + +/* Bitfield definition for register: DCDC_ADVPARAM */ +/* + * MIN_DUT (RW) + * + * minimum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) + +/* + * MAX_DUT (RW) + * + * maximum duty cycle + */ +#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) +#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) + +/* Bitfield definition for register: DCDC_MISC */ +/* + * EN_HYST (RW) + * + * hysteres enable + */ +#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) +#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) +#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) +#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) + +/* + * HYST_SIGN (RW) + * + * hysteres sign + */ +#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) +#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) +#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) +#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) + +/* + * HYST_THRS (RW) + * + * hysteres threshold + */ +#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) +#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) +#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) +#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) + +/* + * RC_SCALE (RW) + * + * Loop RC scale threshold + */ +#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) +#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) +#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) +#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) + +/* + * DC_FF (RW) + * + * Loop feed forward number + */ +#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) +#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) +#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) +#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) + +/* + * OL_THRE (RW) + * + * overload for threshold for lod power mode + */ +#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) +#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) +#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) +#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) + +/* + * OL_HYST (RW) + * + * current hysteres range + * 0: 12.5mV + * 1: 25mV + */ +#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) +#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) +#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) +#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) + +/* + * DELAY (RW) + * + * enable delay + * 0: delay disabled, + * 1: delay enabled + */ +#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) +#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) +#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) +#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) + +/* + * CLK_SEL (RW) + * + * clock selection + * 0: select DCDC internal oscillator + * 1: select RC24M oscillator + */ +#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) +#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) +#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) +#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) + +/* + * EN_STEP (RW) + * + * enable stepping in voltage change + * 0: stepping disabled, + * 1: steping enabled + */ +#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) +#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) +#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) +#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) + +/* Bitfield definition for register: DCDC_DEBUG */ +/* + * UPDATE_TIME (RW) + * + * DCDC voltage change time in 24M clock cycles, default value is 1mS + */ +#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) +#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_START_TIME */ +/* + * START_TIME (RW) + * + * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS + */ +#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) +#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) +#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) + +/* Bitfield definition for register: DCDC_RESUME_TIME */ +/* + * RESUME_TIME (RW) + * + * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS + */ +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) +#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) + +/* Bitfield definition for register: POWER_TRAP */ +/* + * TRIGGERED (RW) + * + * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. + * 0: low power trap is not triggered + * 1: low power trap triggered + */ +#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) +#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) +#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) +#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) + +/* + * RETENTION (RW) + * + * DCDC enter standby mode, which will reduce voltage for memory content retention + * 0: Shutdown DCDC + * 1: reduce DCDC voltage + */ +#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) +#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) +#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) +#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) + +/* + * TRAP (RW) + * + * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered + * 0: trap not enabled, pmic side low power function disabled + * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. + */ +#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) +#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) +#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) +#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) + +/* Bitfield definition for register: WAKE_CAUSE */ +/* + * CAUSE (RW) + * + * wake up cause, each bit represents one wake up source, write 1 to clear the register bit + * 0: wake up source is not active during last wakeup + * 1: wake up source is active furing last wakeup + * bit 0: pmic_enable + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit31: pin wakeup + */ +#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) +#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) +#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) + +/* Bitfield definition for register: WAKE_MASK */ +/* + * MASK (RW) + * + * mask for wake up sources, each bit represents one wakeup source + * 0: allow source to wake up system + * 1: disallow source to wakeup system + * bit 0: pmic_enable + * bit 7: UART interrupt + * bit 8: TMR interrupt + * bit 9: WDG interrupt + * bit10: GPIO in PMIC interrupt + * bit31: pin wakeup + */ +#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) +#define PCFG_WAKE_MASK_MASK_SHIFT (0U) +#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) +#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) + +/* Bitfield definition for register: SCG_CTRL */ +/* + * SCG (RW) + * + * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral + * 00,01: reserved + * 10: clock is always off + * 11: clock is always on + * bit6-7:gpio + * bit8-9:ioc + * bit10-11: timer + * bit12-13:wdog + * bit14-15:uart + */ +#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) +#define PCFG_SCG_CTRL_SCG_SHIFT (0U) +#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) +#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) + +/* Bitfield definition for register: RC24M */ +/* + * RC_TRIMMED (RW) + * + * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: RC is not trimmed + * 1: RC is trimmed + */ +#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) +#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) +#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) +#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) + +/* + * TRIM_C (RW) + * + * Coarse trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_C_MASK (0x700U) +#define PCFG_RC24M_TRIM_C_SHIFT (8U) +#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) +#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) + +/* + * TRIM_F (RW) + * + * Fine trim for RC24M, bigger value means faster + */ +#define PCFG_RC24M_TRIM_F_MASK (0x1FU) +#define PCFG_RC24M_TRIM_F_SHIFT (0U) +#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) +#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) + +/* Bitfield definition for register: RC24M_TRACK */ +/* + * SEL24M (RW) + * + * Select track reference + * 0: select 32K as reference + * 1: select 24M XTAL as reference + */ +#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) +#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) +#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) +#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) + +/* + * RETURN (RW) + * + * Retrun default value when XTAL loss + * 0: remain last tracking value + * 1: switch to default value + */ +#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) +#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) +#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) +#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) + +/* + * TRACK (RW) + * + * track mode + * 0: RC24M free running + * 1: track RC24M to external XTAL + */ +#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) +#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) +#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) +#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) + +/* Bitfield definition for register: TRACK_TARGET */ +/* + * PRE_DIV (RW) + * + * Divider for reference source + */ +#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) +#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) +#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) +#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) + +/* + * TARGET (RW) + * + * Target frequency multiplier of divided source + */ +#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) +#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) +#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) +#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * SEL32K (RO) + * + * track is using XTAL32K + * 0: track is not using XTAL32K + * 1: track is using XTAL32K + */ +#define PCFG_STATUS_SEL32K_MASK (0x100000UL) +#define PCFG_STATUS_SEL32K_SHIFT (20U) +#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) + +/* + * SEL24M (RO) + * + * track is using XTAL24M + * 0: track is not using XTAL24M + * 1: track is using XTAL24M + */ +#define PCFG_STATUS_SEL24M_MASK (0x10000UL) +#define PCFG_STATUS_SEL24M_SHIFT (16U) +#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) + +/* + * EN_TRIM (RO) + * + * default value takes effect + * 0: default value is invalid + * 1: default value is valid + */ +#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) +#define PCFG_STATUS_EN_TRIM_SHIFT (15U) +#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) + +/* + * TRIM_C (RO) + * + * default coarse trim value + */ +#define PCFG_STATUS_TRIM_C_MASK (0x700U) +#define PCFG_STATUS_TRIM_C_SHIFT (8U) +#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) + +/* + * TRIM_F (RO) + * + * default fine trim value + */ +#define PCFG_STATUS_TRIM_F_MASK (0x1FU) +#define PCFG_STATUS_TRIM_F_SHIFT (0U) +#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) + + + + +#endif /* HPM_PCFG_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_pdgo_regs.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_pdgo_regs.h new file mode 100644 index 00000000..1bd97b31 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_pdgo_regs.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PDGO_H +#define HPM_PDGO_H + +typedef struct { + __W uint32_t DGO_TURNOFF; /* 0x0: trunoff control */ + __RW uint32_t DGO_RC32K_CFG; /* 0x4: RC32K CLOCK */ + __R uint8_t RESERVED0[1528]; /* 0x8 - 0x5FF: Reserved */ + __RW uint32_t DGO_GPR00; /* 0x600: Generic control 0 */ + __RW uint32_t DGO_GPR01; /* 0x604: Generic control 1 */ + __RW uint32_t DGO_GPR02; /* 0x608: Generic control 2 */ + __RW uint32_t DGO_GPR03; /* 0x60C: Generic control 3 */ + __R uint8_t RESERVED1[240]; /* 0x610 - 0x6FF: Reserved */ + __RW uint32_t DGO_CTR0; /* 0x700: control register 0 */ + __RW uint32_t DGO_CTR1; /* 0x704: control register 1 */ + __RW uint32_t DGO_CTR2; /* 0x708: control register 2 */ + __RW uint32_t DGO_CTR3; /* 0x70C: control register 3 */ + __RW uint32_t DGO_CTR4; /* 0x710: control register 4 */ +} PDGO_Type; + + +/* Bitfield definition for register: DGO_TURNOFF */ +/* + * COUNTER (WO) + * + * trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1. + */ +#define PDGO_DGO_TURNOFF_COUNTER_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_TURNOFF_COUNTER_SHIFT (0U) +#define PDGO_DGO_TURNOFF_COUNTER_SET(x) (((uint32_t)(x) << PDGO_DGO_TURNOFF_COUNTER_SHIFT) & PDGO_DGO_TURNOFF_COUNTER_MASK) +#define PDGO_DGO_TURNOFF_COUNTER_GET(x) (((uint32_t)(x) & PDGO_DGO_TURNOFF_COUNTER_MASK) >> PDGO_DGO_TURNOFF_COUNTER_SHIFT) + +/* Bitfield definition for register: DGO_RC32K_CFG */ +/* + * IRC_TRIMMED (RW) + * + * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value + * 0: irc is not trimmed + * 1: irc is trimmed + */ +#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) +#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT (31U) +#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) +#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) >> PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) + +/* + * CAPEX7_TRIM (RW) + * + * IRC32K bit 7 + */ +#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) +#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT (23U) +#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) +#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) + +/* + * CAPEX6_TRIM (RW) + * + * IRC32K bit 6 + */ +#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) +#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT (22U) +#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) +#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) + +/* + * CAP_TRIM (RW) + * + * capacitor trim bits + */ +#define PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK (0x1FFU) +#define PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT (0U) +#define PDGO_DGO_RC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) +#define PDGO_DGO_RC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) + +/* Bitfield definition for register: DGO_GPR00 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PDGO_DGO_GPR00_GPR_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_GPR00_GPR_SHIFT (0U) +#define PDGO_DGO_GPR00_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR00_GPR_SHIFT) & PDGO_DGO_GPR00_GPR_MASK) +#define PDGO_DGO_GPR00_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR00_GPR_MASK) >> PDGO_DGO_GPR00_GPR_SHIFT) + +/* Bitfield definition for register: DGO_GPR01 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PDGO_DGO_GPR01_GPR_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_GPR01_GPR_SHIFT (0U) +#define PDGO_DGO_GPR01_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR01_GPR_SHIFT) & PDGO_DGO_GPR01_GPR_MASK) +#define PDGO_DGO_GPR01_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR01_GPR_MASK) >> PDGO_DGO_GPR01_GPR_SHIFT) + +/* Bitfield definition for register: DGO_GPR02 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PDGO_DGO_GPR02_GPR_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_GPR02_GPR_SHIFT (0U) +#define PDGO_DGO_GPR02_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR02_GPR_SHIFT) & PDGO_DGO_GPR02_GPR_MASK) +#define PDGO_DGO_GPR02_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR02_GPR_MASK) >> PDGO_DGO_GPR02_GPR_SHIFT) + +/* Bitfield definition for register: DGO_GPR03 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PDGO_DGO_GPR03_GPR_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_GPR03_GPR_SHIFT (0U) +#define PDGO_DGO_GPR03_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR03_GPR_SHIFT) & PDGO_DGO_GPR03_GPR_MASK) +#define PDGO_DGO_GPR03_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR03_GPR_MASK) >> PDGO_DGO_GPR03_GPR_SHIFT) + +/* Bitfield definition for register: DGO_CTR0 */ +/* + * RETENTION (RW) + * + * dgo register status retenion + */ +#define PDGO_DGO_CTR0_RETENTION_MASK (0x10000UL) +#define PDGO_DGO_CTR0_RETENTION_SHIFT (16U) +#define PDGO_DGO_CTR0_RETENTION_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR0_RETENTION_SHIFT) & PDGO_DGO_CTR0_RETENTION_MASK) +#define PDGO_DGO_CTR0_RETENTION_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR0_RETENTION_MASK) >> PDGO_DGO_CTR0_RETENTION_SHIFT) + +/* Bitfield definition for register: DGO_CTR1 */ +/* + * AOTO_SYS_WAKEUP (RW) + * + * software wakeup： 0 : wakeup once； 1：auto wakeup Continuously + */ +#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK (0x80000000UL) +#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT (31U) +#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) +#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) >> PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) + +/* + * WAKEUP_EN (RW) + * + * permit wakeup pin or software wakeup + */ +#define PDGO_DGO_CTR1_WAKEUP_EN_MASK (0x10000UL) +#define PDGO_DGO_CTR1_WAKEUP_EN_SHIFT (16U) +#define PDGO_DGO_CTR1_WAKEUP_EN_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) +#define PDGO_DGO_CTR1_WAKEUP_EN_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) >> PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) + +/* + * PIN_WAKEUP_STATUS (RO) + * + * wakeup pin status + */ +#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK (0x1U) +#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT (0U) +#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK) >> PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT) + +/* Bitfield definition for register: DGO_CTR2 */ +/* + * RESETN_PULLUP_DISABLE (RW) + * + * resetn pin pull up disable + */ +#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK (0x1000000UL) +#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT (24U) +#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) +#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) >> PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) + +/* + * WAKEUP_PULLDN_DISABLE (RW) + * + * wakeup pin pull down disable + */ +#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK (0x10000UL) +#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT (16U) +#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) +#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) >> PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) + +/* Bitfield definition for register: DGO_CTR3 */ +/* + * WAKEUP_COUNTER (RW) + * + * software wakeup counter + */ +#define PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK (0xFFFFFFFFUL) +#define PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT (0U) +#define PDGO_DGO_CTR3_WAKEUP_COUNTER_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) +#define PDGO_DGO_CTR3_WAKEUP_COUNTER_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) >> PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) + +/* Bitfield definition for register: DGO_CTR4 */ +/* + * BANDGAP_LESS_POWER (RW) + * + * Banggap work in power save mode, banggap function normally + * 0: banggap works in high performance mode + * 1: banggap works in power saving mode + */ +#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK (0x2U) +#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT (1U) +#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) +#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) >> PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) + +/* + * BANDGAP_LP_MODE (RW) + * + * Banggap work in low power mode, banggap function limited + * 0: banggap works in normal mode + * 1: banggap works in low power mode + */ +#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK (0x1U) +#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT (0U) +#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) +#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) >> PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) + + + + +#endif /* HPM_PDGO_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_pgpr_regs.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_pgpr_regs.h new file mode 100644 index 00000000..0369149b --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_pgpr_regs.h @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PGPR_H +#define HPM_PGPR_H + +typedef struct { + __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ + __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ + __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ + __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ + __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ + __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ + __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ + __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ + __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ + __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ + __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ + __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ + __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ + __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ + __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ + __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ +} PGPR_Type; + + +/* Bitfield definition for register: PMIC_GPR00 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) +#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR01 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) +#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR02 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) +#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR03 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) +#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR04 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) +#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR05 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) +#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR06 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) +#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR07 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) +#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR08 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) +#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR09 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) +#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR10 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) +#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR11 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) +#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR12 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) +#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR13 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) +#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR14 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) +#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) + +/* Bitfield definition for register: PMIC_GPR15 */ +/* + * GPR (RW) + * + * Generic control + */ +#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) +#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) +#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) +#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) + + + + +#endif /* HPM_PGPR_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_plic_drv.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_plic_drv.h new file mode 100644 index 00000000..4c96737e --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_plic_drv.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PLIC_DRV_H +#define HPM_PLIC_DRV_H + +/** + * @brief PLIC driver APIs + * @defgroup plic_interface PLIC driver APIs + * @{ + */ + +#define HPM_PLIC_TARGET_M_MODE 0 +#define HPM_PLIC_TARGET_S_MODE 1 + +/* Feature Register */ +#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) +#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) +#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) + +/* Priority Register - 32 bits per irq */ +#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) +#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 + +/* Pending Register - 1 bit per source */ +#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) +#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 + +#define HPM_PLIC_TRIGGER_TYPE_OFFSET (0x00001080UL) +#define HPM_PLIC_TRIGGER_TYPE_SHIFT_PER_SORUCE 1 + +/* Enable Register - 0x80 per target */ +#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) +#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 + +/* Priority Threshold Register - 0x1000 per target */ +#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) +#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 + + +/* Claim Register - 0x1000 per target */ +#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) +#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#if !defined(__ASSEMBLER__) + +/** + * @brief Set plic feature + * + * @param[in] base PLIC base address + * @param[in] feature Specific feature to be set + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) +{ + *(volatile uint32_t *) (base + HPM_PLIC_FEATURE_OFFSET) = feature; +} + +/** + * @brief Set plic threshold + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] threshold Threshold of IRQ can be serviced + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, + uint32_t target, + uint32_t threshold) +{ + volatile uint32_t *threshold_ptr = (volatile uint32_t *) (base + + HPM_PLIC_THRESHOLD_OFFSET + + (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); + *threshold_ptr = threshold; +} + +/** + * @brief Set interrupt priority + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * @param[in] priority Priority to be assigned + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, + uint32_t irq, + uint32_t priority) +{ + volatile uint32_t *priority_ptr = (volatile uint32_t *) (base + + HPM_PLIC_PRIORITY_OFFSET + + ((irq - 1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; +} + +/** + * @brief Set interrupt pending bit + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); + *current_ptr = (1 << (irq & 0x1F)); +} + +/** + * @brief Set interrupt trigger type to edge-triggerred + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq_edge_trigger(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_TRIGGER_TYPE_OFFSET + ((irq >> 5) << 2)); + *current_ptr |= (1UL << (irq & 0x1F)); +} + +/** + * @brief Set interrupt trigger type to level-triggerred + * + * @param[in] base PLIC base address + * @param[in] irq Target interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq_level_trigger(uint32_t base, uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_TRIGGER_TYPE_OFFSET + ((irq >> 5) << 2)); + *current_ptr &= ~(1UL << (irq & 0x1F)); +} + +/** + * @brief Enable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be enabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current | (1 << (irq & 0x1F)); + *current_ptr = current; +} + +/** + * @brief Disable interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number to be disabled + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *current_ptr = (volatile uint32_t *) (base + + HPM_PLIC_ENABLE_OFFSET + + (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + + ((irq >> 5) << 2)); + uint32_t current = *current_ptr; + current = current & ~((1 << (irq & 0x1F))); + *current_ptr = current; +} + +/** + * @brief Claim interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to claim interrupt + * + */ +ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *) (base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + return *claim_addr; +} + +/** + * @brief Complete interrupt + * + * @param[in] base PLIC base address + * @param[in] target Target to handle specific interrupt + * @param[in] irq Interrupt number + * + */ +ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, + uint32_t target, + uint32_t irq) +{ + volatile uint32_t *claim_addr = (volatile uint32_t *) (base + + HPM_PLIC_CLAIM_OFFSET + + (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = irq; +} + +#endif /* __ASSEMBLER__ */ +/** + * @} + */ +#endif /* HPM_PLIC_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_pmic_iomux.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_pmic_iomux.h new file mode 100644 index 00000000..f23a7185 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_pmic_iomux.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PMIC_IOMUX_H +#define HPM_PMIC_IOMUX_H + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY00_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY01_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY02_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY03_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) +#define IOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) +#define IOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) +#define IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) + + +#endif /* HPM_PMIC_IOMUX_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_ppor_drv.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_ppor_drv.h new file mode 100644 index 00000000..3d836857 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_ppor_drv.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PPOR_DRV_H +#define HPM_PPOR_DRV_H +#include "hpm_ppor_regs.h" + +typedef enum { + ppor_reset_brownout = 1 << 0, + ppor_reset_debug = 1 << 4, + ppor_reset_wdog0 = 1 << 16, + ppor_reset_wdog1 = 1 << 17, + ppor_reset_pmic_wdog = 1 << 24, + ppor_reset_software = 1 << 31, +} ppor_reset_source_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * perform software reset in counter * (1/24Mhz) seconds + */ +static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) +{ + ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } + +/* + * clear enable reset source according to the given mask + */ +static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE &= ~mask; +} + +/* + * set enable reset source according to the given mask + */ +static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_ENABLE |= mask; +} + +/* + * set enable reset source + */ +static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) +{ + ptr->RESET_ENABLE = reset_sources; +} + +/* + * get enabled reset source + */ +static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) +{ + return ptr->RESET_ENABLE; +} + +/* + * get reset status + */ +static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) +{ + return ptr->RESET_STATUS; +} + +/* + * get reset flags + */ +static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) +{ + return ptr->RESET_FLAG; +} + +/* + * clear reset flags + */ +static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_FLAG |= mask; +} + +/* + * set cold reset + */ +static inline void ppor_reset_set_reset_type(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_TYPE = mask; +} + +/* + * clear cold reset + */ +static inline void ppor_reset_clear_reset_type(PPOR_Type *ptr, uint32_t mask) +{ + ptr->RESET_TYPE &= ~mask; +} + + +#ifdef __cplusplus +} +#endif +#endif diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_ppor_regs.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_ppor_regs.h new file mode 100644 index 00000000..529cc169 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_ppor_regs.h @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PPOR_H +#define HPM_PPOR_H + +typedef struct { + __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ + __R uint32_t RESET_STATUS; /* 0x4: reset source status */ + __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ + __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ + __RW uint32_t RESET_TYPE; /* 0x10: reset type triggered by reset */ + __R uint8_t RESERVED0[8]; /* 0x14 - 0x1B: Reserved */ + __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ +} PPOR_Type; + + +/* Bitfield definition for register: RESET_FLAG */ +/* + * FLAG (W1C) + * + * reset reason of last hard reset, write 1 to clear each bit + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) +#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) +#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) + +/* Bitfield definition for register: RESET_STATUS */ +/* + * STATUS (RO) + * + * current status of reset sources + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) +#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register: RESET_HOLD */ +/* + * HOLD (RW) + * + * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_HOLD_HOLD_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_HOLD_HOLD_SHIFT (0U) +#define PPOR_RESET_HOLD_HOLD_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_HOLD_SHIFT) & PPOR_RESET_HOLD_HOLD_MASK) +#define PPOR_RESET_HOLD_HOLD_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_HOLD_MASK) >> PPOR_RESET_HOLD_HOLD_SHIFT) + +/* Bitfield definition for register: RESET_ENABLE */ +/* + * ENABLE (RW) + * + * enable of reset sources + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) +#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) +#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) + +/* Bitfield definition for register: RESET_TYPE */ +/* + * TYPE (RW) + * + * reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem + * 0: brownout + * 1: temperature + * 4: debug reset + * 5: jtag soft reset + * 8: cpu0 lockup(not available) + * 9: cpu1 lockup(not available) + * 10: cpu0 request(not available) + * 11: cpu1 request(not available) + * 16: watch dog 0 + * 17: watch dog 1 + * 18: watch dog 2(not available) + * 19: watch dog 3(not available) + * 24: pmic watch dog + * 30: jtag ieee reset + * 31: software + */ +#define PPOR_RESET_TYPE_TYPE_MASK (0xFFFFFFFFUL) +#define PPOR_RESET_TYPE_TYPE_SHIFT (0U) +#define PPOR_RESET_TYPE_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_TYPE_TYPE_SHIFT) & PPOR_RESET_TYPE_TYPE_MASK) +#define PPOR_RESET_TYPE_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_TYPE_TYPE_MASK) >> PPOR_RESET_TYPE_TYPE_SHIFT) + +/* Bitfield definition for register: SOFTWARE_RESET */ +/* + * COUNTER (RW) + * + * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset + */ +#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) +#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) +#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) +#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) + + + + +#endif /* HPM_PPOR_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_romapi.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_romapi.h new file mode 100644 index 00000000..26f951ca --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_romapi.h @@ -0,0 +1,938 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_H +#define HPM_ROMAPI_H + +/** + * @brief ROM APIs + * @defgroup romapi_interface ROM APIs + * @{ + */ + +#include "hpm_common.h" +#include "hpm_otp_drv.h" +#include "hpm_romapi_xpi_def.h" +#include "hpm_romapi_xpi_soc_def.h" +#include "hpm_romapi_xpi_nor_def.h" +#include "hpm_romapi_xpi_ram_def.h" +#include "hpm_sdp_drv.h" + +/* XPI0 base address */ +#define HPM_XPI0_BASE (0xF3000000UL) /**< XPI0 Base address */ +/* XPI0 base pointer */ +#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ + + +/*********************************************************************************************************************** + * + * + * Definitions + * + * + **********************************************************************************************************************/ +/** + * @brief Enter Bootloader API argument + */ +typedef union { + uint32_t U; + struct { + uint32_t index: 8; /**< Image index */ + uint32_t peripheral: 8; /**< Boot peripheral */ + uint32_t src: 8; /**< Boot source */ + uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ + }; +} api_boot_arg_t; + +/*EXiP Region Parameter */ +typedef struct { + uint32_t start; /**< Start address, must be 4KB aligned */ + uint32_t len; /**< Must be 4KB aligned */ + uint8_t key[16]; /**< AES Key */ + uint8_t ctr[8]; /**< Initial Vector/Counter */ +} exip_region_param_t; + +typedef struct { + uint32_t region_start; + uint32_t region_end; + uint8_t aes_key[16]; + uint8_t nonce[8]; + uint8_t index; + bool enable; + bool valid; + bool lock; +} exip_region_context_t; + +#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ +#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ +#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ +#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ +#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ +#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ +#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ +#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ + +/** + * @brief OTP driver interface + */ +typedef struct { + /**< OTP driver interface version */ + uint32_t version; + /**< OTP driver interface: init */ + void (*init)(void); + /**< OTP driver interface: deinit */ + void (*deinit)(void); + /**< OTP driver interface: read from shadow */ + uint32_t (*read_from_shadow)(uint32_t addr); + /**< OTP driver interface: read from ip */ + uint32_t (*read_from_ip)(uint32_t addr); + /**< OTP driver interface: program */ + hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); + /**< OTP driver interface: reload */ + hpm_stat_t (*reload)(otp_region_t region); + /**< OTP driver interface: lock */ + hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: lock_shadow */ + hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); + /**< OTP driver interface: set_configurable_region */ + hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); + /**< OTP driver interface: write_shadow_register */ + hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); +} otp_driver_interface_t; + +/** + * @brief XPI driver interface + */ +typedef struct { + /**< XPI driver interface: version */ + uint32_t version; + /**< XPI driver interface: get default configuration */ + hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); + /**< XPI driver interface: get default device configuration */ + hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); + /**< XPI driver interface: initialize the XPI using xpi_config */ + hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); + /**< XPI driver interface: configure the AHB buffer */ + hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); + /**< XPI driver interface: configure the device */ + hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); + /**< XPI driver interface: update instruction talbe */ + hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); + /**< XPI driver interface: transfer command/data using block interface */ + hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); + /**< Software reset the XPI controller */ + void (*software_reset)(XPI_Type *base); + /**< XPI driver interface: Check whether IP is idle */ + bool (*is_idle)(XPI_Type *base); + /**< XPI driver interface: update delay line setting */ + void (*update_dllcr)(XPI_Type *base, + uint32_t serial_root_clk_freq, + uint32_t data_valid_time, + xpi_channel_t channel, + uint32_t dly_target); + /**< XPI driver interface: Get absolute address for APB transfer */ + hpm_stat_t + (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); +} xpi_driver_interface_t; + +/** + * @brief XPI NOR driver interface + */ +typedef struct { + /**< XPI NOR driver interface: API version */ + uint32_t version; + /**< XPI NOR driver interface: Get FLASH configuration */ + hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + /**< XPI NOR driver interface: initialize FLASH */ + hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Enable write access to FLASH */ + hpm_stat_t + (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Get FLASH status register */ + hpm_stat_t (*get_status)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr, + uint16_t *out_status); + /**< XPI NOR driver interface: Wait when FLASH is still busy */ + hpm_stat_t + (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: erase a specified FLASH region */ + hpm_stat_t (*erase)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: Erase the whole FLASH */ + hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + /**< XPI NOR driver interface: Erase specified FLASH sector */ + hpm_stat_t + (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Erase specified FLASH block */ + hpm_stat_t + (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); + /**< XPI NOR driver interface: Program data to specified FLASH address */ + hpm_stat_t (*program)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: read data from specified FLASH address */ + hpm_stat_t (*read)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length); + /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ + hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length); + /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ + hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ + hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr); + /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ + hpm_stat_t + (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); + + uint32_t reserved0[3]; + + /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ + hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); + + /**< XPI NOR driver interface: Get FLASH properties */ + hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); + +} xpi_nor_driver_interface_t; + +/** + * @brief EXIP driver interface + */ +typedef struct { + uint32_t version; + hpm_stat_t (*enable)(XPI_Type *base); + hpm_stat_t (*disable)(XPI_Type *base); + hpm_stat_t (*lock_reg_access)(XPI_Type *base); + hpm_stat_t (*configure_region)(XPI_Type *base, const exip_region_context_t *ctx); + + bool (*remap_config)(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset); + bool (*remap_enabled)(XPI_Type *base); + void (*remap_disable)(XPI_Type *base); + bool (*exip_region_config)(XPI_Type *base, uint32_t index, exip_region_param_t *param); + void (*exip_region_disable)(XPI_Type *base, uint32_t index); +} exip_driver_interface_t; + +/** + * @brief SDP API interface + */ +typedef struct { + /**< SDP API interface: API version */ + uint32_t version; + /**< SDP API interface: Initialize IP */ + hpm_stat_t (*sdp_ip_init)(void); + /**< SDP API interface: Deinitialize IP */ + hpm_stat_t (*sdp_ip_deinit)(void); + /**< SDP API interface: Set AES key */ + hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); + /**< SDP API interface: AES ECB crypto operation */ + hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); + /**< SDP API interface: AES CBC crypto operation */ + hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *input, + uint8_t *output); + /**< SDP API interface: AES CTR crypto operation */ + hpm_stat_t + (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); + /**< SDP API interface: AES CCM encryption */ + hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); + /**< SDP API interface: AES CCM Decrypt and verify */ + hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); + /**< SDP API interface: memcpy */ + hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); + /**< SDP API interface: memset */ + hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); + /**< SDP API interface: HASH initialization */ + hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); + /**< SDP API interface: HASH update */ + hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); + /**< SDP API interface: HASH finish */ + hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); + /**< SDP API interface: Set SM4 Key */ + hpm_stat_t (*sm4_set_key)(sdp_sm4_ctx_t *sm4_ctx, const uint8_t *key, sdp_sm4_key_bits_t keybits, uint32_t key_idx); + /**< SDP API interface: SM4 Crypto ECB mode */ + hpm_stat_t (*sm4_crypt_ecb)(sdp_sm4_ctx_t *sm4_ctx, sdp_sm4_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); + /**< SDP API Interface: SM4 Crypto CBC mode*/ + hpm_stat_t (*sm4_crypt_cbc)(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *input, + uint8_t *output); + /**< SDP API Interface: SM4 CTR mode */ + hpm_stat_t + (*sm4_crypt_ctr)(sdp_sm4_ctx_t *sm4_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); + /**< SDP API Interface: SM4 CCM Encryption */ + hpm_stat_t (*sm4_ccm_gen_enc)(sdp_sm4_ctx_t *sm4_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + uint8_t *tag, + uint32_t tag_len); + /**< SDP API Interface: SM4 CCM Decrypt and Verify */ + hpm_stat_t (*sm4_ccm_dec_verify)(sdp_sm4_ctx_t *sm4_ctx, + uint32_t input_len, + const uint8_t *nonce, + uint32_t nonce_len, + const uint8_t *aad, + uint32_t aad_len, + const uint8_t *input, + uint8_t *output, + const uint8_t *tag, + uint32_t tag_len); +} sdp_driver_interface_t; + +/** + * @brief Bootloader API table + */ +typedef struct { + /**< Bootloader API table: version */ + const uint32_t version; + /**< Bootloader API table: copyright string address */ + const char *copyright; + /**< Bootloader API table: run_bootloader API */ + const hpm_stat_t (*run_bootloader)(void *arg); + /**< Bootloader API table: otp driver interface address */ + const otp_driver_interface_t *otp_driver_if; + /**< Bootloader API table: xpi driver interface address */ + const xpi_driver_interface_t *xpi_driver_if; + /**< Bootloader API table: xpi nor driver interface address */ + const xpi_nor_driver_interface_t *xpi_nor_driver_if; + /**< Bootloader API table: xpi ram driver interface address */ + const uint32_t reserved0; + /**< Bootloader API table: sdp driver interface address */ + const sdp_driver_interface_t *sdp_driver_if; + const uint32_t reserved2; + const exip_driver_interface_t *exip_api_if; + const uint32_t family_id; +} bootloader_api_table_t; + +/**< Bootloader API table Root */ +#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) + + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** + * + * + * Enter bootloader Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Eneter specified Boot mode + * @param [in] ctx Enter bootloader context + * @retval status_invalid Invalid parameters were deteced + */ +static inline hpm_stat_t rom_enter_bootloader(void *ctx) +{ + return ROM_API_TABLE_ROOT->run_bootloader(ctx); +} + +/*********************************************************************************************************************** + * + * + * XPI NOR Driver Wrapper + * + * + **********************************************************************************************************************/ + +/** + * @brief Get XPI NOR configuration via cfg_option + * @param [in] base XPI base address + * @param [out] nor_cfg XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, + xpi_nor_config_t *nor_cfg, + xpi_nor_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); +} + +/** + * @brief Initialize XPI NOR based on nor_config + * @param [in] base XPI base address + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); +} + +/** + * @brief Erase specified FLASH region + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI nOR configuration + * @param[in] start Erase address start address + * @param[in] length Region size to be erased + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start, + uint32_t length) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); + fencei(); + return status; +} + +/** + * @brief Erase specified FLASH sector in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); + fencei(); + return status; +} + +/** + * @brief Erase specified FLASH sector in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Sector address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase specified FLASH blcok in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); + fencei(); + return status; +} + +/** + * @brief Erase specified FLASH blcok in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] start Block address + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t start) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); +} + +/** + * @brief Erase the whole FLASH in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); +} + +/** + * @brief Erase the whole FLASH in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); + fencei(); + return status; +} + +/** + * @brief Program data to specified FLASH address in blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); + fencei(); + return status; +} + +/** + * @brief Page-Program data to specified FLASH address in non-blocking way + * @param[in] base XPI base address + * @param[in] channel XPI transfer channel + * @param[in] nor_config XPI NOR configuration + * @param[in] src data source address + * @param[in] dst_addr Destination FLASH address + * @param[in] length length of data to be programmed + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + const uint32_t *src, + uint32_t dst_addr, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if + ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); +} + +/** + * @brief Read data from specified FLASH address + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] dst Memory start address to store the data read out from FLASH + * @param [in] start FLASH address for data read + * @param [in] length length of data to be read out + * @return API execution address + */ +static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t *dst, + uint32_t start, + uint32_t length) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); +} + +/** + * @brief Automatically configure XPI NOR based on cfg_option + * @param [in] base XPI base address + * @param [out] config XPI NOR configuration structure + * @param [in] cfg_option XPI NOR configuration option + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, + xpi_nor_config_t *config, + xpi_nor_config_option_t *cfg_option) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); +} + +/** + * @brief Get XPI NOR properties + * @param [in] base XPI base address + * @param [in] nor_cfg XPI NOR configuration structure + * @param [in] property_id + * @param [out] value property value retrieved by this API + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, + xpi_nor_config_t *nor_cfg, + uint32_t property_id, + uint32_t *value) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); +} + +/** + * @brief Return the status register value on XPI NOR FLASH + * + * @param [in] base XPI base address + * @param [in] channel XPI transfer channel + * @param [in] nor_config XPI NOR configuration + * @param [in] addr FLASH address offset + * @param [out] out_status FLASH status register value + * @return API execution status + */ +static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, + xpi_xfer_channel_t channel, + const xpi_nor_config_t *nor_config, + uint32_t addr, + uint16_t *out_status) +{ + return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); +} + +/** + * @brief Configure the XPI Address Remapping Logic + * @param [in] base XPI base address + * @param [in] start Start Address (memory mapped address) + * @param [in] len Size for the remapping region + * @param [in] offset Relative address based on parameter "start" + * @retval true is all parameters are valid + * @retval false if any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) +{ + return ROM_API_TABLE_ROOT->exip_api_if->remap_config(base, start, len, offset); +} + +/** + * @brief Disable XPI Remapping logic + * @param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_remap_disable(XPI_Type *base) +{ + ROM_API_TABLE_ROOT->exip_api_if->remap_disable(base); + fencei(); +} + +/** + * @brief Check whether XPI Remapping is enabled + * @param [in] base XPI base address + * + * @retval true Remapping logic is enabled + * @retval false Remapping logic is disabled + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) +{ + return ROM_API_TABLE_ROOT->exip_api_if->remap_enabled(base); +} + +/** + * @brief Configure Specified EXiP Region + * @param [in] base XPI base address + * @param [in] index EXiP Region index + * @param [in] param ExiP Region Parameter + * @retval true All parameters are valid + * @retval false Any parameter is invalid + */ +ATTR_RAMFUNC +static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) +{ + bool result = ROM_API_TABLE_ROOT->exip_api_if->exip_region_config(base, index, param); + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); + fencei(); + return result; +} + +/** + * @brief Disable EXiP Feature on specified EXiP Region + * @@param [in] base XPI base address + * @param [in] index EXiP Region index + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) +{ + ROM_API_TABLE_ROOT->exip_api_if->exip_region_disable(base, index); + fencei(); +} + +/** + * @brief Enable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_enable(XPI_Type *base) +{ + ROM_API_TABLE_ROOT->exip_api_if->enable(base); + fencei(); +} + +/** + * @brief Disable global EXiP logic + * @@param [in] base XPI base address + */ +ATTR_RAMFUNC +static inline void rom_xpi_nor_exip_disable(XPI_Type *base) +{ + ROM_API_TABLE_ROOT->exip_api_if->disable(base); + fencei(); +} + +/*********************************************************************************************************************** + * + * + * SDP Driver Wrapper + * + * + **********************************************************************************************************************/ +/** + * @brief Initialize SDP IP + */ +static inline void rom_sdp_init(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); +} + +/** + * @brief De-initialize SDP IP + */ +static inline void rom_sdp_deinit(void) +{ + ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); +} + +/** + * @brief Set AES key to SDP + * @param [in] aes_ctx AES context + * @param [in] key AES key buffer + * @param [in] key_bits AES key-bit option + * @param[in] key_idx AES key index + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, + const uint8_t *key, + sdp_aes_key_bits_t key_bits, + uint32_t key_idx) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); +} + +/** + * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] len Data length for AES encryption/decryption + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t len, + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); +} + +/** + * @brief SDP AES CBC crypto operation(Encrypt or Decrypt) + * @param [in] aes_ctx AES context + * @param [in] op AES operation: encrypt or decrypt + * @param [in] length Data length for AES encryption/decryption + * @param [in] iv Initial vector/nonce + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, + sdp_aes_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); +} + +/** + * @brief Set SM4 key to SDP + * @param [in] sm4_ctx SM4 context + * @param [in] key SM4 key buffer + * @param [in] key_bits SM4 key-bit option + * @param[in] key_idx SM4 key index + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_set_key(sdp_sm4_ctx_t *sm4_ctx, + const uint8_t *key, + sdp_sm4_key_bits_t key_bits, + uint32_t key_idx) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_set_key(sm4_ctx, key, key_bits, key_idx); +} + +/** + * @brief SDP SM4 ECB crypto operation(Encrypt or Decrypt) + * @param [in] sm4_ctx SM4 context + * @param [in] op SM4 operation: encrypt or decrypt + * @param [in] len Data length for SM4 encryption/decryption + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_crypt_ecb(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t len, + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_ecb(sm4_ctx, op, len, in, out); +} + +/** + * @brief SDP SM4 CBC crypto operation(Encrypt or Decrypt) + * @param [in] sm4_ctx SM4 context + * @param [in] op SM4 operation: encrypt or decrypt + * @param [in] length Data length for SM4 encryption/decryption + * @param [in] iv Initial vector/nonce + * @param [in] in Input data + * @param [out] out Output data + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_sm4_crypt_cbc(sdp_sm4_ctx_t *sm4_ctx, + sdp_sm4_op_t op, + uint32_t length, + uint8_t iv[16], + const uint8_t *in, + uint8_t *out) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_cbc(sm4_ctx, op, length, iv, in, out); +} + +/** + * @brief HASH initialization + * @param [in] hash_ctx HASH context + * @param [in] alg HASH algorithm + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); +} + +/** + * @brief HASH Update + * @param [in] hash_ctx HASH context + * @param [in] data Data for HASH operation + * @param [in] length of the data for HASH operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); +} + +/** + * @brief HASH finialize + * @param [in] hash_ctx HASH context + * @param [out] digest the output digest + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); +} + +/** + * @brief SDP memcpy operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memcpy + * @param [in] src Source address for memcpy + * @param [in] length Size of data for memcpy operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); +} + +/** + * @brief SDP memset operation + * @param [in] dma_ctx DMA context + * @param [out] dst Destination address for memset + * @param [in] pattern pattern for memset + * @param [in] length Size of data for memset operation + * @return API execution status + */ +static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) +{ + return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + + +#endif /* HPM_ROMAPI_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_romapi_xpi_soc_def.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_romapi_xpi_soc_def.h new file mode 100644 index 00000000..ea3ba9e8 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_romapi_xpi_soc_def.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_ROMAPI_XPI_SOC_DEF_H +#define HPM_ROMAPI_XPI_SOC_DEF_H + +#include "hpm_common.h" +#include "hpm_romapi_xpi_def.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) +#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) +#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) +#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) +#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) +#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) +#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) +#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) +#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) + +typedef struct { + struct { + uint8_t priority; /* Offset: 0x00 */ + uint8_t master_idx; /* Offset: 0x01 */ + uint8_t buf_size_in_dword; /* Offset: 0x02 */ + bool enable_prefetch; /* Offset: 0x03 */ + } entry[8]; +} xpi_ahb_buffer_cfg_t; + +typedef struct { + uint8_t data_pads; + xpi_channel_t channel; + xpi_io_group_t io_group; + uint8_t drive_strength; + bool enable_dqs; + bool enable_diff_clk; +} xpi_io_config_t; + +typedef enum { + xpi_freq_type_typical, + xpi_freq_type_mhz, +} clk_freq_type_t; + +typedef enum { + xpi_clk_src_auto, + xpi_clk_src_osc, + xpi_clk_src_pll0clk0, + xpi_clk_src_pll1clk0, + xpi_clk_src_pll1clk1, + xpi_clk_src_pll2clk0, + xpi_clk_src_pll2clk1, + xpi_clk_src_pll3clk0, + xpi_clk_src_pll4clk0, +} xpi_clk_src_t; + + +typedef union { + struct { + uint8_t freq; + bool enable_ddr; + xpi_clk_src_t clk_src; + clk_freq_type_t freq_type; + }; + uint32_t freq_opt; +} xpi_clk_config_t; + +typedef enum { + xpi_clock_bus, + xpi_clock_serial_root, + xpi_clock_serial, +} xpi_clock_t; + +#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_ses_reg.xml b/common/libraries/hpm_sdk/soc/HPM5361/hpm_ses_reg.xml new file mode 100644 index 00000000..fb7c308c --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_ses_reg.xml @@ -0,0 +1,24013 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_ses_riscv_cpu_regs.xml b/common/libraries/hpm_sdk/soc/HPM5361/hpm_ses_riscv_cpu_regs.xml new file mode 100644 index 00000000..da5654d4 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_ses_riscv_cpu_regs.xml @@ -0,0 +1,593 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_soc.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_soc.h new file mode 100644 index 00000000..53384406 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_soc.h @@ -0,0 +1,573 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SOC_H +#define HPM_SOC_H + + +/* List of external IRQs */ +#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ +#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ +#define IRQn_GPIO0_X 3 /* GPIO0_X IRQ */ +#define IRQn_GPIO0_Y 4 /* GPIO0_Y IRQ */ +#define IRQn_GPTMR0 5 /* GPTMR0 IRQ */ +#define IRQn_GPTMR1 6 /* GPTMR1 IRQ */ +#define IRQn_GPTMR2 7 /* GPTMR2 IRQ */ +#define IRQn_GPTMR3 8 /* GPTMR3 IRQ */ +#define IRQn_LIN0 9 /* LIN0 IRQ */ +#define IRQn_LIN1 10 /* LIN1 IRQ */ +#define IRQn_LIN2 11 /* LIN2 IRQ */ +#define IRQn_LIN3 12 /* LIN3 IRQ */ +#define IRQn_UART0 13 /* UART0 IRQ */ +#define IRQn_UART1 14 /* UART1 IRQ */ +#define IRQn_UART2 15 /* UART2 IRQ */ +#define IRQn_UART3 16 /* UART3 IRQ */ +#define IRQn_UART4 17 /* UART4 IRQ */ +#define IRQn_UART5 18 /* UART5 IRQ */ +#define IRQn_UART6 19 /* UART6 IRQ */ +#define IRQn_UART7 20 /* UART7 IRQ */ +#define IRQn_I2C0 21 /* I2C0 IRQ */ +#define IRQn_I2C1 22 /* I2C1 IRQ */ +#define IRQn_I2C2 23 /* I2C2 IRQ */ +#define IRQn_I2C3 24 /* I2C3 IRQ */ +#define IRQn_SPI0 25 /* SPI0 IRQ */ +#define IRQn_SPI1 26 /* SPI1 IRQ */ +#define IRQn_SPI2 27 /* SPI2 IRQ */ +#define IRQn_SPI3 28 /* SPI3 IRQ */ +#define IRQn_TSNS 29 /* TSNS IRQ */ +#define IRQn_MBX0A 30 /* MBX0A IRQ */ +#define IRQn_MBX0B 31 /* MBX0B IRQ */ +#define IRQn_WDG0 32 /* WDG0 IRQ */ +#define IRQn_WDG1 33 /* WDG1 IRQ */ +#define IRQn_HDMA 34 /* HDMA IRQ */ +#define IRQn_CAN0 35 /* CAN0 IRQ */ +#define IRQn_CAN1 36 /* CAN1 IRQ */ +#define IRQn_CAN2 37 /* CAN2 IRQ */ +#define IRQn_CAN3 38 /* CAN3 IRQ */ +#define IRQn_PTPC 39 /* PTPC IRQ */ +#define IRQn_PWM0 40 /* PWM0 IRQ */ +#define IRQn_QEI0 41 /* QEI0 IRQ */ +#define IRQn_SEI0 42 /* SEI0 IRQ */ +#define IRQn_MMC0 43 /* MMC0 IRQ */ +#define IRQn_TRGMUX0 44 /* TRGMUX0 IRQ */ +#define IRQn_PWM1 45 /* PWM1 IRQ */ +#define IRQn_QEI1 46 /* QEI1 IRQ */ +#define IRQn_SEI1 47 /* SEI1 IRQ */ +#define IRQn_MMC1 48 /* MMC1 IRQ */ +#define IRQn_TRGMUX1 49 /* TRGMUX1 IRQ */ +#define IRQn_RDC 50 /* RDC IRQ */ +#define IRQn_USB0 51 /* USB0 IRQ */ +#define IRQn_XPI0 52 /* XPI0 IRQ */ +#define IRQn_SDP 53 /* SDP IRQ */ +#define IRQn_PSEC 54 /* PSEC IRQ */ +#define IRQn_SECMON 55 /* SECMON IRQ */ +#define IRQn_RNG 56 /* RNG IRQ */ +#define IRQn_FUSE 57 /* FUSE IRQ */ +#define IRQn_ADC0 58 /* ADC0 IRQ */ +#define IRQn_ADC1 59 /* ADC1 IRQ */ +#define IRQn_DAC0 60 /* DAC0 IRQ */ +#define IRQn_DAC1 61 /* DAC1 IRQ */ +#define IRQn_ACMP_0 62 /* ACMP_0 IRQ */ +#define IRQn_ACMP_1 63 /* ACMP_1 IRQ */ +#define IRQn_SYSCTL 64 /* SYSCTL IRQ */ +#define IRQn_PGPIO 65 /* PGPIO IRQ */ +#define IRQn_PTMR 66 /* PTMR IRQ */ +#define IRQn_PUART 67 /* PUART IRQ */ +#define IRQn_PWDG 68 /* PWDG IRQ */ +#define IRQn_BROWNOUT 69 /* BROWNOUT IRQ */ +#define IRQn_PAD_WAKEUP 70 /* PAD_WAKEUP IRQ */ +#define IRQn_DEBUG0 71 /* DEBUG0 IRQ */ +#define IRQn_DEBUG1 72 /* DEBUG1 IRQ */ + +#include "hpm_common.h" + +#include "hpm_gpio_regs.h" +/* Address of GPIO instances */ +/* FGPIO base address */ +#define HPM_FGPIO_BASE (0xC0000UL) +/* FGPIO base pointer */ +#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) +/* GPIO0 base address */ +#define HPM_GPIO0_BASE (0xF00D0000UL) +/* GPIO0 base pointer */ +#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) +/* PGPIO base address */ +#define HPM_PGPIO_BASE (0xF411C000UL) +/* PGPIO base pointer */ +#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) + +/* Address of DM instances */ +/* DM base address */ +#define HPM_DM_BASE (0x30000000UL) + +#include "hpm_plic_regs.h" +/* Address of PLIC instances */ +/* PLIC base address */ +#define HPM_PLIC_BASE (0xE4000000UL) +/* PLIC base pointer */ +#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) + +#include "hpm_mchtmr_regs.h" +/* Address of MCHTMR instances */ +/* MCHTMR base address */ +#define HPM_MCHTMR_BASE (0xE6000000UL) +/* MCHTMR base pointer */ +#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) + +#include "hpm_plic_sw_regs.h" +/* Address of PLICSW instances */ +/* PLICSW base address */ +#define HPM_PLICSW_BASE (0xE6400000UL) +/* PLICSW base pointer */ +#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) + +#include "hpm_gptmr_regs.h" +/* Address of TMR instances */ +/* GPTMR0 base address */ +#define HPM_GPTMR0_BASE (0xF0000000UL) +/* GPTMR0 base pointer */ +#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) +/* GPTMR1 base address */ +#define HPM_GPTMR1_BASE (0xF0004000UL) +/* GPTMR1 base pointer */ +#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) +/* GPTMR2 base address */ +#define HPM_GPTMR2_BASE (0xF0008000UL) +/* GPTMR2 base pointer */ +#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) +/* GPTMR3 base address */ +#define HPM_GPTMR3_BASE (0xF000C000UL) +/* GPTMR3 base pointer */ +#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) +/* PTMR base address */ +#define HPM_PTMR_BASE (0xF4120000UL) +/* PTMR base pointer */ +#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) + +#include "hpm_linv2_regs.h" +/* Address of LINV2 instances */ +/* LIN0 base address */ +#define HPM_LIN0_BASE (0xF0020000UL) +/* LIN0 base pointer */ +#define HPM_LIN0 ((LINV2_Type *) HPM_LIN0_BASE) +/* LIN1 base address */ +#define HPM_LIN1_BASE (0xF0024000UL) +/* LIN1 base pointer */ +#define HPM_LIN1 ((LINV2_Type *) HPM_LIN1_BASE) +/* LIN2 base address */ +#define HPM_LIN2_BASE (0xF0028000UL) +/* LIN2 base pointer */ +#define HPM_LIN2 ((LINV2_Type *) HPM_LIN2_BASE) +/* LIN3 base address */ +#define HPM_LIN3_BASE (0xF002C000UL) +/* LIN3 base pointer */ +#define HPM_LIN3 ((LINV2_Type *) HPM_LIN3_BASE) + +#include "hpm_uart_regs.h" +/* Address of UART instances */ +/* UART0 base address */ +#define HPM_UART0_BASE (0xF0040000UL) +/* UART0 base pointer */ +#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) +/* UART1 base address */ +#define HPM_UART1_BASE (0xF0044000UL) +/* UART1 base pointer */ +#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) +/* UART2 base address */ +#define HPM_UART2_BASE (0xF0048000UL) +/* UART2 base pointer */ +#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) +/* UART3 base address */ +#define HPM_UART3_BASE (0xF004C000UL) +/* UART3 base pointer */ +#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) +/* UART4 base address */ +#define HPM_UART4_BASE (0xF0050000UL) +/* UART4 base pointer */ +#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) +/* UART5 base address */ +#define HPM_UART5_BASE (0xF0054000UL) +/* UART5 base pointer */ +#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) +/* UART6 base address */ +#define HPM_UART6_BASE (0xF0058000UL) +/* UART6 base pointer */ +#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) +/* UART7 base address */ +#define HPM_UART7_BASE (0xF005C000UL) +/* UART7 base pointer */ +#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) +/* PUART base address */ +#define HPM_PUART_BASE (0xF4124000UL) +/* PUART base pointer */ +#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) + +#include "hpm_i2c_regs.h" +/* Address of I2C instances */ +/* I2C0 base address */ +#define HPM_I2C0_BASE (0xF0060000UL) +/* I2C0 base pointer */ +#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) +/* I2C1 base address */ +#define HPM_I2C1_BASE (0xF0064000UL) +/* I2C1 base pointer */ +#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) +/* I2C2 base address */ +#define HPM_I2C2_BASE (0xF0068000UL) +/* I2C2 base pointer */ +#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) +/* I2C3 base address */ +#define HPM_I2C3_BASE (0xF006C000UL) +/* I2C3 base pointer */ +#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) + +#include "hpm_spi_regs.h" +/* Address of SPI instances */ +/* SPI0 base address */ +#define HPM_SPI0_BASE (0xF0070000UL) +/* SPI0 base pointer */ +#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) +/* SPI1 base address */ +#define HPM_SPI1_BASE (0xF0074000UL) +/* SPI1 base pointer */ +#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) +/* SPI2 base address */ +#define HPM_SPI2_BASE (0xF0078000UL) +/* SPI2 base pointer */ +#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) +/* SPI3 base address */ +#define HPM_SPI3_BASE (0xF007C000UL) +/* SPI3 base pointer */ +#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) + +#include "hpm_crc_regs.h" +/* Address of CRC instances */ +/* CRC base address */ +#define HPM_CRC_BASE (0xF0080000UL) +/* CRC base pointer */ +#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) + +#include "hpm_tsns_regs.h" +/* Address of TSNS instances */ +/* TSNS base address */ +#define HPM_TSNS_BASE (0xF0090000UL) +/* TSNS base pointer */ +#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) + +#include "hpm_mbx_regs.h" +/* Address of MBX instances */ +/* MBX0A base address */ +#define HPM_MBX0A_BASE (0xF00A0000UL) +/* MBX0A base pointer */ +#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) +/* MBX0B base address */ +#define HPM_MBX0B_BASE (0xF00A4000UL) +/* MBX0B base pointer */ +#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) + +#include "hpm_ewdg_regs.h" +/* Address of EWDG instances */ +/* WDG0 base address */ +#define HPM_WDG0_BASE (0xF00B0000UL) +/* WDG0 base pointer */ +#define HPM_WDG0 ((EWDG_Type *) HPM_WDG0_BASE) +/* WDG1 base address */ +#define HPM_WDG1_BASE (0xF00B4000UL) +/* WDG1 base pointer */ +#define HPM_WDG1 ((EWDG_Type *) HPM_WDG1_BASE) +/* PWDG base address */ +#define HPM_PWDG_BASE (0xF4128000UL) +/* PWDG base pointer */ +#define HPM_PWDG ((EWDG_Type *) HPM_PWDG_BASE) + +#include "hpm_dmamux_regs.h" +/* Address of DMAMUX instances */ +/* DMAMUX base address */ +#define HPM_DMAMUX_BASE (0xF00C4000UL) +/* DMAMUX base pointer */ +#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) + +#include "hpm_dmav2_regs.h" +/* Address of DMAV2 instances */ +/* HDMA base address */ +#define HPM_HDMA_BASE (0xF00C8000UL) +/* HDMA base pointer */ +#define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE) + +#include "hpm_gpiom_regs.h" +/* Address of GPIOM instances */ +/* GPIOM base address */ +#define HPM_GPIOM_BASE (0xF00D8000UL) +/* GPIOM base pointer */ +#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) + +#include "hpm_mcan_regs.h" +/* Address of MCAN instances */ +/* MCAN0 base address */ +#define HPM_MCAN0_BASE (0xF0280000UL) +/* MCAN0 base pointer */ +#define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE) +/* MCAN1 base address */ +#define HPM_MCAN1_BASE (0xF0284000UL) +/* MCAN1 base pointer */ +#define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE) +/* MCAN2 base address */ +#define HPM_MCAN2_BASE (0xF0288000UL) +/* MCAN2 base pointer */ +#define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE) +/* MCAN3 base address */ +#define HPM_MCAN3_BASE (0xF028C000UL) +/* MCAN3 base pointer */ +#define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE) + +#include "hpm_ptpc_regs.h" +/* Address of PTPC instances */ +/* PTPC base address */ +#define HPM_PTPC_BASE (0xF02FC000UL) +/* PTPC base pointer */ +#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) + +#include "hpm_qeiv2_regs.h" +/* Address of QEIV2 instances */ +/* QEI0 base address */ +#define HPM_QEI0_BASE (0xF0300000UL) +/* QEI0 base pointer */ +#define HPM_QEI0 ((QEIV2_Type *) HPM_QEI0_BASE) +/* QEI1 base address */ +#define HPM_QEI1_BASE (0xF0304000UL) +/* QEI1 base pointer */ +#define HPM_QEI1 ((QEIV2_Type *) HPM_QEI1_BASE) + +#include "hpm_qeo_regs.h" +/* Address of QEO instances */ +/* QEO0 base address */ +#define HPM_QEO0_BASE (0xF0308000UL) +/* QEO0 base pointer */ +#define HPM_QEO0 ((QEO_Type *) HPM_QEO0_BASE) +/* QEO1 base address */ +#define HPM_QEO1_BASE (0xF030C000UL) +/* QEO1 base pointer */ +#define HPM_QEO1 ((QEO_Type *) HPM_QEO1_BASE) + +#include "hpm_mmc_regs.h" +/* Address of MMC instances */ +/* MMC0 base address */ +#define HPM_MMC0_BASE (0xF0310000UL) +/* MMC0 base pointer */ +#define HPM_MMC0 ((MMC_Type *) HPM_MMC0_BASE) +/* MMC1 base address */ +#define HPM_MMC1_BASE (0xF0314000UL) +/* MMC1 base pointer */ +#define HPM_MMC1 ((MMC_Type *) HPM_MMC1_BASE) + +#include "hpm_pwm_regs.h" +/* Address of PWM instances */ +/* PWM0 base address */ +#define HPM_PWM0_BASE (0xF0318000UL) +/* PWM0 base pointer */ +#define HPM_PWM0 ((PWM_Type *) HPM_PWM0_BASE) +/* PWM1 base address */ +#define HPM_PWM1_BASE (0xF031C000UL) +/* PWM1 base pointer */ +#define HPM_PWM1 ((PWM_Type *) HPM_PWM1_BASE) + +#include "hpm_rdc_regs.h" +/* Address of RDC instances */ +/* RDC base address */ +#define HPM_RDC_BASE (0xF0320000UL) +/* RDC base pointer */ +#define HPM_RDC ((RDC_Type *) HPM_RDC_BASE) + +#include "hpm_plb_regs.h" +/* Address of PLB instances */ +/* PLB base address */ +#define HPM_PLB_BASE (0xF0324000UL) +/* PLB base pointer */ +#define HPM_PLB ((PLB_Type *) HPM_PLB_BASE) + +#include "hpm_synt_regs.h" +/* Address of SYNT instances */ +/* SYNT base address */ +#define HPM_SYNT_BASE (0xF0328000UL) +/* SYNT base pointer */ +#define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) + +#include "hpm_sei_regs.h" +/* Address of SEI instances */ +/* SEI base address */ +#define HPM_SEI_BASE (0xF032C000UL) +/* SEI base pointer */ +#define HPM_SEI ((SEI_Type *) HPM_SEI_BASE) + +#include "hpm_trgm_regs.h" +/* Address of TRGM instances */ +/* TRGM0 base address */ +#define HPM_TRGM0_BASE (0xF033C000UL) +/* TRGM0 base pointer */ +#define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) + +#include "hpm_usb_regs.h" +/* Address of USB instances */ +/* USB0 base address */ +#define HPM_USB0_BASE (0xF300C000UL) +/* USB0 base pointer */ +#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) + +/* Address of ROMC instances */ +/* ROMC base address */ +#define HPM_ROMC_BASE (0xF3014000UL) + +#include "hpm_sdp_regs.h" +/* Address of SDP instances */ +/* SDP base address */ +#define HPM_SDP_BASE (0xF3040000UL) +/* SDP base pointer */ +#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) + +#include "hpm_sec_regs.h" +/* Address of SEC instances */ +/* SEC base address */ +#define HPM_SEC_BASE (0xF3044000UL) +/* SEC base pointer */ +#define HPM_SEC ((SEC_Type *) HPM_SEC_BASE) + +#include "hpm_mon_regs.h" +/* Address of MON instances */ +/* MON base address */ +#define HPM_MON_BASE (0xF3048000UL) +/* MON base pointer */ +#define HPM_MON ((MON_Type *) HPM_MON_BASE) + +#include "hpm_rng_regs.h" +/* Address of RNG instances */ +/* RNG base address */ +#define HPM_RNG_BASE (0xF304C000UL) +/* RNG base pointer */ +#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) + +#include "hpm_otp_regs.h" +/* Address of OTP instances */ +/* OTP base address */ +#define HPM_OTP_BASE (0xF3050000UL) +/* OTP base pointer */ +#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) + +#include "hpm_keym_regs.h" +/* Address of KEYM instances */ +/* KEYM base address */ +#define HPM_KEYM_BASE (0xF3054000UL) +/* KEYM base pointer */ +#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) + +#include "hpm_adc16_regs.h" +/* Address of ADC16 instances */ +/* ADC0 base address */ +#define HPM_ADC0_BASE (0xF3080000UL) +/* ADC0 base pointer */ +#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) +/* ADC1 base address */ +#define HPM_ADC1_BASE (0xF3084000UL) +/* ADC1 base pointer */ +#define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE) + +#include "hpm_dac_regs.h" +/* Address of DAC instances */ +/* DAC0 base address */ +#define HPM_DAC0_BASE (0xF3090000UL) +/* DAC0 base pointer */ +#define HPM_DAC0 ((DAC_Type *) HPM_DAC0_BASE) +/* DAC1 base address */ +#define HPM_DAC1_BASE (0xF3094000UL) +/* DAC1 base pointer */ +#define HPM_DAC1 ((DAC_Type *) HPM_DAC1_BASE) + +#include "hpm_opamp_regs.h" +/* Address of OPAMP instances */ +/* OPAMP0 base address */ +#define HPM_OPAMP0_BASE (0xF30A0000UL) +/* OPAMP0 base pointer */ +#define HPM_OPAMP0 ((OPAMP_Type *) HPM_OPAMP0_BASE) +/* OPAMP1 base address */ +#define HPM_OPAMP1_BASE (0xF30A4000UL) +/* OPAMP1 base pointer */ +#define HPM_OPAMP1 ((OPAMP_Type *) HPM_OPAMP1_BASE) + +#include "hpm_acmp_regs.h" +/* Address of ACMP instances */ +/* ACMP base address */ +#define HPM_ACMP_BASE (0xF30B0000UL) +/* ACMP base pointer */ +#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) + +#include "hpm_sysctl_regs.h" +/* Address of SYSCTL instances */ +/* SYSCTL base address */ +#define HPM_SYSCTL_BASE (0xF4000000UL) +/* SYSCTL base pointer */ +#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) + +#include "hpm_ioc_regs.h" +/* Address of IOC instances */ +/* IOC base address */ +#define HPM_IOC_BASE (0xF4040000UL) +/* IOC base pointer */ +#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) +/* PIOC base address */ +#define HPM_PIOC_BASE (0xF4118000UL) +/* PIOC base pointer */ +#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) + +#include "hpm_pllctlv2_regs.h" +/* Address of PLLCTLV2 instances */ +/* PLLCTLV2 base address */ +#define HPM_PLLCTLV2_BASE (0xF40C0000UL) +/* PLLCTLV2 base pointer */ +#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) + +#include "hpm_ppor_regs.h" +/* Address of PPOR instances */ +/* PPOR base address */ +#define HPM_PPOR_BASE (0xF4100000UL) +/* PPOR base pointer */ +#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) + +#include "hpm_pcfg_regs.h" +/* Address of PCFG instances */ +/* PCFG base address */ +#define HPM_PCFG_BASE (0xF4104000UL) +/* PCFG base pointer */ +#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) + +#include "hpm_pgpr_regs.h" +/* Address of PGPR instances */ +/* PGPR0 base address */ +#define HPM_PGPR0_BASE (0xF4110000UL) +/* PGPR0 base pointer */ +#define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE) +/* PGPR1 base address */ +#define HPM_PGPR1_BASE (0xF4114000UL) +/* PGPR1 base pointer */ +#define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE) + +#include "hpm_pdgo_regs.h" +/* Address of PDGO instances */ +/* PDGO base address */ +#define HPM_PDGO_BASE (0xF4134000UL) +/* PDGO base pointer */ +#define HPM_PDGO ((PDGO_Type *) HPM_PDGO_BASE) + + +#include "riscv/riscv_core.h" +#include "hpm_csr_regs.h" +#include "hpm_interrupt.h" +#include "hpm_misc.h" +#include "hpm_dmamux_src.h" +#include "hpm_trgmmux_src.h" +#include "hpm_iomux.h" +#include "hpm_pmic_iomux.h" +#endif /* HPM_SOC_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_soc_feature.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_soc_feature.h new file mode 100644 index 00000000..e16e9943 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_soc_feature.h @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SOC_FEATURE_H +#define HPM_SOC_FEATURE_H + +#include "hpm_soc.h" + +/* + * PLIC feature + */ +#define PLIC_SUPPORT_EDGE_TRIGGER (1) + +/* + * PMP/PMA Feature + */ +#define PMP_SUPPORT_PMA (0) + +/* + * I2C Section + */ +#define I2C_SOC_FIFO_SIZE (4U) +#define I2C_SOC_TRANSFER_COUNT_MAX (4096U) +#define I2C_SOC_SUPPORT_RESET (1U) + +/* + * PMIC Section + */ +#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) +#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) +#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) +#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) +#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) +#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) + +/* + * PLLCTL Section + */ +#define PLLCTL_SOC_PLL_MAX_COUNT (2U) +/* PLL reference clock in hz */ +#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) +/* only PLL1 and PLL2 have DIV0, DIV1 */ +#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) +#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) + + +/* + * PWM Section + */ +#define PWM_SOC_PWM_MAX_COUNT (8U) +#define PWM_SOC_CMP_MAX_COUNT (24U) +#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) + +/* + * DMA Section + */ +#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (DMA_TRANSFER_WIDTH_WORD) +#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (DMA_NUM_TRANSFER_PER_BURST_128T) +#define DMA_SOC_CHANNEL_NUM (32U) +#define DMA_SOC_MAX_COUNT (1U) +#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (DMAMUX_MUXCFG_HDMA_MUX0 + n) +#define DMA_SOC_HAS_IDLE_FLAG (1U) + +/* + * USB Section + */ +#define USB_SOC_MAX_COUNT (1U) + +#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) +#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) +#define USB_SOC_DCD_QTD_ALIGNMENT (32U) +#define USB_SOC_DCD_QHD_ALIGNMENT (64U) +#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (8U) +#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) +#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) + +#define USB_SOC_HCD_QTD_BUFFER_COUNT (5U) +#define USB_SOC_HCD_QTD_ALIGNMENT (32U) +#define USB_SOC_HCD_QHD_ALIGNMENT (32U) +#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) +#define USB_SOC_HCD_DATA_RAM_ADDRESS_ALIGNMENT (4096U) + + +/* + * ADC Section + */ +#define ADC_SOC_IP_VERSION (3U) +#define ADC_SOC_SEQ_MAX_LEN (16U) +#define ADC_SOC_SEQ_HCFG_EN (1U) +#define ADC_SOC_MAX_TRIG_CH_LEN (4U) +#define ADC_SOC_MAX_TRIG_CH_NUM (11U) +#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) +#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) +#define ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT (1U) +#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) +#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (16777216U) +#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) + +#define ADC16_SOC_PARAMS_LEN (34U) +#define ADC16_SOC_MAX_CH_NUM (15U) +#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) +#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) + +/* + * SYSCTL Section + */ +#define SYSCTL_SOC_CPU_GPR_COUNT (14U) +#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) + +/* + * PTPC Section + */ +#define PTPC_SOC_TIMER_MAX_COUNT (2U) + +/* + * SDP Section + */ +#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) +#define SDP_HAS_SM3_SUPPORT (1U) +#define SDP_HAS_SM4_SUPPORT (1U) + +/* + * SOC Privilege mdoe + */ +#define SOC_HAS_S_MODE (0U) + +/* + * DAC Section + */ +#define DAC_SOC_BUFF_ALIGNED_SIZE (32U) +#define DAC_SOC_MAX_DATA (4095U) +#define DAC_SOC_MAX_BUFF_COUNT (65536U) +#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL) + + +/* + * UART Section + */ +#define UART_SOC_FIFO_SIZE (16U) +#define UART_SOC_HAS_RXLINE_IDLE_DETECTION (1U) +#define UART_SOC_HAS_RXEN_CFG (1U) +#define UART_SOC_HAS_FINE_FIFO_THR (1U) +#define UART_SOC_HAS_FCCR_REG (1U) /* has FCRR register */ +#define UART_SOC_HAS_TXLINE_IDLE_DETECTION (1U) +#define UART_SOC_HAS_ADDR_MATCH (1U) +#define UART_SOC_HAS_IIR2_REG (1U) /* has IIR2 register */ +#define UART_SOC_HAS_TRIG_MODE (1U) + +/* + * SPI Section + */ +#define SPI_SOC_TRANSFER_COUNT_MAX (0xFFFFFFFFU) +#define SPI_SOC_FIFO_DEPTH (8U) +#define SPI_SOC_HAS_NEW_TRANS_COUNT (1U) +#define SPI_SOC_HAS_CS_SELECT (1U) +#define SPI_SOC_SUPPORT_DIRECTIO (1U) + +/* + * OTP Section + */ +#define OTP_SOC_UUID_IDX (88U) +#define OTP_SOC_UUID_LEN (16U) /* in bytes */ + +/* + * PWM Section + */ +#define PWM_SOC_HRPWM_SUPPORT (0U) +#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) +#define PWM_SOC_TIMER_RESET_SUPPORT (1U) + + +/* + * TRGM section + */ +#define TRGM_SOC_HAS_ADC_MATRIX_SEL (1U) +#define TRGM_SOC_HAS_DAC_MATRIX_SEL (1U) +#define TRGM_SOC_HAS_POS_MATRIX_SEL (1U) + +/* + * MCAN Section + */ +#define MCAN_SOC_MAX_COUNT (4U) +#define MCAN_SOC_MSG_BUF_IN_IP (0U) +#define MCAN_SOC_MSG_BUF_IN_AHB_RAM (1U) +#define CAN_SOC_MAX_COUNT MCAN_SOC_MAX_COUNT + +/* + * EWDG Section + */ +#define EWDG_SOC_CLK_DIV_VAL_MAX (5U) +#define EWDG_SOC_OVERTIME_REG_WIDTH (16U) +#define EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT (1) +#define EWDG_TIMEOUT_INTERRUPT_REQUIRE_EDGE_TRIGGER (1) + +/* + * Sync Timer + */ +#define SYNT_SOC_HAS_TIMESTAMP (1U) + +/* + * GPIO + */ +#define GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT (1U) + +/** + * OPAMP + */ +#define OPAMP_SOC_HAS_MAX_PRESET_CHN_NUM (7U) + + +#endif /* HPM_SOC_FEATURE_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_drv.c b/common/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_drv.c new file mode 100644 index 00000000..5119570e --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_drv.c @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_sysctl_drv.h" +#include "hpm_soc_feature.h" + +#define SYSCTL_RESOURCE_GROUP0 0 + +#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | (((cpu) & 1) << 24)) + +static inline bool sysctl_valid_cpu_index(uint8_t cpu) +{ + if (cpu != SYSCTL_CPU_CPU0) { + return false; + } + return true; +} + +hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint32_t *data, uint32_t size) +{ + uint32_t i; + if ((!sysctl_valid_cpu_index(cpu)) || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { + return status_invalid_argument; + } + for (i = 0; i < size; i++) { + *(data + i) = ptr->CPU[cpu].GPR[i]; + } + return status_success; +} + +static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + *(data + i) = ptr->CPU[cpu].GPR[start + i]; + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); +} + +hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) +{ + return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); +} + +static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, const uint32_t *data) +{ + uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); + if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || + (start + count) > size) { + return status_invalid_argument; + } + for (i = 0; i < count; i++) { + ptr->CPU[cpu].GPR[start + i] = *(data + i); + } + return status_success; +} + +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) +{ + hpm_stat_t stat = status_success; + uint16_t gpr_mask; + stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); + if (stat != status_success) { + return stat; + } + if (lock) { + gpr_mask = ((1 << count) - 1) << start; + sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); + } + return stat; +} + +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) +{ + config->mode = monitor_work_mode_record; + config->accuracy = monitor_accuracy_1khz; + config->reference = monitor_reference_24mhz; + config->divide_by = 1; + config->high_limit = 0; + config->low_limit = 0; + config->start_measure = true; + config->enable_output = false; + config->target = monitor_target_clk_top_cpu0; +} + +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t slice, monitor_config_t *config) +{ + ptr->MONITOR[slice].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); + + if (config->mode == monitor_work_mode_compare) { + ptr->MONITOR[slice].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); + ptr->MONITOR[slice].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); + } + + ptr->MONITOR[slice].CONTROL = (ptr->MONITOR[slice].CONTROL & + ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | + SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | + (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | + SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | + SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | + SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | + SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | + SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); +} + +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output) +{ + uint32_t frequency = 0; + monitor_config_t monitor = { 0 }; + sysctl_monitor_get_default_config(ptr, &monitor); + monitor.target = target; + monitor.enable_output = enable_output; + sysctl_monitor_init(ptr, monitor_index, &monitor); + if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { + frequency = sysctl_monitor_get_current_result(ptr, monitor_index); + } + return frequency; +} + +hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) +{ + if (!sysctl_valid_cpu_index(cpu)) { + return status_invalid_argument; + } + ptr->CPU[cpu].GPR[0] = entry; + ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); + return status_success; +} + +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) +{ + return sysctl_set_cpu_entry(ptr, 0, entry); +} + +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t linkable_resource, + bool enable) +{ + uint32_t index, offset; + if (linkable_resource < sysctl_resource_linkable_start) { + return status_invalid_argument; + } + + index = (linkable_resource - sysctl_resource_linkable_start) / 32; + offset = (linkable_resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); + break; + default: + return status_invalid_argument; + } + + return status_success; +} + +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t linkable_resource) +{ + uint32_t index, offset; + bool enable; + + index = (linkable_resource - sysctl_resource_linkable_start) / 32; + offset = (linkable_resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + default: + enable = false; + break; + } + + return enable; +} + +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) +{ + uint32_t value; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + value = ptr->GROUP0[index].VALUE; + break; + default: + value = 0; + break; + } + return value; +} + +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); +} + +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); +} + +hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint32_t divide_by) +{ + uint32_t node = (uint32_t) node_index; + if (node >= clock_node_adc_start) { + return status_invalid_argument; + } + + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); + while (sysctl_clock_target_is_busy(ptr, node)) { + } + return status_success; +} + +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node_index, clock_source_t source, uint32_t divide_by) +{ + uint32_t node = (uint32_t) node_index; + if (node >= clock_node_adc_start) { + return status_invalid_argument; + } + + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | + (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); + while (sysctl_clock_target_is_busy(ptr, node)) { + } + return status_success; +} + +hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, + clock_source_t source, + uint32_t cpu_div, + uint32_t ahb_sub_div) +{ + if (source >= clock_source_general_source_end) { + return status_invalid_argument; + } + + uint32_t origin_cpu_div = SYSCTL_CLOCK_CPU_DIV_GET(ptr->CLOCK_CPU[0]) + 1U; + if (origin_cpu_div == cpu_div) { + ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div) | SYSCTL_CLOCK_CPU_SUB0_DIV_SET(ahb_sub_div - 1); + while (sysctl_cpu_clock_any_is_busy(ptr)) { + } + } + ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div - 1) | SYSCTL_CLOCK_CPU_SUB0_DIV_SET(ahb_sub_div - 1); + + while (sysctl_cpu_clock_any_is_busy(ptr)) { + } + + return status_success; +} + +hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source) +{ + if (source >= clock_source_adc_clk_end) { + return status_invalid_argument; + } + uint32_t adc_index = (uint32_t) (node - clock_node_adc_start); + if (adc_index >= ARRAY_SIZE(ptr->ADCCLK)) { + return status_invalid_argument; + } + + ptr->ADCCLK[adc_index] = (ptr->ADCCLK[adc_index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); + + return status_success; +} + +hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source) +{ + if (source >= clock_source_dac_clk_end) { + return status_invalid_argument; + } + uint32_t dac_index = (uint32_t) (node - clock_node_dac_start); + if (dac_index >= ARRAY_SIZE(ptr->DACCLK)) { + return status_invalid_argument; + } + + ptr->DACCLK[dac_index] = (ptr->DACCLK[dac_index] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(source); + + return status_success; +} diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_drv.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_drv.h new file mode 100644 index 00000000..bdf2dd78 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_drv.h @@ -0,0 +1,1236 @@ +/** + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_SYSCTL_DRV_H +#define HPM_SYSCTL_DRV_H + +#include "hpm_common.h" +#include "hpm_sysctl_regs.h" + +/** + * + * @brief SYSCTL driver APIs + * @defgroup sysctl_interface SYSCTL driver APIs + * @ingroup io_interfaces + * @{ + */ + +/** + * @brief Retention domains + */typedef enum { + sysctl_retention_domain_sys = 0, + sysctl_retention_domain_cpu0 = 2, + + sysctl_retention_domain_xtal24m = 4, + sysctl_retention_domain_pll0 = 5, + sysctl_retention_domain_pll1 = 6, +} sysctl_retention_domain_t; + +/** + * @brief Clock presets + */ +typedef enum { + sysctl_preset_0 = 1 << 0, + sysctl_preset_1 = 1 << 1, + sysctl_preset_2 = 1 << 2, + sysctl_preset_3 = 1 << 3, +} sysctl_preset_t; + +/** + * @brief Reset domains + */ +typedef enum { + sysctl_reset_domain_soc = 0, + sysctl_reset_domain_cpu0, +} sysctl_reset_domain_t; + +/** + * @brief Resource + */ +typedef enum { + sysctl_resource_cpu0 = 0, + sysctl_resource_cpx0 = 1, + sysctl_resource_pow_cpu0 = 21, + sysctl_resource_rst_soc = 22, + sysctl_resource_rst_cpu0 = 23, + sysctl_resource_xtal = 32, + sysctl_resource_pll0 = 33, + sysctl_resource_clk0_pll0 = 34, + sysctl_resource_clk1_pll0 = 35, + sysctl_resource_clk2_pll0 = 36, + sysctl_resource_pll1 = 37, + sysctl_resource_clk0_pll1 = 38, + sysctl_resource_clk1_pll1 = 39, + sysctl_resource_clk2_pll1 = 40, + sysctl_resource_clk3_pll1 = 41, + sysctl_resource_pll0_ref = 42, + sysctl_resource_pll1_ref = 43, + sysctl_resource_clk_top_cpu0 = 64, + sysctl_resource_clk_top_mchtmr0 = 65, + sysctl_resource_clk_top_can0 = 66, + sysctl_resource_clk_top_can1 = 67, + sysctl_resource_clk_top_can2 = 68, + sysctl_resource_clk_top_can3 = 69, + sysctl_resource_clk_top_lin0 = 70, + sysctl_resource_clk_top_lin1 = 71, + sysctl_resource_clk_top_lin2 = 72, + sysctl_resource_clk_top_lin3 = 73, + sysctl_resource_clk_top_gptmr0 = 74, + sysctl_resource_clk_top_gptmr1 = 75, + sysctl_resource_clk_top_gptmr2 = 76, + sysctl_resource_clk_top_gptmr3 = 77, + sysctl_resource_clk_top_i2c0 = 78, + sysctl_resource_clk_top_i2c1 = 79, + sysctl_resource_clk_top_i2c2 = 80, + sysctl_resource_clk_top_i2c3 = 81, + sysctl_resource_clk_top_spi0 = 82, + sysctl_resource_clk_top_spi1 = 83, + sysctl_resource_clk_top_spi2 = 84, + sysctl_resource_clk_top_spi3 = 85, + sysctl_resource_clk_top_uart0 = 86, + sysctl_resource_clk_top_uart1 = 87, + sysctl_resource_clk_top_uart2 = 88, + sysctl_resource_clk_top_uart3 = 89, + sysctl_resource_clk_top_uart4 = 90, + sysctl_resource_clk_top_uart5 = 91, + sysctl_resource_clk_top_uart6 = 92, + sysctl_resource_clk_top_uart7 = 93, + sysctl_resource_clk_top_xip0 = 94, + sysctl_resource_clk_top_ana0 = 95, + sysctl_resource_clk_top_ana1 = 96, + sysctl_resource_clk_top_ana2 = 97, + sysctl_resource_clk_top_ana3 = 98, + sysctl_resource_clk_top_ref0 = 99, + sysctl_resource_clk_top_ref1 = 100, + sysctl_resource_clk_top_adc0 = 101, + sysctl_resource_clk_top_adc1 = 102, + sysctl_resource_clk_top_dac0 = 103, + sysctl_resource_clk_top_dac1 = 104, + + sysctl_resource_linkable_start = 256, + sysctl_resource_ahb0 = 256, + sysctl_resource_lmm0 = 257, + sysctl_resource_mchtmr0 = 258, + sysctl_resource_rom0 = 259, + sysctl_resource_can0 = 260, + sysctl_resource_can1 = 261, + sysctl_resource_can2 = 262, + sysctl_resource_can3 = 263, + sysctl_resource_ptpc = 264, + sysctl_resource_lin0 = 265, + sysctl_resource_lin1 = 266, + sysctl_resource_lin2 = 267, + sysctl_resource_lin3 = 268, + sysctl_resource_gptmr0 = 269, + sysctl_resource_gptmr1 = 270, + sysctl_resource_gptmr2 = 271, + sysctl_resource_gptmr3 = 272, + sysctl_resource_i2c0 = 273, + sysctl_resource_i2c1 = 274, + sysctl_resource_i2c2 = 275, + sysctl_resource_i2c3 = 276, + sysctl_resource_spi0 = 277, + sysctl_resource_spi1 = 278, + sysctl_resource_spi2 = 279, + sysctl_resource_spi3 = 280, + sysctl_resource_uart0 = 281, + sysctl_resource_uart1 = 282, + sysctl_resource_uart2 = 283, + sysctl_resource_uart3 = 284, + sysctl_resource_uart4 = 285, + sysctl_resource_uart5 = 286, + sysctl_resource_uart6 = 287, + sysctl_resource_uart7 = 288, + sysctl_resource_wdg0 = 289, + sysctl_resource_wdg1 = 290, + sysctl_resource_mbx0 = 291, + sysctl_resource_tsns = 292, + sysctl_resource_crc0 = 293, + sysctl_resource_adc0 = 294, + sysctl_resource_adc1 = 295, + sysctl_resource_dac0 = 296, + sysctl_resource_dac1 = 297, + sysctl_resource_acmp = 298, + sysctl_resource_opa0 = 299, + sysctl_resource_opa1 = 300, + sysctl_resource_mot0 = 301, + sysctl_resource_rng0 = 302, + sysctl_resource_sdp0 = 303, + sysctl_resource_kman = 304, + sysctl_resource_gpio = 305, + sysctl_resource_hdma = 306, + sysctl_resource_xpi0 = 307, + sysctl_resource_usb0 = 308, + sysctl_resource_ref0 = 309, + sysctl_resource_ref1 = 310, + sysctl_resource_linkable_end, + sysctl_resource_end = sysctl_resource_linkable_end, +} sysctl_resource_t; + +/** + * @brief Resource modes + */ +typedef enum { + sysctl_resource_mode_auto = 0, /*!< Resource clock is automatically managed by system request */ + sysctl_resource_mode_force_on, /*!< Force the resource clock on */ + sysctl_resource_mode_force_off, /*!< Force the resource clock off */ +} sysctl_resource_mode_t; + +/** + * @brief Clock nodes + */ +typedef enum { + clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0, + clock_node_can0 = SYSCTL_CLOCK_CLK_TOP_CAN0, + clock_node_can1 = SYSCTL_CLOCK_CLK_TOP_CAN1, + clock_node_can2 = SYSCTL_CLOCK_CLK_TOP_CAN2, + clock_node_can3 = SYSCTL_CLOCK_CLK_TOP_CAN3, + clock_node_lin0 = SYSCTL_CLOCK_CLK_TOP_LIN0, + clock_node_lin1 = SYSCTL_CLOCK_CLK_TOP_LIN1, + clock_node_lin2 = SYSCTL_CLOCK_CLK_TOP_LIN2, + clock_node_lin3 = SYSCTL_CLOCK_CLK_TOP_LIN3, + clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0, + clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1, + clock_node_gptmr2 = SYSCTL_CLOCK_CLK_TOP_TMR2, + clock_node_gptmr3 = SYSCTL_CLOCK_CLK_TOP_TMR3, + clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0, + clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1, + clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2, + clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3, + clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0, + clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1, + clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2, + clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3, + clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0, + clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1, + clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2, + clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3, + clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4, + clock_node_uart5 = SYSCTL_CLOCK_CLK_TOP_URT5, + clock_node_uart6 = SYSCTL_CLOCK_CLK_TOP_URT6, + clock_node_uart7 = SYSCTL_CLOCK_CLK_TOP_URT7, + clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0, + clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0, + clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1, + clock_node_ana2 = SYSCTL_CLOCK_CLK_TOP_ANA2, + clock_node_ana3 = SYSCTL_CLOCK_CLK_TOP_ANA3, + clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0, + clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1, + + clock_node_adc_start, + clock_node_adc0 = clock_node_adc_start, + clock_node_adc1, + + clock_node_dac_start, + clock_node_dac0 = clock_node_dac_start, + clock_node_dac1, + clock_node_end, + + clock_node_core_start = 0xfc, + clock_node_cpu0 = clock_node_core_start, + clock_node_axi, + clock_node_ahb, +} clock_node_t; + +/** + * @brief General clock sources + */ +typedef enum { + clock_source_osc0_clk0 = 0, + clock_source_pll0_clk0 = 1, + clock_source_pll0_clk1 = 2, + clock_source_pll0_clk2 = 3, + clock_source_pll1_clk0 = 4, + clock_source_pll1_clk1 = 5, + clock_source_pll1_clk2 = 6, + clock_source_pll1_clk3 = 7, + clock_source_general_source_end, +} clock_source_t; + +/** + * @brief ADC/I2S clock sources + */ +typedef enum { + clock_source_adc_ana_clock = 0, + clock_source_adc_ahb_clock = 1, + clock_source_adc_clk_end, +} clock_source_adc_t; + +/** + * @brief DAC clock sources + */ +typedef enum { + clock_source_dac_ana_clock = 0, + clock_source_dac_ahb_clock = 1, + clock_source_dac_clk_end, +} clock_source_dac_t; + +/** + * @brief CPU low power mode + */ +typedef enum { + cpu_lp_mode_gate_cpu_clock = 0, + cpu_lp_mode_trigger_system_lp = 0x1, + cpu_lp_mode_ungate_cpu_clock = 0x2, +} cpu_lp_mode_t; + +/** + * @brief Monitor targets + */ +typedef enum { + monitor_target_clk_32k = 1, + monitor_target_clk_irc24m = 2, + monitor_target_clk_xtal_24m = 3, + monitor_target_clk_usb0_phy = 4, + monitor_target_clk0_osc0 = 20, + monitor_target_clk0_pll0 = 21, + monitor_target_clk0_pll1 = 22, + monitor_target_clk0_pll2 = 23, + monitor_target_clk1_pll0 = 24, + monitor_target_clk1_pll1 = 25, + monitor_target_clk1_pll2 = 26, + monitor_target_clk1_pll3 = 27, + monitor_target_clk_top_cpu0 = 128, + monitor_target_clk_top_mchtmr0 = 129, + monitor_target_clk_top_can0 = 130, + monitor_target_clk_top_can1 = 131, + monitor_target_clk_top_can2 = 132, + monitor_target_clk_top_can3 = 133, + monitor_target_clk_top_lin0 = 134, + monitor_target_clk_top_lin1 = 135, + monitor_target_clk_top_lin2 = 136, + monitor_target_clk_top_lin3 = 137, + monitor_target_clk_top_gptmr0 = 138, + monitor_target_clk_top_gptmr1 = 139, + monitor_target_clk_top_gptmr2 = 140, + monitor_target_clk_top_gptmr3 = 141, + monitor_target_clk_top_i2c0 = 142, + monitor_target_clk_top_i2c1 = 143, + monitor_target_clk_top_i2c2 = 144, + monitor_target_clk_top_i2c3 = 145, + monitor_target_clk_top_spi0 = 146, + monitor_target_clk_top_spi1 = 147, + monitor_target_clk_top_spi2 = 148, + monitor_target_clk_top_spi3 = 149, + monitor_target_clk_top_uart0 = 150, + monitor_target_clk_top_uart1 = 151, + monitor_target_clk_top_uart2 = 152, + monitor_target_clk_top_uart3 = 153, + monitor_target_clk_top_uart4 = 154, + monitor_target_clk_top_uart5 = 155, + monitor_target_clk_top_uart6 = 156, + monitor_target_clk_top_uart7 = 157, + monitor_target_clk_top_xpi0 = 158, + monitor_target_clk_top_ana0 = 159, + monitor_target_clk_top_ana1 = 160, + monitor_target_clk_top_ana2 = 161, + monitor_target_clk_top_ana3 = 162, + monitor_target_clk_top_ref0 = 163, + monitor_target_clk_top_ref1 = 164, +} monitor_target_t; + +/** + * @brief Monitor work mode + */ +typedef enum { + monitor_work_mode_compare = 0, + monitor_work_mode_record = 1, +} monitor_work_mode_t; + +/** + * @brief Monitor accuracy + */ +typedef enum { + monitor_accuracy_1khz = 0, + monitor_accuracy_1hz = 1, +} monitor_accuracy_t; + +/** + * @brief Monitor reference clock source + */ +typedef enum { + monitor_reference_32khz = 0, + monitor_reference_24mhz = 1, +} monitor_reference_t; + +typedef enum { + cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, + cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, + cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, + cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, +} cpu_event_flag_mask_t; + +/** + * @brief Monitor config + */ +typedef struct monitor_config { + uint8_t divide_by; /**< Divider to be used for OBS output to pads */ + monitor_work_mode_t mode; /**< Monitor work mode */ + monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ + monitor_reference_t reference; /**< Monitor reference clock source */ + monitor_target_t target; /**< Monitor target */ + bool start_measure; /**< Start flag */ + bool enable_output; /**< Enable output to pads if true */ + uint32_t high_limit; /**< Maximum frequency at compare mode */ + uint32_t low_limit; /**< Minimum frequency at compare mode */ +} monitor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Check if monitor result is valid + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * + * @return true if it is valid + */ +static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); +} + +/** + * @brief Get target monitor instance result + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return value of monitor result measured + */ +static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) +{ + while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { + } + return ptr->MONITOR[monitor_index].CURRENT; +} + +/** + * @brief Set work mode for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record + */ +static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) +{ + ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | + (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); +} + +/** + * @brief Set minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit measurement high limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); + return status_success; +} + +/** + * @brief Set frequency limit for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] limit_high measurement high limit + * @param[in] limit_low measurement low limit + */ +static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, + uint8_t monitor_index, + uint32_t limit_high, + uint32_t limit_low) +{ + if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { + return status_invalid_argument; + } + ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); + ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); + return status_success; +} + +/** + * @brief Get maximum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current high limit value + */ +static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); +} + +/** + * @brief Get minimum frequency for target monitor instance + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @return current low limit value + */ +static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) +{ + return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); +} + +/** + * @brief Measure specific target frequency + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index specific monitor instance to be used + * @param[in] target monitor target to be measured + * @param[in] enable_output enable clock obs output + * @return frequency of monitor target measured + */ +uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, + uint8_t monitor_index, + monitor_target_t target, + bool enable_output); + +/** + * @brief Link current CPU core its own group + * + * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; +} + +/** + * @brief Unlink current CPU core with its own group + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index to enable its own affiliated group + */ +static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; +} + +/** + * @brief Check if any resource is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any resource is busy + */ +static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; +} + +/** + * @brief Check if specific target is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return true if target resource is busy + */ +static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) +{ + return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; +} + +/** + * @brief Set target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @param[in] mode target resource mode + */ +static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource, + sysctl_resource_mode_t mode) +{ + ptr->RESOURCE[resource] = + (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | + SYSCTL_RESOURCE_MODE_SET(mode); +} + +/** + * @brief Get target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return target resource mode + */ +static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource) +{ + return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); +} + +/** + * @brief Disable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].CLEAR = mask; +} + +/** + * @brief Disable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to clear + */ +static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) +{ + ptr->RETENTION[cpu_index].SET = mask; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); +} + +/** + * @brief Enable resource retention when CPU1 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mask bit mask to set + */ +static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) +{ + sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); +} + +/** + * @brief Enable resource retention when specific CPU enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index cpu index + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t value) +{ + ptr->RETENTION[cpu_index].VALUE = value; +} + +/** + * @brief Enable resource retention when CPU0 enters stop mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] value value to be set + */ +static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) +{ + sysctl_set_cpu_lp_retention(ptr, 0, value); +} + +/** + * @brief Retain target domain for specific CPU + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, + uint8_t cpu_index, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + uint8_t set_mask = 0x1; + if (domain < sysctl_retention_domain_xtal24m) { + set_mask = retain_mem ? 0x3 : 0x1; + } + ptr->RETENTION[cpu_index].SET = (set_mask << domain); +} + +/** + * @brief Retain target domain for specific CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain power to be retained + * @param[in] retain_mem set true to retain memory/register of target domain + */ +static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, + sysctl_retention_domain_t domain, + bool retain_mem) +{ + sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); +} + +/** + * @brief Check if cpu clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_cpu_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK_CPU[0] & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK; +} + +/** + * @brief Check if any clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @return true if any clock is busy + */ +static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) +{ + return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; +} + +/** + * @brief Check if target clock is busy + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] clock target clock + * @return true if target clock is busy + */ +static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, uint32_t clock) +{ + return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; +} + +/** + * @brief Set clock preset + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] preset preset + */ +static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) +{ + ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); +} + +/** + * @brief Check if target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken wakeup reset + */ +static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain wakeup status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + * @return true if target domain was taken reset + */ +static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; +} + +/** + * @brief Clear target reset domain for all reset status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] domain target domain to be checked + */ +static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) +{ + ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; +} + +/** + * @brief Get target CPU wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; +} + +/** + * @brief Get target CPU0 wakeup source status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @return wakeup source status mask + */ +static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) +{ + return sysctl_get_wakeup_source_status(ptr, 0, status_index); +} + +/** + * @brief Check wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t status_index, + uint32_t mask) +{ + return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; +} + +/** + * @brief Check CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] status_index wakeup status index 0 - 7 + * @param[in] mask expected status mask + * @return wakeup status according to given bit mask + */ +static inline uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, + uint8_t status_index, + uint32_t mask) +{ + return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); +} + +/** + * @brief Enable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Enable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; +} + +/** + * @brief Disable wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t cpu_index, + uint8_t enable_index, + uint32_t mask) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; +} + +/** + * @brief Disable CPU0 wakeup source status with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] enable_index wakeup enable index 0 - 7 + * @param[in] mask expected status mask + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, + uint8_t enable_index, + uint32_t mask) +{ + sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); +} + +/** + * @brief Disable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); +} + +/** + * @brief Disable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be disabled as wakeup source + */ +static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, + uint16_t irq_num) +{ + sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); +} + + +/** + * @brief Enable wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) +{ + ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); +} + +/** + * @brief Enable CPU0 wakeup source status with irq + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] irq_num irq number to be set as wakeup source + */ +static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) +{ + sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); +} + +/** + * @brief Lock CPU gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t gpr_mask) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); +} + + +/** + * @brief Lock CPU0 gpr with mask + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] gpr_mask bit mask of gpr registers to be locked + */ +static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) +{ + sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); +} + +/** + * @brief Lock CPU lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + */ +static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; +} + +/** + * @brief Lock CPU0 lock + * + * @param[in] ptr SYSCTL_Type base address + */ +static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) +{ + sysctl_cpu_lock(ptr, 0); +} + +/** + * @brief Set CPU low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) +{ + ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); +} + +/** + * @brief Set CPU0 low power mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] mode target mode to set + */ +static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) +{ + sysctl_set_cpu_lp_mode(ptr, 0, mode); +} + +/** + * @brief Clear CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) +{ + ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); +} + +/** + * @brief Clear CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] flags flag mask to be cleared + */ +static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) +{ + sysctl_clear_cpu_flags(ptr, 0, flags); +} + +/** + * @brief Get CPU event flags + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] cpu_index CPU index + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) +{ + return ptr->CPU[cpu_index].LP & (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); +} + +/** + * @brief Get CPU0 event flags + * + * @param[in] ptr SYSCTL_Type base address + * @retval event flag mask + */ +static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) +{ + return sysctl_get_cpu_flags(ptr, 0); +} + +/** + * @brief Config lock + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @param[in] divide_by clock frequency divider + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); + +/** + * @brief Configure CPU domain clock + * @param ptr SYSCTL base address + * @param source clock source to be used + * @param cpu_div CPU divider + * @param ahb_sub_div AHB BUS divider based on divided CPU clock + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, clock_source_t source, uint32_t cpu_div, uint32_t ahb_sub_div); + +/** + * @brief Set ADC clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source); + + +/** + * @brief Set DAC clock mux + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] node clock node to be configured + * @param[in] source clock source to be used + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source); + + +/** + * @brief Enable group resource + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be modified + * @param[in] resource target resource to be added/removed from group + * @param[in] enable set true to add resource, remove otherwise + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); + +/** + * @brief Check group resource enable status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be checked + * @param[in] resource target resource to be checked from group + * @return enable true if resource enable, false if resource disable + */ +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t linkable_resource); + +/** + * @brief Get group resource value + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be getted + * @param[in] index target group index + * @return group index value + */ +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); + +/** + * @brief Add resource to CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource resource to be added to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Remove resource from CPU0 + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource Resource to be removed to CPU0 + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); + +/** + * @brief Get default monitor config + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); + +/** + * @brief Initialize Monitor + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] monitor_index Monitor instance to be initialized + * @param[in] config Monitor config structure pointer + */ +void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); + +/** + * @brief Save data to GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[in] data Pointer to data buffer + * @param[in] lock Set true to lock written GPR registers after setting + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); + +/** + * @brief Get data saved from GPU0 GPR starting from given index + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] start Starting GPR index + * @param[in] count Number of GPR registers to set + * @param[out] data Pointer of buffer to save data + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); + +/** + * @brief Set entry point on CPU0 wakeup + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] entry Entry address for CPU0 on its wakeup + * @return status_success if everything is okay + */ +hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); + + +#ifdef __cplusplus +} +#endif +/** + * @} + */ +#endif /* HPM_SYSCTL_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_regs.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_regs.h new file mode 100644 index 00000000..85c49266 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_sysctl_regs.h @@ -0,0 +1,1283 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SYSCTL_H +#define HPM_SYSCTL_H + +typedef struct { + __RW uint32_t RESOURCE[311]; /* 0x0 - 0x4D8: Resource control register for cpu0_core */ + __R uint8_t RESERVED0[804]; /* 0x4DC - 0x7FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x800: Group setting */ + __RW uint32_t SET; /* 0x804: Group setting */ + __RW uint32_t CLEAR; /* 0x808: Group setting */ + __RW uint32_t TOGGLE; /* 0x80C: Group setting */ + } GROUP0[2]; + __R uint8_t RESERVED1[224]; /* 0x820 - 0x8FF: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ + __RW uint32_t SET; /* 0x904: Affiliate of Group */ + __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ + __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ + } AFFILIATE[1]; + __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */ + struct { + __RW uint32_t VALUE; /* 0x920: Retention Contol */ + __RW uint32_t SET; /* 0x924: Retention Contol */ + __RW uint32_t CLEAR; /* 0x928: Retention Contol */ + __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */ + } RETENTION[1]; + __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */ + struct { + __RW uint32_t STATUS; /* 0x1000: Power Setting */ + __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ + __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ + __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ + __RW uint32_t RET_WAIT; /* 0x1010: Power Setting */ + } POWER[1]; + __R uint8_t RESERVED4[1004]; /* 0x1014 - 0x13FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ + __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ + __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ + __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ + } RESET[2]; + __R uint8_t RESERVED5[992]; /* 0x1420 - 0x17FF: Reserved */ + __RW uint32_t CLOCK_CPU[1]; /* 0x1800: Clock setting */ + __RW uint32_t CLOCK[36]; /* 0x1804 - 0x1890: Clock setting */ + __R uint8_t RESERVED6[876]; /* 0x1894 - 0x1BFF: Reserved */ + __RW uint32_t ADCCLK[2]; /* 0x1C00 - 0x1C04: Clock setting */ + __RW uint32_t DACCLK[2]; /* 0x1C08 - 0x1C0C: Clock setting */ + __R uint8_t RESERVED7[1008]; /* 0x1C10 - 0x1FFF: Reserved */ + __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ + __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ + struct { + __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ + __R uint32_t CURRENT; /* 0x2404: Clock measure result */ + __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ + __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ + __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ + } MONITOR[4]; + __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ + struct { + __RW uint32_t LP; /* 0x2800: CPU0 LP control */ + __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ + __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ + __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ + __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ + __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ + __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ + } CPU[1]; +} SYSCTL_Type; + + +/* Bitfield definition for register array: RESOURCE */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any nodes + * 1: any of nodes is changing status + */ +#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) +#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: no change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) +#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) + +/* + * MODE (RW) + * + * resource work mode + * 0:auto turn on and off as system required(recommended) + * 1:always on + * 2:always off + * 3:reserved + */ +#define SYSCTL_RESOURCE_MODE_MASK (0x3U) +#define SYSCTL_RESOURCE_MODE_SHIFT (0U) +#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) +#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: VALUE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: peripheral is not needed + * 1: periphera is needed + */ +#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) +#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: SET */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: add periphera into this group，periphera is needed + */ +#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) +#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: CLEAR */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: delete periphera in this group，periphera is not needed + */ +#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) +#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array GROUP0: TOGGLE */ +/* + * LINK (RW) + * + * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral + * 0: no effect + * 1: toggle the result that whether periphera is needed before + */ +#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) +#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) +#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: VALUE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * bit0: cpu0 depends on group0 + * bit1: cpu0 depends on group1 + * bit2: cpu0 depends on group2 + * bit3: cpu0 depends on group3 + */ +#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) +#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: SET */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0，each bit represents a group + * 0: no effect + * 1: the group is assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) +#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: the group is not assigned to CPU0 + */ +#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) +#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ +/* + * LINK (RW) + * + * Affiliate groups of cpu0, each bit represents a group + * 0: no effect + * 1: toggle the result that whether the group is assigned to CPU0 before + */ +#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) +#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: VALUE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * bit00: soc_mem is kept on while cpu0 stop + * bit01: soc_ctx is kept on while cpu0 stop + * bit02: cpu0_mem is kept on while cpu0 stop + * bit03: cpu0_ctx is kept on while cpu0 stop + * bit04: xtal_hold is kept on while cpu0 stop + * bit05: pll0_hold is kept on while cpu0 stop + * bit06: pll1_hold is kept on while cpu0 stop + */ +#define SYSCTL_RETENTION_VALUE_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) +#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: SET */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: keep + */ +#define SYSCTL_RETENTION_SET_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) +#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: CLEAR */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: no keep + */ +#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) +#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) + +/* Bitfield definition for register of struct array RETENTION: TOGGLE */ +/* + * LINK (RW) + * + * retention setting while CPU0 enter stop mode, each bit represents a resource + * 0: no effect + * 1: toggle the result that whether the resource is kept on while CPU0 stop before + */ +#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x7FFFU) +#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) +#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) +#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) + +/* Bitfield definition for register of struct array POWER: STATUS */ +/* + * FLAG (RW) + * + * flag represents power cycle happened from last clear of this bit + * 0: power domain did not edurance power cycle since last clear of this bit + * 1: power domain enduranced power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) +#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) +#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) +#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup power cycle happened from last clear of this bit + * 0: power domain did not edurance wakeup power cycle since last clear of this bit + * 1: power domain enduranced wakeup power cycle since last clear of this bit + */ +#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) +#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) + +/* + * MEM_RET_N (RO) + * + * memory info retention control signal + * 0: memory enter retention mode + * 1: memory exit retention mode + */ +#define SYSCTL_POWER_STATUS_MEM_RET_N_MASK (0x20000UL) +#define SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT (17U) +#define SYSCTL_POWER_STATUS_MEM_RET_N_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_N_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT) + +/* + * MEM_RET_P (RO) + * + * memory info retention control signal + * 0: memory not enterexitretention mode + * 1: memory enter retention mode + */ +#define SYSCTL_POWER_STATUS_MEM_RET_P_MASK (0x10000UL) +#define SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT (16U) +#define SYSCTL_POWER_STATUS_MEM_RET_P_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_P_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT) + +/* + * LF_DISABLE (RO) + * + * low fanout power switch disable + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) +#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) + +/* + * LF_ACK (RO) + * + * low fanout power switch feedback + * 0: low fanout power switches are turned on + * 1: low fanout power switches are truned off + */ +#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) +#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) +#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) + +/* Bitfield definition for register of struct array POWER: LF_WAIT */ +/* + * WAIT (RW) + * + * wait time for low fan out power switch turn on, default value is 255 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array POWER: OFF_WAIT */ +/* + * WAIT (RW) + * + * wait time for power switch turn off, default value is 15 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) +#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array POWER: RET_WAIT */ +/* + * WAIT (RW) + * + * wait time for memory retention mode transition, default value is 15 + * 0: 0 clock cycle + * 1: 1 clock cycles + * . . . + * clock cycles count on 24MHz + */ +#define SYSCTL_POWER_RET_WAIT_WAIT_MASK (0xFFFFFUL) +#define SYSCTL_POWER_RET_WAIT_WAIT_SHIFT (0U) +#define SYSCTL_POWER_RET_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_RET_WAIT_WAIT_SHIFT) & SYSCTL_POWER_RET_WAIT_WAIT_MASK) +#define SYSCTL_POWER_RET_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_RET_WAIT_WAIT_MASK) >> SYSCTL_POWER_RET_WAIT_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONTROL */ +/* + * FLAG (RW) + * + * flag represents reset happened from last clear of this bit + * 0: domain did not edurance reset cycle since last clear of this bit + * 1: domain enduranced reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) +#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) + +/* + * FLAG_WAKE (RW) + * + * flag represents wakeup reset happened from last clear of this bit + * 0: domain did not edurance wakeup reset cycle since last clear of this bit + * 1: domain enduranced wakeup reset cycle since last clear of this bit + */ +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) + +/* + * HOLD (RW) + * + * perform reset and hold in reset, until ths bit cleared by software + * 0: reset is released for function + * 1: reset is assert and hold + */ +#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) +#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) +#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) +#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) + +/* + * RESET (RW) + * + * perform reset and release imediately + * 0: reset is released + * 1 reset is asserted and will release automaticly + */ +#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) +#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) +#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) +#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) + +/* Bitfield definition for register of struct array RESET: CONFIG */ +/* + * PRE_WAIT (RW) + * + * wait cycle numbers before assert reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) + +/* + * RSTCLK_NUM (RW) + * + * reset clock number(must be even number) + * 0: 0 cycle + * 1: 0 cycles + * 2: 2 cycles + * 3: 2 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) + +/* + * POST_WAIT (RW) + * + * time guard band for reset release + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) +#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) + +/* Bitfield definition for register of struct array RESET: COUNTER */ +/* + * COUNTER (RW) + * + * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset + * 0: wait 0 cycle + * 1: wait 1 cycles + * . . . + * Note, clock cycle is base on 24M + */ +#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) +#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) +#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) +#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) + +/* Bitfield definition for register array: CLOCK_CPU */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_CPU_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_CPU_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK) >> SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_CPU_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_CPU_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_LOC_BUSY_MASK) >> SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_CPU_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_CPU_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_CPU_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) +#define SYSCTL_CLOCK_CPU_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) >> SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) + +/* + * SUB0_DIV (RW) + * + * ahb bus divider, the bus clock is generated by cpu_clock/div + * 0: divider by 1 + * 1: divider by 2 + * … + */ +#define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xF0000UL) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16U) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll0_clk1 + * 3:pll0_clk2 + * 4:pll1_clk0 + * 5:pll1_clk1 + * 6:pll1_clk2 + * 7:pll1_clk3 + */ +#define SYSCTL_CLOCK_CPU_MUX_MASK (0x700U) +#define SYSCTL_CLOCK_CPU_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_CPU_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_MUX_SHIFT) & SYSCTL_CLOCK_CPU_MUX_MASK) +#define SYSCTL_CLOCK_CPU_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_MUX_MASK) >> SYSCTL_CLOCK_CPU_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_CPU_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_CPU_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_CPU_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_DIV_SHIFT) & SYSCTL_CLOCK_CPU_DIV_MASK) +#define SYSCTL_CLOCK_CPU_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_DIV_MASK) >> SYSCTL_CLOCK_CPU_DIV_SHIFT) + +/* Bitfield definition for register array: CLOCK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) +#define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) +#define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux in clock component + * 0:osc0_clk0 + * 1:pll0_clk0 + * 2:pll0_clk1 + * 3:pll0_clk2 + * 4:pll1_clk0 + * 5:pll1_clk1 + * 6:pll1_clk2 + * 7:pll1_clk3 + */ +#define SYSCTL_CLOCK_MUX_MASK (0x700U) +#define SYSCTL_CLOCK_MUX_SHIFT (8U) +#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) +#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) + +/* + * DIV (RW) + * + * clock divider + * 0: divider by 1 + * 1: divider by 2 + * 2: divider by 3 + * . . . + * 255: divider by 256 + */ +#define SYSCTL_CLOCK_DIV_MASK (0xFFU) +#define SYSCTL_CLOCK_DIV_SHIFT (0U) +#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) +#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) + +/* Bitfield definition for register array: ADCCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) +#define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ahb0 clock N + * 1: ana clock + */ +#define SYSCTL_ADCCLK_MUX_MASK (0x100U) +#define SYSCTL_ADCCLK_MUX_SHIFT (8U) +#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) +#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) + +/* Bitfield definition for register array: DACCLK */ +/* + * GLB_BUSY (RO) + * + * global busy + * 0: no changes pending to any clock + * 1: any of nodes is changing status + */ +#define SYSCTL_DACCLK_GLB_BUSY_MASK (0x80000000UL) +#define SYSCTL_DACCLK_GLB_BUSY_SHIFT (31U) +#define SYSCTL_DACCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_GLB_BUSY_MASK) >> SYSCTL_DACCLK_GLB_BUSY_SHIFT) + +/* + * LOC_BUSY (RO) + * + * local busy + * 0: a change is pending for current node + * 1: current node is changing status + */ +#define SYSCTL_DACCLK_LOC_BUSY_MASK (0x40000000UL) +#define SYSCTL_DACCLK_LOC_BUSY_SHIFT (30U) +#define SYSCTL_DACCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_LOC_BUSY_MASK) >> SYSCTL_DACCLK_LOC_BUSY_SHIFT) + +/* + * PRESERVE (RW) + * + * preserve function against global select + * 0: select global clock setting + * 1: not select global clock setting + */ +#define SYSCTL_DACCLK_PRESERVE_MASK (0x10000000UL) +#define SYSCTL_DACCLK_PRESERVE_SHIFT (28U) +#define SYSCTL_DACCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_PRESERVE_SHIFT) & SYSCTL_DACCLK_PRESERVE_MASK) +#define SYSCTL_DACCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_PRESERVE_MASK) >> SYSCTL_DACCLK_PRESERVE_SHIFT) + +/* + * MUX (RW) + * + * current mux + * 0: ahb0 clock N + * 1: ana clock + */ +#define SYSCTL_DACCLK_MUX_MASK (0x100U) +#define SYSCTL_DACCLK_MUX_SHIFT (8U) +#define SYSCTL_DACCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_MUX_SHIFT) & SYSCTL_DACCLK_MUX_MASK) +#define SYSCTL_DACCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_MUX_MASK) >> SYSCTL_DACCLK_MUX_SHIFT) + +/* Bitfield definition for register: GLOBAL00 */ +/* + * MUX (RW) + * + * global clock override request + * bit0: override to preset0 + * bit1: override to preset1 + * bit2: override to preset2 + * bit3: override to preset3 + * bit4: override to preset4 + * bit5: override to preset5 + * bit6: override to preset6 + * bit7: override to preset7 + */ +#define SYSCTL_GLOBAL00_MUX_MASK (0xFFU) +#define SYSCTL_GLOBAL00_MUX_SHIFT (0U) +#define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) +#define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CONTROL */ +/* + * VALID (RW) + * + * result is ready for read + * 0: not ready + * 1: result is ready + */ +#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) +#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) +#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) +#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) + +/* + * DIV_BUSY (RO) + * + * divider is applying new setting + */ +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) + +/* + * OUTEN (RW) + * + * enable clock output + */ +#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) +#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) +#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) + +/* + * DIV (RW) + * + * output divider + */ +#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) +#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) +#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) +#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) + +/* + * HIGH (RW) + * + * clock frequency higher than upper limit + */ +#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) +#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) +#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) + +/* + * LOW (RW) + * + * clock frequency lower than lower limit + */ +#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) +#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) +#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) +#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) + +/* + * START (RW) + * + * start measurement + */ +#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) +#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) +#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) +#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) + +/* + * MODE (RW) + * + * work mode, + * 0: register value will be compared to measurement + * 1: upper and lower value will be recordered in register + */ +#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) +#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) +#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) +#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) + +/* + * ACCURACY (RW) + * + * measurement accuracy, + * 0: resolution is 1kHz + * 1: resolution is 1Hz + */ +#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) +#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) + +/* + * REFERENCE (RW) + * + * refrence clock selection, + * 0: 32k + * 1: 24M + */ +#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) +#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) + +/* + * SELECTION (RW) + * + * clock measurement selection + */ +#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) +#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: CURRENT */ +/* + * FREQUENCY (RO) + * + * self updating measure result + */ +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ +/* + * FREQUENCY (RW) + * + * lower frequency + */ +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ +/* + * FREQUENCY (RW) + * + * upper frequency + */ +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) +#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) + +/* Bitfield definition for register of struct array CPU: LP */ +/* + * WAKE_CNT (RW) + * + * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear + */ +#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) +#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) +#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) +#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) + +/* + * HALT (RW) + * + * halt request for CPU0, + * 0: CPU0 will start to execute after reset or receive wakeup request + * 1: CPU0 will not start after reset, or wakeup after WFI + */ +#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) +#define SYSCTL_CPU_LP_HALT_SHIFT (16U) +#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) +#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) + +/* + * WAKE (RO) + * + * CPU0 is waking up + * 0: CPU0 wake up not asserted + * 1: CPU0 wake up asserted + */ +#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) +#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) +#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) + +/* + * EXEC (RO) + * + * CPU0 is executing + * 0: CPU0 is not executing + * 1: CPU0 is executing + */ +#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) +#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) +#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) + +/* + * WAKE_FLAG (RW) + * + * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit + * 0: CPU0 wakeup not happened + * 1: CPU0 wake up happened + */ +#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) +#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) +#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) + +/* + * SLEEP_FLAG (RW) + * + * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit + * 0: CPU0 sleep not happened + * 1: CPU0 sleep happened + */ +#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) +#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) +#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) + +/* + * RESET_FLAG (RW) + * + * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit + * 0: CPU0 reset not happened + * 1: CPU0 reset happened + */ +#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) +#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) +#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) +#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) + +/* + * MODE (RW) + * + * Low power mode, system behavior after WFI + * 00: CPU clock stop after WFI + * 01: System enter low power mode after WFI + * 10: Keep running after WFI + * 11: reserved + */ +#define SYSCTL_CPU_LP_MODE_MASK (0x3U) +#define SYSCTL_CPU_LP_MODE_SHIFT (0U) +#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) +#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) + +/* Bitfield definition for register of struct array CPU: LOCK */ +/* + * GPR (RW) + * + * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset + */ +#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) +#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) +#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) +#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) + +/* + * LOCK (RW) + * + * Lock bit for CPU_LOCK + */ +#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) +#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) +#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) +#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) + +/* Bitfield definition for register of struct array CPU: GPR0 */ +/* + * GPR (RW) + * + * register for software to handle resume, can save resume address or status + */ +#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) +#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) +#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) + +/* Bitfield definition for register of struct array CPU: STATUS0 */ +/* + * STATUS (RO) + * + * IRQ values + */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) + +/* Bitfield definition for register of struct array CPU: ENABLE0 */ +/* + * ENABLE (RW) + * + * IRQ wakeup enable + */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) + + + +/* RESOURCE register group index macro definition */ +#define SYSCTL_RESOURCE_CPU0 (0UL) +#define SYSCTL_RESOURCE_CPX0 (1UL) +#define SYSCTL_RESOURCE_POW_CPU0 (21UL) +#define SYSCTL_RESOURCE_RST_SOC (22UL) +#define SYSCTL_RESOURCE_RST_CPU0 (23UL) +#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (36UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (37UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (38UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (39UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL1 (40UL) +#define SYSCTL_RESOURCE_CLK_SRC_CLK3_PLL1 (41UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (42UL) +#define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (43UL) +#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) +#define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (66UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (67UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN2 (68UL) +#define SYSCTL_RESOURCE_CLK_TOP_CAN3 (69UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN0 (70UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN1 (71UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN2 (72UL) +#define SYSCTL_RESOURCE_CLK_TOP_LIN3 (73UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR0 (74UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR1 (75UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR2 (76UL) +#define SYSCTL_RESOURCE_CLK_TOP_TMR3 (77UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (78UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (79UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (80UL) +#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (81UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (82UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (83UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (84UL) +#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (85UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT0 (86UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT1 (87UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT2 (88UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT3 (89UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT4 (90UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT5 (91UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT6 (92UL) +#define SYSCTL_RESOURCE_CLK_TOP_URT7 (93UL) +#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (94UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (95UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (96UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (97UL) +#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (98UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF0 (99UL) +#define SYSCTL_RESOURCE_CLK_TOP_REF1 (100UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (101UL) +#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (102UL) +#define SYSCTL_RESOURCE_CLK_TOP_DAC0 (103UL) +#define SYSCTL_RESOURCE_CLK_TOP_DAC1 (104UL) +#define SYSCTL_RESOURCE_AHB0 (256UL) +#define SYSCTL_RESOURCE_LMM0 (257UL) +#define SYSCTL_RESOURCE_MCT0 (258UL) +#define SYSCTL_RESOURCE_ROM0 (259UL) +#define SYSCTL_RESOURCE_CAN0 (260UL) +#define SYSCTL_RESOURCE_CAN1 (261UL) +#define SYSCTL_RESOURCE_CAN2 (262UL) +#define SYSCTL_RESOURCE_CAN3 (263UL) +#define SYSCTL_RESOURCE_PTPC (264UL) +#define SYSCTL_RESOURCE_LIN0 (265UL) +#define SYSCTL_RESOURCE_LIN1 (266UL) +#define SYSCTL_RESOURCE_LIN2 (267UL) +#define SYSCTL_RESOURCE_LIN3 (268UL) +#define SYSCTL_RESOURCE_TMR0 (269UL) +#define SYSCTL_RESOURCE_TMR1 (270UL) +#define SYSCTL_RESOURCE_TMR2 (271UL) +#define SYSCTL_RESOURCE_TMR3 (272UL) +#define SYSCTL_RESOURCE_I2C0 (273UL) +#define SYSCTL_RESOURCE_I2C1 (274UL) +#define SYSCTL_RESOURCE_I2C2 (275UL) +#define SYSCTL_RESOURCE_I2C3 (276UL) +#define SYSCTL_RESOURCE_SPI0 (277UL) +#define SYSCTL_RESOURCE_SPI1 (278UL) +#define SYSCTL_RESOURCE_SPI2 (279UL) +#define SYSCTL_RESOURCE_SPI3 (280UL) +#define SYSCTL_RESOURCE_URT0 (281UL) +#define SYSCTL_RESOURCE_URT1 (282UL) +#define SYSCTL_RESOURCE_URT2 (283UL) +#define SYSCTL_RESOURCE_URT3 (284UL) +#define SYSCTL_RESOURCE_URT4 (285UL) +#define SYSCTL_RESOURCE_URT5 (286UL) +#define SYSCTL_RESOURCE_URT6 (287UL) +#define SYSCTL_RESOURCE_URT7 (288UL) +#define SYSCTL_RESOURCE_WDG0 (289UL) +#define SYSCTL_RESOURCE_WDG1 (290UL) +#define SYSCTL_RESOURCE_MBX0 (291UL) +#define SYSCTL_RESOURCE_TSNS (292UL) +#define SYSCTL_RESOURCE_CRC0 (293UL) +#define SYSCTL_RESOURCE_ADC0 (294UL) +#define SYSCTL_RESOURCE_ADC1 (295UL) +#define SYSCTL_RESOURCE_DAC0 (296UL) +#define SYSCTL_RESOURCE_DAC1 (297UL) +#define SYSCTL_RESOURCE_ACMP (298UL) +#define SYSCTL_RESOURCE_OPA0 (299UL) +#define SYSCTL_RESOURCE_OPA1 (300UL) +#define SYSCTL_RESOURCE_MOT0 (301UL) +#define SYSCTL_RESOURCE_RNG0 (302UL) +#define SYSCTL_RESOURCE_SDP0 (303UL) +#define SYSCTL_RESOURCE_KMAN (304UL) +#define SYSCTL_RESOURCE_GPIO (305UL) +#define SYSCTL_RESOURCE_HDMA (306UL) +#define SYSCTL_RESOURCE_XPI0 (307UL) +#define SYSCTL_RESOURCE_USB0 (308UL) +#define SYSCTL_RESOURCE_REF0 (309UL) +#define SYSCTL_RESOURCE_REF1 (310UL) + +/* GROUP0 register group index macro definition */ +#define SYSCTL_GROUP0_LINK0 (0UL) +#define SYSCTL_GROUP0_LINK1 (1UL) + +/* AFFILIATE register group index macro definition */ +#define SYSCTL_AFFILIATE_CPU0 (0UL) + +/* RETENTION register group index macro definition */ +#define SYSCTL_RETENTION_CPU0 (0UL) + +/* POWER register group index macro definition */ +#define SYSCTL_POWER_CPU0 (0UL) + +/* RESET register group index macro definition */ +#define SYSCTL_RESET_SOC (0UL) +#define SYSCTL_RESET_CPU0 (1UL) + +/* CLOCK_CPU register group index macro definition */ +#define SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (0UL) + +/* CLOCK register group index macro definition */ +#define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN0 (1UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN1 (2UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN2 (3UL) +#define SYSCTL_CLOCK_CLK_TOP_CAN3 (4UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN0 (5UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN1 (6UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN2 (7UL) +#define SYSCTL_CLOCK_CLK_TOP_LIN3 (8UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR0 (9UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR1 (10UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR2 (11UL) +#define SYSCTL_CLOCK_CLK_TOP_TMR3 (12UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C0 (13UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C1 (14UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C2 (15UL) +#define SYSCTL_CLOCK_CLK_TOP_I2C3 (16UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI0 (17UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI1 (18UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI2 (19UL) +#define SYSCTL_CLOCK_CLK_TOP_SPI3 (20UL) +#define SYSCTL_CLOCK_CLK_TOP_URT0 (21UL) +#define SYSCTL_CLOCK_CLK_TOP_URT1 (22UL) +#define SYSCTL_CLOCK_CLK_TOP_URT2 (23UL) +#define SYSCTL_CLOCK_CLK_TOP_URT3 (24UL) +#define SYSCTL_CLOCK_CLK_TOP_URT4 (25UL) +#define SYSCTL_CLOCK_CLK_TOP_URT5 (26UL) +#define SYSCTL_CLOCK_CLK_TOP_URT6 (27UL) +#define SYSCTL_CLOCK_CLK_TOP_URT7 (28UL) +#define SYSCTL_CLOCK_CLK_TOP_XPI0 (29UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA0 (30UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA1 (31UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA2 (32UL) +#define SYSCTL_CLOCK_CLK_TOP_ANA3 (33UL) +#define SYSCTL_CLOCK_CLK_TOP_REF0 (34UL) +#define SYSCTL_CLOCK_CLK_TOP_REF1 (35UL) + +/* ADCCLK register group index macro definition */ +#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) +#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) + +/* DACCLK register group index macro definition */ +#define SYSCTL_DACCLK_CLK_TOP_DAC0 (0UL) +#define SYSCTL_DACCLK_CLK_TOP_DAC1 (1UL) + +/* MONITOR register group index macro definition */ +#define SYSCTL_MONITOR_SLICE0 (0UL) +#define SYSCTL_MONITOR_SLICE1 (1UL) +#define SYSCTL_MONITOR_SLICE2 (2UL) +#define SYSCTL_MONITOR_SLICE3 (3UL) + +/* GPR register group index macro definition */ +#define SYSCTL_CPU_GPR_GPR0 (0UL) +#define SYSCTL_CPU_GPR_GPR1 (1UL) +#define SYSCTL_CPU_GPR_GPR2 (2UL) +#define SYSCTL_CPU_GPR_GPR3 (3UL) +#define SYSCTL_CPU_GPR_GPR4 (4UL) +#define SYSCTL_CPU_GPR_GPR5 (5UL) +#define SYSCTL_CPU_GPR_GPR6 (6UL) +#define SYSCTL_CPU_GPR_GPR7 (7UL) +#define SYSCTL_CPU_GPR_GPR8 (8UL) +#define SYSCTL_CPU_GPR_GPR9 (9UL) +#define SYSCTL_CPU_GPR_GPR10 (10UL) +#define SYSCTL_CPU_GPR_GPR11 (11UL) +#define SYSCTL_CPU_GPR_GPR12 (12UL) +#define SYSCTL_CPU_GPR_GPR13 (13UL) + +/* WAKEUP_STATUS register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) +#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) + +/* WAKEUP_ENABLE register group index macro definition */ +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) +#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) + +/* CPU register group index macro definition */ +#define SYSCTL_CPU_CPU0 (0UL) + + +#endif /* HPM_SYSCTL_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_regs.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_regs.h new file mode 100644 index 00000000..0fb068dd --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_regs.h @@ -0,0 +1,526 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TRGM_H +#define HPM_TRGM_H + +typedef struct { + __RW uint32_t FILTCFG[28]; /* 0x0 - 0x6C: Filter configure register */ + __R uint8_t RESERVED0[144]; /* 0x70 - 0xFF: Reserved */ + __RW uint32_t TRGOCFG[137]; /* 0x100 - 0x320: Trigger manager output configure register */ + __R uint8_t RESERVED1[220]; /* 0x324 - 0x3FF: Reserved */ + __RW uint32_t DMACFG[8]; /* 0x400 - 0x41C: DMA request configure register */ + __R uint8_t RESERVED2[224]; /* 0x420 - 0x4FF: Reserved */ + __RW uint32_t GCR; /* 0x500: General Control Register */ + __R uint8_t RESERVED3[12]; /* 0x504 - 0x50F: Reserved */ + __RW uint32_t ADC_MATRIX_SEL; /* 0x510: adc matrix select register */ + __RW uint32_t DAC_MATRIX_SEL; /* 0x514: dac matrix select register */ + __RW uint32_t POS_MATRIX_SEL0; /* 0x518: position matrix select register0 */ + __RW uint32_t POS_MATRIX_SEL1; /* 0x51C: position matrix select register1 */ + __R uint8_t RESERVED4[224]; /* 0x520 - 0x5FF: Reserved */ + __R uint32_t TRGM_IN[4]; /* 0x600 - 0x60C: trigmux input read register0 */ + __R uint8_t RESERVED5[16]; /* 0x610 - 0x61F: Reserved */ + __R uint32_t TRGM_OUT[5]; /* 0x620 - 0x630: trigmux output read register0 */ +} TRGM_Type; + + +/* Bitfield definition for register array: FILTCFG */ +/* + * OUTINV (RW) + * + * 1- Filter will invert the output + * 0- Filter will not invert the output + */ +#define TRGM_FILTCFG_OUTINV_MASK (0x10000UL) +#define TRGM_FILTCFG_OUTINV_SHIFT (16U) +#define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK) +#define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT) + +/* + * MODE (RW) + * + * This bitfields defines the filter mode + * 000-bypass; + * 100-rapid change mode; + * 101-delay filter mode; + * 110-stalbe low mode; + * 111-stable high mode + */ +#define TRGM_FILTCFG_MODE_MASK (0xE000U) +#define TRGM_FILTCFG_MODE_SHIFT (13U) +#define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK) +#define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT) + +/* + * SYNCEN (RW) + * + * set to enable sychronization input signal with TRGM clock + */ +#define TRGM_FILTCFG_SYNCEN_MASK (0x1000U) +#define TRGM_FILTCFG_SYNCEN_SHIFT (12U) +#define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK) +#define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT) + +/* + * FILTLEN (RW) + * + * This bitfields defines the filter counter length. + */ +#define TRGM_FILTCFG_FILTLEN_MASK (0xFFFU) +#define TRGM_FILTCFG_FILTLEN_SHIFT (0U) +#define TRGM_FILTCFG_FILTLEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT) & TRGM_FILTCFG_FILTLEN_MASK) +#define TRGM_FILTCFG_FILTLEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT) + +/* Bitfield definition for register array: TRGOCFG */ +/* + * OUTINV (RW) + * + * 1- Invert the output + */ +#define TRGM_TRGOCFG_OUTINV_MASK (0x800U) +#define TRGM_TRGOCFG_OUTINV_SHIFT (11U) +#define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK) +#define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT) + +/* + * FEDG2PEN (RW) + * + * 1- The selected input signal falling edge will be convert to an pulse on output. + */ +#define TRGM_TRGOCFG_FEDG2PEN_MASK (0x400U) +#define TRGM_TRGOCFG_FEDG2PEN_SHIFT (10U) +#define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK) +#define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT) + +/* + * REDG2PEN (RW) + * + * 1- The selected input signal rising edge will be convert to an pulse on output. + */ +#define TRGM_TRGOCFG_REDG2PEN_MASK (0x200U) +#define TRGM_TRGOCFG_REDG2PEN_SHIFT (9U) +#define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK) +#define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT) + +/* + * TRIGOSEL (RW) + * + * This bitfield selects one of the TRGM inputs as output. + */ +#define TRGM_TRGOCFG_TRIGOSEL_MASK (0x7FU) +#define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U) +#define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK) +#define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT) + +/* Bitfield definition for register array: DMACFG */ +/* + * DMAMUX_EN (RW) + * + */ +#define TRGM_DMACFG_DMAMUX_EN_MASK (0x80000000UL) +#define TRGM_DMACFG_DMAMUX_EN_SHIFT (31U) +#define TRGM_DMACFG_DMAMUX_EN_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMAMUX_EN_SHIFT) & TRGM_DMACFG_DMAMUX_EN_MASK) +#define TRGM_DMACFG_DMAMUX_EN_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMAMUX_EN_MASK) >> TRGM_DMACFG_DMAMUX_EN_SHIFT) + +/* + * DMASRCSEL (RW) + * + * This field selects one of the DMA requests as the DMA request output. + */ +#define TRGM_DMACFG_DMASRCSEL_MASK (0x3FU) +#define TRGM_DMACFG_DMASRCSEL_SHIFT (0U) +#define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK) +#define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT) + +/* Bitfield definition for register: GCR */ +/* + * TRGOPEN (RW) + * + * The bitfield enable the TRGM outputs. + */ +#define TRGM_GCR_TRGOPEN_MASK (0xFFU) +#define TRGM_GCR_TRGOPEN_SHIFT (0U) +#define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK) +#define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT) + +/* Bitfield definition for register: ADC_MATRIX_SEL */ +/* + * QEI1_ADC1_SEL (RW) + * + * 0-adc0; 1-adc1; 2-rdc_adc0; 3-rdc_adc1; + * bit7 is used to invert adc_value; + * others reserved + */ +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_MASK (0xFF000000UL) +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_SHIFT (24U) +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_MASK) +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_SHIFT) + +/* + * QEI1_ADC0_SEL (RW) + * + */ +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_MASK (0xFF0000UL) +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_SHIFT (16U) +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_MASK) +#define TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_SHIFT) + +/* + * QEI0_ADC1_SEL (RW) + * + */ +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_MASK (0xFF00U) +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_SHIFT (8U) +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_MASK) +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_SHIFT) + +/* + * QEI0_ADC0_SEL (RW) + * + */ +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_MASK (0xFFU) +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_SHIFT (0U) +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_MASK) +#define TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_SHIFT) + +/* Bitfield definition for register: DAC_MATRIX_SEL */ +/* + * DAC1_DAC_SEL (RW) + * + * 0-qeo0_dac0; 1-qeo0_dac1; 2-qeo0_dac2; + * 3-qeo1_dac0; 4-qeo1_dac1; 5-qeo1_dac2; + * 6-rdc_dac0; 7-rdc_dac1; + * bit7 is used to invert dac_value; + * others reserved + */ +#define TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_MASK (0xFF000000UL) +#define TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_SHIFT (24U) +#define TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_MASK) +#define TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_SHIFT) + +/* + * DAC0_DAC_SEL (RW) + * + */ +#define TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_MASK (0xFF0000UL) +#define TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_SHIFT (16U) +#define TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_MASK) +#define TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_SHIFT) + +/* + * ACMP1_DAC_SEL (RW) + * + */ +#define TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_MASK (0xFF00U) +#define TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_SHIFT (8U) +#define TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_MASK) +#define TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_SHIFT) + +/* + * ACMP0_DAC_SEL (RW) + * + */ +#define TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_MASK (0xFFU) +#define TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_SHIFT (0U) +#define TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_MASK) +#define TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_SHIFT) + +/* Bitfield definition for register: POS_MATRIX_SEL0 */ +/* + * MMC1_POSIN_SEL (RW) + * + * 0-sei_pos_out0; 1-sei_pos_out1; + * 2-qei0_pos; 3-qei1_pos; + * 4-mmc0_pos_out0; 5-mmc0_pos_out1; + * 6-mmc1_pos_out0; 7-mmc1_pos_out1; + * bit7 is used to invert position value; + * others reserved + */ +#define TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_MASK (0xFF000000UL) +#define TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_SHIFT (24U) +#define TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_MASK) +#define TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_SHIFT) + +/* + * MMC0_POSIN_SEL (RW) + * + */ +#define TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_MASK (0xFF0000UL) +#define TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_SHIFT (16U) +#define TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_MASK) +#define TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_SHIFT) + +/* + * SEI_POSIN1_SEL (RW) + * + */ +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK (0xFF00U) +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT (8U) +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK) +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT) + +/* + * SEI_POSIN0_SEL (RW) + * + */ +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK (0xFFU) +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT (0U) +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK) +#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT) + +/* Bitfield definition for register: POS_MATRIX_SEL1 */ +/* + * QEO1_POS_SEL (RW) + * + */ +#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK (0xFF00U) +#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT (8U) +#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK) +#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT) + +/* + * QEO0_POS_SEL (RW) + * + */ +#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK (0xFFU) +#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT (0U) +#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK) +#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT) + +/* Bitfield definition for register array: TRGM_IN */ +/* + * TRGM_IN (RO) + * + * mmc1_trig_out[1:0], mmc0_trig_out[1:0],sync_pulse[3:0],moto_gpio_in_sync[7:0],//31:16 + * gtmr3_to_motor_sync[1:0],gtmr2_to_motor_sync[1:0],gtmr1_to_motor_sync[1:0],gtmr0_to_motor_sync[1:0], //15:8 + * acmp_out_sync[1:0],can2mot_event_sync[1:0],usb0_sof_tog_sync,pwm_debug,1'b1,1'b0 //7:0 + */ +#define TRGM_TRGM_IN_TRGM_IN_MASK (0xFFFFFFFFUL) +#define TRGM_TRGM_IN_TRGM_IN_SHIFT (0U) +#define TRGM_TRGM_IN_TRGM_IN_GET(x) (((uint32_t)(x) & TRGM_TRGM_IN_TRGM_IN_MASK) >> TRGM_TRGM_IN_TRGM_IN_SHIFT) + +/* Bitfield definition for register array: TRGM_OUT */ +/* + * TRGM_OUT (RO) + * + * motor_to_opamp0[7:0] = trig_mux_out[7:0]; + * motor_to_opamp1[7:0] = trig_mux_out[15:8]; + * motor_to_gtmr0_capt[1:0] = trig_mux_out[17:16]; + * motor_to_gtmr0_sync = trig_mux_out[18]; + * motor_to_gtmr1_capt[1:0] = trig_mux_out[20:19]; + * motor_to_gtmr1_sync = trig_mux_out[21]; + * motor_to_gtmr2_capt[1:0] = trig_mux_out[23:22]; + * motor_to_gtmr2_sync = trig_mux_out[24]; + * motor_to_gtmr3_capt[1:0] = trig_mux_out[26:25]; + * motor_to_gtmr3_sync = trig_mux_out[27]; + * acmp_window[1:0] = trig_mux_out[29:28]; + * dac0_buf_trigger = trig_mux_out[30]; + * dac1_buf_trigger = trig_mux_out[31]; + * dac0_step_trigger[3:0] = {trig_mux_out[24:22],trig_mux_out[30]};//use same buf_trig, and gtmr2 + * dac1_step_trigger[3:0] = {trig_mux_out[27:25],trig_mux_out[31]}; //use same buf_trig, and gtmr3 + */ +#define TRGM_TRGM_OUT_TRGM_OUT_MASK (0xFFFFFFFFUL) +#define TRGM_TRGM_OUT_TRGM_OUT_SHIFT (0U) +#define TRGM_TRGM_OUT_TRGM_OUT_GET(x) (((uint32_t)(x) & TRGM_TRGM_OUT_TRGM_OUT_MASK) >> TRGM_TRGM_OUT_TRGM_OUT_SHIFT) + + + +/* FILTCFG register group index macro definition */ +#define TRGM_FILTCFG_PWM0_IN0 (0UL) +#define TRGM_FILTCFG_PWM0_IN1 (1UL) +#define TRGM_FILTCFG_PWM0_IN2 (2UL) +#define TRGM_FILTCFG_PWM0_IN3 (3UL) +#define TRGM_FILTCFG_PWM0_IN4 (4UL) +#define TRGM_FILTCFG_PWM0_IN5 (5UL) +#define TRGM_FILTCFG_PWM0_IN6 (6UL) +#define TRGM_FILTCFG_PWM0_IN7 (7UL) +#define TRGM_FILTCFG_PWM1_IN0 (8UL) +#define TRGM_FILTCFG_PWM1_IN1 (9UL) +#define TRGM_FILTCFG_PWM1_IN2 (10UL) +#define TRGM_FILTCFG_PWM1_IN3 (11UL) +#define TRGM_FILTCFG_PWM1_IN4 (12UL) +#define TRGM_FILTCFG_PWM1_IN5 (13UL) +#define TRGM_FILTCFG_PWM1_IN6 (14UL) +#define TRGM_FILTCFG_PWM1_IN7 (15UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN0 (16UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN1 (17UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN2 (18UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN3 (19UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN4 (20UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN5 (21UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN6 (22UL) +#define TRGM_FILTCFG_MOTO_GPIO_IN7 (23UL) +#define TRGM_FILTCFG_PWM0_FAULT0 (24UL) +#define TRGM_FILTCFG_PWM0_FAULT1 (25UL) +#define TRGM_FILTCFG_PWM1_FAULT0 (26UL) +#define TRGM_FILTCFG_PWM1_FAULT1 (27UL) + +/* TRGOCFG register group index macro definition */ +#define TRGM_TRGOCFG_MOT2OPAMP0_0 (0UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_1 (1UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_2 (2UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_3 (3UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_4 (4UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_5 (5UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_6 (6UL) +#define TRGM_TRGOCFG_MOT2OPAMP0_7 (7UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_0 (8UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_1 (9UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_2 (10UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_3 (11UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_4 (12UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_5 (13UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_6 (14UL) +#define TRGM_TRGOCFG_MOT2OPAMP1_7 (15UL) +#define TRGM_TRGOCFG_GPTMR0_IN2 (16UL) +#define TRGM_TRGOCFG_GPTMR0_IN3 (17UL) +#define TRGM_TRGOCFG_GPTMR0_SYNCI (18UL) +#define TRGM_TRGOCFG_GPTMR1_IN2 (19UL) +#define TRGM_TRGOCFG_GPTMR1_IN3 (20UL) +#define TRGM_TRGOCFG_GPTMR1_SYNCI (21UL) +#define TRGM_TRGOCFG_GPTMR2_IN2 (22UL) +#define TRGM_TRGOCFG_GPTMR2_IN3 (23UL) +#define TRGM_TRGOCFG_GPTMR2_SYNCI (24UL) +#define TRGM_TRGOCFG_GPTMR3_IN2 (25UL) +#define TRGM_TRGOCFG_GPTMR3_IN3 (26UL) +#define TRGM_TRGOCFG_GPTMR3_SYNCI (27UL) +#define TRGM_TRGOCFG_CMP0_WIN (28UL) +#define TRGM_TRGOCFG_CMP1_WIN (29UL) +#define TRGM_TRGOCFG_DAC0_BUFTRG (30UL) +#define TRGM_TRGOCFG_DAC1_BUFTRG (31UL) +#define TRGM_TRGOCFG_ADC0_STRGI (32UL) +#define TRGM_TRGOCFG_ADC1_STRGI (33UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0A (34UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0B (35UL) +#define TRGM_TRGOCFG_ADCX_PTRGI0C (36UL) +#define TRGM_TRGOCFG_ADCX_PTRGI1A (37UL) +#define TRGM_TRGOCFG_ADCX_PTRGI1B (38UL) +#define TRGM_TRGOCFG_ADCX_PTRGI1C (39UL) +#define TRGM_TRGOCFG_ADCX_PTRGI2A (40UL) +#define TRGM_TRGOCFG_ADCX_PTRGI2B (41UL) +#define TRGM_TRGOCFG_ADCX_PTRGI2C (42UL) +#define TRGM_TRGOCFG_ADCX_PTRGI3A (43UL) +#define TRGM_TRGOCFG_ADCX_PTRGI3B (44UL) +#define TRGM_TRGOCFG_ADCX_PTRGI3C (45UL) +#define TRGM_TRGOCFG_CAN_PTPC0_CAP (46UL) +#define TRGM_TRGOCFG_CAN_PTPC1_CAP (47UL) +#define TRGM_TRGOCFG_QEO0_TRIG_IN0 (48UL) +#define TRGM_TRGOCFG_QEO0_TRIG_IN1 (49UL) +#define TRGM_TRGOCFG_QEO1_TRIG_IN0 (50UL) +#define TRGM_TRGOCFG_QEO1_TRIG_IN1 (51UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN0 (52UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN1 (53UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN2 (54UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN3 (55UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN4 (56UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN5 (57UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN6 (58UL) +#define TRGM_TRGOCFG_SEI_TRIG_IN7 (59UL) +#define TRGM_TRGOCFG_MMC0_TRIG_IN0 (60UL) +#define TRGM_TRGOCFG_MMC0_TRIG_IN1 (61UL) +#define TRGM_TRGOCFG_MMC1_TRIG_IN0 (62UL) +#define TRGM_TRGOCFG_MMC1_TRIG_IN1 (63UL) +#define TRGM_TRGOCFG_PLB_IN_00 (64UL) +#define TRGM_TRGOCFG_PLB_IN_01 (65UL) +#define TRGM_TRGOCFG_PLB_IN_02 (66UL) +#define TRGM_TRGOCFG_PLB_IN_03 (67UL) +#define TRGM_TRGOCFG_PLB_IN_04 (68UL) +#define TRGM_TRGOCFG_PLB_IN_05 (69UL) +#define TRGM_TRGOCFG_PLB_IN_06 (70UL) +#define TRGM_TRGOCFG_PLB_IN_07 (71UL) +#define TRGM_TRGOCFG_PLB_IN_08 (72UL) +#define TRGM_TRGOCFG_PLB_IN_09 (73UL) +#define TRGM_TRGOCFG_PLB_IN_10 (74UL) +#define TRGM_TRGOCFG_PLB_IN_11 (75UL) +#define TRGM_TRGOCFG_PLB_IN_12 (76UL) +#define TRGM_TRGOCFG_PLB_IN_13 (77UL) +#define TRGM_TRGOCFG_PLB_IN_14 (78UL) +#define TRGM_TRGOCFG_PLB_IN_15 (79UL) +#define TRGM_TRGOCFG_PLB_IN_16 (80UL) +#define TRGM_TRGOCFG_PLB_IN_17 (81UL) +#define TRGM_TRGOCFG_PLB_IN_18 (82UL) +#define TRGM_TRGOCFG_PLB_IN_19 (83UL) +#define TRGM_TRGOCFG_PLB_IN_20 (84UL) +#define TRGM_TRGOCFG_PLB_IN_21 (85UL) +#define TRGM_TRGOCFG_PLB_IN_22 (86UL) +#define TRGM_TRGOCFG_PLB_IN_23 (87UL) +#define TRGM_TRGOCFG_PLB_IN_24 (88UL) +#define TRGM_TRGOCFG_PLB_IN_25 (89UL) +#define TRGM_TRGOCFG_PLB_IN_26 (90UL) +#define TRGM_TRGOCFG_PLB_IN_27 (91UL) +#define TRGM_TRGOCFG_PLB_IN_28 (92UL) +#define TRGM_TRGOCFG_PLB_IN_29 (93UL) +#define TRGM_TRGOCFG_PLB_IN_30 (94UL) +#define TRGM_TRGOCFG_PLB_IN_31 (95UL) +#define TRGM_TRGOCFG_MOT_GPIO0 (96UL) +#define TRGM_TRGOCFG_MOT_GPIO1 (97UL) +#define TRGM_TRGOCFG_MOT_GPIO2 (98UL) +#define TRGM_TRGOCFG_MOT_GPIO3 (99UL) +#define TRGM_TRGOCFG_MOT_GPIO4 (100UL) +#define TRGM_TRGOCFG_MOT_GPIO5 (101UL) +#define TRGM_TRGOCFG_MOT_GPIO6 (102UL) +#define TRGM_TRGOCFG_MOT_GPIO7 (103UL) +#define TRGM_TRGOCFG_PWM_IN8 (104UL) +#define TRGM_TRGOCFG_PWM_IN9 (105UL) +#define TRGM_TRGOCFG_PWM_IN10 (106UL) +#define TRGM_TRGOCFG_PWM_IN11 (107UL) +#define TRGM_TRGOCFG_PWM_IN12 (108UL) +#define TRGM_TRGOCFG_PWM_IN13 (109UL) +#define TRGM_TRGOCFG_PWM_IN14 (110UL) +#define TRGM_TRGOCFG_PWM_IN15 (111UL) +#define TRGM_TRGOCFG_PWM0_FRCI (112UL) +#define TRGM_TRGOCFG_PWM0_FRCSYNCI (113UL) +#define TRGM_TRGOCFG_PWM0_SYNCI (114UL) +#define TRGM_TRGOCFG_PWM0_SHRLDSYNCI (115UL) +#define TRGM_TRGOCFG_PWM0_FAULTI0 (116UL) +#define TRGM_TRGOCFG_PWM0_FAULTI1 (117UL) +#define TRGM_TRGOCFG_PWM1_FRCI (118UL) +#define TRGM_TRGOCFG_PWM1_FRCSYNCI (119UL) +#define TRGM_TRGOCFG_PWM1_SYNCI (120UL) +#define TRGM_TRGOCFG_PWM1_SHRLDSYNCI (121UL) +#define TRGM_TRGOCFG_PWM1_FAULTI0 (122UL) +#define TRGM_TRGOCFG_PWM1_FAULTI1 (123UL) +#define TRGM_TRGOCFG_RDC_TRIG_IN0 (124UL) +#define TRGM_TRGOCFG_RDC_TRIG_IN1 (125UL) +#define TRGM_TRGOCFG_SYNCTIMER_TRIG (126UL) +#define TRGM_TRGOCFG_QEI0_TRIG_IN (127UL) +#define TRGM_TRGOCFG_QEI1_TRIG_IN (128UL) +#define TRGM_TRGOCFG_QEI0_PAUSE (129UL) +#define TRGM_TRGOCFG_QEI1_PAUSE (130UL) +#define TRGM_TRGOCFG_UART_TRIG0 (131UL) +#define TRGM_TRGOCFG_UART_TRIG1 (132UL) +#define TRGM_TRGOCFG_TRGM_IRQ0 (133UL) +#define TRGM_TRGOCFG_TRGM_IRQ1 (134UL) +#define TRGM_TRGOCFG_TRGM_DMA0 (135UL) +#define TRGM_TRGOCFG_TRGM_DMA1 (136UL) + +/* DMACFG register group index macro definition */ +#define TRGM_DMACFG_0 (0UL) +#define TRGM_DMACFG_1 (1UL) +#define TRGM_DMACFG_2 (2UL) +#define TRGM_DMACFG_3 (3UL) +#define TRGM_DMACFG_4 (4UL) +#define TRGM_DMACFG_5 (5UL) +#define TRGM_DMACFG_6 (6UL) +#define TRGM_DMACFG_7 (7UL) + +/* TRGM_IN register group index macro definition */ +#define TRGM_TRGM_IN_0 (0UL) +#define TRGM_TRGM_IN_1 (1UL) +#define TRGM_TRGM_IN_2 (2UL) +#define TRGM_TRGM_IN_3 (3UL) + +/* TRGM_OUT register group index macro definition */ +#define TRGM_TRGM_OUT_0 (0UL) +#define TRGM_TRGM_OUT_1 (1UL) +#define TRGM_TRGM_OUT_2 (2UL) +#define TRGM_TRGM_OUT_3 (3UL) +#define TRGM_TRGM_OUT_4 (4UL) + + +#endif /* HPM_TRGM_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_soc_drv.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_soc_drv.h new file mode 100644 index 00000000..103dd0b0 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_soc_drv.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_TRGM_SOC_DRV_H +#define HPM_TRGM_SOC_DRV_H + +#include "hpm_soc.h" +#include "hpm_trgm_regs.h" + +typedef enum { + trgm_adc_matrix_output_to_qei0_adcx = 0, + trgm_adc_matrix_output_to_qei0_adcy = 1, + trgm_adc_matrix_output_to_qei1_adcx = 2, + trgm_adc_matrix_output_to_qei1_adcy = 3, +} trgm_adc_matrix_out_t; + +typedef enum { + trgm_adc_matrix_in_from_adc0 = 0, + trgm_adc_matrix_in_from_adc1 = 1, + trgm_adc_matrix_in_from_rdc_adc0 = 2, + trgm_adc_matrix_in_from_rdc_adc1 = 3, +} trgm_adc_matrix_in_t; + +typedef enum { + trgm_dac_matrix_output_to_acmp0 = 0, + trgm_dac_matrix_output_to_acmp1 = 1, + trgm_dac_matrix_output_to_dac0 = 2, + trgm_dac_matrix_output_to_dac1 = 3, +} trgm_dac_matrix_out_t; + +typedef enum { + trgm_dac_matrix_in_from_qeo0_dac0 = 0, + trgm_dac_matrix_in_from_qeo0_dac1 = 1, + trgm_dac_matrix_in_from_qeo0_dac2 = 2, + trgm_dac_matrix_in_from_qeo1_dac0 = 3, + trgm_dac_matrix_in_from_qeo1_dac1 = 4, + trgm_dac_matrix_in_from_qeo1_dac2 = 5, + trgm_dac_matrix_in_from_rdc_dac0 = 6, + trgm_dac_matrix_in_from_rdc_dac1 = 7, +} trgm_dac_matrix_in_t; + +typedef enum { + trgm_pos_matrix_output_to_sei_pos0 = 0, + trgm_pos_matrix_output_to_sei_pos1 = 1, + trgm_pos_matrix_output_to_mmc0 = 2, + trgm_pos_matrix_output_to_mmc1 = 3, + trgm_pos_matrix_output_to_qeo0 = 4, + trgm_pos_matrix_output_to_qeo1 = 5, +} trgm_pos_matrix_out_t; + +typedef enum { + trgm_pos_matrix_in_from_sei_pos0 = 0, + trgm_pos_matrix_in_from_sei_pos1 = 1, + trgm_pos_matrix_in_from_qei0 = 2, + trgm_pos_matrix_in_from_qei1 = 3, + trgm_pos_matrix_in_from_mmc0_pos0 = 4, + trgm_pos_matrix_in_from_mmc0_pos1 = 5, + trgm_pos_matrix_in_from_mmc1_pos0 = 6, + trgm_pos_matrix_in_from_mmc1_pos1 = 7, +} trgm_pos_matrix_in_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +static inline void trgm_adc_matrix_config(TRGM_Type *ptr, trgm_adc_matrix_out_t consumer, trgm_adc_matrix_in_t src, bool inv_val) +{ + if (inv_val) { + ptr->ADC_MATRIX_SEL |= 0x80 << consumer * 8U; + } else { + ptr->ADC_MATRIX_SEL &= ~(0x80 << consumer * 8U); + } + ptr->ADC_MATRIX_SEL &= ~(0x7f << consumer * 8U); + ptr->ADC_MATRIX_SEL |= src << consumer * 8U; +} + +static inline void trgm_dac_matrix_config(TRGM_Type *ptr, trgm_dac_matrix_out_t consumer, trgm_dac_matrix_in_t src, bool inv_val) +{ + if (inv_val) { + ptr->DAC_MATRIX_SEL |= 0x80 << consumer * 8U; + } else { + ptr->DAC_MATRIX_SEL &= ~(0x80 << consumer * 8U); + } + ptr->DAC_MATRIX_SEL &= ~(0x7f << consumer * 8U); + ptr->DAC_MATRIX_SEL |= src << consumer * 8U; +} + +static inline void trgm_pos_matrix_config(TRGM_Type *ptr, trgm_pos_matrix_out_t consumer, trgm_pos_matrix_in_t src, bool inv_val) +{ + uint8_t index = consumer / 4U; + uint8_t offset = (consumer % 4U) * 8U; + + if (index == 0) { + if (inv_val) { + ptr->POS_MATRIX_SEL0 |= 0x80 << offset; + } else { + ptr->POS_MATRIX_SEL0 &= ~(0x80 << offset); + } + ptr->POS_MATRIX_SEL0 &= ~(0x7f << offset); + ptr->POS_MATRIX_SEL0 |= src << offset; + } else if (index == 1) { + if (inv_val) { + ptr->POS_MATRIX_SEL1 |= 0x80 << offset; + } else { + ptr->POS_MATRIX_SEL1 &= ~(0x80 << offset); + } + ptr->POS_MATRIX_SEL1 &= ~(0x7f << offset); + ptr->POS_MATRIX_SEL1 |= src << offset; + } +} + +#if defined(__cplusplus) +} +#endif + +#endif /* HPM_TRGM_SOC_DRV_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/hpm_trgmmux_src.h b/common/libraries/hpm_sdk/soc/HPM5361/hpm_trgmmux_src.h new file mode 100644 index 00000000..f2ca571e --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/hpm_trgmmux_src.h @@ -0,0 +1,377 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_TRGMMUX_SRC_H +#define HPM_TRGMMUX_SRC_H + +/* trgm0_input mux definitions */ +#define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) +#define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) +#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x2UL) +#define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x3UL) +#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x4UL) +#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x5UL) +#define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x6UL) +#define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x7UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x8UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x9UL) +#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0xAUL) +#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0xBUL) +#define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT2 (0xCUL) +#define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT3 (0xDUL) +#define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 (0xEUL) +#define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT3 (0xFUL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x10UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x11UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x12UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x13UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x14UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x15UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x16UL) +#define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x17UL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x18UL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x19UL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x1AUL) +#define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x1BUL) +#define HPM_TRGM0_INPUT_SRC_MMC0_TRGO_0 (0x1CUL) +#define HPM_TRGM0_INPUT_SRC_MMC0_TRGO_1 (0x1DUL) +#define HPM_TRGM0_INPUT_SRC_MMC1_TRGO_0 (0x1EUL) +#define HPM_TRGM0_INPUT_SRC_MMC1_TRGO_1 (0x1FUL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_0 (0x20UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_1 (0x21UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_2 (0x22UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_3 (0x23UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_4 (0x24UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_5 (0x25UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_6 (0x26UL) +#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_7 (0x27UL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_0 (0x28UL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_1 (0x29UL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_2 (0x2AUL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_3 (0x2BUL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_4 (0x2CUL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_5 (0x2DUL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_6 (0x2EUL) +#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_7 (0x2FUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x30UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x31UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x32UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x33UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x34UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x35UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x36UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x37UL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH8REF (0x38UL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH9REF (0x39UL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH10REF (0x3AUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH11REF (0x3BUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH12REF (0x3CUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH13REF (0x3DUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH14REF (0x3EUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CH15REF (0x3FUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT00 (0x40UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT01 (0x41UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT02 (0x42UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT03 (0x43UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT04 (0x44UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT05 (0x45UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT06 (0x46UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT07 (0x47UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT08 (0x48UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT09 (0x49UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT10 (0x4AUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT11 (0x4BUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT12 (0x4CUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT13 (0x4DUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT14 (0x4EUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT15 (0x4FUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT16 (0x50UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT17 (0x51UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT18 (0x52UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT19 (0x53UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT20 (0x54UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT21 (0x55UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT22 (0x56UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT23 (0x57UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT24 (0x58UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT25 (0x59UL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT26 (0x5AUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT27 (0x5BUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT28 (0x5CUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT29 (0x5DUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT30 (0x5EUL) +#define HPM_TRGM0_INPUT_SRC_PLB_OUT31 (0x5FUL) +#define HPM_TRGM0_INPUT_SRC_RDC_TRGO_0 (0x60UL) +#define HPM_TRGM0_INPUT_SRC_RDC_TRGO_1 (0x61UL) +#define HPM_TRGM0_INPUT_SRC_QEI1_TRGO (0x62UL) +#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x63UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_0 (0x64UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_1 (0x65UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_2 (0x66UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_3 (0x67UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_4 (0x68UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_5 (0x69UL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_6 (0x6AUL) +#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_7 (0x6BUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_FAULT0 (0x6CUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_FAULT1 (0x6DUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_FAULT0 (0x6EUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_FAULT1 (0x6FUL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN0 (0x70UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN1 (0x71UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN2 (0x72UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN3 (0x73UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN4 (0x74UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN5 (0x75UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN6 (0x76UL) +#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN7 (0x77UL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN0 (0x78UL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN1 (0x79UL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN2 (0x7AUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN3 (0x7BUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN4 (0x7CUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN5 (0x7DUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN6 (0x7EUL) +#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN7 (0x7FUL) + +/* trgm0_output mux definitions */ +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_0 (0x0UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_1 (0x1UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_2 (0x2UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_3 (0x3UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_4 (0x4UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_5 (0x5UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_6 (0x6UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_7 (0x7UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_0 (0x8UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_1 (0x9UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_2 (0xAUL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_3 (0xBUL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_4 (0xCUL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_5 (0xDUL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_6 (0xEUL) +#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_7 (0xFUL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x10UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x11UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x12UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x13UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x14UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x15UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN2 (0x16UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN3 (0x17UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_SYNCI (0x18UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN2 (0x19UL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN3 (0x1AUL) +#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_SYNCI (0x1BUL) +#define HPM_TRGM0_OUTPUT_SRC_CMP0_WIN (0x1CUL) +#define HPM_TRGM0_OUTPUT_SRC_CMP1_WIN (0x1DUL) +#define HPM_TRGM0_OUTPUT_SRC_DAC0_BUFTRG (0x1EUL) +#define HPM_TRGM0_OUTPUT_SRC_DAC1_BUFTRG (0x1FUL) +#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x20UL) +#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x21UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x22UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x23UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x24UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1A (0x25UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1B (0x26UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1C (0x27UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2A (0x28UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2B (0x29UL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2C (0x2AUL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3A (0x2BUL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3B (0x2CUL) +#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3C (0x2DUL) +#define HPM_TRGM0_OUTPUT_SRC_CAN_PTPC0_CAP (0x2EUL) +#define HPM_TRGM0_OUTPUT_SRC_CAN_PTPC1_CAP (0x2FUL) +#define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN0 (0x30UL) +#define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN1 (0x31UL) +#define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN0 (0x32UL) +#define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN1 (0x33UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN0 (0x34UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN1 (0x35UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN2 (0x36UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN3 (0x37UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN4 (0x38UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN5 (0x39UL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN6 (0x3AUL) +#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN7 (0x3BUL) +#define HPM_TRGM0_OUTPUT_SRC_MMC0_TRIG_IN0 (0x3CUL) +#define HPM_TRGM0_OUTPUT_SRC_MMC0_TRIG_IN1 (0x3DUL) +#define HPM_TRGM0_OUTPUT_SRC_MMC1_TRIG_IN0 (0x3EUL) +#define HPM_TRGM0_OUTPUT_SRC_MMC1_TRIG_IN1 (0x3FUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_00 (0x40UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_01 (0x41UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_02 (0x42UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_03 (0x43UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_04 (0x44UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_05 (0x45UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_06 (0x46UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_07 (0x47UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_08 (0x48UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_09 (0x49UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_10 (0x4AUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_11 (0x4BUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_12 (0x4CUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_13 (0x4DUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_14 (0x4EUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_15 (0x4FUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_16 (0x50UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_17 (0x51UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_18 (0x52UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_19 (0x53UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_20 (0x54UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_21 (0x55UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_22 (0x56UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_23 (0x57UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_24 (0x58UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_25 (0x59UL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_26 (0x5AUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_27 (0x5BUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_28 (0x5CUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_29 (0x5DUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_30 (0x5EUL) +#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_31 (0x5FUL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO0 (0x60UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO1 (0x61UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2 (0x62UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO3 (0x63UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO4 (0x64UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO5 (0x65UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO6 (0x66UL) +#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO7 (0x67UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN8 (0x68UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN9 (0x69UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN10 (0x6AUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN11 (0x6BUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN12 (0x6CUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN13 (0x6DUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN14 (0x6EUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM_IN15 (0x6FUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0x70UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x71UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0x72UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x73UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x74UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x75UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM1_FRCI (0x76UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM1_FRCSYNCI (0x77UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM1_SYNCI (0x78UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x79UL) +#define HPM_TRGM0_OUTPUT_SRC_PWM1_FAULTI0 (0x7AUL) +#define HPM_TRGM0_OUTPUT_SRC_PWM1_FAULTI1 (0x7BUL) +#define HPM_TRGM0_OUTPUT_SRC_RDC_TRIG_IN0 (0x7CUL) +#define HPM_TRGM0_OUTPUT_SRC_RDC_TRIG_IN1 (0x7DUL) +#define HPM_TRGM0_OUTPUT_SRC_SYNCTIMER_TRIG (0x7EUL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_TRIG_IN (0x7FUL) +#define HPM_TRGM0_OUTPUT_SRC_QEI1_TRIG_IN (0x80UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x81UL) +#define HPM_TRGM0_OUTPUT_SRC_QEI1_PAUSE (0x82UL) +#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG0 (0x83UL) +#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 (0x84UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ0 (0x85UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ1 (0x86UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA0 (0x87UL) +#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA1 (0x88UL) + +/* trgm0_filter mux definitions */ +#define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN0 (0x8UL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN1 (0x9UL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN2 (0xAUL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN3 (0xBUL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN4 (0xCUL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN5 (0xDUL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN6 (0xEUL) +#define HPM_TRGM0_FILTER_SRC_PWM1_IN7 (0xFUL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN0 (0x10UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN1 (0x11UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN2 (0x12UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN3 (0x13UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN4 (0x14UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN5 (0x15UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN6 (0x16UL) +#define HPM_TRGM0_FILTER_SRC_TRGM_IN7 (0x17UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_FAULT0 (0x18UL) +#define HPM_TRGM0_FILTER_SRC_PWM0_FAULT1 (0x19UL) +#define HPM_TRGM0_FILTER_SRC_PWM1_FAULT0 (0x1AUL) +#define HPM_TRGM0_FILTER_SRC_PWM1_FAULT1 (0x1BUL) + +/* trgm0_dma mux definitions */ +#define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) +#define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) +#define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) +#define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) +#define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP0 (0x1BUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP1 (0x1CUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP2 (0x1DUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP3 (0x1EUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP4 (0x1FUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP5 (0x20UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP6 (0x21UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP7 (0x22UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP8 (0x23UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP9 (0x24UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP10 (0x25UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP11 (0x26UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP12 (0x27UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP13 (0x28UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP14 (0x29UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP15 (0x2AUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP16 (0x2BUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP17 (0x2CUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP18 (0x2DUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP19 (0x2EUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP20 (0x2FUL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP21 (0x30UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP22 (0x31UL) +#define HPM_TRGM0_DMA_SRC_PWM1_CMP23 (0x32UL) +#define HPM_TRGM0_DMA_SRC_PWM1_RLD (0x33UL) +#define HPM_TRGM0_DMA_SRC_PWM1_HALFRLD (0x34UL) +#define HPM_TRGM0_DMA_SRC_PWM1_XRLD (0x35UL) +#define HPM_TRGM0_DMA_SRC_QEI0 (0x36UL) +#define HPM_TRGM0_DMA_SRC_QEI1 (0x37UL) +#define HPM_TRGM0_DMA_SRC_MMC0 (0x38UL) +#define HPM_TRGM0_DMA_SRC_MMC1 (0x39UL) +#define HPM_TRGM0_DMA_SRC_SEI0 (0x3AUL) +#define HPM_TRGM0_DMA_SRC_SEI1 (0x3BUL) +#define HPM_TRGM0_DMA_SRC_TRGM0 (0x3CUL) +#define HPM_TRGM0_DMA_SRC_TRGM1 (0x3DUL) + + + +#endif /* HPM_TRGMMUX_SRC_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/soc_modules.list b/common/libraries/hpm_sdk/soc/HPM5361/soc_modules.list new file mode 100644 index 00000000..4309658f --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/soc_modules.list @@ -0,0 +1,48 @@ +# Copyright (c) 2022 HPMicro +# SPDX-License-Identifier: BSD-3-Clause +# +# In this file, all modules available on this part are listed + +CONFIG_HAS_HPMSDK_UART=y +CONFIG_HAS_HPMSDK_FEMC=n +CONFIG_HAS_HPMSDK_SDP=y +CONFIG_HAS_HPMSDK_I2C=y +CONFIG_HAS_HPMSDK_PMP=y +CONFIG_HAS_HPMSDK_RNG=y +CONFIG_HAS_HPMSDK_GPIO=y +CONFIG_HAS_HPMSDK_SPI=y +CONFIG_HAS_HPMSDK_EWDG=y +CONFIG_HAS_HPMSDK_DMAV2=y +CONFIG_HAS_HPMSDK_GPTMR=y +CONFIG_HAS_HPMSDK_PWM=y +CONFIG_HAS_HPMSDK_PLLCTLV2=y +CONFIG_HAS_HPMSDK_USB=y +CONFIG_HAS_HPMSDK_RTC=n +CONFIG_HAS_HPMSDK_ACMP=y +CONFIG_HAS_HPMSDK_I2S=n +CONFIG_HAS_HPMSDK_DAO=n +CONFIG_HAS_HPMSDK_PDM=n +CONFIG_HAS_HPMSDK_VAD=n +CONFIG_HAS_HPMSDK_MCAN=y +CONFIG_HAS_HPMSDK_ENET=n +CONFIG_HAS_HPMSDK_SDXC=n +CONFIG_HAS_HPMSDK_ADC16=y +CONFIG_HAS_HPMSDK_PCFG=y +CONFIG_HAS_HPMSDK_PMU=y +CONFIG_HAS_HPMSDK_PTPC=y +CONFIG_HAS_HPMSDK_MCHTMR=y +CONFIG_HAS_HPMSDK_FFA=n +CONFIG_HAS_HPMSDK_TSNS=y +CONFIG_HAS_HPMSDK_DAC=y +CONFIG_HAS_HPMSDK_CRC=y +CONFIG_HAS_HPMSDK_PLA=n +CONFIG_HAS_HPMSDK_SDM=n + +CONFIG_HAS_HPMSDK_SEI=y +CONFIG_HAS_HPMSDK_QEO=y +CONFIG_HAS_HPMSDK_RDC=y +CONFIG_HAS_HPMSDK_QEIV2=y +CONFIG_HAS_HPMSDK_MMC=y +CONFIG_HAS_HPMSDK_LINV2=y +CONFIG_HAS_HPMSDK_PLB=y +CONFIG_HAS_HPMSDK_OPAMP=y diff --git a/common/libraries/hpm_sdk/soc/HPM5361/system.c b/common/libraries/hpm_sdk/soc/HPM5361/system.c new file mode 100644 index 00000000..3f742ad6 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/system.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" + +#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP +#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 +#endif + +void enable_plic_feature(void) +{ + uint32_t plic_feature = 0; +#ifndef USE_NONVECTOR_MODE + /* enabled vector mode and preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; +#endif +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + /* enabled preemptive priority interrupt */ + plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; +#endif + __plic_set_feature(HPM_PLIC_BASE, plic_feature); +} + +__attribute__((weak)) void system_init(void) +{ +#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR + uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); + write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ +#endif + +#ifdef USE_S_MODE_IRQ + disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#else + disable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + + disable_irq_from_intc(); +#ifdef USE_S_MODE_IRQ + disable_s_irq_from_intc(); +#endif + + enable_plic_feature(); + enable_irq_from_intc(); + +#ifdef USE_S_MODE_IRQ + delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); + enable_s_irq_from_intc(); +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP + enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); +#endif +#else +#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif +#endif + +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); + l1c_dc_invalidate_all(); +#endif +} diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash.ld b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash.ld new file mode 100644 index 00000000..c6882fff --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash.ld @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_uf2.ld b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_uf2.ld new file mode 100644 index 00000000..902149fd --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_uf2.ld @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; +UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + KEEP(*(.uf2_signature)) + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_xip.ld b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_xip.ld new file mode 100644 index 00000000..be421694 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_xip.ld @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + *(.tdata) + *(.tdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") +} diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/initfini.c b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/initfini.c new file mode 100644 index 00000000..7d2b8579 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/initfini.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#ifndef USE_LIBC_INITFINI +#define USE_LIBC_INITFINI 0 +#endif + +#if USE_LIBC_INITFINI + +/* + * The _init() and _fini() will be called respectively when use __libc_init_array() + * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. + * The dummy versions of these functions should be provided. + */ +void _init(void) +{ +} + +void _fini(void) +{ +} + +#else + +/* These magic symbols are provided by the linker. */ +extern void (*__preinit_array_start[])(void) __attribute__((weak)); +extern void (*__preinit_array_end[])(void) __attribute__((weak)); +extern void (*__init_array_start[])(void) __attribute__((weak)); +extern void (*__init_array_end[])(void) __attribute__((weak)); + +/* + * The __libc_init_array()/__libc_fnit_array() function is used to do global + * constructor/destructor and can NOT be compilied to generate the code coverage + * data. We have the function attribute to be 'no_profile_instrument_function' + * to prevent been instrumented for coverage analysis when GCOV=1 is applied. + */ +/* Iterate over all the init routines. */ +void __libc_init_array(void) __attribute__((no_profile_instrument_function)); +void __libc_init_array(void) +{ + uint32_t count; + uint32_t i; + + count = __preinit_array_end - __preinit_array_start; + for (i = 0; i < count; i++) { + __preinit_array_start[i](); + } + + count = __init_array_end - __init_array_start; + for (i = 0; i < count; i++) { + __init_array_start[i](); + } +} + +extern void (*__fini_array_start[])(void) __attribute__((weak)); +extern void (*__fini_array_end[])(void) __attribute__((weak)); + +/* Run all the cleanup routines. */ +void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); +void __libc_fini_array(void) +{ + uint32_t count; + uint32_t i; + + count = __fini_array_end - __fini_array_start; + for (i = count; i > 0; i--) { + __fini_array_start[i - 1](); + } +} + +#endif diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/ram.ld b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/ram.ld new file mode 100644 index 00000000..1b9dfa1f --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/ram.ld @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x4000; + +MEMORY +{ + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + KEEP(*(.isr_s_vector)) + KEEP(*(.vector_s_table)) + . = ALIGN(8); + } > ILM + + .rel : { + KEEP(*(.rel*)) + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > ILM + + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > ILM + + .bss (NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + .stack (NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_safe = .); + } > DLM + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(ILM), "****** FAILED! ILM has not enough space! ******") +} diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/start.S b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/start.S new file mode 100644 index 00000000..6feaa9bc --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/start.S @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2021-2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_csr_regs.h" + + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer$ + .option pop + + /* reset mstatus to 0*/ + csrrw x0, mstatus, x0 + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_safe + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + call c_startup + +#if defined(__SES_RISCV) + /* Initialize the heap */ + la a0, __heap_start__ + la a1, __heap_end__ + sub a1, a1, a0 + la t1, __SEGGER_RTL_init_heap + jalr t1 +#endif + + /* Do global constructors */ + call __libc_init_array + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS + #define HANDLER_TRAP freertos_risc_v_trap_handler + #define HANDLER_S_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III + #define HANDLER_TRAP ucos_risc_v_trap_handler + #define HANDLER_S_TRAP ucos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_THREADX) && CONFIG_THREADX + #define HANDLER_TRAP tx_risc_v_trap_handler + #define HANDLER_S_TRAP tx_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#else + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap +#endif + +#ifndef USE_NONVECTOR_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + +#if defined (USE_S_MODE_IRQ) + la t0, __vector_s_table + csrw stvec, t0 +#endif + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 +#if defined (USE_S_MODE_IRQ) + la t0, HANDLER_S_TRAP + csrw stvec, t0 +#endif + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidentally */ +1: j 1b + + .weak exit +exit: +1: j 1b + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/reset.c b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/reset.c new file mode 100644 index 00000000..729ffb63 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/reset.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2022 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include "hpm_interrupt.h" + + +extern void system_init(void); + + +__attribute__((weak)) void _clean_up(void) +{ + /* clean up plic, it will help while debugging */ + disable_irq_from_intc(); + intc_m_set_threshold(0); + for (uint32_t irq = 0; irq < 128; irq++) { + intc_m_complete_irq(irq); + } + /* clear any bits left in plic enable register */ + for (uint32_t i = 0; i < 4; i++) { + *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; + } +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __data_load_addr__[], __fast_load_addr__[], __noncacheable_init_load_addr__[]; + +#if defined(FLASH_XIP) || defined(FLASH_UF2) + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } +} + +__attribute__((weak)) int main(void) +{ + while (1) { + ; + } +} + +__attribute__((weak)) void reset_handler(void) +{ + l1c_dc_disable(); + l1c_dc_invalidate_all(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Entry function */ + main(); +} + +/* + * When compiling C++ code with static objects, the compiler inserts + * a call to __cxa_atexit() with __dso_handle as one of the arguments. + * The dummy versions of these symbols should be provided. + */ +__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) +{ +} + +#if !defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes) +void *__dso_handle = (void *) &__dso_handle; +#endif + +__attribute__((weak)) void _init(void) +{ +} diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/flash.icf b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/flash.icf new file mode 100644 index 00000000..36b9d45b --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/flash.icf @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region AHB_SRAM = [from 0xF0400000 size 32k]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls with fixed order { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place at start of XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { + section .fast, section .fast.* // "ramfunc" section + }; +place in DLM { block cherryusb_usbh_class_info }; +place in DLM { block framebuffer }; +place in DLM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/flash_uf2.icf b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/flash_uf2.icf new file mode 100644 index 00000000..7c3c7180 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/flash_uf2.icf @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; +define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; + +/* Regions */ +define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region AHB_SRAM = [from 0xF0400000 size 32k]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls with fixed order { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place at start of XPI0 with fixed order { section .uf2_signature }; +place in XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in DLM { block cherryusb_usbh_class_info }; +place in DLM { block framebuffer }; +place in DLM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .uf2_signature }; +keep { section .usbh_class_info}; diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/flash_xip.icf b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/flash_xip.icf new file mode 100644 index 00000000..a77420ae --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/flash_xip.icf @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; +define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region AHB_SRAM = [from 0xf0400000 size 32k]; /* AHB_SRAM */ + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls with fixed order { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; +define exported symbol __fw_size__ = 0x1000; + +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; +initialize by copy { block cherryusb_usbh_class_info }; + +/* Placement */ +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of XPI0 with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in XPI0 with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in DLM { block cherryusb_usbh_class_info }; +place in DLM { block framebuffer }; +place in DLM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +keep { section .usbh_class_info}; diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/ram.icf b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/ram.icf new file mode 100644 index 00000000..c0ae37f2 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/ram.icf @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region ILM = [from 0x00000000 size 128k]; /* ILM */ +define region DLM = [from 0x00080000 size 128k]; /* DLM */ +define region AHB_SRAM = [from 0xF0400000 size 32k]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls with fixed order { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer }; + +/* Symbols */ +define exported symbol _stack = end of block stack + 1; +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +/* Initialization */ +do not initialize { section .noncacheable }; +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections + +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +/* Placement */ +place at start of ILM { symbol _start }; +place in ILM { block vectors, block vectors_s }; // Vector table section +place in ILM { section .fast, section .fast.* }; // "ramfunc" section +place in ILM with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in DLM { block cherryusb_usbh_class_info }; +place in DLM { block framebuffer }; +place in DLM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable +place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory +place in DLM { section .fast_ram}; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .usbh_class_info}; diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/startup.s b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/startup.s new file mode 100644 index 00000000..42f64b24 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/segger/startup.s @@ -0,0 +1,398 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2021 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : SEGGER_RISCV_crt0.s +Purpose : Generic runtime init startup code for RISC-V CPUs. + Designed to work with the SEGGER linker to produce + smallest possible executables. + + This file does not normally require any customization. + +Additional information: + Preprocessor Definitions + FULL_LIBRARY + If defined then + - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). + - the exit symbol is defined and executes on return from main. + - the exit symbol calls destructors, atexit functions and then + calls SEGGER_SEMIHOST_Exit(). + + If not defined then + - argc and argv are not valid (main is assumed to not take parameters) + - the exit symbol is defined, executes on return from main and + halts in a loop. +*/ + +#include "hpm_csr_regs.h" + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ +#ifndef APP_ENTRY_POINT + #define APP_ENTRY_POINT reset_handler +#endif + +#ifndef ARGSSPACE + #define ARGSSPACE 128 +#endif + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ +// +// Declare a label as function symbol (without switching sections) +// +.macro MARK_FUNC Name + .global \Name + .type \Name, function +\Name: +.endm + +// +// Declare a regular function. +// Functions from the startup are placed in the init section. +// +.macro START_FUNC Name + .section .init.\Name, "ax" + .global \Name +#if __riscv_compressed + .balign 2 +#else + .balign 4 +#endif + .type \Name, function +\Name: +.endm + +// +// Declare a weak function +// +.macro WEAK_FUNC Name + .section .init.\Name, "ax", %progbits + .global \Name + .weak \Name +#if __riscv_compressed + .balign 2 +#else + .balign 4 +#endif + .type \Name, function +\Name: +.endm + +// +// Mark the end of a function and calculate its size +// +.macro END_FUNC name + .size \name,.-\name +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern APP_ENTRY_POINT // typically main + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* _start +* +* Function description +* Entry point for the startup code. +* Usually called by the reset handler. +* Performs all initialisation, based on the entries in the +* linker-generated init table, then calls main(). +* It is device independent, so there should not be any need for an +* end-user to modify it. +* +* Additional information +* At this point, the stack pointer should already have been +* initialized +* - by hardware (such as on Cortex-M), +* - by the device-specific reset handler, +* - or by the debugger (such as for RAM Code). +*/ +#undef L +#define L(label) .L_start_##label + +START_FUNC _start + .option push + .option norelax + lui gp, %hi(__global_pointer$) + addi gp, gp, %lo(__global_pointer$) + lui tp, %hi(__thread_pointer$) + addi tp, tp, %lo(__thread_pointer$) + .option pop + + csrw mstatus, zero + csrw mcause, zero + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_safe + mv sp, t0 + call _init_ext_ram +#endif + + lui t0, %hi(__stack_end__) + addi sp, t0, %lo(__stack_end__) + +#ifndef __NO_SYSTEM_INIT + // + // Call _init + // + call _init +#endif + // + // Call linker init functions which in turn performs the following: + // * Perform segment init + // * Perform heap init (if used) + // * Call constructors of global Objects (if any exist) + // + la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table +L(RunInit): + lw a0, (s0) // Get next initialization function from table + add s0, s0, 4 // Increment table pointer to point to function arguments + jalr a0 // Call initialization function + j L(RunInit) + // +MARK_FUNC __SEGGER_init_done + // + // Time to call main(), the application entry point. + // + +#ifndef NO_CLEANUP_AT_START + /* clean up */ + call _clean_up +#endif + +#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS + #define HANDLER_TRAP freertos_risc_v_trap_handler + #define HANDLER_S_TRAP freertos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III + #define HANDLER_TRAP ucos_risc_v_trap_handler + #define HANDLER_S_TRAP ucos_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#elif defined(CONFIG_THREADX) && CONFIG_THREADX + #define HANDLER_TRAP tx_risc_v_trap_handler + #define HANDLER_S_TRAP tx_risc_v_trap_handler + + /* Use mscratch to store isr level */ + csrw mscratch, 0 +#else + #define HANDLER_TRAP irq_handler_trap + #define HANDLER_S_TRAP irq_handler_s_trap +#endif + +#if !defined(USE_NONVECTOR_MODE) + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + +#if defined (USE_S_MODE_IRQ) + la t0, __vector_s_table + csrw stvec, t0 +#endif + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, HANDLER_TRAP + csrw mtvec, t0 +#if defined (USE_S_MODE_IRQ) + la t0, HANDLER_S_TRAP + csrw stvec, t0 +#endif + + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + +MARK_FUNC start +#ifndef FULL_LIBRARY + // + // In a real embedded application ("Free-standing environment"), + // main() does not get any arguments, + // which means it is not necessary to init a0 and a1. + // + call APP_ENTRY_POINT + tail exit + +END_FUNC _start + // + // end of _start + // Fall-through to exit if main ever returns. + // +MARK_FUNC exit + // + // In a free-standing environment, if returned from application: + // Loop forever. + // + j . + .size exit,.-exit +#else + // + // In a hosted environment, + // we need to load a0 and a1 with argc and argv, in order to handle + // the command line arguments. + // This is required for some programs running under control of a + // debugger, such as automated tests. + // + li a0, ARGSSPACE + la a1, args + call debug_getargs + li a0, ARGSSPACE + la a1, args + + call APP_ENTRY_POINT // Call to application entry point (usually main()) + call exit // Call exit function + j . // If we unexpectedly return from exit, hang. +END_FUNC _start +#endif + +#ifdef FULL_LIBRARY + li a0, ARGSSPACE + la a1, args + call debug_getargs + li a0, ARGSSPACE + la a1, args +#else + li a0, 0 + li a1, 0 +#endif + + call APP_ENTRY_POINT + tail exit + +END_FUNC _start + + // +#ifdef FULL_LIBRARY +/********************************************************************* +* +* exit +* +* Function description +* Exit of the system. +* Called on return from application entry point or explicit call +* to exit. +* +* Additional information +* In a hosted environment exit gracefully, by +* saving the return value, +* calling destructurs of global objects, +* calling registered atexit functions, +* and notifying the host/debugger. +*/ +#undef L +#define L(label) .L_exit_##label + +WEAK_FUNC exit + mv s1, a0 // Save the exit parameter/return result + // + // Call destructors + // + la s0, __dtors_start__ +L(Loop): + la t0, __dtors_end__ + beq s0, t0, L(End) + lw t1, 0(s0) + addi s0, s0, 4 + jalr t1 + j L(Loop) +L(End): + // + // Call atexit functions + // + call _execute_at_exit_fns + // + // Call debug_exit with return result/exit parameter + // + mv a0, s1 + call debug_exit + // + // If execution is not terminated, loop forever + // +L(ExitLoop): + j L(ExitLoop) // Loop forever. +END_FUNC exit +#endif + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE + .size args, .-args + .type args, %object +#endif + + .section .isr_vector, "ax" + .weak nmi_handler +nmi_handler: +1: j 1b + +#include "../vectors.h" + +/*************************** End of file ****************************/ diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/trap.c b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/trap.c new file mode 100644 index 00000000..f7fb697e --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/trap.c @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" + +/********************** MCAUSE exception types **************************************/ +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ +#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ +#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ +#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ +#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ +#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ +#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ +#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +__attribute__((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void swi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) +{ +} + +__attribute__((weak)) long exception_handler(long cause, long epc) +{ + switch (cause) { + case MCAUSE_INSTR_ADDR_MISALIGNED: + break; + case MCAUSE_INSTR_ACCESS_FAULT: + break; + case MCAUSE_ILLEGAL_INSTR: + break; + case MCAUSE_BREAKPOINT: + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + break; + case MCAUSE_LOAD_ACCESS_FAULT: + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + break; + case MCAUSE_ECALL_FROM_USER_MODE: + break; + case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: + break; + case MCAUSE_ECALL_FROM_MACHINE_MODE: + break; + case MCAUSE_INSTR_PAGE_FAULT: + break; + case MCAUSE_LOAD_PAGE_FAULT: + break; + case MCAUSE_STORE_AMO_PAGE_FAULT: + break; + default: + break; + } + /* Unhandled Trap */ + return epc; +} + +#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))); +#else +void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); +#endif +void irq_handler_trap(void) +{ + long mcause = read_csr(CSR_MCAUSE); + long mepc = read_csr(CSR_MEPC); + long mstatus = read_csr(CSR_MSTATUS); +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH + long mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { + /* Machine timer interrupt */ + mchtmr_isr(); + } +#ifdef USE_NONVECTOR_MODE + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { + + typedef void(*isr_func_t)(void); + + /* Machine-level interrupt from PLIC */ + uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + if (irq_index) { + /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ +#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#endif + ((isr_func_t)__vector_table[irq_index])(); + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + } +#endif + + else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { + /* Machine SWI interrupt */ + intc_m_claim_swi(); + swi_isr(); + intc_m_complete_swi(); + } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" + #ifdef __riscv_32e + "mv a0, t0\n" + #else + "mv a0, a7\n" + #endif + "jalr %0\n" + : :"r"(syscall_handler) : "a4" + ); + mepc += 4; + } else { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} diff --git a/common/libraries/hpm_sdk/soc/HPM5361/toolchains/vectors.h b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/vectors.h new file mode 100644 index 00000000..5cc24cd5 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/HPM5361/toolchains/vectors.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +.global default_irq_handler +.weak default_irq_handler +.align 2 +default_irq_handler: +1: j 1b + +.macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq +.endm + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, irq_handler_trap + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 5 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 6 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 7 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 8 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 9 /* LIN0 IRQ handler */ + IRQ_HANDLER 10 /* LIN1 IRQ handler */ + IRQ_HANDLER 11 /* LIN2 IRQ handler */ + IRQ_HANDLER 12 /* LIN3 IRQ handler */ + IRQ_HANDLER 13 /* UART0 IRQ handler */ + IRQ_HANDLER 14 /* UART1 IRQ handler */ + IRQ_HANDLER 15 /* UART2 IRQ handler */ + IRQ_HANDLER 16 /* UART3 IRQ handler */ + IRQ_HANDLER 17 /* UART4 IRQ handler */ + IRQ_HANDLER 18 /* UART5 IRQ handler */ + IRQ_HANDLER 19 /* UART6 IRQ handler */ + IRQ_HANDLER 20 /* UART7 IRQ handler */ + IRQ_HANDLER 21 /* I2C0 IRQ handler */ + IRQ_HANDLER 22 /* I2C1 IRQ handler */ + IRQ_HANDLER 23 /* I2C2 IRQ handler */ + IRQ_HANDLER 24 /* I2C3 IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* TSNS IRQ handler */ + IRQ_HANDLER 30 /* MBX0A IRQ handler */ + IRQ_HANDLER 31 /* MBX0B IRQ handler */ + IRQ_HANDLER 32 /* WDG0 IRQ handler */ + IRQ_HANDLER 33 /* WDG1 IRQ handler */ + IRQ_HANDLER 34 /* HDMA IRQ handler */ + IRQ_HANDLER 35 /* CAN0 IRQ handler */ + IRQ_HANDLER 36 /* CAN1 IRQ handler */ + IRQ_HANDLER 37 /* CAN2 IRQ handler */ + IRQ_HANDLER 38 /* CAN3 IRQ handler */ + IRQ_HANDLER 39 /* PTPC IRQ handler */ + IRQ_HANDLER 40 /* PWM0 IRQ handler */ + IRQ_HANDLER 41 /* QEI0 IRQ handler */ + IRQ_HANDLER 42 /* SEI0 IRQ handler */ + IRQ_HANDLER 43 /* MMC0 IRQ handler */ + IRQ_HANDLER 44 /* TRGMUX0 IRQ handler */ + IRQ_HANDLER 45 /* PWM1 IRQ handler */ + IRQ_HANDLER 46 /* QEI1 IRQ handler */ + IRQ_HANDLER 47 /* SEI1 IRQ handler */ + IRQ_HANDLER 48 /* MMC1 IRQ handler */ + IRQ_HANDLER 49 /* TRGMUX1 IRQ handler */ + IRQ_HANDLER 50 /* RDC IRQ handler */ + IRQ_HANDLER 51 /* USB0 IRQ handler */ + IRQ_HANDLER 52 /* XPI0 IRQ handler */ + IRQ_HANDLER 53 /* SDP IRQ handler */ + IRQ_HANDLER 54 /* PSEC IRQ handler */ + IRQ_HANDLER 55 /* SECMON IRQ handler */ + IRQ_HANDLER 56 /* RNG IRQ handler */ + IRQ_HANDLER 57 /* FUSE IRQ handler */ + IRQ_HANDLER 58 /* ADC0 IRQ handler */ + IRQ_HANDLER 59 /* ADC1 IRQ handler */ + IRQ_HANDLER 60 /* DAC0 IRQ handler */ + IRQ_HANDLER 61 /* DAC1 IRQ handler */ + IRQ_HANDLER 62 /* ACMP_0 IRQ handler */ + IRQ_HANDLER 63 /* ACMP_1 IRQ handler */ + IRQ_HANDLER 64 /* SYSCTL IRQ handler */ + IRQ_HANDLER 65 /* PGPIO IRQ handler */ + IRQ_HANDLER 66 /* PTMR IRQ handler */ + IRQ_HANDLER 67 /* PUART IRQ handler */ + IRQ_HANDLER 68 /* PWDG IRQ handler */ + IRQ_HANDLER 69 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 70 /* PAD_WAKEUP IRQ handler */ + IRQ_HANDLER 71 /* DEBUG0 IRQ handler */ + IRQ_HANDLER 72 /* DEBUG1 IRQ handler */ + diff --git a/common/libraries/hpm_sdk/soc/HPM6280/HPM6280_svd.xml b/common/libraries/hpm_sdk/soc/HPM6280/HPM6280_svd.xml index b617ddd6..f0834167 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/HPM6280_svd.xml +++ b/common/libraries/hpm_sdk/soc/HPM6280/HPM6280_svd.xml @@ -42,14 +42,14 @@ 0xc0000 0x0 - 0x800 + 0x824 registers 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz DI[%s] no description available 0x0 @@ -76,7 +76,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz DO[%s] no description available 0x100 @@ -160,7 +160,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz OE[%s] no description available 0x200 @@ -244,7 +244,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz IF[%s] no description available 0x300 @@ -271,7 +271,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz IE[%s] no description available 0x400 @@ -355,7 +355,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz PL[%s] no description available 0x500 @@ -439,7 +439,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz TP[%s] no description available 0x600 @@ -523,7 +523,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz AS[%s] no description available 0x700 @@ -997,7 +997,7 @@ Note: combinational interrupt is sensitive to environment noise 16 0x80 - gpioa,gpiob,gpioc,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz ASSIGN[%s] no description available 0x0 @@ -1311,24 +1311,6 @@ If cont_en is 0, this bit is not used - - seq_wr_addr - No description avaiable - 0x808 - 32 - 0x00000000 - 0x00FFFFFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 24 - read-only - - - seq_dma_cfg No description avaiable @@ -1509,7 +1491,7 @@ it may be updated period according to config, also may be updated due to other q CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 22 adc clock cycles(based on clock after divider); + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz). 4 @@ -1583,14 +1565,14 @@ Adc_clk must to be set to same as bus clock at this mode interrupt for one trigger conversion complete if enabled 31 1 - write-only + read-write TRIG_SW_CFLCT No description avaiable 30 1 - write-only + read-write TRIG_HW_CFLCT @@ -1604,14 +1586,14 @@ Adc_clk must to be set to same as bus clock at this mode read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel 28 1 - write-only + read-write SEQ_SW_CFLCT sequence queue conflict interrup, set if HW or SW trigger received during conversion 27 1 - write-only + read-write SEQ_HW_CFLCT @@ -1625,21 +1607,21 @@ Adc_clk must to be set to same as bus clock at this mode dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set 25 1 - write-only + read-write SEQ_CMPT the whole sequence complete interrupt 24 1 - write-only + read-write SEQ_CVC one conversion complete in seq_queue if related seq_int_en is set 23 1 - write-only + read-write DMA_FIFO_FULL @@ -1660,7 +1642,7 @@ Adc_clk must to be set to same as bus clock at this mode set if one chanel watch dog event triggered 0 14 - write-only + read-write @@ -1677,14 +1659,14 @@ Adc_clk must to be set to same as bus clock at this mode interrupt for one trigger conversion complete if enabled 31 1 - write-only + read-write TRIG_SW_CFLCT No description avaiable 30 1 - write-only + read-write TRIG_HW_CFLCT @@ -1698,14 +1680,14 @@ Adc_clk must to be set to same as bus clock at this mode read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel 28 1 - write-only + read-write SEQ_SW_CFLCT sequence queue conflict interrup, set if HW or SW trigger received during conversion 27 1 - write-only + read-write SEQ_HW_CFLCT @@ -1719,21 +1701,21 @@ Adc_clk must to be set to same as bus clock at this mode dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set 25 1 - write-only + read-write SEQ_CMPT the whole sequence complete interrupt 24 1 - write-only + read-write SEQ_CVC one conversion complete in seq_queue if related seq_int_en is set 23 1 - write-only + read-write DMA_FIFO_FULL @@ -1754,7 +1736,7 @@ Adc_clk must to be set to same as bus clock at this mode set if one chanel watch dog event triggered 0 14 - write-only + read-write @@ -1826,15 +1808,8 @@ MUST set clock_period to 0 or 1 for adc16 reg access 0x1444 32 0x00000000 - 0x03F07FFF + 0x01F07FFF - - TEMPSNS_EN - set to enable temp senser - 25 - 1 - read-write - REG_EN set to enable regulator @@ -1932,13 +1907,6 @@ should set to (21-convert_clock_number+1). 1 read-write - - RESERVED - No description avaiable - 26 - 5 - read-write - CHMD Channel Rcv mode @@ -1995,13 +1963,6 @@ Others: Undefined 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 8 - 24 - read-write - CH3DRY Ch3 Data Ready interrupt enable. @@ -2068,13 +2029,6 @@ Others: Undefined 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 8 - 24 - read-only - CH3DRY Ch3 Data Ready. @@ -2151,13 +2105,6 @@ De-assert this bit by write-1-clear the corresponding error status bits in the c 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 9 - 23 - read-write - THRSH FIFO threshold (0,..,16) (fillings > threshold, then gen int) @@ -2165,13 +2112,6 @@ De-assert this bit by write-1-clear the corresponding error status bits in the c 5 read-write - - RESERVED - No description avaiable - 3 - 1 - read-write - D_RDY_INT_EN FIFO data ready interrupt enable @@ -2179,13 +2119,6 @@ De-assert this bit by write-1-clear the corresponding error status bits in the c 1 read-write - - RESERVED - No description avaiable - 0 - 2 - read-write - @@ -2308,13 +2241,6 @@ De-assert this bit by write-1-clear the corresponding error status bits in the c 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 19 - 13 - read-write - SGD_ORDR CIC order @@ -2333,13 +2259,6 @@ De-assert this bit by write-1-clear the corresponding error status bits in the c 1 read-write - - RESERVED - No description avaiable - 15 - 1 - read-write - CIC_SCL CIC shift control @@ -2372,13 +2291,6 @@ Zero: Store all samples 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 31 - 1 - read-only - PERIOD_MCLK maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. @@ -2386,13 +2298,6 @@ Zero: Store all samples 8 read-only - - RESERVED - No description avaiable - 10 - 13 - read-only - FIFO_DR FIFO data ready @@ -2479,13 +2384,6 @@ Zero: Store all samples 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 16 - 16 - read-only - VAL instant Amplitude Results @@ -2503,13 +2401,6 @@ Zero: Store all samples 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 16 - 16 - read-write - VAL Amplitude Threshold for High Limit @@ -2527,13 +2418,6 @@ Zero: Store all samples 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 16 - 16 - read-write - VAL Amplitude Threshold for zero crossing @@ -2551,13 +2435,6 @@ Zero: Store all samples 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 16 - 16 - read-write - VAL Amplitude Threshold for low limit @@ -2575,13 +2452,6 @@ Zero: Store all samples 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 24 - 8 - read-write - HZ_EN Zero Crossing Enable @@ -2621,13 +2491,6 @@ Zero: Store all samples 2 read-write - - RESERVED - No description avaiable - 9 - 9 - read-write - CIC_DEC_RATIO CIC decimation ratio. 0 means div-by-32 @@ -2660,13 +2523,6 @@ Zero: Use all samples 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 4 - 28 - read-only - HZ Amplitude rising above HZ event found. @@ -2999,7 +2855,10 @@ Should only be used in buffer mode. DAC_MODE 00: direct mode, DAC output the fixed configured data(from sw_dac_data) 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down -10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; +11: trigger mode, DAC output from external trigger signals +Note: +Trigger mode is not supported in hpm63xx and hpm62xx families. 4 2 write-only @@ -3034,7 +2893,8 @@ others are reserved ANA_CLK_EN - set to enable analog clock(divided by ana_div_cfg) + set to enable analog clock(divided by ana_div_cfg) +need to be set in direct mode and trigger mode 18 1 read-write @@ -3052,8 +2912,12 @@ others are reserved DIV_CFG - how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. -Used for step mode and buffer mode, if set to continual trigger mode + step mode and buffer mode: + defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. +Direct mode and trigger mode: + defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. +Note: +For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. 0 16 read-write @@ -3517,8 +3381,8 @@ others are reserved SPI 0xf0030000 - 0x0 - 0x80 + 0x10 + 0x70 registers @@ -3530,13 +3394,6 @@ others are reserved 0x00020780 0xFFFF1F9F - - RESERVED - No description avaiable - 18 - 14 - read-write - ADDRLEN Address length in bytes @@ -4244,8 +4101,8 @@ When an SPI transaction other than slave status-reading command ends, this bit w UART 0xf0040000 - 0x0 - 0x40 + 0x4 + 0x3c registers @@ -4293,13 +4150,6 @@ it should be enabled if enable address match feature 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 2 - 30 - read-write - FIFOSIZE The depth of RXFIFO and TXFIFO @@ -4338,6 +4188,7 @@ OSC<=8: The over-sample ratio is 8 RBR Receiver Buffer Register (when DLAB = 0) + UNION_20 0x20 32 0x00000000 @@ -4355,6 +4206,7 @@ OSC<=8: The over-sample ratio is 8 THR Transmitter Holding Register (when DLAB = 0) + UNION_20 0x20 32 0x00000000 @@ -4372,6 +4224,7 @@ OSC<=8: The over-sample ratio is 8 DLL Divisor Latch LSB (when DLAB = 1) + UNION_20 0x20 32 0x00000001 @@ -4389,6 +4242,7 @@ OSC<=8: The over-sample ratio is 8 IER Interrupt Enable Register (when DLAB = 0) + UNION_24 0x24 32 0x00000000 @@ -4446,6 +4300,7 @@ character timeout interrupt DLM Divisor Latch MSB (when DLAB = 1) + UNION_24 0x24 32 0x00000000 @@ -4463,6 +4318,7 @@ character timeout interrupt IIR Interrupt Identification Register + UNION_28 0x28 32 0x00000001 @@ -4499,6 +4355,7 @@ Register (FIFOE) is set to 1. FCR FIFO Control Register + UNION_28 0x28 32 0x00000000 @@ -4803,6 +4660,23 @@ register is read. + + GPR + GPR Register + 0x3c + 32 + 0x00000000 + 0x000000FF + + + DATA + An one-byte storage register + 0 + 8 + read-write + + + @@ -4859,8 +4733,8 @@ register is read. MCAN 0xf0080000 - 0x0 - 0x2a00 + 0x4 + 0x29fc registers @@ -4902,7 +4776,8 @@ The endianness test value is 0x87654321. DBRP Data Bit Rate Prescaler -The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. +The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. +When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 16 5 read-write @@ -5283,7 +5158,8 @@ Configures the timestamp and timeout counters time unit in multiples of CAN bit TSC Timestamp Counter -The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. +The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. +A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. 0 16 read-only @@ -5309,7 +5185,8 @@ Start value of the Timeout Counter (down-counter). Configures the Timeout Period TOS Timeout Select -When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. +When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. +When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00= Continuous operation 01= Timeout controlled by Tx Event FIFO 10= Timeout controlled by Rx FIFO 0 @@ -5340,7 +5217,8 @@ When operating in Continuous mode, a write to TOCV presets the counter to the va TOC Timeout Counter -The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. +The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. +When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. 0 16 @@ -5359,7 +5237,8 @@ Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2 CEL CAN Error Logging -The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. +The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. +The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. 16 @@ -5405,7 +5284,8 @@ Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC a TDCV Transmitter Delay Compensation Value -Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. +Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. +The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. 16 7 read-only @@ -5514,12 +5394,16 @@ The LEC indicates the type of the last error to occur on the CAN bus. This field 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus value was dominant. -5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at +5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. + During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. -Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. +Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. + Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. +At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, +enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. 0 3 @@ -5546,7 +5430,8 @@ Offset value defining the distance between the measured delay from m_can_tx to m TDCF Transmitter Delay Compensation Filter Window Length -Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. +Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. +The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. 0 7 read-write @@ -5636,7 +5521,8 @@ Defines the minimum value for the SSP position, dominant edges on m_can_rx that BEU Bit Error Uncorrected -Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. +Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. +An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. 0= No bit error detected when reading from Message RAM 1= Bit error detected, uncorrected (e.g. parity logic) 21 @@ -6430,7 +6316,8 @@ Start address of extended Message ID filter list (32-bit word address). EIDM Extended ID Mask -For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. +For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. + Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. 0 29 read-write @@ -6495,7 +6382,8 @@ Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] ND1 New Data[31:0] -The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. +The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. +The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message 0 @@ -6515,7 +6403,8 @@ The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set w ND2 New Data[63:32] -The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. +The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. +The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message 0 @@ -6638,7 +6527,8 @@ Number of elements stored in Rx FIFO 0, range 0 to 64. F0AI Rx FIFO 0 Acknowledge Index -After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. +After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. +This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. 0 6 read-write @@ -6788,7 +6678,8 @@ Number of elements stored in Rx FIFO 1, range 0 to 64. F1AI Rx FIFO 1 Acknowledge Index -After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. +After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. +This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. 0 6 read-write @@ -6844,7 +6735,8 @@ After the Host has read a message or a sequence of messages from Rx FIFO 1 it ha 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field -Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. +Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, +only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. 0 3 read-write @@ -6987,7 +6879,8 @@ Each Tx Buffer has its own Transmission Request Pending bit. The bits are set vi TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). -A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. +A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, +this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signalled via TXBCF ? after successful transmission together with the corresponding TXBTO bit ? when the transmission has not yet been started at the point of cancellation @@ -7037,7 +6930,8 @@ Note: If an add request is applied for a Tx Buffer with pending transmission req CR Cancellation Request -Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. +Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. +This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0= No cancellation pending 1= Cancellation pending 0 @@ -7077,7 +6971,8 @@ Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the CF Cancellation Finished -Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. +Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. +In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. 0= No transmit buffer cancellation 1= Transmit buffer cancellation finished 0 @@ -7473,7 +7368,7 @@ Value also signalled on output m_can_tsp[3:0]. 0x400 32 0x00000000 - 0xE0000007 + 0xE0000003 M_CAN_STBY @@ -7500,9 +7395,9 @@ Value also signalled on output m_can_tsp[3:0]. TSU_TBIN_SEL - No description avaiable + external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 0 - 3 + 2 read-write @@ -7577,8 +7472,8 @@ Value also signalled on output m_can_tsp[3:0]. WDOG 0xf0090000 - 0x0 - 0x20 + 0x10 + 0x10 registers @@ -7744,7 +7639,7 @@ Restart Register. 0xf00a0000 0x0 - 0x30 + 0x24 registers @@ -7763,13 +7658,6 @@ Restart Register. 1 read-write - - RESERVED - Reserved - 16 - 15 - read-only - BARCTL Bus Acccess Response Control, when bit 15:14= @@ -7781,13 +7669,6 @@ Restart Register. 2 read-write - - RESERVED - Reserved - 9 - 5 - read-only - BEIE Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. @@ -7833,13 +7714,6 @@ Restart Register. 1 read-write - - RESERVED - Reserved - 2 - 2 - read-only - TWMEIE TX word message empty interrupt enable. @@ -7868,13 +7742,6 @@ Restart Register. 0x000000E2 0xFFFF3FFF - - RESERVED - Not used - 24 - 8 - read-only - RFVC RX FIFO valid message count @@ -7979,13 +7846,6 @@ Restart Register. 1 read-only - - RESERVED - Not used - 2 - 2 - read-only - TWME TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. @@ -8041,9 +7901,9 @@ Restart Register. - 4 + 1 0x4 - TXFIFO0,TXFIFO1,TXFIFO2,TXFIFO3 + TXFIFO0 TXWRD[%s] no description available 0x10 @@ -8063,9 +7923,9 @@ can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 4 + 1 0x4 - RXFIFO0,RXFIFO1,RXFIFO2,RXFIFO3 + RXFIFO0 RXWRD[%s] no description available 0x20 @@ -8111,7 +7971,7 @@ can also use 4x32 burst read from 0x020 to read 4 words from the FIFO.0xf00b0000 0x0 - 0x200c + 0x3004 registers @@ -8162,13 +8022,6 @@ If this bit is cleared, capture result will be updated at each capture event1 read-write - - RESERVED - No description avaiable - 5 - 1 - read-write - COMP_EN set to enable compare, will be cleared by HW when compare event triggered @@ -8192,8 +8045,8 @@ If this bit is cleared, capture result will be updated at each capture event FINE_COARSE_SEL - 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow -1: coarse update, ns counter add ss_incr[7:0] each clk + 0: coarse update, ns counter add ss_incr[7:0] each clk +1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow 1 1 read-write @@ -8547,35 +8400,73 @@ clr to use ptpc0 for canx - - - - CRC - CRC - CRC - 0xf00b8000 - - 0x0 - 0x200 - registers - - - - 8 - 0x40 - 0,1,2,3,4,5,6,7 - CHN[%s] - no description available - 0x0 - - pre_set - &index0 pre set for crc setting - 0x0 - 32 - 0x00000000 - 0x000000FF - - + + ptpc_can_ts_sel + No description avaiable + 0x3000 + 32 + 0x00000000 + 0xFFFFFF00 + + + TSU_TBIN3_SEL + No description avaiable + 26 + 6 + read-write + + + TSU_TBIN2_SEL + No description avaiable + 20 + 6 + read-write + + + TSU_TBIN1_SEL + No description avaiable + 14 + 6 + read-write + + + TSU_TBIN0_SEL + No description avaiable + 8 + 6 + read-write + + + + + + + CRC + CRC + CRC + 0xf00b8000 + + 0x0 + 0x200 + registers + + + + 8 + 0x40 + 0,1,2,3,4,5,6,7 + CHN[%s] + no description available + 0x0 + + pre_set + &index0 pre set for crc setting + 0x0 + 32 + 0x00000000 + 0x000000FF + + PRE_SET 0: no pre set 1: CRC32 @@ -8802,8 +8693,8 @@ Specifies which DMA source, if any, is routed to a particular DMA channel. See t DMA 0xf00c4000 - 0x0 - 0x140 + 0x4 + 0x13c registers @@ -9373,13 +9264,6 @@ This register exists only when the address bus width is wider than 32 bits.0x00000000 0xFFFFFFFF - - RESERVED - Not used - 7 - 25 - read-write - SFTRST Soft Reset, Perform a software reset of the RNG This bit is self-clearing. @@ -9407,13 +9291,6 @@ This register exists only when the address bus width is wider than 32 bits.1 read-write - - RESERVED - Not used - 2 - 2 - read-only - GENSD Generate Seed, when both ST and GS triggered, ST first and GS next. @@ -9438,13 +9315,6 @@ This register exists only when the address bus width is wider than 32 bits.0x00000000 0xFFFFFFFF - - RESERVED - Not used - 7 - 25 - read-only - MIRQERR Mask Interrupt Request for Error @@ -9468,13 +9338,6 @@ This register exists only when the address bus width is wider than 32 bits.1 read-write - - RESERVED - Not used - 2 - 2 - read-only - FUFMOD FIFO underflow response mode @@ -9496,13 +9359,6 @@ This register exists only when the address bus width is wider than 32 bits.0x00000000 0xFFFFFFFF - - RESERVED - Not used - 24 - 8 - read-only - SCPF Self Check Pass Fail @@ -9510,13 +9366,6 @@ This register exists only when the address bus width is wider than 32 bits.3 read-only - - RESERVED - Not used - 17 - 4 - read-only - FUNCERR Error was detected, check ESR register for details @@ -9538,13 +9387,6 @@ This register exists only when the address bus width is wider than 32 bits.4 read-only - - RESERVED - Not used - 7 - 1 - read-only - NSDDN New seed done. @@ -9594,13 +9436,6 @@ automatically if the CTRL[ARS] is set. 1 read-only - - RESERVED - Not used - 0 - 1 - read-only - @@ -9611,33 +9446,6 @@ automatically if the CTRL[ARS] is set. 0x00000000 0xFFFFFF3F - - RESERVED - OSC1 Satistics test pass failed. -Indicates the pass or fail status of the various statistics tests on the last seed generated. -0 Pass -1 Fail - 24 - 8 - read-only - - - RESERVED - OSC0 Satistics test pass failed. -Indicates the pass or fail status of the various statistics tests on the last seed generated. -0 Pass -1 Fail - 16 - 8 - read-only - - - RESERVED - Not used - 8 - 8 - read-only - FUFE FIFO access error(underflow) @@ -9645,17 +9453,6 @@ Indicates the pass or fail status of the various statistics tests on the last se 1 read-only - - RESERVED - Statistical test error -Indicates whether the statistical tests for the last generated seed was failed or not. This bit is sticky and is -cleared by a hardware or software reset or by writing 1 to the CMD[CE]. -0 No fail for the statistical tests. -1 Failed the statistical tests during the initialization - 4 - 1 - read-only - SCKERR Self-test error @@ -9665,30 +9462,6 @@ hardware reset or by writing 1 to the CMD[CE] 1 read-only - - RESERVED - Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a -software or hardware reset. - 2 - 1 - read-only - - - RESERVED - Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a -software or hardware reset. - 1 - 1 - read-only - - - RESERVED - Linear feedback shift register (LFSR) error -When this bit is set, the interrupt generated was caused by a failure of one of the LFSRs in any of the RNG LFSR ciruit. - 0 - 1 - read-only - @@ -9977,7 +9750,7 @@ bit2: software key 0: not selected, 1:selected 0xf0200000 0x0 - 0x42c + 0x424 registers @@ -10002,6 +9775,7 @@ otherwise the shadow registers can not be written. sta Counter start register + UNION_STA 0x4 32 0x00000000 @@ -10022,18 +9796,12 @@ otherwise the shadow registers can not be written. 24 read-write - - RESERVED - reserved - 0 - 4 - read-write - sta_hrpwm Counter start register + UNION_STA 0x4 32 0x00000000 @@ -10051,6 +9819,7 @@ otherwise the shadow registers can not be written. rld Counter reload register + UNION_RLD 0x8 32 0x00000000 @@ -10070,18 +9839,12 @@ otherwise the shadow registers can not be written. 24 read-write - - RESERVED - reserved - 0 - 4 - read-write - rld_hrpwm Counter reload register + UNION_RLD 0x8 32 0x00000000 @@ -10104,9 +9867,9 @@ otherwise the shadow registers can not be written. - 24 + 16 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 CMP[%s] no description available 0xc @@ -10146,9 +9909,9 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c - 24 + 16 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 CMP_HRPWM[%s] no description available 0xc @@ -10211,9 +9974,9 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c - 24 + 16 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 CHCFG[%s] no description available 0x80 @@ -10221,13 +9984,6 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c 0x00000000 0xFFFF0003 - - RESERVED - read as 0 - 29 - 3 - read-write - CMPSELEND assign the last comparator for this output channel @@ -10235,13 +9991,6 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c 5 read-write - - RESERVED - read as 0 - 21 - 3 - read-write - CMPSELBEG assign the first comparator for this output channel @@ -10256,13 +10005,6 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c 1 read-write - - RESERVED - read as 0 - 0 - 1 - read-write - @@ -10504,9 +10246,9 @@ User should write 1 to this bit after the active FAULT signal de-assert and befo - 24 + 16 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 CAPPOS[%s] no description available 0x100 @@ -10545,19 +10287,12 @@ User should write 1 to this bit after the active FAULT signal de-assert and befo 24 read-only - - RESERVED - read-only as 0 - 0 - 4 - read-only - - 24 + 16 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 CAPNEG[%s] no description available 0x180 @@ -10596,13 +10331,6 @@ User should write 1 to this bit after the active FAULT signal de-assert and befo 24 read-only - - RESERVED - read-only as 0 - 0 - 4 - read-only - @@ -10832,9 +10560,9 @@ Note: user should configure pair bit and this bitfield before PWM output is enab - 24 + 16 0x4 - cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 + cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 CMPCFG[%s] no description available 0x230 @@ -10870,13 +10598,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 0 - 1 - read-only - @@ -10966,13 +10687,6 @@ each bit for one channel. 1 write-only - - RESERVED - reserved - 16 - 1 - read-write - SNAPEN 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert @@ -10980,13 +10694,6 @@ each bit for one channel. 1 read-write - - RESERVED - reserved - 5 - 1 - read-write - RSTCNT set to reset all counter and related snapshots @@ -10994,20 +10701,6 @@ each bit for one channel. 1 read-write - - RESERVED - reserved - 2 - 2 - read-write - - - RESERVED - reserved - 0 - 2 - read-write - @@ -11027,13 +10720,6 @@ each bit for one channel. 1 read-write - - RESERVED - reserved - 24 - 7 - read-write - DLYCNT delay clock cycles number @@ -11075,13 +10761,6 @@ each bit for one channel. 0x00000000 0x07FFFFFF - - RESERVED - reserved - 24 - 3 - read-write - PRECNT the clock cycle number which the pre flag will set before the next uvw transition @@ -11127,34 +10806,6 @@ each bit for one channel. 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UFEN 1- enable trigger output when u flag set @@ -11214,34 +10865,6 @@ each bit for one channel. 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UFEN 1- load counters to their read registers when u flag set @@ -11301,34 +10924,6 @@ each bit for one channel. 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UFEN 1- generate dma request when u flag set @@ -11388,34 +10983,6 @@ each bit for one channel. 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UF u flag, will set when u signal toggle @@ -11475,34 +11042,6 @@ each bit for one channel. 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UFIE 1- generate interrupt request when u flag set @@ -11558,20 +11097,6 @@ each bit for one channel. 0x00000000 0xCFFFFFFF - - RESERVED - reserved - 31 - 1 - read-only - - - RESERVED - reserved - 30 - 1 - read-only - VCNT vcnt counter @@ -11817,15 +11342,6 @@ each bit for one channel. 1 read-write - - RESERVED - 00-x1, phase_cnt will increase at each A posedge -01-x2, phase_cnt will increase at each A/B posedge -10-x4, phase_cnt will increase at each edge(A/B, pos/neg) - 2 - 2 - read-write - ENCTYP 00-abz; 01-pd; 10-ud; 11-reserved @@ -13983,8 +13499,8 @@ each bit for one channel. USB 0xf2020000 - 0x0 - 0x228 + 0x80 + 0x1a8 registers @@ -14718,6 +14234,7 @@ The bit field values description below is represented as (Frame List Size) Numbe DEVICEADDR Device Address Register + UNION_154 0x154 32 0x00000000 @@ -14753,6 +14270,7 @@ If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (be PERIODICLISTBASE Frame List Base Address Register + UNION_154 0x154 32 0x00000000 @@ -14773,6 +14291,7 @@ Only used by the host controller. ASYNCLISTADDR Next Asynch. Address Register + UNION_158 0x158 32 0x00000000 @@ -14794,6 +14313,7 @@ Only used by the host controller. ENDPTLISTADDR Endpoint List Address Register + UNION_158 0x158 32 0x00000000 @@ -16014,13 +15534,6 @@ This bit will be auto cleared after 1 cycle 1 write-only - - RESERVED - not exist - 18 - 13 - read-write - CNTRST 1- reset counter @@ -16268,13 +15781,6 @@ User should set this bit before set CMPEN to 1. 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 16 - 16 - read-write - CH3CMP1F channel 3 compare value 1 match flag @@ -16397,13 +15903,6 @@ User should set this bit before set CMPEN to 1. 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 16 - 16 - read-write - CH3CMP1EN 1- generate interrupt request when ch3cmp1f flag is set @@ -16567,8 +16066,8 @@ User should set this bit before set CMPEN to 1. I2C 0xf3020000 - 0x0 - 0x34 + 0x4 + 0x30 registers @@ -16580,13 +16079,6 @@ User should set this bit before set CMPEN to 1. 0x00000001 0xFFFFFFFF - - RESERVED - No description avaiable - 2 - 30 - read-write - FIFOSIZE FIFO Size: @@ -16608,13 +16100,6 @@ User should set this bit before set CMPEN to 1. 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 10 - 22 - read-write - CMPL Set to enable the Completion Interrupt. @@ -16711,13 +16196,6 @@ Interrupts when the FIFO is empty. 0x00000001 0xFFFFFFFF - - RESERVED - No description avaiable - 15 - 17 - read-write - LINESDA Indicates the current status of the SDA line on the bus @@ -16847,13 +16325,6 @@ Slave: indicates that a transaction is targeting the controller (including the G 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 10 - 22 - read-write - ADDR The slave address. @@ -16872,13 +16343,6 @@ For 7-bit addressing mode, the most significant 3 bits are ignored and only the 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 8 - 24 - read-write - DATA Write this register to put one byte of data to the FIFO. @@ -16897,13 +16361,6 @@ Read this register to get one byte of data from the FIFO. 0x00001E00 0x000F9FFF - - RESERVED - No description avaiable - 15 - 5 - read-write - PHASE_START Enable this bit to send a START condition at the beginning of transaction. @@ -16970,13 +16427,6 @@ If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will n 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 3 - 29 - read-write - CMD Write this register with the following values to perform the corresponding actions: @@ -17002,13 +16452,6 @@ Note: No transaction will be issued by the controller when all phases (Start, Ad 0x05252100 0xFFFFFFFF - - RESERVED - No description avaiable - 29 - 3 - read-write - T_SUDAT T_SUDAT defines the data setup time before releasing the SCL. @@ -17035,13 +16478,6 @@ Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) 5 read-write - - RESERVED - No description avaiable - 14 - 2 - read-write - T_SCLRADIO The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. @@ -17109,13 +16545,6 @@ This field is only valid when the controller is in the master mode.0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 5 - 27 - read-write - TPM A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). @@ -17546,13 +16975,6 @@ Write to 1 will clock gate for most logic of the SDP block, dynamic power saving 1 read-only - - RESERVED - Not used - 24 - 4 - read-only - CIPHEN Cipher Enablement, controlled by SW. @@ -17596,13 +17018,6 @@ Write to 1 will clock gate for most logic of the SDP block, dynamic power saving 1 read-write - - RESERVED - Reserved - 18 - 1 - read-write - TSTPKT0IRQ Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. @@ -17684,13 +17099,6 @@ Other values, reserved. 6 read-write - - RESERVED - Not used - 17 - 1 - read-only - AESDIR AES direction @@ -17736,21 +17144,7 @@ For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. 9 1 - read-write - - - RESERVED - Not used - 8 - 1 - read-only - - - RESERVED - Not used - 6 - 2 - read-only + read-write DINSWP @@ -17785,27 +17179,6 @@ When all bits are set, the data is assumed to be in the big-endian format0x00000000 0xFFFFFFFF - - RESERVED - Not used - 31 - 1 - read-write - - - RESERVED - Not used - 30 - 1 - read-write - - - RESERVED - Not used - 24 - 6 - read-only - CNTVAL This read-only field shows the current (instantaneous) value of the packet counter @@ -17813,13 +17186,6 @@ When all bits are set, the data is assumed to be in the big-endian format8 read-only - - RESERVED - Not used - 8 - 8 - read-only - CNTINCR The value written to this field is added to the spacket count. @@ -17851,13 +17217,6 @@ When all bits are set, the data is assumed to be in the big-endian format1 write-only - - RESERVED - Not used - 21 - 2 - read-only - CHN1PKT0 the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. @@ -17893,13 +17252,6 @@ When all bits are set, the data is assumed to be in the big-endian format1 write-only - - RESERVED - Not used - 6 - 10 - read-only - ERRSET Working mode setup error. @@ -17952,13 +17304,6 @@ When all bits are set, the data is assumed to be in the big-endian format0x00000040 0xFFFFFFFF - - RESERVED - Not used - 24 - 8 - read-only - INDEX To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. @@ -17968,13 +17313,6 @@ In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys 8 read-write - - RESERVED - Not used - 2 - 14 - read-only - SUBWRD Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field @@ -18096,13 +17434,6 @@ descriptor that is to be executed (or is currently being executed) 8 read-write - - RESERVED - Not used - 7 - 17 - read-write - CIPHIV Load Initial Vector for the AES in this packet. @@ -18147,13 +17478,6 @@ When the semaphore reaches a value of zero, no more operations are issued from t 1 read-write - - RESERVED - Not used - 0 - 1 - read-write - @@ -18221,9 +17545,9 @@ When the semaphore reaches a value of zero, no more operations are issued from t - 166 + 134 0x4 - cpu0,cpx0,exe0,wak0,cpu0_per,cpu1,cpx1,exe1,wak1,cpu1_per,logic0,logic1,logic2,logic3,pmic,pow_cpu0,pow_cpu1,rst_soc,rst_cpu0,rst_cpu1,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_pll2,clk_src_clk0_pll2,clk_src_clk1_pll2,clk_src_pll0_ref,clk_src_pll1_ref,clk_src_pll2_ref,mbist_soc,mbist_cpu0,mbist_cpu1,mbist_con,dft_start_bus,clk_top_cpu0,clk_top_mct0,clk_top_mct1,clk_top_xpi0,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ana4,clk_top_ref0,clk_top_ref1,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_dac0,clk_top_dac1,usb0_mem,rom0_mem,ram0_mem,ahbp_mem,xpi0_mem,can0_mem,can1_mem,can2_mem,can3_mem,sdp0_mem,cpx0_mem,cor0_mem,lmm0_mem,cpx1_mem,cor1_mem,lmm1_mem,ahbp,axis,axic,lmm0,mct0,lmm1,mct1,rom0,ram0,i2c0,i2c1,i2c2,i2c3,tmr0,tmr1,tmr2,tmr3,gpio,adc0,adc1,adc2,dac0,dac1,acmp,spi0,spi1,spi2,spi3,sdm0,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,lin0,lin1,lin2,lin3,ptpc,can0,can1,can2,can3,wdg0,wdg1,mbx0,mbx1,crc0,mot0,mot1,mot2,mot3,msyn,xpi0,hdma,xdma,kman,sdp0,rng0,tsns,usb0,ref0,ref1 + cpu0,cpx0,cpu1,cpx1,pow_cpu0,pow_cpu1,rst_soc,rst_cpu0,rst_cpu1,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_pll2,clk_src_clk0_pll2,clk_src_clk1_pll2,clk_src_pll0_ref,clk_src_pll1_ref,clk_src_pll2_ref,clk_top_cpu0,clk_top_mct0,clk_top_mct1,clk_top_xpi0,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ana4,clk_top_ref0,clk_top_ref1,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_dac0,clk_top_dac1,ahbp,axis,axic,lmm0,mct0,lmm1,mct1,rom0,ram0,i2c0,i2c1,i2c2,i2c3,tmr0,tmr1,tmr2,tmr3,gpio,adc0,adc1,adc2,dac0,dac1,acmp,spi0,spi1,spi2,spi3,sdm0,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,lin0,lin1,lin2,lin3,ptpc,can0,can1,can2,can3,wdg0,wdg1,mbx0,mbx1,crc0,mot0,mot1,mot2,mot3,msyn,xpi0,hdma,xdma,kman,sdp0,rng0,tsns,usb0,ref0,ref1 RESOURCE[%s] no description available 0x0 @@ -18263,9 +17587,9 @@ When the semaphore reaches a value of zero, no more operations are issued from t - 4 + 3 0x10 - link0,link1,link2,link3 + link0,link1,link2 GROUP0[%s] no description available 0x800 @@ -18347,9 +17671,9 @@ When the semaphore reaches a value of zero, no more operations are issued from t - 4 + 3 0x10 - link0,link1,link2,link3 + link0,link1,link2 GROUP1[%s] no description available 0x840 @@ -19493,7 +18817,7 @@ bit3: override to preset3 488 0x8 - pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,px00,px01,px02,px03,px04,px05,px06,px07,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,py00,py01,py02,py03,py04,py05,py06,py07,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07 + pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,rsv93,rsv94,rsv95,rsv96,rsv97,rsv98,rsv99,rsv100,rsv101,rsv102,rsv103,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,rsv416,px00,px01,px02,px03,px04,px05,px06,px07,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,rsv448,py00,py01,py02,py03,py04,py05,py06,py07,rsv457,rsv458,rsv459,rsv460,rsv461,rsv462,rsv463,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,rsv480,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07 PAD[%s] no description available 0x0 @@ -20445,7 +19769,7 @@ XX0: trun off 1: overcurrent happened in low power mode 24 1 - read-write + read-only DISABLE_POWER_LOSS @@ -22022,9 +21346,9 @@ This register should not be changed during PLL and spread spectrum enabled. If - 4 + 3 0x4 - DIV0,DIV1,DIV2,DIV3 + DIV0,DIV1,DIV2 DIV[%s] no description available 0x40 @@ -22480,6 +21804,114 @@ This register should not be changed during PLL and spread spectrum enabled. If + + BACC + BACC + BACC + 0xf5000000 + + 0x0 + 0x10 + registers + + + + CONFIG + Access timing for access + 0x0 + 32 + 0x00000000 + 0x3000FFFF + + + FAST_WRITE + Use fast write +0: Write normally +1: boost write + 29 + 1 + read-write + + + FAST_READ + Use fast read +0: Read normally +1: boost read + 28 + 1 + read-write + + + TIMING + Time in APB clock cycles, for battery timing penerate + 0 + 16 + read-write + + + + + PRE_TIME + Timing gap before rising edge + 0x8 + 32 + 0x00000000 + 0x000FFFFF + + + PRE_RATIO + Ratio of guard band before rising edge +0: 0 +1: 1/32768 of low level width +2: 1/16384 of low level width +14: 1/4 of low level width +15: 1/2 of low level width + 16 + 4 + read-write + + + PRE_OFFSET + guard band before rising edge +this value will be added to ratio number + 0 + 16 + read-write + + + + + POST_TIME + Timing gap after rising edge + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + POST_RATIO + Ratio of guard band after rising edge +0: 0 +1: 1/32768 of high level width +2: 1/16384 of high level width +14: 1/4 of high level width +15: 1/2 of high level width + 16 + 4 + read-write + + + POST_OFFSET + guard band after rising edge +this value will be added to ratio number + 0 + 16 + read-write + + + + + BPOR BPOR @@ -22487,7 +21919,7 @@ This register should not be changed during PLL and spread spectrum enabled. If 0xf5004000 0x0 - 0x14 + 0x10 registers @@ -22968,134 +22400,18 @@ bit3: button long long pressed - BATT_GPR0 - Generic control + 8 + 0x4 + 0,1,2,3,4,5,6,7 + GPR[%s] + no description available 0x0 32 0x00000000 0xFFFFFFFF - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR1 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR2 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR3 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR4 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR5 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR6 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR7 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR + DATA Generic control 0 32 @@ -23112,7 +22428,7 @@ bit3: button long long pressed 0xf5040000 0x0 - 0x18 + 0x14 registers @@ -23339,7 +22655,7 @@ bit3: button long long pressed 0xf5044000 0x0 - 0x2c + 0x28 registers @@ -23638,7 +22954,7 @@ bit3: button long long pressed 0xf504c000 0x0 - 0x24 + 0x20 registers @@ -23938,4 +23254,4 @@ Note, clear can only be cleared when tamper disapeared - \ No newline at end of file + diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h index 4c3bb66f..f24c986d 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_bgpr_regs.h @@ -10,106 +10,32 @@ #define HPM_BGPR_H typedef struct { - __RW uint32_t BATT_GPR0; /* 0x0: Generic control */ - __RW uint32_t BATT_GPR1; /* 0x4: Generic control */ - __RW uint32_t BATT_GPR2; /* 0x8: Generic control */ - __RW uint32_t BATT_GPR3; /* 0xC: Generic control */ - __RW uint32_t BATT_GPR4; /* 0x10: Generic control */ - __RW uint32_t BATT_GPR5; /* 0x14: Generic control */ - __RW uint32_t BATT_GPR6; /* 0x18: Generic control */ - __RW uint32_t BATT_GPR7; /* 0x1C: Generic control */ + __RW uint32_t GPR[8]; /* 0x0 - 0x1C: Generic control */ } BGPR_Type; -/* Bitfield definition for register: BATT_GPR0 */ +/* Bitfield definition for register array: GPR */ /* - * GPR (RW) + * DATA (RW) * * Generic control */ -#define BGPR_BATT_GPR0_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR0_GPR_SHIFT (0U) -#define BGPR_BATT_GPR0_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR0_GPR_SHIFT) & BGPR_BATT_GPR0_GPR_MASK) -#define BGPR_BATT_GPR0_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR0_GPR_MASK) >> BGPR_BATT_GPR0_GPR_SHIFT) +#define BGPR_GPR_DATA_MASK (0xFFFFFFFFUL) +#define BGPR_GPR_DATA_SHIFT (0U) +#define BGPR_GPR_DATA_SET(x) (((uint32_t)(x) << BGPR_GPR_DATA_SHIFT) & BGPR_GPR_DATA_MASK) +#define BGPR_GPR_DATA_GET(x) (((uint32_t)(x) & BGPR_GPR_DATA_MASK) >> BGPR_GPR_DATA_SHIFT) -/* Bitfield definition for register: BATT_GPR1 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR1_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR1_GPR_SHIFT (0U) -#define BGPR_BATT_GPR1_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR1_GPR_SHIFT) & BGPR_BATT_GPR1_GPR_MASK) -#define BGPR_BATT_GPR1_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR1_GPR_MASK) >> BGPR_BATT_GPR1_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR2 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR2_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR2_GPR_SHIFT (0U) -#define BGPR_BATT_GPR2_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR2_GPR_SHIFT) & BGPR_BATT_GPR2_GPR_MASK) -#define BGPR_BATT_GPR2_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR2_GPR_MASK) >> BGPR_BATT_GPR2_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR3 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR3_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR3_GPR_SHIFT (0U) -#define BGPR_BATT_GPR3_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR3_GPR_SHIFT) & BGPR_BATT_GPR3_GPR_MASK) -#define BGPR_BATT_GPR3_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR3_GPR_MASK) >> BGPR_BATT_GPR3_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR4 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR4_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR4_GPR_SHIFT (0U) -#define BGPR_BATT_GPR4_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR4_GPR_SHIFT) & BGPR_BATT_GPR4_GPR_MASK) -#define BGPR_BATT_GPR4_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR4_GPR_MASK) >> BGPR_BATT_GPR4_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR5 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR5_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR5_GPR_SHIFT (0U) -#define BGPR_BATT_GPR5_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR5_GPR_SHIFT) & BGPR_BATT_GPR5_GPR_MASK) -#define BGPR_BATT_GPR5_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR5_GPR_MASK) >> BGPR_BATT_GPR5_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR6 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR6_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR6_GPR_SHIFT (0U) -#define BGPR_BATT_GPR6_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR6_GPR_SHIFT) & BGPR_BATT_GPR6_GPR_MASK) -#define BGPR_BATT_GPR6_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR6_GPR_MASK) >> BGPR_BATT_GPR6_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR7 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR7_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR7_GPR_SHIFT (0U) -#define BGPR_BATT_GPR7_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR7_GPR_SHIFT) & BGPR_BATT_GPR7_GPR_MASK) -#define BGPR_BATT_GPR7_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR7_GPR_MASK) >> BGPR_BATT_GPR7_GPR_SHIFT) +/* GPR register group index macro definition */ +#define BGPR_GPR_0 (0UL) +#define BGPR_GPR_1 (1UL) +#define BGPR_GPR_2 (2UL) +#define BGPR_GPR_3 (3UL) +#define BGPR_GPR_4 (4UL) +#define BGPR_GPR_5 (5UL) +#define BGPR_GPR_6 (6UL) +#define BGPR_GPR_7 (7UL) #endif /* HPM_BGPR_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c b/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c index 04c48be7..11881770 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.c @@ -60,6 +60,11 @@ static uint32_t get_frequency_for_dac(uint32_t instance); */ static uint32_t get_frequency_for_wdg(uint32_t instance); +/** + * @brief Get Clock frequency for PWDG + */ +static uint32_t get_frequency_for_pwdg(void); + /** * @brief Turn on/off the IP clock */ @@ -105,6 +110,9 @@ uint32_t clock_get_frequency(clock_name_t clock_name) case CLK_SRC_GROUP_WDG: clk_freq = get_frequency_for_wdg(node_or_instance); break; + case CLK_SRC_GROUP_PWDG: + clk_freq = get_frequency_for_pwdg(); + break; case CLK_SRC_GROUP_PMIC: clk_freq = FREQ_PRESET1_OSC0_CLK0; break; @@ -236,7 +244,7 @@ static uint32_t get_frequency_for_wdg(uint32_t instance) uint32_t freq_in_hz; /* EXT clock is chosen */ if (WDG_CTRL_CLKSEL_GET(s_wdgs[instance]->CTRL) == 0) { - freq_in_hz = get_frequency_for_cpu(); + freq_in_hz = get_frequency_for_ahb(); } /* PCLK is chosen */ else { @@ -246,6 +254,18 @@ static uint32_t get_frequency_for_wdg(uint32_t instance) return freq_in_hz; } +static uint32_t get_frequency_for_pwdg(void) +{ + uint32_t freq_in_hz; + if (WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL) == 0) { + freq_in_hz = FREQ_PRESET1_OSC0_CLK0; + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + static uint32_t get_frequency_for_cpu(void) { uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); @@ -282,12 +302,22 @@ clk_src_t clock_get_source(clock_name_t clock_name) clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); } break; + case CLK_SRC_GROUP_DAC: + if (node_or_instance < DAC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_DAC; + clk_src_index = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[node_or_instance]); + } + break; case CLK_SRC_GROUP_WDG: if (node_or_instance < WDG_INSTANCE_NUM) { clk_src_group = CLK_SRC_GROUP_WDG; clk_src_index = (WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL) == 0); } break; + case CLK_SRC_GROUP_PWDG: + clk_src_group = CLK_SRC_GROUP_PWDG; + clk_src_index = (WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL) == 0); + break; case CLK_SRC_GROUP_PMIC: clk_src_group = CLK_SRC_GROUP_COMMON; clk_src_index = clock_source_osc0_clk0; @@ -325,7 +355,7 @@ hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) return status_clk_invalid; } - if ((src <= clk_adc_src_ahb0) || (src >= clk_adc_src_ana2)) { + if ((src < clk_adc_src_ana0) || (src > clk_adc_src_ahb0)) { return status_clk_src_invalid; } @@ -383,6 +413,15 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint } } break; + case CLK_SRC_GROUP_PWDG: + if (src == clk_pwdg_src_osc24m) { + HPM_PWDG->CTRL &= ~WDG_CTRL_CLKSEL_MASK; + } else if (src == clk_pwdg_src_osc32k) { + HPM_PWDG->CTRL |= WDG_CTRL_CLKSEL_MASK; + } else { + status = status_clk_src_invalid; + } + break; case CLK_SRC_GROUP_PMIC: status = status_clk_fixed; break; @@ -444,8 +483,6 @@ void clock_add_to_group(clock_name_t clock_name, uint32_t group) if (resource < sysctl_resource_end) { sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); - } else if (resource == RESOURCE_SHARED_PTPC) { - sysctl_enable_group_resource(HPM_SYSCTL, group, sysctl_resource_ptpc, true); } } @@ -455,11 +492,16 @@ void clock_remove_from_group(clock_name_t clock_name, uint32_t group) if (resource < sysctl_resource_end) { sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); - } else if (resource == RESOURCE_SHARED_PTPC) { - sysctl_enable_group_resource(HPM_SYSCTL, group, sysctl_resource_ptpc, false); } } +bool clock_check_in_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + return sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); +} + void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) { if (cpu < 2U) { diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h index bfdc0d09..da56cf2b 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_clock_drv.h @@ -44,6 +44,7 @@ enum { #define CLK_SRC_GROUP_DAC (7U) #define CLK_SRC_GROUP_CPU0 (9U) #define CLK_SRC_GROUP_SRC (10U) +#define CLK_SRC_GROUP_PWDG (11U) #define CLK_SRC_GROUP_INVALID (15U) #define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) @@ -64,23 +65,26 @@ typedef enum _clock_sources { clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), - clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 2), - clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 3), + clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), clk_dac_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), + clk_dac_src_ana4 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), clk_dac_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), + clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 0), + clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 1), + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), } clk_src_t; #define RESOURCE_INVALID (0xFFFFU) -#define RESOURCE_SHARED_PTPC (0xFFFEU) #define RESOURCE_SHARED_CPU0 (0xFFFDU) /* Clock NAME related Macros */ @@ -139,7 +143,7 @@ typedef enum _clock_name { clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PWDG, 0), clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI, 0), clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI, 1), clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXI, 2), @@ -283,6 +287,13 @@ void clock_add_to_group(clock_name_t clock_name, uint32_t group); */ void clock_remove_from_group(clock_name_t clock_name, uint32_t group); +/** + * @brief Check IP in specified group + * @param[in] clock_name IP clock name + * @return true if in group, false if not in group + */ +bool clock_check_in_group(clock_name_t clock_name, uint32_t group); + /** * @brief Disconnect the clock group from specified CPU * @param[in] group clock group index, value value is 0/1/2/3 diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h index b1eca481..49d630e0 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_gpiom_soc_drv.h @@ -14,7 +14,7 @@ */ /* @brief gpiom control module */ -typedef enum hpm6300_gpiom_gpio { +typedef enum gpiom_gpio { gpiom_soc_gpio0 = 0, gpiom_soc_gpio1 = 1, gpiom_core0_fast = 2, diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h index e61b5e1c..c5f56fee 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_interrupt.h @@ -7,8 +7,8 @@ #ifndef HPM_INTERRUPT_H #define HPM_INTERRUPT_H -#include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_csr_drv.h" #include "hpm_plic_drv.h" /** @@ -40,7 +40,7 @@ ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) * @brief Disable global IRQ with mask and return mstatus * * @param[in] mask interrupt mask to be disabled - * @retval current mstatus value before irq disabled + * @retval current mstatus value before irq mask is disabled */ ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) { @@ -137,7 +137,7 @@ ATTR_ALWAYS_INLINE static inline uint32_t disable_s_global_irq(uint32_t mask) } /** - * @brief Restore global IRQ with mask + * @brief Restore global IRQ with mask for supervisor mode * * @param[in] mask interrupt mask to be restored */ @@ -779,25 +779,17 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) csrr s3, mstatus \n");\ SAVE_FPU_STATE(); \ SAVE_DSP_CONTEXT(); \ - __asm volatile ("\n\ - c.li a5, 8\n\ - csrs mstatus, a5\n"); \ + __asm volatile("csrsi mstatus, 8"); \ } /* * @brief Complete IRQ Handling */ #define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("\n\ - lui a5, 0x1\n\ - addi a5, a5, -2048\n\ - csrc mie, a5\n"); \ - __asm volatile("\n\ - lui a4, 0xe4200\n");\ + __asm volatile("csrci mstatus, 8"); \ + __asm volatile("lui a4, 0xe4200"); \ __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)\n\ - fence io, io\n"); \ - __asm volatile("csrs mie, a5"); \ + __asm volatile("sw a3, 4(a4)"); \ } /* @@ -823,24 +815,15 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) csrr s3, sstatus \n");\ SAVE_FPU_STATE(); \ SAVE_DSP_CONTEXT(); \ - __asm volatile ("\n\ - c.li a5, 8\n\ - csrs sstatus, a5\n"); \ + __asm volatile("csrsi sstatus, 2"); \ } #define COMPLETE_IRQ_HANDLING_S(irq_num) {\ - __asm volatile("\n\ - lui a5, 0x1\n\ - addi a5, a5, -2048\n\ - csrc sie, a5\n"); \ - __asm volatile("\n\ - lui a4, 0xe4201\n");\ + __asm volatile("csrci sstatus, 2"); \ + __asm volatile("lui a4, 0xe4201"); \ __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)\n\ - fence io, io\n"); \ - __asm volatile("csrs sie, a5"); \ + __asm volatile("sw a3, 4(a4)"); \ } - /* * @brief Exit Nested IRQ Handling at supervisor mode * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: @@ -873,18 +856,6 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) RESTORE_FCSR() \ RESTORE_UCODE() -/* - * @brief Nested IRQ exit macro : Restore CSRs - * @param[in] irq Target interrupt number - */ -#define NESTED_VPLIC_COMPLETE_INTERRUPT(irq) \ -do { \ - clear_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq); \ - __asm volatile("fence io, io"); \ - set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ -} while (0) - #ifdef __cplusplus #define EXTERN_C extern "C" #else @@ -913,6 +884,7 @@ void ISR_NAME_M(irq_num)(void) \ COMPLETE_IRQ_HANDLING_M(irq_num);\ EXIT_NESTED_IRQ_HANDLING_M();\ RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ __asm volatile("mret\n");\ } @@ -933,6 +905,7 @@ void ISR_NAME_S(irq_num)(void) {\ COMPLETE_IRQ_HANDLING_S(irq_num);\ EXIT_NESTED_IRQ_HANDLING_S();\ RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ __asm volatile("sret\n");\ } diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h index 480e7639..7b848c91 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_l1c_drv.h @@ -7,8 +7,8 @@ #ifndef _HPM_L1_CACHE_H #define _HPM_L1_CACHE_H -#include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_csr_drv.h" #include "hpm_soc.h" /** diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h index b6d28069..08f7f8f0 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_mcan_soc.h @@ -19,8 +19,8 @@ #define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN1 (1U) #define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN2 (2U) #define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN3 (3U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_PTP (4U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_PTP) +#define MCAN_TSU_EXT_TIMEBASE_SRC_PTPC (4U) +#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_PTPC) #ifdef __cpluspus extern "C" { diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h index fa899118..d7f58667 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_drv.h @@ -20,11 +20,9 @@ */ #define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) #define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW (0x1UL) #define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) #define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) -#define PCFG_PERIPH_SET_CLOCK_AUTO(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW << (p)) /* @brief PCFG irc24m reference */ typedef enum { @@ -229,12 +227,11 @@ static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) * * @param[in] ptr base address * @param[in] limit current limit at low power mode - * @param[in] over_limit set to true means current is greater than limit + * @param[in] over_limit unused parameter, will be discarded */ static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) { - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) - | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(over_limit); + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_ILIMIT_LP_MASK) | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); } /** diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h index 63ae7e49..db074075 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_pcfg_regs.h @@ -240,7 +240,7 @@ typedef struct { #define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) /* - * OVERLOAD_LP (RW) + * OVERLOAD_LP (RO) * * over current in low power mode * 0: current is below setting @@ -248,7 +248,6 @@ typedef struct { */ #define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) #define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDC_PROT_OVERLOAD_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) #define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) /* diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h index 52ba031d..ab90cd08 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ppor_drv.h @@ -11,15 +11,7 @@ typedef enum { ppor_reset_brownout = 1 << 0, - ppor_reset_temperature = 1 << 1, - ppor_reset_pin = 1 << 2, ppor_reset_debug = 1 << 4, - ppor_reset_security_violation = 1 << 5, - ppor_reset_jtag = 1 << 6, - ppor_reset_cpu0_lockup = 1 << 8, - ppor_reset_cpu1_lockup = 1 << 9, - ppor_reset_cpu0_request = 1 << 10, - ppor_reset_cpu1_request = 1 << 11, ppor_reset_wdog0 = 1 << 16, ppor_reset_wdog1 = 1 << 17, ppor_reset_wdog2 = 1 << 18, diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml index 95786789..e2dbf056 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ses_reg.xml @@ -4461,6 +4461,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -4501,6 +4521,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4541,6 +4681,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4581,6 +4841,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4813,9 +5193,6 @@ - - - @@ -5274,7 +5651,6 @@ - @@ -5516,9 +5892,6 @@ - - - @@ -5977,7 +6350,6 @@ - @@ -6219,9 +6591,6 @@ - - - @@ -6680,7 +7049,6 @@ - @@ -6694,7 +7062,6 @@ - @@ -6702,7 +7069,6 @@ - @@ -6713,7 +7079,6 @@ - @@ -6724,11 +7089,8 @@ - - - @@ -6747,18 +7109,14 @@ - - - - @@ -6773,46 +7131,36 @@ - - - - - - - - - - @@ -6831,18 +7179,14 @@ - - - - @@ -6857,46 +7201,36 @@ - - - - - - - - - - @@ -6915,18 +7249,14 @@ - - - - @@ -6941,46 +7271,36 @@ - - - - - - - - - - @@ -6999,18 +7319,14 @@ - - - - @@ -7025,35 +7341,28 @@ - - - - - - - @@ -7398,7 +7707,6 @@ - @@ -7491,7 +7799,6 @@ - @@ -7584,7 +7891,6 @@ - @@ -7677,7 +7983,6 @@ - @@ -7775,7 +8080,6 @@ - @@ -7841,6 +8145,9 @@ + + + @@ -7849,7 +8156,6 @@ - @@ -7915,6 +8221,9 @@ + + + @@ -7923,7 +8232,6 @@ - @@ -7989,6 +8297,9 @@ + + + @@ -7997,7 +8308,6 @@ - @@ -8063,6 +8373,9 @@ + + + @@ -8071,7 +8384,6 @@ - @@ -8137,6 +8449,9 @@ + + + @@ -8145,7 +8460,6 @@ - @@ -8211,6 +8525,9 @@ + + + @@ -8219,7 +8536,6 @@ - @@ -8285,6 +8601,9 @@ + + + @@ -8293,7 +8612,6 @@ - @@ -8359,6 +8677,9 @@ + + + @@ -8367,7 +8688,6 @@ - @@ -8433,6 +8753,9 @@ + + + @@ -8821,7 +9144,7 @@ - + @@ -11135,7 +11458,7 @@ - + @@ -13449,7 +13772,7 @@ - + @@ -15763,7 +16086,7 @@ - + @@ -17750,20 +18073,16 @@ - - - - @@ -17776,7 +18095,6 @@ - @@ -17796,20 +18114,16 @@ - - - - @@ -17822,7 +18136,6 @@ - @@ -17842,20 +18155,16 @@ - - - - @@ -17868,7 +18177,6 @@ - @@ -17888,20 +18196,16 @@ - - - - @@ -17914,7 +18218,6 @@ - @@ -17937,7 +18240,6 @@ - @@ -17983,7 +18285,6 @@ - @@ -18046,6 +18347,12 @@ + + + + + + @@ -19033,48 +19340,33 @@ - - - - - - - - - - - - - - - @@ -19185,7 +19477,6 @@ - @@ -19193,7 +19484,6 @@ - @@ -19295,54 +19585,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -19407,38 +19649,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -19446,196 +19656,84 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -19717,34 +19815,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -19794,34 +19867,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -19928,145 +19976,81 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20103,7 +20087,6 @@ - @@ -20111,7 +20094,6 @@ - @@ -20213,54 +20195,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20325,38 +20259,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20364,196 +20266,84 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20635,34 +20425,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20712,34 +20477,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20846,145 +20586,81 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21021,7 +20697,6 @@ - @@ -21029,7 +20704,6 @@ - @@ -21131,54 +20805,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21243,38 +20869,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21282,196 +20876,84 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21553,34 +21035,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21630,34 +21087,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21764,145 +21196,81 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21939,7 +21307,6 @@ - @@ -21947,7 +21314,6 @@ - @@ -22049,54 +21415,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22161,38 +21479,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22200,196 +21486,84 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22471,34 +21645,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22548,34 +21697,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22682,145 +21806,81 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -22853,16 +21913,11 @@ - - - - - @@ -22870,7 +21925,6 @@ - @@ -22878,10 +21932,6 @@ - - - - @@ -22891,10 +21941,6 @@ - - - - @@ -22904,10 +21950,6 @@ - - - - @@ -22917,10 +21959,6 @@ - - - - @@ -22930,10 +21968,6 @@ - - - - @@ -22942,8 +21976,6 @@ - - @@ -22960,8 +21992,6 @@ - - @@ -22978,8 +22008,6 @@ - - @@ -22996,8 +22024,6 @@ - - @@ -23032,16 +22058,11 @@ - - - - - @@ -23049,7 +22070,6 @@ - @@ -23057,10 +22077,6 @@ - - - - @@ -23070,10 +22086,6 @@ - - - - @@ -23083,10 +22095,6 @@ - - - - @@ -23096,10 +22104,6 @@ - - - - @@ -23109,10 +22113,6 @@ - - - - @@ -23121,8 +22121,6 @@ - - @@ -23139,8 +22137,6 @@ - - @@ -23157,8 +22153,6 @@ - - @@ -23175,8 +22169,6 @@ - - @@ -23211,16 +22203,11 @@ - - - - - @@ -23228,7 +22215,6 @@ - @@ -23236,10 +22222,6 @@ - - - - @@ -23249,10 +22231,6 @@ - - - - @@ -23262,10 +22240,6 @@ - - - - @@ -23275,10 +22249,6 @@ - - - - @@ -23288,10 +22258,6 @@ - - - - @@ -23300,8 +22266,6 @@ - - @@ -23318,8 +22282,6 @@ - - @@ -23336,8 +22298,6 @@ - - @@ -23354,8 +22314,6 @@ - - @@ -23390,16 +22348,11 @@ - - - - - @@ -23407,7 +22360,6 @@ - @@ -23415,10 +22367,6 @@ - - - - @@ -23428,10 +22376,6 @@ - - - - @@ -23441,10 +22385,6 @@ - - - - @@ -23454,10 +22394,6 @@ - - - - @@ -23467,10 +22403,6 @@ - - - - @@ -23479,8 +22411,6 @@ - - @@ -23497,8 +22427,6 @@ - - @@ -23515,8 +22443,6 @@ - - @@ -23533,8 +22459,6 @@ - - @@ -23581,7 +22505,6 @@ - @@ -23738,7 +22661,6 @@ - @@ -23895,7 +22817,6 @@ - @@ -24052,7 +22973,6 @@ - @@ -33443,7 +32363,6 @@ - @@ -33486,7 +32405,6 @@ - @@ -33529,7 +32447,6 @@ - @@ -33572,7 +32489,6 @@ - @@ -33614,7 +32530,6 @@ - @@ -33633,7 +32548,6 @@ - @@ -33658,7 +32572,6 @@ - @@ -33701,7 +32614,6 @@ - @@ -33744,7 +32656,6 @@ - @@ -33787,7 +32698,6 @@ - @@ -33829,7 +32739,6 @@ - @@ -33848,7 +32757,6 @@ - @@ -33873,7 +32781,6 @@ - @@ -33916,7 +32823,6 @@ - @@ -33959,7 +32865,6 @@ - @@ -34002,7 +32907,6 @@ - @@ -34044,7 +32948,6 @@ - @@ -34063,7 +32966,6 @@ - @@ -34088,7 +32990,6 @@ - @@ -34131,7 +33032,6 @@ - @@ -34174,7 +33074,6 @@ - @@ -34217,7 +33116,6 @@ - @@ -34259,7 +33157,6 @@ - @@ -34278,7 +33175,6 @@ - @@ -34303,7 +33199,6 @@ - @@ -34346,7 +33241,6 @@ - @@ -34389,7 +33283,6 @@ - @@ -34432,7 +33325,6 @@ - @@ -34474,7 +33366,6 @@ - @@ -34493,7 +33384,6 @@ - @@ -34517,11 +33407,9 @@ - - @@ -34534,7 +33422,6 @@ - @@ -34552,15 +33439,12 @@ - - - @@ -34569,15 +33453,12 @@ - - - @@ -34586,17 +33467,14 @@ - - - @@ -34609,7 +33487,6 @@ - @@ -34627,15 +33504,12 @@ - - - @@ -34644,15 +33518,12 @@ - - - @@ -34661,17 +33532,14 @@ - - - @@ -34684,7 +33552,6 @@ - @@ -34702,15 +33569,12 @@ - - - @@ -34719,15 +33583,12 @@ - - - @@ -34736,17 +33597,14 @@ - - - @@ -34759,7 +33617,6 @@ - @@ -34777,15 +33634,12 @@ - - - @@ -34794,15 +33648,12 @@ - - - @@ -34811,7 +33662,6 @@ - @@ -35113,13 +33963,11 @@ - - @@ -35128,36 +33976,27 @@ - - - - - - - - - @@ -35166,9 +34005,7 @@ - - @@ -35218,14 +34055,12 @@ - - @@ -44319,6 +43154,12 @@ + + + + + + @@ -44363,6 +43204,12 @@ + + + + + + @@ -44427,6 +43274,21 @@ + + + + + + + + + + + + + + + @@ -44493,29 +43355,29 @@ - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + @@ -44744,4 +43606,4 @@ - \ No newline at end of file + diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_ses_riscv_cpu_regs.xml b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ses_riscv_cpu_regs.xml index e3f4886c..fffbd735 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_ses_riscv_cpu_regs.xml +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_ses_riscv_cpu_regs.xml @@ -767,4 +767,4 @@ - \ No newline at end of file + diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h index be9c6c6f..6a269a1e 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc.h @@ -134,10 +134,6 @@ /* DM base address */ #define HPM_DM_BASE (0x30000000UL) -/* Address of XBUS_SOC instances */ -/* GPV_SOC base address */ -#define HPM_GPV_SOC_BASE (0x30100000UL) - #include "hpm_plic_regs.h" /* Address of PLIC instances */ /* PLIC base address */ @@ -457,10 +453,6 @@ /* SYNT base pointer */ #define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) -/* Address of PLA_X2 instances */ -/* PLA_X2 base address */ -#define HPM_PLA_X2_BASE (0xF024E000UL) - #include "hpm_usb_regs.h" /* Address of USB instances */ /* USB0 base address */ @@ -622,9 +614,12 @@ /* TSNS base pointer */ #define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) +#include "hpm_bacc_regs.h" /* Address of BACC instances */ /* BACC base address */ #define HPM_BACC_BASE (0xF5000000UL) +/* BACC base pointer */ +#define HPM_BACC ((BACC_Type *) HPM_BACC_BASE) #include "hpm_bpor_regs.h" /* Address of BPOR instances */ @@ -706,4 +701,4 @@ #include "hpm_iomux.h" #include "hpm_pmic_iomux.h" #include "hpm_batt_iomux.h" -#endif /* HPM_SOC_H */ \ No newline at end of file +#endif /* HPM_SOC_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h index a560b691..dec054b6 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_soc_feature.h @@ -55,7 +55,6 @@ */ #define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) #define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_BUS_NUM (1U) #define DMA_SOC_CHANNEL_NUM (8U) #define DMA_SOC_MAX_COUNT (2U) #define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) @@ -99,6 +98,7 @@ /* * ADC Section */ +#define ADC_SOC_IP_VERSION (1U) #define ADC_SOC_SEQ_MAX_LEN (16U) #define ADC_SOC_MAX_TRIG_CH_LEN (4U) #define ADC_SOC_MAX_TRIG_CH_NUM (11U) diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c b/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c index 110f4dba..d9c0ca8e 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.c @@ -196,6 +196,47 @@ hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, return status_success; } +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t linkable_resource) +{ + uint32_t index, offset; + bool enable; + + index = (linkable_resource - sysctl_resource_linkable_start) / 32; + offset = (linkable_resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + case SYSCTL_RESOURCE_GROUP1: + enable = ((ptr->GROUP1[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + default: + enable = false; + break; + } + + return enable; +} + +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) +{ + uint32_t value; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + value = ptr->GROUP0[index].VALUE; + break; + case SYSCTL_RESOURCE_GROUP1: + value = ptr->GROUP1[index].VALUE; + break; + default: + value = 0; + break; + } + return value; +} + hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) { return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h index 0b2c1f7d..48dff9ca 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_sysctl_drv.h @@ -613,6 +613,19 @@ static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, SYSCTL_RESOURCE_MODE_SET(mode); } +/** + * @brief Get target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return target resource mode + */ +static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource) +{ + return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); +} + /** * @brief Disable resource retention when specific CPU enters stop mode * @@ -1385,6 +1398,27 @@ hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); + +/** + * @brief Check group resource enable status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be checked + * @param[in] resource target resource to be checked from group + * @return enable true if resource enable, false if resource disable + */ +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t linkable_resource); + +/** + * @brief Get group resource value + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be getted + * @param[in] index target group index + * @return group index value + */ +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); + /** * @brief Add resource to CPU0 * @@ -1439,7 +1473,7 @@ void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *confi void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); /** - * @brief Save data to GPU0 GPR starting from given index + * @brief Save data to CPU0 GPR starting from given index * * @param[in] ptr SYSCTL_Type base address * @param[in] start Starting GPR index @@ -1451,7 +1485,7 @@ void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); /** - * @brief Get data saved from GPU0 GPR starting from given index + * @brief Get data saved from CPU0 GPR starting from given index * * @param[in] ptr SYSCTL_Type base address * @param[in] start Starting GPR index diff --git a/common/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h b/common/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h index 54c28f6a..a6a89374 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/hpm_trgmmux_src.h @@ -731,4 +731,4 @@ -#endif /* HPM_TRGMMUX_SRC_H */ \ No newline at end of file +#endif /* HPM_TRGMMUX_SRC_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/soc_modules.list b/common/libraries/hpm_sdk/soc/HPM6280/soc_modules.list index 635eed58..3112e231 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/soc_modules.list +++ b/common/libraries/hpm_sdk/soc/HPM6280/soc_modules.list @@ -38,3 +38,4 @@ CONFIG_HAS_HPMSDK_CRC=y CONFIG_HAS_HPMSDK_PLA=y CONFIG_HAS_HPMSDK_SDM=y CONFIG_HAS_HPMSDK_LIN=y +CONFIG_HAS_HPMSDK_QEI=y diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld index 1f5dd280..8a912fe2 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash.ld @@ -26,7 +26,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text : { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(.text) *(.text*) @@ -45,36 +57,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - .vectors ORIGIN(ILM) : AT(etext) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext + __vector_ram_end__ - __vector_ram_start__) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -82,8 +83,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -127,12 +126,13 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM .bss (NOLOAD) : { @@ -140,11 +140,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -152,13 +150,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -208,5 +230,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld index cef727ae..6c4e2b82 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_uf2.ld @@ -27,7 +27,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { . = ALIGN(8); *(.text) *(.text*) @@ -46,39 +58,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -86,8 +84,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -131,12 +127,13 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM .bss (NOLOAD) : { @@ -144,11 +141,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -156,13 +151,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -212,5 +231,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld index 39623d35..bb500192 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/flash_xip.ld @@ -25,6 +25,7 @@ __app_load_addr__ = ORIGIN(XPI0) + 0x3000; __boot_header_length__ = __boot_header_end__ - __boot_header_start__; __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + SECTIONS { .nor_cfg_option __nor_cfg_option_load_addr__ : { @@ -44,7 +45,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(.text) *(.text*) @@ -63,39 +76,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -148,25 +147,23 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM - __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -174,13 +171,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -230,5 +251,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld index 013415ca..cc886a95 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram.ld @@ -70,7 +70,8 @@ SECTIONS PROVIDE (etext = .); } > ILM - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -78,8 +79,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -124,7 +123,8 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -137,11 +137,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -149,13 +147,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -195,6 +217,7 @@ SECTIONS . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; + . = ALIGN(8); PROVIDE (_stack = .); PROVIDE (_stack_safe = .); } > DLM @@ -204,5 +227,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(ILM), "****** FAILED! ILM has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld index 14f7bd8c..bf24524a 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/ram_core1.ld @@ -66,7 +66,8 @@ SECTIONS PROVIDE (etext = .); } > ILM - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -74,8 +75,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -120,7 +119,8 @@ SECTIONS PROVIDE (edata = .); } > DLM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -133,11 +133,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -145,13 +143,37 @@ SECTIONS __bss_end__ = .; } > DLM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > DLM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > DLM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > DLM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -197,5 +219,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(ILM), "****** FAILED! ILM has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S index e860bc31..f4e0e5fa 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/gcc/start.S @@ -16,6 +16,7 @@ _start: .option push .option norelax la gp, __global_pointer$ + la tp, __thread_pointer$ .option pop /* reset mstatus to 0*/ diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c index abb52b8c..bdd2320a 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/reset.c @@ -30,6 +30,13 @@ __attribute__((weak)) void _clean_up(void) __attribute__((weak)) void c_startup(void) { uint32_t i, size; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __data_load_addr__[], __fast_load_addr__[], __noncacheable_init_load_addr__[]; + #if defined(FLASH_XIP) || defined(FLASH_UF2) extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; size = __vector_ram_end__ - __vector_ram_start__; @@ -38,13 +45,6 @@ __attribute__((weak)) void c_startup(void) } #endif - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - /* bss section */ size = __bss_end__ - __bss_start__; for (i = 0; i < size; i++) { @@ -60,19 +60,19 @@ __attribute__((weak)) void c_startup(void) /* data section LMA: etext */ size = __data_end__ - __data_start__; for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + i); + *(__data_start__ + i) = *(__data_load_addr__ + i); } /* ramfunc section LMA: etext + data length */ size = __ramfunc_end__ - __ramfunc_start__; for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); } - /* noncacheable init section LMA: etext + data length + ramfunc legnth */ + /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ size = __noncacheable_init_end__ - __noncacheable_init_start__; for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } } diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf index 4e9e3791..761f3368 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf @@ -15,16 +15,15 @@ define region AXI_SRAM = [from 0x010A0000 size 112k]; define region SHARE_RAM = [from 0x010BC000 size 16k]; define region AHB_SRAM = [from 0xF0300000 size 32k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - /* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -32,14 +31,14 @@ define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_cla define block framebuffer with alignment = 8 { section .framebuffer }; /* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; /* Initialization */ do not initialize { section .noncacheable }; @@ -52,8 +51,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors, block vectors_s }; initialize by copy { block cherryusb_usbh_class_info }; @@ -61,12 +60,12 @@ initialize by copy { block cherryusb_usbh_class_info }; place at start of XPI0 with fixed order { symbol _start }; place at start of ILM with fixed order { block vectors, block vectors_s }; place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) }; // diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf index 4ccc7afe..ce54db73 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf @@ -16,8 +16,6 @@ define region AXI_SRAM = [from 0x010A0000 size 112k]; define region SHARE_RAM = [from 0x010BC000 size 16k]; define region AHB_SRAM = [from 0xF0300000 size 32k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - /* Blocks */ define block vectors with fixed order { section .vector_table, section .isr_vector }; define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; @@ -26,7 +24,7 @@ define block dtors { section .dtors, section .dtors define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -34,14 +32,14 @@ define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_cla define block framebuffer with alignment = 8 { section .framebuffer }; /* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; /* Initialization */ do not initialize { section .noncacheable }; @@ -54,8 +52,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors, block vectors_s }; initialize by copy { block cherryusb_usbh_class_info }; diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf index dd91654a..9729ac53 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf @@ -17,8 +17,6 @@ define region AXI_SRAM = [from 0x010A0000 size 112k]; define region SHARE_RAM = [from 0x010BC000 size 16k]; define region AHB_SRAM = [from 0xF0300000 size 32k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - /* Blocks */ define block vectors with fixed order { section .vector_table, section .isr_vector }; define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; @@ -27,7 +25,7 @@ define block dtors { section .dtors, section .dtors define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -43,14 +41,14 @@ define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_a define exported symbol __boot_header_length__ = size of block boot_header; define exported symbol __fw_size__ = 0x1000; -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; /* Initialization */ do not initialize { section .noncacheable }; @@ -63,8 +61,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors, block vectors_s }; initialize by copy { block cherryusb_usbh_class_info }; diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf index d170c8c6..81b1c34c 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf @@ -14,8 +14,6 @@ define region AXI_SRAM = [from 0x010A0000 size 112k]; define region SHARE_RAM = [from 0x010BC000 size 16k]; define region AHB_SRAM = [from 0xF0300000 size 32k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - /* Blocks */ define block vectors with fixed order { section .vector_table, section .isr_vector }; define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; @@ -24,7 +22,7 @@ define block dtors { section .dtors, section .dtors define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -32,10 +30,10 @@ define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_cla define block framebuffer with alignment = 8 { section .framebuffer }; /* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack = end of block stack + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; @@ -52,8 +50,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. /* Placement */ place at start of ILM { symbol _start }; diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf index 375962ac..2a3bf854 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf @@ -12,16 +12,15 @@ define region DLM = [from 0x000A0000 size 96k]; /* DLM */ define region NONCACHEABLE_RAM = [from 0x000B8000 size 32k]; /* AXI SRAM1 */ define region SHARE_RAM = [from 0x010BC000 size 16k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; - /* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block cherryusb_usbh_class_info { section .usbh_class_info }; define block framebuffer { section .framebuffer }; @@ -31,8 +30,8 @@ define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ r /* Symbols */ define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack = end of block stack + 1; define exported symbol _stack_safe = end of block stack + 1; @@ -50,12 +49,12 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. /* Placement */ place at start of ILM { symbol _start }; -place in ILM { block vectors }; // Vector table section +place in ILM { block vectors, block vectors_s }; // Vector table section place in ILM { section .fast, section .fast.* }; // "ramfunc" section place in ILM with minimum size order { block tdata_load, // Thread-local-storage load image diff --git a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h index ed369e02..f44f10a7 100644 --- a/common/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h +++ b/common/libraries/hpm_sdk/soc/HPM6280/toolchains/vectors.h @@ -232,3 +232,4 @@ IRQ_S_HANDLER 91 /* LIN1 IRQ handler */ IRQ_S_HANDLER 92 /* LIN2 IRQ handler */ IRQ_S_HANDLER 93 /* LIN3 IRQ handler */ + diff --git a/common/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml b/common/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml index 6265443c..7ee8e567 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml +++ b/common/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml @@ -42,14 +42,14 @@ 0xc0000 0x0 - 0x800 + 0x824 registers 16 0x10 - gpioa,gpiob,gpioc,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz DI[%s] no description available 0x0 @@ -76,7 +76,7 @@ 16 0x10 - gpioa,gpiob,gpioc,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz DO[%s] no description available 0x100 @@ -160,7 +160,7 @@ 16 0x10 - gpioa,gpiob,gpioc,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz OE[%s] no description available 0x200 @@ -244,7 +244,7 @@ 16 0x10 - gpioa,gpiob,gpioc,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz IF[%s] no description available 0x300 @@ -271,7 +271,7 @@ 16 0x10 - gpioa,gpiob,gpioc,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz IE[%s] no description available 0x400 @@ -355,7 +355,7 @@ 16 0x10 - gpioa,gpiob,gpioc,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz PL[%s] no description available 0x500 @@ -439,7 +439,7 @@ 16 0x10 - gpioa,gpiob,gpioc,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz TP[%s] no description available 0x600 @@ -523,7 +523,7 @@ 16 0x10 - gpioa,gpiob,gpioc,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz AS[%s] no description available 0x700 @@ -991,7 +991,7 @@ Note: combinational interrupt is sensitive to environment noise 16 0x80 - gpioa,gpiob,gpioc,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz ASSIGN[%s] no description available 0x0 @@ -1301,24 +1301,6 @@ If cont_en is 0, this bit is not used - - seq_wr_addr - No description avaiable - 0x808 - 32 - 0x00000000 - 0x00FFFFFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 24 - read-only - - - seq_dma_cfg No description avaiable @@ -1499,7 +1481,7 @@ it may be updated period according to config, also may be updated due to other q CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 22 adc clock cycles(based on clock after divider); + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz). 4 @@ -1573,14 +1555,14 @@ Adc_clk must to be set to same as bus clock at this mode interrupt for one trigger conversion complete if enabled 31 1 - write-only + read-write TRIG_SW_CFLCT No description avaiable 30 1 - write-only + read-write TRIG_HW_CFLCT @@ -1594,14 +1576,14 @@ Adc_clk must to be set to same as bus clock at this mode read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel 28 1 - write-only + read-write SEQ_SW_CFLCT sequence queue conflict interrup, set if HW or SW trigger received during conversion 27 1 - write-only + read-write SEQ_HW_CFLCT @@ -1615,21 +1597,21 @@ Adc_clk must to be set to same as bus clock at this mode dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set 25 1 - write-only + read-write SEQ_CMPT the whole sequence complete interrupt 24 1 - write-only + read-write SEQ_CVC one conversion complete in seq_queue if related seq_int_en is set 23 1 - write-only + read-write DMA_FIFO_FULL @@ -1650,7 +1632,7 @@ Adc_clk must to be set to same as bus clock at this mode set if one chanel watch dog event triggered 0 14 - write-only + read-write @@ -1667,14 +1649,14 @@ Adc_clk must to be set to same as bus clock at this mode interrupt for one trigger conversion complete if enabled 31 1 - write-only + read-write TRIG_SW_CFLCT No description avaiable 30 1 - write-only + read-write TRIG_HW_CFLCT @@ -1688,14 +1670,14 @@ Adc_clk must to be set to same as bus clock at this mode read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel 28 1 - write-only + read-write SEQ_SW_CFLCT sequence queue conflict interrup, set if HW or SW trigger received during conversion 27 1 - write-only + read-write SEQ_HW_CFLCT @@ -1709,21 +1691,21 @@ Adc_clk must to be set to same as bus clock at this mode dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set 25 1 - write-only + read-write SEQ_CMPT the whole sequence complete interrupt 24 1 - write-only + read-write SEQ_CVC one conversion complete in seq_queue if related seq_int_en is set 23 1 - write-only + read-write DMA_FIFO_FULL @@ -1744,7 +1726,7 @@ Adc_clk must to be set to same as bus clock at this mode set if one chanel watch dog event triggered 0 14 - write-only + read-write @@ -1816,15 +1798,8 @@ MUST set clock_period to 0 or 1 for adc16 reg access 0x1444 32 0x00000000 - 0x03F07FFF + 0x01F07FFF - - TEMPSNS_EN - set to enable temp senser - 25 - 1 - read-write - REG_EN set to enable regulator @@ -2195,7 +2170,10 @@ Should only be used in buffer mode. DAC_MODE 00: direct mode, DAC output the fixed configured data(from sw_dac_data) 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down -10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; +10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; +11: trigger mode, DAC output from external trigger signals +Note: +Trigger mode is not supported in hpm63xx and hpm62xx families. 4 2 write-only @@ -2230,7 +2208,8 @@ others are reserved ANA_CLK_EN - set to enable analog clock(divided by ana_div_cfg) + set to enable analog clock(divided by ana_div_cfg) +need to be set in direct mode and trigger mode 18 1 read-write @@ -2248,8 +2227,12 @@ others are reserved DIV_CFG - how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. -Used for step mode and buffer mode, if set to continual trigger mode + step mode and buffer mode: + defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. +Direct mode and trigger mode: + defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. +Note: +For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. 0 16 read-write @@ -2438,15 +2421,8 @@ AHB burst can't cross 1K-byte boundary, user should config the address/length/bu 0x30 32 0x00000000 - 0x0000001F + 0x0000000F - - STEP_CMPT - No description avaiable - 4 - 1 - write-only - AHB_ERROR set if hresp==2'b01(ERROR) @@ -2528,15 +2504,8 @@ AHB burst can't cross 1K-byte boundary, user should config the address/length/bu 0x38 32 0x00000000 - 0x00000013 + 0x00000003 - - STEP_CMPT - No description avaiable - 4 - 1 - read-write - BUF1_CMPT No description avaiable @@ -2707,8 +2676,8 @@ others are reserved SPI 0xf0030000 - 0x0 - 0x80 + 0x10 + 0x70 registers @@ -2720,13 +2689,6 @@ others are reserved 0x00020780 0xFFFF1F9F - - RESERVED - No description avaiable - 18 - 14 - read-write - ADDRLEN Address length in bytes @@ -3434,8 +3396,8 @@ When an SPI transaction other than slave status-reading command ends, this bit w UART 0xf0040000 - 0x0 - 0x40 + 0x10 + 0x30 registers @@ -3447,13 +3409,6 @@ When an SPI transaction other than slave status-reading command ends, this bit w 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 2 - 30 - read-write - FIFOSIZE The depth of RXFIFO and TXFIFO @@ -3492,6 +3447,7 @@ OSC<=8: The over-sample ratio is 8 RBR Receiver Buffer Register (when DLAB = 0) + UNION_20 0x20 32 0x00000000 @@ -3509,6 +3465,7 @@ OSC<=8: The over-sample ratio is 8 THR Transmitter Holding Register (when DLAB = 0) + UNION_20 0x20 32 0x00000000 @@ -3526,6 +3483,7 @@ OSC<=8: The over-sample ratio is 8 DLL Divisor Latch LSB (when DLAB = 1) + UNION_20 0x20 32 0x00000001 @@ -3543,6 +3501,7 @@ OSC<=8: The over-sample ratio is 8 IER Interrupt Enable Register (when DLAB = 0) + UNION_24 0x24 32 0x00000000 @@ -3591,6 +3550,7 @@ character timeout interrupt DLM Divisor Latch MSB (when DLAB = 1) + UNION_24 0x24 32 0x00000000 @@ -3608,6 +3568,7 @@ character timeout interrupt IIR Interrupt Identification Register + UNION_28 0x28 32 0x00000001 @@ -3634,6 +3595,7 @@ Register (FIFOE) is set to 1. FCR FIFO Control Register + UNION_28 0x28 32 0x00000000 @@ -3938,6 +3900,23 @@ register is read. + + GPR + GPR Register + 0x3c + 32 + 0x00000000 + 0x000000FF + + + DATA + An one-byte storage register + 0 + 8 + read-write + + + @@ -5284,8 +5263,8 @@ TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch tri WDOG 0xf0090000 - 0x0 - 0x20 + 0x10 + 0x10 registers @@ -5451,7 +5430,7 @@ Restart Register. 0xf00a0000 0x0 - 0x30 + 0x24 registers @@ -5470,13 +5449,6 @@ Restart Register. 1 read-write - - RESERVED - Reserved - 16 - 15 - read-only - BARCTL Bus Acccess Response Control, when bit 15:14= @@ -5488,13 +5460,6 @@ Restart Register. 2 read-write - - RESERVED - Reserved - 9 - 5 - read-only - BEIE Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. @@ -5540,13 +5505,6 @@ Restart Register. 1 read-write - - RESERVED - Reserved - 2 - 2 - read-only - TWMEIE TX word message empty interrupt enable. @@ -5575,13 +5533,6 @@ Restart Register. 0x000000E2 0xFFFF3FFF - - RESERVED - Not used - 24 - 8 - read-only - RFVC RX FIFO valid message count @@ -5686,13 +5637,6 @@ Restart Register. 1 read-only - - RESERVED - Not used - 2 - 2 - read-only - TWME TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. @@ -5748,9 +5692,9 @@ Restart Register. - 4 + 1 0x4 - TXFIFO0,TXFIFO1,TXFIFO2,TXFIFO3 + TXFIFO0 TXWRD[%s] no description available 0x10 @@ -5770,9 +5714,9 @@ can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 4 + 1 0x4 - RXFIFO0,RXFIFO1,RXFIFO2,RXFIFO3 + RXFIFO0 RXWRD[%s] no description available 0x20 @@ -5806,7 +5750,7 @@ can also use 4x32 burst read from 0x020 to read 4 words from the FIFO.0xf00b0000 0x0 - 0x200c + 0x3004 registers @@ -5857,13 +5801,6 @@ If this bit is cleared, capture result will be updated at each capture event1 read-write - - RESERVED - No description avaiable - 5 - 1 - read-write - COMP_EN set to enable compare, will be cleared by HW when compare event triggered @@ -5887,8 +5824,8 @@ If this bit is cleared, capture result will be updated at each capture event FINE_COARSE_SEL - 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow -1: coarse update, ns counter add ss_incr[7:0] each clk + 0: coarse update, ns counter add ss_incr[7:0] each clk +1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow 1 1 read-write @@ -6242,6 +6179,44 @@ clr to use ptpc0 for canx + + ptpc_can_ts_sel + No description avaiable + 0x3000 + 32 + 0x00000000 + 0xFFFFFF00 + + + TSU_TBIN3_SEL + No description avaiable + 26 + 6 + read-write + + + TSU_TBIN2_SEL + No description avaiable + 20 + 6 + read-write + + + TSU_TBIN1_SEL + No description avaiable + 14 + 6 + read-write + + + TSU_TBIN0_SEL + No description avaiable + 8 + 6 + read-write + + + @@ -6295,8 +6270,8 @@ Specifies which DMA source, if any, is routed to a particular DMA channel. See t DMA 0xf00c4000 - 0x0 - 0x140 + 0x10 + 0x130 registers @@ -6847,13 +6822,6 @@ This register exists only when the address bus width is wider than 32 bits.0x00000000 0xFFFFFFFF - - RESERVED - Not used - 7 - 25 - read-write - SFTRST Soft Reset, Perform a software reset of the RNG This bit is self-clearing. @@ -6881,13 +6849,6 @@ This register exists only when the address bus width is wider than 32 bits.1 read-write - - RESERVED - Not used - 2 - 2 - read-only - GENSD Generate Seed, when both ST and GS triggered, ST first and GS next. @@ -6912,13 +6873,6 @@ This register exists only when the address bus width is wider than 32 bits.0x00000000 0xFFFFFFFF - - RESERVED - Not used - 7 - 25 - read-only - MIRQERR Mask Interrupt Request for Error @@ -6942,13 +6896,6 @@ This register exists only when the address bus width is wider than 32 bits.1 read-write - - RESERVED - Not used - 2 - 2 - read-only - FUFMOD FIFO underflow response mode @@ -6970,13 +6917,6 @@ This register exists only when the address bus width is wider than 32 bits.0x00000000 0xFFFFFFFF - - RESERVED - Not used - 24 - 8 - read-only - SCPF Self Check Pass Fail @@ -6984,13 +6924,6 @@ This register exists only when the address bus width is wider than 32 bits.3 read-only - - RESERVED - Not used - 17 - 4 - read-only - FUNCERR Error was detected, check ESR register for details @@ -7012,13 +6945,6 @@ This register exists only when the address bus width is wider than 32 bits.4 read-only - - RESERVED - Not used - 7 - 1 - read-only - NSDDN New seed done. @@ -7068,13 +6994,6 @@ automatically if the CTRL[ARS] is set. 1 read-only - - RESERVED - Not used - 0 - 1 - read-only - @@ -7085,33 +7004,6 @@ automatically if the CTRL[ARS] is set. 0x00000000 0xFFFFFF3F - - RESERVED - OSC1 Satistics test pass failed. -Indicates the pass or fail status of the various statistics tests on the last seed generated. -0 Pass -1 Fail - 24 - 8 - read-only - - - RESERVED - OSC0 Satistics test pass failed. -Indicates the pass or fail status of the various statistics tests on the last seed generated. -0 Pass -1 Fail - 16 - 8 - read-only - - - RESERVED - Not used - 8 - 8 - read-only - FUFE FIFO access error(underflow) @@ -7119,17 +7011,6 @@ Indicates the pass or fail status of the various statistics tests on the last se 1 read-only - - RESERVED - Statistical test error -Indicates whether the statistical tests for the last generated seed was failed or not. This bit is sticky and is -cleared by a hardware or software reset or by writing 1 to the CMD[CE]. -0 No fail for the statistical tests. -1 Failed the statistical tests during the initialization - 4 - 1 - read-only - SCKERR Self-test error @@ -7139,30 +7020,6 @@ hardware reset or by writing 1 to the CMD[CE] 1 read-only - - RESERVED - Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a -software or hardware reset. - 2 - 1 - read-only - - - RESERVED - Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a -software or hardware reset. - 1 - 1 - read-only - - - RESERVED - Linear feedback shift register (LFSR) error -When this bit is set, the interrupt generated was caused by a failure of one of the LFSRs in any of the RNG LFSR ciruit. - 0 - 1 - read-only - @@ -7463,13 +7320,6 @@ bit2: software key 0: not selected, 1:selected 0x00000000 0xFFFFFFFF - - RSV - Reserved - 19 - 13 - read-write - SFTRST_RX software reset the RX module if asserted to be 1'b1. Self-clear. @@ -7654,13 +7504,6 @@ This bit controls the generation of an interrupt when an error condition (UD, O 0x00000000 0xFFFFFFFF - - RSV - No description avaiable - 16 - 16 - read-write - TX TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. @@ -7685,13 +7528,6 @@ This bit controls the generation of an interrupt when an error condition (UD, O 0x00000000 0xFFFFFFFF - - RSV - Reserved - 17 - 15 - read-only - TX_UD Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. @@ -7720,13 +7556,6 @@ This bit controls the generation of an interrupt when an error condition (UD, O 4 read-only - - RSV - Reserved - 0 - 1 - read-only - @@ -7777,13 +7606,6 @@ This bit controls the generation of an interrupt when an error condition (UD, O 0x40000000 0xFFFFFFFF - - RSV - Reserved - 31 - 1 - read-write - BCLK_GATEOFF Gate off the bclk. Asserted to gate-off the BCLK. @@ -7940,13 +7762,6 @@ Note: For correct operation, this bit should be configured when the I2S is disab 0x00042000 0xFFFFEC01 - - RSV - Reserved - 14 - 18 - read-write - MCLK_GATEOFF Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. @@ -7954,20 +7769,6 @@ Note: For correct operation, this bit should be configured when the I2S is disab 1 read-write - - RSV - Reserved - 11 - 1 - read-write - - - RSV - Reserved - 10 - 1 - read-write - MCLKOE Master clock output to pad enable @@ -8707,6 +8508,7 @@ otherwise the shadow registers can not be written. sta Counter start register + UNION_STA 0x4 32 0x00000000 @@ -8727,18 +8529,12 @@ otherwise the shadow registers can not be written. 24 read-write - - RESERVED - reserved - 0 - 4 - read-write - rld Counter reload register + UNION_RLD 0x8 32 0x00000000 @@ -8758,13 +8554,6 @@ otherwise the shadow registers can not be written. 24 read-write - - RESERVED - reserved - 0 - 4 - read-write - @@ -8858,13 +8647,6 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c 0x00000000 0xFFFF0003 - - RESERVED - read as 0 - 29 - 3 - read-write - CMPSELEND assign the last comparator for this output channel @@ -8872,13 +8654,6 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c 5 read-write - - RESERVED - read as 0 - 21 - 3 - read-write - CMPSELBEG assign the first comparator for this output channel @@ -8893,13 +8668,6 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c 1 read-write - - RESERVED - read as 0 - 0 - 1 - read-write - @@ -9154,13 +8922,6 @@ User should write 1 to this bit after the active FAULT signal de-assert and befo 24 read-only - - RESERVED - read-only as 0 - 0 - 4 - read-only - @@ -9205,13 +8966,6 @@ User should write 1 to this bit after the active FAULT signal de-assert and befo 24 read-only - - RESERVED - read-only as 0 - 0 - 4 - read-only - @@ -9469,13 +9223,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 0 - 1 - read-only - @@ -9512,13 +9259,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 write-only - - RESERVED - reserved - 16 - 1 - read-write - SNAPEN 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert @@ -9526,13 +9266,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - reserved - 5 - 1 - read-write - RSTCNT set to reset all counter and related snapshots @@ -9540,20 +9273,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - reserved - 2 - 2 - read-write - - - RESERVED - reserved - 0 - 2 - read-write - @@ -9573,13 +9292,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - reserved - 24 - 7 - read-write - DLYCNT delay clock cycles number @@ -9621,13 +9333,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 0x00000000 0x07FFFFFF - - RESERVED - reserved - 24 - 3 - read-write - PRECNT the clock cycle number which the pre flag will set before the next uvw transition @@ -9673,34 +9378,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UFEN 1- enable trigger output when u flag set @@ -9760,34 +9437,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UFEN 1- load counters to their read registers when u flag set @@ -9847,34 +9496,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UFEN 1- generate dma request when u flag set @@ -9934,34 +9555,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UF u flag, will set when u signal toggle @@ -10021,34 +9614,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UFIE 1- generate interrupt request when u flag set @@ -10104,20 +9669,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 0x00000000 0xCFFFFFFF - - RESERVED - reserved - 31 - 1 - read-only - - - RESERVED - reserved - 30 - 1 - read-only - VCNT vcnt counter @@ -10351,15 +9902,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - 00-x1, phase_cnt will increase at each A posedge -01-x2, phase_cnt will increase at each A/B posedge -10-x4, phase_cnt will increase at each edge(A/B, pos/neg) - 2 - 2 - read-write - ENCTYP 00-abz; 01-pd; 10-ud; 11-reserved @@ -11099,7 +10641,7 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 0xf2000000 0x0 - 0x105c + 0x1058 registers @@ -13882,9 +13424,9 @@ ICMP payload - 4 - 0x30 - 0,1,2,3 + 1 + 0x20 + 0 L3_L4_CFG[%s] no description available 0x400 @@ -15970,13 +15512,6 @@ This bit will be auto cleared after 1 cycle 1 write-only - - RESERVED - not exist - 18 - 13 - read-write - CNTRST 1- reset counter @@ -16224,13 +15759,6 @@ User should set this bit before set CMPEN to 1. 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 16 - 16 - read-write - CH3CMP1F channel 3 compare value 1 match flag @@ -16353,13 +15881,6 @@ User should set this bit before set CMPEN to 1. 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 16 - 16 - read-write - CH3CMP1EN 1- generate interrupt request when ch3cmp1f flag is set @@ -16529,8 +16050,8 @@ User should set this bit before set CMPEN to 1. USB 0xf2020000 - 0x0 - 0x228 + 0x80 + 0x1a8 registers @@ -17264,6 +16785,7 @@ The bit field values description below is represented as (Frame List Size) Numbe DEVICEADDR Device Address Register + UNION_154 0x154 32 0x00000000 @@ -17299,6 +16821,7 @@ If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (be PERIODICLISTBASE Frame List Base Address Register + UNION_154 0x154 32 0x00000000 @@ -17319,6 +16842,7 @@ Only used by the host controller. ASYNCLISTADDR Next Asynch. Address Register + UNION_158 0x158 32 0x00000000 @@ -17340,6 +16864,7 @@ Only used by the host controller. ENDPTLISTADDR Endpoint List Address Register + UNION_158 0x158 32 0x00000000 @@ -22569,8 +22094,8 @@ Write 1 when this bit is 1 will cause unknown result(actually no use except writ I2C 0xf3020000 - 0x0 - 0x34 + 0x4 + 0x30 registers @@ -22582,13 +22107,6 @@ Write 1 when this bit is 1 will cause unknown result(actually no use except writ 0x00000001 0xFFFFFFFF - - RESERVED - No description avaiable - 2 - 30 - read-write - FIFOSIZE FIFO Size: @@ -22610,13 +22128,6 @@ Write 1 when this bit is 1 will cause unknown result(actually no use except writ 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 10 - 22 - read-write - CMPL Set to enable the Completion Interrupt. @@ -22713,13 +22224,6 @@ Interrupts when the FIFO is empty. 0x00000001 0xFFFFFFFF - - RESERVED - No description avaiable - 15 - 17 - read-write - LINESDA Indicates the current status of the SDA line on the bus @@ -22849,13 +22353,6 @@ Slave: indicates that a transaction is targeting the controller (including the G 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 10 - 22 - read-write - ADDR The slave address. @@ -22874,13 +22371,6 @@ For 7-bit addressing mode, the most significant 3 bits are ignored and only the 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 8 - 24 - read-write - DATA Write this register to put one byte of data to the FIFO. @@ -22899,13 +22389,6 @@ Read this register to get one byte of data from the FIFO. 0x00001E00 0x000F9FFF - - RESERVED - No description avaiable - 15 - 5 - read-write - PHASE_START Enable this bit to send a START condition at the beginning of transaction. @@ -22972,13 +22455,6 @@ If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will n 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 3 - 29 - read-write - CMD Write this register with the following values to perform the corresponding actions: @@ -23004,13 +22480,6 @@ Note: No transaction will be issued by the controller when all phases (Start, Ad 0x05252100 0xFFFFFFFF - - RESERVED - No description avaiable - 29 - 3 - read-write - T_SUDAT T_SUDAT defines the data setup time before releasing the SCL. @@ -23037,13 +22506,6 @@ Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) 5 read-write - - RESERVED - No description avaiable - 14 - 2 - read-write - T_SCLRADIO The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. @@ -23111,13 +22573,6 @@ This field is only valid when the controller is in the master mode.0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 5 - 27 - read-write - TPM A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). @@ -23200,13 +22655,6 @@ Write to 1 will clock gate for most logic of the SDP block, dynamic power saving 1 read-only - - RESERVED - Not used - 24 - 4 - read-only - CIPHEN Cipher Enablement, controlled by SW. @@ -23250,13 +22698,6 @@ Write to 1 will clock gate for most logic of the SDP block, dynamic power saving 1 read-write - - RESERVED - Reserved - 18 - 1 - read-write - TSTPKT0IRQ Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. @@ -23338,13 +22779,6 @@ Other values, reserved. 6 read-write - - RESERVED - Not used - 17 - 1 - read-only - AESDIR AES direction @@ -23392,20 +22826,6 @@ For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words.1 read-write - - RESERVED - Not used - 8 - 1 - read-only - - - RESERVED - Not used - 6 - 2 - read-only - DINSWP Decide whether the SDP byteswaps the input data (big-endian data); @@ -23439,27 +22859,6 @@ When all bits are set, the data is assumed to be in the big-endian format0x00000000 0xFFFFFFFF - - RESERVED - Not used - 31 - 1 - read-write - - - RESERVED - Not used - 30 - 1 - read-write - - - RESERVED - Not used - 24 - 6 - read-only - CNTVAL This read-only field shows the current (instantaneous) value of the packet counter @@ -23467,13 +22866,6 @@ When all bits are set, the data is assumed to be in the big-endian format8 read-only - - RESERVED - Not used - 8 - 8 - read-only - CNTINCR The value written to this field is added to the spacket count. @@ -23505,13 +22897,6 @@ When all bits are set, the data is assumed to be in the big-endian format1 write-only - - RESERVED - Not used - 21 - 2 - read-only - CHN1PKT0 the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. @@ -23547,13 +22932,6 @@ When all bits are set, the data is assumed to be in the big-endian format1 write-only - - RESERVED - Not used - 6 - 10 - read-only - ERRSET Working mode setup error. @@ -23606,13 +22984,6 @@ When all bits are set, the data is assumed to be in the big-endian format0x00000040 0xFFFFFFFF - - RESERVED - Not used - 24 - 8 - read-only - INDEX To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. @@ -23622,13 +22993,6 @@ In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys 8 read-write - - RESERVED - Not used - 2 - 14 - read-only - SUBWRD Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field @@ -23750,13 +23114,6 @@ descriptor that is to be executed (or is currently being executed) 8 read-write - - RESERVED - Not used - 7 - 17 - read-write - CIPHIV Load Initial Vector for the AES in this packet. @@ -23801,13 +23158,6 @@ When the semaphore reaches a value of zero, no more operations are issued from t 1 read-write - - RESERVED - Not used - 0 - 1 - read-write - @@ -24804,13 +24154,6 @@ EN is only active after this bit is zero. 1 read-write - - RSV - Reserved - 9 - 22 - read-write - EN Asserted to enable the module @@ -24828,68 +24171,54 @@ EN is only active after this bit is zero. 0x00000000 0xFFFFFFFF - - RSV - Reserved - 8 - 24 - read-only - FIR_OV FIR Overflow err 7 1 - read-only + write-only FFT_OV FFT Overflow Err 6 1 - read-only + write-only WR_ERR AXI Data Write Error 5 1 - read-only + write-only RD_NXT_ERR AXI Read Bus Error for NXT DATA 4 1 - read-only + write-only RD_ERR AXI Data Read Error 3 1 - read-only - - - RSV - Reserved - 2 - 1 - read-only + write-only NXT_CMD_RD_DONE Indicate that next command sequence is already read into the module. 1 1 - read-only + write-only OP_CMD_DONE Indicate that operation cmd is done, and data are available in system memory. 0 1 - read-only + write-only @@ -24943,13 +24272,6 @@ EN is only active after this bit is zero. 1 read-write - - RSV - Write as zero - 2 - 1 - read-write - NXT_CMD_RD_DONE Indicate that next command sequence is already read into the module. @@ -25061,6 +24383,7 @@ Others: Reserved OP_REG0 No description avaiable + UNION_28 0x28 32 0x00000000 @@ -25078,6 +24401,7 @@ Others: Reserved OP_FIR_MISC No description avaiable + UNION_28 0x28 32 0x00000000 @@ -25095,6 +24419,7 @@ Others: Reserved OP_FFT_MISC No description avaiable + UNION_28 0x28 32 0x00000000 @@ -25117,13 +24442,6 @@ n:2^(3+n) 1 read-write - - RSV - Reserved. Should be written as zero - 4 - 2 - read-write - TMP_BLK Memory block for indata. Should be assigned as 1 @@ -25143,6 +24461,7 @@ n:2^(3+n) OP_REG1 No description avaiable + UNION_2C 0x2c 32 0x00000000 @@ -25160,6 +24479,7 @@ n:2^(3+n) OP_FIR_MISC1 No description avaiable + UNION_2C 0x2c 32 0x00000000 @@ -25198,6 +24518,7 @@ n:2^(3+n) OP_REG2 No description avaiable + UNION_30 0x30 32 0x00000000 @@ -25215,6 +24536,7 @@ n:2^(3+n) OP_FFT_INRBUF No description avaiable + UNION_30 0x30 32 0x00000000 @@ -25232,6 +24554,7 @@ n:2^(3+n) OP_REG3 No description avaiable + UNION_34 0x34 32 0x00000000 @@ -25249,6 +24572,7 @@ n:2^(3+n) OP_FIR_INBUF No description avaiable + UNION_34 0x34 32 0x00000000 @@ -25266,6 +24590,7 @@ n:2^(3+n) OP_REG4 No description avaiable + UNION_38 0x38 32 0x00000000 @@ -25283,6 +24608,7 @@ n:2^(3+n) OP_FIR_COEFBUF No description avaiable + UNION_38 0x38 32 0x00000000 @@ -25300,6 +24626,7 @@ n:2^(3+n) OP_FFT_OUTRBUF No description avaiable + UNION_38 0x38 32 0x00000000 @@ -25317,6 +24644,7 @@ n:2^(3+n) OP_REG5 No description avaiable + UNION_3C 0x3c 32 0x00000000 @@ -25334,6 +24662,7 @@ n:2^(3+n) OP_FIR_OUTBUF No description avaiable + UNION_3C 0x3c 32 0x00000000 @@ -25396,9 +24725,9 @@ n:2^(3+n) - 158 + 127 0x4 - cpu0,cpx0,exe0,wak0,cpu0_per,logic0,logic1,logic2,logic3,pmic,pow_cpu0,rst_soc,rst_cpu0,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_pll2,clk_src_clk0_pll2,clk_src_clk1_pll2,clk_src_pll0_ref,clk_src_pll1_ref,clk_src_pll2_ref,mbist_soc,mbist_cpu,mbist_con,dft_start_bus,clk_top_cpu0,clk_top_mct0,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_aud0,clk_top_aud1,clk_top_eth0,clk_top_ptp0,clk_top_ref0,clk_top_ref1,clk_top_ntm0,clk_top_sdc0,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_dac0,clk_top_i2s0,clk_top_i2s1,eth0_mem,sdc0_mem,usb0_mem,ram0_mem,ahbp_mem,femc_mem,rom0_mem,xpi0_mem,xpi1_mem,can0_mem,can1_mem,i2s0_mem,i2s1_mem,pdm0_mem,sdp0_mem,ffa0_mem,cpx0_mem,core_mem,lmm0_mem,ahbp,axis,axic,femc,rom0,lmm0,ram0,mct0,xpi0,xpi1,sdp0,rng0,kman,dma0,dma1,ffa0,gpio,mbx0,wdg0,wdg1,tsns,tmr0,tmr1,tmr2,tmr3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,can0,can1,ptpc,adc0,adc1,adc2,dac0,acmp,i2s0,i2s1,pdm0,dao,msyn,mot0,mot1,eth0,ntm0,sdc0,usb0,ref0,ref1 + cpu0,cpx0,pow_cpu0,rst_soc,rst_cpu0,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_pll2,clk_src_clk0_pll2,clk_src_clk1_pll2,clk_src_pll0_ref,clk_src_pll1_ref,clk_src_pll2_ref,clk_top_cpu0,clk_top_mct0,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_aud0,clk_top_aud1,clk_top_eth0,clk_top_ptp0,clk_top_ref0,clk_top_ref1,clk_top_ntm0,clk_top_sdc0,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_dac0,clk_top_i2s0,clk_top_i2s1,ahbp,axis,axic,femc,rom0,lmm0,ram0,mct0,xpi0,xpi1,sdp0,rng0,kman,dma0,dma1,ffa0,gpio,mbx0,wdg0,wdg1,tsns,tmr0,tmr1,tmr2,tmr3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,can0,can1,ptpc,adc0,adc1,adc2,dac0,acmp,i2s0,i2s1,pdm0,dao,msyn,mot0,mot1,eth0,ntm0,sdc0,usb0,ref0,ref1 RESOURCE[%s] no description available 0x0 @@ -25438,9 +24767,9 @@ n:2^(3+n) - 4 + 2 0x10 - link0,link1,link2,link3 + link0,link1 GROUP0[%s] no description available 0x800 @@ -26579,7 +25908,7 @@ bit3: override to preset3 488 0x8 - pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,px00,px01,px02,px03,px04,px05,px06,px07,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,py00,py01,py02,py03,py04,py05,py06,py07,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07 + pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,rsv93,rsv94,rsv95,rsv96,rsv97,rsv98,rsv99,rsv100,rsv101,rsv102,rsv103,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,rsv416,px00,px01,px02,px03,px04,px05,px06,px07,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,rsv448,py00,py01,py02,py03,py04,py05,py06,py07,rsv457,rsv458,rsv459,rsv460,rsv461,rsv462,rsv463,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,rsv480,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07 PAD[%s] no description available 0x0 @@ -27531,7 +26860,7 @@ XX0: trun off 1: overcurrent happened in low power mode 24 1 - read-write + read-only DISABLE_POWER_LOSS @@ -29110,9 +28439,9 @@ This register should not be changed during PLL and spread spectrum enabled. If - 4 + 3 0x4 - DIV0,DIV1,DIV2,DIV3 + DIV0,DIV1,DIV2 DIV[%s] no description available 0x40 @@ -29568,6 +28897,114 @@ This register should not be changed during PLL and spread spectrum enabled. If + + BACC + BACC + BACC + 0xf5000000 + + 0x0 + 0x10 + registers + + + + CONFIG + Access timing for access + 0x0 + 32 + 0x00000000 + 0x3000FFFF + + + FAST_WRITE + Use fast write +0: Write normally +1: boost write + 29 + 1 + read-write + + + FAST_READ + Use fast read +0: Read normally +1: boost read + 28 + 1 + read-write + + + TIMING + Time in APB clock cycles, for battery timing penerate + 0 + 16 + read-write + + + + + PRE_TIME + Timing gap before rising edge + 0x8 + 32 + 0x00000000 + 0x000FFFFF + + + PRE_RATIO + Ratio of guard band before rising edge +0: 0 +1: 1/32768 of low level width +2: 1/16384 of low level width +14: 1/4 of low level width +15: 1/2 of low level width + 16 + 4 + read-write + + + PRE_OFFSET + guard band before rising edge +this value will be added to ratio number + 0 + 16 + read-write + + + + + POST_TIME + Timing gap after rising edge + 0xc + 32 + 0x00000000 + 0x000FFFFF + + + POST_RATIO + Ratio of guard band after rising edge +0: 0 +1: 1/32768 of high level width +2: 1/16384 of high level width +14: 1/4 of high level width +15: 1/2 of high level width + 16 + 4 + read-write + + + POST_OFFSET + guard band after rising edge +this value will be added to ratio number + 0 + 16 + read-write + + + + + BPOR BPOR @@ -29575,7 +29012,7 @@ This register should not be changed during PLL and spread spectrum enabled. If 0xf5004000 0x0 - 0x14 + 0x10 registers @@ -30056,134 +29493,18 @@ bit3: button long long pressed - BATT_GPR0 - Generic control + 8 + 0x4 + 0,1,2,3,4,5,6,7 + GPR[%s] + no description available 0x0 32 0x00000000 0xFFFFFFFF - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR1 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR2 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR3 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR4 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR5 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR6 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR7 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR + DATA Generic control 0 32 @@ -30200,7 +29521,7 @@ bit3: button long long pressed 0xf5040000 0x0 - 0x18 + 0x14 registers @@ -30427,7 +29748,7 @@ bit3: button long long pressed 0xf5044000 0x0 - 0x2c + 0x28 registers @@ -30726,7 +30047,7 @@ bit3: button long long pressed 0xf504c000 0x0 - 0x24 + 0x20 registers @@ -31026,4 +30347,4 @@ Note, clear can only be cleared when tamper disapeared - \ No newline at end of file + diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h index 4c3bb66f..f24c986d 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_bgpr_regs.h @@ -10,106 +10,32 @@ #define HPM_BGPR_H typedef struct { - __RW uint32_t BATT_GPR0; /* 0x0: Generic control */ - __RW uint32_t BATT_GPR1; /* 0x4: Generic control */ - __RW uint32_t BATT_GPR2; /* 0x8: Generic control */ - __RW uint32_t BATT_GPR3; /* 0xC: Generic control */ - __RW uint32_t BATT_GPR4; /* 0x10: Generic control */ - __RW uint32_t BATT_GPR5; /* 0x14: Generic control */ - __RW uint32_t BATT_GPR6; /* 0x18: Generic control */ - __RW uint32_t BATT_GPR7; /* 0x1C: Generic control */ + __RW uint32_t GPR[8]; /* 0x0 - 0x1C: Generic control */ } BGPR_Type; -/* Bitfield definition for register: BATT_GPR0 */ +/* Bitfield definition for register array: GPR */ /* - * GPR (RW) + * DATA (RW) * * Generic control */ -#define BGPR_BATT_GPR0_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR0_GPR_SHIFT (0U) -#define BGPR_BATT_GPR0_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR0_GPR_SHIFT) & BGPR_BATT_GPR0_GPR_MASK) -#define BGPR_BATT_GPR0_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR0_GPR_MASK) >> BGPR_BATT_GPR0_GPR_SHIFT) +#define BGPR_GPR_DATA_MASK (0xFFFFFFFFUL) +#define BGPR_GPR_DATA_SHIFT (0U) +#define BGPR_GPR_DATA_SET(x) (((uint32_t)(x) << BGPR_GPR_DATA_SHIFT) & BGPR_GPR_DATA_MASK) +#define BGPR_GPR_DATA_GET(x) (((uint32_t)(x) & BGPR_GPR_DATA_MASK) >> BGPR_GPR_DATA_SHIFT) -/* Bitfield definition for register: BATT_GPR1 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR1_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR1_GPR_SHIFT (0U) -#define BGPR_BATT_GPR1_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR1_GPR_SHIFT) & BGPR_BATT_GPR1_GPR_MASK) -#define BGPR_BATT_GPR1_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR1_GPR_MASK) >> BGPR_BATT_GPR1_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR2 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR2_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR2_GPR_SHIFT (0U) -#define BGPR_BATT_GPR2_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR2_GPR_SHIFT) & BGPR_BATT_GPR2_GPR_MASK) -#define BGPR_BATT_GPR2_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR2_GPR_MASK) >> BGPR_BATT_GPR2_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR3 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR3_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR3_GPR_SHIFT (0U) -#define BGPR_BATT_GPR3_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR3_GPR_SHIFT) & BGPR_BATT_GPR3_GPR_MASK) -#define BGPR_BATT_GPR3_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR3_GPR_MASK) >> BGPR_BATT_GPR3_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR4 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR4_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR4_GPR_SHIFT (0U) -#define BGPR_BATT_GPR4_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR4_GPR_SHIFT) & BGPR_BATT_GPR4_GPR_MASK) -#define BGPR_BATT_GPR4_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR4_GPR_MASK) >> BGPR_BATT_GPR4_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR5 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR5_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR5_GPR_SHIFT (0U) -#define BGPR_BATT_GPR5_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR5_GPR_SHIFT) & BGPR_BATT_GPR5_GPR_MASK) -#define BGPR_BATT_GPR5_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR5_GPR_MASK) >> BGPR_BATT_GPR5_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR6 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR6_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR6_GPR_SHIFT (0U) -#define BGPR_BATT_GPR6_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR6_GPR_SHIFT) & BGPR_BATT_GPR6_GPR_MASK) -#define BGPR_BATT_GPR6_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR6_GPR_MASK) >> BGPR_BATT_GPR6_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR7 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR7_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR7_GPR_SHIFT (0U) -#define BGPR_BATT_GPR7_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR7_GPR_SHIFT) & BGPR_BATT_GPR7_GPR_MASK) -#define BGPR_BATT_GPR7_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR7_GPR_MASK) >> BGPR_BATT_GPR7_GPR_SHIFT) +/* GPR register group index macro definition */ +#define BGPR_GPR_0 (0UL) +#define BGPR_GPR_1 (1UL) +#define BGPR_GPR_2 (2UL) +#define BGPR_GPR_3 (3UL) +#define BGPR_GPR_4 (4UL) +#define BGPR_GPR_5 (5UL) +#define BGPR_GPR_6 (6UL) +#define BGPR_GPR_7 (7UL) #endif /* HPM_BGPR_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c b/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c index 85067f4c..2c6621c7 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.c @@ -61,6 +61,11 @@ static uint32_t get_frequency_for_dac(uint32_t instance); */ static uint32_t get_frequency_for_wdg(uint32_t instance); +/** + * @brief Get Clock frequency for PWDG + */ +static uint32_t get_frequency_for_pwdg(void); + /** * @brief Turn on/off the IP clock */ @@ -118,6 +123,9 @@ uint32_t clock_get_frequency(clock_name_t clock_name) case CLK_SRC_GROUP_WDG: clk_freq = get_frequency_for_wdg(node_or_instance); break; + case CLK_SRC_GROUP_PWDG: + clk_freq = get_frequency_for_pwdg(); + break; case CLK_SRC_GROUP_PMIC: clk_freq = FREQ_PRESET1_OSC0_CLK0; break; @@ -219,7 +227,11 @@ static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t ins } if (is_mux_valid) { - clk_freq = get_frequency_for_ip_in_common_group(node); + if (node == clock_node_ahb) { + clk_freq = get_frequency_for_ahb(); + } else { + clk_freq = get_frequency_for_ip_in_common_group(node); + } } return clk_freq; } @@ -251,7 +263,7 @@ static uint32_t get_frequency_for_wdg(uint32_t instance) uint32_t freq_in_hz; /* EXT clock is chosen */ if (WDG_CTRL_CLKSEL_GET(s_wdgs[instance]->CTRL) == 0) { - freq_in_hz = get_frequency_for_cpu(); + freq_in_hz = get_frequency_for_ahb(); } /* PCLK is chosen */ else { @@ -261,6 +273,18 @@ static uint32_t get_frequency_for_wdg(uint32_t instance) return freq_in_hz; } +static uint32_t get_frequency_for_pwdg(void) +{ + uint32_t freq_in_hz; + if (WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL) == 0) { + freq_in_hz = FREQ_PRESET1_OSC0_CLK0; + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + static uint32_t get_frequency_for_cpu(void) { uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); @@ -297,6 +321,12 @@ clk_src_t clock_get_source(clock_name_t clock_name) clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); } break; + case CLK_SRC_GROUP_DAC: + if (node_or_instance < DAC_INSTANCE_NUM) { + clk_src_group = CLK_SRC_GROUP_DAC; + clk_src_index = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[node_or_instance]); + } + break; case CLK_SRC_GROUP_I2S: if (node_or_instance < I2S_INSTANCE_NUM) { clk_src_group = CLK_SRC_GROUP_I2S; @@ -309,6 +339,10 @@ clk_src_t clock_get_source(clock_name_t clock_name) clk_src_index = (WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL) == 0); } break; + case CLK_SRC_GROUP_PWDG: + clk_src_group = CLK_SRC_GROUP_PWDG; + clk_src_index = (WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL) == 0); + break; case CLK_SRC_GROUP_PMIC: clk_src_group = CLK_SRC_GROUP_COMMON; clk_src_index = clock_source_osc0_clk0; @@ -346,7 +380,7 @@ hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) return status_clk_invalid; } - if ((src != clk_adc_src_ahb) && (src != clk_adc_src_ana)) { + if ((src < clk_adc_src_ana0) || (src > clk_adc_src_ahb0)) { return status_clk_src_invalid; } @@ -366,7 +400,7 @@ hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src) return status_clk_invalid; } - if ((src != clk_dac_src_ana) || (src != clk_dac_src_ahb)) { + if ((src < clk_dac_src_ana3) || (src > clk_dac_src_ahb0)) { return status_clk_src_invalid; } @@ -428,6 +462,15 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint } } break; + case CLK_SRC_GROUP_PWDG: + if (src == clk_pwdg_src_osc24m) { + HPM_PWDG->CTRL &= ~WDG_CTRL_CLKSEL_MASK; + } else if (src == clk_pwdg_src_osc32k) { + HPM_PWDG->CTRL |= WDG_CTRL_CLKSEL_MASK; + } else { + status = status_clk_src_invalid; + } + break; case CLK_SRC_GROUP_PMIC: status = status_clk_fixed; break; @@ -507,6 +550,19 @@ void clock_remove_from_group(clock_name_t clock_name, uint32_t group) } } +bool clock_check_in_group(clock_name_t clock_name, uint32_t group) +{ + bool added = false; + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + if (resource < sysctl_resource_end) { + added = sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); + } else if (resource == RESOURCE_SHARED_PTPC) { + added = sysctl_check_group_resource_enable(HPM_SYSCTL, group, sysctl_resource_ptpc); + } + return added; +} + void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) { if (cpu < 2U) { diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h index 28a413a5..8bbd2a84 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_clock_drv.h @@ -45,6 +45,7 @@ enum { #define CLK_SRC_GROUP_DAC (7U) #define CLK_SRC_GROUP_CPU0 (9U) #define CLK_SRC_GROUP_SRC (10U) +#define CLK_SRC_GROUP_PWDG (11U) #define CLK_SRC_GROUP_INVALID (15U) #define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) @@ -65,11 +66,13 @@ typedef enum _clock_sources { clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), - clk_adc_src_ana = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ahb = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), + clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), + clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - clk_dac_src_ana = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), - clk_dac_src_ahb = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), + clk_dac_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), + clk_dac_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), clk_i2s_src_aud0 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), clk_i2s_src_aud1 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 1), @@ -77,6 +80,9 @@ typedef enum _clock_sources { clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), + clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 0), + clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 1), + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), } clk_src_t; @@ -139,7 +145,7 @@ typedef enum _clock_name { clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PWDG, 0), clock_eth0 = MAKE_CLOCK_NAME(sysctl_resource_eth0, CLK_SRC_GROUP_COMMON, clock_node_eth0), clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI, 0), clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI, 1), @@ -296,6 +302,13 @@ void clock_add_to_group(clock_name_t clock_name, uint32_t group); */ void clock_remove_from_group(clock_name_t clock_name, uint32_t group); +/** + * @brief Check IP in specified group + * @param[in] clock_name IP clock name + * @return true if in group, false if not in group + */ +bool clock_check_in_group(clock_name_t clock_name, uint32_t group); + /** * @brief Disconnect the clock group from specified CPU * @param[in] group clock group index, value value is 0/1/2/3 diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h index 28decd78..bf019bb3 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_gpiom_soc_drv.h @@ -14,7 +14,7 @@ */ /* @brief gpiom control module */ -typedef enum hpm6300_gpiom_gpio { +typedef enum gpiom_gpio { gpiom_soc_gpio0 = 0, gpiom_core0_fast = 1, } gpiom_gpio_t; diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h index 24919129..c5f56fee 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_interrupt.h @@ -7,8 +7,8 @@ #ifndef HPM_INTERRUPT_H #define HPM_INTERRUPT_H -#include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_csr_drv.h" #include "hpm_plic_drv.h" /** @@ -37,10 +37,10 @@ ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) } /** - * @brief Disable global IRQ with mask return mstatus + * @brief Disable global IRQ with mask and return mstatus * * @param[in] mask interrupt mask to be disabled - * @retval current mstatus value before irq disabled + * @retval current mstatus value before irq mask is disabled */ ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) { @@ -146,7 +146,6 @@ ATTR_ALWAYS_INLINE static inline void restore_s_global_irq(uint32_t mask) set_csr(CSR_SSTATUS, mask); } - /** * @brief Disable IRQ from interrupt controller for supervisor mode * @@ -780,25 +779,17 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) csrr s3, mstatus \n");\ SAVE_FPU_STATE(); \ SAVE_DSP_CONTEXT(); \ - __asm volatile ("\n\ - c.li a5, 8\n\ - csrs mstatus, a5\n"); \ + __asm volatile("csrsi mstatus, 8"); \ } /* * @brief Complete IRQ Handling */ #define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("\n\ - lui a5, 0x1\n\ - addi a5, a5, -2048\n\ - csrc mie, a5\n"); \ - __asm volatile("\n\ - lui a4, 0xe4200\n");\ + __asm volatile("csrci mstatus, 8"); \ + __asm volatile("lui a4, 0xe4200"); \ __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)\n\ - fence io, io\n"); \ - __asm volatile("csrs mie, a5"); \ + __asm volatile("sw a3, 4(a4)"); \ } /* @@ -824,24 +815,15 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) csrr s3, sstatus \n");\ SAVE_FPU_STATE(); \ SAVE_DSP_CONTEXT(); \ - __asm volatile ("\n\ - c.li a5, 8\n\ - csrs sstatus, a5\n"); \ + __asm volatile("csrsi sstatus, 2"); \ } #define COMPLETE_IRQ_HANDLING_S(irq_num) {\ - __asm volatile("\n\ - lui a5, 0x1\n\ - addi a5, a5, -2048\n\ - csrc sie, a5\n"); \ - __asm volatile("\n\ - lui a4, 0xe4201\n");\ + __asm volatile("csrci sstatus, 2"); \ + __asm volatile("lui a4, 0xe4201"); \ __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)\n\ - fence io, io\n"); \ - __asm volatile("csrs sie, a5"); \ + __asm volatile("sw a3, 4(a4)"); \ } - /* * @brief Exit Nested IRQ Handling at supervisor mode * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: @@ -874,18 +856,6 @@ ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) RESTORE_FCSR() \ RESTORE_UCODE() -/* - * @brief Nested IRQ exit macro : Restore CSRs - * @param[in] irq Target interrupt number - */ -#define NESTED_VPLIC_COMPLETE_INTERRUPT(irq) \ -do { \ - clear_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq); \ - __asm volatile("fence io, io"); \ - set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ -} while (0) - #ifdef __cplusplus #define EXTERN_C extern "C" #else @@ -914,6 +884,7 @@ void ISR_NAME_M(irq_num)(void) \ COMPLETE_IRQ_HANDLING_M(irq_num);\ EXIT_NESTED_IRQ_HANDLING_M();\ RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ __asm volatile("mret\n");\ } @@ -934,6 +905,7 @@ void ISR_NAME_S(irq_num)(void) {\ COMPLETE_IRQ_HANDLING_S(irq_num);\ EXIT_NESTED_IRQ_HANDLING_S();\ RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ __asm volatile("sret\n");\ } diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h index 480e7639..7b848c91 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_l1c_drv.h @@ -7,8 +7,8 @@ #ifndef _HPM_L1_CACHE_H #define _HPM_L1_CACHE_H -#include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_csr_drv.h" #include "hpm_soc.h" /** diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h index fa899118..d7f58667 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_drv.h @@ -20,11 +20,9 @@ */ #define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) #define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW (0x1UL) #define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) #define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) -#define PCFG_PERIPH_SET_CLOCK_AUTO(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW << (p)) /* @brief PCFG irc24m reference */ typedef enum { @@ -229,12 +227,11 @@ static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) * * @param[in] ptr base address * @param[in] limit current limit at low power mode - * @param[in] over_limit set to true means current is greater than limit + * @param[in] over_limit unused parameter, will be discarded */ static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) { - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) - | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(over_limit); + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_ILIMIT_LP_MASK) | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); } /** diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h index e53036a5..a22f579a 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_pcfg_regs.h @@ -240,7 +240,7 @@ typedef struct { #define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) /* - * OVERLOAD_LP (RW) + * OVERLOAD_LP (RO) * * over current in low power mode * 0: current is below setting @@ -248,7 +248,6 @@ typedef struct { */ #define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) #define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDC_PROT_OVERLOAD_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) #define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) /* diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h index 52ba031d..ab90cd08 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ppor_drv.h @@ -11,15 +11,7 @@ typedef enum { ppor_reset_brownout = 1 << 0, - ppor_reset_temperature = 1 << 1, - ppor_reset_pin = 1 << 2, ppor_reset_debug = 1 << 4, - ppor_reset_security_violation = 1 << 5, - ppor_reset_jtag = 1 << 6, - ppor_reset_cpu0_lockup = 1 << 8, - ppor_reset_cpu1_lockup = 1 << 9, - ppor_reset_cpu0_request = 1 << 10, - ppor_reset_cpu1_request = 1 << 11, ppor_reset_wdog0 = 1 << 16, ppor_reset_wdog1 = 1 << 17, ppor_reset_wdog2 = 1 << 18, diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml index 3f9175ce..3458521b 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ses_reg.xml @@ -2821,6 +2821,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -2861,6 +2881,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2901,6 +3041,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2941,6 +3201,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -3173,9 +3553,6 @@ - - - @@ -3634,7 +4011,6 @@ - @@ -3876,9 +4252,6 @@ - - - @@ -4337,7 +4710,6 @@ - @@ -4579,9 +4951,6 @@ - - - @@ -5040,7 +5409,6 @@ - @@ -5240,7 +5608,6 @@ - @@ -5254,7 +5621,6 @@ - @@ -5282,7 +5648,6 @@ - @@ -5375,7 +5740,6 @@ - @@ -5468,7 +5832,6 @@ - @@ -5561,7 +5924,6 @@ - @@ -5654,7 +6016,6 @@ - @@ -5718,10 +6079,12 @@ + + + - @@ -5785,10 +6148,12 @@ + + + - @@ -5852,10 +6217,12 @@ + + + - @@ -5919,10 +6286,12 @@ + + + - @@ -5986,10 +6355,12 @@ + + + - @@ -6053,10 +6424,12 @@ + + + - @@ -6120,10 +6493,12 @@ + + + - @@ -6187,10 +6562,12 @@ + + + - @@ -6254,6 +6631,9 @@ + + + @@ -6833,20 +7213,16 @@ - - - - @@ -6859,7 +7235,6 @@ - @@ -6879,20 +7254,16 @@ - - - - @@ -6905,7 +7276,6 @@ - @@ -6928,7 +7298,6 @@ - @@ -6974,7 +7343,6 @@ - @@ -7037,6 +7405,12 @@ + + + + + + @@ -7800,48 +8174,33 @@ - - - - - - - - - - - - - - - @@ -7947,7 +8306,6 @@ - @@ -7975,17 +8333,14 @@ - - - @@ -8012,7 +8367,6 @@ - @@ -8032,10 +8386,7 @@ - - - @@ -8065,7 +8416,6 @@ - @@ -8093,17 +8443,14 @@ - - - @@ -8130,7 +8477,6 @@ - @@ -8150,10 +8496,7 @@ - - - @@ -8288,12 +8631,10 @@ - - @@ -8446,196 +8787,124 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -8740,7 +9009,6 @@ - @@ -8817,7 +9085,6 @@ - @@ -8916,145 +9183,121 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -9064,12 +9307,10 @@ - - @@ -9222,196 +9463,124 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -9516,7 +9685,6 @@ - @@ -9593,7 +9761,6 @@ - @@ -9692,160 +9859,131 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -9853,7 +9991,6 @@ - @@ -9861,10 +9998,6 @@ - - - - @@ -9874,10 +10007,6 @@ - - - - @@ -9887,10 +10016,6 @@ - - - - @@ -9900,10 +10025,6 @@ - - - - @@ -9913,10 +10034,6 @@ - - - - @@ -9925,8 +10042,6 @@ - - @@ -9943,8 +10058,6 @@ - - @@ -9961,8 +10074,6 @@ - - @@ -9979,8 +10090,6 @@ - - @@ -10015,16 +10124,11 @@ - - - - - @@ -10032,7 +10136,6 @@ - @@ -10040,10 +10143,6 @@ - - - - @@ -10053,10 +10152,6 @@ - - - - @@ -10066,10 +10161,6 @@ - - - - @@ -10079,10 +10170,6 @@ - - - - @@ -10092,10 +10179,6 @@ - - - - @@ -10104,8 +10187,6 @@ - - @@ -10122,8 +10203,6 @@ - - @@ -10140,8 +10219,6 @@ - - @@ -10158,8 +10235,6 @@ - - @@ -10206,7 +10281,6 @@ - @@ -10363,7 +10437,6 @@ - @@ -11997,54 +12070,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -12320,7 +12345,6 @@ - @@ -12363,7 +12387,6 @@ - @@ -12406,7 +12429,6 @@ - @@ -12449,7 +12471,6 @@ - @@ -12491,7 +12512,6 @@ - @@ -12510,7 +12530,6 @@ - @@ -12535,7 +12554,6 @@ - @@ -12578,7 +12596,6 @@ - @@ -12621,7 +12638,6 @@ - @@ -12664,7 +12680,6 @@ - @@ -12706,7 +12721,6 @@ - @@ -12725,7 +12739,6 @@ - @@ -12750,7 +12763,6 @@ - @@ -12793,7 +12805,6 @@ - @@ -12836,7 +12847,6 @@ - @@ -12879,7 +12889,6 @@ - @@ -12921,7 +12930,6 @@ - @@ -12940,7 +12948,6 @@ - @@ -12965,7 +12972,6 @@ - @@ -13008,7 +13014,6 @@ - @@ -13051,7 +13056,6 @@ - @@ -13094,7 +13098,6 @@ - @@ -13136,7 +13139,6 @@ - @@ -13155,7 +13157,6 @@ - @@ -13180,7 +13181,6 @@ - @@ -13223,7 +13223,6 @@ - @@ -13266,7 +13265,6 @@ - @@ -13309,7 +13307,6 @@ - @@ -13351,7 +13348,6 @@ - @@ -13370,7 +13366,6 @@ - @@ -13395,7 +13390,6 @@ - @@ -13438,7 +13432,6 @@ - @@ -13481,7 +13474,6 @@ - @@ -13524,7 +13516,6 @@ - @@ -13566,7 +13557,6 @@ - @@ -13585,7 +13575,6 @@ - @@ -14349,11 +14338,9 @@ - - @@ -14366,7 +14353,6 @@ - @@ -14384,15 +14370,12 @@ - - - @@ -14401,15 +14384,12 @@ - - - @@ -14418,17 +14398,14 @@ - - - @@ -14441,7 +14418,6 @@ - @@ -14459,15 +14435,12 @@ - - - @@ -14476,15 +14449,12 @@ - - - @@ -14493,17 +14463,14 @@ - - - @@ -14516,7 +14483,6 @@ - @@ -14534,15 +14500,12 @@ - - - @@ -14551,15 +14514,12 @@ - - - @@ -14568,17 +14528,14 @@ - - - @@ -14591,7 +14548,6 @@ - @@ -14609,15 +14565,12 @@ - - - @@ -14626,15 +14579,12 @@ - - - @@ -14643,7 +14593,6 @@ - @@ -14653,13 +14602,11 @@ - - @@ -14668,36 +14615,27 @@ - - - - - - - - - @@ -14706,9 +14644,7 @@ - - @@ -14758,14 +14694,12 @@ - - @@ -14908,17 +14842,14 @@ - - - @@ -14929,7 +14860,6 @@ - @@ -14955,7 +14885,6 @@ - @@ -23877,6 +23806,12 @@ + + + + + + @@ -23921,6 +23856,12 @@ + + + + + + @@ -23985,6 +23926,21 @@ + + + + + + + + + + + + + + + @@ -24051,29 +24007,29 @@ - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + @@ -24302,4 +24258,4 @@ - \ No newline at end of file + diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_ses_riscv_cpu_regs.xml b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ses_riscv_cpu_regs.xml index de6e8964..9e30fbc7 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_ses_riscv_cpu_regs.xml +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_ses_riscv_cpu_regs.xml @@ -767,4 +767,4 @@ - \ No newline at end of file + diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h index 4c2d9d69..ec38fbcd 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc.h @@ -556,9 +556,12 @@ /* TSNS base pointer */ #define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) +#include "hpm_bacc_regs.h" /* Address of BACC instances */ /* BACC base address */ #define HPM_BACC_BASE (0xF5000000UL) +/* BACC base pointer */ +#define HPM_BACC ((BACC_Type *) HPM_BACC_BASE) #include "hpm_bpor_regs.h" /* Address of BPOR instances */ @@ -640,4 +643,4 @@ #include "hpm_iomux.h" #include "hpm_pmic_iomux.h" #include "hpm_batt_iomux.h" -#endif /* HPM_SOC_H */ \ No newline at end of file +#endif /* HPM_SOC_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h index c9497f4f..9c7ad728 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_soc_feature.h @@ -63,7 +63,6 @@ */ #define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) #define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_BUS_NUM (1U) #define DMA_SOC_CHANNEL_NUM (8U) #define DMA_SOC_MAX_COUNT (2U) #define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) @@ -117,6 +116,7 @@ /* * ADC Section */ +#define ADC_SOC_IP_VERSION (1U) #define ADC_SOC_SEQ_MAX_LEN (16U) #define ADC_SOC_MAX_TRIG_CH_LEN (4U) #define ADC_SOC_MAX_TRIG_CH_NUM (11U) diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c b/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c index d0bb58cb..5456b1f1 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.c @@ -9,7 +9,6 @@ #include "hpm_soc_feature.h" #define SYSCTL_RESOURCE_GROUP0 0 -#define SYSCTL_RESOURCE_GROUP1 1 #define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | ((cpu & 1) << 24)) @@ -168,6 +167,41 @@ sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t return status_success; } +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t linkable_resource) +{ + uint32_t index, offset; + bool enable; + + index = (linkable_resource - sysctl_resource_linkable_start) / 32; + offset = (linkable_resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + default: + enable = false; + break; + } + + return enable; +} + +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) +{ + uint32_t value; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + value = ptr->GROUP0[index].VALUE; + break; + default: + value = 0; + break; + } + return value; +} + hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) { return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h index 26ca8fd1..169009f4 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_sysctl_drv.h @@ -624,10 +624,26 @@ static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resou * @param[in] resource target resource index * @param[in] mode target resource mode */ -static inline void -sysctl_resource_target_set_mode(SYSCTL_Type *ptr, sysctl_resource_t resource, sysctl_resource_mode_t mode) +static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource, + sysctl_resource_mode_t mode) +{ + ptr->RESOURCE[resource] = + (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | + SYSCTL_RESOURCE_MODE_SET(mode); +} + +/** + * @brief Get target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return target resource mode + */ +static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource) { - ptr->RESOURCE[resource] = (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); + return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); } /** @@ -1172,6 +1188,27 @@ hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clo * @return status_success if everything is okay */ hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); + +/** + * @brief Check group resource enable status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be checked + * @param[in] resource target resource to be checked from group + * @return enable true if resource enable, false if resource disable + */ +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t linkable_resource); + +/** + * @brief Get group resource value + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be getted + * @param[in] index target group index + * @return group index value + */ +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); + /** * @brief Add resource to CPU0 * @@ -1208,7 +1245,7 @@ void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *confi void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); /** - * @brief Save data to GPU0 GPR starting from given index + * @brief Save data to CPU0 GPR starting from given index * * @param[in] ptr SYSCTL_Type base address * @param[in] start Starting GPR index @@ -1220,7 +1257,7 @@ void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); /** - * @brief Get data saved from GPU0 GPR starting from given index + * @brief Get data saved from CPU0 GPR starting from given index * * @param[in] ptr SYSCTL_Type base address * @param[in] start Starting GPR index diff --git a/common/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h b/common/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h index 2f36dfc8..3d65643e 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/hpm_trgmmux_src.h @@ -60,8 +60,6 @@ #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0x33UL) #define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x34UL) #define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM0_INPUT_SRC_CMP2_OUT (0x36UL) -#define HPM_TRGM0_INPUT_SRC_CMP3_OUT (0x37UL) #define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x38UL) /* trgm1_input mux definitions */ @@ -115,8 +113,6 @@ #define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT3 (0x33UL) #define HPM_TRGM1_INPUT_SRC_CMP0_OUT (0x34UL) #define HPM_TRGM1_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM1_INPUT_SRC_CMP2_OUT (0x36UL) -#define HPM_TRGM1_INPUT_SRC_CMP3_OUT (0x37UL) #define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x38UL) /* trgm0_output mux definitions */ diff --git a/common/libraries/hpm_sdk/soc/HPM6360/soc_modules.list b/common/libraries/hpm_sdk/soc/HPM6360/soc_modules.list index 06e20aa5..297b2284 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/soc_modules.list +++ b/common/libraries/hpm_sdk/soc/HPM6360/soc_modules.list @@ -33,4 +33,5 @@ CONFIG_HAS_HPMSDK_MCHTMR=y CONFIG_HAS_HPMSDK_FFA=y CONFIG_HAS_HPMSDK_TSNS=y CONFIG_HAS_HPMSDK_DAC=y +CONFIG_HAS_HPMSDK_QEI=y diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld index 20ad96b8..1a64227c 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash.ld @@ -25,7 +25,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text : { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(.text) *(.text*) @@ -44,36 +56,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - .vectors ORIGIN(ILM) : AT(etext) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext + __vector_ram_end__ - __vector_ram_start__) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -81,8 +82,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -126,12 +125,13 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM .bss (NOLOAD) : { @@ -139,11 +139,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -151,13 +149,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -201,5 +223,6 @@ SECTIONS __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld index 70f59e1e..9d7d3839 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_uf2.ld @@ -27,7 +27,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { . = ALIGN(8); *(.text) *(.text*) @@ -46,39 +58,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -86,8 +84,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -131,12 +127,13 @@ SECTIONS PROVIDE (edata = .); } > SDRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM .bss (NOLOAD) : { @@ -144,11 +141,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -156,13 +151,37 @@ SECTIONS __bss_end__ = .; } > SDRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > SDRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > SDRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > SDRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){ + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -205,4 +224,7 @@ SECTIONS __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld index 3f65dbce..33a10cdf 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_sdram_xip.ld @@ -44,7 +44,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(.text) *(.text*) @@ -63,39 +75,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -103,8 +101,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -142,31 +138,30 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) . = ALIGN(8); + __data_end__ = .; PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); } > SDRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM - __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -174,13 +169,37 @@ SECTIONS __bss_end__ = .; } > SDRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > SDRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > SDRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > SDRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -223,4 +242,7 @@ SECTIONS __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld index 323439d8..59598393 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_uf2.ld @@ -26,7 +26,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { . = ALIGN(8); *(.text) *(.text*) @@ -45,39 +57,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -85,8 +83,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -130,12 +126,13 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM .bss (NOLOAD) : { @@ -143,11 +140,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -155,13 +150,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -205,5 +224,6 @@ SECTIONS __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld index 8ff892ab..0d7b18db 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/flash_xip.ld @@ -24,6 +24,7 @@ __app_load_addr__ = ORIGIN(XPI0) + 0x3000; __boot_header_length__ = __boot_header_end__ - __boot_header_start__; __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + SECTIONS { .nor_cfg_option __nor_cfg_option_load_addr__ : { @@ -43,7 +44,19 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + KEEP(*(.vector_s_table)) + KEEP(*(.isr_s_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(.text) *(.text*) @@ -62,39 +75,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -102,8 +101,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -147,25 +144,23 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); - __ramfunc_start__ = .; + PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); - __ramfunc_end__ = .; + PROVIDE(__ramfunc_end__ = .); } > ILM - __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -173,13 +168,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -223,5 +242,6 @@ SECTIONS __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld index 9f1111c5..d9b9a4c5 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/ram.ld @@ -58,19 +58,19 @@ SECTIONS KEEP (*(.fini)) /* section information for usbh class */ - . = ALIGN(4); + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); - PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); } > ILM - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -78,8 +78,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -124,7 +122,8 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -137,11 +136,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -149,13 +146,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -191,6 +212,7 @@ SECTIONS . = ALIGN(8); __stack_base__ = .; . += STACK_SIZE; + . = ALIGN(8); PROVIDE (_stack = .); PROVIDE (_stack_safe = .); } > DLM @@ -198,5 +220,6 @@ SECTIONS __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 128K, "stack and heap total size larger than 128k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(ILM), "****** FAILED! ILM has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S index e6edcbc3..f0b1812e 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S @@ -16,6 +16,7 @@ _start: .option push .option norelax la gp, __global_pointer$ + la tp, __thread_pointer$ .option pop /* reset mstatus to 0*/ diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c index abb52b8c..bdd2320a 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/reset.c @@ -30,6 +30,13 @@ __attribute__((weak)) void _clean_up(void) __attribute__((weak)) void c_startup(void) { uint32_t i, size; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __data_load_addr__[], __fast_load_addr__[], __noncacheable_init_load_addr__[]; + #if defined(FLASH_XIP) || defined(FLASH_UF2) extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; size = __vector_ram_end__ - __vector_ram_start__; @@ -38,13 +45,6 @@ __attribute__((weak)) void c_startup(void) } #endif - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - /* bss section */ size = __bss_end__ - __bss_start__; for (i = 0; i < size; i++) { @@ -60,19 +60,19 @@ __attribute__((weak)) void c_startup(void) /* data section LMA: etext */ size = __data_end__ - __data_start__; for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + i); + *(__data_start__ + i) = *(__data_load_addr__ + i); } /* ramfunc section LMA: etext + data length */ size = __ramfunc_end__ - __ramfunc_start__; for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); } - /* noncacheable init section LMA: etext + data length + ramfunc legnth */ + /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ size = __noncacheable_init_end__ - __noncacheable_init_start__; for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } } diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf index 7e7feba4..cafe8b9b 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf @@ -14,16 +14,15 @@ define region AXI_SRAM = [from 0x01080000 size 256k]; define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; define region AHB_SRAM = [from 0xF0300000 size 32k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - /* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; +define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -31,12 +30,12 @@ define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_cla define block framebuffer with alignment = 8 { section .framebuffer }; /* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; /* Initialization */ do not initialize { section .noncacheable }; @@ -49,8 +48,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors, block vectors_s }; initialize by copy { block cherryusb_usbh_class_info }; diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf index add2a04b..027459ac 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf @@ -24,7 +24,7 @@ define block dtors { section .dtors, section .dtors define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -32,12 +32,12 @@ define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_cla define block framebuffer with alignment = 8 { section .framebuffer }; /* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; /* Initialization */ do not initialize { section .noncacheable }; @@ -50,8 +50,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors, block vectors_s }; initialize by copy { block cherryusb_usbh_class_info }; diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf index 051f1d9f..f486f65a 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf @@ -7,7 +7,7 @@ define memory with size = 4G; /* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; +define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ define region ILM = [from 0x00000000 size 128k]; /* ILM */ @@ -19,13 +19,13 @@ define region AHB_SRAM = [from 0xF0300000 size 32k]; /* Blocks */ define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -41,12 +41,12 @@ define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_a define exported symbol __boot_header_length__ = size of block boot_header; define exported symbol __fw_size__ = 0x1000; -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; /* Initialization */ do not initialize { section .noncacheable }; @@ -59,8 +59,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors, block vectors_s }; initialize by copy { block cherryusb_usbh_class_info }; diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf index c7b672c8..5ff19e8f 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf @@ -15,8 +15,6 @@ define region AXI_SRAM = [from 0x01080000 size 256k]; define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; define region AHB_SRAM = [from 0xF0300000 size 32k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - /* Blocks */ define block vectors with fixed order { section .vector_table, section .isr_vector }; define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; @@ -25,7 +23,7 @@ define block dtors { section .dtors, section .dtors define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -33,12 +31,12 @@ define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_cla define block framebuffer with alignment = 8 { section .framebuffer }; /* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; /* Initialization */ do not initialize { section .noncacheable }; @@ -51,8 +49,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors, block vectors_s }; initialize by copy { block cherryusb_usbh_class_info }; diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf index 335ebc70..979c70e8 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf @@ -7,7 +7,7 @@ define memory with size = 4G; /* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; +define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ define region ILM = [from 0x00000000 size 128k]; /* ILM */ @@ -16,8 +16,6 @@ define region AXI_SRAM = [from 0x01080000 size 256k]; define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; define region AHB_SRAM = [from 0xF0300000 size 32k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - /* Blocks */ define block vectors with fixed order { section .vector_table, section .isr_vector }; define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; @@ -26,7 +24,7 @@ define block dtors { section .dtors, section .dtors define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -42,12 +40,12 @@ define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_a define exported symbol __boot_header_length__ = size of block boot_header; define exported symbol __fw_size__ = 0x1000; -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; /* Initialization */ do not initialize { section .noncacheable }; @@ -60,8 +58,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors, block vectors_s }; initialize by copy { block cherryusb_usbh_class_info }; diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf index d5b9dcd6..8b89e6a4 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf @@ -9,12 +9,10 @@ define memory with size = 4G; /* Regions */ define region ILM = [from 0x00000000 size 128k]; /* ILM */ define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 256k]; +define region AXI_SRAM = [from 0x01080000 size 256k]; define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; define region AHB_SRAM = [from 0xF0300000 size 32k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 128k with error "stack and heap total size larger than 128k"; - /* Blocks */ define block vectors with fixed order { section .vector_table, section .isr_vector }; define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; @@ -23,7 +21,7 @@ define block dtors { section .dtors, section .dtors define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -31,8 +29,8 @@ define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_cla define block framebuffer with alignment = 8 { section .framebuffer }; /* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; define exported symbol _stack = end of block stack + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; @@ -49,8 +47,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. /* Placement */ place at start of ILM { symbol _start }; diff --git a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h index 4e90fb3f..e1765fe4 100644 --- a/common/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h +++ b/common/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h @@ -202,3 +202,4 @@ IRQ_S_HANDLER 76 /* SYSCTL IRQ handler */ IRQ_S_HANDLER 77 /* DEBUG[0] IRQ handler */ IRQ_S_HANDLER 78 /* DEBUG[1] IRQ handler */ + diff --git a/common/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml b/common/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml index a2d8e36c..d56dce09 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml +++ b/common/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml @@ -42,14 +42,14 @@ 0xc0000 0x0 - 0x800 + 0x824 registers 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz DI[%s] no description available 0x0 @@ -76,7 +76,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz DO[%s] no description available 0x100 @@ -160,7 +160,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz OE[%s] no description available 0x200 @@ -244,7 +244,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz IF[%s] no description available 0x300 @@ -271,7 +271,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz IE[%s] no description available 0x400 @@ -355,7 +355,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz PL[%s] no description available 0x500 @@ -439,7 +439,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz TP[%s] no description available 0x600 @@ -523,7 +523,7 @@ 16 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz AS[%s] no description available 0x700 @@ -997,7 +997,7 @@ Note: combinational interrupt is sensitive to environment noise 16 0x80 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv,rsv,rsv,rsv,rsv,rsv,rsv,gpiox,gpioy,gpioz + gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpiox,gpioy,gpioz ASSIGN[%s] no description available 0x0 @@ -1428,20 +1428,20 @@ Set to 0 means disable current channel 0x4 32 0x00000000 - 0xFFFFFFFF + 0xFFF0FFF0 THSHDH threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 + 20 + 12 read-write THSHDL threshold low - 0 - 16 + 4 + 12 read-write @@ -1569,14 +1569,14 @@ Adc_clk must to be set to same as bus clock at this mode interrupt for one trigger conversion complete if enabled 31 1 - write-only + read-write TRIG_SW_CFLCT No description avaiable 30 1 - write-only + read-write TRIG_HW_CFLCT @@ -1590,14 +1590,14 @@ Adc_clk must to be set to same as bus clock at this mode read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel 28 1 - write-only + read-write SEQ_SW_CFLCT sequence queue conflict interrup, set if HW or SW trigger received during conversion 27 1 - write-only + read-write SEQ_HW_CFLCT @@ -1611,21 +1611,21 @@ Adc_clk must to be set to same as bus clock at this mode dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set 25 1 - write-only + read-write SEQ_CMPT the whole sequence complete interrupt 24 1 - write-only + read-write SEQ_CVC one conversion complete in seq_queue if related seq_int_en is set 23 1 - write-only + read-write DMA_FIFO_FULL @@ -1646,7 +1646,7 @@ Adc_clk must to be set to same as bus clock at this mode set if one chanel watch dog event triggered 0 19 - write-only + read-write @@ -1663,14 +1663,14 @@ Adc_clk must to be set to same as bus clock at this mode interrupt for one trigger conversion complete if enabled 31 1 - write-only + read-write TRIG_SW_CFLCT No description avaiable 30 1 - write-only + read-write TRIG_HW_CFLCT @@ -1684,14 +1684,14 @@ Adc_clk must to be set to same as bus clock at this mode read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel 28 1 - write-only + read-write SEQ_SW_CFLCT sequence queue conflict interrup, set if HW or SW trigger received during conversion 27 1 - write-only + read-write SEQ_HW_CFLCT @@ -1705,42 +1705,42 @@ Adc_clk must to be set to same as bus clock at this mode dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set 25 1 - write-only + read-write SEQ_CMPT the whole sequence complete interrupt 24 1 - write-only + read-write SEQ_CVC one conversion complete in seq_queue if related seq_int_en is set 23 1 - write-only + read-write DMA_FIFO_FULL DMA fifo full interrupt, user need to check clock frequency if it's set. 22 1 - write-only + read-write AHB_ERR set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr 21 1 - write-only + read-write WDOG set if one chanel watch dog event triggered 0 19 - write-only + read-write @@ -2140,24 +2140,6 @@ If cont_en is 0, this bit is not used - - seq_wr_addr - No description avaiable - 0x808 - 32 - 0x00000000 - 0x00FFFFFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 24 - read-only - - - seq_dma_cfg No description avaiable @@ -2338,7 +2320,7 @@ it may be updated period according to config, also may be updated due to other q CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 22 adc clock cycles(based on clock after divider); + convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz). 4 @@ -2412,14 +2394,14 @@ Adc_clk must to be set to same as bus clock at this mode interrupt for one trigger conversion complete if enabled 31 1 - write-only + read-write TRIG_SW_CFLCT No description avaiable 30 1 - write-only + read-write TRIG_HW_CFLCT @@ -2433,14 +2415,14 @@ Adc_clk must to be set to same as bus clock at this mode read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel 28 1 - write-only + read-write SEQ_SW_CFLCT sequence queue conflict interrup, set if HW or SW trigger received during conversion 27 1 - write-only + read-write SEQ_HW_CFLCT @@ -2454,21 +2436,21 @@ Adc_clk must to be set to same as bus clock at this mode dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set 25 1 - write-only + read-write SEQ_CMPT the whole sequence complete interrupt 24 1 - write-only + read-write SEQ_CVC one conversion complete in seq_queue if related seq_int_en is set 23 1 - write-only + read-write DMA_FIFO_FULL @@ -2489,7 +2471,7 @@ Adc_clk must to be set to same as bus clock at this mode set if one chanel watch dog event triggered 0 14 - write-only + read-write @@ -2506,14 +2488,14 @@ Adc_clk must to be set to same as bus clock at this mode interrupt for one trigger conversion complete if enabled 31 1 - write-only + read-write TRIG_SW_CFLCT No description avaiable 30 1 - write-only + read-write TRIG_HW_CFLCT @@ -2527,14 +2509,14 @@ Adc_clk must to be set to same as bus clock at this mode read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel 28 1 - write-only + read-write SEQ_SW_CFLCT sequence queue conflict interrup, set if HW or SW trigger received during conversion 27 1 - write-only + read-write SEQ_HW_CFLCT @@ -2548,21 +2530,21 @@ Adc_clk must to be set to same as bus clock at this mode dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set 25 1 - write-only + read-write SEQ_CMPT the whole sequence complete interrupt 24 1 - write-only + read-write SEQ_CVC one conversion complete in seq_queue if related seq_int_en is set 23 1 - write-only + read-write DMA_FIFO_FULL @@ -2583,7 +2565,7 @@ Adc_clk must to be set to same as bus clock at this mode set if one chanel watch dog event triggered 0 14 - write-only + read-write @@ -2965,8 +2947,8 @@ should set to (21-convert_clock_number+1). SPI 0xf0030000 - 0x0 - 0x80 + 0x10 + 0x70 registers @@ -2978,13 +2960,6 @@ should set to (21-convert_clock_number+1). 0x00020780 0xFFFF1F9F - - RESERVED - No description avaiable - 18 - 14 - read-write - ADDRLEN Address length in bytes @@ -3692,8 +3667,8 @@ When an SPI transaction other than slave status-reading command ends, this bit w UART 0xf0040000 - 0x0 - 0x40 + 0x10 + 0x30 registers @@ -3705,13 +3680,6 @@ When an SPI transaction other than slave status-reading command ends, this bit w 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 2 - 30 - read-write - FIFOSIZE The depth of RXFIFO and TXFIFO @@ -3750,6 +3718,7 @@ OSC<=8: The over-sample ratio is 8 RBR Receiver Buffer Register (when DLAB = 0) + UNION_20 0x20 32 0x00000000 @@ -3767,6 +3736,7 @@ OSC<=8: The over-sample ratio is 8 THR Transmitter Holding Register (when DLAB = 0) + UNION_20 0x20 32 0x00000000 @@ -3784,6 +3754,7 @@ OSC<=8: The over-sample ratio is 8 DLL Divisor Latch LSB (when DLAB = 1) + UNION_20 0x20 32 0x00000001 @@ -3801,6 +3772,7 @@ OSC<=8: The over-sample ratio is 8 IER Interrupt Enable Register (when DLAB = 0) + UNION_24 0x24 32 0x00000000 @@ -3849,6 +3821,7 @@ character timeout interrupt DLM Divisor Latch MSB (when DLAB = 1) + UNION_24 0x24 32 0x00000000 @@ -3866,6 +3839,7 @@ character timeout interrupt IIR Interrupt Identification Register + UNION_28 0x28 32 0x00000001 @@ -3892,6 +3866,7 @@ Register (FIFOE) is set to 1. FCR FIFO Control Register + UNION_28 0x28 32 0x00000000 @@ -4196,6 +4171,23 @@ register is read. + + GPR + GPR Register + 0x3c + 32 + 0x00000000 + 0x000000FF + + + DATA + An one-byte storage register + 0 + 8 + read-write + + + @@ -5602,8 +5594,8 @@ TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch tri WDOG 0xf0090000 - 0x0 - 0x20 + 0x10 + 0x10 registers @@ -5781,7 +5773,7 @@ Restart Register. 0xf00a0000 0x0 - 0x30 + 0x24 registers @@ -5800,13 +5792,6 @@ Restart Register. 1 read-write - - RESERVED - Reserved - 16 - 15 - read-only - BARCTL Bus Acccess Response Control, when bit 15:14= @@ -5818,13 +5803,6 @@ Restart Register. 2 read-write - - RESERVED - Reserved - 9 - 5 - read-only - BEIE Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. @@ -5870,13 +5848,6 @@ Restart Register. 1 read-write - - RESERVED - Reserved - 2 - 2 - read-only - TWMEIE TX word message empty interrupt enable. @@ -5905,13 +5876,6 @@ Restart Register. 0x000000E2 0xFFFF3FFF - - RESERVED - Not used - 24 - 8 - read-only - RFVC RX FIFO valid message count @@ -6016,13 +5980,6 @@ Restart Register. 1 read-only - - RESERVED - Not used - 2 - 2 - read-only - TWME TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. @@ -6078,9 +6035,9 @@ Restart Register. - 4 + 1 0x4 - TXFIFO0,TXFIFO1,TXFIFO2,TXFIFO3 + TXFIFO0 TXWRD[%s] no description available 0x10 @@ -6100,9 +6057,9 @@ can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 4 + 1 0x4 - RXFIFO0,RXFIFO1,RXFIFO2,RXFIFO3 + RXFIFO0 RXWRD[%s] no description available 0x20 @@ -6148,7 +6105,7 @@ can also use 4x32 burst read from 0x020 to read 4 words from the FIFO.0xf00b0000 0x0 - 0x200c + 0x3004 registers @@ -6199,13 +6156,6 @@ If this bit is cleared, capture result will be updated at each capture event1 read-write - - RESERVED - No description avaiable - 5 - 1 - read-write - COMP_EN set to enable compare, will be cleared by HW when compare event triggered @@ -6229,8 +6179,8 @@ If this bit is cleared, capture result will be updated at each capture event FINE_COARSE_SEL - 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow -1: coarse update, ns counter add ss_incr[7:0] each clk + 0: coarse update, ns counter add ss_incr[7:0] each clk +1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow 1 1 read-write @@ -6584,6 +6534,44 @@ clr to use ptpc0 for canx + + ptpc_can_ts_sel + No description avaiable + 0x3000 + 32 + 0x00000000 + 0xFFFFFF00 + + + TSU_TBIN3_SEL + No description avaiable + 26 + 6 + read-write + + + TSU_TBIN2_SEL + No description avaiable + 20 + 6 + read-write + + + TSU_TBIN1_SEL + No description avaiable + 14 + 6 + read-write + + + TSU_TBIN0_SEL + No description avaiable + 8 + 6 + read-write + + + @@ -6637,8 +6625,8 @@ Specifies which DMA source, if any, is routed to a particular DMA channel. See t DMA 0xf00c4000 - 0x0 - 0x140 + 0x10 + 0x130 registers @@ -7189,13 +7177,6 @@ This register exists only when the address bus width is wider than 32 bits.0x00000000 0xFFFFFFFF - - RESERVED - Not used - 7 - 25 - read-write - SFTRST Soft Reset, Perform a software reset of the RNG This bit is self-clearing. @@ -7223,13 +7204,6 @@ This register exists only when the address bus width is wider than 32 bits.1 read-write - - RESERVED - Not used - 2 - 2 - read-only - GENSD Generate Seed, when both ST and GS triggered, ST first and GS next. @@ -7254,13 +7228,6 @@ This register exists only when the address bus width is wider than 32 bits.0x00000000 0xFFFFFFFF - - RESERVED - Not used - 7 - 25 - read-only - MIRQERR Mask Interrupt Request for Error @@ -7284,13 +7251,6 @@ This register exists only when the address bus width is wider than 32 bits.1 read-write - - RESERVED - Not used - 2 - 2 - read-only - FUFMOD FIFO underflow response mode @@ -7312,13 +7272,6 @@ This register exists only when the address bus width is wider than 32 bits.0x00000000 0xFFFFFFFF - - RESERVED - Not used - 24 - 8 - read-only - SCPF Self Check Pass Fail @@ -7326,13 +7279,6 @@ This register exists only when the address bus width is wider than 32 bits.3 read-only - - RESERVED - Not used - 17 - 4 - read-only - FUNCERR Error was detected, check ESR register for details @@ -7354,13 +7300,6 @@ This register exists only when the address bus width is wider than 32 bits.4 read-only - - RESERVED - Not used - 7 - 1 - read-only - NSDDN New seed done. @@ -7410,13 +7349,6 @@ automatically if the CTRL[ARS] is set. 1 read-only - - RESERVED - Not used - 0 - 1 - read-only - @@ -7427,33 +7359,6 @@ automatically if the CTRL[ARS] is set. 0x00000000 0xFFFFFF3F - - RESERVED - OSC1 Satistics test pass failed. -Indicates the pass or fail status of the various statistics tests on the last seed generated. -0 Pass -1 Fail - 24 - 8 - read-only - - - RESERVED - OSC0 Satistics test pass failed. -Indicates the pass or fail status of the various statistics tests on the last seed generated. -0 Pass -1 Fail - 16 - 8 - read-only - - - RESERVED - Not used - 8 - 8 - read-only - FUFE FIFO access error(underflow) @@ -7461,17 +7366,6 @@ Indicates the pass or fail status of the various statistics tests on the last se 1 read-only - - RESERVED - Statistical test error -Indicates whether the statistical tests for the last generated seed was failed or not. This bit is sticky and is -cleared by a hardware or software reset or by writing 1 to the CMD[CE]. -0 No fail for the statistical tests. -1 Failed the statistical tests during the initialization - 4 - 1 - read-only - SCKERR Self-test error @@ -7481,30 +7375,6 @@ hardware reset or by writing 1 to the CMD[CE] 1 read-only - - RESERVED - Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a -software or hardware reset. - 2 - 1 - read-only - - - RESERVED - Indicates that the oscillator in the RNG is broken. This bit is sticky and can only be cleared by a -software or hardware reset. - 1 - 1 - read-only - - - RESERVED - Linear feedback shift register (LFSR) error -When this bit is set, the interrupt generated was caused by a failure of one of the LFSRs in any of the RNG LFSR ciruit. - 0 - 1 - read-only - @@ -7805,13 +7675,6 @@ bit2: software key 0: not selected, 1:selected 0x00000000 0xFFFFFFFF - - RSV - Reserved - 19 - 13 - read-write - SFTRST_RX software reset the RX module if asserted to be 1'b1. Self-clear. @@ -7996,13 +7859,6 @@ This bit controls the generation of an interrupt when an error condition (UD, O 0x00000000 0xFFFFFFFF - - RSV - No description avaiable - 16 - 16 - read-write - TX TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. @@ -8027,13 +7883,6 @@ This bit controls the generation of an interrupt when an error condition (UD, O 0x00000000 0xFFFFFFFF - - RSV - Reserved - 17 - 15 - read-only - TX_UD Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. @@ -8062,13 +7911,6 @@ This bit controls the generation of an interrupt when an error condition (UD, O 4 read-only - - RSV - Reserved - 0 - 1 - read-only - @@ -8119,13 +7961,6 @@ This bit controls the generation of an interrupt when an error condition (UD, O 0x40000000 0xFFFFFFFF - - RSV - Reserved - 31 - 1 - read-write - BCLK_GATEOFF Gate off the bclk. Asserted to gate-off the BCLK. @@ -8282,13 +8117,6 @@ Note: For correct operation, this bit should be configured when the I2S is disab 0x00042000 0xFFFFEC01 - - RSV - Reserved - 14 - 18 - read-write - MCLK_GATEOFF Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. @@ -8296,20 +8124,6 @@ Note: For correct operation, this bit should be configured when the I2S is disab 1 read-write - - RSV - Reserved - 11 - 1 - read-write - - - RSV - Reserved - 10 - 1 - read-write - MCLKOE Master clock output to pad enable @@ -9061,6 +8875,7 @@ otherwise the shadow registers can not be written. sta Counter start register + UNION_STA 0x4 32 0x00000000 @@ -9081,18 +8896,12 @@ otherwise the shadow registers can not be written. 24 read-write - - RESERVED - reserved - 0 - 4 - read-write - rld Counter reload register + UNION_RLD 0x8 32 0x00000000 @@ -9112,13 +8921,6 @@ otherwise the shadow registers can not be written. 24 read-write - - RESERVED - reserved - 0 - 4 - read-write - @@ -9212,13 +9014,6 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c 0x00000000 0xFFFF0003 - - RESERVED - read as 0 - 29 - 3 - read-write - CMPSELEND assign the last comparator for this output channel @@ -9226,13 +9021,6 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c 5 read-write - - RESERVED - read as 0 - 21 - 3 - read-write - CMPSELBEG assign the first comparator for this output channel @@ -9247,13 +9035,6 @@ and clr to 0 when timer reload. Software can invert the output by setting chan_c 1 read-write - - RESERVED - read as 0 - 0 - 1 - read-write - @@ -9501,13 +9282,6 @@ User should write 1 to this bit after the active FAULT signal de-assert and befo 24 read-only - - RESERVED - read-only as 0 - 0 - 4 - read-only - @@ -9552,13 +9326,6 @@ User should write 1 to this bit after the active FAULT signal de-assert and befo 24 read-only - - RESERVED - read-only as 0 - 0 - 4 - read-only - @@ -9816,13 +9583,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 0 - 1 - read-only - @@ -9871,13 +9631,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 write-only - - RESERVED - reserved - 16 - 1 - read-write - SNAPEN 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert @@ -9885,13 +9638,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - reserved - 5 - 1 - read-write - RSTCNT set to reset all counter and related snapshots @@ -9899,20 +9645,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - reserved - 2 - 2 - read-write - - - RESERVED - reserved - 0 - 2 - read-write - @@ -9932,13 +9664,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - reserved - 24 - 7 - read-write - DLYCNT delay clock cycles number @@ -9980,13 +9705,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 0x00000000 0x07FFFFFF - - RESERVED - reserved - 24 - 3 - read-write - PRECNT the clock cycle number which the pre flag will set before the next uvw transition @@ -10032,34 +9750,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UFEN 1- enable trigger output when u flag set @@ -10119,34 +9809,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UFEN 1- load counters to their read registers when u flag set @@ -10206,34 +9868,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UFEN 1- generate dma request when u flag set @@ -10293,34 +9927,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UF u flag, will set when u signal toggle @@ -10380,34 +9986,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - No description avaiable - 27 - 1 - read-write - - - RESERVED - No description avaiable - 26 - 1 - read-write - - - RESERVED - No description avaiable - 25 - 1 - read-write - - - RESERVED - No description avaiable - 24 - 1 - read-write - UFIE 1- generate interrupt request when u flag set @@ -10463,20 +10041,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 0x00000000 0xCFFFFFFF - - RESERVED - reserved - 31 - 1 - read-only - - - RESERVED - reserved - 30 - 1 - read-only - VCNT vcnt counter @@ -10722,15 +10286,6 @@ Note: user should configure pair bit and this bitfield before PWM output is enab 1 read-write - - RESERVED - 00-x1, phase_cnt will increase at each A posedge -01-x2, phase_cnt will increase at each A/B posedge -10-x4, phase_cnt will increase at each edge(A/B, pos/neg) - 2 - 2 - read-write - ENCTYP 00-abz; 01-pd; 10-ud; 11-reserved @@ -11657,13 +11212,6 @@ So a good procedure to stop and turn on the display is: 0x00000000 0xFFFFFFFF - - RSV - Reserved - 28 - 4 - read-write - Y Sets the display size vertical resolution in pixels. @@ -11671,13 +11219,6 @@ So a good procedure to stop and turn on the display is: 12 read-write - - RSV - Reserved - 12 - 4 - read-write - X Sets the display size horizontal resolution in pixels. @@ -11695,13 +11236,6 @@ So a good procedure to stop and turn on the display is: 0x00000000 0xFFFFFFFF - - RSV - Reserved - 31 - 1 - read-write - FP HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC @@ -11709,13 +11243,6 @@ So a good procedure to stop and turn on the display is: 9 read-write - - RSV - Reserved - 20 - 2 - read-write - BP HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC @@ -11723,13 +11250,6 @@ So a good procedure to stop and turn on the display is: 9 read-write - - RSV - Reserved - 9 - 2 - read-write - PW HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. @@ -11747,13 +11267,6 @@ So a good procedure to stop and turn on the display is: 0x00000000 0xFFFFFFFF - - RSV - Reserved - 31 - 1 - read-write - FP VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC @@ -11761,13 +11274,6 @@ So a good procedure to stop and turn on the display is: 9 read-write - - RSV - Reserved - 20 - 2 - read-write - BP VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC @@ -11775,13 +11281,6 @@ So a good procedure to stop and turn on the display is: 9 read-write - - RSV - Reserved - 9 - 2 - read-write - PW VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. @@ -11882,13 +11381,6 @@ So a good procedure to stop and turn on the display is: 8 read-write - - RSV - Interrupt enable for DMA underflow - 8 - 8 - read-write - URGENT_UNDERRUN Asserted when the output buffer urgent underrun condition encountered @@ -11927,13 +11419,6 @@ So a good procedure to stop and turn on the display is: 0x00000000 0xFFFFFFFF - - RSV - Reserved - 8 - 24 - read-write - THRSH Threshold to start the lcd raster (0--0x7F) @@ -11967,20 +11452,6 @@ So a good procedure to stop and turn on the display is: 1 read-write - - RSV - Reserved to be asserted. - 18 - 1 - read-write - - - RSV - Asserted when posx and posy are changed - 17 - 1 - read-write - SHADOW_LOAD_EN Shadow Load Enable @@ -12010,7 +11481,7 @@ FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Eve 0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. 0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. 0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), byte sequence as B,R +0100b - 16 bpp (RGB565), the low byte contains teh full R component. 0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] 1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A 1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 @@ -12081,13 +11552,6 @@ Others: Reserved. 0x00000000 0xFFFFFFFF - - RSV - Reserved - 16 - 16 - read-write - LOCD The system alpha value for the data stream of current layer stream (SRC) @@ -12112,13 +11576,6 @@ Others: Reserved. 0x00000000 0xFFFFFFFF - - RSV - Reserved - 28 - 4 - read-write - HEIGHT Height of the layer in pixels @@ -12126,13 +11583,6 @@ Others: Reserved. 12 read-write - - RSV - Reserved - 12 - 4 - read-write - WIDTH Width of the layer in pixels (Note: not actual width-1) @@ -12212,13 +11662,6 @@ If zero, it means max 8. 3 read-write - - RSV - Reserved - 16 - 5 - read-write - PITCH Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. @@ -12272,13 +11715,6 @@ This bit will be shadowed. 1 read-write - - RSV - Reserved - 29 - 1 - read-write - C0 Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) @@ -12312,13 +11748,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 27 - 5 - read-write - C1 Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). @@ -12326,13 +11755,6 @@ typically -16 (0x1F0). 11 read-write - - RSV - Reserved - 11 - 5 - read-write - C4 Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). @@ -12350,13 +11772,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 27 - 5 - read-write - C2 Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). @@ -12364,13 +11779,6 @@ typically -16 (0x1F0). 11 read-write - - RSV - Reserved - 11 - 5 - read-write - C3 Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). @@ -12403,13 +11811,6 @@ Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Ca 3 read-write - - RSV - Reserved - 1 - 3 - read-write - UPDATE_EN CLUT Update Enable @@ -12444,13 +11845,6 @@ Hardware will automatically clear this bit when selected CLUT is updated accordi 0x00000000 0xBF9AAFFF - - RSV - Reserved - 31 - 1 - read-write - COLOR_EXT If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. @@ -12546,13 +11940,6 @@ When asserted, this bit clears RXFIFO on every SOF. 1 read-write - - RSV - Reserved - 13 - 1 - read-write - STORAGE_MODE 00: Normal Mode (one plane mode) @@ -12563,13 +11950,6 @@ When asserted, this bit clears RXFIFO on every SOF. 2 read-write - - RSV - Reserved - 7 - 3 - read-write - COLOR_FORMATS input color formats: @@ -12608,13 +11988,6 @@ Others: Undefined 0x00000000 0xFFFFFF5F - - RSV - Reserved - 14 - 18 - read-write - ERR_CL_BWID_CFG_INT_EN The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable @@ -12638,13 +12011,6 @@ Others: Undefined 1 read-write - - RSV - Reserved - 10 - 1 - read-write - EOF_INT_EN End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. @@ -12654,13 +12020,6 @@ Others: Undefined 1 read-write - - RSV - Reserved - 8 - 1 - read-write - RF_OR_INTEN RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. @@ -12670,13 +12029,6 @@ Others: Undefined 1 read-write - - RSV - Reserved - 4 - 1 - read-write - FB2_DMA_DONE_INTEN Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA @@ -12697,13 +12049,6 @@ transfer done. 1 read-write - - RSV - Reserved - 1 - 1 - read-write - SOF_INT_EN Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. @@ -12755,13 +12100,6 @@ transfer done. 3 read-write - - RSV - Reserved - 6 - 3 - read-write - DMA_REQ_EN_RFF DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. @@ -12788,13 +12126,6 @@ transfer done. 0x00000000 0xFFFFA7FC - - RSV - Reserved - 20 - 12 - read-write - ERR_CL_BWID_CFG The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found @@ -12809,13 +12140,6 @@ transfer done. 1 write-only - - RSV - Reserved - 15 - 3 - read-write - RF_OR_INT RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing @@ -12844,13 +12168,6 @@ transfer done. 1 write-only - - RSV - Reserved - 8 - 1 - read-write - EOF_INT End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) @@ -12869,13 +12186,6 @@ transfer done. 1 write-only - - RSV - Reserved - 3 - 3 - read-write - HRESP_ERR_INT Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing @@ -12904,13 +12214,6 @@ In Two-Plane Mode, Y buffer1 30 read-write - - RSV - Reserved - 0 - 2 - read-write - @@ -12929,13 +12232,6 @@ In Two-Plane Mode, Y buffer2 30 read-write - - RSV - Reserved - 0 - 2 - read-write - @@ -12946,13 +12242,6 @@ In Two-Plane Mode, Y buffer2 0x00000000 0xFFFFFFFF - - RSV - Reserved - 16 - 16 - read-write - LINEBSP_STRIDE Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. @@ -13004,13 +12293,6 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 1 read-write - - RSV - Reserved - 13 - 18 - read-write - AWQOS AWQOS for bus fabric arbitration @@ -13018,13 +12300,6 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 4 read-write - - RSV - Reserved - 0 - 6 - read-write - @@ -13042,13 +12317,6 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 30 read-write - - RSV - Reserved - 0 - 2 - read-write - @@ -13066,13 +12334,6 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 30 read-write - - RSV - Reserved - 0 - 2 - read-write - @@ -13097,13 +12358,6 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 1 read-write - - RSV - Reserved - 9 - 21 - read-write - BIG_END Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. @@ -13120,30 +12374,6 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should - - MAX_WN_CYCLE - Max Window Size Register - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - ROW - Max Width-1 - 16 - 16 - read-write - - - COL - Max Height-1 - 0 - 16 - read-write - - - CSC_COEF0 Color Space Conversion Config Register 0 @@ -13170,13 +12400,6 @@ As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should 1 read-write - - RSV - Reserved - 29 - 1 - read-write - C0 Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) @@ -13210,13 +12433,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 27 - 5 - read-write - C1 Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). @@ -13224,13 +12440,6 @@ typically -16 (0x1F0). 11 read-write - - RSV - Reserved - 11 - 5 - read-write - C4 Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). @@ -13248,13 +12457,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 27 - 5 - read-write - C2 Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). @@ -13262,13 +12464,6 @@ typically -16 (0x1F0). 11 read-write - - RSV - Reserved - 11 - 5 - read-write - C3 Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). @@ -13286,13 +12481,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 24 - 8 - read-write - LIMIT Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. @@ -13310,13 +12498,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 24 - 8 - read-write - LIMIT Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. @@ -13337,13 +12518,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - reserved - 24 - 8 - read-only - HIST_Y the appearance of bin x (x=(address-DATA0)/4) @@ -13380,13 +12554,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 23 - 9 - read-write - ARQOS QoS for AXI read bus @@ -13426,13 +12593,6 @@ typically -16 (0x1F0). 1 read-write - - RSV - Asserted to re-shadow the registers to enable on-the-fly new display pattern generation. Auto clear to zero. - 10 - 1 - read-write - CLKGATE Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. @@ -13440,20 +12600,6 @@ typically -16 (0x1F0). 1 read-write - - RSV - Enable handshake with LCD0 controller. When this is set, the PDMA will not process an entire framebuffer, but will instead process rows of NxN blocks in a double-buffer handshake with the LCDIF. This enables the use of the onboard SRAM for a partial frame buffer. - 8 - 1 - read-write - - - RSV - Enable the next irq interrupt - 7 - 1 - read-write - IRQ_EN Enable normal interrupt @@ -13482,13 +12628,6 @@ typically -16 (0x1F0). 1 read-write - - RSV - Asserted to use repeat mode - 2 - 1 - read-write - PDMA_SFTRST Software Reset. @@ -13529,19 +12668,12 @@ Write 0 to exit software reset mode. 8 read-only - - RSV - Reserved - 10 - 6 - read-only - PDMA_DONE PDMA one image done 9 1 - read-only + write-only AXI_ERR_ID @@ -13571,19 +12703,12 @@ Write 0 to exit software reset mode. 1 write-only - - RSV - Asserted to indicate NEXT_CMD event triggering IRQ - 1 - 1 - write-only - IRQ Asserted to indicate a IRQ event 0 1 - write-only + read-only @@ -14145,13 +13270,6 @@ typically -16 (0x1F0). 1 read-write - - RSV - Reserved - 29 - 1 - read-write - C0 CSC parameters C0 @@ -14292,13 +13410,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFC - - RSV - Reserved - 23 - 9 - read-write - ARQOS QoS for AXI read channel @@ -14494,13 +13605,6 @@ For 32 bits per pixel, it will be set as 2. 0x00000000 0xFFFFFFFC - - RSV - Reserved - 18 - 14 - read-write - AWQOS No description avaiable @@ -14689,13 +13793,6 @@ For 32 bits per pixel, it will be set as 2. 0x00000000 0xFFFFFFFF - - RSV - Reserved - 23 - 9 - read-write - JD_UVSWAP Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. @@ -14734,20 +13831,6 @@ For 32 bits per pixel, it will be set as 2. 1 read-write - - RSV - memory power down - 16 - 1 - read-write - - - RSV - No description avaiable - 10 - 6 - read-write - CLKGATE Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. @@ -14826,13 +13909,6 @@ Auto clear. 1 read-only - - RSV - Reserved - 15 - 16 - read-only - AXI_ERR_ID the axi err id @@ -14914,13 +13990,6 @@ The module is completely not busy only when in_dma_transfer_done and out_dma_tra 0x00000000 0xFFFFFFFF - - RSV - No description avaiable - 16 - 16 - read-write - IMG Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) @@ -14938,13 +14007,6 @@ The module is completely not busy only when in_dma_transfer_done and out_dma_tra 0x00000000 0xFFFFFFFF - - RSV - No description avaiable - 16 - 16 - read-write - IMG Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) @@ -15038,13 +14100,6 @@ The n-th address read will be actually the data written for n-1 th address, and 1 read-write - - RSV - Reserved - 29 - 1 - read-write - C0 Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) @@ -15078,13 +14133,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 27 - 5 - read-write - C1 Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). @@ -15092,13 +14140,6 @@ typically -16 (0x1F0). 11 read-write - - RSV - Reserved - 11 - 5 - read-write - C4 Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). @@ -15116,13 +14157,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 27 - 5 - read-write - C2 Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). @@ -15130,13 +14164,6 @@ typically -16 (0x1F0). 11 read-write - - RSV - Reserved - 11 - 5 - read-write - C3 Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). @@ -15168,13 +14195,6 @@ typically -16 (0x1F0). 1 read-write - - RSV - Reserved - 29 - 1 - read-write - C0 CSC parameters C0 @@ -15206,13 +14226,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 27 - 5 - read-write - C1 CSC parameters C1 @@ -15220,13 +14233,6 @@ typically -16 (0x1F0). 11 read-write - - RSV - Reserved - 11 - 5 - read-write - C4 CSC parameters C4 @@ -15244,13 +14250,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 27 - 5 - read-write - C2 CSC parameters C2 @@ -15258,13 +14257,6 @@ typically -16 (0x1F0). 11 read-write - - RSV - Reserved - 11 - 5 - read-write - C3 CSC parameters C3 @@ -15282,13 +14274,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 27 - 5 - read-write - C6 CSC parameters C6 @@ -15296,13 +14281,6 @@ typically -16 (0x1F0). 11 read-write - - RSV - Reserved - 11 - 5 - read-write - C5 CSC parameters C5 @@ -15320,13 +14298,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFFF - - RSV - Reserved - 27 - 5 - read-write - C8 CSC parameters C8 @@ -15334,13 +14305,6 @@ typically -16 (0x1F0). 11 read-write - - RSV - Reserved - 11 - 5 - read-write - C7 CSC parameters C7 @@ -15358,13 +14322,6 @@ typically -16 (0x1F0). 0x00000000 0xFFFFFFF7 - - RSV - No description avaiable - 4 - 28 - read-write - RE Encoder Use only. @@ -15390,13 +14347,6 @@ Asseted to enable the Restart Marker processing. A Restart Marker is inserted in 0x00000000 0xFFFFFFFF - - RSV - No description avaiable - 26 - 6 - read-write - NMCU Encoder Use only. @@ -15415,13 +14365,6 @@ The number of NMCU to be generated in encoder mode 0x00000000 0xFFFFFFFF - - RSV - No description avaiable - 16 - 16 - read-write - NRST Encoder use only. @@ -15443,13 +14386,6 @@ It is the number of MCUs between two Restart Markers (if enabled) minus 1. The c 0x00000000 0xFFFFFFFF - - RSV - No description avaiable - 8 - 24 - read-write - NBLOCK Encoder use only. @@ -15493,7 +14429,7 @@ The selection of the Huffman table for the encoding of the DC coefficients in th 0xf2000000 0x0 - 0x105c + 0x1058 registers @@ -18276,9 +17212,9 @@ ICMP payload - 4 - 0x30 - 0,1,2,3 + 1 + 0x20 + 0 L3_L4_CFG[%s] no description available 0x400 @@ -20370,13 +19306,6 @@ This bit will be auto cleared after 1 cycle 1 write-only - - RESERVED - not exist - 18 - 13 - read-write - CNTRST 1- reset counter @@ -20624,13 +19553,6 @@ User should set this bit before set CMPEN to 1. 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 16 - 16 - read-write - CH3CMP1F channel 3 compare value 1 match flag @@ -20753,13 +19675,6 @@ User should set this bit before set CMPEN to 1. 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 16 - 16 - read-write - CH3CMP1EN 1- generate interrupt request when ch3cmp1f flag is set @@ -20959,8 +19874,8 @@ User should set this bit before set CMPEN to 1. USB 0xf2020000 - 0x0 - 0x228 + 0x80 + 0x1a8 registers @@ -21694,6 +20609,7 @@ The bit field values description below is represented as (Frame List Size) Numbe DEVICEADDR Device Address Register + UNION_154 0x154 32 0x00000000 @@ -21729,6 +20645,7 @@ If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (be PERIODICLISTBASE Frame List Base Address Register + UNION_154 0x154 32 0x00000000 @@ -21749,6 +20666,7 @@ Only used by the host controller. ASYNCLISTADDR Next Asynch. Address Register + UNION_158 0x158 32 0x00000000 @@ -21770,6 +20688,7 @@ Only used by the host controller. ENDPTLISTADDR Endpoint List Address Register + UNION_158 0x158 32 0x00000000 @@ -22969,7 +21888,7 @@ Bit. 0xf2030000 0x0 - 0xf70 + 0x548 registers @@ -26948,13 +25867,6 @@ Values: 0x00000000 0xFF0FFFFF - - RESERVED - No description avaiable - 24 - 8 - read-write - ENET1_RXCLK_DLY_SEL No description avaiable @@ -27221,8 +26133,8 @@ set from pad， two option here: I2C 0xf3020000 - 0x0 - 0x34 + 0x4 + 0x30 registers @@ -27234,13 +26146,6 @@ set from pad， two option here: 0x00000001 0xFFFFFFFF - - RESERVED - No description avaiable - 2 - 30 - read-write - FIFOSIZE FIFO Size: @@ -27262,13 +26167,6 @@ set from pad， two option here: 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 10 - 22 - read-write - CMPL Set to enable the Completion Interrupt. @@ -27365,13 +26263,6 @@ Interrupts when the FIFO is empty. 0x00000001 0xFFFFFFFF - - RESERVED - No description avaiable - 15 - 17 - read-write - LINESDA Indicates the current status of the SDA line on the bus @@ -27501,13 +26392,6 @@ Slave: indicates that a transaction is targeting the controller (including the G 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 10 - 22 - read-write - ADDR The slave address. @@ -27526,13 +26410,6 @@ For 7-bit addressing mode, the most significant 3 bits are ignored and only the 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 8 - 24 - read-write - DATA Write this register to put one byte of data to the FIFO. @@ -27551,13 +26428,6 @@ Read this register to get one byte of data from the FIFO. 0x00001E00 0x000F9FFF - - RESERVED - No description avaiable - 15 - 5 - read-write - PHASE_START Enable this bit to send a START condition at the beginning of transaction. @@ -27624,13 +26494,6 @@ If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will n 0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 3 - 29 - read-write - CMD Write this register with the following values to perform the corresponding actions: @@ -27656,13 +26519,6 @@ Note: No transaction will be issued by the controller when all phases (Start, Ad 0x05252100 0xFFFFFFFF - - RESERVED - No description avaiable - 29 - 3 - read-write - T_SUDAT T_SUDAT defines the data setup time before releasing the SCL. @@ -27689,13 +26545,6 @@ Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) 5 read-write - - RESERVED - No description avaiable - 14 - 2 - read-write - T_SCLRADIO The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. @@ -27763,13 +26612,6 @@ This field is only valid when the controller is in the master mode.0x00000000 0xFFFFFFFF - - RESERVED - No description avaiable - 5 - 27 - read-write - TPM A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). @@ -27852,13 +26694,6 @@ Write to 1 will clock gate for most logic of the SDP block, dynamic power saving 1 read-only - - RESERVED - Not used - 24 - 4 - read-only - CIPHEN Cipher Enablement, controlled by SW. @@ -27902,13 +26737,6 @@ Write to 1 will clock gate for most logic of the SDP block, dynamic power saving 1 read-write - - RESERVED - Reserved - 18 - 1 - read-write - TSTPKT0IRQ Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. @@ -27982,13 +26810,6 @@ Other values, reserved. 6 read-write - - RESERVED - Not used - 17 - 1 - read-only - AESDIR AES direction @@ -28036,20 +26857,6 @@ For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words.1 read-write - - RESERVED - Not used - 8 - 1 - read-only - - - RESERVED - Not used - 6 - 2 - read-only - DINSWP Decide whether the SDP byteswaps the input data (big-endian data); @@ -28083,27 +26890,6 @@ When all bits are set, the data is assumed to be in the big-endian format0x00000000 0xFFFFFFFF - - RESERVED - Not used - 31 - 1 - read-write - - - RESERVED - Not used - 30 - 1 - read-write - - - RESERVED - Not used - 24 - 6 - read-only - CNTVAL This read-only field shows the current (instantaneous) value of the packet counter @@ -28111,13 +26897,6 @@ When all bits are set, the data is assumed to be in the big-endian format8 read-only - - RESERVED - Not used - 8 - 8 - read-only - CNTINCR The value written to this field is added to the spacket count. @@ -28149,13 +26928,6 @@ When all bits are set, the data is assumed to be in the big-endian format1 write-only - - RESERVED - Not used - 21 - 2 - read-only - CHN1PKT0 the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. @@ -28191,13 +26963,6 @@ When all bits are set, the data is assumed to be in the big-endian format1 write-only - - RESERVED - Not used - 6 - 10 - read-only - ERRSET Working mode setup error. @@ -28250,13 +27015,6 @@ When all bits are set, the data is assumed to be in the big-endian format0x00000040 0xFFFFFFFF - - RESERVED - Not used - 24 - 8 - read-only - INDEX To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. @@ -28266,13 +27024,6 @@ In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys 8 read-write - - RESERVED - Not used - 2 - 14 - read-only - SUBWRD Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field @@ -28394,13 +27145,6 @@ descriptor that is to be executed (or is currently being executed) 8 read-write - - RESERVED - Not used - 7 - 17 - read-write - CIPHIV Load Initial Vector for the AES in this packet. @@ -28445,13 +27189,6 @@ When the semaphore reaches a value of zero, no more operations are issued from t 1 read-write - - RESERVED - Not used - 0 - 1 - read-write - @@ -29433,9 +28170,9 @@ pending device access. - 211 + 195 0x4 - cpu0_core,cpu0_subsys,exe0,wak0,cpu0_per,cpu1_core,cpx1_subsys,exe1,wak1,cpu1_per,logic0,logic1,logic2,logic3,pmic,pow_con,pow_vis,pow_cpu0,pow_cpu1,rst_soc,rst_con,rst_vis,rst_cpu0,rst_cpu1,clk_src_xtal,clk_src_pll0,clk_src_pll0clk0,clk_src_pll1,clk_src_pll1clk0,clk_src_pll1clk1,clk_src_pll2,clk_src_pll2clk0,clk_src_pll2clk1,clk_src_pll3,clk_src_pll3clk0,clk_src_pll4,clk_src_pll4clk0,mbist_soc,mbist_cpu,mbist_cpu1,mbist_con,mbist_vis,clk_top_cpu0,clk_top_mchtmr0,clk_top_cpu1,clk_top_mchtmr1,clk_top_axi,clk_top_conn,clk_top_vis,clk_top_ahb,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_gptmr0,clk_top_gptmr1,clk_top_gptmr2,clk_top_gptmr3,clk_top_gptmr4,clk_top_gptmr5,clk_top_gptmr6,clk_top_gptmr7,clk_top_uart0,clk_top_uart1,clk_top_uart2,clk_top_uart3,clk_top_uart4,clk_top_uart5,clk_top_uart6,clk_top_uart7,clk_top_uart8,clk_top_uart9,clk_top_uart10,clk_top_uart11,clk_top_uart12,clk_top_uart13,clk_top_uart14,clk_top_uart15,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_lcdc,clk_top_cam0,clk_top_cam1,clk_top_enet0,clk_top_enet1,clk_top_ptp0,clk_top_ptp1,clk_top_ref0,clk_top_ref1,clk_top_ntmr0,clk_top_ntmr1,clk_top_sdxc0,clk_top_sdxc1,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_adc3,clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3,ahbapb_bus,axi_bus,conn_bus,vis_bus,femc,rom,lmm0,lmm1,mchtmr0,mchtmr1,axi_sram0,axi_sram1,xpi0,xpi1,sdp,rng,keym,hdma,xdma,gpio,mbx0,mbx1,wdg0,wdg1,wdg2,wdg3,gptmr0,gptmr1,gptmr2,gptmr3,gptmr4,gptmr5,gptmr6,gptmr7,uart0,uart1,uart2,uart3,uart4,uart5,uart6,uart7,uart8,uart9,uart10,uart11,uart12,uart13,uart14,uart15,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,can0,can1,can2,can3,ptpc,adc0,adc1,adc2,adc3,acmp,i2s0,i2s1,i2s2,i2s3,pdm,dao,synt,mot0,mot1,mot2,mot3,lcdc,cam0,cam1,jpeg,pdma,enet0,enet1,ntmr0,ntmr1,sdxc0,sdxc1,usb0,usb1,ref0,ref1 + cpu0_core,cpu0_subsys,cpu1_core,cpx1_subsys,pow_con,pow_vis,pow_cpu0,pow_cpu1,rst_soc,rst_con,rst_vis,rst_cpu0,rst_cpu1,clk_src_xtal,clk_src_pll0,clk_src_pll0clk0,clk_src_pll1,clk_src_pll1clk0,clk_src_pll1clk1,clk_src_pll2,clk_src_pll2clk0,clk_src_pll2clk1,clk_src_pll3,clk_src_pll3clk0,clk_src_pll4,clk_src_pll4clk0,clk_top_cpu0,clk_top_mchtmr0,clk_top_cpu1,clk_top_mchtmr1,clk_top_axi,clk_top_conn,clk_top_vis,clk_top_ahb,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_gptmr0,clk_top_gptmr1,clk_top_gptmr2,clk_top_gptmr3,clk_top_gptmr4,clk_top_gptmr5,clk_top_gptmr6,clk_top_gptmr7,clk_top_uart0,clk_top_uart1,clk_top_uart2,clk_top_uart3,clk_top_uart4,clk_top_uart5,clk_top_uart6,clk_top_uart7,clk_top_uart8,clk_top_uart9,clk_top_uart10,clk_top_uart11,clk_top_uart12,clk_top_uart13,clk_top_uart14,clk_top_uart15,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_lcdc,clk_top_cam0,clk_top_cam1,clk_top_enet0,clk_top_enet1,clk_top_ptp0,clk_top_ptp1,clk_top_ref0,clk_top_ref1,clk_top_ntmr0,clk_top_ntmr1,clk_top_sdxc0,clk_top_sdxc1,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_adc3,clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3,ahbapb_bus,axi_bus,conn_bus,vis_bus,femc,rom,lmm0,lmm1,mchtmr0,mchtmr1,axi_sram0,axi_sram1,xpi0,xpi1,sdp,rng,keym,hdma,xdma,gpio,mbx0,mbx1,wdg0,wdg1,wdg2,wdg3,gptmr0,gptmr1,gptmr2,gptmr3,gptmr4,gptmr5,gptmr6,gptmr7,uart0,uart1,uart2,uart3,uart4,uart5,uart6,uart7,uart8,uart9,uart10,uart11,uart12,uart13,uart14,uart15,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,can0,can1,can2,can3,ptpc,adc0,adc1,adc2,adc3,acmp,i2s0,i2s1,i2s2,i2s3,pdm,dao,synt,mot0,mot1,mot2,mot3,lcdc,cam0,cam1,jpeg,pdma,enet0,enet1,ntmr0,ntmr1,sdxc0,sdxc1,usb0,usb1,ref0,ref1 RESOURCE[%s] no description available 0x0 @@ -29475,9 +28212,9 @@ pending device access. - 4 + 3 0x10 - 0,1,2,3 + 0,1,2 GROUP0[%s] no description available 0x800 @@ -29559,9 +28296,9 @@ pending device access. - 4 + 3 0x10 - 0,1,2,3 + 0,1,2 GROUP1[%s] no description available 0x840 @@ -30549,7 +29286,7 @@ bit3: override to preset3 492 0x8 - pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,pc28,pc29,pc30,pc31,pd00,pd01,pd02,pd03,pd04,pd05,pd06,pd07,pd08,pd09,pd10,pd11,pd12,pd13,pd14,pd15,pd16,pd17,pd18,pd19,pd20,pd21,pd22,pd23,pd24,pd25,pd26,pd27,pd28,pd29,pd30,pd31,pe00,pe01,pe02,pe03,pe04,pe05,pe06,pe07,pe08,pe09,pe10,pe11,pe12,pe13,pe14,pe15,pe16,pe17,pe18,pe19,pe20,pe21,pe22,pe23,pe24,pe25,pe26,pe27,pe28,pe29,pe30,pe31,pf00,pf01,pf02,pf03,pf04,pf05,pf06,pf07,pf08,pf09,pf10,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,px00,px01,px02,px03,px04,px05,px06,px07,px08,px09,px10,px11,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,py00,py01,py02,py03,py04,py05,py06,py07,py08,py09,py10,py11,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,rsv,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07,pz08,pz09,pz10,pz11 + pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,pc28,pc29,pc30,pc31,pd00,pd01,pd02,pd03,pd04,pd05,pd06,pd07,pd08,pd09,pd10,pd11,pd12,pd13,pd14,pd15,pd16,pd17,pd18,pd19,pd20,pd21,pd22,pd23,pd24,pd25,pd26,pd27,pd28,pd29,pd30,pd31,pe00,pe01,pe02,pe03,pe04,pe05,pe06,pe07,pe08,pe09,pe10,pe11,pe12,pe13,pe14,pe15,pe16,pe17,pe18,pe19,pe20,pe21,pe22,pe23,pe24,pe25,pe26,pe27,pe28,pe29,pe30,pe31,pf00,pf01,pf02,pf03,pf04,pf05,pf06,pf07,pf08,pf09,pf10,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,rsv416,px00,px01,px02,px03,px04,px05,px06,px07,px08,px09,px10,px11,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,rsv448,py00,py01,py02,py03,py04,py05,py06,py07,py08,py09,py10,py11,rsv461,rsv462,rsv463,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,rsv480,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07,pz08,pz09,pz10,pz11 PAD[%s] no description available 0x0 @@ -31466,7 +30203,7 @@ XX0: trun off 1: overcurrent happened in low power mode 24 1 - read-write + read-only DISABLE_POWER_LOSS @@ -33157,9 +31894,9 @@ When there is two channels, the samples in the 32-bits are: bit [31:16]: the sam - 28 + 1 0x4 - S0B1,S1B1,S1B2,S1B3,S1MA2,S1MA3,S2B1,S2B2,S2B3,S2MA2,S2MA3,S3B1,S3B2,S3B3,S3MA2,S3MA3,S4B1,S4B2,S4B3,S4MA2,S4MA3,S5B1,S5B2,S5B3,S5MA2,S5MA3,S6B1,STE_ACT + STE_ACT COEF[%s] no description available 0xa0 @@ -33600,7 +32337,7 @@ if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) 0xf5004000 0x0 - 0x14 + 0x10 registers @@ -34143,134 +32880,18 @@ bit3: button long long pressed - BATT_GPR0 - Generic control + 8 + 0x4 + 0,1,2,3,4,5,6,7 + GPR[%s] + no description available 0x0 32 0x00000000 0xFFFFFFFF - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR1 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR2 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR3 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR4 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR5 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR6 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - BATT_GPR7 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR + DATA Generic control 0 32 @@ -34287,7 +32908,7 @@ bit3: button long long pressed 0xf501c000 0x0 - 0x2c + 0x28 registers @@ -34494,7 +33115,7 @@ bit3: button long long pressed 0xf5040000 0x0 - 0x18 + 0x14 registers @@ -34819,7 +33440,7 @@ bit3: button long long pressed 0xf504c000 0x0 - 0x24 + 0x20 registers @@ -35119,4 +33740,4 @@ Note, clear can only be cleared when tamper disapeared - \ No newline at end of file + diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h index 4c3bb66f..f24c986d 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h @@ -10,106 +10,32 @@ #define HPM_BGPR_H typedef struct { - __RW uint32_t BATT_GPR0; /* 0x0: Generic control */ - __RW uint32_t BATT_GPR1; /* 0x4: Generic control */ - __RW uint32_t BATT_GPR2; /* 0x8: Generic control */ - __RW uint32_t BATT_GPR3; /* 0xC: Generic control */ - __RW uint32_t BATT_GPR4; /* 0x10: Generic control */ - __RW uint32_t BATT_GPR5; /* 0x14: Generic control */ - __RW uint32_t BATT_GPR6; /* 0x18: Generic control */ - __RW uint32_t BATT_GPR7; /* 0x1C: Generic control */ + __RW uint32_t GPR[8]; /* 0x0 - 0x1C: Generic control */ } BGPR_Type; -/* Bitfield definition for register: BATT_GPR0 */ +/* Bitfield definition for register array: GPR */ /* - * GPR (RW) + * DATA (RW) * * Generic control */ -#define BGPR_BATT_GPR0_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR0_GPR_SHIFT (0U) -#define BGPR_BATT_GPR0_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR0_GPR_SHIFT) & BGPR_BATT_GPR0_GPR_MASK) -#define BGPR_BATT_GPR0_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR0_GPR_MASK) >> BGPR_BATT_GPR0_GPR_SHIFT) +#define BGPR_GPR_DATA_MASK (0xFFFFFFFFUL) +#define BGPR_GPR_DATA_SHIFT (0U) +#define BGPR_GPR_DATA_SET(x) (((uint32_t)(x) << BGPR_GPR_DATA_SHIFT) & BGPR_GPR_DATA_MASK) +#define BGPR_GPR_DATA_GET(x) (((uint32_t)(x) & BGPR_GPR_DATA_MASK) >> BGPR_GPR_DATA_SHIFT) -/* Bitfield definition for register: BATT_GPR1 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR1_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR1_GPR_SHIFT (0U) -#define BGPR_BATT_GPR1_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR1_GPR_SHIFT) & BGPR_BATT_GPR1_GPR_MASK) -#define BGPR_BATT_GPR1_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR1_GPR_MASK) >> BGPR_BATT_GPR1_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR2 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR2_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR2_GPR_SHIFT (0U) -#define BGPR_BATT_GPR2_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR2_GPR_SHIFT) & BGPR_BATT_GPR2_GPR_MASK) -#define BGPR_BATT_GPR2_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR2_GPR_MASK) >> BGPR_BATT_GPR2_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR3 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR3_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR3_GPR_SHIFT (0U) -#define BGPR_BATT_GPR3_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR3_GPR_SHIFT) & BGPR_BATT_GPR3_GPR_MASK) -#define BGPR_BATT_GPR3_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR3_GPR_MASK) >> BGPR_BATT_GPR3_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR4 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR4_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR4_GPR_SHIFT (0U) -#define BGPR_BATT_GPR4_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR4_GPR_SHIFT) & BGPR_BATT_GPR4_GPR_MASK) -#define BGPR_BATT_GPR4_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR4_GPR_MASK) >> BGPR_BATT_GPR4_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR5 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR5_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR5_GPR_SHIFT (0U) -#define BGPR_BATT_GPR5_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR5_GPR_SHIFT) & BGPR_BATT_GPR5_GPR_MASK) -#define BGPR_BATT_GPR5_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR5_GPR_MASK) >> BGPR_BATT_GPR5_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR6 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR6_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR6_GPR_SHIFT (0U) -#define BGPR_BATT_GPR6_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR6_GPR_SHIFT) & BGPR_BATT_GPR6_GPR_MASK) -#define BGPR_BATT_GPR6_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR6_GPR_MASK) >> BGPR_BATT_GPR6_GPR_SHIFT) - -/* Bitfield definition for register: BATT_GPR7 */ -/* - * GPR (RW) - * - * Generic control - */ -#define BGPR_BATT_GPR7_GPR_MASK (0xFFFFFFFFUL) -#define BGPR_BATT_GPR7_GPR_SHIFT (0U) -#define BGPR_BATT_GPR7_GPR_SET(x) (((uint32_t)(x) << BGPR_BATT_GPR7_GPR_SHIFT) & BGPR_BATT_GPR7_GPR_MASK) -#define BGPR_BATT_GPR7_GPR_GET(x) (((uint32_t)(x) & BGPR_BATT_GPR7_GPR_MASK) >> BGPR_BATT_GPR7_GPR_SHIFT) +/* GPR register group index macro definition */ +#define BGPR_GPR_0 (0UL) +#define BGPR_GPR_1 (1UL) +#define BGPR_GPR_2 (2UL) +#define BGPR_GPR_3 (3UL) +#define BGPR_GPR_4 (4UL) +#define BGPR_GPR_5 (5UL) +#define BGPR_GPR_6 (6UL) +#define BGPR_GPR_7 (7UL) #endif /* HPM_BGPR_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c b/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c index 84a2e6a5..6baaf9c0 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.c @@ -58,6 +58,11 @@ static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t ins */ static uint32_t get_frequency_for_wdg(uint32_t instance); +/** + * @brief Get Clock frequency for PWDG + */ +static uint32_t get_frequency_for_pwdg(void); + /** * @brief Turn on/off the IP clock */ @@ -106,6 +111,9 @@ uint32_t clock_get_frequency(clock_name_t clock_name) case CLK_SRC_GROUP_WDG: clk_freq = get_frequency_for_wdg(node_or_instance); break; + case CLK_SRC_GROUP_PWDG: + clk_freq = get_frequency_for_pwdg(); + break; case CLK_SRC_GROUP_PMIC: clk_freq = FREQ_PRESET1_OSC0_CLK0; break; @@ -219,7 +227,11 @@ static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t ins } if (is_mux_valid) { - clk_freq = get_frequency_for_ip_in_common_group(node); + if (node == clock_node_ahb0) { + clk_freq = get_frequency_for_ip_in_common_group(clock_node_ahb0); + } else { + clk_freq = get_frequency_for_ip_in_common_group(node); + } } return clk_freq; } @@ -239,6 +251,18 @@ static uint32_t get_frequency_for_wdg(uint32_t instance) return freq_in_hz; } +static uint32_t get_frequency_for_pwdg(void) +{ + uint32_t freq_in_hz; + if (WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL) == 0) { + freq_in_hz = FREQ_PRESET1_OSC0_CLK0; + } else { + freq_in_hz = FREQ_32KHz; + } + + return freq_in_hz; +} + clk_src_t clock_get_source(clock_name_t clock_name) { uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; @@ -268,6 +292,10 @@ clk_src_t clock_get_source(clock_name_t clock_name) clk_src_index = (WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL) == 0); } break; + case CLK_SRC_GROUP_PWDG: + clk_src_group = CLK_SRC_GROUP_PWDG; + clk_src_index = (WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL) == 0); + break; case CLK_SRC_GROUP_PMIC: clk_src_group = CLK_SRC_GROUP_COMMON; clk_src_index = clock_source_osc0_clk0; @@ -323,7 +351,7 @@ hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) return status_clk_invalid; } - if ((src <= clk_adc_src_ahb0) || (src >= clk_adc_src_ana2)) { + if ((src < clk_adc_src_ahb0) || (src > clk_adc_src_ana2)) { return status_clk_src_invalid; } @@ -385,6 +413,15 @@ hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint } } break; + case CLK_SRC_GROUP_PWDG: + if (src == clk_pwdg_src_osc24m) { + HPM_PWDG->CTRL &= ~WDG_CTRL_CLKSEL_MASK; + } else if (src == clk_pwdg_src_osc32k) { + HPM_PWDG->CTRL |= WDG_CTRL_CLKSEL_MASK; + } else { + status = status_clk_src_invalid; + } + break; case CLK_SRC_GROUP_PMIC: status = status_clk_fixed; break; @@ -457,6 +494,13 @@ void clock_remove_from_group(clock_name_t clock_name, uint32_t group) } } +bool clock_check_in_group(clock_name_t clock_name, uint32_t group) +{ + uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); + + return sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); +} + void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) { if (cpu < 2U) { diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h index a9c5d2d5..5d5b86a1 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_clock_drv.h @@ -51,6 +51,7 @@ enum { #define CLK_SRC_GROUP_CPU0 (9U) #define CLK_SRC_GROUP_CPU1 (10U) #define CLK_SRC_GROUP_SRC (11U) +#define CLK_SRC_GROUP_PWDG (12U) #define CLK_SRC_GROUP_INVALID (15U) #define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp) << 4) | (index)) @@ -86,6 +87,9 @@ typedef enum _clock_sources { clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), + clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 0), + clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 1), + clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), } clk_src_t; @@ -164,7 +168,7 @@ typedef enum _clock_name { clock_watchdog2 = MAKE_CLOCK_NAME(sysctl_resource_wdg2, CLK_SRC_GROUP_WDG, 2), clock_watchdog3 = MAKE_CLOCK_NAME(sysctl_resource_wdg3, CLK_SRC_GROUP_WDG, 3), clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), + clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PWDG, 0), clock_eth0 = MAKE_CLOCK_NAME(sysctl_resource_eth0, CLK_SRC_GROUP_COMMON, clock_node_eth0), clock_eth1 = MAKE_CLOCK_NAME(sysctl_resource_eth1, CLK_SRC_GROUP_COMMON, clock_node_eth1), clock_ptp0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ptp0), @@ -311,6 +315,13 @@ extern "C" */ void clock_remove_from_group(clock_name_t clock_name, uint32_t group); + /** + * @brief Check IP in specified group + * @param[in] clock_name IP clock name + * @return true if in group, false if not in group + */ + bool clock_check_in_group(clock_name_t clock_name, uint32_t group); + /** * @brief Disconnect the clock group from specified CPU * @param[in] group clock group index, value value is 0/1/2/3 diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h index 952f01f0..a2142870 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h @@ -14,7 +14,7 @@ */ /* @brief gpiom control module */ -typedef enum hpm6700_gpiom_gpio { +typedef enum gpiom_gpio { gpiom_soc_gpio0 = 0, gpiom_soc_gpio1 = 1, gpiom_core0_fast = 2, diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h index 8a8b0606..2f848860 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_interrupt.h @@ -7,8 +7,8 @@ #ifndef HPM_INTERRUPT_H #define HPM_INTERRUPT_H -#include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_csr_drv.h" #include "hpm_plic_drv.h" /** @@ -574,25 +574,17 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) csrr s3, mstatus \n");\ SAVE_FPU_STATE(); \ SAVE_DSP_CONTEXT(); \ - __asm volatile ("\n\ - c.li a5, 8\n\ - csrs mstatus, a5\n"); \ + __asm volatile("csrsi mstatus, 8"); \ } /* * @brief Complete IRQ Handling */ #define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("\n\ - lui a5, 0x1\n\ - addi a5, a5, -2048\n\ - csrc mie, a5\n"); \ - __asm volatile("\n\ - lui a4, 0xe4200\n");\ + __asm volatile("csrci mstatus, 8"); \ + __asm volatile("lui a4, 0xe4200"); \ __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)\n\ - fence io, io\n"); \ - __asm volatile("csrs mie, a5"); \ + __asm volatile("sw a3, 4(a4)"); \ } /* @@ -611,7 +603,6 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) RESTORE_DSP_CONTEXT(); \ } - /* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ #define NESTED_IRQ_ENTER() \ SAVE_CSR(CSR_MEPC) \ @@ -629,18 +620,6 @@ ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) RESTORE_FCSR() \ RESTORE_UCODE() -/* - * @brief Nested IRQ exit macro : Restore CSRs - * @param[in] irq Target interrupt number - */ -#define NESTED_VPLIC_COMPLETE_INTERRUPT(irq) \ -do { \ - clear_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq); \ - __asm volatile("fence io, io"); \ - set_csr(CSR_MIE, CSR_MIP_MEIP_MASK); \ -} while (0) - #ifdef __cplusplus #define HPM_EXTERN_C extern "C" #else @@ -667,6 +646,7 @@ void ISR_NAME_M(irq_num)(void) \ COMPLETE_IRQ_HANDLING_M(irq_num);\ EXIT_NESTED_IRQ_HANDLING_M();\ RESTORE_CALLER_CONTEXT();\ + __asm volatile("fence io, io");\ __asm volatile("mret\n");\ } #else diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h index 480e7639..7b848c91 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_l1c_drv.h @@ -7,8 +7,8 @@ #ifndef _HPM_L1_CACHE_H #define _HPM_L1_CACHE_H -#include "riscv/riscv_core.h" #include "hpm_common.h" +#include "hpm_csr_drv.h" #include "hpm_soc.h" /** diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h index fa899118..1867a0fb 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h @@ -229,12 +229,11 @@ static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) * * @param[in] ptr base address * @param[in] limit current limit at low power mode - * @param[in] over_limit set to true means current is greater than limit + * @param[in] over_limit unused parameter, will be discarded */ static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) { - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) - | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit) | PCFG_DCDC_PROT_OVERLOAD_LP_SET(over_limit); + ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_ILIMIT_LP_MASK) | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); } /** @@ -580,6 +579,31 @@ static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; } +/** + * @brief dcdc switch to dcm mode + * + * @param[in] ptr base address + */ +static inline void pcfg_dcdc_switch_to_dcm_mode(PCFG_Type *ptr) +{ + const uint8_t pcfc_dcdc_min_duty_cycle[] = { + 0x6E, 0x6E, 0x70, 0x70, 0x70, 0x70, 0x72, 0x72, + 0x72, 0x72, 0x74, 0x74, 0x74, 0x74, 0x76, 0x76, + 0x76, 0x78, 0x78, 0x78, 0x78, 0x7A, 0x7A, 0x7A, + 0x7A, 0x7C, 0x7C, 0x7C, 0x7E, 0x7E, 0x7E, 0x7E + }; + uint16_t voltage; + + ptr->DCDC_MODE |= 0x77000u; + ptr->DCDC_ADVMODE = (ptr->DCDC_ADVMODE & ~0x73F0067u) | 0x4120067u; + ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_SHORT_CURRENT_MASK; + ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_SHORT_MASK; + ptr->DCDC_MISC = 0x100000u; + voltage = PCFG_DCDC_MODE_VOLT_GET(ptr->DCDC_MODE); + voltage = (voltage - 600) / 25; + ptr->DCDC_ADVPARAM = (ptr->DCDC_ADVPARAM & ~PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) | PCFG_DCDC_ADVPARAM_MIN_DUT_SET(pcfc_dcdc_min_duty_cycle[voltage]); +} + /** * @brief config irc24m track * diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h index e53036a5..a22f579a 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h @@ -240,7 +240,7 @@ typedef struct { #define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) /* - * OVERLOAD_LP (RW) + * OVERLOAD_LP (RO) * * over current in low power mode * 0: current is below setting @@ -248,7 +248,6 @@ typedef struct { */ #define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) #define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDC_PROT_OVERLOAD_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) #define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) /* diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h index 52ba031d..ab90cd08 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ppor_drv.h @@ -11,15 +11,7 @@ typedef enum { ppor_reset_brownout = 1 << 0, - ppor_reset_temperature = 1 << 1, - ppor_reset_pin = 1 << 2, ppor_reset_debug = 1 << 4, - ppor_reset_security_violation = 1 << 5, - ppor_reset_jtag = 1 << 6, - ppor_reset_cpu0_lockup = 1 << 8, - ppor_reset_cpu1_lockup = 1 << 9, - ppor_reset_cpu0_request = 1 << 10, - ppor_reset_cpu1_request = 1 << 11, ppor_reset_wdog0 = 1 << 16, ppor_reset_wdog1 = 1 << 17, ppor_reset_wdog2 = 1 << 18, diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml index 319a23a2..5a0fcaf8 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ses_reg.xml @@ -4856,6 +4856,111 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4916,6 +5021,106 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -4976,6 +5181,106 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -5036,6 +5341,106 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -5346,8 +5751,8 @@ - - + + @@ -5357,8 +5762,8 @@ - - + + @@ -5368,8 +5773,8 @@ - - + + @@ -5379,8 +5784,8 @@ - - + + @@ -5390,8 +5795,8 @@ - - + + @@ -5401,8 +5806,8 @@ - - + + @@ -5412,8 +5817,8 @@ - - + + @@ -5423,8 +5828,8 @@ - - + + @@ -5434,8 +5839,8 @@ - - + + @@ -5445,8 +5850,8 @@ - - + + @@ -5456,8 +5861,8 @@ - - + + @@ -5467,8 +5872,8 @@ - - + + @@ -5478,8 +5883,8 @@ - - + + @@ -5489,8 +5894,8 @@ - - + + @@ -5500,8 +5905,8 @@ - - + + @@ -5511,8 +5916,8 @@ - - + + @@ -5522,8 +5927,8 @@ - - + + @@ -5533,8 +5938,8 @@ - - + + @@ -5544,8 +5949,8 @@ - - + + @@ -6010,8 +6415,8 @@ - - + + @@ -6021,8 +6426,8 @@ - - + + @@ -6032,8 +6437,8 @@ - - + + @@ -6043,8 +6448,8 @@ - - + + @@ -6054,8 +6459,8 @@ - - + + @@ -6065,8 +6470,8 @@ - - + + @@ -6076,8 +6481,8 @@ - - + + @@ -6087,8 +6492,8 @@ - - + + @@ -6098,8 +6503,8 @@ - - + + @@ -6109,8 +6514,8 @@ - - + + @@ -6120,8 +6525,8 @@ - - + + @@ -6131,8 +6536,8 @@ - - + + @@ -6142,8 +6547,8 @@ - - + + @@ -6153,8 +6558,8 @@ - - + + @@ -6164,8 +6569,8 @@ - - + + @@ -6175,8 +6580,8 @@ - - + + @@ -6186,8 +6591,8 @@ - - + + @@ -6197,8 +6602,8 @@ - - + + @@ -6208,8 +6613,8 @@ - - + + @@ -6674,8 +7079,8 @@ - - + + @@ -6685,8 +7090,8 @@ - - + + @@ -6696,8 +7101,8 @@ - - + + @@ -6707,8 +7112,8 @@ - - + + @@ -6718,8 +7123,8 @@ - - + + @@ -6729,8 +7134,8 @@ - - + + @@ -6740,8 +7145,8 @@ - - + + @@ -6751,8 +7156,8 @@ - - + + @@ -6762,8 +7167,8 @@ - - + + @@ -6773,8 +7178,8 @@ - - + + @@ -6784,8 +7189,8 @@ - - + + @@ -6795,8 +7200,8 @@ - - + + @@ -6806,8 +7211,8 @@ - - + + @@ -6817,8 +7222,8 @@ - - + + @@ -6828,8 +7233,8 @@ - - + + @@ -6839,8 +7244,8 @@ - - + + @@ -6850,8 +7255,8 @@ - - + + @@ -6861,8 +7266,8 @@ - - + + @@ -6872,8 +7277,8 @@ - - + + @@ -7216,9 +7621,6 @@ - - - @@ -7692,7 +8094,6 @@ - @@ -7785,7 +8186,6 @@ - @@ -7878,7 +8278,6 @@ - @@ -7971,7 +8370,6 @@ - @@ -8064,7 +8462,6 @@ - @@ -8128,10 +8525,12 @@ + + + - @@ -8195,10 +8594,12 @@ + + + - @@ -8262,10 +8663,12 @@ + + + - @@ -8329,10 +8732,12 @@ + + + - @@ -8396,10 +8801,12 @@ + + + - @@ -8463,10 +8870,12 @@ + + + - @@ -8530,10 +8939,12 @@ + + + - @@ -8597,10 +9008,12 @@ + + + - @@ -8664,10 +9077,12 @@ + + + - @@ -8731,10 +9146,12 @@ + + + - @@ -8798,10 +9215,12 @@ + + + - @@ -8865,10 +9284,12 @@ + + + - @@ -8932,10 +9353,12 @@ + + + - @@ -8999,10 +9422,12 @@ + + + - @@ -9066,10 +9491,12 @@ + + + - @@ -9133,10 +9560,12 @@ + + + - @@ -9200,6 +9629,9 @@ + + + @@ -10335,20 +10767,16 @@ - - - - @@ -10361,7 +10789,6 @@ - @@ -10381,20 +10808,16 @@ - - - - @@ -10407,7 +10830,6 @@ - @@ -10427,20 +10849,16 @@ - - - - @@ -10453,7 +10871,6 @@ - @@ -10473,20 +10890,16 @@ - - - - @@ -10499,7 +10912,6 @@ - @@ -10522,7 +10934,6 @@ - @@ -10568,7 +10979,6 @@ - @@ -10631,6 +11041,12 @@ + + + + + + @@ -11394,48 +11810,33 @@ - - - - - - - - - - - - - - - @@ -11541,7 +11942,6 @@ - @@ -11569,17 +11969,14 @@ - - - @@ -11606,7 +12003,6 @@ - @@ -11626,10 +12022,7 @@ - - - @@ -11659,7 +12052,6 @@ - @@ -11687,17 +12079,14 @@ - - - @@ -11724,7 +12113,6 @@ - @@ -11744,10 +12132,7 @@ - - - @@ -11777,7 +12162,6 @@ - @@ -11805,17 +12189,14 @@ - - - @@ -11842,7 +12223,6 @@ - @@ -11862,10 +12242,7 @@ - - - @@ -11895,7 +12272,6 @@ - @@ -11923,17 +12299,14 @@ - - - @@ -11960,7 +12333,6 @@ - @@ -11980,10 +12352,7 @@ - - - @@ -12118,12 +12487,10 @@ - - @@ -12276,196 +12643,124 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -12569,7 +12864,6 @@ - @@ -12646,7 +12940,6 @@ - @@ -12745,145 +13038,121 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -12893,12 +13162,10 @@ - - @@ -13051,196 +13318,124 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -13344,7 +13539,6 @@ - @@ -13421,7 +13615,6 @@ - @@ -13520,145 +13713,121 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -13668,12 +13837,10 @@ - - @@ -13826,196 +13993,124 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -14119,7 +14214,6 @@ - @@ -14196,7 +14290,6 @@ - @@ -14295,145 +14388,121 @@ - - - - - - - - - - - - - - - - - - - - - - - - @@ -14443,12 +14512,10 @@ - - @@ -14601,196 +14668,124 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -14894,7 +14889,6 @@ - @@ -14971,7 +14965,6 @@ - @@ -15070,160 +15063,131 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -15231,7 +15195,6 @@ - @@ -15239,10 +15202,6 @@ - - - - @@ -15252,10 +15211,6 @@ - - - - @@ -15265,10 +15220,6 @@ - - - - @@ -15278,10 +15229,6 @@ - - - - @@ -15291,10 +15238,6 @@ - - - - @@ -15303,8 +15246,6 @@ - - @@ -15321,8 +15262,6 @@ - - @@ -15339,8 +15278,6 @@ - - @@ -15357,8 +15294,6 @@ - - @@ -15393,16 +15328,11 @@ - - - - - @@ -15410,7 +15340,6 @@ - @@ -15418,10 +15347,6 @@ - - - - @@ -15431,10 +15356,6 @@ - - - - @@ -15444,10 +15365,6 @@ - - - - @@ -15457,10 +15374,6 @@ - - - - @@ -15470,10 +15383,6 @@ - - - - @@ -15482,8 +15391,6 @@ - - @@ -15500,8 +15407,6 @@ - - @@ -15518,8 +15423,6 @@ - - @@ -15536,8 +15439,6 @@ - - @@ -15572,16 +15473,11 @@ - - - - - @@ -15589,7 +15485,6 @@ - @@ -15597,10 +15492,6 @@ - - - - @@ -15610,10 +15501,6 @@ - - - - @@ -15623,10 +15510,6 @@ - - - - @@ -15636,10 +15519,6 @@ - - - - @@ -15649,10 +15528,6 @@ - - - - @@ -15661,8 +15536,6 @@ - - @@ -15679,8 +15552,6 @@ - - @@ -15697,8 +15568,6 @@ - - @@ -15715,8 +15584,6 @@ - - @@ -15751,16 +15618,11 @@ - - - - - @@ -15768,7 +15630,6 @@ - @@ -15776,10 +15637,6 @@ - - - - @@ -15789,10 +15646,6 @@ - - - - @@ -15802,10 +15655,6 @@ - - - - @@ -15815,10 +15664,6 @@ - - - - @@ -15828,10 +15673,6 @@ - - - - @@ -15840,8 +15681,6 @@ - - @@ -15858,8 +15697,6 @@ - - @@ -15876,8 +15713,6 @@ - - @@ -15894,8 +15729,6 @@ - - @@ -15942,7 +15775,6 @@ - @@ -16099,7 +15931,6 @@ - @@ -16256,7 +16087,6 @@ - @@ -16413,7 +16243,6 @@ - @@ -18683,25 +18512,17 @@ - - - - - - - - @@ -18718,20 +18539,16 @@ - - - - @@ -18741,14 +18558,11 @@ - - - @@ -18761,7 +18575,6 @@ - @@ -18770,27 +18583,20 @@ - - - - - - - @@ -18800,14 +18606,11 @@ - - - @@ -18820,7 +18623,6 @@ - @@ -18829,27 +18631,20 @@ - - - - - - - @@ -18859,14 +18654,11 @@ - - - @@ -18879,7 +18671,6 @@ - @@ -18888,27 +18679,20 @@ - - - - - - - @@ -18918,14 +18702,11 @@ - - - @@ -18938,7 +18719,6 @@ - @@ -18947,27 +18727,20 @@ - - - - - - - @@ -18977,14 +18750,11 @@ - - - @@ -18997,7 +18767,6 @@ - @@ -19006,27 +18775,20 @@ - - - - - - - @@ -19036,14 +18798,11 @@ - - - @@ -19056,7 +18815,6 @@ - @@ -19065,27 +18823,20 @@ - - - - - - - @@ -19095,14 +18846,11 @@ - - - @@ -19115,7 +18863,6 @@ - @@ -19124,27 +18871,20 @@ - - - - - - - @@ -19154,14 +18894,11 @@ - - - @@ -19174,7 +18911,6 @@ - @@ -19183,32 +18919,25 @@ - - - - - - - @@ -19220,59 +18949,44 @@ - - - - - - - - - - - - - - - @@ -19281,1085 +18995,812 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -20371,59 +19812,44 @@ - - - - - - - - - - - - - - - @@ -20432,1112 +19858,833 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -21670,7 +20817,6 @@ - @@ -21694,7 +20840,6 @@ - @@ -21724,7 +20869,6 @@ - @@ -21754,14 +20898,11 @@ - - - @@ -21772,7 +20913,6 @@ - @@ -21785,11 +20925,9 @@ - - @@ -21804,91 +20942,70 @@ - - - - - - - - - - - - - - - - - - - - - @@ -22321,54 +21438,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -23067,54 +22136,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -23390,7 +22411,6 @@ - @@ -23433,7 +22453,6 @@ - @@ -23476,7 +22495,6 @@ - @@ -23519,7 +22537,6 @@ - @@ -23561,7 +22578,6 @@ - @@ -23580,7 +22596,6 @@ - @@ -23605,7 +22620,6 @@ - @@ -23648,7 +22662,6 @@ - @@ -23691,7 +22704,6 @@ - @@ -23734,7 +22746,6 @@ - @@ -23776,7 +22787,6 @@ - @@ -23795,7 +22805,6 @@ - @@ -23820,7 +22829,6 @@ - @@ -23863,7 +22871,6 @@ - @@ -23906,7 +22913,6 @@ - @@ -23949,7 +22955,6 @@ - @@ -23991,7 +22996,6 @@ - @@ -24010,7 +23014,6 @@ - @@ -24035,7 +23038,6 @@ - @@ -24078,7 +23080,6 @@ - @@ -24121,7 +23122,6 @@ - @@ -24164,7 +23164,6 @@ - @@ -24206,7 +23205,6 @@ - @@ -24225,7 +23223,6 @@ - @@ -24250,7 +23247,6 @@ - @@ -24293,7 +23289,6 @@ - @@ -24336,7 +23331,6 @@ - @@ -24379,7 +23373,6 @@ - @@ -24421,7 +23414,6 @@ - @@ -24440,7 +23432,6 @@ - @@ -24465,7 +23456,6 @@ - @@ -24508,7 +23498,6 @@ - @@ -24551,7 +23540,6 @@ - @@ -24594,7 +23582,6 @@ - @@ -24636,7 +23623,6 @@ - @@ -24655,7 +23641,6 @@ - @@ -24680,7 +23665,6 @@ - @@ -24723,7 +23707,6 @@ - @@ -24766,7 +23749,6 @@ - @@ -24809,7 +23791,6 @@ - @@ -24851,7 +23832,6 @@ - @@ -24870,7 +23850,6 @@ - @@ -24895,7 +23874,6 @@ - @@ -24938,7 +23916,6 @@ - @@ -24981,7 +23958,6 @@ - @@ -25024,7 +24000,6 @@ - @@ -25066,7 +24041,6 @@ - @@ -25085,7 +24059,6 @@ - @@ -25110,7 +24083,6 @@ - @@ -25153,7 +24125,6 @@ - @@ -25196,7 +24167,6 @@ - @@ -25239,7 +24209,6 @@ - @@ -25281,7 +24250,6 @@ - @@ -25300,7 +24268,6 @@ - @@ -25325,7 +24292,6 @@ - @@ -25368,7 +24334,6 @@ - @@ -25411,7 +24376,6 @@ - @@ -25454,7 +24418,6 @@ - @@ -25496,7 +24459,6 @@ - @@ -25515,7 +24477,6 @@ - @@ -25540,7 +24501,6 @@ - @@ -25583,7 +24543,6 @@ - @@ -25626,7 +24585,6 @@ - @@ -25669,7 +24627,6 @@ - @@ -25711,7 +24668,6 @@ - @@ -25730,7 +24686,6 @@ - @@ -27212,7 +26167,6 @@ - @@ -27255,11 +26209,9 @@ - - @@ -27272,7 +26224,6 @@ - @@ -27290,15 +26241,12 @@ - - - @@ -27307,15 +26255,12 @@ - - - @@ -27324,17 +26269,14 @@ - - - @@ -27347,7 +26289,6 @@ - @@ -27365,15 +26306,12 @@ - - - @@ -27382,15 +26320,12 @@ - - - @@ -27399,17 +26334,14 @@ - - - @@ -27422,7 +26354,6 @@ - @@ -27440,15 +26371,12 @@ - - - @@ -27457,15 +26385,12 @@ - - - @@ -27474,17 +26399,14 @@ - - - @@ -27497,7 +26419,6 @@ - @@ -27515,15 +26436,12 @@ - - - @@ -27532,15 +26450,12 @@ - - - @@ -27549,7 +26464,6 @@ - @@ -27559,13 +26473,11 @@ - - @@ -27573,36 +26485,27 @@ - - - - - - - - - @@ -27611,9 +26514,7 @@ - - @@ -27663,14 +26564,12 @@ - - @@ -40220,29 +39119,29 @@ - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + @@ -40537,4 +39436,4 @@ - \ No newline at end of file + diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_ses_riscv_cpu_regs.xml b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ses_riscv_cpu_regs.xml index de6e8964..9e30fbc7 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_ses_riscv_cpu_regs.xml +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_ses_riscv_cpu_regs.xml @@ -767,4 +767,4 @@ - \ No newline at end of file + diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h index e72c844a..3f9a5179 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc.h @@ -849,4 +849,4 @@ #include "hpm_iomux.h" #include "hpm_pmic_iomux.h" #include "hpm_batt_iomux.h" -#endif /* HPM_SOC_H */ \ No newline at end of file +#endif /* HPM_SOC_H */ diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h index 11da5f9a..7b9255aa 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_soc_feature.h @@ -63,7 +63,6 @@ */ #define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) #define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_BUS_NUM (1U) #define DMA_SOC_CHANNEL_NUM (8U) #define DMA_SOC_MAX_COUNT (2U) #define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) @@ -122,6 +121,7 @@ /* * ADC Section */ +#define ADC_SOC_IP_VERSION (0U) #define ADC_SOC_SEQ_MAX_LEN (16U) #define ADC_SOC_MAX_TRIG_CH_LEN (4U) #define ADC_SOC_MAX_TRIG_CH_NUM (11U) diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c b/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c index 197698b3..11f3824e 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c @@ -228,6 +228,47 @@ hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, return status_success; } +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, + uint8_t group, + sysctl_resource_t linkable_resource) +{ + uint32_t index, offset; + bool enable; + + index = (linkable_resource - sysctl_resource_linkable_start) / 32; + offset = (linkable_resource - sysctl_resource_linkable_start) % 32; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + case SYSCTL_RESOURCE_GROUP1: + enable = ((ptr->GROUP1[index].VALUE & (1UL << offset)) != 0) ? true : false; + break; + default: + enable = false; + break; + } + + return enable; +} + +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) +{ + uint32_t value; + switch (group) { + case SYSCTL_RESOURCE_GROUP0: + value = ptr->GROUP0[index].VALUE; + break; + case SYSCTL_RESOURCE_GROUP1: + value = ptr->GROUP1[index].VALUE; + break; + default: + value = 0; + break; + } + return value; +} + hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) { return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); diff --git a/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h b/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h index fb077923..6925e633 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h @@ -748,6 +748,19 @@ static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, SYSCTL_RESOURCE_MODE_SET(mode); } +/** + * @brief Get target mode + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] resource target resource index + * @return target resource mode + */ +static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, + sysctl_resource_t resource) +{ + return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); +} + /** * @brief Disable resource retention when specific CPU enters stop mode * @@ -1523,6 +1536,27 @@ hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); + +/** + * @brief Check group resource enable status + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be checked + * @param[in] resource target resource to be checked from group + * @return enable true if resource enable, false if resource disable + */ +bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t linkable_resource); + +/** + * @brief Get group resource value + * + * @param[in] ptr SYSCTL_Type base address + * @param[in] group target group to be getted + * @param[in] index target group index + * @return group index value + */ +uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); + /** * @brief Add resource to CPU0 * @@ -1579,7 +1613,7 @@ void sysctl_monitor_init(SYSCTL_Type *ptr, monitor_config_t *config); /** - * @brief Save data to GPU0 GPR starting from given index + * @brief Save data to CPU0 GPR starting from given index * * @param[in] ptr SYSCTL_Type base address * @param[in] start Starting GPR index @@ -1595,7 +1629,7 @@ hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, bool lock); /** - * @brief Get data saved from GPU0 GPR starting from given index + * @brief Get data saved from CPU0 GPR starting from given index * * @param[in] ptr SYSCTL_Type base address * @param[in] start Starting GPR index diff --git a/common/libraries/hpm_sdk/soc/HPM6750/soc_modules.list b/common/libraries/hpm_sdk/soc/HPM6750/soc_modules.list index ac5d3ba0..b11b3e30 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/soc_modules.list +++ b/common/libraries/hpm_sdk/soc/HPM6750/soc_modules.list @@ -35,4 +35,5 @@ CONFIG_HAS_HPMSDK_ADC16=y CONFIG_HAS_HPMSDK_PCFG=y CONFIG_HAS_HPMSDK_PTPC=y CONFIG_HAS_HPMSDK_MCHTMR=y +CONFIG_HAS_HPMSDK_QEI=y diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld index 4c07e4ca..b628bda5 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash.ld @@ -27,7 +27,17 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text : { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(.text) *(.text*) @@ -46,36 +56,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - .vectors ORIGIN(ILM) : AT(etext) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext + __vector_ram_end__ - __vector_ram_start__) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -83,8 +82,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -128,7 +125,8 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -141,11 +139,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -153,13 +149,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __vector_ram_end__ - __vector_ram_start__ + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -213,5 +233,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld index 6c280da2..2b235195 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_uf2.ld @@ -29,7 +29,17 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { . = ALIGN(8); *(.text) *(.text*) @@ -48,37 +58,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -86,8 +84,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -131,7 +127,8 @@ SECTIONS PROVIDE (edata = .); } > SDRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -144,11 +141,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -156,13 +151,37 @@ SECTIONS __bss_end__ = .; } > SDRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > SDRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > SDRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > SDRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -215,4 +234,7 @@ SECTIONS __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld index 8e58d241..f4c0718a 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_sdram_xip.ld @@ -46,7 +46,17 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(EXCLUDE_FILE (nx*.o*) .text) *(EXCLUDE_FILE (nx*.o*) .text*) @@ -65,37 +75,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -103,8 +101,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -142,13 +138,15 @@ SECTIONS KEEP(*(SORT(.dtors.*))) KEEP(*(.dtors)) . = ALIGN(8); + __data_end__ = .; PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); } > SDRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -162,17 +160,14 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > ILM - __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -180,13 +175,37 @@ SECTIONS __bss_end__ = .; } > SDRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > SDRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > SDRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > SDRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -239,4 +258,7 @@ SECTIONS __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld index ea8c4510..663e0684 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_uf2.ld @@ -28,7 +28,17 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__): { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)): { . = ALIGN(8); *(.text) *(.text*) @@ -47,37 +57,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -85,8 +83,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -130,7 +126,8 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -143,11 +140,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -155,13 +150,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -215,5 +234,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld index 13c2c94f..03c2a14d 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/flash_xip.ld @@ -46,7 +46,17 @@ SECTIONS KEEP(*(.start)) } > XPI0 - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { . = ALIGN(8); *(EXCLUDE_FILE (nx*.o*) .text) *(EXCLUDE_FILE (nx*.o*) .text*) @@ -65,37 +75,25 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) - . = ALIGN(8); - } > XPI0 - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - /* section information for usbh class */ - .usbh_class_info : { - . = ALIGN(4); + /* section information for usbh class */ + . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; . = ALIGN(8); } > XPI0 + .rel : { + KEEP(*(.rel*)) + } > XPI0 + PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -103,8 +101,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -148,7 +144,8 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -162,17 +159,14 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > ILM - __fw_size__ = __ramfunc_end__ - __ramfunc_start__ + __data_end__ - __data_start__ + etext - __app_load_addr__; .bss (NOLOAD) : { . = ALIGN(8); __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -180,13 +174,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -240,5 +258,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(XPI0), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld index a32af928..2416281a 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld @@ -69,7 +69,8 @@ SECTIONS PROVIDE (etext = .); } > ILM - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -77,8 +78,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -123,7 +122,8 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -136,11 +136,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -148,13 +146,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -208,5 +230,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(ILM), "****** FAILED! ILM has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld index 78a320df..0ecee075 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/ram_core1.ld @@ -67,7 +67,8 @@ SECTIONS PROVIDE (etext = .); } > ILM - .data : AT(etext) { + __data_load_addr__ = etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -75,8 +76,6 @@ SECTIONS *(.data*) *(.sdata) *(.sdata*) - *(.tdata) - *(.tdata*) KEEP(*(.jcr)) KEEP(*(.dynamic)) @@ -121,7 +120,8 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __data_start__) { + __fast_load_addr__ = etext + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -134,11 +134,9 @@ SECTIONS __bss_start__ = .; *(.bss) *(.bss*) - *(.tbss*) *(.sbss*) *(.scommon) *(.scommon*) - *(.tcommon*) *(.dynsbss*) *(COMMON) . = ALIGN(8); @@ -146,13 +144,37 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + .tbss (NOLOAD) : { + . = ALIGN(8); + PROVIDE(__tbss_start__ = .); + __thread_pointer$ = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + *(.tcommon) + . = ALIGN(8); + PROVIDE(__tbss_end__ = .); + } > AXI_SRAM + + __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + PROVIDE(__tdata_start__ = .); + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + PROVIDE(__tdata_end__ = .); + } > AXI_SRAM + .framebuffer (NOLOAD) : { . = ALIGN(8); KEEP(*(.framebuffer)) . = ALIGN(8); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -198,5 +220,6 @@ SECTIONS __share_mem_start__ = ORIGIN(SHARE_RAM); __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - ASSERT((STACK_SIZE + HEAP_SIZE) <= 256K, "stack and heap total size larger than 256k") + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + ASSERT(__fw_size__ <= LENGTH(ILM), "****** FAILED! ILM has not enough space! ******") } diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S index cd45d56f..c0b54780 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S @@ -16,6 +16,7 @@ _start: .option push .option norelax la gp, __global_pointer$ + la tp, __thread_pointer$ .option pop /* reset mstatus to 0*/ @@ -30,6 +31,12 @@ _start: fscsr zero #endif + /* Enable LMM1 clock */ + la t0, 0xF4000800 + lw t1, 0(t0) + ori t1, t1, 0x80 + sw t1, 0(t0) + #ifdef INIT_EXT_RAM_FOR_DATA la t0, _stack_safe mv sp, t0 diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c index cf87e229..73174803 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/reset.c @@ -30,6 +30,13 @@ __attribute__((weak)) void _clean_up(void) __attribute__((weak)) void c_startup(void) { uint32_t i, size; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + extern uint8_t __data_load_addr__[], __fast_load_addr__[], __noncacheable_init_load_addr__[]; + #if defined(FLASH_XIP) || defined(FLASH_UF2) extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; size = __vector_ram_end__ - __vector_ram_start__; @@ -38,13 +45,6 @@ __attribute__((weak)) void c_startup(void) } #endif - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - /* bss section */ size = __bss_end__ - __bss_start__; for (i = 0; i < size; i++) { @@ -60,19 +60,19 @@ __attribute__((weak)) void c_startup(void) /* data section LMA: etext */ size = __data_end__ - __data_start__; for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + i); + *(__data_start__ + i) = *(__data_load_addr__ + i); } /* ramfunc section LMA: etext + data length */ size = __ramfunc_end__ - __ramfunc_start__; for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i); + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); } - /* noncacheable init section LMA: etext + data length + ramfunc legnth */ + /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ size = __noncacheable_init_end__ - __noncacheable_init_start__; for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } } diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf index 863c117d..7fec74dc 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf @@ -16,16 +16,14 @@ define region SHARE_RAM = [from 0x0117C000 size 16k]; define region AHB_SRAM = [from 0xF0300000 size 32k]; define region APB_SRAM = [from 0xF40F0000 size 8k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; - /* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; +define block vectors with fixed order { section .isr_vector, section .vector_table }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -34,16 +32,16 @@ define block framebuffer with alignment = 8 { section .framebuffer }; /* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; /* Initialization */ do not initialize { section .noncacheable }; @@ -57,8 +55,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors }; initialize by copy { block cherryusb_usbh_class_info }; diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf index d7ad5c99..4e65fc35 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf @@ -19,31 +19,28 @@ define region SDRAM = [from 0x40000000 size _extram_size - 4M]; define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; /* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; +define block vectors with fixed order { section .isr_vector, section .vector_table }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; define block framebuffer with alignment = 8 { section .framebuffer }; - /* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; - -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; /* Initialization */ do not initialize { section .noncacheable }; @@ -57,8 +54,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors }; initialize by copy { block cherryusb_usbh_class_info }; diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf index c9987c17..8ef19292 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf @@ -20,13 +20,13 @@ define region SDRAM = [from 0x40000000 size _extram_size - 4M]; define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; /* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; +define block vectors with fixed order { section .isr_vector, section .vector_table }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -42,10 +42,10 @@ define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_a define exported symbol __boot_header_length__ = size of block boot_header; define exported symbol __fw_size__ = 0x1000; -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; @@ -65,8 +65,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors }; initialize by copy { block cherryusb_usbh_class_info }; diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf index e6f41480..950af422 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf @@ -17,16 +17,14 @@ define region SHARE_RAM = [from 0x0117C000 size 16k]; define region AHB_SRAM = [from 0xF0300000 size 32k]; define region APB_SRAM = [from 0xF40F0000 size 8k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; - /* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; +define block vectors with fixed order { section .isr_vector, section .vector_table }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -34,16 +32,16 @@ define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_cl define block framebuffer with alignment = 8 { section .framebuffer }; /* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; /* Initialization */ do not initialize { section .noncacheable }; @@ -57,8 +55,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors }; initialize by copy { block cherryusb_usbh_class_info }; diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf index 43b0b01e..e5995c65 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf @@ -18,16 +18,14 @@ define region SHARE_RAM = [from 0x0117C000 size 16k]; define region AHB_SRAM = [from 0xF0300000 size 32k]; define region APB_SRAM = [from 0xF40F0000 size 8k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; - /* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; +define block vectors with fixed order { section .isr_vector, section .vector_table }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; @@ -43,16 +41,16 @@ define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_a define exported symbol __boot_header_length__ = size of block boot_header; define exported symbol __fw_size__ = 0x1000; -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; /* Initialization */ do not initialize { section .noncacheable }; @@ -66,8 +64,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors }; initialize by copy { block cherryusb_usbh_class_info }; diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf index 9d7403a2..cb5b538d 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf @@ -14,16 +14,14 @@ define region SHARE_RAM = [from 0x0117C000 size 16k]; define region AHB_SRAM = [from 0xF0300000 size 32k]; define region APB_SRAM = [from 0xF40F0000 size 8k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; - /* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; +define block vectors with fixed order { section .isr_vector, section .vector_table }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block cherryusb_usbh_class_info { section .usbh_class_info }; define block framebuffer { section .framebuffer }; @@ -33,8 +31,8 @@ define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ r /* Symbols */ define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack = end of block stack + 1; define exported symbol _stack_safe = end of block stack + 1; @@ -53,8 +51,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. /* Placement */ place at start of ILM { symbol _start }; diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf index efabc22a..4a0438f2 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf @@ -13,16 +13,14 @@ define region NONCACHEABLE_RAM = [from 0x01140000 size 64k]; /* AXI SRAM1 */ define region AXI_SRAM = [from 0x01150000 size 176k]; define region SHARE_RAM = [from 0x0117C000 size 16k]; -assert (__STACKSIZE__ + __HEAPSIZE__) <= 256k with error "stack and heap total size larger than 256k"; - /* Blocks */ -define block vectors { section .isr_vector, section .vector_table }; +define block vectors with fixed order { section .isr_vector, section .vector_table }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; define block eh_frame { section .eh_frame, section .eh_frame.* }; define block tbss { section .tbss, section .tbss.* }; define block tdata { section .tdata, section .tdata.* }; -define block tls { block tbss, block tdata }; +define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; define block cherryusb_usbh_class_info { section .usbh_class_info }; define block framebuffer { section .framebuffer }; @@ -32,8 +30,8 @@ define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ r /* Symbols */ define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; +define exported symbol __share_mem_start__ = start of region SHARE_RAM; +define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack = end of block stack + 1; define exported symbol _stack_safe = end of block stack + 1; @@ -51,8 +49,8 @@ initialize by copy with packing=none { section .data, section .data.*, se initialize by copy with packing=auto { section .sdata, section .sdata.* }; initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. /* Placement */ place at start of ILM { symbol _start }; diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s index 3d9fa00d..95675dfe 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s @@ -185,6 +185,12 @@ START_FUNC _start fscsr zero #endif + /* Enable LMM1 clock */ + la t0, 0xF4000800 + lw t1, 0(t0) + ori t1, t1, 0x80 + sw t1, 0(t0) + #ifdef INIT_EXT_RAM_FOR_DATA la t0, _stack_safe mv sp, t0 diff --git a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h index 262d108b..dbb51edf 100644 --- a/common/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h +++ b/common/libraries/hpm_sdk/soc/HPM6750/toolchains/vectors.h @@ -151,3 +151,4 @@ IRQ_HANDLER 125 /* SYSCTL IRQ handler */ IRQ_HANDLER 126 /* DEBUG[0] IRQ handler */ IRQ_HANDLER 127 /* DEBUG[1] IRQ handler */ + diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h index 3b9797fc..e822fefc 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_adc12_regs.h @@ -392,8 +392,8 @@ typedef struct { * * threshold high, assert interrupt(if enabled) if result exceed high or low. */ -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFFF0000UL) -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (16U) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFF00000UL) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (20U) #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) @@ -402,8 +402,8 @@ typedef struct { * * threshold low */ -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFFFU) -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (0U) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFF0U) +#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (4U) #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) #define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) @@ -502,7 +502,7 @@ typedef struct { /* Bitfield definition for register: INT_STS */ /* - * TRIG_CMPT (W1C) + * TRIG_CMPT (RW1C) * * interrupt for one trigger conversion complete if enabled */ @@ -512,7 +512,7 @@ typedef struct { #define ADC12_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_CMPT_MASK) >> ADC12_INT_STS_TRIG_CMPT_SHIFT) /* - * TRIG_SW_CFLCT (W1C) + * TRIG_SW_CFLCT (RW1C) * */ #define ADC12_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) @@ -521,7 +521,7 @@ typedef struct { #define ADC12_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC12_INT_STS_TRIG_SW_CFLCT_SHIFT) /* - * TRIG_HW_CFLCT (RW) + * TRIG_HW_CFLCT (RW1C) * */ #define ADC12_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) @@ -530,7 +530,7 @@ typedef struct { #define ADC12_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC12_INT_STS_TRIG_HW_CFLCT_SHIFT) /* - * READ_CFLCT (W1C) + * READ_CFLCT (RW1C) * * read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel */ @@ -540,7 +540,7 @@ typedef struct { #define ADC12_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_READ_CFLCT_MASK) >> ADC12_INT_STS_READ_CFLCT_SHIFT) /* - * SEQ_SW_CFLCT (W1C) + * SEQ_SW_CFLCT (RW1C) * * sequence queue conflict interrup, set if HW or SW trigger received during conversion */ @@ -550,7 +550,7 @@ typedef struct { #define ADC12_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC12_INT_STS_SEQ_SW_CFLCT_SHIFT) /* - * SEQ_HW_CFLCT (RW) + * SEQ_HW_CFLCT (RW1C) * */ #define ADC12_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) @@ -559,7 +559,7 @@ typedef struct { #define ADC12_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC12_INT_STS_SEQ_HW_CFLCT_SHIFT) /* - * SEQ_DMAABT (W1C) + * SEQ_DMAABT (RW1C) * * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set */ @@ -569,7 +569,7 @@ typedef struct { #define ADC12_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_DMAABT_MASK) >> ADC12_INT_STS_SEQ_DMAABT_SHIFT) /* - * SEQ_CMPT (W1C) + * SEQ_CMPT (RW1C) * * the whole sequence complete interrupt */ @@ -579,7 +579,7 @@ typedef struct { #define ADC12_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_CMPT_MASK) >> ADC12_INT_STS_SEQ_CMPT_SHIFT) /* - * SEQ_CVC (W1C) + * SEQ_CVC (RW1C) * * one conversion complete in seq_queue if related seq_int_en is set */ @@ -589,7 +589,7 @@ typedef struct { #define ADC12_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_CVC_MASK) >> ADC12_INT_STS_SEQ_CVC_SHIFT) /* - * DMA_FIFO_FULL (RW) + * DMA_FIFO_FULL (RW1C) * */ #define ADC12_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL) @@ -598,7 +598,7 @@ typedef struct { #define ADC12_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC12_INT_STS_DMA_FIFO_FULL_MASK) >> ADC12_INT_STS_DMA_FIFO_FULL_SHIFT) /* - * AHB_ERR (RW) + * AHB_ERR (RW1C) * * set if got hresp=1 */ @@ -608,7 +608,7 @@ typedef struct { #define ADC12_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC12_INT_STS_AHB_ERR_MASK) >> ADC12_INT_STS_AHB_ERR_SHIFT) /* - * WDOG (W1C) + * WDOG (RW1C) * * set if one chanel watch dog event triggered */ @@ -619,7 +619,7 @@ typedef struct { /* Bitfield definition for register: INT_EN */ /* - * TRIG_CMPT (W1C) + * TRIG_CMPT (RW) * * interrupt for one trigger conversion complete if enabled */ @@ -629,7 +629,7 @@ typedef struct { #define ADC12_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_CMPT_MASK) >> ADC12_INT_EN_TRIG_CMPT_SHIFT) /* - * TRIG_SW_CFLCT (W1C) + * TRIG_SW_CFLCT (RW) * */ #define ADC12_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) @@ -647,7 +647,7 @@ typedef struct { #define ADC12_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC12_INT_EN_TRIG_HW_CFLCT_SHIFT) /* - * READ_CFLCT (W1C) + * READ_CFLCT (RW) * * read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel */ @@ -657,7 +657,7 @@ typedef struct { #define ADC12_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_READ_CFLCT_MASK) >> ADC12_INT_EN_READ_CFLCT_SHIFT) /* - * SEQ_SW_CFLCT (W1C) + * SEQ_SW_CFLCT (RW) * * sequence queue conflict interrup, set if HW or SW trigger received during conversion */ @@ -676,7 +676,7 @@ typedef struct { #define ADC12_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC12_INT_EN_SEQ_HW_CFLCT_SHIFT) /* - * SEQ_DMAABT (W1C) + * SEQ_DMAABT (RW) * * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set */ @@ -686,7 +686,7 @@ typedef struct { #define ADC12_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_DMAABT_MASK) >> ADC12_INT_EN_SEQ_DMAABT_SHIFT) /* - * SEQ_CMPT (W1C) + * SEQ_CMPT (RW) * * the whole sequence complete interrupt */ @@ -696,7 +696,7 @@ typedef struct { #define ADC12_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_CMPT_MASK) >> ADC12_INT_EN_SEQ_CMPT_SHIFT) /* - * SEQ_CVC (W1C) + * SEQ_CVC (RW) * * one conversion complete in seq_queue if related seq_int_en is set */ @@ -706,7 +706,7 @@ typedef struct { #define ADC12_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_CVC_MASK) >> ADC12_INT_EN_SEQ_CVC_SHIFT) /* - * DMA_FIFO_FULL (W1C) + * DMA_FIFO_FULL (RW) * * DMA fifo full interrupt, user need to check clock frequency if it's set. */ @@ -716,7 +716,7 @@ typedef struct { #define ADC12_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC12_INT_EN_DMA_FIFO_FULL_MASK) >> ADC12_INT_EN_DMA_FIFO_FULL_SHIFT) /* - * AHB_ERR (W1C) + * AHB_ERR (RW) * * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr */ @@ -726,7 +726,7 @@ typedef struct { #define ADC12_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC12_INT_EN_AHB_ERR_MASK) >> ADC12_INT_EN_AHB_ERR_SHIFT) /* - * WDOG (W1C) + * WDOG (RW) * * set if one chanel watch dog event triggered */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h index c58cd93a..eb667f65 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_adc16_regs.h @@ -23,7 +23,8 @@ typedef struct { __R uint32_t SEQ_WR_ADDR; /* 0x808: */ __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */ __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */ - __R uint8_t RESERVED3[944]; /* 0x850 - 0xBFF: Reserved */ + __RW uint32_t SEQ_HIGH_CFG; /* 0x850: */ + __R uint8_t RESERVED3[940]; /* 0x854 - 0xBFF: Reserved */ struct { __RW uint32_t PRD_CFG; /* 0xC00: */ __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */ @@ -388,6 +389,25 @@ typedef struct { #define ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) #define ADC16_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) +/* Bitfield definition for register: SEQ_HIGH_CFG */ +/* + * STOP_POS_HIGH (RW) + * + */ +#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK (0xFFF000UL) +#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT (12U) +#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SET(x) (((uint32_t)(x) << ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT) & ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) +#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_GET(x) (((uint32_t)(x) & ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) >> ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT) + +/* + * BUF_LEN_HIGH (RW) + * + */ +#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK (0xFFFU) +#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT (0U) +#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SET(x) (((uint32_t)(x) << ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT) & ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) +#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_GET(x) (((uint32_t)(x) & ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) >> ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT) + /* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */ /* * PRESCALE (RW) @@ -467,7 +487,7 @@ typedef struct { /* * CONVERT_CLOCK_NUMBER (RW) * - * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 22 adc clock cycles(based on clock after divider); + * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); * user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz). */ @@ -536,7 +556,7 @@ typedef struct { /* Bitfield definition for register: INT_STS */ /* - * TRIG_CMPT (W1C) + * TRIG_CMPT (RW1C) * * interrupt for one trigger conversion complete if enabled */ @@ -546,7 +566,7 @@ typedef struct { #define ADC16_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_CMPT_MASK) >> ADC16_INT_STS_TRIG_CMPT_SHIFT) /* - * TRIG_SW_CFLCT (W1C) + * TRIG_SW_CFLCT (RW1C) * */ #define ADC16_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) @@ -555,7 +575,7 @@ typedef struct { #define ADC16_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) /* - * TRIG_HW_CFLCT (RW) + * TRIG_HW_CFLCT (RW1C) * */ #define ADC16_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) @@ -564,7 +584,7 @@ typedef struct { #define ADC16_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) /* - * READ_CFLCT (W1C) + * READ_CFLCT (RW1C) * * read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel */ @@ -574,7 +594,7 @@ typedef struct { #define ADC16_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_READ_CFLCT_MASK) >> ADC16_INT_STS_READ_CFLCT_SHIFT) /* - * SEQ_SW_CFLCT (W1C) + * SEQ_SW_CFLCT (RW1C) * * sequence queue conflict interrup, set if HW or SW trigger received during conversion */ @@ -584,7 +604,7 @@ typedef struct { #define ADC16_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) /* - * SEQ_HW_CFLCT (RW) + * SEQ_HW_CFLCT (RW1C) * */ #define ADC16_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) @@ -593,7 +613,7 @@ typedef struct { #define ADC16_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) /* - * SEQ_DMAABT (W1C) + * SEQ_DMAABT (RW1C) * * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set */ @@ -603,7 +623,7 @@ typedef struct { #define ADC16_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_DMAABT_MASK) >> ADC16_INT_STS_SEQ_DMAABT_SHIFT) /* - * SEQ_CMPT (W1C) + * SEQ_CMPT (RW1C) * * the whole sequence complete interrupt */ @@ -613,7 +633,7 @@ typedef struct { #define ADC16_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CMPT_MASK) >> ADC16_INT_STS_SEQ_CMPT_SHIFT) /* - * SEQ_CVC (W1C) + * SEQ_CVC (RW1C) * * one conversion complete in seq_queue if related seq_int_en is set */ @@ -623,7 +643,7 @@ typedef struct { #define ADC16_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CVC_MASK) >> ADC16_INT_STS_SEQ_CVC_SHIFT) /* - * DMA_FIFO_FULL (RW) + * DMA_FIFO_FULL (RW1C) * * DMA fifo full interrupt, user need to check clock frequency if it's set. */ @@ -633,7 +653,7 @@ typedef struct { #define ADC16_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) >> ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) /* - * AHB_ERR (RW) + * AHB_ERR (RW1C) * * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr */ @@ -643,7 +663,7 @@ typedef struct { #define ADC16_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_STS_AHB_ERR_MASK) >> ADC16_INT_STS_AHB_ERR_SHIFT) /* - * WDOG (W1C) + * WDOG (RW1C) * * set if one chanel watch dog event triggered */ @@ -654,7 +674,7 @@ typedef struct { /* Bitfield definition for register: INT_EN */ /* - * TRIG_CMPT (W1C) + * TRIG_CMPT (RW) * * interrupt for one trigger conversion complete if enabled */ @@ -664,7 +684,7 @@ typedef struct { #define ADC16_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_CMPT_MASK) >> ADC16_INT_EN_TRIG_CMPT_SHIFT) /* - * TRIG_SW_CFLCT (W1C) + * TRIG_SW_CFLCT (RW) * */ #define ADC16_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) @@ -682,7 +702,7 @@ typedef struct { #define ADC16_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) /* - * READ_CFLCT (W1C) + * READ_CFLCT (RW) * * read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel */ @@ -692,7 +712,7 @@ typedef struct { #define ADC16_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_READ_CFLCT_MASK) >> ADC16_INT_EN_READ_CFLCT_SHIFT) /* - * SEQ_SW_CFLCT (W1C) + * SEQ_SW_CFLCT (RW) * * sequence queue conflict interrup, set if HW or SW trigger received during conversion */ @@ -711,7 +731,7 @@ typedef struct { #define ADC16_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) /* - * SEQ_DMAABT (W1C) + * SEQ_DMAABT (RW) * * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set */ @@ -721,7 +741,7 @@ typedef struct { #define ADC16_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_DMAABT_MASK) >> ADC16_INT_EN_SEQ_DMAABT_SHIFT) /* - * SEQ_CMPT (W1C) + * SEQ_CMPT (RW) * * the whole sequence complete interrupt */ @@ -731,7 +751,7 @@ typedef struct { #define ADC16_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CMPT_MASK) >> ADC16_INT_EN_SEQ_CMPT_SHIFT) /* - * SEQ_CVC (W1C) + * SEQ_CVC (RW) * * one conversion complete in seq_queue if related seq_int_en is set */ @@ -761,7 +781,7 @@ typedef struct { #define ADC16_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_EN_AHB_ERR_MASK) >> ADC16_INT_EN_AHB_ERR_SHIFT) /* - * WDOG (W1C) + * WDOG (RW) * * set if one chanel watch dog event triggered */ @@ -771,6 +791,17 @@ typedef struct { #define ADC16_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_EN_WDOG_MASK) >> ADC16_INT_EN_WDOG_SHIFT) /* Bitfield definition for register: ANA_CTRL0 */ +/* + * MOTO_EN (RW) + * + * "set to enable moto_soc and moto_valid. + * Should use AHB clock for adc, this bit can be used avoid async output" + */ +#define ADC16_ANA_CTRL0_MOTO_EN_MASK (0x80000000UL) +#define ADC16_ANA_CTRL0_MOTO_EN_SHIFT (31U) +#define ADC16_ANA_CTRL0_MOTO_EN_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_MOTO_EN_SHIFT) & ADC16_ANA_CTRL0_MOTO_EN_MASK) +#define ADC16_ANA_CTRL0_MOTO_EN_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_MOTO_EN_MASK) >> ADC16_ANA_CTRL0_MOTO_EN_SHIFT) + /* * ADC_CLK_ON (RW) * diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h index 67aaea0e..f9153d7c 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_cam_regs.h @@ -26,8 +26,7 @@ typedef struct { __RW uint32_t DMASA_UV1; /* 0x50: Pixel UV DMA Frame Buffer 1 Address */ __RW uint32_t DMASA_UV2; /* 0x54: Pixel UV DMA Frame Buffer 2 Address */ __RW uint32_t CR20; /* 0x58: Control CR20 Register */ - __RW uint32_t MAX_WN_CYCLE; /* 0x5C: Max Window Size Register */ - __R uint8_t RESERVED4[16]; /* 0x60 - 0x6F: Reserved */ + __R uint8_t RESERVED4[20]; /* 0x5C - 0x6F: Reserved */ __RW uint32_t CSC_COEF0; /* 0x70: Color Space Conversion Config Register 0 */ __RW uint32_t CSC_COEF1; /* 0x74: Color Space Conversion Config Register 1 */ __RW uint32_t CSC_COEF2; /* 0x78: Color Space Conversion Config Register 2 */ @@ -628,27 +627,6 @@ typedef struct { #define CAM_CR20_THRESHOLD_SET(x) (((uint32_t)(x) << CAM_CR20_THRESHOLD_SHIFT) & CAM_CR20_THRESHOLD_MASK) #define CAM_CR20_THRESHOLD_GET(x) (((uint32_t)(x) & CAM_CR20_THRESHOLD_MASK) >> CAM_CR20_THRESHOLD_SHIFT) -/* Bitfield definition for register: MAX_WN_CYCLE */ -/* - * ROW (RW) - * - * Max Width-1 - */ -#define CAM_MAX_WN_CYCLE_ROW_MASK (0xFFFF0000UL) -#define CAM_MAX_WN_CYCLE_ROW_SHIFT (16U) -#define CAM_MAX_WN_CYCLE_ROW_SET(x) (((uint32_t)(x) << CAM_MAX_WN_CYCLE_ROW_SHIFT) & CAM_MAX_WN_CYCLE_ROW_MASK) -#define CAM_MAX_WN_CYCLE_ROW_GET(x) (((uint32_t)(x) & CAM_MAX_WN_CYCLE_ROW_MASK) >> CAM_MAX_WN_CYCLE_ROW_SHIFT) - -/* - * COL (RW) - * - * Max Height-1 - */ -#define CAM_MAX_WN_CYCLE_COL_MASK (0xFFFFU) -#define CAM_MAX_WN_CYCLE_COL_SHIFT (0U) -#define CAM_MAX_WN_CYCLE_COL_SET(x) (((uint32_t)(x) << CAM_MAX_WN_CYCLE_COL_SHIFT) & CAM_MAX_WN_CYCLE_COL_MASK) -#define CAM_MAX_WN_CYCLE_COL_GET(x) (((uint32_t)(x) & CAM_MAX_WN_CYCLE_COL_MASK) >> CAM_MAX_WN_CYCLE_COL_SHIFT) - /* Bitfield definition for register: CSC_COEF0 */ /* * YCBCR_MODE (RW) diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h index be790a32..ff8f56d6 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_dac_regs.h @@ -90,6 +90,9 @@ typedef struct { * 00: direct mode, DAC output the fixed configured data(from sw_dac_data) * 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down * 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; + * 11: trigger mode, DAC output from external trigger signals + * Note: + * Trigger mode is not supported in hpm63xx and hpm62xx families. */ #define DAC_CFG0_DAC_MODE_MASK (0x30U) #define DAC_CFG0_DAC_MODE_SHIFT (4U) @@ -125,6 +128,7 @@ typedef struct { * ANA_CLK_EN (RW) * * set to enable analog clock(divided by ana_div_cfg) + * need to be set in direct mode and trigger mode */ #define DAC_CFG1_ANA_CLK_EN_MASK (0x40000UL) #define DAC_CFG1_ANA_CLK_EN_SHIFT (18U) @@ -148,8 +152,12 @@ typedef struct { /* * DIV_CFG (RW) * - * how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. - * Used for step mode and buffer mode, if set to continual trigger mode + * step mode and buffer mode: + * defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. + * Direct mode and trigger mode: + * defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. + * Note: + * For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. */ #define DAC_CFG1_DIV_CFG_MASK (0xFFFFU) #define DAC_CFG1_DIV_CFG_SHIFT (0U) diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h index b58971ff..c9d53722 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_dao_regs.h @@ -128,6 +128,18 @@ typedef struct { #define DAO_CMD_RUN_GET(x) (((uint32_t)(x) & DAO_CMD_RUN_MASK) >> DAO_CMD_RUN_SHIFT) /* Bitfield definition for register: RX_CFGR */ +/* + * FRAME_EDGE (RW) + * + * The start edge of a frame + * 0: Falling edge indicates a new frame (Just like standard I2S Philips standard) + * 1: Rising edge indicates a new frame + */ +#define DAO_RX_CFGR_FRAME_EDGE_MASK (0x800U) +#define DAO_RX_CFGR_FRAME_EDGE_SHIFT (11U) +#define DAO_RX_CFGR_FRAME_EDGE_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_FRAME_EDGE_SHIFT) & DAO_RX_CFGR_FRAME_EDGE_MASK) +#define DAO_RX_CFGR_FRAME_EDGE_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_FRAME_EDGE_MASK) >> DAO_RX_CFGR_FRAME_EDGE_SHIFT) + /* * CH_MAX (RW) * @@ -142,6 +154,63 @@ typedef struct { #define DAO_RX_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CH_MAX_SHIFT) & DAO_RX_CFGR_CH_MAX_MASK) #define DAO_RX_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CH_MAX_MASK) >> DAO_RX_CFGR_CH_MAX_SHIFT) +/* + * TDM_EN (RW) + * + * TDM mode + * 0: not TDM mode + * 1: TDM mode + */ +#define DAO_RX_CFGR_TDM_EN_MASK (0x20U) +#define DAO_RX_CFGR_TDM_EN_SHIFT (5U) +#define DAO_RX_CFGR_TDM_EN_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_TDM_EN_SHIFT) & DAO_RX_CFGR_TDM_EN_MASK) +#define DAO_RX_CFGR_TDM_EN_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_TDM_EN_MASK) >> DAO_RX_CFGR_TDM_EN_SHIFT) + +/* + * STD (RW) + * + * I2S standard selection + * 00: I2S Philips standard. + * 01: MSB justified standard (left justified) + * 10: LSB justified standard (right justified) + * 11: PCM standard + * For more details on I2S standards. + * Note: For correct operation, these bits should be configured when the I2S is disabled. + */ +#define DAO_RX_CFGR_STD_MASK (0x18U) +#define DAO_RX_CFGR_STD_SHIFT (3U) +#define DAO_RX_CFGR_STD_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_STD_SHIFT) & DAO_RX_CFGR_STD_MASK) +#define DAO_RX_CFGR_STD_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_STD_MASK) >> DAO_RX_CFGR_STD_SHIFT) + +/* + * DATSIZ (RW) + * + * Data length to be transferred + * 00: 16-bit data length + * 01: 24-bit data length + * 10: 32-bit data length + * 11: Not allowed + * Note: For correct operation, these bits should be configured when the I2S is disabled. + */ +#define DAO_RX_CFGR_DATSIZ_MASK (0x6U) +#define DAO_RX_CFGR_DATSIZ_SHIFT (1U) +#define DAO_RX_CFGR_DATSIZ_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_DATSIZ_SHIFT) & DAO_RX_CFGR_DATSIZ_MASK) +#define DAO_RX_CFGR_DATSIZ_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_DATSIZ_MASK) >> DAO_RX_CFGR_DATSIZ_SHIFT) + +/* + * CHSIZ (RW) + * + * Channel length (number of bits per audio channel) + * 0: 16-bit wide + * 1: 32-bit wide + * The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. + * Note: For correct operation, this bit should be configured when the I2S is disabled. + */ +#define DAO_RX_CFGR_CHSIZ_MASK (0x1U) +#define DAO_RX_CFGR_CHSIZ_SHIFT (0U) +#define DAO_RX_CFGR_CHSIZ_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CHSIZ_SHIFT) & DAO_RX_CFGR_CHSIZ_MASK) +#define DAO_RX_CFGR_CHSIZ_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CHSIZ_MASK) >> DAO_RX_CFGR_CHSIZ_SHIFT) + /* Bitfield definition for register: RXSLT */ /* * EN (RW) @@ -178,4 +247,4 @@ typedef struct { -#endif /* HPM_DAO_H */ \ No newline at end of file +#endif /* HPM_DAO_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_dmav2_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_dmav2_regs.h new file mode 100644 index 00000000..9fbe188a --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_dmav2_regs.h @@ -0,0 +1,596 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_DMAV2_H +#define HPM_DMAV2_H + +typedef struct { + __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ + __R uint32_t IDMISC; /* 0x4: ID Misc */ + __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ + __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ + __W uint32_t DMACTRL; /* 0x14: DMAC Control Register */ + __W uint32_t CHABORT; /* 0x18: Channel Abort Register */ + __R uint8_t RESERVED2[8]; /* 0x1C - 0x23: Reserved */ + __RW uint32_t INTHALFSTS; /* 0x24: Harlf Complete Interrupt Status */ + __W uint32_t INTTCSTS; /* 0x28: Trans Complete Interrupt Status Register */ + __W uint32_t INTABORTSTS; /* 0x2C: Abort Interrupt Status Register */ + __W uint32_t INTERRSTS; /* 0x30: Error Interrupt Status Register */ + __R uint32_t CHEN; /* 0x34: Channel Enable Register */ + __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ + struct { + __RW uint32_t CTRL; /* 0x40: Channel Control Register */ + __RW uint32_t TRANSIZE; /* 0x44: Channel Transfer Size Register */ + __RW uint32_t SRCADDR; /* 0x48: Channel Source Address Low Part Register */ + __RW uint32_t CHANREQCTRL; /* 0x4C: Channel DMA Request Control Register */ + __RW uint32_t DSTADDR; /* 0x50: Channel Destination Address Low Part Register */ + __R uint8_t RESERVED0[4]; /* 0x54 - 0x57: Reserved */ + __RW uint32_t LLPOINTER; /* 0x58: Channel Linked List Pointer Low Part Register */ + __R uint8_t RESERVED1[4]; /* 0x5C - 0x5F: Reserved */ + } CHCTRL[32]; +} DMAV2_Type; + + +/* Bitfield definition for register: IDMISC */ +/* + * DMASTATE (RO) + * + * DMA state machine + * localparam ST_IDLE = 3'b000; + * localparam ST_READ = 3'b001; + * localparam ST_READ_ACK = 3'b010; + * localparam ST_WRITE = 3'b011; + * localparam ST_WRITE_ACK = 3'b100; + * localparam ST_LL = 3'b101; + * localparam ST_END = 3'b110; + * localparam ST_END_WAIT = 3'b111; + */ +#define DMAV2_IDMISC_DMASTATE_MASK (0xE000U) +#define DMAV2_IDMISC_DMASTATE_SHIFT (13U) +#define DMAV2_IDMISC_DMASTATE_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_DMASTATE_MASK) >> DMAV2_IDMISC_DMASTATE_SHIFT) + +/* + * CURCHAN (RO) + * + * current channel in used + */ +#define DMAV2_IDMISC_CURCHAN_MASK (0x1F00U) +#define DMAV2_IDMISC_CURCHAN_SHIFT (8U) +#define DMAV2_IDMISC_CURCHAN_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_CURCHAN_MASK) >> DMAV2_IDMISC_CURCHAN_SHIFT) + +/* Bitfield definition for register: DMACFG */ +/* + * CHAINXFR (RO) + * + * Chain transfer + * 0x0: Chain transfer is not configured + * 0x1: Chain transfer is configured + */ +#define DMAV2_DMACFG_CHAINXFR_MASK (0x80000000UL) +#define DMAV2_DMACFG_CHAINXFR_SHIFT (31U) +#define DMAV2_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHAINXFR_MASK) >> DMAV2_DMACFG_CHAINXFR_SHIFT) + +/* + * REQSYNC (RO) + * + * DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, + * which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. + * 0x0: Request synchronization is not configured + * 0x1: Request synchronization is configured + */ +#define DMAV2_DMACFG_REQSYNC_MASK (0x40000000UL) +#define DMAV2_DMACFG_REQSYNC_SHIFT (30U) +#define DMAV2_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQSYNC_MASK) >> DMAV2_DMACFG_REQSYNC_SHIFT) + +/* + * DATAWIDTH (RO) + * + * AXI bus data width + * 0x0: 32 bits + * 0x1: 64 bits + * 0x2: 128 bits + * 0x3: 256 bits + */ +#define DMAV2_DMACFG_DATAWIDTH_MASK (0x3000000UL) +#define DMAV2_DMACFG_DATAWIDTH_SHIFT (24U) +#define DMAV2_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_DATAWIDTH_MASK) >> DMAV2_DMACFG_DATAWIDTH_SHIFT) + +/* + * ADDRWIDTH (RO) + * + * AXI bus address width + * 0x18: 24 bits + * 0x19: 25 bits + * ... + * 0x40: 64 bits + * Others: Invalid + */ +#define DMAV2_DMACFG_ADDRWIDTH_MASK (0xFE0000UL) +#define DMAV2_DMACFG_ADDRWIDTH_SHIFT (17U) +#define DMAV2_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_ADDRWIDTH_MASK) >> DMAV2_DMACFG_ADDRWIDTH_SHIFT) + +/* + * CORENUM (RO) + * + * DMA core number + * 0x0: 1 core + * 0x1: 2 cores + */ +#define DMAV2_DMACFG_CORENUM_MASK (0x10000UL) +#define DMAV2_DMACFG_CORENUM_SHIFT (16U) +#define DMAV2_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CORENUM_MASK) >> DMAV2_DMACFG_CORENUM_SHIFT) + +/* + * BUSNUM (RO) + * + * AXI bus interface number + * 0x0: 1 AXI bus + * 0x1: 2 AXI busses + */ +#define DMAV2_DMACFG_BUSNUM_MASK (0x8000U) +#define DMAV2_DMACFG_BUSNUM_SHIFT (15U) +#define DMAV2_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_BUSNUM_MASK) >> DMAV2_DMACFG_BUSNUM_SHIFT) + +/* + * REQNUM (RO) + * + * Request/acknowledge pair number + * 0x0: 0 pair + * 0x1: 1 pair + * 0x2: 2 pairs + * ... + * 0x10: 16 pairs + */ +#define DMAV2_DMACFG_REQNUM_MASK (0x7C00U) +#define DMAV2_DMACFG_REQNUM_SHIFT (10U) +#define DMAV2_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQNUM_MASK) >> DMAV2_DMACFG_REQNUM_SHIFT) + +/* + * FIFODEPTH (RO) + * + * FIFO depth + * 0x4: 4 entries + * 0x8: 8 entries + * 0x10: 16 entries + * 0x20: 32 entries + * Others: Invalid + */ +#define DMAV2_DMACFG_FIFODEPTH_MASK (0x3F0U) +#define DMAV2_DMACFG_FIFODEPTH_SHIFT (4U) +#define DMAV2_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_FIFODEPTH_MASK) >> DMAV2_DMACFG_FIFODEPTH_SHIFT) + +/* + * CHANNELNUM (RO) + * + * Channel number + * 0x1: 1 channel + * 0x2: 2 channels + * ... + * 0x8: 8 channels + * Others: Invalid + */ +#define DMAV2_DMACFG_CHANNELNUM_MASK (0xFU) +#define DMAV2_DMACFG_CHANNELNUM_SHIFT (0U) +#define DMAV2_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHANNELNUM_MASK) >> DMAV2_DMACFG_CHANNELNUM_SHIFT) + +/* Bitfield definition for register: DMACTRL */ +/* + * RESET (WO) + * + * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. + * Note: The software reset may cause the in-completion of AXI transaction. + */ +#define DMAV2_DMACTRL_RESET_MASK (0x1U) +#define DMAV2_DMACTRL_RESET_SHIFT (0U) +#define DMAV2_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMAV2_DMACTRL_RESET_SHIFT) & DMAV2_DMACTRL_RESET_MASK) +#define DMAV2_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMAV2_DMACTRL_RESET_MASK) >> DMAV2_DMACTRL_RESET_SHIFT) + +/* Bitfield definition for register: CHABORT */ +/* + * CHABORT (WO) + * + * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. + * Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) + */ +#define DMAV2_CHABORT_CHABORT_MASK (0xFFFFFFFFUL) +#define DMAV2_CHABORT_CHABORT_SHIFT (0U) +#define DMAV2_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMAV2_CHABORT_CHABORT_SHIFT) & DMAV2_CHABORT_CHABORT_MASK) +#define DMAV2_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMAV2_CHABORT_CHABORT_MASK) >> DMAV2_CHABORT_CHABORT_SHIFT) + +/* Bitfield definition for register: INTHALFSTS */ +/* + * STS (RW) + * + * half transfer done irq status + */ +#define DMAV2_INTHALFSTS_STS_MASK (0xFFFFFFFFUL) +#define DMAV2_INTHALFSTS_STS_SHIFT (0U) +#define DMAV2_INTHALFSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTHALFSTS_STS_SHIFT) & DMAV2_INTHALFSTS_STS_MASK) +#define DMAV2_INTHALFSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTHALFSTS_STS_MASK) >> DMAV2_INTHALFSTS_STS_SHIFT) + +/* Bitfield definition for register: INTTCSTS */ +/* + * STS (W1C) + * + * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. + * 0x0: Channel n has no terminal count status + * 0x1: Channel n has terminal count status + */ +#define DMAV2_INTTCSTS_STS_MASK (0xFFFFFFFFUL) +#define DMAV2_INTTCSTS_STS_SHIFT (0U) +#define DMAV2_INTTCSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTTCSTS_STS_SHIFT) & DMAV2_INTTCSTS_STS_MASK) +#define DMAV2_INTTCSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTTCSTS_STS_MASK) >> DMAV2_INTTCSTS_STS_SHIFT) + +/* Bitfield definition for register: INTABORTSTS */ +/* + * STS (W1C) + * + * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. + * 0x0: Channel n has no abort status + * 0x1: Channel n has abort status + */ +#define DMAV2_INTABORTSTS_STS_MASK (0xFFFFFFFFUL) +#define DMAV2_INTABORTSTS_STS_SHIFT (0U) +#define DMAV2_INTABORTSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTABORTSTS_STS_SHIFT) & DMAV2_INTABORTSTS_STS_MASK) +#define DMAV2_INTABORTSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTABORTSTS_STS_MASK) >> DMAV2_INTABORTSTS_STS_SHIFT) + +/* Bitfield definition for register: INTERRSTS */ +/* + * STS (W1C) + * + * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: + * - Bus error + * - Unaligned address + * - Unaligned transfer width + * - Reserved configuration + * 0x0: Channel n has no error status + * 0x1: Channel n has error status + */ +#define DMAV2_INTERRSTS_STS_MASK (0xFFFFFFFFUL) +#define DMAV2_INTERRSTS_STS_SHIFT (0U) +#define DMAV2_INTERRSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTERRSTS_STS_SHIFT) & DMAV2_INTERRSTS_STS_MASK) +#define DMAV2_INTERRSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTERRSTS_STS_MASK) >> DMAV2_INTERRSTS_STS_SHIFT) + +/* Bitfield definition for register: CHEN */ +/* + * CHEN (RO) + * + * Alias of the Enable field of all ChnCtrl registers + */ +#define DMAV2_CHEN_CHEN_MASK (0xFFFFFFFFUL) +#define DMAV2_CHEN_CHEN_SHIFT (0U) +#define DMAV2_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMAV2_CHEN_CHEN_MASK) >> DMAV2_CHEN_CHEN_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: CTRL */ +/* + * INFINITELOOP (RW) + * + * set to loop current config infinitely + */ +#define DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK (0x80000000UL) +#define DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT (31U) +#define DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) +#define DMAV2_CHCTRL_CTRL_INFINITELOOP_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) >> DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) + +/* + * HANDSHAKEOPT (RW) + * + * 0: one request to transfer one burst + * 1: one request to transfer all the data defined in ch_tts + */ +#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK (0x40000000UL) +#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT (30U) +#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) +#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) >> DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) + +/* + * PRIORITY (RW) + * + * Channel priority level + * 0x0: Lower priority + * 0x1: Higher priority + */ +#define DMAV2_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL) +#define DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT (29U) +#define DMAV2_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) +#define DMAV2_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) >> DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) + +/* + * BURSTOPT (RW) + * + * set to change burst_size definition + */ +#define DMAV2_CHCTRL_CTRL_BURSTOPT_MASK (0x10000000UL) +#define DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT (28U) +#define DMAV2_CHCTRL_CTRL_BURSTOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) +#define DMAV2_CHCTRL_CTRL_BURSTOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) >> DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) + +/* + * SRCBURSTSIZE (RW) + * + * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. + * The burst transfer byte number is (SrcBurstSize * SrcWidth). + * 0x0: 1 transfer + * 0x1: 2 transfers + * 0x2: 4 transfers + * 0x3: 8 transfers + * 0x4: 16 transfers + * 0x5: 32 transfers + * 0x6: 64 transfers + * 0x7: 128 transfers + * 0x8: 256 transfers + * 0x9:512 transfers + * 0xa: 1024 transfers + * 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception + */ +#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) +#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) +#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) +#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) + +/* + * SRCWIDTH (RW) + * + * Source transfer width + * 0x0: Byte transfer + * 0x1: Half-word transfer + * 0x2: Word transfer + * 0x3: Double word transfer + * 0x4: Quad word transfer + * 0x5: Eight word transfer + * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception + */ +#define DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) +#define DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) +#define DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) +#define DMAV2_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) + +/* + * DSTWIDTH (RW) + * + * Destination transfer width. + * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. + * For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. + * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. + * 0x0: Byte transfer + * 0x1: Half-word transfer + * 0x2: Word transfer + * 0x3: Double word transfer + * 0x4: Quad word transfer + * 0x5: Eight word transfer + * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception + */ +#define DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) +#define DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) +#define DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) +#define DMAV2_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) + +/* + * SRCMODE (RW) + * + * Source DMA handshake mode + * 0x0: Normal mode + * 0x1: Handshake mode + * Normal mode is enabled and started by software set Enable bit; + * Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block + */ +#define DMAV2_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL) +#define DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT (17U) +#define DMAV2_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) +#define DMAV2_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) >> DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) + +/* + * DSTMODE (RW) + * + * Destination DMA handshake mode + * 0x0: Normal mode + * 0x1: Handshake mode + * the difference bewteen Source/Destination handshake mode is: + * the dma block will response hardware request after read in Source handshake mode; + * the dma block will response hardware request after write in Destination handshake mode; + * NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. + */ +#define DMAV2_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL) +#define DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT (16U) +#define DMAV2_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) +#define DMAV2_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) >> DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) + +/* + * SRCADDRCTRL (RW) + * + * Source address control + * 0x0: Increment address + * 0x1: Decrement address + * 0x2: Fixed address + * 0x3: Reserved, setting the field with this value triggers the error exception + */ +#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U) +#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U) +#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) +#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) + +/* + * DSTADDRCTRL (RW) + * + * Destination address control + * 0x0: Increment address + * 0x1: Decrement address + * 0x2: Fixed address + * 0x3: Reserved, setting the field with this value triggers the error exception + */ +#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U) +#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U) +#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) +#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) + +/* + * INTHALFCNTMASK (RW) + * + * Channel half interrupt mask + * 0x0: Allow the half interrupt to be triggered + * 0x1: Disable the half interrupt + */ +#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK (0x10U) +#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT (4U) +#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) +#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) + +/* + * INTABTMASK (RW) + * + * Channel abort interrupt mask + * 0x0: Allow the abort interrupt to be triggered + * 0x1: Disable the abort interrupt + */ +#define DMAV2_CHCTRL_CTRL_INTABTMASK_MASK (0x8U) +#define DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT (3U) +#define DMAV2_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) +#define DMAV2_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) + +/* + * INTERRMASK (RW) + * + * Channel error interrupt mask + * 0x0: Allow the error interrupt to be triggered + * 0x1: Disable the error interrupt + */ +#define DMAV2_CHCTRL_CTRL_INTERRMASK_MASK (0x4U) +#define DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT (2U) +#define DMAV2_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) +#define DMAV2_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) + +/* + * INTTCMASK (RW) + * + * Channel terminal count interrupt mask + * 0x0: Allow the terminal count interrupt to be triggered + * 0x1: Disable the terminal count interrupt + */ +#define DMAV2_CHCTRL_CTRL_INTTCMASK_MASK (0x2U) +#define DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT (1U) +#define DMAV2_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) +#define DMAV2_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) + +/* + * ENABLE (RW) + * + * Channel enable bit + * 0x0: Disable + * 0x1: Enable + */ +#define DMAV2_CHCTRL_CTRL_ENABLE_MASK (0x1U) +#define DMAV2_CHCTRL_CTRL_ENABLE_SHIFT (0U) +#define DMAV2_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) +#define DMAV2_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) >> DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: TRANSIZE */ +/* + * TRANSIZE (RW) + * + * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. + * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. + */ +#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFUL) +#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U) +#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) +#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: SRCADDR */ +/* + * SRCADDRL (RW) + * + * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. + * This address must be aligned to the source transfer size; otherwise, an error event will be triggered. + */ +#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL) +#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U) +#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) +#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: CHANREQCTRL */ +/* + * SRCREQSEL (RW) + * + * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + */ +#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK (0x1F000000UL) +#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT (24U) +#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) +#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) + +/* + * DSTREQSEL (RW) + * + * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + */ +#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK (0x1F0000UL) +#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT (16U) +#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) +#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: DSTADDR */ +/* + * DSTADDRL (RW) + * + * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. + * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. + */ +#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL) +#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U) +#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) +#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) + +/* Bitfield definition for register of struct array CHCTRL: LLPOINTER */ +/* + * LLPOINTERL (RW) + * + * Low part of the pointer to the next descriptor. The pointer must be double word aligned. + */ +#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL) +#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U) +#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) +#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) + + + +/* CHCTRL register group index macro definition */ +#define DMAV2_CHCTRL_CH0 (0UL) +#define DMAV2_CHCTRL_CH1 (1UL) +#define DMAV2_CHCTRL_CH2 (2UL) +#define DMAV2_CHCTRL_CH3 (3UL) +#define DMAV2_CHCTRL_CH4 (4UL) +#define DMAV2_CHCTRL_CH5 (5UL) +#define DMAV2_CHCTRL_CH6 (6UL) +#define DMAV2_CHCTRL_CH7 (7UL) +#define DMAV2_CHCTRL_CH8 (8UL) +#define DMAV2_CHCTRL_CH9 (9UL) +#define DMAV2_CHCTRL_CH10 (10UL) +#define DMAV2_CHCTRL_CH11 (11UL) +#define DMAV2_CHCTRL_CH12 (12UL) +#define DMAV2_CHCTRL_CH13 (13UL) +#define DMAV2_CHCTRL_CH14 (14UL) +#define DMAV2_CHCTRL_CH15 (15UL) +#define DMAV2_CHCTRL_CH16 (16UL) +#define DMAV2_CHCTRL_CH17 (17UL) +#define DMAV2_CHCTRL_CH18 (18UL) +#define DMAV2_CHCTRL_CH19 (19UL) +#define DMAV2_CHCTRL_CH20 (20UL) +#define DMAV2_CHCTRL_CH21 (21UL) +#define DMAV2_CHCTRL_CH22 (22UL) +#define DMAV2_CHCTRL_CH23 (23UL) +#define DMAV2_CHCTRL_CH24 (24UL) +#define DMAV2_CHCTRL_CH25 (25UL) +#define DMAV2_CHCTRL_CH26 (26UL) +#define DMAV2_CHCTRL_CH27 (27UL) +#define DMAV2_CHCTRL_CH28 (28UL) +#define DMAV2_CHCTRL_CH29 (29UL) +#define DMAV2_CHCTRL_CH30 (30UL) +#define DMAV2_CHCTRL_CH31 (31UL) + + +#endif /* HPM_DMAV2_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_ewdg_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_ewdg_regs.h new file mode 100644 index 00000000..c62dfb0a --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_ewdg_regs.h @@ -0,0 +1,465 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_EWDG_H +#define HPM_EWDG_H + +typedef struct { + __RW uint32_t CTRL0; /* 0x0: wdog ctrl register 0 +Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits */ + __RW uint32_t CTRL1; /* 0x4: wdog ctrl register 1 +Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits */ + __RW uint32_t OT_INT_VAL; /* 0x8: wdog timeout interrupt counter value */ + __RW uint32_t OT_RST_VAL; /* 0xC: wdog timeout reset counter value */ + __W uint32_t WDT_REFRESH_REG; /* 0x10: wdog refresh register */ + __RW uint32_t WDT_STATUS; /* 0x14: wdog status register */ + __RW uint32_t CFG_PROT; /* 0x18: ctrl register protection register */ + __RW uint32_t REF_PROT; /* 0x1C: refresh protection register */ + __RW uint32_t WDT_EN; /* 0x20: Wdog enable */ + __RW uint32_t REF_TIME; /* 0x24: Refresh period value */ +} EWDG_Type; + + +/* Bitfield definition for register: CTRL0 */ +/* + * CLK_SEL (RW) + * + * clock select + * 0：bus clock + * 1：ext clock + */ +#define EWDG_CTRL0_CLK_SEL_MASK (0x20000000UL) +#define EWDG_CTRL0_CLK_SEL_SHIFT (29U) +#define EWDG_CTRL0_CLK_SEL_SET(x) (((uint32_t)(x) << EWDG_CTRL0_CLK_SEL_SHIFT) & EWDG_CTRL0_CLK_SEL_MASK) +#define EWDG_CTRL0_CLK_SEL_GET(x) (((uint32_t)(x) & EWDG_CTRL0_CLK_SEL_MASK) >> EWDG_CTRL0_CLK_SEL_SHIFT) + +/* + * DIV_VALUE (RW) + * + * clock divider, the clock divider works as 2 ^ div_value for wdt counter + */ +#define EWDG_CTRL0_DIV_VALUE_MASK (0xE000000UL) +#define EWDG_CTRL0_DIV_VALUE_SHIFT (25U) +#define EWDG_CTRL0_DIV_VALUE_SET(x) (((uint32_t)(x) << EWDG_CTRL0_DIV_VALUE_SHIFT) & EWDG_CTRL0_DIV_VALUE_MASK) +#define EWDG_CTRL0_DIV_VALUE_GET(x) (((uint32_t)(x) & EWDG_CTRL0_DIV_VALUE_MASK) >> EWDG_CTRL0_DIV_VALUE_SHIFT) + +/* + * WIN_EN (RW) + * + * window mode enable + */ +#define EWDG_CTRL0_WIN_EN_MASK (0x1000000UL) +#define EWDG_CTRL0_WIN_EN_SHIFT (24U) +#define EWDG_CTRL0_WIN_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_EN_SHIFT) & EWDG_CTRL0_WIN_EN_MASK) +#define EWDG_CTRL0_WIN_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_EN_MASK) >> EWDG_CTRL0_WIN_EN_SHIFT) + +/* + * WIN_LOWER (RW) + * + * Once window mode is opened, the lower counter value to refresh wdt + * 00: 4/8 overtime value + * 01: 5/8 of overtime value + * 10: 6/8 of overtime value + * 11: 7/8 of overtime value + */ +#define EWDG_CTRL0_WIN_LOWER_MASK (0xC00000UL) +#define EWDG_CTRL0_WIN_LOWER_SHIFT (22U) +#define EWDG_CTRL0_WIN_LOWER_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_LOWER_SHIFT) & EWDG_CTRL0_WIN_LOWER_MASK) +#define EWDG_CTRL0_WIN_LOWER_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_LOWER_MASK) >> EWDG_CTRL0_WIN_LOWER_SHIFT) + +/* + * CFG_LOCK (RW) + * + * The register is locked and unlock is needed before re-config registers + * Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. + * The register update needs to be finished in the required period defined by UPD_OT_TIME register + */ +#define EWDG_CTRL0_CFG_LOCK_MASK (0x200000UL) +#define EWDG_CTRL0_CFG_LOCK_SHIFT (21U) +#define EWDG_CTRL0_CFG_LOCK_SET(x) (((uint32_t)(x) << EWDG_CTRL0_CFG_LOCK_SHIFT) & EWDG_CTRL0_CFG_LOCK_MASK) +#define EWDG_CTRL0_CFG_LOCK_GET(x) (((uint32_t)(x) & EWDG_CTRL0_CFG_LOCK_MASK) >> EWDG_CTRL0_CFG_LOCK_SHIFT) + +/* + * OT_SELF_CLEAR (RW) + * + * overtime reset can be self released after 32 function cycles + */ +#define EWDG_CTRL0_OT_SELF_CLEAR_MASK (0x20000UL) +#define EWDG_CTRL0_OT_SELF_CLEAR_SHIFT (17U) +#define EWDG_CTRL0_OT_SELF_CLEAR_SET(x) (((uint32_t)(x) << EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) +#define EWDG_CTRL0_OT_SELF_CLEAR_GET(x) (((uint32_t)(x) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) >> EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) + +/* + * REF_OT_REQ (RW) + * + * If refresh event has to be limited into a period after refresh unlocked. + * Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter + */ +#define EWDG_CTRL0_REF_OT_REQ_MASK (0x8000U) +#define EWDG_CTRL0_REF_OT_REQ_SHIFT (15U) +#define EWDG_CTRL0_REF_OT_REQ_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_OT_REQ_SHIFT) & EWDG_CTRL0_REF_OT_REQ_MASK) +#define EWDG_CTRL0_REF_OT_REQ_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_OT_REQ_MASK) >> EWDG_CTRL0_REF_OT_REQ_SHIFT) + +/* + * WIN_UPPER (RW) + * + * The upper threshold of window value + * The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value + * If this register value is zero, then no upper level limitation + */ +#define EWDG_CTRL0_WIN_UPPER_MASK (0x7000U) +#define EWDG_CTRL0_WIN_UPPER_SHIFT (12U) +#define EWDG_CTRL0_WIN_UPPER_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_UPPER_SHIFT) & EWDG_CTRL0_WIN_UPPER_MASK) +#define EWDG_CTRL0_WIN_UPPER_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_UPPER_MASK) >> EWDG_CTRL0_WIN_UPPER_SHIFT) + +/* + * REF_LOCK (RW) + * + * WDT refresh has to be unlocked firstly once refresh lock is enable. + */ +#define EWDG_CTRL0_REF_LOCK_MASK (0x20U) +#define EWDG_CTRL0_REF_LOCK_SHIFT (5U) +#define EWDG_CTRL0_REF_LOCK_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_LOCK_SHIFT) & EWDG_CTRL0_REF_LOCK_MASK) +#define EWDG_CTRL0_REF_LOCK_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_LOCK_MASK) >> EWDG_CTRL0_REF_LOCK_SHIFT) + +/* + * REF_UNLOCK_MEC (RW) + * + * Unlock refresh mechanism + * 00: the required unlock password is the same with refresh_psd_register + * 01: the required unlock password is a ring shift left value of refresh_psd_register + * 10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is + * 11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 + */ +#define EWDG_CTRL0_REF_UNLOCK_MEC_MASK (0x18U) +#define EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT (3U) +#define EWDG_CTRL0_REF_UNLOCK_MEC_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) +#define EWDG_CTRL0_REF_UNLOCK_MEC_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) >> EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) + +/* + * EN_DBG (RW) + * + * WTD enable or not in debug mode + */ +#define EWDG_CTRL0_EN_DBG_MASK (0x4U) +#define EWDG_CTRL0_EN_DBG_SHIFT (2U) +#define EWDG_CTRL0_EN_DBG_SET(x) (((uint32_t)(x) << EWDG_CTRL0_EN_DBG_SHIFT) & EWDG_CTRL0_EN_DBG_MASK) +#define EWDG_CTRL0_EN_DBG_GET(x) (((uint32_t)(x) & EWDG_CTRL0_EN_DBG_MASK) >> EWDG_CTRL0_EN_DBG_SHIFT) + +/* + * EN_LP (RW) + * + * WDT enable or not in low power mode + * 2'b00: wdt is halted once in low power mode + * 2'b01: wdt will work with 1/4 normal clock freq in low power mode + * 2'b10: wdt will work with 1/2 normal clock freq in low power mode + * 2'b11: wdt will work with normal clock freq in low power mode + */ +#define EWDG_CTRL0_EN_LP_MASK (0x3U) +#define EWDG_CTRL0_EN_LP_SHIFT (0U) +#define EWDG_CTRL0_EN_LP_SET(x) (((uint32_t)(x) << EWDG_CTRL0_EN_LP_SHIFT) & EWDG_CTRL0_EN_LP_MASK) +#define EWDG_CTRL0_EN_LP_GET(x) (((uint32_t)(x) & EWDG_CTRL0_EN_LP_MASK) >> EWDG_CTRL0_EN_LP_SHIFT) + +/* Bitfield definition for register: CTRL1 */ +/* + * REF_FAIL_RST_EN (RW) + * + * Refresh violation will trigger an reset. + * These event will be taken as a refresh violation: + * 1) Not refresh in the window once window mode is enabled + * 2) Not unlock refresh firstly if unlock is required + * 3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. + * 4) Not write the required word to refresh wdt. + */ +#define EWDG_CTRL1_REF_FAIL_RST_EN_MASK (0x800000UL) +#define EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT (23U) +#define EWDG_CTRL1_REF_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) +#define EWDG_CTRL1_REF_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) + +/* + * REF_FAIL_INT_EN (RW) + * + * Refresh violation will trigger an interrupt + */ +#define EWDG_CTRL1_REF_FAIL_INT_EN_MASK (0x400000UL) +#define EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT (22U) +#define EWDG_CTRL1_REF_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) +#define EWDG_CTRL1_REF_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) + +/* + * UNL_REF_FAIL_RST_EN (RW) + * + * Refresh unlock fail will trigger a reset + */ +#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK (0x200000UL) +#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT (21U) +#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) +#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) + +/* + * UNL_REF_FAIL_INT_EN (RW) + * + * Refresh unlock fail will trigger a interrupt + */ +#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK (0x100000UL) +#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT (20U) +#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) +#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) + +/* + * OT_RST_EN (RW) + * + * WDT overtime will generate a reset + */ +#define EWDG_CTRL1_OT_RST_EN_MASK (0x20000UL) +#define EWDG_CTRL1_OT_RST_EN_SHIFT (17U) +#define EWDG_CTRL1_OT_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_OT_RST_EN_SHIFT) & EWDG_CTRL1_OT_RST_EN_MASK) +#define EWDG_CTRL1_OT_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_OT_RST_EN_MASK) >> EWDG_CTRL1_OT_RST_EN_SHIFT) + +/* + * OT_INT_EN (RW) + * + * WDT can generate an interrupt warning before timeout + */ +#define EWDG_CTRL1_OT_INT_EN_MASK (0x10000UL) +#define EWDG_CTRL1_OT_INT_EN_SHIFT (16U) +#define EWDG_CTRL1_OT_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_OT_INT_EN_SHIFT) & EWDG_CTRL1_OT_INT_EN_MASK) +#define EWDG_CTRL1_OT_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_OT_INT_EN_MASK) >> EWDG_CTRL1_OT_INT_EN_SHIFT) + +/* + * CTL_VIO_RST_EN (RW) + * + * Ctrl update violation will trigger a reset + * The violation event is to try updating the locked register before unlock them + */ +#define EWDG_CTRL1_CTL_VIO_RST_EN_MASK (0x80U) +#define EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT (7U) +#define EWDG_CTRL1_CTL_VIO_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) +#define EWDG_CTRL1_CTL_VIO_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) >> EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) + +/* + * CTL_VIO_INT_EN (RW) + * + * Ctrl update violation will trigger a interrupt + */ +#define EWDG_CTRL1_CTL_VIO_INT_EN_MASK (0x40U) +#define EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT (6U) +#define EWDG_CTRL1_CTL_VIO_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) +#define EWDG_CTRL1_CTL_VIO_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) >> EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) + +/* + * UNL_CTL_FAIL_RST_EN (RW) + * + * Unlock register update failure will trigger a reset + */ +#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK (0x20U) +#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT (5U) +#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) +#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) + +/* + * UNL_CTL_FAIL_INT_EN (RW) + * + * Unlock register update failure will trigger a interrupt + */ +#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK (0x10U) +#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT (4U) +#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) +#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) + +/* + * PARITY_FAIL_RST_EN (RW) + * + * Parity error will trigger a reset + * A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits + */ +#define EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK (0x8U) +#define EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT (3U) +#define EWDG_CTRL1_PARITY_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) +#define EWDG_CTRL1_PARITY_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) + +/* + * PARITY_FAIL_INT_EN (RW) + * + * Parity error will trigger a interrupt + */ +#define EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK (0x4U) +#define EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT (2U) +#define EWDG_CTRL1_PARITY_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) +#define EWDG_CTRL1_PARITY_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) + +/* Bitfield definition for register: OT_INT_VAL */ +/* + * OT_INT_VAL (RW) + * + * WDT timeout interrupt value + */ +#define EWDG_OT_INT_VAL_OT_INT_VAL_MASK (0xFFFFU) +#define EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT (0U) +#define EWDG_OT_INT_VAL_OT_INT_VAL_SET(x) (((uint32_t)(x) << EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK) +#define EWDG_OT_INT_VAL_OT_INT_VAL_GET(x) (((uint32_t)(x) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK) >> EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT) + +/* Bitfield definition for register: OT_RST_VAL */ +/* + * OT_RST_VAL (RW) + * + * WDT timeout reset value + */ +#define EWDG_OT_RST_VAL_OT_RST_VAL_MASK (0xFFFFU) +#define EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT (0U) +#define EWDG_OT_RST_VAL_OT_RST_VAL_SET(x) (((uint32_t)(x) << EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) +#define EWDG_OT_RST_VAL_OT_RST_VAL_GET(x) (((uint32_t)(x) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) >> EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) + +/* Bitfield definition for register: WDT_REFRESH_REG */ +/* + * WDT_REFRESH_REG (WO) + * + * Write this register by 32'h5A45_524F to refresh wdog + * Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose + */ +#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK (0xFFFFFFFFUL) +#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT (0U) +#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SET(x) (((uint32_t)(x) << EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) +#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_GET(x) (((uint32_t)(x) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) >> EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) + +/* Bitfield definition for register: WDT_STATUS */ +/* + * PARITY_ERROR (RW) + * + * parity error + * Write one to clear the bit + */ +#define EWDG_WDT_STATUS_PARITY_ERROR_MASK (0x40U) +#define EWDG_WDT_STATUS_PARITY_ERROR_SHIFT (6U) +#define EWDG_WDT_STATUS_PARITY_ERROR_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) +#define EWDG_WDT_STATUS_PARITY_ERROR_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) >> EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) + +/* + * OT_RST (RO) + * + * Timeout happens, a reset will happen once enable bit set + * This bit can be cleared only by refreshing wdt or reset + */ +#define EWDG_WDT_STATUS_OT_RST_MASK (0x20U) +#define EWDG_WDT_STATUS_OT_RST_SHIFT (5U) +#define EWDG_WDT_STATUS_OT_RST_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_OT_RST_MASK) >> EWDG_WDT_STATUS_OT_RST_SHIFT) + +/* + * OT_INT (RO) + * + * Timeout happens, a interrupt will happen once enable bit set + * This bit can be cleared only by refreshing wdt or reset + */ +#define EWDG_WDT_STATUS_OT_INT_MASK (0x10U) +#define EWDG_WDT_STATUS_OT_INT_SHIFT (4U) +#define EWDG_WDT_STATUS_OT_INT_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_OT_INT_MASK) >> EWDG_WDT_STATUS_OT_INT_SHIFT) + +/* + * CTL_UNL_FAIL (RW) + * + * Unlock ctrl reg update protection fail + * Write one to clear the bit + */ +#define EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK (0x8U) +#define EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT (3U) +#define EWDG_WDT_STATUS_CTL_UNL_FAIL_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) +#define EWDG_WDT_STATUS_CTL_UNL_FAIL_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) + +/* + * CTL_VIO (RW) + * + * Violate register update protection mechanism + * Write one to clear the bit + */ +#define EWDG_WDT_STATUS_CTL_VIO_MASK (0x4U) +#define EWDG_WDT_STATUS_CTL_VIO_SHIFT (2U) +#define EWDG_WDT_STATUS_CTL_VIO_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_VIO_SHIFT) & EWDG_WDT_STATUS_CTL_VIO_MASK) +#define EWDG_WDT_STATUS_CTL_VIO_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_VIO_MASK) >> EWDG_WDT_STATUS_CTL_VIO_SHIFT) + +/* + * REF_UNL_FAIL (RW) + * + * Refresh unlock fail + * Write one to clear the bit + */ +#define EWDG_WDT_STATUS_REF_UNL_FAIL_MASK (0x2U) +#define EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT (1U) +#define EWDG_WDT_STATUS_REF_UNL_FAIL_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) +#define EWDG_WDT_STATUS_REF_UNL_FAIL_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) + +/* + * REF_VIO (RW) + * + * Refresh fail + * Write one to clear the bit + */ +#define EWDG_WDT_STATUS_REF_VIO_MASK (0x1U) +#define EWDG_WDT_STATUS_REF_VIO_SHIFT (0U) +#define EWDG_WDT_STATUS_REF_VIO_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_REF_VIO_SHIFT) & EWDG_WDT_STATUS_REF_VIO_MASK) +#define EWDG_WDT_STATUS_REF_VIO_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_REF_VIO_MASK) >> EWDG_WDT_STATUS_REF_VIO_SHIFT) + +/* Bitfield definition for register: CFG_PROT */ +/* + * UPD_OT_TIME (RW) + * + * The period in which register update has to be in after unlock + * The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle + */ +#define EWDG_CFG_PROT_UPD_OT_TIME_MASK (0xF0000UL) +#define EWDG_CFG_PROT_UPD_OT_TIME_SHIFT (16U) +#define EWDG_CFG_PROT_UPD_OT_TIME_SET(x) (((uint32_t)(x) << EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) +#define EWDG_CFG_PROT_UPD_OT_TIME_GET(x) (((uint32_t)(x) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) >> EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) + +/* + * UPD_PSD (RW) + * + * The password of unlocking register update + */ +#define EWDG_CFG_PROT_UPD_PSD_MASK (0xFFFFU) +#define EWDG_CFG_PROT_UPD_PSD_SHIFT (0U) +#define EWDG_CFG_PROT_UPD_PSD_SET(x) (((uint32_t)(x) << EWDG_CFG_PROT_UPD_PSD_SHIFT) & EWDG_CFG_PROT_UPD_PSD_MASK) +#define EWDG_CFG_PROT_UPD_PSD_GET(x) (((uint32_t)(x) & EWDG_CFG_PROT_UPD_PSD_MASK) >> EWDG_CFG_PROT_UPD_PSD_SHIFT) + +/* Bitfield definition for register: REF_PROT */ +/* + * REF_UNL_PSD (RW) + * + * The password to unlock refreshing + */ +#define EWDG_REF_PROT_REF_UNL_PSD_MASK (0xFFFFU) +#define EWDG_REF_PROT_REF_UNL_PSD_SHIFT (0U) +#define EWDG_REF_PROT_REF_UNL_PSD_SET(x) (((uint32_t)(x) << EWDG_REF_PROT_REF_UNL_PSD_SHIFT) & EWDG_REF_PROT_REF_UNL_PSD_MASK) +#define EWDG_REF_PROT_REF_UNL_PSD_GET(x) (((uint32_t)(x) & EWDG_REF_PROT_REF_UNL_PSD_MASK) >> EWDG_REF_PROT_REF_UNL_PSD_SHIFT) + +/* Bitfield definition for register: WDT_EN */ +/* + * WDOG_EN (RW) + * + * Wdog is enabled, the re-written of this register is impacted by enable lock function + */ +#define EWDG_WDT_EN_WDOG_EN_MASK (0x1U) +#define EWDG_WDT_EN_WDOG_EN_SHIFT (0U) +#define EWDG_WDT_EN_WDOG_EN_SET(x) (((uint32_t)(x) << EWDG_WDT_EN_WDOG_EN_SHIFT) & EWDG_WDT_EN_WDOG_EN_MASK) +#define EWDG_WDT_EN_WDOG_EN_GET(x) (((uint32_t)(x) & EWDG_WDT_EN_WDOG_EN_MASK) >> EWDG_WDT_EN_WDOG_EN_SHIFT) + +/* Bitfield definition for register: REF_TIME */ +/* + * REFRESH_PERIOD (RW) + * + * The refresh period after refresh unlocked + * Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter + */ +#define EWDG_REF_TIME_REFRESH_PERIOD_MASK (0xFFFFU) +#define EWDG_REF_TIME_REFRESH_PERIOD_SHIFT (0U) +#define EWDG_REF_TIME_REFRESH_PERIOD_SET(x) (((uint32_t)(x) << EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) +#define EWDG_REF_TIME_REFRESH_PERIOD_GET(x) (((uint32_t)(x) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) >> EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) + + + + +#endif /* HPM_EWDG_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h index 160bc374..71dae5bb 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h @@ -11,7 +11,7 @@ typedef struct { __RW uint32_t CTRL; /* 0x0: */ - __R uint32_t STATUS; /* 0x4: */ + __RW uint32_t STATUS; /* 0x4: */ __RW uint32_t INT_EN; /* 0x8: */ __R uint8_t RESERVED0[20]; /* 0xC - 0x1F: Reserved */ __RW uint32_t OP_CTRL; /* 0x20: */ @@ -71,66 +71,73 @@ typedef struct { /* Bitfield definition for register: STATUS */ /* - * FIR_OV (RO) + * FIR_OV (W1C) * * FIR Overflow err */ #define FFA_STATUS_FIR_OV_MASK (0x80U) #define FFA_STATUS_FIR_OV_SHIFT (7U) +#define FFA_STATUS_FIR_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FIR_OV_SHIFT) & FFA_STATUS_FIR_OV_MASK) #define FFA_STATUS_FIR_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FIR_OV_MASK) >> FFA_STATUS_FIR_OV_SHIFT) /* - * FFT_OV (RO) + * FFT_OV (W1C) * * FFT Overflow Err */ #define FFA_STATUS_FFT_OV_MASK (0x40U) #define FFA_STATUS_FFT_OV_SHIFT (6U) +#define FFA_STATUS_FFT_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FFT_OV_SHIFT) & FFA_STATUS_FFT_OV_MASK) #define FFA_STATUS_FFT_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FFT_OV_MASK) >> FFA_STATUS_FFT_OV_SHIFT) /* - * WR_ERR (RO) + * WR_ERR (W1C) * * AXI Data Write Error */ #define FFA_STATUS_WR_ERR_MASK (0x20U) #define FFA_STATUS_WR_ERR_SHIFT (5U) +#define FFA_STATUS_WR_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_WR_ERR_SHIFT) & FFA_STATUS_WR_ERR_MASK) #define FFA_STATUS_WR_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_WR_ERR_MASK) >> FFA_STATUS_WR_ERR_SHIFT) /* - * RD_NXT_ERR (RO) + * RD_NXT_ERR (W1C) * * AXI Read Bus Error for NXT DATA */ #define FFA_STATUS_RD_NXT_ERR_MASK (0x10U) #define FFA_STATUS_RD_NXT_ERR_SHIFT (4U) +#define FFA_STATUS_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_NXT_ERR_SHIFT) & FFA_STATUS_RD_NXT_ERR_MASK) #define FFA_STATUS_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_NXT_ERR_MASK) >> FFA_STATUS_RD_NXT_ERR_SHIFT) /* - * RD_ERR (RO) + * RD_ERR (W1C) * * AXI Data Read Error */ #define FFA_STATUS_RD_ERR_MASK (0x8U) #define FFA_STATUS_RD_ERR_SHIFT (3U) +#define FFA_STATUS_RD_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_ERR_SHIFT) & FFA_STATUS_RD_ERR_MASK) #define FFA_STATUS_RD_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_ERR_MASK) >> FFA_STATUS_RD_ERR_SHIFT) /* - * NXT_CMD_RD_DONE (RO) + * NXT_CMD_RD_DONE (W1C) * * Indicate that next command sequence is already read into the module. */ #define FFA_STATUS_NXT_CMD_RD_DONE_MASK (0x2U) #define FFA_STATUS_NXT_CMD_RD_DONE_SHIFT (1U) +#define FFA_STATUS_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) #define FFA_STATUS_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) >> FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) /* - * OP_CMD_DONE (RO) + * OP_CMD_DONE (W1C) * * Indicate that operation cmd is done, and data are available in system memory. */ #define FFA_STATUS_OP_CMD_DONE_MASK (0x1U) #define FFA_STATUS_OP_CMD_DONE_SHIFT (0U) +#define FFA_STATUS_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_OP_CMD_DONE_SHIFT) & FFA_STATUS_OP_CMD_DONE_MASK) #define FFA_STATUS_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_OP_CMD_DONE_MASK) >> FFA_STATUS_OP_CMD_DONE_SHIFT) /* Bitfield definition for register: INT_EN */ @@ -557,4 +564,4 @@ typedef struct { -#endif /* HPM_FFA_H */ \ No newline at end of file +#endif /* HPM_FFA_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h index eb2764d4..0d5eb242 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h @@ -54,6 +54,12 @@ typedef struct { __RW uint32_t CLEAR; /* 0x708: GPIO interrupt asynchronous clear */ __RW uint32_t TOGGLE; /* 0x70C: GPIO interrupt asynchronous toggle */ } AS[16]; + struct { + __RW uint32_t VALUE; /* 0x800: GPIO dual edge interrupt enable value */ + __RW uint32_t SET; /* 0x804: GPIO dual edge interrupt enable set */ + __RW uint32_t CLEAR; /* 0x808: GPIO dual edge interrupt enable clear */ + __RW uint32_t TOGGLE; /* 0x80C: GPIO dual edge interrupt enable toggle */ + } PD[16]; } GPIO_Type; @@ -398,6 +404,58 @@ typedef struct { #define GPIO_AS_TOGGLE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) #define GPIO_AS_TOGGLE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) >> GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) +/* Bitfield definition for register of struct array PD: VALUE */ +/* + * IRQ_DUAL (RW) + * + * GPIO dual edge interrupt enable + * 0: single edge interrupt + * 1: dual edge interrupt enable + */ +#define GPIO_PD_VALUE_IRQ_DUAL_MASK (0x1U) +#define GPIO_PD_VALUE_IRQ_DUAL_SHIFT (0U) +#define GPIO_PD_VALUE_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_VALUE_IRQ_DUAL_SHIFT) & GPIO_PD_VALUE_IRQ_DUAL_MASK) +#define GPIO_PD_VALUE_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_VALUE_IRQ_DUAL_MASK) >> GPIO_PD_VALUE_IRQ_DUAL_SHIFT) + +/* Bitfield definition for register of struct array PD: SET */ +/* + * IRQ_DUAL (RW) + * + * GPIO dual edge interrupt enable set + * 0: keep original edge interrupt type + * 1: dual edge interrupt enable + */ +#define GPIO_PD_SET_IRQ_DUAL_MASK (0x1U) +#define GPIO_PD_SET_IRQ_DUAL_SHIFT (0U) +#define GPIO_PD_SET_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_SET_IRQ_DUAL_SHIFT) & GPIO_PD_SET_IRQ_DUAL_MASK) +#define GPIO_PD_SET_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_SET_IRQ_DUAL_MASK) >> GPIO_PD_SET_IRQ_DUAL_SHIFT) + +/* Bitfield definition for register of struct array PD: CLEAR */ +/* + * IRQ_DUAL (RW) + * + * GPIO dual edge interrupt enable clear + * 0: keep original edge interrupt type + * 1: single edge interrupt enable + */ +#define GPIO_PD_CLEAR_IRQ_DUAL_MASK (0x1U) +#define GPIO_PD_CLEAR_IRQ_DUAL_SHIFT (0U) +#define GPIO_PD_CLEAR_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_CLEAR_IRQ_DUAL_SHIFT) & GPIO_PD_CLEAR_IRQ_DUAL_MASK) +#define GPIO_PD_CLEAR_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_CLEAR_IRQ_DUAL_MASK) >> GPIO_PD_CLEAR_IRQ_DUAL_SHIFT) + +/* Bitfield definition for register of struct array PD: TOGGLE */ +/* + * IRQ_DUAL (RW) + * + * GPIO dual edge interrupt enable toggle + * 0: keep original edge interrupt type + * 1: change original edge interrupt type to another one. + */ +#define GPIO_PD_TOGGLE_IRQ_DUAL_MASK (0x1U) +#define GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT (0U) +#define GPIO_PD_TOGGLE_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT) & GPIO_PD_TOGGLE_IRQ_DUAL_MASK) +#define GPIO_PD_TOGGLE_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_TOGGLE_IRQ_DUAL_MASK) >> GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT) + /* DI register group index macro definition */ @@ -488,5 +546,16 @@ typedef struct { #define GPIO_AS_GPIOY (14UL) #define GPIO_AS_GPIOZ (15UL) +/* PD register group index macro definition */ +#define GPIO_PD_GPIOA (0UL) +#define GPIO_PD_GPIOB (1UL) +#define GPIO_PD_GPIOC (2UL) +#define GPIO_PD_GPIOD (3UL) +#define GPIO_PD_GPIOE (4UL) +#define GPIO_PD_GPIOF (5UL) +#define GPIO_PD_GPIOX (13UL) +#define GPIO_PD_GPIOY (14UL) +#define GPIO_PD_GPIOZ (15UL) + -#endif /* HPM_GPIO_H */ \ No newline at end of file +#endif /* HPM_GPIO_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h index 15a08af3..0e06f89a 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h @@ -588,4 +588,4 @@ typedef struct { #define I2S_TXDSLOT_DATA3 (3UL) -#endif /* HPM_I2S_H */ \ No newline at end of file +#endif /* HPM_I2S_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h index 3a50c8ff..36a94732 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h @@ -888,7 +888,7 @@ typedef struct { * 0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. * 0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. * 0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. - * 0100b - 16 bpp (RGB565), byte sequence as B,R + * 0100b - 16 bpp (RGB565), the low byte contains teh full R component. * 0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] * 1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A * 1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_linv2_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_linv2_regs.h new file mode 100644 index 00000000..d8f94b68 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_linv2_regs.h @@ -0,0 +1,466 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_LINV2_H +#define HPM_LINV2_H + +typedef struct { + union { + __RW uint32_t DATA[2]; /* 0x0 - 0x4: data byte */ + __RW uint8_t DATA_BYTE[8]; /* 0x0 - 0x7: */ + }; + __RW uint32_t DATA_LEN_ID; /* 0x8: data length and ID register */ + __RW uint32_t CONTROL_STATUS; /* 0xC: control and status register */ + __RW uint32_t TIMING_CONTROL; /* 0x10: timing control register */ + __RW uint32_t DMA_CONTROL; /* 0x14: dma control register */ +} LINV2_Type; + + +/* Bitfield definition for register: DATA0 */ +/* + * DATA (RW) + * + * data + */ +#define LINV2_DATA_DATA_MASK (0xFFFFFFFFUL) +#define LINV2_DATA_DATA_SHIFT (0U) +#define LINV2_DATA_DATA_SET(x) (((uint32_t)(x) << LINV2_DATA_DATA_SHIFT) & LINV2_DATA_DATA_MASK) +#define LINV2_DATA_DATA_GET(x) (((uint32_t)(x) & LINV2_DATA_DATA_MASK) >> LINV2_DATA_DATA_SHIFT) + +/* Bitfield definition for register: DATA_BYTE0 */ +/* + * DATA_BYTE (RW) + * + * data byte + */ +#define LINV2_DATA_BYTE_DATA_BYTE_MASK (0xFFU) +#define LINV2_DATA_BYTE_DATA_BYTE_SHIFT (0U) +#define LINV2_DATA_BYTE_DATA_BYTE_SET(x) (((uint8_t)(x) << LINV2_DATA_BYTE_DATA_BYTE_SHIFT) & LINV2_DATA_BYTE_DATA_BYTE_MASK) +#define LINV2_DATA_BYTE_DATA_BYTE_GET(x) (((uint8_t)(x) & LINV2_DATA_BYTE_DATA_BYTE_MASK) >> LINV2_DATA_BYTE_DATA_BYTE_SHIFT) + +/* Bitfield definition for register: DATA_LEN_ID */ +/* + * CHECKSUM (RO) + * + */ +#define LINV2_DATA_LEN_ID_CHECKSUM_MASK (0xFF0000UL) +#define LINV2_DATA_LEN_ID_CHECKSUM_SHIFT (16U) +#define LINV2_DATA_LEN_ID_CHECKSUM_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_CHECKSUM_MASK) >> LINV2_DATA_LEN_ID_CHECKSUM_SHIFT) + +/* + * ID_PARITY (RO) + * + */ +#define LINV2_DATA_LEN_ID_ID_PARITY_MASK (0xC000U) +#define LINV2_DATA_LEN_ID_ID_PARITY_SHIFT (14U) +#define LINV2_DATA_LEN_ID_ID_PARITY_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_ID_PARITY_MASK) >> LINV2_DATA_LEN_ID_ID_PARITY_SHIFT) + +/* + * ID (RW) + * + * ID register + */ +#define LINV2_DATA_LEN_ID_ID_MASK (0x3F00U) +#define LINV2_DATA_LEN_ID_ID_SHIFT (8U) +#define LINV2_DATA_LEN_ID_ID_SET(x) (((uint32_t)(x) << LINV2_DATA_LEN_ID_ID_SHIFT) & LINV2_DATA_LEN_ID_ID_MASK) +#define LINV2_DATA_LEN_ID_ID_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_ID_MASK) >> LINV2_DATA_LEN_ID_ID_SHIFT) + +/* + * ENH_CHECK (RW) + * + * 1:enhance check mode 0:classical check mode + */ +#define LINV2_DATA_LEN_ID_ENH_CHECK_MASK (0x80U) +#define LINV2_DATA_LEN_ID_ENH_CHECK_SHIFT (7U) +#define LINV2_DATA_LEN_ID_ENH_CHECK_SET(x) (((uint32_t)(x) << LINV2_DATA_LEN_ID_ENH_CHECK_SHIFT) & LINV2_DATA_LEN_ID_ENH_CHECK_MASK) +#define LINV2_DATA_LEN_ID_ENH_CHECK_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_ENH_CHECK_MASK) >> LINV2_DATA_LEN_ID_ENH_CHECK_SHIFT) + +/* + * DATA_LEN (RW) + * + * payload data length control register。The data length will decoded from ID[5:4] when all 1 is configured: 00-2 01-2 10-4 11-8 + */ +#define LINV2_DATA_LEN_ID_DATA_LEN_MASK (0xFU) +#define LINV2_DATA_LEN_ID_DATA_LEN_SHIFT (0U) +#define LINV2_DATA_LEN_ID_DATA_LEN_SET(x) (((uint32_t)(x) << LINV2_DATA_LEN_ID_DATA_LEN_SHIFT) & LINV2_DATA_LEN_ID_DATA_LEN_MASK) +#define LINV2_DATA_LEN_ID_DATA_LEN_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_DATA_LEN_MASK) >> LINV2_DATA_LEN_ID_DATA_LEN_SHIFT) + +/* Bitfield definition for register: CONTROL_STATUS */ +/* + * BREAK_ERR_DIS (RW) + * + */ +#define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK (0x200000UL) +#define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SHIFT (21U) +#define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SHIFT) & LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK) +#define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK) >> LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SHIFT) + +/* + * BREAK_ERR (RO) + * + */ +#define LINV2_CONTROL_STATUS_BREAK_ERR_MASK (0x100000UL) +#define LINV2_CONTROL_STATUS_BREAK_ERR_SHIFT (20U) +#define LINV2_CONTROL_STATUS_BREAK_ERR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BREAK_ERR_MASK) >> LINV2_CONTROL_STATUS_BREAK_ERR_SHIFT) + +/* + * PARITY_ERROR (RO) + * + * slave only. identifier parity error + */ +#define LINV2_CONTROL_STATUS_PARITY_ERROR_MASK (0x80000UL) +#define LINV2_CONTROL_STATUS_PARITY_ERROR_SHIFT (19U) +#define LINV2_CONTROL_STATUS_PARITY_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_PARITY_ERROR_MASK) >> LINV2_CONTROL_STATUS_PARITY_ERROR_SHIFT) + +/* + * TIME_OUT (RO) + * + * timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms + */ +#define LINV2_CONTROL_STATUS_TIME_OUT_MASK (0x40000UL) +#define LINV2_CONTROL_STATUS_TIME_OUT_SHIFT (18U) +#define LINV2_CONTROL_STATUS_TIME_OUT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_TIME_OUT_MASK) >> LINV2_CONTROL_STATUS_TIME_OUT_SHIFT) + +/* + * CHK_ERROR (RO) + * + * checksum error + */ +#define LINV2_CONTROL_STATUS_CHK_ERROR_MASK (0x20000UL) +#define LINV2_CONTROL_STATUS_CHK_ERROR_SHIFT (17U) +#define LINV2_CONTROL_STATUS_CHK_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_CHK_ERROR_MASK) >> LINV2_CONTROL_STATUS_CHK_ERROR_SHIFT) + +/* + * BIT_ERROR (RO) + * + * bit error + */ +#define LINV2_CONTROL_STATUS_BIT_ERROR_MASK (0x10000UL) +#define LINV2_CONTROL_STATUS_BIT_ERROR_SHIFT (16U) +#define LINV2_CONTROL_STATUS_BIT_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BIT_ERROR_MASK) >> LINV2_CONTROL_STATUS_BIT_ERROR_SHIFT) + +/* + * LIN_ACTIVE (RO) + * + * The bit indicates whether the LIN bus is active or not + */ +#define LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK (0x8000U) +#define LINV2_CONTROL_STATUS_LIN_ACTIVE_SHIFT (15U) +#define LINV2_CONTROL_STATUS_LIN_ACTIVE_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK) >> LINV2_CONTROL_STATUS_LIN_ACTIVE_SHIFT) + +/* + * BUS_IDLE_TIMEOUT (RO) + * + * slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s + */ +#define LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_MASK (0x4000U) +#define LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_SHIFT (14U) +#define LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_MASK) >> LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_SHIFT) + +/* + * ABORTED (RO) + * + * slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error. + */ +#define LINV2_CONTROL_STATUS_ABORTED_MASK (0x2000U) +#define LINV2_CONTROL_STATUS_ABORTED_SHIFT (13U) +#define LINV2_CONTROL_STATUS_ABORTED_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_ABORTED_MASK) >> LINV2_CONTROL_STATUS_ABORTED_SHIFT) + +/* + * DATA_REQ (RO) + * + * slave only. Sets after receiving the identifier and requests an interrupt to the host controller. + */ +#define LINV2_CONTROL_STATUS_DATA_REQ_MASK (0x1000U) +#define LINV2_CONTROL_STATUS_DATA_REQ_SHIFT (12U) +#define LINV2_CONTROL_STATUS_DATA_REQ_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_DATA_REQ_MASK) >> LINV2_CONTROL_STATUS_DATA_REQ_SHIFT) + +/* + * INT (RO) + * + * set when request an interrupt. Reset by reset_int + */ +#define LINV2_CONTROL_STATUS_INT_MASK (0x800U) +#define LINV2_CONTROL_STATUS_INT_SHIFT (11U) +#define LINV2_CONTROL_STATUS_INT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_INT_MASK) >> LINV2_CONTROL_STATUS_INT_SHIFT) + +/* + * ERROR (RO) + * + * set when detecte an error, clear by reset_error + */ +#define LINV2_CONTROL_STATUS_ERROR_MASK (0x400U) +#define LINV2_CONTROL_STATUS_ERROR_SHIFT (10U) +#define LINV2_CONTROL_STATUS_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_ERROR_MASK) >> LINV2_CONTROL_STATUS_ERROR_SHIFT) + +/* + * WAKEUP (RO) + * + * set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1 + */ +#define LINV2_CONTROL_STATUS_WAKEUP_MASK (0x200U) +#define LINV2_CONTROL_STATUS_WAKEUP_SHIFT (9U) +#define LINV2_CONTROL_STATUS_WAKEUP_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_WAKEUP_MASK) >> LINV2_CONTROL_STATUS_WAKEUP_SHIFT) + +/* + * COMPLETE (RO) + * + * set after a transmission has been successful finished and it will reset at the start of a transmission. + */ +#define LINV2_CONTROL_STATUS_COMPLETE_MASK (0x100U) +#define LINV2_CONTROL_STATUS_COMPLETE_SHIFT (8U) +#define LINV2_CONTROL_STATUS_COMPLETE_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_COMPLETE_MASK) >> LINV2_CONTROL_STATUS_COMPLETE_SHIFT) + +/* + * STOP (WO) + * + * slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID + */ +#define LINV2_CONTROL_STATUS_STOP_MASK (0x80U) +#define LINV2_CONTROL_STATUS_STOP_SHIFT (7U) +#define LINV2_CONTROL_STATUS_STOP_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_STOP_SHIFT) & LINV2_CONTROL_STATUS_STOP_MASK) +#define LINV2_CONTROL_STATUS_STOP_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_STOP_MASK) >> LINV2_CONTROL_STATUS_STOP_SHIFT) + +/* + * SLEEP (RW) + * + * The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core. + */ +#define LINV2_CONTROL_STATUS_SLEEP_MASK (0x40U) +#define LINV2_CONTROL_STATUS_SLEEP_SHIFT (6U) +#define LINV2_CONTROL_STATUS_SLEEP_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_SLEEP_SHIFT) & LINV2_CONTROL_STATUS_SLEEP_MASK) +#define LINV2_CONTROL_STATUS_SLEEP_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_SLEEP_MASK) >> LINV2_CONTROL_STATUS_SLEEP_SHIFT) + +/* + * TRANSMIT (RW) + * + * 1: transmit operation 0: receive operation + */ +#define LINV2_CONTROL_STATUS_TRANSMIT_MASK (0x20U) +#define LINV2_CONTROL_STATUS_TRANSMIT_SHIFT (5U) +#define LINV2_CONTROL_STATUS_TRANSMIT_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_TRANSMIT_SHIFT) & LINV2_CONTROL_STATUS_TRANSMIT_MASK) +#define LINV2_CONTROL_STATUS_TRANSMIT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_TRANSMIT_MASK) >> LINV2_CONTROL_STATUS_TRANSMIT_SHIFT) + +/* + * DATA_ACK (RW) + * + * slave only. Write 1 after handling a data request interrupt + */ +#define LINV2_CONTROL_STATUS_DATA_ACK_MASK (0x10U) +#define LINV2_CONTROL_STATUS_DATA_ACK_SHIFT (4U) +#define LINV2_CONTROL_STATUS_DATA_ACK_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_DATA_ACK_SHIFT) & LINV2_CONTROL_STATUS_DATA_ACK_MASK) +#define LINV2_CONTROL_STATUS_DATA_ACK_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_DATA_ACK_MASK) >> LINV2_CONTROL_STATUS_DATA_ACK_SHIFT) + +/* + * RESET_INT (WO) + * + * set 1 will clear the int register + */ +#define LINV2_CONTROL_STATUS_RESET_INT_MASK (0x8U) +#define LINV2_CONTROL_STATUS_RESET_INT_SHIFT (3U) +#define LINV2_CONTROL_STATUS_RESET_INT_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_RESET_INT_SHIFT) & LINV2_CONTROL_STATUS_RESET_INT_MASK) +#define LINV2_CONTROL_STATUS_RESET_INT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_RESET_INT_MASK) >> LINV2_CONTROL_STATUS_RESET_INT_SHIFT) + +/* + * RESET_ERROR (WO) + * + * set 1 will clear the error register, and also the timeout/complete/wakeup register + */ +#define LINV2_CONTROL_STATUS_RESET_ERROR_MASK (0x4U) +#define LINV2_CONTROL_STATUS_RESET_ERROR_SHIFT (2U) +#define LINV2_CONTROL_STATUS_RESET_ERROR_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_RESET_ERROR_SHIFT) & LINV2_CONTROL_STATUS_RESET_ERROR_MASK) +#define LINV2_CONTROL_STATUS_RESET_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_RESET_ERROR_MASK) >> LINV2_CONTROL_STATUS_RESET_ERROR_SHIFT) + +/* + * WAKEUP_REQ (RW) + * + * set 1 will make LIN bus exit sleep mode, the bit auto cleared after a wakeup signal has been complete + */ +#define LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK (0x2U) +#define LINV2_CONTROL_STATUS_WAKEUP_REQ_SHIFT (1U) +#define LINV2_CONTROL_STATUS_WAKEUP_REQ_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_WAKEUP_REQ_SHIFT) & LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK) +#define LINV2_CONTROL_STATUS_WAKEUP_REQ_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK) >> LINV2_CONTROL_STATUS_WAKEUP_REQ_SHIFT) + +/* + * START_REQ (RW) + * + * master only. Set 1 will start lin transmission, the bit will be auto cleared when an error occur or the trasmission complete + */ +#define LINV2_CONTROL_STATUS_START_REQ_MASK (0x1U) +#define LINV2_CONTROL_STATUS_START_REQ_SHIFT (0U) +#define LINV2_CONTROL_STATUS_START_REQ_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_START_REQ_SHIFT) & LINV2_CONTROL_STATUS_START_REQ_MASK) +#define LINV2_CONTROL_STATUS_START_REQ_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_START_REQ_MASK) >> LINV2_CONTROL_STATUS_START_REQ_SHIFT) + +/* Bitfield definition for register: TIMING_CONTROL */ +/* + * WAKE_LEN (RW) + * + */ +#define LINV2_TIMING_CONTROL_WAKE_LEN_MASK (0x38000000UL) +#define LINV2_TIMING_CONTROL_WAKE_LEN_SHIFT (27U) +#define LINV2_TIMING_CONTROL_WAKE_LEN_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_WAKE_LEN_SHIFT) & LINV2_TIMING_CONTROL_WAKE_LEN_MASK) +#define LINV2_TIMING_CONTROL_WAKE_LEN_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_WAKE_LEN_MASK) >> LINV2_TIMING_CONTROL_WAKE_LEN_SHIFT) + +/* + * BRK_LEN (RW) + * + */ +#define LINV2_TIMING_CONTROL_BRK_LEN_MASK (0x7000000UL) +#define LINV2_TIMING_CONTROL_BRK_LEN_SHIFT (24U) +#define LINV2_TIMING_CONTROL_BRK_LEN_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BRK_LEN_SHIFT) & LINV2_TIMING_CONTROL_BRK_LEN_MASK) +#define LINV2_TIMING_CONTROL_BRK_LEN_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BRK_LEN_MASK) >> LINV2_TIMING_CONTROL_BRK_LEN_SHIFT) + +/* + * LINBUSDISABLE (RW) + * + * 1：lin rx is disable + */ +#define LINV2_TIMING_CONTROL_LINBUSDISABLE_MASK (0x400000UL) +#define LINV2_TIMING_CONTROL_LINBUSDISABLE_SHIFT (22U) +#define LINV2_TIMING_CONTROL_LINBUSDISABLE_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_LINBUSDISABLE_SHIFT) & LINV2_TIMING_CONTROL_LINBUSDISABLE_MASK) +#define LINV2_TIMING_CONTROL_LINBUSDISABLE_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_LINBUSDISABLE_MASK) >> LINV2_TIMING_CONTROL_LINBUSDISABLE_SHIFT) + +/* + * LIN_INITIAL (RW) + * + * 1:initial lin controller + */ +#define LINV2_TIMING_CONTROL_LIN_INITIAL_MASK (0x200000UL) +#define LINV2_TIMING_CONTROL_LIN_INITIAL_SHIFT (21U) +#define LINV2_TIMING_CONTROL_LIN_INITIAL_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_LIN_INITIAL_SHIFT) & LINV2_TIMING_CONTROL_LIN_INITIAL_MASK) +#define LINV2_TIMING_CONTROL_LIN_INITIAL_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_LIN_INITIAL_MASK) >> LINV2_TIMING_CONTROL_LIN_INITIAL_SHIFT) + +/* + * MASTER_MODE (RW) + * + * 1：master mode + */ +#define LINV2_TIMING_CONTROL_MASTER_MODE_MASK (0x100000UL) +#define LINV2_TIMING_CONTROL_MASTER_MODE_SHIFT (20U) +#define LINV2_TIMING_CONTROL_MASTER_MODE_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_MASTER_MODE_SHIFT) & LINV2_TIMING_CONTROL_MASTER_MODE_MASK) +#define LINV2_TIMING_CONTROL_MASTER_MODE_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_MASTER_MODE_MASK) >> LINV2_TIMING_CONTROL_MASTER_MODE_SHIFT) + +/* + * BUS_INACTIVE_TIME (RW) + * + * slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s + */ +#define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK (0xC0000UL) +#define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SHIFT (18U) +#define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SHIFT) & LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK) +#define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK) >> LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SHIFT) + +/* + * WUP_REPEAT_TIME (RW) + * + * slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms + */ +#define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK (0x30000UL) +#define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SHIFT (16U) +#define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SHIFT) & LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK) +#define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK) >> LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SHIFT) + +/* + * PRESCL (RW) + * + * prescl register + */ +#define LINV2_TIMING_CONTROL_PRESCL_MASK (0xC000U) +#define LINV2_TIMING_CONTROL_PRESCL_SHIFT (14U) +#define LINV2_TIMING_CONTROL_PRESCL_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_PRESCL_SHIFT) & LINV2_TIMING_CONTROL_PRESCL_MASK) +#define LINV2_TIMING_CONTROL_PRESCL_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_PRESCL_MASK) >> LINV2_TIMING_CONTROL_PRESCL_SHIFT) + +/* + * BT_MUL (RW) + * + * bt_mul register + */ +#define LINV2_TIMING_CONTROL_BT_MUL_MASK (0x3E00U) +#define LINV2_TIMING_CONTROL_BT_MUL_SHIFT (9U) +#define LINV2_TIMING_CONTROL_BT_MUL_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BT_MUL_SHIFT) & LINV2_TIMING_CONTROL_BT_MUL_MASK) +#define LINV2_TIMING_CONTROL_BT_MUL_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BT_MUL_MASK) >> LINV2_TIMING_CONTROL_BT_MUL_SHIFT) + +/* + * BT_DIV (RW) + * + * bt_div register + */ +#define LINV2_TIMING_CONTROL_BT_DIV_MASK (0x1FFU) +#define LINV2_TIMING_CONTROL_BT_DIV_SHIFT (0U) +#define LINV2_TIMING_CONTROL_BT_DIV_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BT_DIV_SHIFT) & LINV2_TIMING_CONTROL_BT_DIV_MASK) +#define LINV2_TIMING_CONTROL_BT_DIV_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BT_DIV_MASK) >> LINV2_TIMING_CONTROL_BT_DIV_SHIFT) + +/* Bitfield definition for register: DMA_CONTROL */ +/* + * DMA_REQ_ENH_CHK (RW) + * + * payload data checksum type for dma operation + */ +#define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_MASK (0x1000U) +#define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SHIFT (12U) +#define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_MASK) +#define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SHIFT) + +/* + * DMA_REQ_LEN (RW) + * + * paylaod length for dma request + */ +#define LINV2_DMA_CONTROL_DMA_REQ_LEN_MASK (0xF00U) +#define LINV2_DMA_CONTROL_DMA_REQ_LEN_SHIFT (8U) +#define LINV2_DMA_CONTROL_DMA_REQ_LEN_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_LEN_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_LEN_MASK) +#define LINV2_DMA_CONTROL_DMA_REQ_LEN_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_LEN_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_LEN_SHIFT) + +/* + * DMA_REQ_ID_TYPE (RW) + * + * 1：transmite 0：receive + */ +#define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_MASK (0x80U) +#define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SHIFT (7U) +#define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_MASK) +#define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SHIFT) + +/* + * DMA_REQ_ID (RW) + * + * dma_req_id register + */ +#define LINV2_DMA_CONTROL_DMA_REQ_ID_MASK (0x7EU) +#define LINV2_DMA_CONTROL_DMA_REQ_ID_SHIFT (1U) +#define LINV2_DMA_CONTROL_DMA_REQ_ID_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ID_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ID_MASK) +#define LINV2_DMA_CONTROL_DMA_REQ_ID_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ID_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ID_SHIFT) + +/* + * DMA_REQ_ENABLE (RW) + * + * slave mode only. 1: enable dma request for data request ID equal dma_req_id + */ +#define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK (0x1U) +#define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SHIFT (0U) +#define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK) +#define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SHIFT) + + + +/* DATA register group index macro definition */ +#define LINV2_DATA_DATA0 (0UL) +#define LINV2_DATA_DATA1 (1UL) + +/* DATA_BYTE register group index macro definition */ +#define LINV2_DATA_BYTE_DATA_BYTE0 (0UL) +#define LINV2_DATA_BYTE_DATA_BYTE1 (1UL) +#define LINV2_DATA_BYTE_DATA_BYTE2 (2UL) +#define LINV2_DATA_BYTE_DATA_BYTE3 (3UL) +#define LINV2_DATA_BYTE_DATA_BYTE4 (4UL) +#define LINV2_DATA_BYTE_DATA_BYTE5 (5UL) +#define LINV2_DATA_BYTE_DATA_BYTE6 (6UL) +#define LINV2_DATA_BYTE_DATA_BYTE7 (7UL) + + +#endif /* HPM_LINV2_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h index 6d4ad56e..5caabb43 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h @@ -106,7 +106,8 @@ typedef struct { * DBRP (RW) * * Data Bit Rate Prescaler - * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. + * When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. */ #define MCAN_DBTP_DBRP_MASK (0x1F0000UL) #define MCAN_DBTP_DBRP_SHIFT (16U) @@ -531,7 +532,8 @@ typedef struct { * TSC (RC) * * Timestamp Counter - * The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. + * The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. + * A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. */ #define MCAN_TSCV_TSC_MASK (0xFFFFU) #define MCAN_TSCV_TSC_SHIFT (0U) @@ -553,7 +555,8 @@ typedef struct { * TOS (RW) * * Timeout Select - * When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. + * When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. + * When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. * 00= Continuous operation * 01= Timeout controlled by Tx Event FIFO * 10= Timeout controlled by Rx FIFO 0 @@ -581,7 +584,8 @@ typedef struct { * TOC (RC) * * Timeout Counter - * The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. + * The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. + * When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. * Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. */ #define MCAN_TOCV_TOC_MASK (0xFFFFU) @@ -593,7 +597,8 @@ typedef struct { * CEL (X) * * CAN Error Logging - * The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. + * The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. + * The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. * The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. * Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. */ @@ -638,7 +643,8 @@ typedef struct { * TDCV (R) * * Transmitter Delay Compensation Value - * Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. + * Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. + * The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. */ #define MCAN_PSR_TDCV_MASK (0x7F0000UL) #define MCAN_PSR_TDCV_SHIFT (16U) @@ -767,12 +773,16 @@ typedef struct { * 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), * the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus * value was dominant. - * 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at + * 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. + * During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at * dominant or continuously disturbed). * 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. * 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. * Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. - * Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. + * Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. + * Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. + * At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, + * enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. * Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. */ #define MCAN_PSR_LEC_MASK (0x7U) @@ -795,7 +805,8 @@ typedef struct { * TDCF (RW) * * Transmitter Delay Compensation Filter Window Length - * Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. + * Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. + * The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. */ #define MCAN_TDCR_TDCF_MASK (0x7FU) #define MCAN_TDCR_TDCF_SHIFT (0U) @@ -903,7 +914,8 @@ typedef struct { * BEU (RW) * * Bit Error Uncorrected - * Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. + * Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. + * An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. * 0= No bit error detected when reading from Message RAM * 1= Bit error detected, uncorrected (e.g. parity logic) */ @@ -1910,7 +1922,8 @@ typedef struct { * EIDM (RW) * * Extended ID Mask - * For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. + * For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. + * Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. */ #define MCAN_XIDAM_EIDM_MASK (0x1FFFFFFFUL) #define MCAN_XIDAM_EIDM_SHIFT (0U) @@ -1968,7 +1981,8 @@ typedef struct { * ND1 (RW) * * New Data[31:0] - * The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. + * The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. + * The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. * 0= Rx Buffer not updated * 1= Rx Buffer updated from new message */ @@ -1982,7 +1996,8 @@ typedef struct { * ND2 (RW) * * New Data[63:32] - * The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. + * The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. + * The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. * 0= Rx Buffer not updated * 1= Rx Buffer updated from new message */ @@ -2103,7 +2118,8 @@ typedef struct { * F0AI (RW) * * Rx FIFO 0 Acknowledge Index - * After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. + * After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. + * This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. */ #define MCAN_RXF0A_F0AI_MASK (0x3FU) #define MCAN_RXF0A_F0AI_SHIFT (0U) @@ -2247,7 +2263,8 @@ typedef struct { * F1AI (RW) * * Rx FIFO 1 Acknowledge Index - * After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. + * After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. + * This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. */ #define MCAN_RXF1A_F1AI_MASK (0x3FU) #define MCAN_RXF1A_F1AI_SHIFT (0U) @@ -2303,7 +2320,8 @@ typedef struct { * 101= 32 byte data field * 110= 48 byte data field * 111= 64 byte data field - * Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. + * Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, + * only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. */ #define MCAN_RXESC_F0DS_MASK (0x7U) #define MCAN_RXESC_F0DS_SHIFT (0U) @@ -2436,7 +2454,8 @@ typedef struct { * TXBCR. * TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the * highest priority (Tx Buffer with lowest Message ID). - * A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. + * A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, + * this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. * After a cancellation has been requested, a finished cancellation is signalled via TXBCF * ? after successful transmission together with the corresponding TXBTO bit * ? when the transmission has not yet been started at the point of cancellation @@ -2473,7 +2492,8 @@ typedef struct { * CR (RW) * * Cancellation Request - * Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. + * Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. + * This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. * 0= No cancellation pending * 1= Cancellation pending */ @@ -2500,7 +2520,8 @@ typedef struct { * CF (R) * * Cancellation Finished - * Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. + * Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. + * In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. * 0= No transmit buffer cancellation * 1= Transmit buffer cancellation finished */ @@ -2881,8 +2902,9 @@ typedef struct { /* * TSU_TBIN_SEL (RW) * + * external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 */ -#define MCAN_GLB_CTL_TSU_TBIN_SEL_MASK (0x7U) +#define MCAN_GLB_CTL_TSU_TBIN_SEL_MASK (0x3U) #define MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT (0U) #define MCAN_GLB_CTL_TSU_TBIN_SEL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) #define MCAN_GLB_CTL_TSU_TBIN_SEL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) >> MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_mipi_dsi_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_mipi_dsi_regs.h new file mode 100644 index 00000000..43122f9d --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_mipi_dsi_regs.h @@ -0,0 +1,2882 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MIPI_DSI_H +#define HPM_MIPI_DSI_H + +typedef struct { + __R uint32_t VERSION; /* 0x0: version */ + __RW uint32_t PWR_UP; /* 0x4: power up */ + __RW uint32_t CLKMGR_CFG; /* 0x8: divide lanebyteclk for timeout */ + __RW uint32_t DPI_VCID; /* 0xC: virtual channel ID for DPI traffic */ + __RW uint32_t DPI_COLOR_CODING; /* 0x10: dpi color coding */ + __RW uint32_t DPI_CFG_POL; /* 0x14: the polarity of DPI signals */ + __RW uint32_t DPI_LP_CMD_TIM; /* 0x18: the timing for low-power commands sent while in video mode */ + __R uint8_t RESERVED0[16]; /* 0x1C - 0x2B: Reserved */ + __RW uint32_t PCKHDL_CFG; /* 0x2C: configures how EoTp, BTA, CRC and ECC to be used */ + __RW uint32_t GEN_VCID; /* 0x30: configures the virtual channel ID of read response to store and return to generic interface */ + __RW uint32_t MODE_CFG; /* 0x34: configures the mode of operation between video or command mode */ + __RW uint32_t VID_MODE_CFG; /* 0x38: several aspect of video mode operation */ + __RW uint32_t VID_PKT_SIZE; /* 0x3C: configures the video packet size */ + __RW uint32_t VID_NUM_CHUNKS; /* 0x40: configures the number of chunks to use */ + __RW uint32_t VID_NULL_SIZE; /* 0x44: configures the size of null packets */ + __RW uint32_t VID_HSA_TIME; /* 0x48: configures the video HAS time */ + __RW uint32_t VID_HBP_TIME; /* 0x4C: configure the video HBP time */ + __RW uint32_t VID_HLINE_TIME; /* 0x50: configures the overall time for each video line */ + __RW uint32_t VID_VSA_LINES; /* 0x54: configures the vsa period */ + __RW uint32_t VID_VBP_LINES; /* 0x58: configures the vbp period */ + __RW uint32_t VID_VFP_LINES; /* 0x5C: configures the vfp period */ + __RW uint32_t VID_VACTIVE_LINES; /* 0x60: configures the vertical resolution of video */ + __R uint8_t RESERVED1[4]; /* 0x64 - 0x67: Reserved */ + __RW uint32_t CMD_MODE_CFG; /* 0x68: This register configures several aspect of command mode operation, tearing effect, acknowledge for each packet and the speed mode to transmit each Data Type related to commands. */ + __RW uint32_t GEN_HDR; /* 0x6C: sets the header for new packets sent using the generic interface */ + __RW uint32_t GEN_PLD_DATA; /* 0x70: sets the payload for packets sent using the generic interface */ + __R uint32_t CMD_PKT_STATUS; /* 0x74: information about the status of FIFOs related to DBI and Generic interface */ + __RW uint32_t TO_CNT_CFG; /* 0x78: configures the trigger timeout errors */ + __RW uint32_t HS_RD_TO_CNT; /* 0x7C: configures the peripheral response timeout after high speed read operations */ + __RW uint32_t LP_RD_TO_CNT; /* 0x80: configures the peripheral response timeout after low-power read operation */ + __RW uint32_t HS_WR_TO_CNT; /* 0x84: configures the peripheral response timeout after high speed write operations */ + __RW uint32_t LP_WR_TO_CNT; /* 0x88: configures the peripheral response timeout after low power write operations */ + __RW uint32_t BTA_TO_CNT; /* 0x8C: configures the periphera response timeout after bus turnaround */ + __RW uint32_t SDF_3D; /* 0x90: sotres 3d control information for vss packets in video mode */ + __RW uint32_t LPCLK_CTRL; /* 0x94: configures the possibility for using non continous clock in the clock lane */ + __RW uint32_t PHY_TMR_LPCLK_CFG; /* 0x98: sets the time that dsi host assumes in calculations for the clock lane to switch between high-speed and low-power */ + __RW uint32_t PHY_TMR_CFG; /* 0x9C: sets the time that dsi host assumes in calculations for data lanes to switch between hs to lp */ + __RW uint32_t PHY_RSTZ; /* 0xA0: controls resets and the pll of d-phy */ + __RW uint32_t PHY_IF_CFG; /* 0xA4: configures the number of active lanes */ + __RW uint32_t PHY_ULPS_CTRL; /* 0xA8: configures entering and leaving ulps */ + __RW uint32_t PHY_TX_TRIGGERS; /* 0xAC: configures the pins that activate triggers in the d-phy */ + __R uint32_t PHY_STATUS; /* 0xB0: contains information about the status of the d-phy */ + __RW uint32_t PHY_TST_CTRL0; /* 0xB4: controls clock and clear pins of the d-phy vendor specific interface */ + __RW uint32_t PHY_TST_CTRL1; /* 0xB8: controls data and enable pins of the d-phy */ + __R uint32_t INT_ST0; /* 0xBC: controls the status of interrupt */ + __R uint32_t INT_ST1; /* 0xC0: the interrupt source related to timeout etc */ + __RW uint32_t INT_MSK0; /* 0xC4: configures masks for the sources of interrupt that affec int_st0 */ + __RW uint32_t INT_MSK1; /* 0xC8: configures masks for int_st1 */ + __RW uint32_t PHY_CAL; /* 0xCC: controls the skew calibration of D-phy */ + __R uint8_t RESERVED2[8]; /* 0xD0 - 0xD7: Reserved */ + __RW uint32_t INT_FORCE0; /* 0xD8: forces that affect the int_st0 register */ + __RW uint32_t INT_FORCE1; /* 0xDC: forces interrupts that affect the int_st1 register */ + __R uint8_t RESERVED3[20]; /* 0xE0 - 0xF3: Reserved */ + __RW uint32_t PHY_TMR_RD; /* 0xF4: configures times related to PHY to perform some operations in lane byte clock cycle */ + __RW uint32_t AUTO_ULPS_MIN_TIME; /* 0xF8: configures the minimum time required by phy between ulpsactivenot and ulpsexitreq for clock and data lane */ + __RW uint32_t PHY_MODE; /* 0xFC: select phy mode */ + __RW uint32_t VID_SHADOW_CTRL; /* 0x100: controls dpi shadow feature */ + __R uint8_t RESERVED4[8]; /* 0x104 - 0x10B: Reserved */ + __R uint32_t DPI_VCID_ACT; /* 0x10C: holds the value that controller is using for DPI_VCID */ + __R uint32_t DPI_COLOR_CODING_ACT; /* 0x110: holds the value that controller is using for DPI_COLOR_CODING */ + __R uint8_t RESERVED5[4]; /* 0x114 - 0x117: Reserved */ + __R uint32_t DPI_LP_CMD_TIM_ACT; /* 0x118: holds value that controller is using for dpi_lp_cmd_time */ + __R uint8_t RESERVED6[28]; /* 0x11C - 0x137: Reserved */ + __R uint32_t VID_MODE_CFG_ACT; /* 0x138: holds value that controller is using for vid_mode_cfg */ + __R uint32_t VID_PKT_SIZE_ACT; /* 0x13C: holds value that controller is using for vid_pkt_size */ + __R uint32_t VID_NUM_CHUNKS_ACT; /* 0x140: holds value that controller is using for vid_num_chunks */ + __R uint32_t VID_NULL_SIZE_ACT; /* 0x144: holds the value that controller is using for vid_null_size */ + __R uint32_t VID_HSA_TIME_ACT; /* 0x148: the value of vid_hsa_time */ + __R uint32_t VID_HBP_TIME_ACT; /* 0x14C: the value that controller is using for vid_hbp_time */ + __R uint32_t VID_HLINE_TIME_ACT; /* 0x150: the value for vid_hline_time */ + __R uint32_t VID_VSA_LINES_ACT; /* 0x154: value for vid_vsa_lines */ + __R uint32_t VID_VBP_LINES_ACT; /* 0x158: value for vid_vbp_lines */ + __R uint32_t VID_VFP_LINES_ACT; /* 0x15C: value for vid_vfp_lines */ + __R uint32_t VID_VACTIVE_LINES_ACT; /* 0x160: value for vid_vactive_lines */ + __R uint8_t RESERVED7[4]; /* 0x164 - 0x167: Reserved */ + __R uint32_t VID_PKT_STATUS; /* 0x168: status of fifo related to dpi */ + __R uint8_t RESERVED8[36]; /* 0x16C - 0x18F: Reserved */ + __R uint32_t SDF_3D_ACT; /* 0x190: value for sdf_3d */ +} MIPI_DSI_Type; + + +/* Bitfield definition for register: VERSION */ +/* + * VERSION (RO) + * + * version of DSI + */ +#define MIPI_DSI_VERSION_VERSION_MASK (0xFFFFFFFFUL) +#define MIPI_DSI_VERSION_VERSION_SHIFT (0U) +#define MIPI_DSI_VERSION_VERSION_GET(x) (((uint32_t)(x) & MIPI_DSI_VERSION_VERSION_MASK) >> MIPI_DSI_VERSION_VERSION_SHIFT) + +/* Bitfield definition for register: PWR_UP */ +/* + * SHUTDOWNZ (RW) + * + * 0x0: reset the core + * 0x1: power up the core + */ +#define MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK (0x1U) +#define MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT (0U) +#define MIPI_DSI_PWR_UP_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT) & MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK) +#define MIPI_DSI_PWR_UP_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK) >> MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT) + +/* Bitfield definition for register: CLKMGR_CFG */ +/* + * TO_CLK_DIVISION (RW) + * + * the timeout clock division factor for HS to LP and LP to HS transition error + */ +#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK (0xFF00U) +#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT (8U) +#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SET(x) (((uint32_t)(x) << MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT) & MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK) +#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_GET(x) (((uint32_t)(x) & MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK) >> MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT) + +/* + * TX_ESC_CLK_DIVISION (RW) + * + * the division factor for the TX Escape clock source lanebyteclk + */ +#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK (0xFFU) +#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT (0U) +#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SET(x) (((uint32_t)(x) << MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT) & MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK) +#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_GET(x) (((uint32_t)(x) & MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK) >> MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT) + +/* Bitfield definition for register: DPI_VCID */ +/* + * DPI_VCID (RW) + * + * the DPI virtual channel id to the video mode packets + */ +#define MIPI_DSI_DPI_VCID_DPI_VCID_MASK (0x3U) +#define MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT (0U) +#define MIPI_DSI_DPI_VCID_DPI_VCID_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT) & MIPI_DSI_DPI_VCID_DPI_VCID_MASK) +#define MIPI_DSI_DPI_VCID_DPI_VCID_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_VCID_DPI_VCID_MASK) >> MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT) + +/* Bitfield definition for register: DPI_COLOR_CODING */ +/* + * LOOSELY18_EN (RW) + * + * when set to 1, this bit activates loosely packed variant to 18-bit configurations + */ +#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK (0x100U) +#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT (8U) +#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT) & MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK) +#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK) >> MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT) + +/* + * DPI_COLOR_CODING (RW) + * + * configures the DPI color for video mode + */ +#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK (0xFU) +#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT (0U) +#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT) & MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK) +#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK) >> MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT) + +/* Bitfield definition for register: DPI_CFG_POL */ +/* + * COLORM_ACTIVE_LOW (RW) + * + * configures the color mode pin as active low + */ +#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK (0x10U) +#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT (4U) +#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK) +#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT) + +/* + * SHUTD_ACTIVE_LOW (RW) + * + * configures the shutdown pin as active low + */ +#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK (0x8U) +#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT (3U) +#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK) +#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT) + +/* + * HSYNC_ACTIVE_LOW (RW) + * + * configures the horizontal synchronism pin as active low + */ +#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK (0x4U) +#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT (2U) +#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK) +#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT) + +/* + * VSYNC_ACTIVE_LOW (RW) + * + * configures the vertical synchronism pin as active low + */ +#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK (0x2U) +#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT (1U) +#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK) +#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT) + +/* + * DATAEN_ACTIVE_LOW (RW) + * + * configures the data enable pin active low + */ +#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK (0x1U) +#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT (0U) +#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK) +#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT) + +/* Bitfield definition for register: DPI_LP_CMD_TIM */ +/* + * OUTVACT_LPCMD_TIME (RW) + * + * transmission of commands in low-power mode, defines the size in bytes of the largest pachet that can fit in a line during the VSA VBP and VFP; + */ +#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK (0xFF0000UL) +#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT (16U) +#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT) & MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK) +#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT) + +/* + * INVACT_LPCMD_TIME (RW) + * + * transmission of commands in low-power mode, defines the size in bytes of the largest packet that can fit in a line during the VACT region. + */ +#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK (0xFFU) +#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT (0U) +#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT) & MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK) +#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT) + +/* Bitfield definition for register: PCKHDL_CFG */ +/* + * EOTP_TX_LP_EN (RW) + * + * enable the EoTp transmission in low-power + */ +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK (0x20U) +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT (5U) +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK) +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT) + +/* + * CRC_RX_EN (RW) + * + * enable the crc reception and error reporting + */ +#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK (0x10U) +#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT (4U) +#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK) +#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT) + +/* + * ECC_RX_EN (RW) + * + * enable the ecc reception error correction and reporting + */ +#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK (0x8U) +#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT (3U) +#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK) +#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT) + +/* + * BTA_EN (RW) + * + * enable the bus turn-around request + */ +#define MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK (0x4U) +#define MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT (2U) +#define MIPI_DSI_PCKHDL_CFG_BTA_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK) +#define MIPI_DSI_PCKHDL_CFG_BTA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT) + +/* + * EOTP_RX_EN (RW) + * + * enable the EoTp reception + */ +#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK (0x2U) +#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT (1U) +#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK) +#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT) + +/* + * EOTP_TX_EN (RW) + * + * enable the EoTp transmission in high-speed + */ +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK (0x1U) +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT (0U) +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK) +#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT) + +/* Bitfield definition for register: GEN_VCID */ +/* + * GEN_VCID_TX_AUTO (RW) + * + * indicates the generic interface virtual channel identification where generic packet is automatically generated and transmitted + */ +#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK (0x30000UL) +#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT (16U) +#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK) +#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT) + +/* + * GEN_VCID_TEAR_AUTO (RW) + * + * indicates the virtual channel identification for tear effect by hardware + */ +#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK (0x300U) +#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT (8U) +#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK) +#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT) + +/* + * GEN_VCID_RX (RW) + * + * indicates the generic interface read-back virtual channel identication + */ +#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK (0x3U) +#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT (0U) +#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK) +#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT) + +/* Bitfield definition for register: MODE_CFG */ +/* + * CMD_VIDEO_MODE (RW) + * + * 0x0: video mode + * 0x1: command mode + */ +#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK (0x1U) +#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT (0U) +#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT) & MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK) +#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK) >> MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT) + +/* Bitfield definition for register: VID_MODE_CFG */ +/* + * VPG_ORIENTATION (RW) + * + * indicates the color bar orientation : + * 0x0: vertical mode + * 0x1: horizontal mode + */ +#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK (0x1000000UL) +#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT (24U) +#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK) +#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT) + +/* + * VPG_MODE (RW) + * + * 0x0: colorbar + * 0x1: berpattern, vertical only + */ +#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK (0x100000UL) +#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT (20U) +#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK) +#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT) + +/* + * VPG_EN (RW) + * + * enable video mode pattern generator + */ +#define MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK (0x10000UL) +#define MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT (16U) +#define MIPI_DSI_VID_MODE_CFG_VPG_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_VPG_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT) + +/* + * LP_CMD_EN (RW) + * + * enable command transmission only in low-power mode + */ +#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK (0x8000U) +#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT (15U) +#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT) + +/* + * FRAME_BTA_ACK_EN (RW) + * + * enable the request for an acknowledge response at the end of a frame + */ +#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK (0x4000U) +#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT (14U) +#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT) + +/* + * LP_HFP_EN (RW) + * + * enable the return to low-power inside the HFP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK (0x2000U) +#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT (13U) +#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT) + +/* + * LP_HBP_EN (RW) + * + * enable the return to low-power inside the HBP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK (0x1000U) +#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT (12U) +#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT) + +/* + * LP_VACT_EN (RW) + * + * enable the return to low-power inside the VACT period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK (0x800U) +#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT (11U) +#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT) + +/* + * LP_VFP_EN (RW) + * + * enable the return to low-power inside the VFP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK (0x400U) +#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT (10U) +#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT) + +/* + * LP_VBP_EN (RW) + * + * enable the return to low-power inside the VBP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK (0x200U) +#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT (9U) +#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT) + +/* + * LP_VSA_EN (RW) + * + * enable the return to low-power inside the VSA period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK (0x100U) +#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT (8U) +#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK) +#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT) + +/* + * VID_MODE_TYPE (RW) + * + * indicates the video mode transmission type + */ +#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK (0x3U) +#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT (0U) +#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT) & MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK) +#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK) >> MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT) + +/* Bitfield definition for register: VID_PKT_SIZE */ +/* + * VID_PKT_SIZE (RW) + * + * configures the number of pixels in a single video packet + */ +#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK (0x3FFFU) +#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT (0U) +#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT) & MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK) +#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK) >> MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT) + +/* Bitfield definition for register: VID_NUM_CHUNKS */ +/* + * VID_NUM_CHUNKS (RW) + * + * configures the number of chunks to be transmitted a line period + */ +#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK (0x1FFFU) +#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT (0U) +#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT) & MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK) +#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK) >> MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT) + +/* Bitfield definition for register: VID_NULL_SIZE */ +/* + * VID_NULL_SIZE (RW) + * + * configures the number of bytes inside a null packet + */ +#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK (0x1FFFU) +#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT (0U) +#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT) & MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK) +#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK) >> MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT) + +/* Bitfield definition for register: VID_HSA_TIME */ +/* + * VID_HSA_TIME (RW) + * + * configure the Horizontal synchronism active period in lane byte clock cycles + */ +#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK (0xFFFU) +#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT (0U) +#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT) & MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK) +#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK) >> MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT) + +/* Bitfield definition for register: VID_HBP_TIME */ +/* + * VID_HPB_TIME (RW) + * + * configures the Horizontal back porch period in lane byte clock cycles + */ +#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK (0xFFFU) +#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT (0U) +#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT) & MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK) +#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK) >> MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT) + +/* Bitfield definition for register: VID_HLINE_TIME */ +/* + * VID_HLINE_TIME (RW) + * + * configures the size of the total line time in lane byte clock cycles + */ +#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK (0x7FFFU) +#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT (0U) +#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT) & MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK) +#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK) >> MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT) + +/* Bitfield definition for register: VID_VSA_LINES */ +/* + * VSA_LINES (RW) + * + * configures the verical synchronism active period measured in number of horizontal lines + */ +#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK (0x3FFU) +#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT) & MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK) +#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK) >> MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT) + +/* Bitfield definition for register: VID_VBP_LINES */ +/* + * VBP_LINES (RW) + * + * configures the vertical back porch period measured in number of horizontal lines + */ +#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK (0x3FFU) +#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT) & MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK) +#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK) >> MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT) + +/* Bitfield definition for register: VID_VFP_LINES */ +/* + * VFP_LINIES (RW) + * + * configures the vertical front porch period measured in number of horizontal lines + */ +#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK (0x3FFU) +#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT (0U) +#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT) & MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK) +#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK) >> MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT) + +/* Bitfield definition for register: VID_VACTIVE_LINES */ +/* + * V_ACTIVE_LINES (RW) + * + * configures the vertical active period measured in number of horizontal lines + */ +#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK (0x3FFFU) +#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT) & MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK) +#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK) >> MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT) + +/* Bitfield definition for register: CMD_MODE_CFG */ +/* + * MAX_RD_PKT_SIZE (RW) + * + * This bit configures the maximum read packet size command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK (0x1000000UL) +#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT (24U) +#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT) & MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK) +#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK) >> MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT) + +/* + * DCS_LW_TX (RW) + * + * This bit configures the DCS long write packet command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK (0x80000UL) +#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT (19U) +#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT) + +/* + * DCS_SR_0P_TX (RW) + * + * This bit configures the DCS short read packet with zero parameter command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK (0x40000UL) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT (18U) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT) + +/* + * DCS_SW_1P_TX (RW) + * + * This bit configures the DCS short write packet with one parameter command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK (0x20000UL) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT (17U) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT) + +/* + * DCS_SW_0P_TX (RW) + * + * This bit configures the DCS short write packet with zero parameter command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK (0x10000UL) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT (16U) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT) + +/* + * GEN_LW_TX (RW) + * + * This bit configures the Generic long write packet command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK (0x4000U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT (14U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT) + +/* + * GEN_SR_2P_TX (RW) + * + * This bit configures the Generic short read packet with two parameters command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK (0x2000U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT (13U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT) + +/* + * GEN_SR_1P_TX (RW) + * + * This bit configures the Generic short read packet with two parameters command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK (0x1000U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT (12U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT) + +/* + * GEN_SR_0P_TX (RW) + * + * This bit configures the Generic short read packet with two parameters command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK (0x800U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT (11U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT) + +/* + * GEN_SW_2P_TX (RW) + * + * This bit configures the Generic short read packet with two parameters command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK (0x400U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT (10U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT) + +/* + * GEN_SW_1P_TX (RW) + * + * This bit configures the Generic short read packet with two parameters command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK (0x200U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT (9U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT) + +/* + * GEN_SW_0P_TX (RW) + * + * This bit configures the Generic short read packet with two parameters command transmission type: + * 0x0 (HIGHSPEED): Transition type is High Speed + * 0x1 (LOWPOWER): Transition type is Low Power + */ +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK (0x100U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT (8U) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK) +#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT) + +/* + * ACK_RQST_EN (RW) + * + * When set to 1, this bit enables the acknowledge request after each packet transmission. + */ +#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK (0x2U) +#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT (1U) +#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT) & MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK) +#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK) >> MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT) + +/* + * TEAR_FX_EN (RW) + * + * When set to 1, this bit enables the tearing effect acknowledge request. + */ +#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK (0x1U) +#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT (0U) +#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT) & MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK) +#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK) >> MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT) + +/* Bitfield definition for register: GEN_HDR */ +/* + * GEN_WC_MSBYTE (RW) + * + * configures the most significant byte of the header packet's word count for long packets or data 1 for shout packets + */ +#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK (0xFF0000UL) +#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT (16U) +#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT) & MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK) +#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK) >> MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT) + +/* + * GEN_WC_LSBYTE (RW) + * + * configures the least significant byte of the header packet's word count for long packets or data0 for short packets + */ +#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK (0xFF00U) +#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT (8U) +#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT) & MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK) +#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK) >> MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT) + +/* + * GEN_VC (RW) + * + * configures the virtual channel ID of the header packet + */ +#define MIPI_DSI_GEN_HDR_GEN_VC_MASK (0xC0U) +#define MIPI_DSI_GEN_HDR_GEN_VC_SHIFT (6U) +#define MIPI_DSI_GEN_HDR_GEN_VC_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_VC_SHIFT) & MIPI_DSI_GEN_HDR_GEN_VC_MASK) +#define MIPI_DSI_GEN_HDR_GEN_VC_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_VC_MASK) >> MIPI_DSI_GEN_HDR_GEN_VC_SHIFT) + +/* + * GEN_DT (RW) + * + * configures the packet data type of the header packet + */ +#define MIPI_DSI_GEN_HDR_GEN_DT_MASK (0x3FU) +#define MIPI_DSI_GEN_HDR_GEN_DT_SHIFT (0U) +#define MIPI_DSI_GEN_HDR_GEN_DT_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_DT_SHIFT) & MIPI_DSI_GEN_HDR_GEN_DT_MASK) +#define MIPI_DSI_GEN_HDR_GEN_DT_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_DT_MASK) >> MIPI_DSI_GEN_HDR_GEN_DT_SHIFT) + +/* Bitfield definition for register: GEN_PLD_DATA */ +/* + * GEN_PLD_B4 (RW) + * + * indicates byte4 of the packet payload + */ +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK (0xFF000000UL) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT (24U) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT) + +/* + * GEN_PLD_B3 (RW) + * + * indicates byte3 of the packet payload + */ +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK (0xFF0000UL) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT (16U) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT) + +/* + * GEN_PLD_B2 (RW) + * + * indicates byte2 of the packet payload + */ +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK (0xFF00U) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT (8U) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT) + +/* + * GEN_PLD_B1 (RW) + * + * indicates byte1 of the packet payload + */ +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK (0xFFU) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT (0U) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK) +#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT) + +/* Bitfield definition for register: CMD_PKT_STATUS */ +/* + * GEN_BUFF_PLD_FULL (R) + * + * the full status of the generic payload internal buffer + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK (0x80000UL) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT (19U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT) + +/* + * GEN_BUFF_PLD_EMPTY (R) + * + * the empty status of the generic payload internal buffer + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK (0x40000UL) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT (18U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT) + +/* + * GEN_BUFF_CMD_FULL (R) + * + * the full status of the generic command internal buffer + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK (0x20000UL) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT (17U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT) + +/* + * GEN_BUFF_CMD_EMPTY (R) + * + * the empty status of the generic command internal buffer + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK (0x10000UL) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT (16U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT) + +/* + * GEN_RD_CMD_BUSY (R) + * + * indicates a read command is issued and the entire response is not sotred in the FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK (0x40U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT (6U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT) + +/* + * GEN_PLD_R_FULL (R) + * + * indicates the full status of the generic read payoad FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK (0x20U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT (5U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT) + +/* + * GEN_PLD_R_EMPTY (R) + * + * indicates the empty status of the generic read payload FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK (0x10U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT (4U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT) + +/* + * GEN_PLD_W_FULL (R) + * + * indicates the full status of the generic write payload FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK (0x8U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT (3U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT) + +/* + * GEN_PLD_W_EMPTY (R) + * + * indicates the empty status of the generic write payload FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK (0x4U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT (2U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT) + +/* + * GEN_CMD_FULL (R) + * + * indicates the full status of the generic command FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK (0x2U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT (1U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT) + +/* + * GEN_CMD_EMPTY (R) + * + * indicates the empty status of the generic command FIFO + */ +#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK (0x1U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT (0U) +#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT) + +/* Bitfield definition for register: TO_CNT_CFG */ +/* + * HSTX_TO_CNT (RW) + * + * configures the timeout counter that triggers a high speed transmission timeout contention detection + */ +#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK (0xFFFF0000UL) +#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT (16U) +#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT) & MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK) +#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK) >> MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT) + +/* + * LPRX_TO_CNT (RW) + * + * configures the timeout counter that triggers a low power reception timeout contention detection + */ +#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK (0xFFFFU) +#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT (0U) +#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT) & MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK) +#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK) >> MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT) + +/* Bitfield definition for register: HS_RD_TO_CNT */ +/* + * HS_RD_TO_CNT (RW) + * + * sets a period for which DWC_mipi_dsi_host keeps the link still after sending a high speed read operation; + */ +#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK (0xFFFFU) +#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT (0U) +#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT) & MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK) +#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK) >> MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT) + +/* Bitfield definition for register: LP_RD_TO_CNT */ +/* + * LP_RD_TO_CNT (RW) + * + * sets a period for which dwc_mipi_dsi_host keeps the link still after sending a low power read operation + */ +#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK (0xFFFFU) +#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT (0U) +#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT) & MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK) +#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK) >> MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT) + +/* Bitfield definition for register: HS_WR_TO_CNT */ +/* + * HS_WR_TO_CNT (RW) + * + * sets the period for which dwc_mipi_dsi_host keeps the link still after sending a high speed wirte operation + */ +#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK (0xFFFFU) +#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT (0U) +#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT) & MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK) +#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK) >> MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT) + +/* Bitfield definition for register: LP_WR_TO_CNT */ +/* + * LP_WR_TO_CNT (RW) + * + * sets the period for which dsi host keeps the link still after sending a low power write operation + */ +#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK (0xFFFFU) +#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT (0U) +#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT) & MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK) +#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK) >> MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT) + +/* Bitfield definition for register: BTA_TO_CNT */ +/* + * BTA_TO_CNT (RW) + * + * sets the period for which dsi host keeps the link still after completing a bus turnaround. + */ +#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK (0xFFFFU) +#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT (0U) +#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT) & MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK) +#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK) >> MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT) + +/* Bitfield definition for register: SDF_3D */ +/* + * SEND_3D_CFG (RW) + * + * set the next vss packet to include 3d control payload in every vss packet + */ +#define MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK (0x10000UL) +#define MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT (16U) +#define MIPI_DSI_SDF_3D_SEND_3D_CFG_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT) & MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK) +#define MIPI_DSI_SDF_3D_SEND_3D_CFG_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK) >> MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT) + +/* + * RIGHT_FIRST (RW) + * + * 0x0: left eye is sent first + * 0x1:right eye is sent first + */ +#define MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK (0x20U) +#define MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT (5U) +#define MIPI_DSI_SDF_3D_RIGHT_FIRST_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT) & MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK) +#define MIPI_DSI_SDF_3D_RIGHT_FIRST_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK) >> MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT) + +/* + * SECOND_VSYNC (RW) + * + * defines whether there is a second VSYNC pulse + */ +#define MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK (0x10U) +#define MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT (4U) +#define MIPI_DSI_SDF_3D_SECOND_VSYNC_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT) & MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK) +#define MIPI_DSI_SDF_3D_SECOND_VSYNC_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK) >> MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT) + +/* + * FORMAT_3D (RW) + * + * defines 3D image format + */ +#define MIPI_DSI_SDF_3D_FORMAT_3D_MASK (0xCU) +#define MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT (2U) +#define MIPI_DSI_SDF_3D_FORMAT_3D_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT) & MIPI_DSI_SDF_3D_FORMAT_3D_MASK) +#define MIPI_DSI_SDF_3D_FORMAT_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_FORMAT_3D_MASK) >> MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT) + +/* + * MODE_3D (RW) + * + * defines 3D mode on/off + */ +#define MIPI_DSI_SDF_3D_MODE_3D_MASK (0x3U) +#define MIPI_DSI_SDF_3D_MODE_3D_SHIFT (0U) +#define MIPI_DSI_SDF_3D_MODE_3D_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_MODE_3D_SHIFT) & MIPI_DSI_SDF_3D_MODE_3D_MASK) +#define MIPI_DSI_SDF_3D_MODE_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_MODE_3D_MASK) >> MIPI_DSI_SDF_3D_MODE_3D_SHIFT) + +/* Bitfield definition for register: LPCLK_CTRL */ +/* + * AUTO_CLKLANE_CTRL (RW) + * + * enables the automatic mechanism to stop providing clock in the clock lane + */ +#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK (0x2U) +#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT (1U) +#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SET(x) (((uint32_t)(x) << MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT) & MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK) +#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_GET(x) (((uint32_t)(x) & MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK) >> MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT) + +/* + * PHY_TXREQUESTCLKHS (RW) + * + * controls the D-PHY PPI txrequestclkhs signal + */ +#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK (0x1U) +#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT (0U) +#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SET(x) (((uint32_t)(x) << MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT) & MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK) +#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_GET(x) (((uint32_t)(x) & MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK) >> MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT) + +/* Bitfield definition for register: PHY_TMR_LPCLK_CFG */ +/* + * PHY_CLKHS2LP_TIME (RW) + * + * configures the maximum time that the d-phy clock lane takes to go from high-speed to low-power transmission + */ +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK (0x3FF0000UL) +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT (16U) +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK) +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK) >> MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT) + +/* + * PHY_CLKLP2HS_TIME (RW) + * + * configures the maximum time that the d-phy clock lane takes to go from low-power to high-speed transmission + */ +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK (0x3FFU) +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT (0U) +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK) +#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK) >> MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT) + +/* Bitfield definition for register: PHY_TMR_CFG */ +/* + * PHY_HS2LP_TIME (RW) + * + * This field configures the maximum time that the D-PHY data + * lanes take to go from high-speed to low-power transmission + * measured in lane byte clock cycles + */ +#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK (0x3FF0000UL) +#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT (16U) +#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT) & MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK) +#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK) >> MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT) + +/* + * PHY_LP2HS_TIME (RW) + * + * This field configures the maximum time that the D-PHY data + * lanes take to go from low-power to high-speed transmission + * measured in lane byte clock cycles. + */ +#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK (0x3FFU) +#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT (0U) +#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT) & MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK) +#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK) >> MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT) + +/* Bitfield definition for register: PHY_RSTZ */ +/* + * PHY_FORCEPLL (RW) + * + * when the d-phy is in ulps, enable the d-phy pll + */ +#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK (0x8U) +#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT (3U) +#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK) +#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT) + +/* + * PHY_ENABLECLK (RW) + * + * enable dphy clock lane + */ +#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK (0x4U) +#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT (2U) +#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK) +#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT) + +/* + * PHY_RSTZ (RW) + * + * make the dphy in reset state when set to 0 + */ +#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK (0x2U) +#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT (1U) +#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK) +#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT) + +/* + * PHY_SHUTDOWNZ (RW) + * + * places the dphy macro in power down mode when set to 0 + */ +#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK (0x1U) +#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT (0U) +#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK) +#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT) + +/* Bitfield definition for register: PHY_IF_CFG */ +/* + * PHY_STOP_WAIT_TIME (RW) + * + * configures the minimum time phy needs to stay in stopstate before requesting an highspeed transmission + */ +#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK (0xFF00U) +#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT (8U) +#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT) & MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK) +#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK) >> MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT) + +/* + * N_LANES (RW) + * + * configures the number of active data lanes + */ +#define MIPI_DSI_PHY_IF_CFG_N_LANES_MASK (0x3U) +#define MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT (0U) +#define MIPI_DSI_PHY_IF_CFG_N_LANES_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT) & MIPI_DSI_PHY_IF_CFG_N_LANES_MASK) +#define MIPI_DSI_PHY_IF_CFG_N_LANES_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_IF_CFG_N_LANES_MASK) >> MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT) + +/* Bitfield definition for register: PHY_ULPS_CTRL */ +/* + * PHY_TXEXITULPSLAN (RW) + * + * ulps mode exit on all active data lanes + */ +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK (0x8U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT (3U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT) + +/* + * PHY_TXREQULPSLAN (RW) + * + * ulps mode request on all active data lanes + */ +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK (0x4U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT (2U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT) + +/* + * PHY_TXEXITULPSCLK (RW) + * + * ulps mode exit on clock lane + */ +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK (0x2U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT (1U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT) + +/* + * PHY_TXREQULPSCLK (RW) + * + * ulps mode request on clock lane + */ +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK (0x1U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT (0U) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK) +#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT) + +/* Bitfield definition for register: PHY_TX_TRIGGERS */ +/* + * PHY_TX_TRIGGERS (RW) + * + * controls the trigger transmissions + */ +#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK (0xFU) +#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT (0U) +#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT) & MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK) +#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK) >> MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT) + +/* Bitfield definition for register: PHY_STATUS */ +/* + * PHY_ULPSACTIVENOT3LANE (R) + * + * indicates the status of ulpsactivenot3lane d-phy signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK (0x1000U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT (12U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT) + +/* + * PHY_STOPSTATE3LANE (R) + * + * This bit indicates the status of phystopstate3lane D-PHY + * signal. + */ +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK (0x800U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT (11U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT) + +/* + * PHY_ULPSACTIVENOT2LANE (R) + * + * This bit indicates the status of ulpsactivenot2lane D-PHY + * signa + */ +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK (0x400U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT (10U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT) + +/* + * PHY_STOPSTATE2LANE (R) + * + * This bit indicates the status of phystopstate2lane D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK (0x200U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT (9U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT) + +/* + * PHY_ULPSACTIVENOT1LANE (R) + * + * This bit indicates the status of ulpsactivenot1lane D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK (0x100U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT (8U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT) + +/* + * PHY_STOPSTATE1LANE (R) + * + * This bit indicates the status of phystopstate1lane D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK (0x80U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT (7U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT) + +/* + * PHY_RXULPSESC0LANE (R) + * + * This bit indicates the status of rxulpsesc0lane D-PHY signa + */ +#define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK (0x40U) +#define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT (6U) +#define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT) + +/* + * PHY_ULPSACTIVENOT0LANE (R) + * + * This bit indicates the status of ulpsactivenot0lane D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK (0x20U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT (5U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT) + +/* + * PHY_STOPSTATE0LANE (R) + * + * This bit indicates the status of phystopstate0lane D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK (0x10U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT (4U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT) + +/* + * PHY_ULPSACTIVENOTCLK (R) + * + * This bit indicates the status of phyulpsactivenotclk D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK (0x8U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT (3U) +#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT) + +/* + * PHY_STOPSTATECLKLANE (R) + * + * This bit indicates the status of phystopstateclklane D-PHY + * signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK (0x4U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT (2U) +#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT) + +/* + * PHY_DIRECTION (R) + * + * This bit indicates the status of phydirection D-PHY signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK (0x2U) +#define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT (1U) +#define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK) >> MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT) + +/* + * PHY_LOCK (R) + * + * This bit indicates the status of phylock D-PHY signal + */ +#define MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK (0x1U) +#define MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT (0U) +#define MIPI_DSI_PHY_STATUS_PHY_LOCK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK) >> MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT) + +/* Bitfield definition for register: PHY_TST_CTRL0 */ +/* + * PHY_TESTCLK (RW) + * + * reserve + */ +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK (0x2U) +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT (1U) +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK) +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK) >> MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT) + +/* + * PHY_TESTCLR (RW) + * + * reserve + */ +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK (0x1U) +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT (0U) +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK) +#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK) >> MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT) + +/* Bitfield definition for register: PHY_TST_CTRL1 */ +/* + * PHY_TESTEN (RW) + * + * reserve + */ +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK (0x10000UL) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT (16U) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT) + +/* + * PHY_TESTDOUT (R) + * + * reserve + */ +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK (0xFF00U) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT (8U) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT) + +/* + * PHY_TESTDIN (RW) + * + * reserve + */ +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK (0xFFU) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT (0U) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK) +#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT) + +/* Bitfield definition for register: INT_ST0 */ +/* + * DPHY_ERRORS_4 (R) + * + * indicates LP1 contention error ErrContentionLP1 from lane0 + */ +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK (0x100000UL) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT (20U) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT) + +/* + * DPHY_ERRORS_3 (R) + * + * indicates LP0 contention error ErrContentionLP0 from lane0 + */ +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK (0x80000UL) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT (19U) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT) + +/* + * DPHY_ERRORS_2 (R) + * + * indicates control error ErrControl from lane0 + */ +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK (0x40000UL) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT (18U) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT) + +/* + * DPHY_ERRORS_1 (R) + * + * indicates ErrSyncEsc low-power data transmission synchronization error from lane 0 + */ +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK (0x20000UL) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT (17U) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT) + +/* + * DPHY_ERRORS_0 (R) + * + * indicates ErrEsc escape entry error from lane0 + */ +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK (0x10000UL) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT (16U) +#define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT) + +/* + * ACK_WITH_ERR_15 (R) + * + * retrives the DSI protocal violation from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK (0x8000U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT (15U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT) + +/* + * ACK_WITH_ERR_14 (R) + * + * retrives the reserved from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK (0x4000U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT (14U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT) + +/* + * ACK_WITH_ERR_13 (R) + * + * retrives the invalid transmission length from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK (0x2000U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT (13U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT) + +/* + * ACK_WITH_ERR_12 (R) + * + * retrieves the dsi vc id invalid from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK (0x1000U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT (12U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT) + +/* + * ACK_WITH_ERR_11 (R) + * + * retrives the not recongnized dsi data type from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK (0x800U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT (11U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT) + +/* + * ACK_WITH_ERR_10 (R) + * + * retrives the checksum error from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK (0x400U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT (10U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT) + +/* + * ACK_WITH_ERR_9 (R) + * + * retrives the ECC error multi-bit from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK (0x200U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT (9U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT) + +/* + * ACK_WITH_ERR8 (R) + * + * retrives the ecc error sigle-bit from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK (0x100U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT (8U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT) + +/* + * ACK_WITH_ERR7 (R) + * + * retrieves the reserved from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK (0x80U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT (7U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT) + +/* + * ACK_WITH_ERR6 (R) + * + * retrieves the false control error fro the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK (0x40U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT (6U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT) + +/* + * ACK_WITH_ERR5 (R) + * + * retrives the peripheral timeout error from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK (0x20U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT (5U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT) + +/* + * ACK_WITH_ERR4 (R) + * + * retrives the LP transmit sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK (0x10U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT (4U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT) + +/* + * ACK_WITH_ERR3 (R) + * + * retrives the Escap mode entry command error from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK (0x8U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT (3U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT) + +/* + * ACK_WITH_ERR2 (R) + * + * retrives the EoT sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK (0x4U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT (2U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT) + +/* + * ACK_WITH_ERR1 (R) + * + * retrives the SoT sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK (0x2U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT (1U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT) + +/* + * ACK_WITH_ERR0 (R) + * + * retrives the SoT serror from the acknowledge error report + */ +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK (0x1U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT (0U) +#define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT) + +/* Bitfield definition for register: INT_ST1 */ +/* + * TEAR_REQUEST_ERR (R) + * + * indicates tear_request has occurred but tear effect is not active in dsi host and device + */ +#define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK (0x100000UL) +#define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT (20U) +#define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT) + +/* + * DPI_BUFF_PLD_UNDER (R) + * + * indicates an underflow when reading payload to build dsi packet for video mode + */ +#define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK (0x80000UL) +#define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT (19U) +#define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT) + +/* + * GEN_PLD_RECEV_ERR (R) + * + * indicates that during a generic interface packet read back, the payload FIFO full + */ +#define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK (0x1000U) +#define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT (12U) +#define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT) + +/* + * GEN_PLD_RD_ERR (R) + * + * indicates that during a DCS read data, the payload FIFO becomes empty + */ +#define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK (0x800U) +#define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT (11U) +#define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT) + +/* + * GEN_PLD_SEND_ERR (R) + * + * indicates the payload FIFO become empty when packet build + */ +#define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK (0x400U) +#define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT (10U) +#define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT) + +/* + * GEN_PLD_WR_ERR (R) + * + * indicates the system tried to write a payload and FIFO is full + */ +#define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK (0x200U) +#define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT (9U) +#define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT) + +/* + * GEN_CMD_WR_ERR (R) + * + * indicates the system tried to write a command and FIFO is full + */ +#define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK (0x100U) +#define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT (8U) +#define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT) + +/* + * DPI_BPLD_WR_ERR (R) + * + * indicates the payload FIFO is full during a DPI pixel line storage + */ +#define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK (0x80U) +#define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT (7U) +#define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT) + +/* + * EOPT_ERR (R) + * + * indicates that the EoTp packet has not been received at the end of the incoming peripheral transmission + */ +#define MIPI_DSI_INT_ST1_EOPT_ERR_MASK (0x40U) +#define MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT (6U) +#define MIPI_DSI_INT_ST1_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_EOPT_ERR_MASK) >> MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT) + +/* + * PKT_SIZE_ERR (R) + * + * indicates that the packet size error has been detected during the packet reception + */ +#define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK (0x20U) +#define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT (5U) +#define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT) + +/* + * CRC_ERR (R) + * + * indicates that the CRC error has been detected in the reveived packet payload + */ +#define MIPI_DSI_INT_ST1_CRC_ERR_MASK (0x10U) +#define MIPI_DSI_INT_ST1_CRC_ERR_SHIFT (4U) +#define MIPI_DSI_INT_ST1_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_CRC_ERR_MASK) >> MIPI_DSI_INT_ST1_CRC_ERR_SHIFT) + +/* + * ECC_MULTI_ERR (R) + * + * indicates that the ECC multiple error has been detected in a revieved packet + */ +#define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK (0x8U) +#define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT (3U) +#define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT) + +/* + * ECC_SIGLE_ERR (R) + * + * indicates that the ECC single error has been detected and corrected in a reveived packet + */ +#define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK (0x4U) +#define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT (2U) +#define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT) + +/* + * TO_LP_TX (R) + * + * indicates that the low-power reception timeout counter reached the end and contention has been detected + */ +#define MIPI_DSI_INT_ST1_TO_LP_TX_MASK (0x2U) +#define MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT (1U) +#define MIPI_DSI_INT_ST1_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TO_LP_TX_MASK) >> MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT) + +/* + * TO_HS_TX (R) + * + * indicates that the high-speed transmission timeout counter reached the end and contention has been detected + */ +#define MIPI_DSI_INT_ST1_TO_HS_TX_MASK (0x1U) +#define MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT (0U) +#define MIPI_DSI_INT_ST1_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TO_HS_TX_MASK) >> MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT) + +/* Bitfield definition for register: INT_MSK0 */ +/* + * MASK_DPHY_ERRORS_4 (RW) + * + * disable LP1 contention error ErrContentionLP1 from lane0 + */ +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK (0x100000UL) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT (20U) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT) + +/* + * MASK_DPHY_ERRORS_3 (RW) + * + * disable LP0 contention error ErrContentionLP0 from lane0 + */ +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK (0x80000UL) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT (19U) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT) + +/* + * MASK_DPHY_ERRORS_2 (RW) + * + * disable control error ErrControl from lane0 + */ +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK (0x40000UL) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT (18U) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT) + +/* + * MASK_DPHY_ERRORS_1 (RW) + * + * disable ErrSyncEsc low-power data transmission synchronization error from lane 0 + */ +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK (0x20000UL) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT (17U) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT) + +/* + * MASK_DPHY_ERRORS_0 (RW) + * + * disable ErrEsc escape entry error from lane0 + */ +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK (0x10000UL) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT (16U) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK) +#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT) + +/* + * MASK_ACK_WITH_ERR_15 (RW) + * + * disable the DSI protocal violation from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK (0x8000U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT (15U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT) + +/* + * MASK_ACK_WITH_ERR_14 (RW) + * + * disable the reserved from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK (0x4000U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT (14U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT) + +/* + * MASK_ACK_WITH_ERR_13 (RW) + * + * disable the invalid transmission length from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK (0x2000U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT (13U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT) + +/* + * MASK_ACK_WITH_ERR_12 (RW) + * + * disable the dsi vc id invalid from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK (0x1000U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT (12U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT) + +/* + * MASK_ACK_WITH_ERR_11 (RW) + * + * disable the not recongnized dsi data type from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK (0x800U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT (11U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT) + +/* + * MASK_ACK_WITH_ERR_10 (RW) + * + * disable the checksum error from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK (0x400U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT (10U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT) + +/* + * MASK_ACK_WITH_ERR_9 (RW) + * + * disable the ECC error multi-bit from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK (0x200U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT (9U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT) + +/* + * MASK_ACK_WITH_ERR8 (RW) + * + * disable the ecc error sigle-bit from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK (0x100U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT (8U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT) + +/* + * MASK_ACK_WITH_ERR7 (RW) + * + * disable the reserved from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK (0x80U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT (7U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT) + +/* + * MASK_ACK_WITH_ERR6 (RW) + * + * disable the false control error fro the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK (0x40U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT (6U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT) + +/* + * MASK_ACK_WITH_ERR5 (RW) + * + * disable the peripheral timeout error from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK (0x20U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT (5U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT) + +/* + * MASK_ACK_WITH_ERR4 (RW) + * + * disable the LP transmit sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK (0x10U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT (4U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT) + +/* + * MASK_ACK_WITH_ERR3 (RW) + * + * disable the Escap mode entry command error from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK (0x8U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT (3U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT) + +/* + * MASK_ACK_WITH_ERR2 (RW) + * + * disable the EoT sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK (0x4U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT (2U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT) + +/* + * MASK_ACK_WITH_ERR1 (RW) + * + * disable the SoT sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK (0x2U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT (1U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT) + +/* + * MASK_ACK_WITH_ERR0 (RW) + * + * disable the SoT serror from the acknowledge error report + */ +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK (0x1U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT (0U) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK) +#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT) + +/* Bitfield definition for register: INT_MSK1 */ +/* + * MASK_TEAR_REQUEST_ERR (RW) + * + * disable tear_request has occurred but tear effect is not active in dsi host and device + */ +#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK (0x100000UL) +#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT (20U) +#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT) + +/* + * MASK_DPI_BUFF_PLD_UNDER (RW) + * + * disable an underflow when reading payload to build dsi packet for video mode + */ +#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK (0x80000UL) +#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT (19U) +#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT) & MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK) +#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT) + +/* + * MASK_GEN_PLD_RECEV_ERR (RW) + * + * disable that during a generic interface packet read back, the payload FIFO full + */ +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK (0x1000U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT (12U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT) + +/* + * MASK_GEN_PLD_RD_ERR (RW) + * + * disable that during a DCS read data, the payload FIFO becomes empty + */ +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK (0x800U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT (11U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT) + +/* + * MASK_GEN_PLD_SEND_ERR (RW) + * + * disable the payload FIFO become empty when packet build + */ +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK (0x400U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT (10U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT) + +/* + * MASK_GEN_PLD_WR_ERR (RW) + * + * disable the system tried to write a payload and FIFO is full + */ +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK (0x200U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT (9U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT) + +/* + * MASK_GEN_CMD_WR_ERR (RW) + * + * disable the system tried to write a command and FIFO is full + */ +#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK (0x100U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT (8U) +#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT) + +/* + * MASK_DPI_BPLD_WR_ERR (RW) + * + * disable the payload FIFO is full during a DPI pixel line storage + */ +#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK (0x80U) +#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT (7U) +#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT) + +/* + * MASK_EOPT_ERR (RW) + * + * disable that the EoTp packet has not been received at the end of the incoming peripheral transmission + */ +#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK (0x40U) +#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT (6U) +#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT) + +/* + * MASK_PKT_SIZE_ERR (RW) + * + * disable that the packet size error has been detected during the packet reception + */ +#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK (0x20U) +#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT (5U) +#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT) + +/* + * MASK_CRC_ERR (RW) + * + * disable that the CRC error has been detected in the reveived packet payload + */ +#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK (0x10U) +#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT (4U) +#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT) + +/* + * MASK_ECC_MULTI_ERR (RW) + * + * disable that the ECC multiple error has been detected in a revieved packet + */ +#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK (0x8U) +#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT (3U) +#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT) + +/* + * MASK_ECC_SIGLE_ERR (RW) + * + * disable that the ECC single error has been detected and corrected in a reveived packet + */ +#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK (0x4U) +#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT (2U) +#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK) +#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT) + +/* + * MASK_TO_LP_TX (RW) + * + * disable that the low-power reception timeout counter reached the end and contention has been detected + */ +#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK (0x2U) +#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT (1U) +#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK) +#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK) >> MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT) + +/* + * MASK_TO_HS_TX (RW) + * + * disable that the high-speed transmission timeout counter reached the end and contention has been detected + */ +#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK (0x1U) +#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT (0U) +#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK) +#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK) >> MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT) + +/* Bitfield definition for register: PHY_CAL */ +/* + * TXSKEWCALHS (RW) + * + * High-speed skew calibration is started when txskewcalhs is + * set high (assuming that PHY is in Stop state) + */ +#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK (0x1U) +#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT (0U) +#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT) & MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK) +#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK) >> MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT) + +/* Bitfield definition for register: INT_FORCE0 */ +/* + * FORCE_DPHY_ERRORS_4 (RW) + * + * force LP1 contention error ErrContentionLP1 from lane0 + */ +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK (0x100000UL) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT (20U) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT) + +/* + * FORCE_DPHY_ERRORS_3 (RW) + * + * force LP0 contention error ErrContentionLP0 from lane0 + */ +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK (0x80000UL) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT (19U) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT) + +/* + * FORCE_DPHY_ERRORS_2 (RW) + * + * force control error ErrControl from lane0 + */ +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK (0x40000UL) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT (18U) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT) + +/* + * FORCE_DPHY_ERRORS_1 (RW) + * + * force ErrSyncEsc low-power data transmission synchronization error from lane 0 + */ +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK (0x20000UL) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT (17U) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT) + +/* + * FORCE_DPHY_ERRORS_0 (RW) + * + * force ErrEsc escape entry error from lane0 + */ +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK (0x10000UL) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT (16U) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_15 (RW) + * + * force the DSI protocal violation from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK (0x8000U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT (15U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_14 (RW) + * + * force the reserved from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK (0x4000U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT (14U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_13 (RW) + * + * force the invalid transmission length from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK (0x2000U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT (13U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_12 (RW) + * + * force the dsi vc id invalid from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK (0x1000U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT (12U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_11 (RW) + * + * force the not recongnized dsi data type from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK (0x800U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT (11U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_10 (RW) + * + * force the checksum error from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK (0x400U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT (10U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT) + +/* + * FORCE_ACK_WITH_ERR_9 (RW) + * + * force the ECC error multi-bit from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK (0x200U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT (9U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT) + +/* + * FORCE_ACK_WITH_ERR8 (RW) + * + * force the ecc error sigle-bit from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK (0x100U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT (8U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT) + +/* + * FORCE_ACK_WITH_ERR7 (RW) + * + * force the reserved from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK (0x80U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT (7U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT) + +/* + * FORCE_ACK_WITH_ERR6 (RW) + * + * force the false control error fro the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK (0x40U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT (6U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT) + +/* + * FORCE_ACK_WITH_ERR5 (RW) + * + * force the peripheral timeout error from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK (0x20U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT (5U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT) + +/* + * FORCE_ACK_WITH_ERR4 (RW) + * + * force the LP transmit sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK (0x10U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT (4U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT) + +/* + * FORCE_ACK_WITH_ERR3 (RW) + * + * force the Escap mode entry command error from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK (0x8U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT (3U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT) + +/* + * FORCE_ACK_WITH_ERR2 (RW) + * + * force the EoT sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK (0x4U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT (2U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT) + +/* + * FORCE_ACK_WITH_ERR1 (RW) + * + * force the SoT sync error from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK (0x2U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT (1U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT) + +/* + * FORCE_ACK_WITH_ERR0 (RW) + * + * force the SoT serror from the acknowledge error report + */ +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK (0x1U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT (0U) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK) +#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT) + +/* Bitfield definition for register: INT_FORCE1 */ +/* + * FORCE_TEAR_REQUEST_ERR (RW) + * + * force tear_request has occurred but tear effect is not active in dsi host and device + */ +#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK (0x100000UL) +#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT (20U) +#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT) + +/* + * FORCE_DPI_BUFF_PLD_UNDER (RW) + * + * force an underflow when reading payload to build dsi packet for video mode + */ +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK (0x80000UL) +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT (19U) +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT) + +/* + * FORCE_GEN_PLD_RECEV_ERR (RW) + * + * force that during a generic interface packet read back, the payload FIFO full + */ +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK (0x1000U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT (12U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT) + +/* + * FORCE_GEN_PLD_RD_ERR (RW) + * + * force that during a DCS read data, the payload FIFO becomes empty + */ +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK (0x800U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT (11U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT) + +/* + * FORCE_GEN_PLD_SEND_ERR (RW) + * + * force the payload FIFO become empty when packet build + */ +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK (0x400U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT (10U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT) + +/* + * FORCE_GEN_PLD_WR_ERR (RW) + * + * force the system tried to write a payload and FIFO is full + */ +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK (0x200U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT (9U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT) + +/* + * FORCE_GEN_CMD_WR_ERR (RW) + * + * force the system tried to write a command and FIFO is full + */ +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK (0x100U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT (8U) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT) + +/* + * FORCE_DPI_BPLD_WR_ERR (RW) + * + * force the payload FIFO is full during a DPI pixel line storage + */ +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK (0x80U) +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT (7U) +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT) + +/* + * FORCE_EOPT_ERR (RW) + * + * force that the EoTp packet has not been received at the end of the incoming peripheral transmission + */ +#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK (0x40U) +#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT (6U) +#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT) + +/* + * FORCE_PKT_SIZE_ERR (RW) + * + * force that the packet size error has been detected during the packet reception + */ +#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK (0x20U) +#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT (5U) +#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT) + +/* + * FORCE_CRC_ERR (RW) + * + * force that the CRC error has been detected in the reveived packet payload + */ +#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK (0x10U) +#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT (4U) +#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT) + +/* + * FORCE_ECC_MULTI_ERR (RW) + * + * force that the ECC multiple error has been detected in a revieved packet + */ +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK (0x8U) +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT (3U) +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT) + +/* + * FORCE_ECC_SIGLE_ERR (RW) + * + * force that the ECC single error has been detected and corrected in a reveived packet + */ +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK (0x4U) +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT (2U) +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT) + +/* + * FORCE_TO_LP_TX (RW) + * + * force that the low-power reception timeout counter reached the end and contention has been detected + */ +#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK (0x2U) +#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT (1U) +#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT) + +/* + * FORCE_TO_HS_TX (RW) + * + * force that the high-speed transmission timeout counter reached the end and contention has been detected + */ +#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK (0x1U) +#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT (0U) +#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK) +#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT) + +/* Bitfield definition for register: PHY_TMR_RD */ +/* + * MAX_RD_TIME (RW) + * + * the maximum time required to perform a read command in lane byte clock cycles. + */ +#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK (0x7FFFU) +#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT (0U) +#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT) & MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK) +#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK) >> MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT) + +/* Bitfield definition for register: AUTO_ULPS_MIN_TIME */ +/* + * ULPS_MIN_TIME (RW) + * + * configures the minimum time required by phy between ulpsactivenot and ulpsexitreq for clock and data lane + */ +#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK (0xFFFU) +#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT (0U) +#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK) +#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK) >> MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT) + +/* Bitfield definition for register: PHY_MODE */ +/* + * PHY_MODE (RW) + * + * sel DPHY or CPHY + */ +#define MIPI_DSI_PHY_MODE_PHY_MODE_MASK (0x1U) +#define MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT (0U) +#define MIPI_DSI_PHY_MODE_PHY_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT) & MIPI_DSI_PHY_MODE_PHY_MODE_MASK) +#define MIPI_DSI_PHY_MODE_PHY_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MODE_PHY_MODE_MASK) >> MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT) + +/* Bitfield definition for register: VID_SHADOW_CTRL */ +/* + * VID_SHADOW_PIN_REQ (RW) + * + * when set to 1, the video request is done by external pin + */ +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK (0x10000UL) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT (16U) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT) + +/* + * VID_SHADOW_REQ (RW) + * + * when set to 1, request that the dpi register from regbank are copied to the auxiliary registers + */ +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK (0x100U) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT (8U) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT) + +/* + * VID_SHADOW_EN (RW) + * + * when set to 1, DPI receives the active configuration from the auxiliary register + */ +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK (0x1U) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT (0U) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK) +#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT) + +/* Bitfield definition for register: DPI_VCID_ACT */ +/* + * DPI_VCID (R) + * + * specifies the DPI virtual channel id that is indexed to the video mode packets + */ +#define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK (0x3U) +#define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT (0U) +#define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK) >> MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT) + +/* Bitfield definition for register: DPI_COLOR_CODING_ACT */ +/* + * LOOSELY18_EN (R) + * + * avtivates loosely packed variant to 18-bit configuration + */ +#define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK (0x100U) +#define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT (8U) +#define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK) >> MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT) + +/* + * DIP_COLOR_CODING (R) + * + * configures the DPI color for video mode + */ +#define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK (0xFU) +#define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT (0U) +#define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK) >> MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT) + +/* Bitfield definition for register: DPI_LP_CMD_TIM_ACT */ +/* + * OUTVACT_LPCMD_TIME (R) + * + * transmission of commands in low-power mode, it specifies the size in bytes of the lagest packet that can fit in a line during the VSA VBP and VFP regions. + */ +#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK (0xFF0000UL) +#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT (16U) +#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT) + +/* + * INVACT_LPCMD_TIME (R) + * + * transmission of commands in low-power mode, it specifies the size in bytes of the lagest packet that can fit in a line during the vact regions. + */ +#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK (0xFFU) +#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT (0U) +#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT) + +/* Bitfield definition for register: VID_MODE_CFG_ACT */ +/* + * LP_CMD_EN (R) + * + * enable the command transmission only in low-power mode + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK (0x200U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT (9U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT) + +/* + * FRAME_BTA_ACK_EN (R) + * + * enable the request for an acknowledge response at the end of a frame + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK (0x100U) +#define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT (8U) +#define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT) + +/* + * LP_HFP_EN (R) + * + * enable the returne to low-power inside the HFP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK (0x80U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT (7U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT) + +/* + * LP_HBP_EN (R) + * + * enable the returne to low-power inside the HBP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK (0x40U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT (6U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT) + +/* + * LP_VACT_EN (R) + * + * enable the returne to low-power inside the VACT period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK (0x20U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT (5U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT) + +/* + * LP_VFP_EN (R) + * + * enable the returne to low-power inside the VFP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK (0x10U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT (4U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT) + +/* + * LP_VBP_EN (R) + * + * enable the returne to low-power inside the VBP period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK (0x8U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT (3U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT) + +/* + * LP_VSA_EN (R) + * + * enable the returne to low-power inside the VSA period when timing allows + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK (0x4U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT (2U) +#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT) + +/* + * VID_MODE_TYPE (R) + * + * specifies the video mode transmission type + */ +#define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK (0x3U) +#define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT (0U) +#define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT) + +/* Bitfield definition for register: VID_PKT_SIZE_ACT */ +/* + * VID_PKT_SIZE (R) + * + * the number of pixels in a single video packet + */ +#define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK (0x3FFFU) +#define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT (0U) +#define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK) >> MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT) + +/* Bitfield definition for register: VID_NUM_CHUNKS_ACT */ +/* + * VID_NUM_CHUNKS (R) + * + * the number of chunks to be transmitted during a line period + */ +#define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK (0x1FFFU) +#define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT (0U) +#define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK) >> MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT) + +/* Bitfield definition for register: VID_NULL_SIZE_ACT */ +/* + * VID_NULL_SIZE (R) + * + * the number of bytes in side a null packet + */ +#define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK (0x1FFFU) +#define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT (0U) +#define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK) >> MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT) + +/* Bitfield definition for register: VID_HSA_TIME_ACT */ +/* + * VID_HSA_TIME (R) + * + * the horizontal synchronism active period in lane byte clock cycles + */ +#define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK (0xFFFU) +#define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT (0U) +#define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK) >> MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT) + +/* Bitfield definition for register: VID_HBP_TIME_ACT */ +/* + * VID_HBP_TIME (R) + * + * the horizontal back porch period in lane byte clock cycles + */ +#define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK (0xFFFU) +#define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT (0U) +#define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK) >> MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT) + +/* Bitfield definition for register: VID_HLINE_TIME_ACT */ +/* + * VID_HLINE_TIME (R) + * + * the size of total line: hsa+hbp+hact+hfp + */ +#define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK (0x7FFFU) +#define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT (0U) +#define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK) >> MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT) + +/* Bitfield definition for register: VID_VSA_LINES_ACT */ +/* + * VSA_LINES (R) + * + * vertical synchronism active period + */ +#define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK (0x3FFU) +#define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK) >> MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT) + +/* Bitfield definition for register: VID_VBP_LINES_ACT */ +/* + * VBP_LINES (R) + * + * vertical back porch period + */ +#define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK (0x3FFU) +#define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK) >> MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT) + +/* Bitfield definition for register: VID_VFP_LINES_ACT */ +/* + * VFP_LINES (R) + * + * vertical porch period + */ +#define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK (0x3FFU) +#define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK) >> MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT) + +/* Bitfield definition for register: VID_VACTIVE_LINES_ACT */ +/* + * V_ACTIVE_LINES (R) + * + * vertical active period + */ +#define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK (0x3FFFU) +#define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT (0U) +#define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK) >> MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT) + +/* Bitfield definition for register: VID_PKT_STATUS */ +/* + * DPI_BUFF_PLD_FULL (R) + * + * This bit indicates the full status of the payload internal buffer + * for video Mode. This bit is set to 0 for command Mode + */ +#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK (0x20000UL) +#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT (17U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT) + +/* + * DPI_BUFF_PLD_EMPTY (R) + * + * This bit indicates the empty status of the payload internal + * buffer for video Mode. This bit is set to 0 for command Mod + */ +#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK (0x10000UL) +#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT (16U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT) + +/* + * DPI_PLD_W_FULL (R) + * + * This bit indicates the full status of write payload FIFO for + * video Mode. This bit is set to 0 for command Mode + */ +#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK (0x8U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT (3U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT) + +/* + * DPI_PLD_W_EMPTY (R) + * + * This bit indicates the empty status of write payload FIFO for + * video Mode. This bit is set to 0 for command Mode + */ +#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK (0x4U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT (2U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT) + +/* + * DPI_CMD_W_FULL (R) + * + * This bit indicates the full status of write command FIFO for + * video Mode. This bit is set to 0 for command Mode + */ +#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK (0x2U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT (1U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT) + +/* + * DPI_CMD_W_EMPTY (R) + * + * This bit indicates the empty status of write command FIFO + * for video Mode. This bit is set to 0 for command Mode + */ +#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK (0x1U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT (0U) +#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT) + +/* Bitfield definition for register: SDF_3D_ACT */ +/* + * SEND_3D_CFG (R) + * + * When set, causes the next VSS packet to include 3D control + * payload in every VSS packet. + */ +#define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK (0x10000UL) +#define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT (16U) +#define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK) >> MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT) + +/* + * RIGHT_FIRST (R) + * + * This bit specifies the left/right order + */ +#define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK (0x20U) +#define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT (5U) +#define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK) >> MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT) + +/* + * SECOND_VSYNC (R) + * + * This field specifies whether there is a second VSYNC pulse + * between Left and Right Images, when 3D Image Format is + * Frame-based + */ +#define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK (0x10U) +#define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT (4U) +#define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK) >> MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT) + +/* + * FORMAT_3D (R) + * + * This field specifies 3D Image Format + */ +#define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK (0xCU) +#define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT (2U) +#define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK) >> MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT) + +/* + * MODE_3D (R) + * + * This field specifies 3D Mode On/Off and Display Orientation + */ +#define MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK (0x3U) +#define MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT (0U) +#define MIPI_DSI_SDF_3D_ACT_MODE_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK) >> MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT) + + + + +#endif /* HPM_MIPI_DSI_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_mmc_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_mmc_regs.h new file mode 100644 index 00000000..06fc885a --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_mmc_regs.h @@ -0,0 +1,1621 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_MMC_H +#define HPM_MMC_H + +typedef struct { + __RW uint32_t CR; /* 0x0: Control Register */ + __RW uint32_t STA; /* 0x4: Status Register */ + __RW uint32_t INT_EN; /* 0x8: Interrupt Enable Register */ + __RW uint32_t SYSCLK_FREQ; /* 0xC: System Clock Frequency Register */ + __RW uint32_t SYSCLK_PERIOD; /* 0x10: System Clock Period Register */ + __RW uint32_t OOSYNC_THETA_THR; /* 0x14: Position Out-Of-Sync Threshold Regster */ + __RW uint32_t DISCRETECFG0; /* 0x18: Discrete Mode Configuration 0 Register */ + __RW uint32_t DISCRETECFG1; /* 0x1C: Discrete Mode Configuration 1 Register */ + __RW uint32_t CONTCFG0; /* 0x20: Continuous Mode Configuration 0 Register */ + __RW uint32_t INI_POS_TIME; /* 0x24: The destined timestamp register for position initialization */ + __RW uint32_t INI_POS; /* 0x28: The destined position register for position initialization */ + __RW uint32_t INI_REV; /* 0x2C: The destined revolution register for position initialization */ + __RW uint32_t INI_SPEED; /* 0x30: The destined speed register for position initialization */ + __RW uint32_t INI_ACCEL; /* 0x34: The destined accelerator register for position initialization */ + __RW uint32_t INI_COEF_TIME; /* 0x38: The destined timestamp register for coefficients initialization */ + __RW uint32_t INI_PCOEF; /* 0x3C: The destined coefficient P register for coefficients initialization */ + __RW uint32_t INI_ICOEF; /* 0x40: The destined coefficient I register for coefficients initialization */ + __RW uint32_t INI_ACOEF; /* 0x44: The destined coefficient A register for coefficients initialization */ + __R uint32_t ESTM_TIM; /* 0x48: The timestamp register for internal estimation */ + __R uint32_t ESTM_POS; /* 0x4C: The position register for the internal estimation */ + __R uint32_t ESTM_REV; /* 0x50: The revolution register for the internal estimation */ + __R uint32_t ESTM_SPEED; /* 0x54: The speed register for the internal estimation */ + __R uint32_t ESTM_ACCEL; /* 0x58: The accelerator register for theinternal estimation */ + __R uint32_t CUR_PCOEF; /* 0x5C: The coefficient P register for the internal estimation */ + __R uint32_t CUR_ICOEF; /* 0x60: The coefficient I register for the internal estimation */ + __R uint32_t CUR_ACOEF; /* 0x64: The coefficient A register for the internal estimation */ + __RW uint32_t INI_DELTA_POS_TIME; /* 0x68: The destined timestamp register for delta position initialization */ + __RW uint32_t INI_DELTA_POS; /* 0x6C: The destined delta position register for delta position initialization */ + __RW uint32_t INI_DELTA_REV; /* 0x70: The destined delta revolution register for delta position initialization */ + __RW uint32_t INI_DELTA_SPEED; /* 0x74: The destined delta speed register for delta position initialization */ + __RW uint32_t INI_DELTA_ACCEL; /* 0x78: The destined delta accelerator register for delta position initialization */ + __R uint8_t RESERVED0[4]; /* 0x7C - 0x7F: Reserved */ + __RW uint32_t POS_TRG_CFG; /* 0x80: Tracking Configuration pos trigger cfg */ + __RW uint32_t POS_TRG_POS_THR; /* 0x84: Tracking Configuration position threshold */ + __RW uint32_t POS_TRG_REV_THR; /* 0x88: Tracking Configuration revolution threshold */ + __RW uint32_t SPEED_TRG_CFG; /* 0x8C: Tracking Configuration speed trigger cfg */ + __RW uint32_t SPEED_TRG_THR; /* 0x90: Tracking Configuration speed threshold */ + __R uint8_t RESERVED1[12]; /* 0x94 - 0x9F: Reserved */ + struct { + __RW uint32_t ERR_THR; /* 0xA0: Tracking Configuration coef trigger cfg */ + __RW uint32_t P; /* 0xA4: Tracking Configuration coef trigger cfg P */ + __RW uint32_t I; /* 0xA8: Tracking Configuration coef trigger cfg I */ + __RW uint32_t A; /* 0xAC: Tracking Configuration coef trigger cfg A */ + __RW uint32_t TIME; /* 0xB0: Tracking Configuration coef trigger cfg time */ + } COEF_TRG_CFG[3]; + __R uint8_t RESERVED2[36]; /* 0xDC - 0xFF: Reserved */ + struct { + __RW uint32_t BR_CTRL; /* 0x100: Prediction Control Register */ + __RW uint32_t BR_TIMEOFF; /* 0x104: Prediction Timing Offset Register */ + __RW uint32_t BR_TRG_PERIOD; /* 0x108: Prediction Triggering Period Offset Register */ + __RW uint32_t BR_TRG_F_TIME; /* 0x10C: Prediction Triggering First Offset Register */ + __RW uint32_t BR_ST; /* 0x110: Prediction Status Register */ + __R uint8_t RESERVED0[44]; /* 0x114 - 0x13F: Reserved */ + __RW uint32_t BR_TRG_POS_CFG; /* 0x140: Prediction Configuration postion trigger cfg */ + __RW uint32_t BR_TRG_POS_THR; /* 0x144: Prediction Configuration postion threshold */ + __RW uint32_t BR_TRG_REV_THR; /* 0x148: Prediction Configuration revolutiom threshold */ + __RW uint32_t BR_TRG_SPEED_CFG; /* 0x14C: Prediction Configuration speed trigger cfg */ + __RW uint32_t BR_TRG_SPEED_THR; /* 0x150: Prediction Configuration speed threshold */ + __R uint8_t RESERVED1[108]; /* 0x154 - 0x1BF: Reserved */ + __RW uint32_t BR_INI_POS_TIME; /* 0x1C0: Initialization timestamp for open-loop mode */ + __RW uint32_t BR_INI_POS; /* 0x1C4: Initialization position for open-loop mode */ + __RW uint32_t BR_INI_REV; /* 0x1C8: Initialization revolution for open-loop mode */ + __RW uint32_t BR_INI_SPEED; /* 0x1CC: Initialization speed for open-loop mode */ + __RW uint32_t BR_INI_ACCEL; /* 0x1D0: Initialization acceleration for open-loop mode */ + __RW uint32_t BR_INI_DELTA_POS_TIME; /* 0x1D4: Initialization timestamp for delta mode in prediction mode */ + __RW uint32_t BR_INI_DELTA_POS; /* 0x1D8: Initialization delta position for delta mode in prediction mode */ + __RW uint32_t BR_INI_DELTA_REV; /* 0x1DC: Initialization delta revolution for delta mode in prediction mode */ + __RW uint32_t BR_INI_DELTA_SPEED; /* 0x1E0: Initialization delta speed for delta mode in prediction mode */ + __RW uint32_t BR_INI_DELTA_ACCEL; /* 0x1E4: Initialization delta acceleration for delta mode in prediction mode */ + __R uint8_t RESERVED2[4]; /* 0x1E8 - 0x1EB: Reserved */ + __R uint32_t BR_CUR_POS_TIME; /* 0x1EC: Monitor of the output timestamp */ + __R uint32_t BR_CUR_POS; /* 0x1F0: Monitor of the output position */ + __R uint32_t BR_CUR_REV; /* 0x1F4: Monitor of the output revolution */ + __R uint32_t BR_CUR_SPEED; /* 0x1F8: Monitor of the output speed */ + __R uint32_t BR_CUR_ACCEL; /* 0x1FC: Monitor of the output acceleration */ + } BR[2]; + __R uint32_t BK0_TIMESTAMP; /* 0x300: Monitor of the just received input timestamp for tracing logic */ + __R uint32_t BK0_POSITION; /* 0x304: Monitor of the just received input position for tracing logic */ + __R uint32_t BK0_REVOLUTION; /* 0x308: Monitor of the just received input revolution for tracing logic */ + __R uint32_t BK0_SPEED; /* 0x30C: Monitor of the just received input speed for tracing logic */ + __R uint32_t BK0_ACCELERATOR; /* 0x310: Monitor of the just received input acceleration for tracing logic */ + __R uint8_t RESERVED3[12]; /* 0x314 - 0x31F: Reserved */ + __R uint32_t BK1_TIMESTAMP; /* 0x320: Monitor of the previous received input timestamp for tracing logic */ + __R uint32_t BK1_POSITION; /* 0x324: Monitor of the previous received input position for tracing logic */ + __R uint32_t BK1_REVOLUTION; /* 0x328: Monitor of the previous received input revolution for tracing logic */ + __R uint32_t BK1_SPEED; /* 0x32C: Monitor of the previous received input speed for tracing logic */ + __R uint32_t BK1_ACCELERATOR; /* 0x330: Monitor of the previous received input acceleration for tracing logic */ +} MMC_Type; + + +/* Bitfield definition for register: CR */ +/* + * SFTRST (RW) + * + * Software reset, high active. When write 1 ,all internal logical will be reset. + * 0b - No action + * 1b - All MMC internal registers are forced into their reset state. Interface registers are not affected. + */ +#define MMC_CR_SFTRST_MASK (0x80000000UL) +#define MMC_CR_SFTRST_SHIFT (31U) +#define MMC_CR_SFTRST_SET(x) (((uint32_t)(x) << MMC_CR_SFTRST_SHIFT) & MMC_CR_SFTRST_MASK) +#define MMC_CR_SFTRST_GET(x) (((uint32_t)(x) & MMC_CR_SFTRST_MASK) >> MMC_CR_SFTRST_SHIFT) + +/* + * INI_BR0_POS_REQ (RW) + * + * Auto clear. Only effective in open_loop mode. + */ +#define MMC_CR_INI_BR0_POS_REQ_MASK (0x20000000UL) +#define MMC_CR_INI_BR0_POS_REQ_SHIFT (29U) +#define MMC_CR_INI_BR0_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_BR0_POS_REQ_SHIFT) & MMC_CR_INI_BR0_POS_REQ_MASK) +#define MMC_CR_INI_BR0_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_BR0_POS_REQ_MASK) >> MMC_CR_INI_BR0_POS_REQ_SHIFT) + +/* + * INI_BR1_POS_REQ (RW) + * + * Auto clear. Only effective in open_loop mode. + */ +#define MMC_CR_INI_BR1_POS_REQ_MASK (0x10000000UL) +#define MMC_CR_INI_BR1_POS_REQ_SHIFT (28U) +#define MMC_CR_INI_BR1_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_BR1_POS_REQ_SHIFT) & MMC_CR_INI_BR1_POS_REQ_MASK) +#define MMC_CR_INI_BR1_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_BR1_POS_REQ_MASK) >> MMC_CR_INI_BR1_POS_REQ_SHIFT) + +/* + * FRCACCELZERO (RW) + * + * Zeroise the accelerator calculation. + */ +#define MMC_CR_FRCACCELZERO_MASK (0x8000000UL) +#define MMC_CR_FRCACCELZERO_SHIFT (27U) +#define MMC_CR_FRCACCELZERO_SET(x) (((uint32_t)(x) << MMC_CR_FRCACCELZERO_SHIFT) & MMC_CR_FRCACCELZERO_MASK) +#define MMC_CR_FRCACCELZERO_GET(x) (((uint32_t)(x) & MMC_CR_FRCACCELZERO_MASK) >> MMC_CR_FRCACCELZERO_SHIFT) + +/* + * MS_COEF_EN (RW) + * + * Multiple Coefficients Enable + */ +#define MMC_CR_MS_COEF_EN_MASK (0x4000000UL) +#define MMC_CR_MS_COEF_EN_SHIFT (26U) +#define MMC_CR_MS_COEF_EN_SET(x) (((uint32_t)(x) << MMC_CR_MS_COEF_EN_SHIFT) & MMC_CR_MS_COEF_EN_MASK) +#define MMC_CR_MS_COEF_EN_GET(x) (((uint32_t)(x) & MMC_CR_MS_COEF_EN_MASK) >> MMC_CR_MS_COEF_EN_SHIFT) + +/* + * INI_DELTA_POS_TRG_TYPE (RW) + * + * 0: Time Stamp in the configuration + * 1: Risedge of In Trg[0] + * 2: Risedge of In Trg[1] + * 3: Risedge of out trg[0] + * 4: Risedge of out trg[1] + * 5: triggered by self position trigger + * 6: triggered by self speed trigger + * Otherser: no function + */ +#define MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK (0x3800000UL) +#define MMC_CR_INI_DELTA_POS_TRG_TYPE_SHIFT (23U) +#define MMC_CR_INI_DELTA_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_CR_INI_DELTA_POS_TRG_TYPE_SHIFT) & MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK) +#define MMC_CR_INI_DELTA_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK) >> MMC_CR_INI_DELTA_POS_TRG_TYPE_SHIFT) + +/* + * INI_POS_TRG_TYPE (RW) + * + * 0: Time Stamp in the configuration + * 1: Risedge of In Trg[0] + * 2: Risedge of In Trg[1] + * 3: Risedge of out trg[0] + * 4: Risedge of out trg[1] + * 5: triggered by self position trigger + * 6: triggered by self speed trigger + * Otherser: no function + */ +#define MMC_CR_INI_POS_TRG_TYPE_MASK (0x700000UL) +#define MMC_CR_INI_POS_TRG_TYPE_SHIFT (20U) +#define MMC_CR_INI_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_CR_INI_POS_TRG_TYPE_SHIFT) & MMC_CR_INI_POS_TRG_TYPE_MASK) +#define MMC_CR_INI_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_CR_INI_POS_TRG_TYPE_MASK) >> MMC_CR_INI_POS_TRG_TYPE_SHIFT) + +/* + * INI_DELTA_POS_CMD_MSK (RW) + * + * 1: change + * 0: won't change + * bit 3: for delta accel + * bit 2: for delta speed + * bit 1: for delta revolution + * bit 0: for delta position + */ +#define MMC_CR_INI_DELTA_POS_CMD_MSK_MASK (0xF0000UL) +#define MMC_CR_INI_DELTA_POS_CMD_MSK_SHIFT (16U) +#define MMC_CR_INI_DELTA_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_CR_INI_DELTA_POS_CMD_MSK_SHIFT) & MMC_CR_INI_DELTA_POS_CMD_MSK_MASK) +#define MMC_CR_INI_DELTA_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_CR_INI_DELTA_POS_CMD_MSK_MASK) >> MMC_CR_INI_DELTA_POS_CMD_MSK_SHIFT) + +/* + * INI_DELTA_POS_REQ (RW) + * + * 1: Command to reload the delta pos. Auto clear + * 0: + */ +#define MMC_CR_INI_DELTA_POS_REQ_MASK (0x8000U) +#define MMC_CR_INI_DELTA_POS_REQ_SHIFT (15U) +#define MMC_CR_INI_DELTA_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_DELTA_POS_REQ_SHIFT) & MMC_CR_INI_DELTA_POS_REQ_MASK) +#define MMC_CR_INI_DELTA_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_DELTA_POS_REQ_MASK) >> MMC_CR_INI_DELTA_POS_REQ_SHIFT) + +/* + * OPEN_LOOP_MODE (RW) + * + * 1: in open loop mode + * 0: not in open loop mode + */ +#define MMC_CR_OPEN_LOOP_MODE_MASK (0x4000U) +#define MMC_CR_OPEN_LOOP_MODE_SHIFT (14U) +#define MMC_CR_OPEN_LOOP_MODE_SET(x) (((uint32_t)(x) << MMC_CR_OPEN_LOOP_MODE_SHIFT) & MMC_CR_OPEN_LOOP_MODE_MASK) +#define MMC_CR_OPEN_LOOP_MODE_GET(x) (((uint32_t)(x) & MMC_CR_OPEN_LOOP_MODE_MASK) >> MMC_CR_OPEN_LOOP_MODE_SHIFT) + +/* + * POS_TYPE (RW) + * + * 1: 32-bit for rev+pos, with each element occupying 16 bits + * 0: 32-bit for rev, and 32 bit for pos + * When CR[MANUAL_IO]==1, + * 1: means that the INI_POS is acting as INI_POS cmds + * 0: means that the INI_POS is simulating the input of iposition and itimestamp + */ +#define MMC_CR_POS_TYPE_MASK (0x2000U) +#define MMC_CR_POS_TYPE_SHIFT (13U) +#define MMC_CR_POS_TYPE_SET(x) (((uint32_t)(x) << MMC_CR_POS_TYPE_SHIFT) & MMC_CR_POS_TYPE_MASK) +#define MMC_CR_POS_TYPE_GET(x) (((uint32_t)(x) & MMC_CR_POS_TYPE_MASK) >> MMC_CR_POS_TYPE_SHIFT) + +/* + * INI_POS_CMD_MSK (RW) + * + * 1: change + * 0: won't change + * bit 3: for accel + * bit 2: for speed + * bit 1: for revolution + * bit 0: for position + */ +#define MMC_CR_INI_POS_CMD_MSK_MASK (0x1E00U) +#define MMC_CR_INI_POS_CMD_MSK_SHIFT (9U) +#define MMC_CR_INI_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_CR_INI_POS_CMD_MSK_SHIFT) & MMC_CR_INI_POS_CMD_MSK_MASK) +#define MMC_CR_INI_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_CR_INI_POS_CMD_MSK_MASK) >> MMC_CR_INI_POS_CMD_MSK_SHIFT) + +/* + * INI_POS_REQ (RW) + * + * 1: Command to reload the positions. Auto clear + * 0: + */ +#define MMC_CR_INI_POS_REQ_MASK (0x100U) +#define MMC_CR_INI_POS_REQ_SHIFT (8U) +#define MMC_CR_INI_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_POS_REQ_SHIFT) & MMC_CR_INI_POS_REQ_MASK) +#define MMC_CR_INI_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_POS_REQ_MASK) >> MMC_CR_INI_POS_REQ_SHIFT) + +/* + * INI_COEFS_CMD_MSK (RW) + * + * 1: change + * 0: won't change + * bit 2: for ACOEF + * bit 1: for ICOEF + * bit 0: for PCOEF + */ +#define MMC_CR_INI_COEFS_CMD_MSK_MASK (0xE0U) +#define MMC_CR_INI_COEFS_CMD_MSK_SHIFT (5U) +#define MMC_CR_INI_COEFS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_CR_INI_COEFS_CMD_MSK_SHIFT) & MMC_CR_INI_COEFS_CMD_MSK_MASK) +#define MMC_CR_INI_COEFS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_CR_INI_COEFS_CMD_MSK_MASK) >> MMC_CR_INI_COEFS_CMD_MSK_SHIFT) + +/* + * INI_COEFS_CMD (RW) + * + * 1: Command to reload the coefs. Auto clear + * 0: + */ +#define MMC_CR_INI_COEFS_CMD_MASK (0x10U) +#define MMC_CR_INI_COEFS_CMD_SHIFT (4U) +#define MMC_CR_INI_COEFS_CMD_SET(x) (((uint32_t)(x) << MMC_CR_INI_COEFS_CMD_SHIFT) & MMC_CR_INI_COEFS_CMD_MASK) +#define MMC_CR_INI_COEFS_CMD_GET(x) (((uint32_t)(x) & MMC_CR_INI_COEFS_CMD_MASK) >> MMC_CR_INI_COEFS_CMD_SHIFT) + +/* + * SHADOW_RD_REQ (RW) + * + * 1: Shadow Request for read of tracking parameters. Auto clear + * 0: + */ +#define MMC_CR_SHADOW_RD_REQ_MASK (0x8U) +#define MMC_CR_SHADOW_RD_REQ_SHIFT (3U) +#define MMC_CR_SHADOW_RD_REQ_SET(x) (((uint32_t)(x) << MMC_CR_SHADOW_RD_REQ_SHIFT) & MMC_CR_SHADOW_RD_REQ_MASK) +#define MMC_CR_SHADOW_RD_REQ_GET(x) (((uint32_t)(x) & MMC_CR_SHADOW_RD_REQ_MASK) >> MMC_CR_SHADOW_RD_REQ_SHIFT) + +/* + * ADJOP (RW) + * + * 1: use the input iposition whenever a new iposition comes, and force the predicted output stop at the boundaries. + * 0: Continuous tracking mode, without any boundary check + */ +#define MMC_CR_ADJOP_MASK (0x4U) +#define MMC_CR_ADJOP_SHIFT (2U) +#define MMC_CR_ADJOP_SET(x) (((uint32_t)(x) << MMC_CR_ADJOP_SHIFT) & MMC_CR_ADJOP_MASK) +#define MMC_CR_ADJOP_GET(x) (((uint32_t)(x) & MMC_CR_ADJOP_MASK) >> MMC_CR_ADJOP_SHIFT) + +/* + * DISCRETETRC (RW) + * + * 1: Discrete position input + * 0: Continuous position input + */ +#define MMC_CR_DISCRETETRC_MASK (0x2U) +#define MMC_CR_DISCRETETRC_SHIFT (1U) +#define MMC_CR_DISCRETETRC_SET(x) (((uint32_t)(x) << MMC_CR_DISCRETETRC_SHIFT) & MMC_CR_DISCRETETRC_MASK) +#define MMC_CR_DISCRETETRC_GET(x) (((uint32_t)(x) & MMC_CR_DISCRETETRC_MASK) >> MMC_CR_DISCRETETRC_SHIFT) + +/* + * MOD_EN (RW) + * + * Module Enable + */ +#define MMC_CR_MOD_EN_MASK (0x1U) +#define MMC_CR_MOD_EN_SHIFT (0U) +#define MMC_CR_MOD_EN_SET(x) (((uint32_t)(x) << MMC_CR_MOD_EN_SHIFT) & MMC_CR_MOD_EN_MASK) +#define MMC_CR_MOD_EN_GET(x) (((uint32_t)(x) & MMC_CR_MOD_EN_MASK) >> MMC_CR_MOD_EN_SHIFT) + +/* Bitfield definition for register: STA */ +/* + * ERR_ID (RO) + * + * Tracking ERR_ID + */ +#define MMC_STA_ERR_ID_MASK (0xF0000000UL) +#define MMC_STA_ERR_ID_SHIFT (28U) +#define MMC_STA_ERR_ID_GET(x) (((uint32_t)(x) & MMC_STA_ERR_ID_MASK) >> MMC_STA_ERR_ID_SHIFT) + +/* + * SPEED_TRG_VALID (W1C) + * + * W1C + */ +#define MMC_STA_SPEED_TRG_VALID_MASK (0x400U) +#define MMC_STA_SPEED_TRG_VALID_SHIFT (10U) +#define MMC_STA_SPEED_TRG_VALID_SET(x) (((uint32_t)(x) << MMC_STA_SPEED_TRG_VALID_SHIFT) & MMC_STA_SPEED_TRG_VALID_MASK) +#define MMC_STA_SPEED_TRG_VALID_GET(x) (((uint32_t)(x) & MMC_STA_SPEED_TRG_VALID_MASK) >> MMC_STA_SPEED_TRG_VALID_SHIFT) + +/* + * POS_TRG_VALID (W1C) + * + * W1C + */ +#define MMC_STA_POS_TRG_VALID_MASK (0x200U) +#define MMC_STA_POS_TRG_VALID_SHIFT (9U) +#define MMC_STA_POS_TRG_VALID_SET(x) (((uint32_t)(x) << MMC_STA_POS_TRG_VALID_SHIFT) & MMC_STA_POS_TRG_VALID_MASK) +#define MMC_STA_POS_TRG_VALID_GET(x) (((uint32_t)(x) & MMC_STA_POS_TRG_VALID_MASK) >> MMC_STA_POS_TRG_VALID_SHIFT) + +/* + * INI_DELTA_POS_REQ_CMD_DONE (W1C) + * + * W1C + */ +#define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_MASK (0x100U) +#define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SHIFT (8U) +#define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_MASK) +#define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SHIFT) + +/* + * INI_BR0_POS_REQ_CMD_DONE (W1C) + * + * W1C + */ +#define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_MASK (0x80U) +#define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SHIFT (7U) +#define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_BR0_POS_REQ_CMD_DONE_MASK) +#define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_BR0_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SHIFT) + +/* + * INI_BR1_POS_REQ_CMD_DONE (W1C) + * + * W1C + */ +#define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_MASK (0x40U) +#define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SHIFT (6U) +#define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_BR1_POS_REQ_CMD_DONE_MASK) +#define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_BR1_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SHIFT) + +/* + * IDLE (RO) + * + * Tracking Module in Idle status + */ +#define MMC_STA_IDLE_MASK (0x20U) +#define MMC_STA_IDLE_SHIFT (5U) +#define MMC_STA_IDLE_GET(x) (((uint32_t)(x) & MMC_STA_IDLE_MASK) >> MMC_STA_IDLE_SHIFT) + +/* + * OOSYNC (W1C) + * + * Tracking module out-of sync. W1C + */ +#define MMC_STA_OOSYNC_MASK (0x10U) +#define MMC_STA_OOSYNC_SHIFT (4U) +#define MMC_STA_OOSYNC_SET(x) (((uint32_t)(x) << MMC_STA_OOSYNC_SHIFT) & MMC_STA_OOSYNC_MASK) +#define MMC_STA_OOSYNC_GET(x) (((uint32_t)(x) & MMC_STA_OOSYNC_MASK) >> MMC_STA_OOSYNC_SHIFT) + +/* + * INI_POS_REQ_CMD_DONE (W1C) + * + * W1C + */ +#define MMC_STA_INI_POS_REQ_CMD_DONE_MASK (0x4U) +#define MMC_STA_INI_POS_REQ_CMD_DONE_SHIFT (2U) +#define MMC_STA_INI_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_POS_REQ_CMD_DONE_MASK) +#define MMC_STA_INI_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_POS_REQ_CMD_DONE_SHIFT) + +/* + * INI_COEFS_CMD_DONE (W1C) + * + * W1C + */ +#define MMC_STA_INI_COEFS_CMD_DONE_MASK (0x2U) +#define MMC_STA_INI_COEFS_CMD_DONE_SHIFT (1U) +#define MMC_STA_INI_COEFS_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_COEFS_CMD_DONE_SHIFT) & MMC_STA_INI_COEFS_CMD_DONE_MASK) +#define MMC_STA_INI_COEFS_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_COEFS_CMD_DONE_MASK) >> MMC_STA_INI_COEFS_CMD_DONE_SHIFT) + +/* + * SHADOW_RD_DONE (RO) + * + * Shadow ready for read. Auto cleared by setting CR[SHADOW_RD_REQ] as 1 + */ +#define MMC_STA_SHADOW_RD_DONE_MASK (0x1U) +#define MMC_STA_SHADOW_RD_DONE_SHIFT (0U) +#define MMC_STA_SHADOW_RD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_SHADOW_RD_DONE_MASK) >> MMC_STA_SHADOW_RD_DONE_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * SPEED_TRG_VLD_IE (RW) + * + * Interrupt Enable for SPEED_TRG_VALID + */ +#define MMC_INT_EN_SPEED_TRG_VLD_IE_MASK (0x400U) +#define MMC_INT_EN_SPEED_TRG_VLD_IE_SHIFT (10U) +#define MMC_INT_EN_SPEED_TRG_VLD_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_SPEED_TRG_VLD_IE_SHIFT) & MMC_INT_EN_SPEED_TRG_VLD_IE_MASK) +#define MMC_INT_EN_SPEED_TRG_VLD_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_SPEED_TRG_VLD_IE_MASK) >> MMC_INT_EN_SPEED_TRG_VLD_IE_SHIFT) + +/* + * POS_TRG_VLD_IE (RW) + * + * Interrupt Enable for POS_TRG_VALID + */ +#define MMC_INT_EN_POS_TRG_VLD_IE_MASK (0x200U) +#define MMC_INT_EN_POS_TRG_VLD_IE_SHIFT (9U) +#define MMC_INT_EN_POS_TRG_VLD_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_POS_TRG_VLD_IE_SHIFT) & MMC_INT_EN_POS_TRG_VLD_IE_MASK) +#define MMC_INT_EN_POS_TRG_VLD_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_POS_TRG_VLD_IE_MASK) >> MMC_INT_EN_POS_TRG_VLD_IE_SHIFT) + +/* + * INI_DELTA_POS_REQ_CMD_DONE_IE (RW) + * + * Interrupt Enable for INI_DELTA_POS_REQ_CMD_DONE + */ +#define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_MASK (0x100U) +#define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SHIFT (8U) +#define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_MASK) +#define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SHIFT) + +/* + * INI_BR0_POS_REQ_CMD_DONE_IE (RW) + * + * Interrupt Enable for INI_BR0_POS_REQ_CMD_DONE + */ +#define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_MASK (0x80U) +#define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SHIFT (7U) +#define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_MASK) +#define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SHIFT) + +/* + * INI_BR1_POS_REQ_CMD_DONE_IE (RW) + * + * Interrupt Enable for INI_BR1_POS_REQ_CMD_DONE + */ +#define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_MASK (0x40U) +#define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SHIFT (6U) +#define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_MASK) +#define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SHIFT) + +/* + * OOSYNC_IE (RW) + * + * Interrupt Enable for OOSYNC + */ +#define MMC_INT_EN_OOSYNC_IE_MASK (0x10U) +#define MMC_INT_EN_OOSYNC_IE_SHIFT (4U) +#define MMC_INT_EN_OOSYNC_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_OOSYNC_IE_SHIFT) & MMC_INT_EN_OOSYNC_IE_MASK) +#define MMC_INT_EN_OOSYNC_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_OOSYNC_IE_MASK) >> MMC_INT_EN_OOSYNC_IE_SHIFT) + +/* + * INI_POS_REQ_CMD_DONE_IE (RW) + * + * Interrupt Enable for INI_POS_REQ_CMD_DONE + */ +#define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_MASK (0x4U) +#define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SHIFT (2U) +#define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_MASK) +#define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SHIFT) + +/* + * INI_COEFS_CMD_DONE_IE (RW) + * + * Interrupt Enable for INI_COEFS_CMD_DONE + */ +#define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_MASK (0x2U) +#define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SHIFT (1U) +#define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_COEFS_CMD_DONE_IE_MASK) +#define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_COEFS_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SHIFT) + +/* + * SHADOW_RD_DONE_IE (RW) + * + * Interrupt Enable for SHADOW_RD_DONE + */ +#define MMC_INT_EN_SHADOW_RD_DONE_IE_MASK (0x1U) +#define MMC_INT_EN_SHADOW_RD_DONE_IE_SHIFT (0U) +#define MMC_INT_EN_SHADOW_RD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_SHADOW_RD_DONE_IE_SHIFT) & MMC_INT_EN_SHADOW_RD_DONE_IE_MASK) +#define MMC_INT_EN_SHADOW_RD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_SHADOW_RD_DONE_IE_MASK) >> MMC_INT_EN_SHADOW_RD_DONE_IE_SHIFT) + +/* Bitfield definition for register: SYSCLK_FREQ */ +/* + * VAL (RW) + * + * system clock frequency, ufix<32, 0> + */ +#define MMC_SYSCLK_FREQ_VAL_MASK (0xFFFFFFFFUL) +#define MMC_SYSCLK_FREQ_VAL_SHIFT (0U) +#define MMC_SYSCLK_FREQ_VAL_SET(x) (((uint32_t)(x) << MMC_SYSCLK_FREQ_VAL_SHIFT) & MMC_SYSCLK_FREQ_VAL_MASK) +#define MMC_SYSCLK_FREQ_VAL_GET(x) (((uint32_t)(x) & MMC_SYSCLK_FREQ_VAL_MASK) >> MMC_SYSCLK_FREQ_VAL_SHIFT) + +/* Bitfield definition for register: SYSCLK_PERIOD */ +/* + * VAL (RW) + * + * round( the value of clock period * (2^24)*(2^20) ), ufix<32, 0> + */ +#define MMC_SYSCLK_PERIOD_VAL_MASK (0xFFFFFFFFUL) +#define MMC_SYSCLK_PERIOD_VAL_SHIFT (0U) +#define MMC_SYSCLK_PERIOD_VAL_SET(x) (((uint32_t)(x) << MMC_SYSCLK_PERIOD_VAL_SHIFT) & MMC_SYSCLK_PERIOD_VAL_MASK) +#define MMC_SYSCLK_PERIOD_VAL_GET(x) (((uint32_t)(x) & MMC_SYSCLK_PERIOD_VAL_MASK) >> MMC_SYSCLK_PERIOD_VAL_SHIFT) + +/* Bitfield definition for register: OOSYNC_THETA_THR */ +/* + * VAL (RW) + * + * the threshold of theta difference between actual and prediction for out-of-sync determination，ufix<32, 32> + */ +#define MMC_OOSYNC_THETA_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_OOSYNC_THETA_THR_VAL_SHIFT (0U) +#define MMC_OOSYNC_THETA_THR_VAL_SET(x) (((uint32_t)(x) << MMC_OOSYNC_THETA_THR_VAL_SHIFT) & MMC_OOSYNC_THETA_THR_VAL_MASK) +#define MMC_OOSYNC_THETA_THR_VAL_GET(x) (((uint32_t)(x) & MMC_OOSYNC_THETA_THR_VAL_MASK) >> MMC_OOSYNC_THETA_THR_VAL_SHIFT) + +/* Bitfield definition for register: DISCRETECFG0 */ +/* + * POSMAX (RW) + * + * Max ID Of Lines. For example-1, for 512 lines, it is 511. ufix<32, 0> + */ +#define MMC_DISCRETECFG0_POSMAX_MASK (0xFFFFFUL) +#define MMC_DISCRETECFG0_POSMAX_SHIFT (0U) +#define MMC_DISCRETECFG0_POSMAX_SET(x) (((uint32_t)(x) << MMC_DISCRETECFG0_POSMAX_SHIFT) & MMC_DISCRETECFG0_POSMAX_MASK) +#define MMC_DISCRETECFG0_POSMAX_GET(x) (((uint32_t)(x) & MMC_DISCRETECFG0_POSMAX_MASK) >> MMC_DISCRETECFG0_POSMAX_SHIFT) + +/* Bitfield definition for register: DISCRETECFG1 */ +/* + * INV_POSMAX (RW) + * + * discrete mode: ufix<32, 0> of 1/(Number Of Lines) + * continuous mode: the max delta for tracking from the last received position, ufix<32, 32> + */ +#define MMC_DISCRETECFG1_INV_POSMAX_MASK (0xFFFFFFFFUL) +#define MMC_DISCRETECFG1_INV_POSMAX_SHIFT (0U) +#define MMC_DISCRETECFG1_INV_POSMAX_SET(x) (((uint32_t)(x) << MMC_DISCRETECFG1_INV_POSMAX_SHIFT) & MMC_DISCRETECFG1_INV_POSMAX_MASK) +#define MMC_DISCRETECFG1_INV_POSMAX_GET(x) (((uint32_t)(x) & MMC_DISCRETECFG1_INV_POSMAX_MASK) >> MMC_DISCRETECFG1_INV_POSMAX_SHIFT) + +/* Bitfield definition for register: CONTCFG0 */ +/* + * HALF_CIRC_THETA (RW) + * + * the theta for cal the clockwise or anticlockwise rotation between two adjacent inputs, ufix<32, 32> + */ +#define MMC_CONTCFG0_HALF_CIRC_THETA_MASK (0xFFFFFFFFUL) +#define MMC_CONTCFG0_HALF_CIRC_THETA_SHIFT (0U) +#define MMC_CONTCFG0_HALF_CIRC_THETA_SET(x) (((uint32_t)(x) << MMC_CONTCFG0_HALF_CIRC_THETA_SHIFT) & MMC_CONTCFG0_HALF_CIRC_THETA_MASK) +#define MMC_CONTCFG0_HALF_CIRC_THETA_GET(x) (((uint32_t)(x) & MMC_CONTCFG0_HALF_CIRC_THETA_MASK) >> MMC_CONTCFG0_HALF_CIRC_THETA_SHIFT) + +/* Bitfield definition for register: INI_POS_TIME */ +/* + * VAL (RW) + * + * indicate the time to change the values. + * 0: instant change + */ +#define MMC_INI_POS_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_POS_TIME_VAL_SHIFT (0U) +#define MMC_INI_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_INI_POS_TIME_VAL_SHIFT) & MMC_INI_POS_TIME_VAL_MASK) +#define MMC_INI_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_INI_POS_TIME_VAL_MASK) >> MMC_INI_POS_TIME_VAL_SHIFT) + +/* Bitfield definition for register: INI_POS */ +/* + * VAL (RW) + * + * the value； + * continuous mode: ufix<32, 32> + */ +#define MMC_INI_POS_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_POS_VAL_SHIFT (0U) +#define MMC_INI_POS_VAL_SET(x) (((uint32_t)(x) << MMC_INI_POS_VAL_SHIFT) & MMC_INI_POS_VAL_MASK) +#define MMC_INI_POS_VAL_GET(x) (((uint32_t)(x) & MMC_INI_POS_VAL_MASK) >> MMC_INI_POS_VAL_SHIFT) + +/* Bitfield definition for register: INI_REV */ +/* + * VAL (RW) + * + * the value； + * continuous mode: ufix<32, 0> + */ +#define MMC_INI_REV_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_REV_VAL_SHIFT (0U) +#define MMC_INI_REV_VAL_SET(x) (((uint32_t)(x) << MMC_INI_REV_VAL_SHIFT) & MMC_INI_REV_VAL_MASK) +#define MMC_INI_REV_VAL_GET(x) (((uint32_t)(x) & MMC_INI_REV_VAL_MASK) >> MMC_INI_REV_VAL_SHIFT) + +/* Bitfield definition for register: INI_SPEED */ +/* + * VAL (RW) + * + * the value; + * continuous mode: fix<32, 19> + */ +#define MMC_INI_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_SPEED_VAL_SHIFT (0U) +#define MMC_INI_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_INI_SPEED_VAL_SHIFT) & MMC_INI_SPEED_VAL_MASK) +#define MMC_INI_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_INI_SPEED_VAL_MASK) >> MMC_INI_SPEED_VAL_SHIFT) + +/* Bitfield definition for register: INI_ACCEL */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 19> + */ +#define MMC_INI_ACCEL_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_ACCEL_VAL_SHIFT (0U) +#define MMC_INI_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_INI_ACCEL_VAL_SHIFT) & MMC_INI_ACCEL_VAL_MASK) +#define MMC_INI_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_INI_ACCEL_VAL_MASK) >> MMC_INI_ACCEL_VAL_SHIFT) + +/* Bitfield definition for register: INI_COEF_TIME */ +/* + * VAL (RW) + * + * indicate the time to change the values. + * 0: instant change + */ +#define MMC_INI_COEF_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_COEF_TIME_VAL_SHIFT (0U) +#define MMC_INI_COEF_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_INI_COEF_TIME_VAL_SHIFT) & MMC_INI_COEF_TIME_VAL_MASK) +#define MMC_INI_COEF_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_INI_COEF_TIME_VAL_MASK) >> MMC_INI_COEF_TIME_VAL_SHIFT) + +/* Bitfield definition for register: INI_PCOEF */ +/* + * VAL (RW) + * + * the value, fix<32, 15> + */ +#define MMC_INI_PCOEF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_PCOEF_VAL_SHIFT (0U) +#define MMC_INI_PCOEF_VAL_SET(x) (((uint32_t)(x) << MMC_INI_PCOEF_VAL_SHIFT) & MMC_INI_PCOEF_VAL_MASK) +#define MMC_INI_PCOEF_VAL_GET(x) (((uint32_t)(x) & MMC_INI_PCOEF_VAL_MASK) >> MMC_INI_PCOEF_VAL_SHIFT) + +/* Bitfield definition for register: INI_ICOEF */ +/* + * VAL (RW) + * + * the value, fix<32, 21> + */ +#define MMC_INI_ICOEF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_ICOEF_VAL_SHIFT (0U) +#define MMC_INI_ICOEF_VAL_SET(x) (((uint32_t)(x) << MMC_INI_ICOEF_VAL_SHIFT) & MMC_INI_ICOEF_VAL_MASK) +#define MMC_INI_ICOEF_VAL_GET(x) (((uint32_t)(x) & MMC_INI_ICOEF_VAL_MASK) >> MMC_INI_ICOEF_VAL_SHIFT) + +/* Bitfield definition for register: INI_ACOEF */ +/* + * VAL (RW) + * + * the value, fix<32, 19> + */ +#define MMC_INI_ACOEF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_ACOEF_VAL_SHIFT (0U) +#define MMC_INI_ACOEF_VAL_SET(x) (((uint32_t)(x) << MMC_INI_ACOEF_VAL_SHIFT) & MMC_INI_ACOEF_VAL_MASK) +#define MMC_INI_ACOEF_VAL_GET(x) (((uint32_t)(x) & MMC_INI_ACOEF_VAL_MASK) >> MMC_INI_ACOEF_VAL_SHIFT) + +/* Bitfield definition for register: ESTM_TIM */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_ESTM_TIM_VAL_MASK (0xFFFFFFFFUL) +#define MMC_ESTM_TIM_VAL_SHIFT (0U) +#define MMC_ESTM_TIM_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_TIM_VAL_MASK) >> MMC_ESTM_TIM_VAL_SHIFT) + +/* Bitfield definition for register: ESTM_POS */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_ESTM_POS_VAL_MASK (0xFFFFFFFFUL) +#define MMC_ESTM_POS_VAL_SHIFT (0U) +#define MMC_ESTM_POS_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_POS_VAL_MASK) >> MMC_ESTM_POS_VAL_SHIFT) + +/* Bitfield definition for register: ESTM_REV */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_ESTM_REV_VAL_MASK (0xFFFFFFFFUL) +#define MMC_ESTM_REV_VAL_SHIFT (0U) +#define MMC_ESTM_REV_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_REV_VAL_MASK) >> MMC_ESTM_REV_VAL_SHIFT) + +/* Bitfield definition for register: ESTM_SPEED */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_ESTM_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_ESTM_SPEED_VAL_SHIFT (0U) +#define MMC_ESTM_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_SPEED_VAL_MASK) >> MMC_ESTM_SPEED_VAL_SHIFT) + +/* Bitfield definition for register: ESTM_ACCEL */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_ESTM_ACCEL_VAL_MASK (0xFFFFFFFFUL) +#define MMC_ESTM_ACCEL_VAL_SHIFT (0U) +#define MMC_ESTM_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_ACCEL_VAL_MASK) >> MMC_ESTM_ACCEL_VAL_SHIFT) + +/* Bitfield definition for register: CUR_PCOEF */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_CUR_PCOEF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_CUR_PCOEF_VAL_SHIFT (0U) +#define MMC_CUR_PCOEF_VAL_GET(x) (((uint32_t)(x) & MMC_CUR_PCOEF_VAL_MASK) >> MMC_CUR_PCOEF_VAL_SHIFT) + +/* Bitfield definition for register: CUR_ICOEF */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_CUR_ICOEF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_CUR_ICOEF_VAL_SHIFT (0U) +#define MMC_CUR_ICOEF_VAL_GET(x) (((uint32_t)(x) & MMC_CUR_ICOEF_VAL_MASK) >> MMC_CUR_ICOEF_VAL_SHIFT) + +/* Bitfield definition for register: CUR_ACOEF */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_CUR_ACOEF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_CUR_ACOEF_VAL_SHIFT (0U) +#define MMC_CUR_ACOEF_VAL_GET(x) (((uint32_t)(x) & MMC_CUR_ACOEF_VAL_MASK) >> MMC_CUR_ACOEF_VAL_SHIFT) + +/* Bitfield definition for register: INI_DELTA_POS_TIME */ +/* + * VAL (RW) + * + * indicate the time to change the values. + * 0: instant change + */ +#define MMC_INI_DELTA_POS_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_DELTA_POS_TIME_VAL_SHIFT (0U) +#define MMC_INI_DELTA_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_POS_TIME_VAL_SHIFT) & MMC_INI_DELTA_POS_TIME_VAL_MASK) +#define MMC_INI_DELTA_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_POS_TIME_VAL_MASK) >> MMC_INI_DELTA_POS_TIME_VAL_SHIFT) + +/* Bitfield definition for register: INI_DELTA_POS */ +/* + * VAL (RW) + * + * the value + * continuous mode: ufix <32, 32> + */ +#define MMC_INI_DELTA_POS_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_DELTA_POS_VAL_SHIFT (0U) +#define MMC_INI_DELTA_POS_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_POS_VAL_SHIFT) & MMC_INI_DELTA_POS_VAL_MASK) +#define MMC_INI_DELTA_POS_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_POS_VAL_MASK) >> MMC_INI_DELTA_POS_VAL_SHIFT) + +/* Bitfield definition for register: INI_DELTA_REV */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 0> + */ +#define MMC_INI_DELTA_REV_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_DELTA_REV_VAL_SHIFT (0U) +#define MMC_INI_DELTA_REV_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_REV_VAL_SHIFT) & MMC_INI_DELTA_REV_VAL_MASK) +#define MMC_INI_DELTA_REV_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_REV_VAL_MASK) >> MMC_INI_DELTA_REV_VAL_SHIFT) + +/* Bitfield definition for register: INI_DELTA_SPEED */ +/* + * VAL (RW) + * + * the value； + * continuous mode: fix<32, 19> + */ +#define MMC_INI_DELTA_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_DELTA_SPEED_VAL_SHIFT (0U) +#define MMC_INI_DELTA_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_SPEED_VAL_SHIFT) & MMC_INI_DELTA_SPEED_VAL_MASK) +#define MMC_INI_DELTA_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_SPEED_VAL_MASK) >> MMC_INI_DELTA_SPEED_VAL_SHIFT) + +/* Bitfield definition for register: INI_DELTA_ACCEL */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 19> + */ +#define MMC_INI_DELTA_ACCEL_VAL_MASK (0xFFFFFFFFUL) +#define MMC_INI_DELTA_ACCEL_VAL_SHIFT (0U) +#define MMC_INI_DELTA_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_ACCEL_VAL_SHIFT) & MMC_INI_DELTA_ACCEL_VAL_MASK) +#define MMC_INI_DELTA_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_ACCEL_VAL_MASK) >> MMC_INI_DELTA_ACCEL_VAL_SHIFT) + +/* Bitfield definition for register: POS_TRG_CFG */ +/* + * EDGE (RW) + * + * 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than + */ +#define MMC_POS_TRG_CFG_EDGE_MASK (0x2U) +#define MMC_POS_TRG_CFG_EDGE_SHIFT (1U) +#define MMC_POS_TRG_CFG_EDGE_SET(x) (((uint32_t)(x) << MMC_POS_TRG_CFG_EDGE_SHIFT) & MMC_POS_TRG_CFG_EDGE_MASK) +#define MMC_POS_TRG_CFG_EDGE_GET(x) (((uint32_t)(x) & MMC_POS_TRG_CFG_EDGE_MASK) >> MMC_POS_TRG_CFG_EDGE_SHIFT) + +/* + * EN (RW) + * + * 1-trigger valid; 0-Trigger not valid" + */ +#define MMC_POS_TRG_CFG_EN_MASK (0x1U) +#define MMC_POS_TRG_CFG_EN_SHIFT (0U) +#define MMC_POS_TRG_CFG_EN_SET(x) (((uint32_t)(x) << MMC_POS_TRG_CFG_EN_SHIFT) & MMC_POS_TRG_CFG_EN_MASK) +#define MMC_POS_TRG_CFG_EN_GET(x) (((uint32_t)(x) & MMC_POS_TRG_CFG_EN_MASK) >> MMC_POS_TRG_CFG_EN_SHIFT) + +/* Bitfield definition for register: POS_TRG_POS_THR */ +/* + * VAL (RW) + * + * For pos out trigger (pos). + * ufix<32, 32> + */ +#define MMC_POS_TRG_POS_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_POS_TRG_POS_THR_VAL_SHIFT (0U) +#define MMC_POS_TRG_POS_THR_VAL_SET(x) (((uint32_t)(x) << MMC_POS_TRG_POS_THR_VAL_SHIFT) & MMC_POS_TRG_POS_THR_VAL_MASK) +#define MMC_POS_TRG_POS_THR_VAL_GET(x) (((uint32_t)(x) & MMC_POS_TRG_POS_THR_VAL_MASK) >> MMC_POS_TRG_POS_THR_VAL_SHIFT) + +/* Bitfield definition for register: POS_TRG_REV_THR */ +/* + * VAL (RW) + * + * For pos out trigger (rev) + * fix<32, 0> + */ +#define MMC_POS_TRG_REV_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_POS_TRG_REV_THR_VAL_SHIFT (0U) +#define MMC_POS_TRG_REV_THR_VAL_SET(x) (((uint32_t)(x) << MMC_POS_TRG_REV_THR_VAL_SHIFT) & MMC_POS_TRG_REV_THR_VAL_MASK) +#define MMC_POS_TRG_REV_THR_VAL_GET(x) (((uint32_t)(x) & MMC_POS_TRG_REV_THR_VAL_MASK) >> MMC_POS_TRG_REV_THR_VAL_SHIFT) + +/* Bitfield definition for register: SPEED_TRG_CFG */ +/* + * COMP_TYPE (RW) + * + * 1: Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) + */ +#define MMC_SPEED_TRG_CFG_COMP_TYPE_MASK (0x4U) +#define MMC_SPEED_TRG_CFG_COMP_TYPE_SHIFT (2U) +#define MMC_SPEED_TRG_CFG_COMP_TYPE_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_CFG_COMP_TYPE_SHIFT) & MMC_SPEED_TRG_CFG_COMP_TYPE_MASK) +#define MMC_SPEED_TRG_CFG_COMP_TYPE_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_CFG_COMP_TYPE_MASK) >> MMC_SPEED_TRG_CFG_COMP_TYPE_SHIFT) + +/* + * EDGE (RW) + * + * 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than + */ +#define MMC_SPEED_TRG_CFG_EDGE_MASK (0x2U) +#define MMC_SPEED_TRG_CFG_EDGE_SHIFT (1U) +#define MMC_SPEED_TRG_CFG_EDGE_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_CFG_EDGE_SHIFT) & MMC_SPEED_TRG_CFG_EDGE_MASK) +#define MMC_SPEED_TRG_CFG_EDGE_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_CFG_EDGE_MASK) >> MMC_SPEED_TRG_CFG_EDGE_SHIFT) + +/* + * EN (RW) + * + * 1-trigger valid; 0-Trigger not valid + * Normally it means either the max pos speed, or the min negative speed. + */ +#define MMC_SPEED_TRG_CFG_EN_MASK (0x1U) +#define MMC_SPEED_TRG_CFG_EN_SHIFT (0U) +#define MMC_SPEED_TRG_CFG_EN_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_CFG_EN_SHIFT) & MMC_SPEED_TRG_CFG_EN_MASK) +#define MMC_SPEED_TRG_CFG_EN_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_CFG_EN_MASK) >> MMC_SPEED_TRG_CFG_EN_SHIFT) + +/* Bitfield definition for register: SPEED_TRG_THR */ +/* + * VAL (RW) + * + * For speed trigger. + * continuous mode: fix<32, 19> + */ +#define MMC_SPEED_TRG_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_SPEED_TRG_THR_VAL_SHIFT (0U) +#define MMC_SPEED_TRG_THR_VAL_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_THR_VAL_SHIFT) & MMC_SPEED_TRG_THR_VAL_MASK) +#define MMC_SPEED_TRG_THR_VAL_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_THR_VAL_MASK) >> MMC_SPEED_TRG_THR_VAL_SHIFT) + +/* Bitfield definition for register of struct array COEF_TRG_CFG: ERR_THR */ +/* + * VAL (RW) + * + * ErrThr0: Error Threshold 0, (abs(tracking error)>= will choose the coefs as below) + * Note: ErrThr0>ErrThr1>ErrThr2 + * ufix<31, 28> + */ +#define MMC_COEF_TRG_CFG_ERR_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_COEF_TRG_CFG_ERR_THR_VAL_SHIFT (0U) +#define MMC_COEF_TRG_CFG_ERR_THR_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_ERR_THR_VAL_SHIFT) & MMC_COEF_TRG_CFG_ERR_THR_VAL_MASK) +#define MMC_COEF_TRG_CFG_ERR_THR_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_ERR_THR_VAL_MASK) >> MMC_COEF_TRG_CFG_ERR_THR_VAL_SHIFT) + +/* Bitfield definition for register of struct array COEF_TRG_CFG: P */ +/* + * VAL (RW) + * + * P0_Coef, fix<32, 15> + */ +#define MMC_COEF_TRG_CFG_P_VAL_MASK (0xFFFFFFFFUL) +#define MMC_COEF_TRG_CFG_P_VAL_SHIFT (0U) +#define MMC_COEF_TRG_CFG_P_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_P_VAL_SHIFT) & MMC_COEF_TRG_CFG_P_VAL_MASK) +#define MMC_COEF_TRG_CFG_P_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_P_VAL_MASK) >> MMC_COEF_TRG_CFG_P_VAL_SHIFT) + +/* Bitfield definition for register of struct array COEF_TRG_CFG: I */ +/* + * VAL (RW) + * + * I0_Coef, fix<32, 21> + */ +#define MMC_COEF_TRG_CFG_I_VAL_MASK (0xFFFFFFFFUL) +#define MMC_COEF_TRG_CFG_I_VAL_SHIFT (0U) +#define MMC_COEF_TRG_CFG_I_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_I_VAL_SHIFT) & MMC_COEF_TRG_CFG_I_VAL_MASK) +#define MMC_COEF_TRG_CFG_I_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_I_VAL_MASK) >> MMC_COEF_TRG_CFG_I_VAL_SHIFT) + +/* Bitfield definition for register of struct array COEF_TRG_CFG: A */ +/* + * VAL (RW) + * + * A0_Coef，fix<32, 19> + */ +#define MMC_COEF_TRG_CFG_A_VAL_MASK (0xFFFFFFFFUL) +#define MMC_COEF_TRG_CFG_A_VAL_SHIFT (0U) +#define MMC_COEF_TRG_CFG_A_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_A_VAL_SHIFT) & MMC_COEF_TRG_CFG_A_VAL_MASK) +#define MMC_COEF_TRG_CFG_A_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_A_VAL_MASK) >> MMC_COEF_TRG_CFG_A_VAL_SHIFT) + +/* Bitfield definition for register of struct array COEF_TRG_CFG: TIME */ +/* + * VAL (RW) + * + * CoefTime0: Time Stayed using this coefs (counted in input samples). Ideal value of tracing cycles should +1. ufix<32,0> + */ +#define MMC_COEF_TRG_CFG_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_COEF_TRG_CFG_TIME_VAL_SHIFT (0U) +#define MMC_COEF_TRG_CFG_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_TIME_VAL_SHIFT) & MMC_COEF_TRG_CFG_TIME_VAL_MASK) +#define MMC_COEF_TRG_CFG_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_TIME_VAL_MASK) >> MMC_COEF_TRG_CFG_TIME_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_CTRL */ +/* + * SPEED_TRG_VALID_IE (RW) + * + * Interrupt Enable for SPEED_TRG_VALID + */ +#define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK (0x40000000UL) +#define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SHIFT (30U) +#define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SHIFT) & MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK) +#define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK) >> MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SHIFT) + +/* + * POS_TRG_VALID_IE (RW) + * + * Interrupt Enable for POS_TRG_VALID + */ +#define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK (0x20000000UL) +#define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SHIFT (29U) +#define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SHIFT) & MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK) +#define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK) >> MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SHIFT) + +/* + * INI_POS_TRG_TYPE (RW) + * + * 0: Time Stamp in the configuration + * 1: Risedge of In Trg[0] + * 2: Risedge of In Trg[1] + * 3: Risedge of out trg[0] + * 4: Risedge of out trg[1] + * 5: Risedge of self pos trigger + * 6: Risedge of self speed trigger + * Others: no function + */ +#define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK (0x3800000UL) +#define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SHIFT (23U) +#define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK) +#define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SHIFT) + +/* + * INI_POS_CMD_MSK (RW) + * + * 1: change + * 0: won't change + * bit 3: for accel + * bit 2: for speed + * bit 1: for revolution + * bit 0: for position + */ +#define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK (0x3C0000UL) +#define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SHIFT (18U) +#define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SHIFT) & MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK) +#define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK) >> MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SHIFT) + +/* + * INI_DELTA_POS_TRG_TYPE (RW) + * + * 0: Time Stamp in the configuration + * 1: Risedge of In Trg[0] + * 2: Risedge of In Trg[1] + * 3: Risedge of out trg[0] + * 4: Risedge of out trg[1] + * 5: Risedge of self pos trigger + * 6: Risedge of self speed trigger + * Others: no function + */ +#define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK (0x1C000UL) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SHIFT (14U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SHIFT) + +/* + * INI_DELTA_POS_DONE_IE (RW) + * + * Interrupt Enable for INI_DELTA_POS_DONE + */ +#define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK (0x2000U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SHIFT (13U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SHIFT) + +/* + * INI_DELTA_POS_CMD_MSK (RW) + * + * 1: change + * 0: won't change + * bit 3: for delta accel + * bit 2: for delta speed + * bit 1: for delta revolution + * bit 0: for delta position + */ +#define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK (0x1E00U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SHIFT (9U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SHIFT) + +/* + * INI_DELTA_POS_REQ (RW) + * + * 1: Command to reload the delta pos. Auto clear + * 0: + */ +#define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK (0x100U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SHIFT (8U) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK) +#define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SHIFT) + +/* + * OPEN_LOOP_MODE (RW) + * + * 1: in open loop mode + * 0: not in open loop mode + */ +#define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK (0x80U) +#define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SHIFT (7U) +#define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SHIFT) & MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK) +#define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK) >> MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SHIFT) + +/* + * PRED_MODE (RW) + * + * 1:continuously repeat pred, + * 0:cal the pred based on a definite time-stamp offset, + * 2:programed one-shot prediction mode + */ +#define MMC_BR_BR_CTRL_PRED_MODE_MASK (0x30U) +#define MMC_BR_BR_CTRL_PRED_MODE_SHIFT (4U) +#define MMC_BR_BR_CTRL_PRED_MODE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_PRED_MODE_SHIFT) & MMC_BR_BR_CTRL_PRED_MODE_MASK) +#define MMC_BR_BR_CTRL_PRED_MODE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_PRED_MODE_MASK) >> MMC_BR_BR_CTRL_PRED_MODE_SHIFT) + +/* + * NF_TRG_TYPE (RW) + * + * 1. Each non-first trigger by external trigger pin + * 0. Each non-first trigger by the timer + */ +#define MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK (0x4U) +#define MMC_BR_BR_CTRL_NF_TRG_TYPE_SHIFT (2U) +#define MMC_BR_BR_CTRL_NF_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_NF_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK) +#define MMC_BR_BR_CTRL_NF_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_NF_TRG_TYPE_SHIFT) + +/* + * F_TRG_TYPE (RW) + * + * 1. First trigger by external trigger pin + * 0. First trigger by the timer + * When in CR[MANUAL_IO]=1 mode, it is the prediction trigger + */ +#define MMC_BR_BR_CTRL_F_TRG_TYPE_MASK (0x2U) +#define MMC_BR_BR_CTRL_F_TRG_TYPE_SHIFT (1U) +#define MMC_BR_BR_CTRL_F_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_F_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_F_TRG_TYPE_MASK) +#define MMC_BR_BR_CTRL_F_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_F_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_F_TRG_TYPE_SHIFT) + +/* + * BR_EN (RW) + * + * Branch Enable + */ +#define MMC_BR_BR_CTRL_BR_EN_MASK (0x1U) +#define MMC_BR_BR_CTRL_BR_EN_SHIFT (0U) +#define MMC_BR_BR_CTRL_BR_EN_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_BR_EN_SHIFT) & MMC_BR_BR_CTRL_BR_EN_MASK) +#define MMC_BR_BR_CTRL_BR_EN_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_BR_EN_MASK) >> MMC_BR_BR_CTRL_BR_EN_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TIMEOFF */ +/* + * VAL (RW) + * + * ufix<32, 0> time offset incycles from the trigger time + */ +#define MMC_BR_BR_TIMEOFF_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_TIMEOFF_VAL_SHIFT (0U) +#define MMC_BR_BR_TIMEOFF_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TIMEOFF_VAL_SHIFT) & MMC_BR_BR_TIMEOFF_VAL_MASK) +#define MMC_BR_BR_TIMEOFF_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TIMEOFF_VAL_MASK) >> MMC_BR_BR_TIMEOFF_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_PERIOD */ +/* + * VAL (RW) + * + * uifx<32, 0>, time offset incycles between each trigger time + */ +#define MMC_BR_BR_TRG_PERIOD_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_TRG_PERIOD_VAL_SHIFT (0U) +#define MMC_BR_BR_TRG_PERIOD_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_PERIOD_VAL_SHIFT) & MMC_BR_BR_TRG_PERIOD_VAL_MASK) +#define MMC_BR_BR_TRG_PERIOD_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_PERIOD_VAL_MASK) >> MMC_BR_BR_TRG_PERIOD_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_F_TIME */ +/* + * VAL (RW) + * + * uifx<32, 0> the time for the first trigger + */ +#define MMC_BR_BR_TRG_F_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_TRG_F_TIME_VAL_SHIFT (0U) +#define MMC_BR_BR_TRG_F_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_F_TIME_VAL_SHIFT) & MMC_BR_BR_TRG_F_TIME_VAL_MASK) +#define MMC_BR_BR_TRG_F_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_F_TIME_VAL_MASK) >> MMC_BR_BR_TRG_F_TIME_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_ST */ +/* + * OPEN_LOOP_ST (RO) + * + * 1：in open loop mode + * 0：in closed loop mode + */ +#define MMC_BR_BR_ST_OPEN_LOOP_ST_MASK (0x400U) +#define MMC_BR_BR_ST_OPEN_LOOP_ST_SHIFT (10U) +#define MMC_BR_BR_ST_OPEN_LOOP_ST_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_OPEN_LOOP_ST_MASK) >> MMC_BR_BR_ST_OPEN_LOOP_ST_SHIFT) + +/* + * SPEED_TRG_VLD (W1C) + * + * 1：self speed trigger event found + * 0：self speed trigger event not found yet + */ +#define MMC_BR_BR_ST_SPEED_TRG_VLD_MASK (0x200U) +#define MMC_BR_BR_ST_SPEED_TRG_VLD_SHIFT (9U) +#define MMC_BR_BR_ST_SPEED_TRG_VLD_SET(x) (((uint32_t)(x) << MMC_BR_BR_ST_SPEED_TRG_VLD_SHIFT) & MMC_BR_BR_ST_SPEED_TRG_VLD_MASK) +#define MMC_BR_BR_ST_SPEED_TRG_VLD_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_SPEED_TRG_VLD_MASK) >> MMC_BR_BR_ST_SPEED_TRG_VLD_SHIFT) + +/* + * POS_TRG_VLD (W1C) + * + * 1：self position trigger event found + * 0：self position trigger event not found yet + */ +#define MMC_BR_BR_ST_POS_TRG_VLD_MASK (0x100U) +#define MMC_BR_BR_ST_POS_TRG_VLD_SHIFT (8U) +#define MMC_BR_BR_ST_POS_TRG_VLD_SET(x) (((uint32_t)(x) << MMC_BR_BR_ST_POS_TRG_VLD_SHIFT) & MMC_BR_BR_ST_POS_TRG_VLD_MASK) +#define MMC_BR_BR_ST_POS_TRG_VLD_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_POS_TRG_VLD_MASK) >> MMC_BR_BR_ST_POS_TRG_VLD_SHIFT) + +/* + * INI_DELTA_POS_DONE (W1C) + * + * 1: the initialization of delta position command is done + * 0: the initialization of delta position command is not done + */ +#define MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK (0x40U) +#define MMC_BR_BR_ST_INI_DELTA_POS_DONE_SHIFT (6U) +#define MMC_BR_BR_ST_INI_DELTA_POS_DONE_SET(x) (((uint32_t)(x) << MMC_BR_BR_ST_INI_DELTA_POS_DONE_SHIFT) & MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK) +#define MMC_BR_BR_ST_INI_DELTA_POS_DONE_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK) >> MMC_BR_BR_ST_INI_DELTA_POS_DONE_SHIFT) + +/* + * IDLE (RO) + * + * 1: The prediction module is idle. + * 0: The prediction module is not idle. + */ +#define MMC_BR_BR_ST_IDLE_MASK (0x20U) +#define MMC_BR_BR_ST_IDLE_SHIFT (5U) +#define MMC_BR_BR_ST_IDLE_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_IDLE_MASK) >> MMC_BR_BR_ST_IDLE_SHIFT) + +/* + * ERR_ID (RO) + * + * The module's error ID output + */ +#define MMC_BR_BR_ST_ERR_ID_MASK (0xFU) +#define MMC_BR_BR_ST_ERR_ID_SHIFT (0U) +#define MMC_BR_BR_ST_ERR_ID_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_ERR_ID_MASK) >> MMC_BR_BR_ST_ERR_ID_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_POS_CFG */ +/* + * EDGE (RW) + * + * bit1: 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than + */ +#define MMC_BR_BR_TRG_POS_CFG_EDGE_MASK (0x2U) +#define MMC_BR_BR_TRG_POS_CFG_EDGE_SHIFT (1U) +#define MMC_BR_BR_TRG_POS_CFG_EDGE_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_POS_CFG_EDGE_SHIFT) & MMC_BR_BR_TRG_POS_CFG_EDGE_MASK) +#define MMC_BR_BR_TRG_POS_CFG_EDGE_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_POS_CFG_EDGE_MASK) >> MMC_BR_BR_TRG_POS_CFG_EDGE_SHIFT) + +/* + * EN (RW) + * + * 1-trigger valid; 0-Trigger not valid + */ +#define MMC_BR_BR_TRG_POS_CFG_EN_MASK (0x1U) +#define MMC_BR_BR_TRG_POS_CFG_EN_SHIFT (0U) +#define MMC_BR_BR_TRG_POS_CFG_EN_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_POS_CFG_EN_SHIFT) & MMC_BR_BR_TRG_POS_CFG_EN_MASK) +#define MMC_BR_BR_TRG_POS_CFG_EN_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_POS_CFG_EN_MASK) >> MMC_BR_BR_TRG_POS_CFG_EN_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_POS_THR */ +/* + * VAL (RW) + * + * For pos out trigger (pos). + * ufix<32, 32> + */ +#define MMC_BR_BR_TRG_POS_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_TRG_POS_THR_VAL_SHIFT (0U) +#define MMC_BR_BR_TRG_POS_THR_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_POS_THR_VAL_SHIFT) & MMC_BR_BR_TRG_POS_THR_VAL_MASK) +#define MMC_BR_BR_TRG_POS_THR_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_POS_THR_VAL_MASK) >> MMC_BR_BR_TRG_POS_THR_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_REV_THR */ +/* + * VAL (RW) + * + * For pos out trigger (rev) + * ufix<32, 0> + */ +#define MMC_BR_BR_TRG_REV_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_TRG_REV_THR_VAL_SHIFT (0U) +#define MMC_BR_BR_TRG_REV_THR_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_REV_THR_VAL_SHIFT) & MMC_BR_BR_TRG_REV_THR_VAL_MASK) +#define MMC_BR_BR_TRG_REV_THR_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_REV_THR_VAL_MASK) >> MMC_BR_BR_TRG_REV_THR_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_SPEED_CFG */ +/* + * COMP_TYPE (RW) + * + * Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) + */ +#define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_MASK (0x4U) +#define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SHIFT (2U) +#define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SHIFT) & MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_MASK) +#define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_MASK) >> MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SHIFT) + +/* + * EDGE_SEL (RW) + * + * 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than + */ +#define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_MASK (0x2U) +#define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SHIFT (1U) +#define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SHIFT) & MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_MASK) +#define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_MASK) >> MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SHIFT) + +/* + * EN (RW) + * + * 1-trigger valid; 0-Trigger not valid + * Normally it means either the max pos speed, or the min negative speed. + */ +#define MMC_BR_BR_TRG_SPEED_CFG_EN_MASK (0x1U) +#define MMC_BR_BR_TRG_SPEED_CFG_EN_SHIFT (0U) +#define MMC_BR_BR_TRG_SPEED_CFG_EN_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_CFG_EN_SHIFT) & MMC_BR_BR_TRG_SPEED_CFG_EN_MASK) +#define MMC_BR_BR_TRG_SPEED_CFG_EN_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_CFG_EN_MASK) >> MMC_BR_BR_TRG_SPEED_CFG_EN_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_TRG_SPEED_THR */ +/* + * VAL (RW) + * + * For speed trigger. + * continuous mode: fix<32, 19> + */ +#define MMC_BR_BR_TRG_SPEED_THR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_TRG_SPEED_THR_VAL_SHIFT (0U) +#define MMC_BR_BR_TRG_SPEED_THR_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_THR_VAL_SHIFT) & MMC_BR_BR_TRG_SPEED_THR_VAL_MASK) +#define MMC_BR_BR_TRG_SPEED_THR_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_THR_VAL_MASK) >> MMC_BR_BR_TRG_SPEED_THR_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_POS_TIME */ +/* + * VAL (RW) + * + * indicate the time to change the values. + * 0: instant change + */ +#define MMC_BR_BR_INI_POS_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_POS_TIME_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_POS_TIME_VAL_SHIFT) & MMC_BR_BR_INI_POS_TIME_VAL_MASK) +#define MMC_BR_BR_INI_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_POS_TIME_VAL_MASK) >> MMC_BR_BR_INI_POS_TIME_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_POS */ +/* + * VAL (RW) + * + * the value + * ufix<32, 32> + */ +#define MMC_BR_BR_INI_POS_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_POS_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_POS_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_POS_VAL_SHIFT) & MMC_BR_BR_INI_POS_VAL_MASK) +#define MMC_BR_BR_INI_POS_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_POS_VAL_MASK) >> MMC_BR_BR_INI_POS_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_REV */ +/* + * VAL (RW) + * + * the value + * ufix<32, 0> + */ +#define MMC_BR_BR_INI_REV_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_REV_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_REV_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_REV_VAL_SHIFT) & MMC_BR_BR_INI_REV_VAL_MASK) +#define MMC_BR_BR_INI_REV_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_REV_VAL_MASK) >> MMC_BR_BR_INI_REV_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_SPEED */ +/* + * VAL (RW) + * + * the value + * fix<32, 19> + */ +#define MMC_BR_BR_INI_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_SPEED_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_SPEED_VAL_SHIFT) & MMC_BR_BR_INI_SPEED_VAL_MASK) +#define MMC_BR_BR_INI_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_SPEED_VAL_MASK) >> MMC_BR_BR_INI_SPEED_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_ACCEL */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 19> + */ +#define MMC_BR_BR_INI_ACCEL_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_ACCEL_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_ACCEL_VAL_SHIFT) & MMC_BR_BR_INI_ACCEL_VAL_MASK) +#define MMC_BR_BR_INI_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_ACCEL_VAL_MASK) >> MMC_BR_BR_INI_ACCEL_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_DELTA_POS_TIME */ +/* + * VAL (RW) + * + * indicate the time to change the values. + * 0: instant change + */ +#define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_POS_TIME_VAL_MASK) +#define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_POS_TIME_VAL_MASK) >> MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_DELTA_POS */ +/* + * VAL (RW) + * + * the value + * continuous mode: ufix<32, 32> + */ +#define MMC_BR_BR_INI_DELTA_POS_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_DELTA_POS_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_DELTA_POS_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_POS_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_POS_VAL_MASK) +#define MMC_BR_BR_INI_DELTA_POS_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_POS_VAL_MASK) >> MMC_BR_BR_INI_DELTA_POS_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_DELTA_REV */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 0> + */ +#define MMC_BR_BR_INI_DELTA_REV_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_DELTA_REV_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_DELTA_REV_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_REV_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_REV_VAL_MASK) +#define MMC_BR_BR_INI_DELTA_REV_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_REV_VAL_MASK) >> MMC_BR_BR_INI_DELTA_REV_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_DELTA_SPEED */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 19> + */ +#define MMC_BR_BR_INI_DELTA_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_DELTA_SPEED_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_DELTA_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_SPEED_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_SPEED_VAL_MASK) +#define MMC_BR_BR_INI_DELTA_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_SPEED_VAL_MASK) >> MMC_BR_BR_INI_DELTA_SPEED_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_INI_DELTA_ACCEL */ +/* + * VAL (RW) + * + * the value + * continuous mode: fix<32, 19> + */ +#define MMC_BR_BR_INI_DELTA_ACCEL_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_INI_DELTA_ACCEL_VAL_SHIFT (0U) +#define MMC_BR_BR_INI_DELTA_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_ACCEL_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_ACCEL_VAL_MASK) +#define MMC_BR_BR_INI_DELTA_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_ACCEL_VAL_MASK) >> MMC_BR_BR_INI_DELTA_ACCEL_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_CUR_POS_TIME */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BR_BR_CUR_POS_TIME_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_CUR_POS_TIME_VAL_SHIFT (0U) +#define MMC_BR_BR_CUR_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_POS_TIME_VAL_MASK) >> MMC_BR_BR_CUR_POS_TIME_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_CUR_POS */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BR_BR_CUR_POS_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_CUR_POS_VAL_SHIFT (0U) +#define MMC_BR_BR_CUR_POS_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_POS_VAL_MASK) >> MMC_BR_BR_CUR_POS_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_CUR_REV */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BR_BR_CUR_REV_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_CUR_REV_VAL_SHIFT (0U) +#define MMC_BR_BR_CUR_REV_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_REV_VAL_MASK) >> MMC_BR_BR_CUR_REV_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_CUR_SPEED */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BR_BR_CUR_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_CUR_SPEED_VAL_SHIFT (0U) +#define MMC_BR_BR_CUR_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_SPEED_VAL_MASK) >> MMC_BR_BR_CUR_SPEED_VAL_SHIFT) + +/* Bitfield definition for register of struct array BR: BR_CUR_ACCEL */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BR_BR_CUR_ACCEL_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BR_BR_CUR_ACCEL_VAL_SHIFT (0U) +#define MMC_BR_BR_CUR_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_ACCEL_VAL_MASK) >> MMC_BR_BR_CUR_ACCEL_VAL_SHIFT) + +/* Bitfield definition for register: BK0_TIMESTAMP */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK0_TIMESTAMP_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK0_TIMESTAMP_VAL_SHIFT (0U) +#define MMC_BK0_TIMESTAMP_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_TIMESTAMP_VAL_MASK) >> MMC_BK0_TIMESTAMP_VAL_SHIFT) + +/* Bitfield definition for register: BK0_POSITION */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK0_POSITION_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK0_POSITION_VAL_SHIFT (0U) +#define MMC_BK0_POSITION_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_POSITION_VAL_MASK) >> MMC_BK0_POSITION_VAL_SHIFT) + +/* Bitfield definition for register: BK0_REVOLUTION */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK0_REVOLUTION_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK0_REVOLUTION_VAL_SHIFT (0U) +#define MMC_BK0_REVOLUTION_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_REVOLUTION_VAL_MASK) >> MMC_BK0_REVOLUTION_VAL_SHIFT) + +/* Bitfield definition for register: BK0_SPEED */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK0_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK0_SPEED_VAL_SHIFT (0U) +#define MMC_BK0_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_SPEED_VAL_MASK) >> MMC_BK0_SPEED_VAL_SHIFT) + +/* Bitfield definition for register: BK0_ACCELERATOR */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK0_ACCELERATOR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK0_ACCELERATOR_VAL_SHIFT (0U) +#define MMC_BK0_ACCELERATOR_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_ACCELERATOR_VAL_MASK) >> MMC_BK0_ACCELERATOR_VAL_SHIFT) + +/* Bitfield definition for register: BK1_TIMESTAMP */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK1_TIMESTAMP_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK1_TIMESTAMP_VAL_SHIFT (0U) +#define MMC_BK1_TIMESTAMP_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_TIMESTAMP_VAL_MASK) >> MMC_BK1_TIMESTAMP_VAL_SHIFT) + +/* Bitfield definition for register: BK1_POSITION */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK1_POSITION_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK1_POSITION_VAL_SHIFT (0U) +#define MMC_BK1_POSITION_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_POSITION_VAL_MASK) >> MMC_BK1_POSITION_VAL_SHIFT) + +/* Bitfield definition for register: BK1_REVOLUTION */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK1_REVOLUTION_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK1_REVOLUTION_VAL_SHIFT (0U) +#define MMC_BK1_REVOLUTION_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_REVOLUTION_VAL_MASK) >> MMC_BK1_REVOLUTION_VAL_SHIFT) + +/* Bitfield definition for register: BK1_SPEED */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK1_SPEED_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK1_SPEED_VAL_SHIFT (0U) +#define MMC_BK1_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_SPEED_VAL_MASK) >> MMC_BK1_SPEED_VAL_SHIFT) + +/* Bitfield definition for register: BK1_ACCELERATOR */ +/* + * VAL (RO) + * + * the value + */ +#define MMC_BK1_ACCELERATOR_VAL_MASK (0xFFFFFFFFUL) +#define MMC_BK1_ACCELERATOR_VAL_SHIFT (0U) +#define MMC_BK1_ACCELERATOR_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_ACCELERATOR_VAL_MASK) >> MMC_BK1_ACCELERATOR_VAL_SHIFT) + + + +/* COEF_TRG_CFG register group index macro definition */ +#define MMC_COEF_TRG_CFG_0 (0UL) +#define MMC_COEF_TRG_CFG_1 (1UL) +#define MMC_COEF_TRG_CFG_2 (2UL) + +/* BR register group index macro definition */ +#define MMC_BR_0 (0UL) +#define MMC_BR_1 (1UL) + + +#endif /* HPM_MMC_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h index aebabd1b..ed183b3b 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_mon_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -14,8 +14,7 @@ typedef struct { __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ } MONITOR[4]; - __RW uint32_t TEST_MODE; /* 0x20: */ - __R uint8_t RESERVED0[28]; /* 0x24 - 0x3F: Reserved */ + __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ __RW uint32_t IRQ_FLAG; /* 0x40: */ __RW uint32_t IRQ_ENABLE; /* 0x44: */ } MON_Type; @@ -59,28 +58,13 @@ typedef struct { #define MON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << MON_MONITOR_STATUS_FLAG_SHIFT) & MON_MONITOR_STATUS_FLAG_MASK) #define MON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & MON_MONITOR_STATUS_FLAG_MASK) >> MON_MONITOR_STATUS_FLAG_SHIFT) -/* Bitfield definition for register: TEST_MODE */ -/* - * DISABLE (RW) - * - * disable test mode entry, any non-zero value written to this register causes disable bit set - * 0: test mode enabled - * 1: test mode disabled - * Note: This register only available in BATT domain - */ -#define MON_TEST_MODE_DISABLE_MASK (0xFFFFFFFFUL) -#define MON_TEST_MODE_DISABLE_SHIFT (0U) -#define MON_TEST_MODE_DISABLE_SET(x) (((uint32_t)(x) << MON_TEST_MODE_DISABLE_SHIFT) & MON_TEST_MODE_DISABLE_MASK) -#define MON_TEST_MODE_DISABLE_GET(x) (((uint32_t)(x) & MON_TEST_MODE_DISABLE_MASK) >> MON_TEST_MODE_DISABLE_SHIFT) - /* Bitfield definition for register: IRQ_FLAG */ /* * FLAG (RW) * * interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag - * 0: no monitor interrupt + * 0: no monitor interrupt * 1: monitor interrupt happened - * Note: This register only available in PMIC domain */ #define MON_IRQ_FLAG_FLAG_MASK (0xFU) #define MON_IRQ_FLAG_FLAG_SHIFT (0U) @@ -94,7 +78,6 @@ typedef struct { * interrupt enable, each bit represents for one monitor * 0: monitor interrupt disabled * 1: monitor interrupt enabled - * Note: This register only available in PMIC domain */ #define MON_IRQ_ENABLE_ENABLE_MASK (0xFU) #define MON_IRQ_ENABLE_ENABLE_SHIFT (0U) diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_opamp_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_opamp_regs.h new file mode 100644 index 00000000..cb3a9e4c --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_opamp_regs.h @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_OPAMP_H +#define HPM_OPAMP_H + +typedef struct { + __RW uint32_t CTRL0; /* 0x0: control reg */ + __RW uint32_t STATUS; /* 0x4: status reg */ + __RW uint32_t CTRL1; /* 0x8: control reg1 */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + struct { + __RW uint32_t CFG0; /* 0x10: */ + __RW uint32_t CFG1; /* 0x14: */ + __RW uint32_t CFG2; /* 0x18: */ + } CFG[10]; +} OPAMP_Type; + + +/* Bitfield definition for register: CTRL0 */ +/* + * EN_LV (RW) + * + */ +#define OPAMP_CTRL0_EN_LV_MASK (0x4000000UL) +#define OPAMP_CTRL0_EN_LV_SHIFT (26U) +#define OPAMP_CTRL0_EN_LV_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_EN_LV_SHIFT) & OPAMP_CTRL0_EN_LV_MASK) +#define OPAMP_CTRL0_EN_LV_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_EN_LV_MASK) >> OPAMP_CTRL0_EN_LV_SHIFT) + +/* + * VIM_SEL (RW) + * + */ +#define OPAMP_CTRL0_VIM_SEL_MASK (0x70000UL) +#define OPAMP_CTRL0_VIM_SEL_SHIFT (16U) +#define OPAMP_CTRL0_VIM_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_VIM_SEL_SHIFT) & OPAMP_CTRL0_VIM_SEL_MASK) +#define OPAMP_CTRL0_VIM_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_VIM_SEL_MASK) >> OPAMP_CTRL0_VIM_SEL_SHIFT) + +/* + * MODE (RW) + * + */ +#define OPAMP_CTRL0_MODE_MASK (0xF800U) +#define OPAMP_CTRL0_MODE_SHIFT (11U) +#define OPAMP_CTRL0_MODE_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_MODE_SHIFT) & OPAMP_CTRL0_MODE_MASK) +#define OPAMP_CTRL0_MODE_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_MODE_MASK) >> OPAMP_CTRL0_MODE_SHIFT) + +/* + * GAIN_SEL (RW) + * + */ +#define OPAMP_CTRL0_GAIN_SEL_MASK (0x700U) +#define OPAMP_CTRL0_GAIN_SEL_SHIFT (8U) +#define OPAMP_CTRL0_GAIN_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_GAIN_SEL_SHIFT) & OPAMP_CTRL0_GAIN_SEL_MASK) +#define OPAMP_CTRL0_GAIN_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_GAIN_SEL_MASK) >> OPAMP_CTRL0_GAIN_SEL_SHIFT) + +/* + * DISABLE_PM_CAP (RW) + * + */ +#define OPAMP_CTRL0_DISABLE_PM_CAP_MASK (0x80U) +#define OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT (7U) +#define OPAMP_CTRL0_DISABLE_PM_CAP_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT) & OPAMP_CTRL0_DISABLE_PM_CAP_MASK) +#define OPAMP_CTRL0_DISABLE_PM_CAP_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_DISABLE_PM_CAP_MASK) >> OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT) + +/* + * MILLER_SEL (RW) + * + */ +#define OPAMP_CTRL0_MILLER_SEL_MASK (0x70U) +#define OPAMP_CTRL0_MILLER_SEL_SHIFT (4U) +#define OPAMP_CTRL0_MILLER_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_MILLER_SEL_SHIFT) & OPAMP_CTRL0_MILLER_SEL_MASK) +#define OPAMP_CTRL0_MILLER_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_MILLER_SEL_MASK) >> OPAMP_CTRL0_MILLER_SEL_SHIFT) + +/* + * VBYPASS (RW) + * + */ +#define OPAMP_CTRL0_VBYPASS_MASK (0x8U) +#define OPAMP_CTRL0_VBYPASS_SHIFT (3U) +#define OPAMP_CTRL0_VBYPASS_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_VBYPASS_SHIFT) & OPAMP_CTRL0_VBYPASS_MASK) +#define OPAMP_CTRL0_VBYPASS_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_VBYPASS_MASK) >> OPAMP_CTRL0_VBYPASS_SHIFT) + +/* + * VIP_SEL (RW) + * + */ +#define OPAMP_CTRL0_VIP_SEL_MASK (0x7U) +#define OPAMP_CTRL0_VIP_SEL_SHIFT (0U) +#define OPAMP_CTRL0_VIP_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_VIP_SEL_SHIFT) & OPAMP_CTRL0_VIP_SEL_MASK) +#define OPAMP_CTRL0_VIP_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_VIP_SEL_MASK) >> OPAMP_CTRL0_VIP_SEL_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * TRIG_CONFLICT (RWC) + * + * if more than one hardware trigger is set, will put all trigger input here; + * write any value to clear + */ +#define OPAMP_STATUS_TRIG_CONFLICT_MASK (0xFF00000UL) +#define OPAMP_STATUS_TRIG_CONFLICT_SHIFT (20U) +#define OPAMP_STATUS_TRIG_CONFLICT_SET(x) (((uint32_t)(x) << OPAMP_STATUS_TRIG_CONFLICT_SHIFT) & OPAMP_STATUS_TRIG_CONFLICT_MASK) +#define OPAMP_STATUS_TRIG_CONFLICT_GET(x) (((uint32_t)(x) & OPAMP_STATUS_TRIG_CONFLICT_MASK) >> OPAMP_STATUS_TRIG_CONFLICT_SHIFT) + +/* + * PRESET_ACT (RO) + * + * 1 for preset active; one of cur_preset is selected for OPAMP; + * 0 for no preset, OPAMP use cfg0 parameters + */ +#define OPAMP_STATUS_PRESET_ACT_MASK (0x80000UL) +#define OPAMP_STATUS_PRESET_ACT_SHIFT (19U) +#define OPAMP_STATUS_PRESET_ACT_GET(x) (((uint32_t)(x) & OPAMP_STATUS_PRESET_ACT_MASK) >> OPAMP_STATUS_PRESET_ACT_SHIFT) + +/* + * CUR_PRESET (RO) + * + * current selected preset + */ +#define OPAMP_STATUS_CUR_PRESET_MASK (0x70000UL) +#define OPAMP_STATUS_CUR_PRESET_SHIFT (16U) +#define OPAMP_STATUS_CUR_PRESET_GET(x) (((uint32_t)(x) & OPAMP_STATUS_CUR_PRESET_MASK) >> OPAMP_STATUS_CUR_PRESET_SHIFT) + +/* Bitfield definition for register: CTRL1 */ +/* + * SW_PRESET (RW) + * + * set to use preset defined by sw_sel. + * NOTE: when set, the hardware trigger will not be used + */ +#define OPAMP_CTRL1_SW_PRESET_MASK (0x80000000UL) +#define OPAMP_CTRL1_SW_PRESET_SHIFT (31U) +#define OPAMP_CTRL1_SW_PRESET_SET(x) (((uint32_t)(x) << OPAMP_CTRL1_SW_PRESET_SHIFT) & OPAMP_CTRL1_SW_PRESET_MASK) +#define OPAMP_CTRL1_SW_PRESET_GET(x) (((uint32_t)(x) & OPAMP_CTRL1_SW_PRESET_MASK) >> OPAMP_CTRL1_SW_PRESET_SHIFT) + +/* + * SW_SEL (RW) + * + */ +#define OPAMP_CTRL1_SW_SEL_MASK (0x7U) +#define OPAMP_CTRL1_SW_SEL_SHIFT (0U) +#define OPAMP_CTRL1_SW_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL1_SW_SEL_SHIFT) & OPAMP_CTRL1_SW_SEL_MASK) +#define OPAMP_CTRL1_SW_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL1_SW_SEL_MASK) >> OPAMP_CTRL1_SW_SEL_SHIFT) + +/* Bitfield definition for register of struct array CFG: CFG0 */ +/* + * DISABLE_PM_CAP (RW) + * + */ +#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK (0x8000000UL) +#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT (27U) +#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT) & OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK) +#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK) >> OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT) + +/* + * MILLER_SEL (RW) + * + */ +#define OPAMP_CFG_CFG0_MILLER_SEL_MASK (0x7000000UL) +#define OPAMP_CFG_CFG0_MILLER_SEL_SHIFT (24U) +#define OPAMP_CFG_CFG0_MILLER_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_MILLER_SEL_SHIFT) & OPAMP_CFG_CFG0_MILLER_SEL_MASK) +#define OPAMP_CFG_CFG0_MILLER_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_MILLER_SEL_MASK) >> OPAMP_CFG_CFG0_MILLER_SEL_SHIFT) + +/* + * VIM_SEL (RW) + * + */ +#define OPAMP_CFG_CFG0_VIM_SEL_MASK (0x700U) +#define OPAMP_CFG_CFG0_VIM_SEL_SHIFT (8U) +#define OPAMP_CFG_CFG0_VIM_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_VIM_SEL_SHIFT) & OPAMP_CFG_CFG0_VIM_SEL_MASK) +#define OPAMP_CFG_CFG0_VIM_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_VIM_SEL_MASK) >> OPAMP_CFG_CFG0_VIM_SEL_SHIFT) + +/* + * VIP_SEL (RW) + * + */ +#define OPAMP_CFG_CFG0_VIP_SEL_MASK (0x7U) +#define OPAMP_CFG_CFG0_VIP_SEL_SHIFT (0U) +#define OPAMP_CFG_CFG0_VIP_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_VIP_SEL_SHIFT) & OPAMP_CFG_CFG0_VIP_SEL_MASK) +#define OPAMP_CFG_CFG0_VIP_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_VIP_SEL_MASK) >> OPAMP_CFG_CFG0_VIP_SEL_SHIFT) + +/* Bitfield definition for register of struct array CFG: CFG1 */ +/* + * HW_TRIG_EN (RW) + * + * set to enable hardware trigger from moto system. + * NOTE: when sw_preset is enabled, this bit will not take effert + */ +#define OPAMP_CFG_CFG1_HW_TRIG_EN_MASK (0x80000000UL) +#define OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT (31U) +#define OPAMP_CFG_CFG1_HW_TRIG_EN_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT) & OPAMP_CFG_CFG1_HW_TRIG_EN_MASK) +#define OPAMP_CFG_CFG1_HW_TRIG_EN_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_HW_TRIG_EN_MASK) >> OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT) + +/* + * EN_LV (RW) + * + */ +#define OPAMP_CFG_CFG1_EN_LV_MASK (0x40000000UL) +#define OPAMP_CFG_CFG1_EN_LV_SHIFT (30U) +#define OPAMP_CFG_CFG1_EN_LV_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_EN_LV_SHIFT) & OPAMP_CFG_CFG1_EN_LV_MASK) +#define OPAMP_CFG_CFG1_EN_LV_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_EN_LV_MASK) >> OPAMP_CFG_CFG1_EN_LV_SHIFT) + +/* + * VBYPASS_LV (RW) + * + */ +#define OPAMP_CFG_CFG1_VBYPASS_LV_MASK (0x20000000UL) +#define OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT (29U) +#define OPAMP_CFG_CFG1_VBYPASS_LV_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT) & OPAMP_CFG_CFG1_VBYPASS_LV_MASK) +#define OPAMP_CFG_CFG1_VBYPASS_LV_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_VBYPASS_LV_MASK) >> OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT) + +/* + * MODE (RW) + * + */ +#define OPAMP_CFG_CFG1_MODE_MASK (0xF8U) +#define OPAMP_CFG_CFG1_MODE_SHIFT (3U) +#define OPAMP_CFG_CFG1_MODE_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_MODE_SHIFT) & OPAMP_CFG_CFG1_MODE_MASK) +#define OPAMP_CFG_CFG1_MODE_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_MODE_MASK) >> OPAMP_CFG_CFG1_MODE_SHIFT) + +/* + * GAIN_SEL (RW) + * + */ +#define OPAMP_CFG_CFG1_GAIN_SEL_MASK (0x7U) +#define OPAMP_CFG_CFG1_GAIN_SEL_SHIFT (0U) +#define OPAMP_CFG_CFG1_GAIN_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_GAIN_SEL_SHIFT) & OPAMP_CFG_CFG1_GAIN_SEL_MASK) +#define OPAMP_CFG_CFG1_GAIN_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_GAIN_SEL_MASK) >> OPAMP_CFG_CFG1_GAIN_SEL_SHIFT) + +/* Bitfield definition for register of struct array CFG: CFG2 */ +/* + * CHANNEL (RW) + * + */ +#define OPAMP_CFG_CFG2_CHANNEL_MASK (0x7000000UL) +#define OPAMP_CFG_CFG2_CHANNEL_SHIFT (24U) +#define OPAMP_CFG_CFG2_CHANNEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG2_CHANNEL_SHIFT) & OPAMP_CFG_CFG2_CHANNEL_MASK) +#define OPAMP_CFG_CFG2_CHANNEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG2_CHANNEL_MASK) >> OPAMP_CFG_CFG2_CHANNEL_SHIFT) + + + +/* CFG register group index macro definition */ +#define OPAMP_CFG_PRESET0 (0UL) +#define OPAMP_CFG_PRESET1 (1UL) +#define OPAMP_CFG_PRESET2 (2UL) +#define OPAMP_CFG_PRESET3 (4UL) +#define OPAMP_CFG_PRESET4 (5UL) +#define OPAMP_CFG_PRESET5 (6UL) +#define OPAMP_CFG_PRESET6 (8UL) +#define OPAMP_CFG_PRESET7 (9UL) + + +#endif /* HPM_OPAMP_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h index 5b531606..dd9afb5e 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_pdm_regs.h @@ -23,6 +23,7 @@ typedef struct { __RW uint32_t MEMDATA; /* 0x28: Memory Access Data */ __RW uint32_t HPF_MA; /* 0x2C: HPF A Coef Register */ __RW uint32_t HPF_B; /* 0x30: HPF B Coef Register */ + __RW uint32_t ALT_IN_CTRL; /* 0x34: Alternative input control register */ } PDM_Type; @@ -486,6 +487,17 @@ typedef struct { #define PDM_HPF_B_COEF_SET(x) (((uint32_t)(x) << PDM_HPF_B_COEF_SHIFT) & PDM_HPF_B_COEF_MASK) #define PDM_HPF_B_COEF_GET(x) (((uint32_t)(x) & PDM_HPF_B_COEF_MASK) >> PDM_HPF_B_COEF_SHIFT) +/* Bitfield definition for register: ALT_IN_CTRL */ +/* + * OP (RW) + * + * Select the alternative input when asserted to be 1 + */ +#define PDM_ALT_IN_CTRL_OP_MASK (0xFFU) +#define PDM_ALT_IN_CTRL_OP_SHIFT (0U) +#define PDM_ALT_IN_CTRL_OP_SET(x) (((uint32_t)(x) << PDM_ALT_IN_CTRL_OP_SHIFT) & PDM_ALT_IN_CTRL_OP_MASK) +#define PDM_ALT_IN_CTRL_OP_GET(x) (((uint32_t)(x) & PDM_ALT_IN_CTRL_OP_MASK) >> PDM_ALT_IN_CTRL_OP_SHIFT) + diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h index a4e295da..4d880787 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_pdma_regs.h @@ -194,12 +194,13 @@ typedef struct { #define PDMA_STAT_BLOCKX_GET(x) (((uint32_t)(x) & PDMA_STAT_BLOCKX_MASK) >> PDMA_STAT_BLOCKX_SHIFT) /* - * PDMA_DONE (RO) + * PDMA_DONE (W1C) * * PDMA one image done */ #define PDMA_STAT_PDMA_DONE_MASK (0x200U) #define PDMA_STAT_PDMA_DONE_SHIFT (9U) +#define PDMA_STAT_PDMA_DONE_SET(x) (((uint32_t)(x) << PDMA_STAT_PDMA_DONE_SHIFT) & PDMA_STAT_PDMA_DONE_MASK) #define PDMA_STAT_PDMA_DONE_GET(x) (((uint32_t)(x) & PDMA_STAT_PDMA_DONE_MASK) >> PDMA_STAT_PDMA_DONE_SHIFT) /* @@ -242,13 +243,12 @@ typedef struct { #define PDMA_STAT_AXI_0_READ_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_0_READ_ERR_MASK) >> PDMA_STAT_AXI_0_READ_ERR_SHIFT) /* - * IRQ (W1C) + * IRQ (RO) * * Asserted to indicate a IRQ event */ #define PDMA_STAT_IRQ_MASK (0x1U) #define PDMA_STAT_IRQ_SHIFT (0U) -#define PDMA_STAT_IRQ_SET(x) (((uint32_t)(x) << PDMA_STAT_IRQ_SHIFT) & PDMA_STAT_IRQ_MASK) #define PDMA_STAT_IRQ_GET(x) (((uint32_t)(x) & PDMA_STAT_IRQ_MASK) >> PDMA_STAT_IRQ_SHIFT) /* Bitfield definition for register: OUT_CTRL */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_plb_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_plb_regs.h new file mode 100644 index 00000000..de378bef --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_plb_regs.h @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_PLB_H +#define HPM_PLB_H + +typedef struct { + struct { + __RW uint32_t LOOKUP_TABLE[4]; /* 0x0 - 0xC: TYPE A CHN lookup_table 0 */ + __RW uint32_t SW_INJECT; /* 0x10: TYPE A CHN software inject */ + __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ + } TYPE_A[4]; + __R uint8_t RESERVED0[896]; /* 0x80 - 0x3FF: Reserved */ + struct { + __RW uint32_t LUT[2]; /* 0x400 - 0x404: TYPE B CHN lookup table 0 */ + __RW uint32_t CMP[4]; /* 0x408 - 0x414: TYPE B CHN data unit cmp0 */ + __RW uint32_t MODE; /* 0x418: TYPE B CHN mode ctrl */ + __RW uint32_t SW_INJECT; /* 0x41C: TYPE B CHN software inject */ + } TYPE_B[4]; +} PLB_Type; + + +/* Bitfield definition for register of struct array TYPE_A: 0 */ +/* + * LOOKUP_TABLE (RW) + * + * using 4 bit trig_in as lookup index. software can program this register as trig_in's true table. + */ +#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK (0xFFFFU) +#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT (0U) +#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SET(x) (((uint32_t)(x) << PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT) & PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK) +#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_GET(x) (((uint32_t)(x) & PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK) >> PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT) + +/* Bitfield definition for register of struct array TYPE_A: SW_INJECT */ +/* + * SW_INJECT (RW) + * + * software can inject value to TYPEA's output + */ +#define PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK (0xFU) +#define PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT (0U) +#define PLB_TYPE_A_SW_INJECT_SW_INJECT_SET(x) (((uint32_t)(x) << PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT) & PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK) +#define PLB_TYPE_A_SW_INJECT_SW_INJECT_GET(x) (((uint32_t)(x) & PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK) >> PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT) + +/* Bitfield definition for register of struct array TYPE_B: 0 */ +/* + * LOOKUP_TABLE (RW) + * + * lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in + */ +#define PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK (0xFFFFFFFFUL) +#define PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT (0U) +#define PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(x) (((uint32_t)(x) << PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT) & PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK) +#define PLB_TYPE_B_LUT_LOOKUP_TABLE_GET(x) (((uint32_t)(x) & PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK) >> PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT) + +/* Bitfield definition for register of struct array TYPE_B: 0 */ +/* + * CMP_VALUE (RW) + * + * cmp value, using as data unit operation + */ +#define PLB_TYPE_B_CMP_CMP_VALUE_MASK (0xFFFFFFFFUL) +#define PLB_TYPE_B_CMP_CMP_VALUE_SHIFT (0U) +#define PLB_TYPE_B_CMP_CMP_VALUE_SET(x) (((uint32_t)(x) << PLB_TYPE_B_CMP_CMP_VALUE_SHIFT) & PLB_TYPE_B_CMP_CMP_VALUE_MASK) +#define PLB_TYPE_B_CMP_CMP_VALUE_GET(x) (((uint32_t)(x) & PLB_TYPE_B_CMP_CMP_VALUE_MASK) >> PLB_TYPE_B_CMP_CMP_VALUE_SHIFT) + +/* Bitfield definition for register of struct array TYPE_B: MODE */ +/* + * OPT_SEL (RW) + * + * operation selection in data unit. + */ +#define PLB_TYPE_B_MODE_OPT_SEL_MASK (0x10000UL) +#define PLB_TYPE_B_MODE_OPT_SEL_SHIFT (16U) +#define PLB_TYPE_B_MODE_OPT_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OPT_SEL_SHIFT) & PLB_TYPE_B_MODE_OPT_SEL_MASK) +#define PLB_TYPE_B_MODE_OPT_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OPT_SEL_MASK) >> PLB_TYPE_B_MODE_OPT_SEL_SHIFT) + +/* + * OUT3_SEL (RW) + * + * trig out 3 output type in current channel + */ +#define PLB_TYPE_B_MODE_OUT3_SEL_MASK (0xF000U) +#define PLB_TYPE_B_MODE_OUT3_SEL_SHIFT (12U) +#define PLB_TYPE_B_MODE_OUT3_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT3_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT3_SEL_MASK) +#define PLB_TYPE_B_MODE_OUT3_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT3_SEL_MASK) >> PLB_TYPE_B_MODE_OUT3_SEL_SHIFT) + +/* + * OUT2_SEL (RW) + * + * trig out 2 output type in current channel + */ +#define PLB_TYPE_B_MODE_OUT2_SEL_MASK (0xF00U) +#define PLB_TYPE_B_MODE_OUT2_SEL_SHIFT (8U) +#define PLB_TYPE_B_MODE_OUT2_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT2_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT2_SEL_MASK) +#define PLB_TYPE_B_MODE_OUT2_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT2_SEL_MASK) >> PLB_TYPE_B_MODE_OUT2_SEL_SHIFT) + +/* + * OUT1_SEL (RW) + * + * trig out 1 output type in current channel + */ +#define PLB_TYPE_B_MODE_OUT1_SEL_MASK (0xF0U) +#define PLB_TYPE_B_MODE_OUT1_SEL_SHIFT (4U) +#define PLB_TYPE_B_MODE_OUT1_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT1_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT1_SEL_MASK) +#define PLB_TYPE_B_MODE_OUT1_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT1_SEL_MASK) >> PLB_TYPE_B_MODE_OUT1_SEL_SHIFT) + +/* + * OUT0_SEL (RW) + * + * trig out 0 output type in current channel + */ +#define PLB_TYPE_B_MODE_OUT0_SEL_MASK (0xFU) +#define PLB_TYPE_B_MODE_OUT0_SEL_SHIFT (0U) +#define PLB_TYPE_B_MODE_OUT0_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT0_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT0_SEL_MASK) +#define PLB_TYPE_B_MODE_OUT0_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT0_SEL_MASK) >> PLB_TYPE_B_MODE_OUT0_SEL_SHIFT) + +/* Bitfield definition for register of struct array TYPE_B: SW_INJECT */ +/* + * SOFTWARE_INJECT (RW) + * + * data unit value can be changed if program this register + */ +#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK (0xFFFFFFFFUL) +#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT (0U) +#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT) & PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK) +#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK) >> PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT) + + + +/* LOOKUP_TABLE register group index macro definition */ +#define PLB_TYPE_A_LOOKUP_TABLE_0 (0UL) +#define PLB_TYPE_A_LOOKUP_TABLE_1 (1UL) +#define PLB_TYPE_A_LOOKUP_TABLE_2 (2UL) +#define PLB_TYPE_A_LOOKUP_TABLE_3 (3UL) + +/* TYPE_A register group index macro definition */ +#define PLB_TYPE_A_0 (0UL) +#define PLB_TYPE_A_1 (1UL) +#define PLB_TYPE_A_2 (2UL) +#define PLB_TYPE_A_3 (3UL) + +/* LUT register group index macro definition */ +#define PLB_TYPE_B_LUT_0 (0UL) +#define PLB_TYPE_B_LUT_1 (1UL) + +/* CMP register group index macro definition */ +#define PLB_TYPE_B_CMP_0 (0UL) +#define PLB_TYPE_B_CMP_1 (1UL) +#define PLB_TYPE_B_CMP_2 (2UL) +#define PLB_TYPE_B_CMP_3 (3UL) + +/* TYPE_B register group index macro definition */ +#define PLB_TYPE_B_0 (0UL) +#define PLB_TYPE_B_1 (1UL) +#define PLB_TYPE_B_2 (2UL) +#define PLB_TYPE_B_3 (3UL) + + +#endif /* HPM_PLB_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h index 39d8f065..1c68c398 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_ptpc_regs.h @@ -29,6 +29,8 @@ typedef struct { __RW uint32_t TIME_SEL; /* 0x2000: */ __W uint32_t INT_STS; /* 0x2004: */ __RW uint32_t INT_EN; /* 0x2008: */ + __R uint8_t RESERVED0[4084]; /* 0x200C - 0x2FFF: Reserved */ + __RW uint32_t PTPC_CAN_TS_SEL; /* 0x3000: */ } PTPC_Type; @@ -109,8 +111,8 @@ typedef struct { /* * FINE_COARSE_SEL (RW) * - * 0: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - * 1: coarse update, ns counter add ss_incr[7:0] each clk + * 0: coarse update, ns counter add ss_incr[7:0] each clk + * 1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow */ #define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK (0x2U) #define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT (1U) @@ -399,6 +401,43 @@ typedef struct { #define PTPC_INT_EN_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS0_SHIFT) & PTPC_INT_EN_PPS_INT_STS0_MASK) #define PTPC_INT_EN_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS0_MASK) >> PTPC_INT_EN_PPS_INT_STS0_SHIFT) +/* Bitfield definition for register: PTPC_CAN_TS_SEL */ +/* + * TSU_TBIN3_SEL (RW) + * + */ +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK (0xFC000000UL) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT (26U) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) + +/* + * TSU_TBIN2_SEL (RW) + * + */ +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK (0x3F00000UL) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT (20U) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) + +/* + * TSU_TBIN1_SEL (RW) + * + */ +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK (0xFC000UL) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT (14U) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) + +/* + * TSU_TBIN0_SEL (RW) + * + */ +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK (0x3F00U) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT (8U) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) +#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) + /* PTPC register group index macro definition */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_qeiv2_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_qeiv2_regs.h new file mode 100644 index 00000000..0de6ead4 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_qeiv2_regs.h @@ -0,0 +1,2000 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_QEIV2_H +#define HPM_QEIV2_H + +typedef struct { + __RW uint32_t CR; /* 0x0: Control register */ + __RW uint32_t PHCFG; /* 0x4: Phase configure register */ + __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ + __RW uint32_t PHIDX; /* 0xC: Phase index register */ + __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */ + __RW uint32_t READEN; /* 0x14: Read event enable register */ + __RW uint32_t ZCMP; /* 0x18: Z comparator */ + __RW uint32_t PHCMP; /* 0x1C: Phase comparator */ + __RW uint32_t SPDCMP; /* 0x20: Speed comparator */ + __RW uint32_t DMAEN; /* 0x24: DMA request enable register */ + __RW uint32_t SR; /* 0x28: Status register */ + __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */ + struct { + __RW uint32_t Z; /* 0x30: Z counter */ + __R uint32_t PH; /* 0x34: Phase counter */ + __RW uint32_t SPD; /* 0x38: Speed counter */ + __R uint32_t TMR; /* 0x3C: Timer counter */ + } COUNT[4]; + __R uint8_t RESERVED0[16]; /* 0x70 - 0x7F: Reserved */ + __RW uint32_t ZCMP2; /* 0x80: Z comparator */ + __RW uint32_t PHCMP2; /* 0x84: Phase comparator */ + __RW uint32_t SPDCMP2; /* 0x88: Speed comparator */ + __RW uint32_t MATCH_CFG; /* 0x8C: */ + __RW uint32_t FILT_CFG[6]; /* 0x90 - 0xA4: A signal filter config */ + __R uint8_t RESERVED1[88]; /* 0xA8 - 0xFF: Reserved */ + __RW uint32_t QEI_CFG; /* 0x100: qei config register */ + __R uint8_t RESERVED2[12]; /* 0x104 - 0x10F: Reserved */ + __RW uint32_t PULSE0_NUM; /* 0x110: pulse0_num */ + __RW uint32_t PULSE1_NUM; /* 0x114: pulse1_num */ + __R uint32_t CYCLE0_CNT; /* 0x118: cycle0_cnt */ + __R uint32_t CYCLE0PULSE_CNT; /* 0x11C: cycle0pulse_cnt */ + __R uint32_t CYCLE1_CNT; /* 0x120: cycle1_cnt */ + __R uint32_t CYCLE1PULSE_CNT; /* 0x124: cycle1pulse_cnt */ + __R uint32_t CYCLE0_SNAP0; /* 0x128: cycle0_snap0 */ + __R uint32_t CYCLE0_SNAP1; /* 0x12C: cycle0_snap1 */ + __R uint32_t CYCLE1_SNAP0; /* 0x130: cycle1_snap0 */ + __R uint32_t CYCLE1_SNAP1; /* 0x134: cycle1_snap1 */ + __R uint8_t RESERVED3[8]; /* 0x138 - 0x13F: Reserved */ + __RW uint32_t CYCLE0_NUM; /* 0x140: cycle0_num */ + __RW uint32_t CYCLE1_NUM; /* 0x144: cycle1_num */ + __R uint32_t PULSE0_CNT; /* 0x148: pulse0_cnt */ + __R uint32_t PULSE0CYCLE_CNT; /* 0x14C: pulse0cycle_cnt */ + __R uint32_t PULSE1_CNT; /* 0x150: pulse1_cnt */ + __R uint32_t PULSE1CYCLE_CNT; /* 0x154: pulse1cycle_cnt */ + __R uint32_t PULSE0_SNAP0; /* 0x158: pulse0_snap0 */ + __R uint32_t PULSE0CYCLE_SNAP0; /* 0x15C: pulse0cycle_snap0 */ + __R uint32_t PULSE0_SNAP1; /* 0x160: pulse0_snap1 */ + __R uint32_t PULSE0CYCLE_SNAP1; /* 0x164: pulse0cycle_snap1 */ + __R uint32_t PULSE1_SNAP0; /* 0x168: pulse1_snap0 */ + __R uint32_t PULSE1CYCLE_SNAP0; /* 0x16C: pulse1cycle_snap0 */ + __R uint32_t PULSE1_SNAP1; /* 0x170: pulse1_snap1 */ + __R uint32_t PULSE1CYCLE_SNAP1; /* 0x174: pulse1cycle_snap1 */ + __R uint8_t RESERVED4[136]; /* 0x178 - 0x1FF: Reserved */ + __RW uint32_t ADCX_CFG0; /* 0x200: adcx_cfg0 */ + __RW uint32_t ADCX_CFG1; /* 0x204: adcx_cfg1 */ + __RW uint32_t ADCX_CFG2; /* 0x208: adcx_cfg2 */ + __R uint8_t RESERVED5[4]; /* 0x20C - 0x20F: Reserved */ + __RW uint32_t ADCY_CFG0; /* 0x210: adcy_cfg0 */ + __RW uint32_t ADCY_CFG1; /* 0x214: adcy_cfg1 */ + __RW uint32_t ADCY_CFG2; /* 0x218: adcy_cfg2 */ + __R uint8_t RESERVED6[4]; /* 0x21C - 0x21F: Reserved */ + __RW uint32_t CAL_CFG; /* 0x220: cal_cfg */ + __R uint8_t RESERVED7[12]; /* 0x224 - 0x22F: Reserved */ + __RW uint32_t PHASE_PARAM; /* 0x230: phase_param */ + __RW uint32_t ANGLE_ADJ; /* 0x234: angle_adj */ + __RW uint32_t POS_THRESHOLD; /* 0x238: pos_threshold */ + __R uint8_t RESERVED8[4]; /* 0x23C - 0x23F: Reserved */ + __RW uint32_t UVW_POS[6]; /* 0x240 - 0x254: uvw_pos0 */ + __RW uint32_t UVW_POS_CFG[6]; /* 0x258 - 0x26C: */ + __R uint8_t RESERVED9[16]; /* 0x270 - 0x27F: Reserved */ + __RW uint32_t PHASE_CNT; /* 0x280: phase_cnt */ + __W uint32_t PHASE_UPDATE; /* 0x284: phase_update */ + __RW uint32_t POSITION; /* 0x288: position */ + __W uint32_t POSITION_UPDATE; /* 0x28C: position_update */ + __R uint32_t ANGLE; /* 0x290: */ + __RW uint32_t POS_TIMEOUT; /* 0x294: pos_timeout */ +} QEIV2_Type; + + +/* Bitfield definition for register: CR */ +/* + * READ (WO) + * + * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 + */ +#define QEIV2_CR_READ_MASK (0x80000000UL) +#define QEIV2_CR_READ_SHIFT (31U) +#define QEIV2_CR_READ_SET(x) (((uint32_t)(x) << QEIV2_CR_READ_SHIFT) & QEIV2_CR_READ_MASK) +#define QEIV2_CR_READ_GET(x) (((uint32_t)(x) & QEIV2_CR_READ_MASK) >> QEIV2_CR_READ_SHIFT) + +/* + * ZCNTCFG (RW) + * + * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 + * 0- zcnt will increment or decrement when Z input assert + */ +#define QEIV2_CR_ZCNTCFG_MASK (0x400000UL) +#define QEIV2_CR_ZCNTCFG_SHIFT (22U) +#define QEIV2_CR_ZCNTCFG_SET(x) (((uint32_t)(x) << QEIV2_CR_ZCNTCFG_SHIFT) & QEIV2_CR_ZCNTCFG_MASK) +#define QEIV2_CR_ZCNTCFG_GET(x) (((uint32_t)(x) & QEIV2_CR_ZCNTCFG_MASK) >> QEIV2_CR_ZCNTCFG_SHIFT) + +/* + * PHCALIZ (RW) + * + * 1- phcnt will set to phidx when Z input assert(for abz digital signsl) + */ +#define QEIV2_CR_PHCALIZ_MASK (0x200000UL) +#define QEIV2_CR_PHCALIZ_SHIFT (21U) +#define QEIV2_CR_PHCALIZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PHCALIZ_SHIFT) & QEIV2_CR_PHCALIZ_MASK) +#define QEIV2_CR_PHCALIZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PHCALIZ_MASK) >> QEIV2_CR_PHCALIZ_SHIFT) + +/* + * Z_ONLY_EN (RW) + * + * 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz) + */ +#define QEIV2_CR_Z_ONLY_EN_MASK (0x100000UL) +#define QEIV2_CR_Z_ONLY_EN_SHIFT (20U) +#define QEIV2_CR_Z_ONLY_EN_SET(x) (((uint32_t)(x) << QEIV2_CR_Z_ONLY_EN_SHIFT) & QEIV2_CR_Z_ONLY_EN_MASK) +#define QEIV2_CR_Z_ONLY_EN_GET(x) (((uint32_t)(x) & QEIV2_CR_Z_ONLY_EN_MASK) >> QEIV2_CR_Z_ONLY_EN_SHIFT) + +/* + * H2FDIR0 (RW) + * + */ +#define QEIV2_CR_H2FDIR0_MASK (0x80000UL) +#define QEIV2_CR_H2FDIR0_SHIFT (19U) +#define QEIV2_CR_H2FDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR0_SHIFT) & QEIV2_CR_H2FDIR0_MASK) +#define QEIV2_CR_H2FDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR0_MASK) >> QEIV2_CR_H2FDIR0_SHIFT) + +/* + * H2FDIR1 (RW) + * + */ +#define QEIV2_CR_H2FDIR1_MASK (0x40000UL) +#define QEIV2_CR_H2FDIR1_SHIFT (18U) +#define QEIV2_CR_H2FDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR1_SHIFT) & QEIV2_CR_H2FDIR1_MASK) +#define QEIV2_CR_H2FDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR1_MASK) >> QEIV2_CR_H2FDIR1_SHIFT) + +/* + * H2RDIR0 (RW) + * + */ +#define QEIV2_CR_H2RDIR0_MASK (0x20000UL) +#define QEIV2_CR_H2RDIR0_SHIFT (17U) +#define QEIV2_CR_H2RDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR0_SHIFT) & QEIV2_CR_H2RDIR0_MASK) +#define QEIV2_CR_H2RDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR0_MASK) >> QEIV2_CR_H2RDIR0_SHIFT) + +/* + * H2RDIR1 (RW) + * + */ +#define QEIV2_CR_H2RDIR1_MASK (0x10000UL) +#define QEIV2_CR_H2RDIR1_SHIFT (16U) +#define QEIV2_CR_H2RDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR1_SHIFT) & QEIV2_CR_H2RDIR1_MASK) +#define QEIV2_CR_H2RDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR1_MASK) >> QEIV2_CR_H2RDIR1_SHIFT) + +/* + * PAUSEPOS (RW) + * + * 1- pause position output valid when PAUSE assert + */ +#define QEIV2_CR_PAUSEPOS_MASK (0x8000U) +#define QEIV2_CR_PAUSEPOS_SHIFT (15U) +#define QEIV2_CR_PAUSEPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPOS_SHIFT) & QEIV2_CR_PAUSEPOS_MASK) +#define QEIV2_CR_PAUSEPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPOS_MASK) >> QEIV2_CR_PAUSEPOS_SHIFT) + +/* + * PAUSESPD (RW) + * + * 1- pause spdcnt when PAUSE assert + */ +#define QEIV2_CR_PAUSESPD_MASK (0x4000U) +#define QEIV2_CR_PAUSESPD_SHIFT (14U) +#define QEIV2_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSESPD_SHIFT) & QEIV2_CR_PAUSESPD_MASK) +#define QEIV2_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSESPD_MASK) >> QEIV2_CR_PAUSESPD_SHIFT) + +/* + * PAUSEPH (RW) + * + * 1- pause phcnt when PAUSE assert + */ +#define QEIV2_CR_PAUSEPH_MASK (0x2000U) +#define QEIV2_CR_PAUSEPH_SHIFT (13U) +#define QEIV2_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPH_SHIFT) & QEIV2_CR_PAUSEPH_MASK) +#define QEIV2_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPH_MASK) >> QEIV2_CR_PAUSEPH_SHIFT) + +/* + * PAUSEZ (RW) + * + * 1- pause zcnt when PAUSE assert + */ +#define QEIV2_CR_PAUSEZ_MASK (0x1000U) +#define QEIV2_CR_PAUSEZ_SHIFT (12U) +#define QEIV2_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEZ_SHIFT) & QEIV2_CR_PAUSEZ_MASK) +#define QEIV2_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEZ_MASK) >> QEIV2_CR_PAUSEZ_SHIFT) + +/* + * HFDIR0 (RW) + * + * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) + */ +#define QEIV2_CR_HFDIR0_MASK (0x800U) +#define QEIV2_CR_HFDIR0_SHIFT (11U) +#define QEIV2_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR0_SHIFT) & QEIV2_CR_HFDIR0_MASK) +#define QEIV2_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR0_MASK) >> QEIV2_CR_HFDIR0_SHIFT) + +/* + * HFDIR1 (RW) + * + * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) + */ +#define QEIV2_CR_HFDIR1_MASK (0x400U) +#define QEIV2_CR_HFDIR1_SHIFT (10U) +#define QEIV2_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR1_SHIFT) & QEIV2_CR_HFDIR1_MASK) +#define QEIV2_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR1_MASK) >> QEIV2_CR_HFDIR1_SHIFT) + +/* + * HRDIR0 (RW) + * + * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) + */ +#define QEIV2_CR_HRDIR0_MASK (0x200U) +#define QEIV2_CR_HRDIR0_SHIFT (9U) +#define QEIV2_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR0_SHIFT) & QEIV2_CR_HRDIR0_MASK) +#define QEIV2_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR0_MASK) >> QEIV2_CR_HRDIR0_SHIFT) + +/* + * HRDIR1 (RW) + * + * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) + */ +#define QEIV2_CR_HRDIR1_MASK (0x100U) +#define QEIV2_CR_HRDIR1_SHIFT (8U) +#define QEIV2_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR1_SHIFT) & QEIV2_CR_HRDIR1_MASK) +#define QEIV2_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR1_MASK) >> QEIV2_CR_HRDIR1_SHIFT) + +/* + * FAULTPOS (RW) + * + */ +#define QEIV2_CR_FAULTPOS_MASK (0x40U) +#define QEIV2_CR_FAULTPOS_SHIFT (6U) +#define QEIV2_CR_FAULTPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_FAULTPOS_SHIFT) & QEIV2_CR_FAULTPOS_MASK) +#define QEIV2_CR_FAULTPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_FAULTPOS_MASK) >> QEIV2_CR_FAULTPOS_SHIFT) + +/* + * SNAPEN (RW) + * + * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert + */ +#define QEIV2_CR_SNAPEN_MASK (0x20U) +#define QEIV2_CR_SNAPEN_SHIFT (5U) +#define QEIV2_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEIV2_CR_SNAPEN_SHIFT) & QEIV2_CR_SNAPEN_MASK) +#define QEIV2_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEIV2_CR_SNAPEN_MASK) >> QEIV2_CR_SNAPEN_SHIFT) + +/* + * RSTCNT (RW) + * + * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx + */ +#define QEIV2_CR_RSTCNT_MASK (0x10U) +#define QEIV2_CR_RSTCNT_SHIFT (4U) +#define QEIV2_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEIV2_CR_RSTCNT_SHIFT) & QEIV2_CR_RSTCNT_MASK) +#define QEIV2_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEIV2_CR_RSTCNT_MASK) >> QEIV2_CR_RSTCNT_SHIFT) + +/* + * RD_SEL (RW) + * + * define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, width_snap0,width_snap1, timer_snap0, timer_snap1) + * 0 : same as hpm1000/500/500s; + * 1: use width for position; use timer for angle + */ +#define QEIV2_CR_RD_SEL_MASK (0x8U) +#define QEIV2_CR_RD_SEL_SHIFT (3U) +#define QEIV2_CR_RD_SEL_SET(x) (((uint32_t)(x) << QEIV2_CR_RD_SEL_SHIFT) & QEIV2_CR_RD_SEL_MASK) +#define QEIV2_CR_RD_SEL_GET(x) (((uint32_t)(x) & QEIV2_CR_RD_SEL_MASK) >> QEIV2_CR_RD_SEL_SHIFT) + +/* + * ENCTYP (RW) + * + * 000-abz; 001-pd; 010-ud; 011-UVW(hal) + * 100-single A; 101-single sin; 110: sin&cos + */ +#define QEIV2_CR_ENCTYP_MASK (0x7U) +#define QEIV2_CR_ENCTYP_SHIFT (0U) +#define QEIV2_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEIV2_CR_ENCTYP_SHIFT) & QEIV2_CR_ENCTYP_MASK) +#define QEIV2_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEIV2_CR_ENCTYP_MASK) >> QEIV2_CR_ENCTYP_SHIFT) + +/* Bitfield definition for register: PHCFG */ +/* + * PHMAX (RW) + * + * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax + */ +#define QEIV2_PHCFG_PHMAX_MASK (0xFFFFFFFFUL) +#define QEIV2_PHCFG_PHMAX_SHIFT (0U) +#define QEIV2_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEIV2_PHCFG_PHMAX_SHIFT) & QEIV2_PHCFG_PHMAX_MASK) +#define QEIV2_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEIV2_PHCFG_PHMAX_MASK) >> QEIV2_PHCFG_PHMAX_SHIFT) + +/* Bitfield definition for register: WDGCFG */ +/* + * WDGEN (RW) + * + * 1- enable wdog counter + */ +#define QEIV2_WDGCFG_WDGEN_MASK (0x80000000UL) +#define QEIV2_WDGCFG_WDGEN_SHIFT (31U) +#define QEIV2_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGEN_SHIFT) & QEIV2_WDGCFG_WDGEN_MASK) +#define QEIV2_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGEN_MASK) >> QEIV2_WDGCFG_WDGEN_SHIFT) + +/* + * WDOG_CFG (RW) + * + * define as stop if phase_cnt change is less than it + * if 0, then each change of phase_cnt will clear wdog counter; + * if 2, then phase_cnt change larger than 2 will clear wdog counter + */ +#define QEIV2_WDGCFG_WDOG_CFG_MASK (0x70000000UL) +#define QEIV2_WDGCFG_WDOG_CFG_SHIFT (28U) +#define QEIV2_WDGCFG_WDOG_CFG_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDOG_CFG_SHIFT) & QEIV2_WDGCFG_WDOG_CFG_MASK) +#define QEIV2_WDGCFG_WDOG_CFG_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDOG_CFG_MASK) >> QEIV2_WDGCFG_WDOG_CFG_SHIFT) + +/* + * WDGTO (RW) + * + * watch dog timeout value + */ +#define QEIV2_WDGCFG_WDGTO_MASK (0xFFFFFFFUL) +#define QEIV2_WDGCFG_WDGTO_SHIFT (0U) +#define QEIV2_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGTO_SHIFT) & QEIV2_WDGCFG_WDGTO_MASK) +#define QEIV2_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGTO_MASK) >> QEIV2_WDGCFG_WDGTO_SHIFT) + +/* Bitfield definition for register: PHIDX */ +/* + * PHIDX (RW) + * + * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 + */ +#define QEIV2_PHIDX_PHIDX_MASK (0xFFFFFFFFUL) +#define QEIV2_PHIDX_PHIDX_SHIFT (0U) +#define QEIV2_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEIV2_PHIDX_PHIDX_SHIFT) & QEIV2_PHIDX_PHIDX_MASK) +#define QEIV2_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEIV2_PHIDX_PHIDX_MASK) >> QEIV2_PHIDX_PHIDX_SHIFT) + +/* Bitfield definition for register: TRGOEN */ +/* + * WDGFEN (RW) + * + * 1- enable trigger output when wdg flag set + */ +#define QEIV2_TRGOEN_WDGFEN_MASK (0x80000000UL) +#define QEIV2_TRGOEN_WDGFEN_SHIFT (31U) +#define QEIV2_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WDGFEN_SHIFT) & QEIV2_TRGOEN_WDGFEN_MASK) +#define QEIV2_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WDGFEN_MASK) >> QEIV2_TRGOEN_WDGFEN_SHIFT) + +/* + * HOMEFEN (RW) + * + * 1- enable trigger output when homef flag set + */ +#define QEIV2_TRGOEN_HOMEFEN_MASK (0x40000000UL) +#define QEIV2_TRGOEN_HOMEFEN_SHIFT (30U) +#define QEIV2_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOMEFEN_SHIFT) & QEIV2_TRGOEN_HOMEFEN_MASK) +#define QEIV2_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOMEFEN_MASK) >> QEIV2_TRGOEN_HOMEFEN_SHIFT) + +/* + * POSCMPFEN (RW) + * + * 1- enable trigger output when poscmpf flag set + */ +#define QEIV2_TRGOEN_POSCMPFEN_MASK (0x20000000UL) +#define QEIV2_TRGOEN_POSCMPFEN_SHIFT (29U) +#define QEIV2_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POSCMPFEN_SHIFT) & QEIV2_TRGOEN_POSCMPFEN_MASK) +#define QEIV2_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POSCMPFEN_MASK) >> QEIV2_TRGOEN_POSCMPFEN_SHIFT) + +/* + * ZPHFEN (RW) + * + * 1- enable trigger output when zphf flag set + */ +#define QEIV2_TRGOEN_ZPHFEN_MASK (0x10000000UL) +#define QEIV2_TRGOEN_ZPHFEN_SHIFT (28U) +#define QEIV2_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZPHFEN_SHIFT) & QEIV2_TRGOEN_ZPHFEN_MASK) +#define QEIV2_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZPHFEN_MASK) >> QEIV2_TRGOEN_ZPHFEN_SHIFT) + +/* + * ZMISSFEN (RW) + * + */ +#define QEIV2_TRGOEN_ZMISSFEN_MASK (0x8000000UL) +#define QEIV2_TRGOEN_ZMISSFEN_SHIFT (27U) +#define QEIV2_TRGOEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZMISSFEN_SHIFT) & QEIV2_TRGOEN_ZMISSFEN_MASK) +#define QEIV2_TRGOEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZMISSFEN_MASK) >> QEIV2_TRGOEN_ZMISSFEN_SHIFT) + +/* + * WIDTHTMFEN (RW) + * + */ +#define QEIV2_TRGOEN_WIDTHTMFEN_MASK (0x4000000UL) +#define QEIV2_TRGOEN_WIDTHTMFEN_SHIFT (26U) +#define QEIV2_TRGOEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) +#define QEIV2_TRGOEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) >> QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) + +/* + * POS2CMPFEN (RW) + * + */ +#define QEIV2_TRGOEN_POS2CMPFEN_MASK (0x2000000UL) +#define QEIV2_TRGOEN_POS2CMPFEN_SHIFT (25U) +#define QEIV2_TRGOEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POS2CMPFEN_SHIFT) & QEIV2_TRGOEN_POS2CMPFEN_MASK) +#define QEIV2_TRGOEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POS2CMPFEN_MASK) >> QEIV2_TRGOEN_POS2CMPFEN_SHIFT) + +/* + * DIRCHGFEN (RW) + * + */ +#define QEIV2_TRGOEN_DIRCHGFEN_MASK (0x1000000UL) +#define QEIV2_TRGOEN_DIRCHGFEN_SHIFT (24U) +#define QEIV2_TRGOEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_DIRCHGFEN_SHIFT) & QEIV2_TRGOEN_DIRCHGFEN_MASK) +#define QEIV2_TRGOEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_DIRCHGFEN_MASK) >> QEIV2_TRGOEN_DIRCHGFEN_SHIFT) + +/* + * CYCLE0FEN (RW) + * + */ +#define QEIV2_TRGOEN_CYCLE0FEN_MASK (0x800000UL) +#define QEIV2_TRGOEN_CYCLE0FEN_SHIFT (23U) +#define QEIV2_TRGOEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE0FEN_SHIFT) & QEIV2_TRGOEN_CYCLE0FEN_MASK) +#define QEIV2_TRGOEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE0FEN_MASK) >> QEIV2_TRGOEN_CYCLE0FEN_SHIFT) + +/* + * CYCLE1FEN (RW) + * + */ +#define QEIV2_TRGOEN_CYCLE1FEN_MASK (0x400000UL) +#define QEIV2_TRGOEN_CYCLE1FEN_SHIFT (22U) +#define QEIV2_TRGOEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE1FEN_SHIFT) & QEIV2_TRGOEN_CYCLE1FEN_MASK) +#define QEIV2_TRGOEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE1FEN_MASK) >> QEIV2_TRGOEN_CYCLE1FEN_SHIFT) + +/* + * PULSE0FEN (RW) + * + */ +#define QEIV2_TRGOEN_PULSE0FEN_MASK (0x200000UL) +#define QEIV2_TRGOEN_PULSE0FEN_SHIFT (21U) +#define QEIV2_TRGOEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE0FEN_SHIFT) & QEIV2_TRGOEN_PULSE0FEN_MASK) +#define QEIV2_TRGOEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE0FEN_MASK) >> QEIV2_TRGOEN_PULSE0FEN_SHIFT) + +/* + * PULSE1FEN (RW) + * + */ +#define QEIV2_TRGOEN_PULSE1FEN_MASK (0x100000UL) +#define QEIV2_TRGOEN_PULSE1FEN_SHIFT (20U) +#define QEIV2_TRGOEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE1FEN_SHIFT) & QEIV2_TRGOEN_PULSE1FEN_MASK) +#define QEIV2_TRGOEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE1FEN_MASK) >> QEIV2_TRGOEN_PULSE1FEN_SHIFT) + +/* + * HOME2FEN (RW) + * + */ +#define QEIV2_TRGOEN_HOME2FEN_MASK (0x80000UL) +#define QEIV2_TRGOEN_HOME2FEN_SHIFT (19U) +#define QEIV2_TRGOEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOME2FEN_SHIFT) & QEIV2_TRGOEN_HOME2FEN_MASK) +#define QEIV2_TRGOEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOME2FEN_MASK) >> QEIV2_TRGOEN_HOME2FEN_SHIFT) + +/* + * FAULTFEN (RW) + * + */ +#define QEIV2_TRGOEN_FAULTFEN_MASK (0x40000UL) +#define QEIV2_TRGOEN_FAULTFEN_SHIFT (18U) +#define QEIV2_TRGOEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_FAULTFEN_SHIFT) & QEIV2_TRGOEN_FAULTFEN_MASK) +#define QEIV2_TRGOEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_FAULTFEN_MASK) >> QEIV2_TRGOEN_FAULTFEN_SHIFT) + +/* Bitfield definition for register: READEN */ +/* + * WDGFEN (RW) + * + * 1- load counters to their read registers when wdg flag set + */ +#define QEIV2_READEN_WDGFEN_MASK (0x80000000UL) +#define QEIV2_READEN_WDGFEN_SHIFT (31U) +#define QEIV2_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WDGFEN_SHIFT) & QEIV2_READEN_WDGFEN_MASK) +#define QEIV2_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WDGFEN_MASK) >> QEIV2_READEN_WDGFEN_SHIFT) + +/* + * HOMEFEN (RW) + * + * 1- load counters to their read registers when homef flag set + */ +#define QEIV2_READEN_HOMEFEN_MASK (0x40000000UL) +#define QEIV2_READEN_HOMEFEN_SHIFT (30U) +#define QEIV2_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOMEFEN_SHIFT) & QEIV2_READEN_HOMEFEN_MASK) +#define QEIV2_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOMEFEN_MASK) >> QEIV2_READEN_HOMEFEN_SHIFT) + +/* + * POSCMPFEN (RW) + * + * 1- load counters to their read registers when poscmpf flag set + */ +#define QEIV2_READEN_POSCMPFEN_MASK (0x20000000UL) +#define QEIV2_READEN_POSCMPFEN_SHIFT (29U) +#define QEIV2_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POSCMPFEN_SHIFT) & QEIV2_READEN_POSCMPFEN_MASK) +#define QEIV2_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POSCMPFEN_MASK) >> QEIV2_READEN_POSCMPFEN_SHIFT) + +/* + * ZPHFEN (RW) + * + * 1- load counters to their read registers when zphf flag set + */ +#define QEIV2_READEN_ZPHFEN_MASK (0x10000000UL) +#define QEIV2_READEN_ZPHFEN_SHIFT (28U) +#define QEIV2_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZPHFEN_SHIFT) & QEIV2_READEN_ZPHFEN_MASK) +#define QEIV2_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZPHFEN_MASK) >> QEIV2_READEN_ZPHFEN_SHIFT) + +/* + * ZMISSFEN (RW) + * + */ +#define QEIV2_READEN_ZMISSFEN_MASK (0x8000000UL) +#define QEIV2_READEN_ZMISSFEN_SHIFT (27U) +#define QEIV2_READEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZMISSFEN_SHIFT) & QEIV2_READEN_ZMISSFEN_MASK) +#define QEIV2_READEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZMISSFEN_MASK) >> QEIV2_READEN_ZMISSFEN_SHIFT) + +/* + * WIDTHTMFEN (RW) + * + */ +#define QEIV2_READEN_WIDTHTMFEN_MASK (0x4000000UL) +#define QEIV2_READEN_WIDTHTMFEN_SHIFT (26U) +#define QEIV2_READEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WIDTHTMFEN_SHIFT) & QEIV2_READEN_WIDTHTMFEN_MASK) +#define QEIV2_READEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WIDTHTMFEN_MASK) >> QEIV2_READEN_WIDTHTMFEN_SHIFT) + +/* + * POS2CMPFEN (RW) + * + */ +#define QEIV2_READEN_POS2CMPFEN_MASK (0x2000000UL) +#define QEIV2_READEN_POS2CMPFEN_SHIFT (25U) +#define QEIV2_READEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POS2CMPFEN_SHIFT) & QEIV2_READEN_POS2CMPFEN_MASK) +#define QEIV2_READEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POS2CMPFEN_MASK) >> QEIV2_READEN_POS2CMPFEN_SHIFT) + +/* + * DIRCHGFEN (RW) + * + */ +#define QEIV2_READEN_DIRCHGFEN_MASK (0x1000000UL) +#define QEIV2_READEN_DIRCHGFEN_SHIFT (24U) +#define QEIV2_READEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_DIRCHGFEN_SHIFT) & QEIV2_READEN_DIRCHGFEN_MASK) +#define QEIV2_READEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_DIRCHGFEN_MASK) >> QEIV2_READEN_DIRCHGFEN_SHIFT) + +/* + * CYCLE0FEN (RW) + * + */ +#define QEIV2_READEN_CYCLE0FEN_MASK (0x800000UL) +#define QEIV2_READEN_CYCLE0FEN_SHIFT (23U) +#define QEIV2_READEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE0FEN_SHIFT) & QEIV2_READEN_CYCLE0FEN_MASK) +#define QEIV2_READEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE0FEN_MASK) >> QEIV2_READEN_CYCLE0FEN_SHIFT) + +/* + * CYCLE1FEN (RW) + * + */ +#define QEIV2_READEN_CYCLE1FEN_MASK (0x400000UL) +#define QEIV2_READEN_CYCLE1FEN_SHIFT (22U) +#define QEIV2_READEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE1FEN_SHIFT) & QEIV2_READEN_CYCLE1FEN_MASK) +#define QEIV2_READEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE1FEN_MASK) >> QEIV2_READEN_CYCLE1FEN_SHIFT) + +/* + * PULSE0FEN (RW) + * + */ +#define QEIV2_READEN_PULSE0FEN_MASK (0x200000UL) +#define QEIV2_READEN_PULSE0FEN_SHIFT (21U) +#define QEIV2_READEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE0FEN_SHIFT) & QEIV2_READEN_PULSE0FEN_MASK) +#define QEIV2_READEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE0FEN_MASK) >> QEIV2_READEN_PULSE0FEN_SHIFT) + +/* + * PULSE1FEN (RW) + * + */ +#define QEIV2_READEN_PULSE1FEN_MASK (0x100000UL) +#define QEIV2_READEN_PULSE1FEN_SHIFT (20U) +#define QEIV2_READEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE1FEN_SHIFT) & QEIV2_READEN_PULSE1FEN_MASK) +#define QEIV2_READEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE1FEN_MASK) >> QEIV2_READEN_PULSE1FEN_SHIFT) + +/* + * HOME2FEN (RW) + * + */ +#define QEIV2_READEN_HOME2FEN_MASK (0x80000UL) +#define QEIV2_READEN_HOME2FEN_SHIFT (19U) +#define QEIV2_READEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOME2FEN_SHIFT) & QEIV2_READEN_HOME2FEN_MASK) +#define QEIV2_READEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOME2FEN_MASK) >> QEIV2_READEN_HOME2FEN_SHIFT) + +/* + * FAULTFEN (RW) + * + */ +#define QEIV2_READEN_FAULTFEN_MASK (0x40000UL) +#define QEIV2_READEN_FAULTFEN_SHIFT (18U) +#define QEIV2_READEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_FAULTFEN_SHIFT) & QEIV2_READEN_FAULTFEN_MASK) +#define QEIV2_READEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_FAULTFEN_MASK) >> QEIV2_READEN_FAULTFEN_SHIFT) + +/* Bitfield definition for register: ZCMP */ +/* + * ZCMP (RW) + * + * zcnt postion compare value + */ +#define QEIV2_ZCMP_ZCMP_MASK (0xFFFFFFFFUL) +#define QEIV2_ZCMP_ZCMP_SHIFT (0U) +#define QEIV2_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEIV2_ZCMP_ZCMP_SHIFT) & QEIV2_ZCMP_ZCMP_MASK) +#define QEIV2_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEIV2_ZCMP_ZCMP_MASK) >> QEIV2_ZCMP_ZCMP_SHIFT) + +/* Bitfield definition for register: PHCMP */ +/* + * PHCMP (RW) + * + * phcnt position compare value + */ +#define QEIV2_PHCMP_PHCMP_MASK (0xFFFFFFFFUL) +#define QEIV2_PHCMP_PHCMP_SHIFT (0U) +#define QEIV2_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEIV2_PHCMP_PHCMP_SHIFT) & QEIV2_PHCMP_PHCMP_MASK) +#define QEIV2_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEIV2_PHCMP_PHCMP_MASK) >> QEIV2_PHCMP_PHCMP_SHIFT) + +/* Bitfield definition for register: SPDCMP */ +/* + * SPDCMP (RW) + * + * spdcnt position compare value + */ +#define QEIV2_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL) +#define QEIV2_SPDCMP_SPDCMP_SHIFT (0U) +#define QEIV2_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP_SPDCMP_SHIFT) & QEIV2_SPDCMP_SPDCMP_MASK) +#define QEIV2_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP_SPDCMP_MASK) >> QEIV2_SPDCMP_SPDCMP_SHIFT) + +/* Bitfield definition for register: DMAEN */ +/* + * WDGFEN (RW) + * + * 1- generate dma request when wdg flag set + */ +#define QEIV2_DMAEN_WDGFEN_MASK (0x80000000UL) +#define QEIV2_DMAEN_WDGFEN_SHIFT (31U) +#define QEIV2_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WDGFEN_SHIFT) & QEIV2_DMAEN_WDGFEN_MASK) +#define QEIV2_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WDGFEN_MASK) >> QEIV2_DMAEN_WDGFEN_SHIFT) + +/* + * HOMEFEN (RW) + * + * 1- generate dma request when homef flag set + */ +#define QEIV2_DMAEN_HOMEFEN_MASK (0x40000000UL) +#define QEIV2_DMAEN_HOMEFEN_SHIFT (30U) +#define QEIV2_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOMEFEN_SHIFT) & QEIV2_DMAEN_HOMEFEN_MASK) +#define QEIV2_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOMEFEN_MASK) >> QEIV2_DMAEN_HOMEFEN_SHIFT) + +/* + * POSCMPFEN (RW) + * + * 1- generate dma request when poscmpf flag set + */ +#define QEIV2_DMAEN_POSCMPFEN_MASK (0x20000000UL) +#define QEIV2_DMAEN_POSCMPFEN_SHIFT (29U) +#define QEIV2_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POSCMPFEN_SHIFT) & QEIV2_DMAEN_POSCMPFEN_MASK) +#define QEIV2_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POSCMPFEN_MASK) >> QEIV2_DMAEN_POSCMPFEN_SHIFT) + +/* + * ZPHFEN (RW) + * + * 1- generate dma request when zphf flag set + */ +#define QEIV2_DMAEN_ZPHFEN_MASK (0x10000000UL) +#define QEIV2_DMAEN_ZPHFEN_SHIFT (28U) +#define QEIV2_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZPHFEN_SHIFT) & QEIV2_DMAEN_ZPHFEN_MASK) +#define QEIV2_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZPHFEN_MASK) >> QEIV2_DMAEN_ZPHFEN_SHIFT) + +/* + * ZMISSFEN (RW) + * + */ +#define QEIV2_DMAEN_ZMISSFEN_MASK (0x8000000UL) +#define QEIV2_DMAEN_ZMISSFEN_SHIFT (27U) +#define QEIV2_DMAEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZMISSFEN_SHIFT) & QEIV2_DMAEN_ZMISSFEN_MASK) +#define QEIV2_DMAEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZMISSFEN_MASK) >> QEIV2_DMAEN_ZMISSFEN_SHIFT) + +/* + * WIDTHTMFEN (RW) + * + */ +#define QEIV2_DMAEN_WIDTHTMFEN_MASK (0x4000000UL) +#define QEIV2_DMAEN_WIDTHTMFEN_SHIFT (26U) +#define QEIV2_DMAEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WIDTHTMFEN_SHIFT) & QEIV2_DMAEN_WIDTHTMFEN_MASK) +#define QEIV2_DMAEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WIDTHTMFEN_MASK) >> QEIV2_DMAEN_WIDTHTMFEN_SHIFT) + +/* + * POS2CMPFEN (RW) + * + */ +#define QEIV2_DMAEN_POS2CMPFEN_MASK (0x2000000UL) +#define QEIV2_DMAEN_POS2CMPFEN_SHIFT (25U) +#define QEIV2_DMAEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POS2CMPFEN_SHIFT) & QEIV2_DMAEN_POS2CMPFEN_MASK) +#define QEIV2_DMAEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POS2CMPFEN_MASK) >> QEIV2_DMAEN_POS2CMPFEN_SHIFT) + +/* + * DIRCHGFEN (RW) + * + */ +#define QEIV2_DMAEN_DIRCHGFEN_MASK (0x1000000UL) +#define QEIV2_DMAEN_DIRCHGFEN_SHIFT (24U) +#define QEIV2_DMAEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_DIRCHGFEN_SHIFT) & QEIV2_DMAEN_DIRCHGFEN_MASK) +#define QEIV2_DMAEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_DIRCHGFEN_MASK) >> QEIV2_DMAEN_DIRCHGFEN_SHIFT) + +/* + * CYCLE0FEN (RW) + * + */ +#define QEIV2_DMAEN_CYCLE0FEN_MASK (0x800000UL) +#define QEIV2_DMAEN_CYCLE0FEN_SHIFT (23U) +#define QEIV2_DMAEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE0FEN_SHIFT) & QEIV2_DMAEN_CYCLE0FEN_MASK) +#define QEIV2_DMAEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE0FEN_MASK) >> QEIV2_DMAEN_CYCLE0FEN_SHIFT) + +/* + * CYCLE1FEN (RW) + * + */ +#define QEIV2_DMAEN_CYCLE1FEN_MASK (0x400000UL) +#define QEIV2_DMAEN_CYCLE1FEN_SHIFT (22U) +#define QEIV2_DMAEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE1FEN_SHIFT) & QEIV2_DMAEN_CYCLE1FEN_MASK) +#define QEIV2_DMAEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE1FEN_MASK) >> QEIV2_DMAEN_CYCLE1FEN_SHIFT) + +/* + * PULSE0FEN (RW) + * + */ +#define QEIV2_DMAEN_PULSE0FEN_MASK (0x200000UL) +#define QEIV2_DMAEN_PULSE0FEN_SHIFT (21U) +#define QEIV2_DMAEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE0FEN_SHIFT) & QEIV2_DMAEN_PULSE0FEN_MASK) +#define QEIV2_DMAEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE0FEN_MASK) >> QEIV2_DMAEN_PULSE0FEN_SHIFT) + +/* + * PULSE1FEN (RW) + * + */ +#define QEIV2_DMAEN_PULSE1FEN_MASK (0x100000UL) +#define QEIV2_DMAEN_PULSE1FEN_SHIFT (20U) +#define QEIV2_DMAEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE1FEN_SHIFT) & QEIV2_DMAEN_PULSE1FEN_MASK) +#define QEIV2_DMAEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE1FEN_MASK) >> QEIV2_DMAEN_PULSE1FEN_SHIFT) + +/* + * HOME2FEN (RW) + * + */ +#define QEIV2_DMAEN_HOME2FEN_MASK (0x80000UL) +#define QEIV2_DMAEN_HOME2FEN_SHIFT (19U) +#define QEIV2_DMAEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOME2FEN_SHIFT) & QEIV2_DMAEN_HOME2FEN_MASK) +#define QEIV2_DMAEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOME2FEN_MASK) >> QEIV2_DMAEN_HOME2FEN_SHIFT) + +/* + * FAULTFEN (RW) + * + */ +#define QEIV2_DMAEN_FAULTFEN_MASK (0x40000UL) +#define QEIV2_DMAEN_FAULTFEN_SHIFT (18U) +#define QEIV2_DMAEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_FAULTFEN_SHIFT) & QEIV2_DMAEN_FAULTFEN_MASK) +#define QEIV2_DMAEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_FAULTFEN_MASK) >> QEIV2_DMAEN_FAULTFEN_SHIFT) + +/* Bitfield definition for register: SR */ +/* + * WDGF (RW) + * + * watchdog flag + */ +#define QEIV2_SR_WDGF_MASK (0x80000000UL) +#define QEIV2_SR_WDGF_SHIFT (31U) +#define QEIV2_SR_WDGF_SET(x) (((uint32_t)(x) << QEIV2_SR_WDGF_SHIFT) & QEIV2_SR_WDGF_MASK) +#define QEIV2_SR_WDGF_GET(x) (((uint32_t)(x) & QEIV2_SR_WDGF_MASK) >> QEIV2_SR_WDGF_SHIFT) + +/* + * HOMEF (RW) + * + * home flag + */ +#define QEIV2_SR_HOMEF_MASK (0x40000000UL) +#define QEIV2_SR_HOMEF_SHIFT (30U) +#define QEIV2_SR_HOMEF_SET(x) (((uint32_t)(x) << QEIV2_SR_HOMEF_SHIFT) & QEIV2_SR_HOMEF_MASK) +#define QEIV2_SR_HOMEF_GET(x) (((uint32_t)(x) & QEIV2_SR_HOMEF_MASK) >> QEIV2_SR_HOMEF_SHIFT) + +/* + * POSCMPF (RW) + * + * postion compare match flag + */ +#define QEIV2_SR_POSCMPF_MASK (0x20000000UL) +#define QEIV2_SR_POSCMPF_SHIFT (29U) +#define QEIV2_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POSCMPF_SHIFT) & QEIV2_SR_POSCMPF_MASK) +#define QEIV2_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POSCMPF_MASK) >> QEIV2_SR_POSCMPF_SHIFT) + +/* + * ZPHF (RW) + * + * z input flag + */ +#define QEIV2_SR_ZPHF_MASK (0x10000000UL) +#define QEIV2_SR_ZPHF_SHIFT (28U) +#define QEIV2_SR_ZPHF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZPHF_SHIFT) & QEIV2_SR_ZPHF_MASK) +#define QEIV2_SR_ZPHF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZPHF_MASK) >> QEIV2_SR_ZPHF_SHIFT) + +/* + * ZMISSF (RW) + * + */ +#define QEIV2_SR_ZMISSF_MASK (0x8000000UL) +#define QEIV2_SR_ZMISSF_SHIFT (27U) +#define QEIV2_SR_ZMISSF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZMISSF_SHIFT) & QEIV2_SR_ZMISSF_MASK) +#define QEIV2_SR_ZMISSF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZMISSF_MASK) >> QEIV2_SR_ZMISSF_SHIFT) + +/* + * WIDTHTMF (RW) + * + */ +#define QEIV2_SR_WIDTHTMF_MASK (0x4000000UL) +#define QEIV2_SR_WIDTHTMF_SHIFT (26U) +#define QEIV2_SR_WIDTHTMF_SET(x) (((uint32_t)(x) << QEIV2_SR_WIDTHTMF_SHIFT) & QEIV2_SR_WIDTHTMF_MASK) +#define QEIV2_SR_WIDTHTMF_GET(x) (((uint32_t)(x) & QEIV2_SR_WIDTHTMF_MASK) >> QEIV2_SR_WIDTHTMF_SHIFT) + +/* + * POS2CMPF (RW) + * + */ +#define QEIV2_SR_POS2CMPF_MASK (0x2000000UL) +#define QEIV2_SR_POS2CMPF_SHIFT (25U) +#define QEIV2_SR_POS2CMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POS2CMPF_SHIFT) & QEIV2_SR_POS2CMPF_MASK) +#define QEIV2_SR_POS2CMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POS2CMPF_MASK) >> QEIV2_SR_POS2CMPF_SHIFT) + +/* + * DIRCHGF (RW) + * + */ +#define QEIV2_SR_DIRCHGF_MASK (0x1000000UL) +#define QEIV2_SR_DIRCHGF_SHIFT (24U) +#define QEIV2_SR_DIRCHGF_SET(x) (((uint32_t)(x) << QEIV2_SR_DIRCHGF_SHIFT) & QEIV2_SR_DIRCHGF_MASK) +#define QEIV2_SR_DIRCHGF_GET(x) (((uint32_t)(x) & QEIV2_SR_DIRCHGF_MASK) >> QEIV2_SR_DIRCHGF_SHIFT) + +/* + * CYCLE0F (RW) + * + */ +#define QEIV2_SR_CYCLE0F_MASK (0x800000UL) +#define QEIV2_SR_CYCLE0F_SHIFT (23U) +#define QEIV2_SR_CYCLE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE0F_SHIFT) & QEIV2_SR_CYCLE0F_MASK) +#define QEIV2_SR_CYCLE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE0F_MASK) >> QEIV2_SR_CYCLE0F_SHIFT) + +/* + * CYCLE1F (RW) + * + */ +#define QEIV2_SR_CYCLE1F_MASK (0x400000UL) +#define QEIV2_SR_CYCLE1F_SHIFT (22U) +#define QEIV2_SR_CYCLE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE1F_SHIFT) & QEIV2_SR_CYCLE1F_MASK) +#define QEIV2_SR_CYCLE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE1F_MASK) >> QEIV2_SR_CYCLE1F_SHIFT) + +/* + * PULSE0F (RW) + * + */ +#define QEIV2_SR_PULSE0F_MASK (0x200000UL) +#define QEIV2_SR_PULSE0F_SHIFT (21U) +#define QEIV2_SR_PULSE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE0F_SHIFT) & QEIV2_SR_PULSE0F_MASK) +#define QEIV2_SR_PULSE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE0F_MASK) >> QEIV2_SR_PULSE0F_SHIFT) + +/* + * PULSE1F (RW) + * + */ +#define QEIV2_SR_PULSE1F_MASK (0x100000UL) +#define QEIV2_SR_PULSE1F_SHIFT (20U) +#define QEIV2_SR_PULSE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE1F_SHIFT) & QEIV2_SR_PULSE1F_MASK) +#define QEIV2_SR_PULSE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE1F_MASK) >> QEIV2_SR_PULSE1F_SHIFT) + +/* + * HOME2F (RW) + * + */ +#define QEIV2_SR_HOME2F_MASK (0x80000UL) +#define QEIV2_SR_HOME2F_SHIFT (19U) +#define QEIV2_SR_HOME2F_SET(x) (((uint32_t)(x) << QEIV2_SR_HOME2F_SHIFT) & QEIV2_SR_HOME2F_MASK) +#define QEIV2_SR_HOME2F_GET(x) (((uint32_t)(x) & QEIV2_SR_HOME2F_MASK) >> QEIV2_SR_HOME2F_SHIFT) + +/* + * FAULTF (RW) + * + */ +#define QEIV2_SR_FAULTF_MASK (0x40000UL) +#define QEIV2_SR_FAULTF_SHIFT (18U) +#define QEIV2_SR_FAULTF_SET(x) (((uint32_t)(x) << QEIV2_SR_FAULTF_SHIFT) & QEIV2_SR_FAULTF_MASK) +#define QEIV2_SR_FAULTF_GET(x) (((uint32_t)(x) & QEIV2_SR_FAULTF_MASK) >> QEIV2_SR_FAULTF_SHIFT) + +/* Bitfield definition for register: IRQEN */ +/* + * WDGIE (RW) + * + * 1- generate interrupt when wdg flag set + */ +#define QEIV2_IRQEN_WDGIE_MASK (0x80000000UL) +#define QEIV2_IRQEN_WDGIE_SHIFT (31U) +#define QEIV2_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WDGIE_SHIFT) & QEIV2_IRQEN_WDGIE_MASK) +#define QEIV2_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WDGIE_MASK) >> QEIV2_IRQEN_WDGIE_SHIFT) + +/* + * HOMEIE (RW) + * + * 1- generate interrupt when homef flag set + */ +#define QEIV2_IRQEN_HOMEIE_MASK (0x40000000UL) +#define QEIV2_IRQEN_HOMEIE_SHIFT (30U) +#define QEIV2_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOMEIE_SHIFT) & QEIV2_IRQEN_HOMEIE_MASK) +#define QEIV2_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOMEIE_MASK) >> QEIV2_IRQEN_HOMEIE_SHIFT) + +/* + * POSCMPIE (RW) + * + * 1- generate interrupt when poscmpf flag set + */ +#define QEIV2_IRQEN_POSCMPIE_MASK (0x20000000UL) +#define QEIV2_IRQEN_POSCMPIE_SHIFT (29U) +#define QEIV2_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POSCMPIE_SHIFT) & QEIV2_IRQEN_POSCMPIE_MASK) +#define QEIV2_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POSCMPIE_MASK) >> QEIV2_IRQEN_POSCMPIE_SHIFT) + +/* + * ZPHIE (RW) + * + * 1- generate interrupt when zphf flag set + */ +#define QEIV2_IRQEN_ZPHIE_MASK (0x10000000UL) +#define QEIV2_IRQEN_ZPHIE_SHIFT (28U) +#define QEIV2_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZPHIE_SHIFT) & QEIV2_IRQEN_ZPHIE_MASK) +#define QEIV2_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZPHIE_MASK) >> QEIV2_IRQEN_ZPHIE_SHIFT) + +/* + * ZMISSE (RW) + * + */ +#define QEIV2_IRQEN_ZMISSE_MASK (0x8000000UL) +#define QEIV2_IRQEN_ZMISSE_SHIFT (27U) +#define QEIV2_IRQEN_ZMISSE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZMISSE_SHIFT) & QEIV2_IRQEN_ZMISSE_MASK) +#define QEIV2_IRQEN_ZMISSE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZMISSE_MASK) >> QEIV2_IRQEN_ZMISSE_SHIFT) + +/* + * WIDTHTME (RW) + * + */ +#define QEIV2_IRQEN_WIDTHTME_MASK (0x4000000UL) +#define QEIV2_IRQEN_WIDTHTME_SHIFT (26U) +#define QEIV2_IRQEN_WIDTHTME_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WIDTHTME_SHIFT) & QEIV2_IRQEN_WIDTHTME_MASK) +#define QEIV2_IRQEN_WIDTHTME_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WIDTHTME_MASK) >> QEIV2_IRQEN_WIDTHTME_SHIFT) + +/* + * POS2CMPE (RW) + * + */ +#define QEIV2_IRQEN_POS2CMPE_MASK (0x2000000UL) +#define QEIV2_IRQEN_POS2CMPE_SHIFT (25U) +#define QEIV2_IRQEN_POS2CMPE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POS2CMPE_SHIFT) & QEIV2_IRQEN_POS2CMPE_MASK) +#define QEIV2_IRQEN_POS2CMPE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POS2CMPE_MASK) >> QEIV2_IRQEN_POS2CMPE_SHIFT) + +/* + * DIRCHGE (RW) + * + */ +#define QEIV2_IRQEN_DIRCHGE_MASK (0x1000000UL) +#define QEIV2_IRQEN_DIRCHGE_SHIFT (24U) +#define QEIV2_IRQEN_DIRCHGE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_DIRCHGE_SHIFT) & QEIV2_IRQEN_DIRCHGE_MASK) +#define QEIV2_IRQEN_DIRCHGE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_DIRCHGE_MASK) >> QEIV2_IRQEN_DIRCHGE_SHIFT) + +/* + * CYCLE0E (RW) + * + */ +#define QEIV2_IRQEN_CYCLE0E_MASK (0x800000UL) +#define QEIV2_IRQEN_CYCLE0E_SHIFT (23U) +#define QEIV2_IRQEN_CYCLE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE0E_SHIFT) & QEIV2_IRQEN_CYCLE0E_MASK) +#define QEIV2_IRQEN_CYCLE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE0E_MASK) >> QEIV2_IRQEN_CYCLE0E_SHIFT) + +/* + * CYCLE1E (RW) + * + */ +#define QEIV2_IRQEN_CYCLE1E_MASK (0x400000UL) +#define QEIV2_IRQEN_CYCLE1E_SHIFT (22U) +#define QEIV2_IRQEN_CYCLE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE1E_SHIFT) & QEIV2_IRQEN_CYCLE1E_MASK) +#define QEIV2_IRQEN_CYCLE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE1E_MASK) >> QEIV2_IRQEN_CYCLE1E_SHIFT) + +/* + * PULSE0E (RW) + * + */ +#define QEIV2_IRQEN_PULSE0E_MASK (0x200000UL) +#define QEIV2_IRQEN_PULSE0E_SHIFT (21U) +#define QEIV2_IRQEN_PULSE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE0E_SHIFT) & QEIV2_IRQEN_PULSE0E_MASK) +#define QEIV2_IRQEN_PULSE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE0E_MASK) >> QEIV2_IRQEN_PULSE0E_SHIFT) + +/* + * PULSE1E (RW) + * + */ +#define QEIV2_IRQEN_PULSE1E_MASK (0x100000UL) +#define QEIV2_IRQEN_PULSE1E_SHIFT (20U) +#define QEIV2_IRQEN_PULSE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE1E_SHIFT) & QEIV2_IRQEN_PULSE1E_MASK) +#define QEIV2_IRQEN_PULSE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE1E_MASK) >> QEIV2_IRQEN_PULSE1E_SHIFT) + +/* + * HOME2E (RW) + * + */ +#define QEIV2_IRQEN_HOME2E_MASK (0x80000UL) +#define QEIV2_IRQEN_HOME2E_SHIFT (19U) +#define QEIV2_IRQEN_HOME2E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOME2E_SHIFT) & QEIV2_IRQEN_HOME2E_MASK) +#define QEIV2_IRQEN_HOME2E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOME2E_MASK) >> QEIV2_IRQEN_HOME2E_SHIFT) + +/* + * FAULTE (RW) + * + */ +#define QEIV2_IRQEN_FAULTE_MASK (0x40000UL) +#define QEIV2_IRQEN_FAULTE_SHIFT (18U) +#define QEIV2_IRQEN_FAULTE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_FAULTE_SHIFT) & QEIV2_IRQEN_FAULTE_MASK) +#define QEIV2_IRQEN_FAULTE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_FAULTE_MASK) >> QEIV2_IRQEN_FAULTE_SHIFT) + +/* Bitfield definition for register of struct array COUNT: Z */ +/* + * ZCNT (RW) + * + * zcnt value + */ +#define QEIV2_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL) +#define QEIV2_COUNT_Z_ZCNT_SHIFT (0U) +#define QEIV2_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_Z_ZCNT_SHIFT) & QEIV2_COUNT_Z_ZCNT_MASK) +#define QEIV2_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_Z_ZCNT_MASK) >> QEIV2_COUNT_Z_ZCNT_SHIFT) + +/* Bitfield definition for register of struct array COUNT: PH */ +/* + * DIR (RO) + * + * 1- reverse rotation + * 0- forward rotation + */ +#define QEIV2_COUNT_PH_DIR_MASK (0x40000000UL) +#define QEIV2_COUNT_PH_DIR_SHIFT (30U) +#define QEIV2_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_DIR_MASK) >> QEIV2_COUNT_PH_DIR_SHIFT) + +/* + * ASTAT (RO) + * + * 1- a input is high + * 0- a input is low + */ +#define QEIV2_COUNT_PH_ASTAT_MASK (0x4000000UL) +#define QEIV2_COUNT_PH_ASTAT_SHIFT (26U) +#define QEIV2_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_ASTAT_MASK) >> QEIV2_COUNT_PH_ASTAT_SHIFT) + +/* + * BSTAT (RO) + * + * 1- b input is high + * 0- b input is low + */ +#define QEIV2_COUNT_PH_BSTAT_MASK (0x2000000UL) +#define QEIV2_COUNT_PH_BSTAT_SHIFT (25U) +#define QEIV2_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_BSTAT_MASK) >> QEIV2_COUNT_PH_BSTAT_SHIFT) + +/* + * PHCNT (RO) + * + * phcnt value + */ +#define QEIV2_COUNT_PH_PHCNT_MASK (0x1FFFFFUL) +#define QEIV2_COUNT_PH_PHCNT_SHIFT (0U) +#define QEIV2_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_PHCNT_MASK) >> QEIV2_COUNT_PH_PHCNT_SHIFT) + +/* Bitfield definition for register of struct array COUNT: SPD */ +/* + * DIR (RO) + * + * 1- reverse rotation + * 0- forward rotation + */ +#define QEIV2_COUNT_SPD_DIR_MASK (0x80000000UL) +#define QEIV2_COUNT_SPD_DIR_SHIFT (31U) +#define QEIV2_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_DIR_MASK) >> QEIV2_COUNT_SPD_DIR_SHIFT) + +/* + * ASTAT (RO) + * + * 1- a input is high + * 0- a input is low + */ +#define QEIV2_COUNT_SPD_ASTAT_MASK (0x40000000UL) +#define QEIV2_COUNT_SPD_ASTAT_SHIFT (30U) +#define QEIV2_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_ASTAT_MASK) >> QEIV2_COUNT_SPD_ASTAT_SHIFT) + +/* + * BSTAT (RW) + * + * 1- b input is high + * 0- b input is low + */ +#define QEIV2_COUNT_SPD_BSTAT_MASK (0x20000000UL) +#define QEIV2_COUNT_SPD_BSTAT_SHIFT (29U) +#define QEIV2_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_SPD_BSTAT_SHIFT) & QEIV2_COUNT_SPD_BSTAT_MASK) +#define QEIV2_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_BSTAT_MASK) >> QEIV2_COUNT_SPD_BSTAT_SHIFT) + +/* + * SPDCNT (RO) + * + * spdcnt value + */ +#define QEIV2_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL) +#define QEIV2_COUNT_SPD_SPDCNT_SHIFT (0U) +#define QEIV2_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_SPDCNT_MASK) >> QEIV2_COUNT_SPD_SPDCNT_SHIFT) + +/* Bitfield definition for register of struct array COUNT: TMR */ +/* + * TMRCNT (RO) + * + * 32 bit free run timer + */ +#define QEIV2_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL) +#define QEIV2_COUNT_TMR_TMRCNT_SHIFT (0U) +#define QEIV2_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_TMR_TMRCNT_MASK) >> QEIV2_COUNT_TMR_TMRCNT_SHIFT) + +/* Bitfield definition for register: ZCMP2 */ +/* + * ZCMP2 (RW) + * + */ +#define QEIV2_ZCMP2_ZCMP2_MASK (0xFFFFFFFFUL) +#define QEIV2_ZCMP2_ZCMP2_SHIFT (0U) +#define QEIV2_ZCMP2_ZCMP2_SET(x) (((uint32_t)(x) << QEIV2_ZCMP2_ZCMP2_SHIFT) & QEIV2_ZCMP2_ZCMP2_MASK) +#define QEIV2_ZCMP2_ZCMP2_GET(x) (((uint32_t)(x) & QEIV2_ZCMP2_ZCMP2_MASK) >> QEIV2_ZCMP2_ZCMP2_SHIFT) + +/* Bitfield definition for register: PHCMP2 */ +/* + * PHCMP2 (RW) + * + */ +#define QEIV2_PHCMP2_PHCMP2_MASK (0xFFFFFFFFUL) +#define QEIV2_PHCMP2_PHCMP2_SHIFT (0U) +#define QEIV2_PHCMP2_PHCMP2_SET(x) (((uint32_t)(x) << QEIV2_PHCMP2_PHCMP2_SHIFT) & QEIV2_PHCMP2_PHCMP2_MASK) +#define QEIV2_PHCMP2_PHCMP2_GET(x) (((uint32_t)(x) & QEIV2_PHCMP2_PHCMP2_MASK) >> QEIV2_PHCMP2_PHCMP2_SHIFT) + +/* Bitfield definition for register: SPDCMP2 */ +/* + * SPDCMP2 (RW) + * + */ +#define QEIV2_SPDCMP2_SPDCMP2_MASK (0xFFFFFFFFUL) +#define QEIV2_SPDCMP2_SPDCMP2_SHIFT (0U) +#define QEIV2_SPDCMP2_SPDCMP2_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP2_SPDCMP2_SHIFT) & QEIV2_SPDCMP2_SPDCMP2_MASK) +#define QEIV2_SPDCMP2_SPDCMP2_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP2_SPDCMP2_MASK) >> QEIV2_SPDCMP2_SPDCMP2_SHIFT) + +/* Bitfield definition for register: MATCH_CFG */ +/* + * ZCMPDIS (RW) + * + * 1- postion compare not include zcnt + */ +#define QEIV2_MATCH_CFG_ZCMPDIS_MASK (0x80000000UL) +#define QEIV2_MATCH_CFG_ZCMPDIS_SHIFT (31U) +#define QEIV2_MATCH_CFG_ZCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) +#define QEIV2_MATCH_CFG_ZCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) >> QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) + +/* + * DIRCMPDIS (RW) + * + * 1- postion compare not include rotation direction + */ +#define QEIV2_MATCH_CFG_DIRCMPDIS_MASK (0x40000000UL) +#define QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT (30U) +#define QEIV2_MATCH_CFG_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) +#define QEIV2_MATCH_CFG_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) >> QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) + +/* + * DIRCMP (RW) + * + * 0- position compare need positive rotation + * 1- position compare need negative rotation + */ +#define QEIV2_MATCH_CFG_DIRCMP_MASK (0x20000000UL) +#define QEIV2_MATCH_CFG_DIRCMP_SHIFT (29U) +#define QEIV2_MATCH_CFG_DIRCMP_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP_SHIFT) & QEIV2_MATCH_CFG_DIRCMP_MASK) +#define QEIV2_MATCH_CFG_DIRCMP_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP_MASK) >> QEIV2_MATCH_CFG_DIRCMP_SHIFT) + +/* + * SPDCMPDIS (RW) + * + */ +#define QEIV2_MATCH_CFG_SPDCMPDIS_MASK (0x10000000UL) +#define QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT (28U) +#define QEIV2_MATCH_CFG_SPDCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) +#define QEIV2_MATCH_CFG_SPDCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) >> QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) + +/* + * PHASE_MATCH_DIS (RW) + * + */ +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK (0x8000000UL) +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT (27U) +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) + +/* + * POS_MATCH_DIR (RW) + * + */ +#define QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK (0x4000000UL) +#define QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT (26U) +#define QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) +#define QEIV2_MATCH_CFG_POS_MATCH_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) + +/* + * POS_MATCH_OPT (RW) + * + */ +#define QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK (0x2000000UL) +#define QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT (25U) +#define QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) +#define QEIV2_MATCH_CFG_POS_MATCH_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) + +/* + * ZCMP2DIS (RW) + * + */ +#define QEIV2_MATCH_CFG_ZCMP2DIS_MASK (0x8000U) +#define QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT (15U) +#define QEIV2_MATCH_CFG_ZCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) +#define QEIV2_MATCH_CFG_ZCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) >> QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) + +/* + * DIRCMP2DIS (RW) + * + */ +#define QEIV2_MATCH_CFG_DIRCMP2DIS_MASK (0x4000U) +#define QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT (14U) +#define QEIV2_MATCH_CFG_DIRCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) +#define QEIV2_MATCH_CFG_DIRCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) >> QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) + +/* + * DIRCMP2 (RW) + * + */ +#define QEIV2_MATCH_CFG_DIRCMP2_MASK (0x2000U) +#define QEIV2_MATCH_CFG_DIRCMP2_SHIFT (13U) +#define QEIV2_MATCH_CFG_DIRCMP2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2_MASK) +#define QEIV2_MATCH_CFG_DIRCMP2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2_MASK) >> QEIV2_MATCH_CFG_DIRCMP2_SHIFT) + +/* + * SPDCMP2DIS (RW) + * + */ +#define QEIV2_MATCH_CFG_SPDCMP2DIS_MASK (0x1000U) +#define QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT (12U) +#define QEIV2_MATCH_CFG_SPDCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) +#define QEIV2_MATCH_CFG_SPDCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) >> QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) + +/* + * PHASE_MATCH_DIS2 (RW) + * + */ +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK (0x800U) +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT (11U) +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) +#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) + +/* + * POS_MATCH2_DIR (RW) + * + */ +#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK (0x400U) +#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT (10U) +#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) +#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) + +/* + * POS_MATCH2_OPT (RW) + * + */ +#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK (0x200U) +#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT (9U) +#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) +#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) + +/* Bitfield definition for register array: FILT_CFG */ +/* + * OUTINV (RW) + * + * 1- Filter will invert the output + * 0- Filter will not invert the output + */ +#define QEIV2_FILT_CFG_OUTINV_MASK (0x10000UL) +#define QEIV2_FILT_CFG_OUTINV_SHIFT (16U) +#define QEIV2_FILT_CFG_OUTINV_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_OUTINV_SHIFT) & QEIV2_FILT_CFG_OUTINV_MASK) +#define QEIV2_FILT_CFG_OUTINV_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_OUTINV_MASK) >> QEIV2_FILT_CFG_OUTINV_SHIFT) + +/* + * MODE (RW) + * + * This bitfields defines the filter mode + * 000-bypass; + * 100-rapid change mode; + * 101-delay filter mode; + * 110-stable low mode; + * 111-stable high mode + */ +#define QEIV2_FILT_CFG_MODE_MASK (0xE000U) +#define QEIV2_FILT_CFG_MODE_SHIFT (13U) +#define QEIV2_FILT_CFG_MODE_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_MODE_SHIFT) & QEIV2_FILT_CFG_MODE_MASK) +#define QEIV2_FILT_CFG_MODE_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_MODE_MASK) >> QEIV2_FILT_CFG_MODE_SHIFT) + +/* + * SYNCEN (RW) + * + * set to enable sychronization input signal with TRGM clock + */ +#define QEIV2_FILT_CFG_SYNCEN_MASK (0x1000U) +#define QEIV2_FILT_CFG_SYNCEN_SHIFT (12U) +#define QEIV2_FILT_CFG_SYNCEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_SYNCEN_SHIFT) & QEIV2_FILT_CFG_SYNCEN_MASK) +#define QEIV2_FILT_CFG_SYNCEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_SYNCEN_MASK) >> QEIV2_FILT_CFG_SYNCEN_SHIFT) + +/* + * FILTLEN (RW) + * + * This bitfields defines the filter counter length. + */ +#define QEIV2_FILT_CFG_FILTLEN_MASK (0xFFFU) +#define QEIV2_FILT_CFG_FILTLEN_SHIFT (0U) +#define QEIV2_FILT_CFG_FILTLEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_FILTLEN_SHIFT) & QEIV2_FILT_CFG_FILTLEN_MASK) +#define QEIV2_FILT_CFG_FILTLEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_FILTLEN_MASK) >> QEIV2_FILT_CFG_FILTLEN_SHIFT) + +/* Bitfield definition for register: QEI_CFG */ +/* + * SPEED_DIR_CHG_EN (RW) + * + * clear counter if detect direction change + */ +#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK (0x1000U) +#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT (12U) +#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) +#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) >> QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) + +/* + * UVW_POS_OPT0 (RW) + * + * set to output next area position for QEO use; + * clr to output exact point position for MMC use + */ +#define QEIV2_QEI_CFG_UVW_POS_OPT0_MASK (0x20U) +#define QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT (5U) +#define QEIV2_QEI_CFG_UVW_POS_OPT0_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) +#define QEIV2_QEI_CFG_UVW_POS_OPT0_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) >> QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) + +/* + * NEGEDGE_EN (RW) + * + * bit4: negedge enable + * bit3: posedge enable + * bit2: W in hal enable + * bit1: signal b(or V in hal) enable + * bit0: signal a(or U in hal) enable + * such as: + * 01001: use posedge A + * 11010: use both edge of signal B + * 11111: use both edge of all HAL siganls + */ +#define QEIV2_QEI_CFG_NEGEDGE_EN_MASK (0x10U) +#define QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT (4U) +#define QEIV2_QEI_CFG_NEGEDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) +#define QEIV2_QEI_CFG_NEGEDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) >> QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) + +/* + * POSIDGE_EN (RW) + * + */ +#define QEIV2_QEI_CFG_POSIDGE_EN_MASK (0x8U) +#define QEIV2_QEI_CFG_POSIDGE_EN_SHIFT (3U) +#define QEIV2_QEI_CFG_POSIDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) +#define QEIV2_QEI_CFG_POSIDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) >> QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) + +/* + * SIGZ_EN (RW) + * + */ +#define QEIV2_QEI_CFG_SIGZ_EN_MASK (0x4U) +#define QEIV2_QEI_CFG_SIGZ_EN_SHIFT (2U) +#define QEIV2_QEI_CFG_SIGZ_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGZ_EN_SHIFT) & QEIV2_QEI_CFG_SIGZ_EN_MASK) +#define QEIV2_QEI_CFG_SIGZ_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGZ_EN_MASK) >> QEIV2_QEI_CFG_SIGZ_EN_SHIFT) + +/* + * SIGB_EN (RW) + * + */ +#define QEIV2_QEI_CFG_SIGB_EN_MASK (0x2U) +#define QEIV2_QEI_CFG_SIGB_EN_SHIFT (1U) +#define QEIV2_QEI_CFG_SIGB_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGB_EN_SHIFT) & QEIV2_QEI_CFG_SIGB_EN_MASK) +#define QEIV2_QEI_CFG_SIGB_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGB_EN_MASK) >> QEIV2_QEI_CFG_SIGB_EN_SHIFT) + +/* + * SIGA_EN (RW) + * + */ +#define QEIV2_QEI_CFG_SIGA_EN_MASK (0x1U) +#define QEIV2_QEI_CFG_SIGA_EN_SHIFT (0U) +#define QEIV2_QEI_CFG_SIGA_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGA_EN_SHIFT) & QEIV2_QEI_CFG_SIGA_EN_MASK) +#define QEIV2_QEI_CFG_SIGA_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGA_EN_MASK) >> QEIV2_QEI_CFG_SIGA_EN_SHIFT) + +/* Bitfield definition for register: PULSE0_NUM */ +/* + * PULSE0_NUM (RW) + * + * for speed detection, will count the cycle number for configed pulse_num + */ +#define QEIV2_PULSE0_NUM_PULSE0_NUM_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT (0U) +#define QEIV2_PULSE0_NUM_PULSE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) +#define QEIV2_PULSE0_NUM_PULSE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) >> QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) + +/* Bitfield definition for register: PULSE1_NUM */ +/* + * PULSE1_NUM (RW) + * + */ +#define QEIV2_PULSE1_NUM_PULSE1_NUM_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT (0U) +#define QEIV2_PULSE1_NUM_PULSE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) +#define QEIV2_PULSE1_NUM_PULSE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) >> QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) + +/* Bitfield definition for register: CYCLE0_CNT */ +/* + * CYCLE0_CNT (RO) + * + */ +#define QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT (0U) +#define QEIV2_CYCLE0_CNT_CYCLE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK) >> QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT) + +/* Bitfield definition for register: CYCLE0PULSE_CNT */ +/* + * CYCLE0PULSE_CNT (RO) + * + */ +#define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT (0U) +#define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK) >> QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT) + +/* Bitfield definition for register: CYCLE1_CNT */ +/* + * CYCLE1_CNT (RO) + * + */ +#define QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT (0U) +#define QEIV2_CYCLE1_CNT_CYCLE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK) >> QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT) + +/* Bitfield definition for register: CYCLE1PULSE_CNT */ +/* + * CYCLE1PULSE_CNT (RO) + * + */ +#define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT (0U) +#define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK) >> QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT) + +/* Bitfield definition for register: CYCLE0_SNAP0 */ +/* + * CYCLE0_SNAP0 (RO) + * + */ +#define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT (0U) +#define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK) >> QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT) + +/* Bitfield definition for register: CYCLE0_SNAP1 */ +/* + * CYCLE0_SNAP1 (RO) + * + */ +#define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT (0U) +#define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK) >> QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT) + +/* Bitfield definition for register: CYCLE1_SNAP0 */ +/* + * CYCLE1_SNAP0 (RO) + * + */ +#define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT (0U) +#define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK) >> QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT) + +/* Bitfield definition for register: CYCLE1_SNAP1 */ +/* + * CYCLE1_SNAP1 (RO) + * + */ +#define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT (0U) +#define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK) >> QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT) + +/* Bitfield definition for register: CYCLE0_NUM */ +/* + * CYCLE0_NUM (RW) + * + */ +#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT (0U) +#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) +#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) >> QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) + +/* Bitfield definition for register: CYCLE1_NUM */ +/* + * CYCLE1_NUM (RW) + * + */ +#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK (0xFFFFFFFFUL) +#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT (0U) +#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) +#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) >> QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) + +/* Bitfield definition for register: PULSE0_CNT */ +/* + * PULSE0_CNT (RO) + * + */ +#define QEIV2_PULSE0_CNT_PULSE0_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT (0U) +#define QEIV2_PULSE0_CNT_PULSE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_CNT_PULSE0_CNT_MASK) >> QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT) + +/* Bitfield definition for register: PULSE0CYCLE_CNT */ +/* + * PULSE0CYCLE_CNT (RO) + * + */ +#define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT (0U) +#define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK) >> QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT) + +/* Bitfield definition for register: PULSE1_CNT */ +/* + * PULSE1_CNT (RO) + * + */ +#define QEIV2_PULSE1_CNT_PULSE1_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT (0U) +#define QEIV2_PULSE1_CNT_PULSE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_CNT_PULSE1_CNT_MASK) >> QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT) + +/* Bitfield definition for register: PULSE1CYCLE_CNT */ +/* + * PULSE1CYCLE_CNT (RO) + * + */ +#define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT (0U) +#define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK) >> QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT) + +/* Bitfield definition for register: PULSE0_SNAP0 */ +/* + * PULSE0_SNAP0 (RO) + * + */ +#define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT (0U) +#define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK) >> QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT) + +/* Bitfield definition for register: PULSE0CYCLE_SNAP0 */ +/* + * PULSE0CYCLE_SNAP0 (RO) + * + */ +#define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT (0U) +#define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK) >> QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT) + +/* Bitfield definition for register: PULSE0_SNAP1 */ +/* + * PULSE0_SNAP1 (RO) + * + */ +#define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT (0U) +#define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK) >> QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT) + +/* Bitfield definition for register: PULSE0CYCLE_SNAP1 */ +/* + * PULSE0CYCLE_SNAP1 (RO) + * + */ +#define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT (0U) +#define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK) >> QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT) + +/* Bitfield definition for register: PULSE1_SNAP0 */ +/* + * PULSE1_SNAP0 (RO) + * + */ +#define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT (0U) +#define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK) >> QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT) + +/* Bitfield definition for register: PULSE1CYCLE_SNAP0 */ +/* + * PULSE1CYCLE_SNAP0 (RO) + * + */ +#define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT (0U) +#define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK) >> QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT) + +/* Bitfield definition for register: PULSE1_SNAP1 */ +/* + * PULSE1_SNAP1 (RO) + * + */ +#define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT (0U) +#define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK) >> QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT) + +/* Bitfield definition for register: PULSE1CYCLE_SNAP1 */ +/* + * PULSE1CYCLE_SNAP1 (RO) + * + */ +#define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK (0xFFFFFFFFUL) +#define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT (0U) +#define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK) >> QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT) + +/* Bitfield definition for register: ADCX_CFG0 */ +/* + * X_ADCSEL (RW) + * + */ +#define QEIV2_ADCX_CFG0_X_ADCSEL_MASK (0x100U) +#define QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT (8U) +#define QEIV2_ADCX_CFG0_X_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) +#define QEIV2_ADCX_CFG0_X_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) >> QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) + +/* + * X_ADC_ENABLE (RW) + * + */ +#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK (0x80U) +#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT (7U) +#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) +#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) >> QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) + +/* + * X_CHAN (RW) + * + */ +#define QEIV2_ADCX_CFG0_X_CHAN_MASK (0x1FU) +#define QEIV2_ADCX_CFG0_X_CHAN_SHIFT (0U) +#define QEIV2_ADCX_CFG0_X_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_CHAN_SHIFT) & QEIV2_ADCX_CFG0_X_CHAN_MASK) +#define QEIV2_ADCX_CFG0_X_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_CHAN_MASK) >> QEIV2_ADCX_CFG0_X_CHAN_SHIFT) + +/* Bitfield definition for register: ADCX_CFG1 */ +/* + * X_PARAM1 (RW) + * + */ +#define QEIV2_ADCX_CFG1_X_PARAM1_MASK (0xFFFF0000UL) +#define QEIV2_ADCX_CFG1_X_PARAM1_SHIFT (16U) +#define QEIV2_ADCX_CFG1_X_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) +#define QEIV2_ADCX_CFG1_X_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) >> QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) + +/* + * X_PARAM0 (RW) + * + */ +#define QEIV2_ADCX_CFG1_X_PARAM0_MASK (0xFFFFU) +#define QEIV2_ADCX_CFG1_X_PARAM0_SHIFT (0U) +#define QEIV2_ADCX_CFG1_X_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) +#define QEIV2_ADCX_CFG1_X_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) >> QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) + +/* Bitfield definition for register: ADCX_CFG2 */ +/* + * X_OFFSET (RW) + * + */ +#define QEIV2_ADCX_CFG2_X_OFFSET_MASK (0xFFFFFFFFUL) +#define QEIV2_ADCX_CFG2_X_OFFSET_SHIFT (0U) +#define QEIV2_ADCX_CFG2_X_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) +#define QEIV2_ADCX_CFG2_X_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) >> QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) + +/* Bitfield definition for register: ADCY_CFG0 */ +/* + * Y_ADCSEL (RW) + * + */ +#define QEIV2_ADCY_CFG0_Y_ADCSEL_MASK (0x100U) +#define QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT (8U) +#define QEIV2_ADCY_CFG0_Y_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) +#define QEIV2_ADCY_CFG0_Y_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) >> QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) + +/* + * Y_ADC_ENABLE (RW) + * + */ +#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK (0x80U) +#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT (7U) +#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) +#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) >> QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) + +/* + * Y_CHAN (RW) + * + */ +#define QEIV2_ADCY_CFG0_Y_CHAN_MASK (0x1FU) +#define QEIV2_ADCY_CFG0_Y_CHAN_SHIFT (0U) +#define QEIV2_ADCY_CFG0_Y_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) +#define QEIV2_ADCY_CFG0_Y_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) >> QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) + +/* Bitfield definition for register: ADCY_CFG1 */ +/* + * Y_PARAM1 (RW) + * + */ +#define QEIV2_ADCY_CFG1_Y_PARAM1_MASK (0xFFFF0000UL) +#define QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT (16U) +#define QEIV2_ADCY_CFG1_Y_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) +#define QEIV2_ADCY_CFG1_Y_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) + +/* + * Y_PARAM0 (RW) + * + */ +#define QEIV2_ADCY_CFG1_Y_PARAM0_MASK (0xFFFFU) +#define QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT (0U) +#define QEIV2_ADCY_CFG1_Y_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) +#define QEIV2_ADCY_CFG1_Y_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) + +/* Bitfield definition for register: ADCY_CFG2 */ +/* + * Y_OFFSET (RW) + * + */ +#define QEIV2_ADCY_CFG2_Y_OFFSET_MASK (0xFFFFFFFFUL) +#define QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT (0U) +#define QEIV2_ADCY_CFG2_Y_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) +#define QEIV2_ADCY_CFG2_Y_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) >> QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) + +/* Bitfield definition for register: CAL_CFG */ +/* + * XY_DELAY (RW) + * + * valid x/y delay, larger than this delay will be treated as invalid data. + * Default 1.25us@200MHz; max 80ms; + */ +#define QEIV2_CAL_CFG_XY_DELAY_MASK (0xFFFFFFUL) +#define QEIV2_CAL_CFG_XY_DELAY_SHIFT (0U) +#define QEIV2_CAL_CFG_XY_DELAY_SET(x) (((uint32_t)(x) << QEIV2_CAL_CFG_XY_DELAY_SHIFT) & QEIV2_CAL_CFG_XY_DELAY_MASK) +#define QEIV2_CAL_CFG_XY_DELAY_GET(x) (((uint32_t)(x) & QEIV2_CAL_CFG_XY_DELAY_MASK) >> QEIV2_CAL_CFG_XY_DELAY_SHIFT) + +/* Bitfield definition for register: PHASE_PARAM */ +/* + * PHASE_PARAM (RW) + * + */ +#define QEIV2_PHASE_PARAM_PHASE_PARAM_MASK (0xFFFFFFFFUL) +#define QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT (0U) +#define QEIV2_PHASE_PARAM_PHASE_PARAM_SET(x) (((uint32_t)(x) << QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) +#define QEIV2_PHASE_PARAM_PHASE_PARAM_GET(x) (((uint32_t)(x) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) >> QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) + +/* Bitfield definition for register: ANGLE_ADJ */ +/* + * ANGLE_ADJ (RW) + * + */ +#define QEIV2_ANGLE_ADJ_ANGLE_ADJ_MASK (0xFFFFFFFFUL) +#define QEIV2_ANGLE_ADJ_ANGLE_ADJ_SHIFT (0U) +#define QEIV2_ANGLE_ADJ_ANGLE_ADJ_SET(x) (((uint32_t)(x) << QEIV2_ANGLE_ADJ_ANGLE_ADJ_SHIFT) & QEIV2_ANGLE_ADJ_ANGLE_ADJ_MASK) +#define QEIV2_ANGLE_ADJ_ANGLE_ADJ_GET(x) (((uint32_t)(x) & QEIV2_ANGLE_ADJ_ANGLE_ADJ_MASK) >> QEIV2_ANGLE_ADJ_ANGLE_ADJ_SHIFT) + +/* Bitfield definition for register: POS_THRESHOLD */ +/* + * POS_THRESHOLD (RW) + * + */ +#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK (0xFFFFFFFFUL) +#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT (0U) +#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(x) (((uint32_t)(x) << QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) +#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_GET(x) (((uint32_t)(x) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) >> QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) + +/* Bitfield definition for register array: UVW_POS */ +/* + * UVW_POS0 (RW) + * + */ +#define QEIV2_UVW_POS_UVW_POS0_MASK (0xFFFFFFFFUL) +#define QEIV2_UVW_POS_UVW_POS0_SHIFT (0U) +#define QEIV2_UVW_POS_UVW_POS0_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_UVW_POS0_SHIFT) & QEIV2_UVW_POS_UVW_POS0_MASK) +#define QEIV2_UVW_POS_UVW_POS0_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_UVW_POS0_MASK) >> QEIV2_UVW_POS_UVW_POS0_SHIFT) + +/* Bitfield definition for register array: UVW_POS_CFG */ +/* + * POS_EN (RW) + * + */ +#define QEIV2_UVW_POS_CFG_POS_EN_MASK (0x40U) +#define QEIV2_UVW_POS_CFG_POS_EN_SHIFT (6U) +#define QEIV2_UVW_POS_CFG_POS_EN_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_POS_EN_SHIFT) & QEIV2_UVW_POS_CFG_POS_EN_MASK) +#define QEIV2_UVW_POS_CFG_POS_EN_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_POS_EN_MASK) >> QEIV2_UVW_POS_CFG_POS_EN_SHIFT) + +/* + * U_POS_SEL (RW) + * + */ +#define QEIV2_UVW_POS_CFG_U_POS_SEL_MASK (0x30U) +#define QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT (4U) +#define QEIV2_UVW_POS_CFG_U_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) +#define QEIV2_UVW_POS_CFG_U_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) + +/* + * V_POS_SEL (RW) + * + */ +#define QEIV2_UVW_POS_CFG_V_POS_SEL_MASK (0xCU) +#define QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT (2U) +#define QEIV2_UVW_POS_CFG_V_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) +#define QEIV2_UVW_POS_CFG_V_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) + +/* + * W_POS_SEL (RW) + * + */ +#define QEIV2_UVW_POS_CFG_W_POS_SEL_MASK (0x3U) +#define QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT (0U) +#define QEIV2_UVW_POS_CFG_W_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) +#define QEIV2_UVW_POS_CFG_W_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) + +/* Bitfield definition for register: PHASE_CNT */ +/* + * PHASE_CNT (RW) + * + */ +#define QEIV2_PHASE_CNT_PHASE_CNT_MASK (0xFFFFFFFFUL) +#define QEIV2_PHASE_CNT_PHASE_CNT_SHIFT (0U) +#define QEIV2_PHASE_CNT_PHASE_CNT_SET(x) (((uint32_t)(x) << QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) +#define QEIV2_PHASE_CNT_PHASE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) >> QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) + +/* Bitfield definition for register: PHASE_UPDATE */ +/* + * INC (WO) + * + * set to add value to phase_cnt + */ +#define QEIV2_PHASE_UPDATE_INC_MASK (0x80000000UL) +#define QEIV2_PHASE_UPDATE_INC_SHIFT (31U) +#define QEIV2_PHASE_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_INC_SHIFT) & QEIV2_PHASE_UPDATE_INC_MASK) +#define QEIV2_PHASE_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_INC_MASK) >> QEIV2_PHASE_UPDATE_INC_SHIFT) + +/* + * DEC (WO) + * + * set to minus value from phase_cnt(set inc and dec same time willl act inc) + */ +#define QEIV2_PHASE_UPDATE_DEC_MASK (0x40000000UL) +#define QEIV2_PHASE_UPDATE_DEC_SHIFT (30U) +#define QEIV2_PHASE_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_DEC_SHIFT) & QEIV2_PHASE_UPDATE_DEC_MASK) +#define QEIV2_PHASE_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_DEC_MASK) >> QEIV2_PHASE_UPDATE_DEC_SHIFT) + +/* + * VALUE (WO) + * + * value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation + */ +#define QEIV2_PHASE_UPDATE_VALUE_MASK (0x3FFFFFFFUL) +#define QEIV2_PHASE_UPDATE_VALUE_SHIFT (0U) +#define QEIV2_PHASE_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_VALUE_SHIFT) & QEIV2_PHASE_UPDATE_VALUE_MASK) +#define QEIV2_PHASE_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_VALUE_MASK) >> QEIV2_PHASE_UPDATE_VALUE_SHIFT) + +/* Bitfield definition for register: POSITION */ +/* + * POSITION (RW) + * + */ +#define QEIV2_POSITION_POSITION_MASK (0xFFFFFFFFUL) +#define QEIV2_POSITION_POSITION_SHIFT (0U) +#define QEIV2_POSITION_POSITION_SET(x) (((uint32_t)(x) << QEIV2_POSITION_POSITION_SHIFT) & QEIV2_POSITION_POSITION_MASK) +#define QEIV2_POSITION_POSITION_GET(x) (((uint32_t)(x) & QEIV2_POSITION_POSITION_MASK) >> QEIV2_POSITION_POSITION_SHIFT) + +/* Bitfield definition for register: POSITION_UPDATE */ +/* + * INC (WO) + * + * set to add value to position + */ +#define QEIV2_POSITION_UPDATE_INC_MASK (0x80000000UL) +#define QEIV2_POSITION_UPDATE_INC_SHIFT (31U) +#define QEIV2_POSITION_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_INC_SHIFT) & QEIV2_POSITION_UPDATE_INC_MASK) +#define QEIV2_POSITION_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_INC_MASK) >> QEIV2_POSITION_UPDATE_INC_SHIFT) + +/* + * DEC (WO) + * + * set to minus value from position(set inc and dec same time willl act inc) + */ +#define QEIV2_POSITION_UPDATE_DEC_MASK (0x40000000UL) +#define QEIV2_POSITION_UPDATE_DEC_SHIFT (30U) +#define QEIV2_POSITION_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_DEC_SHIFT) & QEIV2_POSITION_UPDATE_DEC_MASK) +#define QEIV2_POSITION_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_DEC_MASK) >> QEIV2_POSITION_UPDATE_DEC_SHIFT) + +/* + * VALUE (WO) + * + * value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation + */ +#define QEIV2_POSITION_UPDATE_VALUE_MASK (0x3FFFFFFFUL) +#define QEIV2_POSITION_UPDATE_VALUE_SHIFT (0U) +#define QEIV2_POSITION_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_VALUE_SHIFT) & QEIV2_POSITION_UPDATE_VALUE_MASK) +#define QEIV2_POSITION_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_VALUE_MASK) >> QEIV2_POSITION_UPDATE_VALUE_SHIFT) + +/* Bitfield definition for register: ANGLE */ +/* + * ANGLE (RO) + * + */ +#define QEIV2_ANGLE_ANGLE_MASK (0xFFFFFFFFUL) +#define QEIV2_ANGLE_ANGLE_SHIFT (0U) +#define QEIV2_ANGLE_ANGLE_GET(x) (((uint32_t)(x) & QEIV2_ANGLE_ANGLE_MASK) >> QEIV2_ANGLE_ANGLE_SHIFT) + +/* Bitfield definition for register: POS_TIMEOUT */ +/* + * ENABLE (RW) + * + * enable position timeout feature, if timeout, send valid again + */ +#define QEIV2_POS_TIMEOUT_ENABLE_MASK (0x80000000UL) +#define QEIV2_POS_TIMEOUT_ENABLE_SHIFT (31U) +#define QEIV2_POS_TIMEOUT_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_ENABLE_SHIFT) & QEIV2_POS_TIMEOUT_ENABLE_MASK) +#define QEIV2_POS_TIMEOUT_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_ENABLE_MASK) >> QEIV2_POS_TIMEOUT_ENABLE_SHIFT) + +/* + * TIMEOUT (RW) + * + * postion timeout value + */ +#define QEIV2_POS_TIMEOUT_TIMEOUT_MASK (0x7FFFFFFFUL) +#define QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT (0U) +#define QEIV2_POS_TIMEOUT_TIMEOUT_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) +#define QEIV2_POS_TIMEOUT_TIMEOUT_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) >> QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) + + + +/* COUNT register group index macro definition */ +#define QEIV2_COUNT_CURRENT (0UL) +#define QEIV2_COUNT_READ (1UL) +#define QEIV2_COUNT_SNAP0 (2UL) +#define QEIV2_COUNT_SNAP1 (3UL) + +/* FILT_CFG register group index macro definition */ +#define QEIV2_FILT_CFG_FILT_CFG_A (0UL) +#define QEIV2_FILT_CFG_FILT_CFG_B (1UL) +#define QEIV2_FILT_CFG_FILT_CFG_Z (2UL) +#define QEIV2_FILT_CFG_FILT_CFG_H (3UL) +#define QEIV2_FILT_CFG_FILT_CFG_H2 (4UL) +#define QEIV2_FILT_CFG_FILT_CFG_F (5UL) + +/* UVW_POS register group index macro definition */ +#define QEIV2_UVW_POS_UVW_POS0 (0UL) +#define QEIV2_UVW_POS_UVW_POS1 (1UL) +#define QEIV2_UVW_POS_UVW_POS2 (2UL) +#define QEIV2_UVW_POS_UVW_POS3 (3UL) +#define QEIV2_UVW_POS_UVW_POS4 (4UL) +#define QEIV2_UVW_POS_UVW_POS5 (5UL) + +/* UVW_POS_CFG register group index macro definition */ +#define QEIV2_UVW_POS_CFG_UVW_POS0_CFG (0UL) +#define QEIV2_UVW_POS_CFG_UVW_POS1_CFG (1UL) +#define QEIV2_UVW_POS_CFG_UVW_POS2_CFG (2UL) +#define QEIV2_UVW_POS_CFG_UVW_POS3_CFG (3UL) +#define QEIV2_UVW_POS_CFG_UVW_POS4_CFG (4UL) +#define QEIV2_UVW_POS_CFG_UVW_POS5_CFG (5UL) + + +#endif /* HPM_QEIV2_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_qeo_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_qeo_regs.h new file mode 100644 index 00000000..e2034885 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_qeo_regs.h @@ -0,0 +1,1065 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_QEO_H +#define HPM_QEO_H + +typedef struct { + struct { + __RW uint32_t MODE; /* 0x0: analog waves mode */ + __RW uint32_t RESOLUTION; /* 0x4: resolution of wave0/1/2 */ + __RW uint32_t PHASE_SHIFT[3]; /* 0x8 - 0x10: wave0 phase shifter */ + __RW uint32_t VD_VQ_INJECT[3]; /* 0x14 - 0x1C: wave0 vd vq inject value */ + __W uint32_t VD_VQ_LOAD; /* 0x20: load wave0/1/2 vd vq value */ + __RW uint32_t AMPLITUDE[3]; /* 0x24 - 0x2C: wave0 amplitude */ + __RW uint32_t MID_POINT[3]; /* 0x30 - 0x38: wave0 output middle point offset */ + struct { + __RW uint32_t MIN; /* 0x3C: wave0 low area limit value */ + __RW uint32_t MAX; /* 0x40: wave0 high area limit value */ + } LIMIT[3]; + __RW uint32_t DEADZONE_SHIFT[3]; /* 0x54 - 0x5C: deadzone_shifter_wave0 */ + } WAVE; + struct { + __RW uint32_t MODE; /* 0x60: wave_a/b/z output mode */ + __RW uint32_t RESOLUTION; /* 0x64: resolution of wave_a/b/z */ + __RW uint32_t PHASE_SHIFT[3]; /* 0x68 - 0x70: wave_a phase shifter */ + __RW uint32_t LINE_WIDTH; /* 0x74: Two-phase orthogonality wave 1/4 period */ + __RW uint32_t WDOG_WIDTH; /* 0x78: wdog width of qeo */ + __W uint32_t POSTION_SYNC; /* 0x7C: sync abz owned postion */ + } ABZ; + struct { + __RW uint32_t MODE; /* 0x80: pwm mode */ + __RW uint32_t RESOLUTION; /* 0x84: resolution of pwm */ + __RW uint32_t PHASE_SHIFT[4]; /* 0x88 - 0x94: pwm_a phase shifter */ + __RW uint32_t PHASE_TABLE[24]; /* 0x98 - 0xF4: pwm_phase_table 0 */ + } PWM; + __RW uint32_t POSTION_SOFTWARE; /* 0xF8: softwave inject postion */ + __RW uint32_t POSTION_SEL; /* 0xFC: select softwave inject postion */ + __R uint32_t STATUS; /* 0x100: qeo status */ + __R uint32_t DEBUG0; /* 0x104: qeo debug 0 */ + __R uint32_t DEBUG1; /* 0x108: qeo debug 1 */ + __R uint32_t DEBUG2; /* 0x10C: qeo debug 2 */ + __R uint32_t DEBUG3; /* 0x110: qeo debug 3 */ +} QEO_Type; + + +/* Bitfield definition for register of struct WAVE: MODE */ +/* + * WAVE2_ABOVE_MAX_LIMIT (RW) + * + * wave2 above max limit mode. + * 0: output 0xffff. + * 1: output 0x0. + * 2: output as level_max_limit2.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK (0xC0000000UL) +#define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT (30U) +#define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) + +/* + * WAVE2_HIGH_AREA1_LIMIT (RW) + * + * wave2 high area1 limit mode. + * 0: output 0xffff. + * 1: output as level_max_limit2.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK (0x20000000UL) +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT (29U) +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) + +/* + * WAVE2_HIGH_AREA0_LIMIT (RW) + * + * wave2 high area0 limit mode. + * 0: output 0xffff. + * 1: output as level_max_limit2.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK (0x10000000UL) +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT (28U) +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) + +/* + * WAVE2_LOW_AREA1_LIMIT (RW) + * + * wave2 low area1 limit mode. + * 0: output 0. + * 1: output as level_min_limit2.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK (0x8000000UL) +#define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT (27U) +#define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) + +/* + * WAVE2_LOW_AREA0_LIMIT (RW) + * + * wave2 low area0 limit mode. + * 0: output 0. + * 1: output as level_min_limit2.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK (0x4000000UL) +#define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT (26U) +#define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) + +/* + * WAVE2_BELOW_MIN_LIMIT (RW) + * + * wave2 below min limit mode. + * 0: output 0. + * 1: output 0xffff. + * 2: output as level_min_limit2.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK (0x3000000UL) +#define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT (24U) +#define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) + +/* + * WAVE1_ABOVE_MAX_LIMIT (RW) + * + * wave1 above max limit mode. + * 0: output 0xffff. + * 1: output 0x0. + * 2: output as level_max_limit1.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK (0xC00000UL) +#define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT (22U) +#define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) + +/* + * WAVE1_HIGH_AREA1_LIMIT (RW) + * + * wave1 high area1 limit mode. + * 0: output 0xffff. + * 1: output as level_max_limit1.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK (0x200000UL) +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT (21U) +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) + +/* + * WAVE1_HIGH_AREA0_LIMIT (RW) + * + * wave1 high area0 limit mode. + * 0: output 0xffff. + * 1: output as level_max_limit1.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK (0x100000UL) +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT (20U) +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) + +/* + * WAVE1_LOW_AREA1_LIMIT (RW) + * + * wave1 low area1 limit mode. + * 0: output 0. + * 1: output as level_min_limit1.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK (0x80000UL) +#define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT (19U) +#define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) + +/* + * WAVE1_LOW_AREA0_LIMIT (RW) + * + * wave1 low area0 limit mode. + * 0: output 0. + * 1: output as level_min_limit1.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK (0x40000UL) +#define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT (18U) +#define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) + +/* + * WAVE1_BELOW_MIN_LIMIT (RW) + * + * wave1 below min limit mode. + * 0: output 0. + * 1: output 0xffff. + * 2: output as level_min_limit1.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK (0x30000UL) +#define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT (16U) +#define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) + +/* + * WAVE0_ABOVE_MAX_LIMIT (RW) + * + * wave0 above max limit mode. + * 0: output 0xffff. + * 1: output 0x0. + * 2: output as level_max_limit0.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK (0xC000U) +#define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT (14U) +#define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) + +/* + * WAVE0_HIGH_AREA1_LIMIT (RW) + * + * wave0 high area1 limit mode. + * 0: output 0xffff. + * 1: output as level_max_limit0.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK (0x2000U) +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT (13U) +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) + +/* + * WAVE0_HIGH_AREA0_LIMIT (RW) + * + * wave0 high area0 limit mode. + * 0: output 0xffff. + * 1: output as level_max_limit0.level0_max_limit + */ +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK (0x1000U) +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT (12U) +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) + +/* + * WAVE0_LOW_AREA1_LIMIT (RW) + * + * wave0 low area1 limit mode. + * 0: output 0. + * 1: output as level_min_limit0.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK (0x800U) +#define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT (11U) +#define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) + +/* + * WAVE0_LOW_AREA0_LIMIT (RW) + * + * wave0 low area0 limit mode. + * 0: output 0. + * 1: output as level_min_limit0.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK (0x400U) +#define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT (10U) +#define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) + +/* + * WAVE0_BELOW_MIN_LIMIT (RW) + * + * wave0 below min limit mode. + * 0: output 0. + * 1: output 0xffff. + * 2: output as level_min_limit0.level1_min_limit + */ +#define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK (0x300U) +#define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT (8U) +#define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) +#define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) + +/* + * SADDLE_TYPE (RW) + * + * saddle type seclect; + * 0:standard saddle. + * 1: triple-cos saddle. + */ +#define QEO_WAVE_MODE_SADDLE_TYPE_MASK (0x80U) +#define QEO_WAVE_MODE_SADDLE_TYPE_SHIFT (7U) +#define QEO_WAVE_MODE_SADDLE_TYPE_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_SADDLE_TYPE_SHIFT) & QEO_WAVE_MODE_SADDLE_TYPE_MASK) +#define QEO_WAVE_MODE_SADDLE_TYPE_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_SADDLE_TYPE_MASK) >> QEO_WAVE_MODE_SADDLE_TYPE_SHIFT) + +/* + * EN_WAVE2_VD_VQ_INJECT (RW) + * + * wave2 VdVq inject enable. + * 0: disable VdVq inject. + * 1: enable VdVq inject. + */ +#define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK (0x40U) +#define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT (6U) +#define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK) +#define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT) + +/* + * EN_WAVE1_VD_VQ_INJECT (RW) + * + * wave1 VdVq inject enable. + * 0: disable VdVq inject. + * 1: enable VdVq inject. + */ +#define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK (0x20U) +#define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT (5U) +#define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK) +#define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT) + +/* + * EN_WAVE0_VD_VQ_INJECT (RW) + * + * wave0 VdVq inject enable. + * 0: disable VdVq inject. + * 1: enable VdVq inject. + */ +#define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK (0x10U) +#define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT (4U) +#define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK) +#define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT) + +/* + * WAVES_OUTPUT_TYPE (RW) + * + * wave0/1/2 output mode. + * 0: cosine wave. + * 1: saddle wave. + * 2. abs cosine wave. + * 3. saw wave + */ +#define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK (0x3U) +#define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT (0U) +#define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) & QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) +#define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) >> QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) + +/* Bitfield definition for register of struct WAVE: RESOLUTION */ +/* + * LINES (RW) + * + * wave0/1/2 resolution + */ +#define QEO_WAVE_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) +#define QEO_WAVE_RESOLUTION_LINES_SHIFT (0U) +#define QEO_WAVE_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEO_WAVE_RESOLUTION_LINES_SHIFT) & QEO_WAVE_RESOLUTION_LINES_MASK) +#define QEO_WAVE_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEO_WAVE_RESOLUTION_LINES_MASK) >> QEO_WAVE_RESOLUTION_LINES_SHIFT) + +/* Bitfield definition for register of struct WAVE: WAVE0 */ +/* + * VAL (RW) + * + * wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period + */ +#define QEO_WAVE_PHASE_SHIFT_VAL_MASK (0xFFFFU) +#define QEO_WAVE_PHASE_SHIFT_VAL_SHIFT (0U) +#define QEO_WAVE_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_PHASE_SHIFT_VAL_SHIFT) & QEO_WAVE_PHASE_SHIFT_VAL_MASK) +#define QEO_WAVE_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_PHASE_SHIFT_VAL_MASK) >> QEO_WAVE_PHASE_SHIFT_VAL_SHIFT) + +/* Bitfield definition for register of struct WAVE: WAVE0 */ +/* + * VQ_VAL (RW) + * + * Vq inject value + */ +#define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK (0xFFFF0000UL) +#define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT (16U) +#define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT) & QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK) +#define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK) >> QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT) + +/* + * VD_VAL (RW) + * + * Vd inject value + */ +#define QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK (0xFFFFU) +#define QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT (0U) +#define QEO_WAVE_VD_VQ_INJECT_VD_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT) & QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK) +#define QEO_WAVE_VD_VQ_INJECT_VD_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK) >> QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT) + +/* Bitfield definition for register of struct WAVE: VD_VQ_LOAD */ +/* + * LOAD (WO) + * + * load wave0/1/2 vd vq value. always read 0 + * 0: vd vq keep previous value. + * 1: load wave0/1/2 vd vq value at sametime. + */ +#define QEO_WAVE_VD_VQ_LOAD_LOAD_MASK (0x1U) +#define QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT (0U) +#define QEO_WAVE_VD_VQ_LOAD_LOAD_SET(x) (((uint32_t)(x) << QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT) & QEO_WAVE_VD_VQ_LOAD_LOAD_MASK) +#define QEO_WAVE_VD_VQ_LOAD_LOAD_GET(x) (((uint32_t)(x) & QEO_WAVE_VD_VQ_LOAD_LOAD_MASK) >> QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT) + +/* Bitfield definition for register of struct WAVE: WAVE0 */ +/* + * EN_SCAL (RW) + * + * enable wave amplitude scaling. 0: disable; 1: enable + */ +#define QEO_WAVE_AMPLITUDE_EN_SCAL_MASK (0x10000UL) +#define QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT (16U) +#define QEO_WAVE_AMPLITUDE_EN_SCAL_SET(x) (((uint32_t)(x) << QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT) & QEO_WAVE_AMPLITUDE_EN_SCAL_MASK) +#define QEO_WAVE_AMPLITUDE_EN_SCAL_GET(x) (((uint32_t)(x) & QEO_WAVE_AMPLITUDE_EN_SCAL_MASK) >> QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT) + +/* + * AMP_VAL (RW) + * + * amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value. + */ +#define QEO_WAVE_AMPLITUDE_AMP_VAL_MASK (0xFFFFU) +#define QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT (0U) +#define QEO_WAVE_AMPLITUDE_AMP_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT) & QEO_WAVE_AMPLITUDE_AMP_VAL_MASK) +#define QEO_WAVE_AMPLITUDE_AMP_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_AMPLITUDE_AMP_VAL_MASK) >> QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT) + +/* Bitfield definition for register of struct WAVE: WAVE0 */ +/* + * VAL (RW) + * + * wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value. + */ +#define QEO_WAVE_MID_POINT_VAL_MASK (0xFFFFFFFFUL) +#define QEO_WAVE_MID_POINT_VAL_SHIFT (0U) +#define QEO_WAVE_MID_POINT_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_MID_POINT_VAL_SHIFT) & QEO_WAVE_MID_POINT_VAL_MASK) +#define QEO_WAVE_MID_POINT_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_MID_POINT_VAL_MASK) >> QEO_WAVE_MID_POINT_VAL_SHIFT) + +/* Bitfield definition for register of struct WAVE: MIN */ +/* + * LIMIT1 (RW) + * + * low area limit level1 + */ +#define QEO_WAVE_LIMIT_MIN_LIMIT1_MASK (0xFFFF0000UL) +#define QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT (16U) +#define QEO_WAVE_LIMIT_MIN_LIMIT1_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT) & QEO_WAVE_LIMIT_MIN_LIMIT1_MASK) +#define QEO_WAVE_LIMIT_MIN_LIMIT1_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MIN_LIMIT1_MASK) >> QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT) + +/* + * LIMIT0 (RW) + * + * low area limit level0 + */ +#define QEO_WAVE_LIMIT_MIN_LIMIT0_MASK (0xFFFFU) +#define QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT (0U) +#define QEO_WAVE_LIMIT_MIN_LIMIT0_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT) & QEO_WAVE_LIMIT_MIN_LIMIT0_MASK) +#define QEO_WAVE_LIMIT_MIN_LIMIT0_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MIN_LIMIT0_MASK) >> QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT) + +/* Bitfield definition for register of struct WAVE: MAX */ +/* + * LIMIT1 (RW) + * + * high area limit level1 + */ +#define QEO_WAVE_LIMIT_MAX_LIMIT1_MASK (0xFFFF0000UL) +#define QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT (16U) +#define QEO_WAVE_LIMIT_MAX_LIMIT1_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT) & QEO_WAVE_LIMIT_MAX_LIMIT1_MASK) +#define QEO_WAVE_LIMIT_MAX_LIMIT1_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MAX_LIMIT1_MASK) >> QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT) + +/* + * LIMIT0 (RW) + * + * high area limit level0 + */ +#define QEO_WAVE_LIMIT_MAX_LIMIT0_MASK (0xFFFFU) +#define QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT (0U) +#define QEO_WAVE_LIMIT_MAX_LIMIT0_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT) & QEO_WAVE_LIMIT_MAX_LIMIT0_MASK) +#define QEO_WAVE_LIMIT_MAX_LIMIT0_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MAX_LIMIT0_MASK) >> QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT) + +/* Bitfield definition for register of struct WAVE: WAVE0 */ +/* + * VAL (RW) + * + * wave0 deadzone shifter value + */ +#define QEO_WAVE_DEADZONE_SHIFT_VAL_MASK (0xFFFFU) +#define QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT (0U) +#define QEO_WAVE_DEADZONE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT) & QEO_WAVE_DEADZONE_SHIFT_VAL_MASK) +#define QEO_WAVE_DEADZONE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_DEADZONE_SHIFT_VAL_MASK) >> QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT) + +/* Bitfield definition for register of struct ABZ: MODE */ +/* + * REVERSE_EDGE_TYPE (RW) + * + * pulse reverse wave，reverse edge point: + * 0: between pulse's posedge and negedge, min period dedicated by the num line_width + * 1: edge change point flow pulse's negedge. + */ +#define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK (0x10000000UL) +#define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT (28U) +#define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) & QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) +#define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) >> QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) + +/* + * EN_WDOG (RW) + * + * enable abz wdog: + * 0: disable abz wdog. + * 1: enable abz wdog. + */ +#define QEO_ABZ_MODE_EN_WDOG_MASK (0x1000000UL) +#define QEO_ABZ_MODE_EN_WDOG_SHIFT (24U) +#define QEO_ABZ_MODE_EN_WDOG_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_EN_WDOG_SHIFT) & QEO_ABZ_MODE_EN_WDOG_MASK) +#define QEO_ABZ_MODE_EN_WDOG_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_EN_WDOG_MASK) >> QEO_ABZ_MODE_EN_WDOG_SHIFT) + +/* + * Z_POLARITY (RW) + * + * wave_z polarity. + * 0: normal output. + * 1: invert normal output + */ +#define QEO_ABZ_MODE_Z_POLARITY_MASK (0x100000UL) +#define QEO_ABZ_MODE_Z_POLARITY_SHIFT (20U) +#define QEO_ABZ_MODE_Z_POLARITY_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_Z_POLARITY_SHIFT) & QEO_ABZ_MODE_Z_POLARITY_MASK) +#define QEO_ABZ_MODE_Z_POLARITY_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_Z_POLARITY_MASK) >> QEO_ABZ_MODE_Z_POLARITY_SHIFT) + +/* + * B_POLARITY (RW) + * + * wave_b polarity. + * 0: normal output. + * 1: invert normal output + */ +#define QEO_ABZ_MODE_B_POLARITY_MASK (0x10000UL) +#define QEO_ABZ_MODE_B_POLARITY_SHIFT (16U) +#define QEO_ABZ_MODE_B_POLARITY_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_B_POLARITY_SHIFT) & QEO_ABZ_MODE_B_POLARITY_MASK) +#define QEO_ABZ_MODE_B_POLARITY_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_B_POLARITY_MASK) >> QEO_ABZ_MODE_B_POLARITY_SHIFT) + +/* + * A_POLARITY (RW) + * + * wave_a polarity. + * 0: normal output. + * 1: invert normal output + */ +#define QEO_ABZ_MODE_A_POLARITY_MASK (0x1000U) +#define QEO_ABZ_MODE_A_POLARITY_SHIFT (12U) +#define QEO_ABZ_MODE_A_POLARITY_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_A_POLARITY_SHIFT) & QEO_ABZ_MODE_A_POLARITY_MASK) +#define QEO_ABZ_MODE_A_POLARITY_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_A_POLARITY_MASK) >> QEO_ABZ_MODE_A_POLARITY_SHIFT) + +/* + * Z_TYPE (RW) + * + * wave_z type: + * 0: zero pulse and output high at both wave_a and wave_b are high. mantain about 25% period. + * 1: zero pulse output high about 75% period. start from 0 to 75% period. + * 2: zero pulse output high about 100% period. + * 3: wave_z output as tree-phase wave same as wave_a/wave_b + */ +#define QEO_ABZ_MODE_Z_TYPE_MASK (0x300U) +#define QEO_ABZ_MODE_Z_TYPE_SHIFT (8U) +#define QEO_ABZ_MODE_Z_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_Z_TYPE_SHIFT) & QEO_ABZ_MODE_Z_TYPE_MASK) +#define QEO_ABZ_MODE_Z_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_Z_TYPE_MASK) >> QEO_ABZ_MODE_Z_TYPE_SHIFT) + +/* + * B_TYPE (RW) + * + * wave_b type: + * 0: Two-phase orthogonality wave_b. + * 1: reverse wave of pulse/reverse type. + * 2: down wave of up/down type. + * 3: Three-phase orthogonality wave_b. + */ +#define QEO_ABZ_MODE_B_TYPE_MASK (0x30U) +#define QEO_ABZ_MODE_B_TYPE_SHIFT (4U) +#define QEO_ABZ_MODE_B_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_B_TYPE_SHIFT) & QEO_ABZ_MODE_B_TYPE_MASK) +#define QEO_ABZ_MODE_B_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_B_TYPE_MASK) >> QEO_ABZ_MODE_B_TYPE_SHIFT) + +/* + * A_TYPE (RW) + * + * wave_a type: + * 0: Two-phase orthogonality wave_a. + * 1: pulse wave of pulse/reverse type. + * 2: up wave of up/down type. + * 3: Three-phase orthogonality wave_a. + */ +#define QEO_ABZ_MODE_A_TYPE_MASK (0x3U) +#define QEO_ABZ_MODE_A_TYPE_SHIFT (0U) +#define QEO_ABZ_MODE_A_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_A_TYPE_SHIFT) & QEO_ABZ_MODE_A_TYPE_MASK) +#define QEO_ABZ_MODE_A_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_A_TYPE_MASK) >> QEO_ABZ_MODE_A_TYPE_SHIFT) + +/* Bitfield definition for register of struct ABZ: RESOLUTION */ +/* + * LINES (RW) + * + * wave_a/b/z resolution + */ +#define QEO_ABZ_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) +#define QEO_ABZ_RESOLUTION_LINES_SHIFT (0U) +#define QEO_ABZ_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEO_ABZ_RESOLUTION_LINES_SHIFT) & QEO_ABZ_RESOLUTION_LINES_MASK) +#define QEO_ABZ_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEO_ABZ_RESOLUTION_LINES_MASK) >> QEO_ABZ_RESOLUTION_LINES_SHIFT) + +/* Bitfield definition for register of struct ABZ: A */ +/* + * VAL (RW) + * + * wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period. + */ +#define QEO_ABZ_PHASE_SHIFT_VAL_MASK (0xFFFFU) +#define QEO_ABZ_PHASE_SHIFT_VAL_SHIFT (0U) +#define QEO_ABZ_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_ABZ_PHASE_SHIFT_VAL_SHIFT) & QEO_ABZ_PHASE_SHIFT_VAL_MASK) +#define QEO_ABZ_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_ABZ_PHASE_SHIFT_VAL_MASK) >> QEO_ABZ_PHASE_SHIFT_VAL_SHIFT) + +/* Bitfield definition for register of struct ABZ: LINE_WIDTH */ +/* + * LINE (RW) + * + * the num of system clk by 1/4 period when using as Two-phase orthogonality. + */ +#define QEO_ABZ_LINE_WIDTH_LINE_MASK (0xFFFFFFFFUL) +#define QEO_ABZ_LINE_WIDTH_LINE_SHIFT (0U) +#define QEO_ABZ_LINE_WIDTH_LINE_SET(x) (((uint32_t)(x) << QEO_ABZ_LINE_WIDTH_LINE_SHIFT) & QEO_ABZ_LINE_WIDTH_LINE_MASK) +#define QEO_ABZ_LINE_WIDTH_LINE_GET(x) (((uint32_t)(x) & QEO_ABZ_LINE_WIDTH_LINE_MASK) >> QEO_ABZ_LINE_WIDTH_LINE_SHIFT) + +/* Bitfield definition for register of struct ABZ: WDOG_WIDTH */ +/* + * WIDTH (RW) + * + * wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk. + */ +#define QEO_ABZ_WDOG_WIDTH_WIDTH_MASK (0xFFFFFFFFUL) +#define QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT (0U) +#define QEO_ABZ_WDOG_WIDTH_WIDTH_SET(x) (((uint32_t)(x) << QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT) & QEO_ABZ_WDOG_WIDTH_WIDTH_MASK) +#define QEO_ABZ_WDOG_WIDTH_WIDTH_GET(x) (((uint32_t)(x) & QEO_ABZ_WDOG_WIDTH_WIDTH_MASK) >> QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT) + +/* Bitfield definition for register of struct ABZ: POSTION_SYNC */ +/* + * POSTION (WO) + * + * load next valid postion into abz owned postion. always read 0 + * 0: sync abz owned postion with next valid postion. + * 1: not sync. + */ +#define QEO_ABZ_POSTION_SYNC_POSTION_MASK (0x1U) +#define QEO_ABZ_POSTION_SYNC_POSTION_SHIFT (0U) +#define QEO_ABZ_POSTION_SYNC_POSTION_SET(x) (((uint32_t)(x) << QEO_ABZ_POSTION_SYNC_POSTION_SHIFT) & QEO_ABZ_POSTION_SYNC_POSTION_MASK) +#define QEO_ABZ_POSTION_SYNC_POSTION_GET(x) (((uint32_t)(x) & QEO_ABZ_POSTION_SYNC_POSTION_MASK) >> QEO_ABZ_POSTION_SYNC_POSTION_SHIFT) + +/* Bitfield definition for register of struct PWM: MODE */ +/* + * PWM7_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM7_SAFETY_MASK (0xC0000000UL) +#define QEO_PWM_MODE_PWM7_SAFETY_SHIFT (30U) +#define QEO_PWM_MODE_PWM7_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM7_SAFETY_SHIFT) & QEO_PWM_MODE_PWM7_SAFETY_MASK) +#define QEO_PWM_MODE_PWM7_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM7_SAFETY_MASK) >> QEO_PWM_MODE_PWM7_SAFETY_SHIFT) + +/* + * PWM6_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM6_SAFETY_MASK (0x30000000UL) +#define QEO_PWM_MODE_PWM6_SAFETY_SHIFT (28U) +#define QEO_PWM_MODE_PWM6_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM6_SAFETY_SHIFT) & QEO_PWM_MODE_PWM6_SAFETY_MASK) +#define QEO_PWM_MODE_PWM6_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM6_SAFETY_MASK) >> QEO_PWM_MODE_PWM6_SAFETY_SHIFT) + +/* + * PWM5_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM5_SAFETY_MASK (0xC000000UL) +#define QEO_PWM_MODE_PWM5_SAFETY_SHIFT (26U) +#define QEO_PWM_MODE_PWM5_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM5_SAFETY_SHIFT) & QEO_PWM_MODE_PWM5_SAFETY_MASK) +#define QEO_PWM_MODE_PWM5_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM5_SAFETY_MASK) >> QEO_PWM_MODE_PWM5_SAFETY_SHIFT) + +/* + * PWM4_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM4_SAFETY_MASK (0x3000000UL) +#define QEO_PWM_MODE_PWM4_SAFETY_SHIFT (24U) +#define QEO_PWM_MODE_PWM4_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM4_SAFETY_SHIFT) & QEO_PWM_MODE_PWM4_SAFETY_MASK) +#define QEO_PWM_MODE_PWM4_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM4_SAFETY_MASK) >> QEO_PWM_MODE_PWM4_SAFETY_SHIFT) + +/* + * PWM3_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM3_SAFETY_MASK (0xC00000UL) +#define QEO_PWM_MODE_PWM3_SAFETY_SHIFT (22U) +#define QEO_PWM_MODE_PWM3_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM3_SAFETY_SHIFT) & QEO_PWM_MODE_PWM3_SAFETY_MASK) +#define QEO_PWM_MODE_PWM3_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM3_SAFETY_MASK) >> QEO_PWM_MODE_PWM3_SAFETY_SHIFT) + +/* + * PWM2_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM2_SAFETY_MASK (0x300000UL) +#define QEO_PWM_MODE_PWM2_SAFETY_SHIFT (20U) +#define QEO_PWM_MODE_PWM2_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM2_SAFETY_SHIFT) & QEO_PWM_MODE_PWM2_SAFETY_MASK) +#define QEO_PWM_MODE_PWM2_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM2_SAFETY_MASK) >> QEO_PWM_MODE_PWM2_SAFETY_SHIFT) + +/* + * PWM1_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM1_SAFETY_MASK (0xC0000UL) +#define QEO_PWM_MODE_PWM1_SAFETY_SHIFT (18U) +#define QEO_PWM_MODE_PWM1_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM1_SAFETY_SHIFT) & QEO_PWM_MODE_PWM1_SAFETY_MASK) +#define QEO_PWM_MODE_PWM1_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM1_SAFETY_MASK) >> QEO_PWM_MODE_PWM1_SAFETY_SHIFT) + +/* + * PWM0_SAFETY (RW) + * + * PWM safety mode phase table + */ +#define QEO_PWM_MODE_PWM0_SAFETY_MASK (0x30000UL) +#define QEO_PWM_MODE_PWM0_SAFETY_SHIFT (16U) +#define QEO_PWM_MODE_PWM0_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM0_SAFETY_SHIFT) & QEO_PWM_MODE_PWM0_SAFETY_MASK) +#define QEO_PWM_MODE_PWM0_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM0_SAFETY_MASK) >> QEO_PWM_MODE_PWM0_SAFETY_SHIFT) + +/* + * PWM_ENTER_SAFETY_MODE (RW) + * + * PWM enter safety mode + * 0: not enter + * 1: enter + */ +#define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK (0x200U) +#define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT (9U) +#define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) & QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) +#define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) >> QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) + +/* + * PWM_SAFETY_BYPASS (RW) + * + * PWM safety mode bypass + * 0: not bypass + * 1: bypass + */ +#define QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK (0x100U) +#define QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT (8U) +#define QEO_PWM_MODE_PWM_SAFETY_BYPASS_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) & QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK) +#define QEO_PWM_MODE_PWM_SAFETY_BYPASS_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK) >> QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) + +/* + * REVISE_UP_DN (RW) + * + * exchange PWM pairs’ output + * 0: not exchange. + * 1: exchange. + */ +#define QEO_PWM_MODE_REVISE_UP_DN_MASK (0x10U) +#define QEO_PWM_MODE_REVISE_UP_DN_SHIFT (4U) +#define QEO_PWM_MODE_REVISE_UP_DN_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_REVISE_UP_DN_SHIFT) & QEO_PWM_MODE_REVISE_UP_DN_MASK) +#define QEO_PWM_MODE_REVISE_UP_DN_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_REVISE_UP_DN_MASK) >> QEO_PWM_MODE_REVISE_UP_DN_SHIFT) + +/* + * PHASE_NUM (RW) + * + * pwm force phase number. + */ +#define QEO_PWM_MODE_PHASE_NUM_MASK (0xFU) +#define QEO_PWM_MODE_PHASE_NUM_SHIFT (0U) +#define QEO_PWM_MODE_PHASE_NUM_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PHASE_NUM_SHIFT) & QEO_PWM_MODE_PHASE_NUM_MASK) +#define QEO_PWM_MODE_PHASE_NUM_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PHASE_NUM_MASK) >> QEO_PWM_MODE_PHASE_NUM_SHIFT) + +/* Bitfield definition for register of struct PWM: RESOLUTION */ +/* + * LINES (RW) + * + * pwm resolution + */ +#define QEO_PWM_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) +#define QEO_PWM_RESOLUTION_LINES_SHIFT (0U) +#define QEO_PWM_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEO_PWM_RESOLUTION_LINES_SHIFT) & QEO_PWM_RESOLUTION_LINES_MASK) +#define QEO_PWM_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEO_PWM_RESOLUTION_LINES_MASK) >> QEO_PWM_RESOLUTION_LINES_SHIFT) + +/* Bitfield definition for register of struct PWM: A */ +/* + * VAL (RW) + * + * pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period + */ +#define QEO_PWM_PHASE_SHIFT_VAL_MASK (0xFFFFU) +#define QEO_PWM_PHASE_SHIFT_VAL_SHIFT (0U) +#define QEO_PWM_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_SHIFT_VAL_SHIFT) & QEO_PWM_PHASE_SHIFT_VAL_MASK) +#define QEO_PWM_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_SHIFT_VAL_MASK) >> QEO_PWM_PHASE_SHIFT_VAL_SHIFT) + +/* Bitfield definition for register of struct PWM: POSEDGE0 */ +/* + * PWM7 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM7_MASK (0xC000U) +#define QEO_PWM_PHASE_TABLE_PWM7_SHIFT (14U) +#define QEO_PWM_PHASE_TABLE_PWM7_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM7_SHIFT) & QEO_PWM_PHASE_TABLE_PWM7_MASK) +#define QEO_PWM_PHASE_TABLE_PWM7_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM7_MASK) >> QEO_PWM_PHASE_TABLE_PWM7_SHIFT) + +/* + * PWM6 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM6_MASK (0x3000U) +#define QEO_PWM_PHASE_TABLE_PWM6_SHIFT (12U) +#define QEO_PWM_PHASE_TABLE_PWM6_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM6_SHIFT) & QEO_PWM_PHASE_TABLE_PWM6_MASK) +#define QEO_PWM_PHASE_TABLE_PWM6_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM6_MASK) >> QEO_PWM_PHASE_TABLE_PWM6_SHIFT) + +/* + * PWM5 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM5_MASK (0xC00U) +#define QEO_PWM_PHASE_TABLE_PWM5_SHIFT (10U) +#define QEO_PWM_PHASE_TABLE_PWM5_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM5_SHIFT) & QEO_PWM_PHASE_TABLE_PWM5_MASK) +#define QEO_PWM_PHASE_TABLE_PWM5_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM5_MASK) >> QEO_PWM_PHASE_TABLE_PWM5_SHIFT) + +/* + * PWM4 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM4_MASK (0x300U) +#define QEO_PWM_PHASE_TABLE_PWM4_SHIFT (8U) +#define QEO_PWM_PHASE_TABLE_PWM4_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM4_SHIFT) & QEO_PWM_PHASE_TABLE_PWM4_MASK) +#define QEO_PWM_PHASE_TABLE_PWM4_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM4_MASK) >> QEO_PWM_PHASE_TABLE_PWM4_SHIFT) + +/* + * PWM3 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM3_MASK (0xC0U) +#define QEO_PWM_PHASE_TABLE_PWM3_SHIFT (6U) +#define QEO_PWM_PHASE_TABLE_PWM3_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM3_SHIFT) & QEO_PWM_PHASE_TABLE_PWM3_MASK) +#define QEO_PWM_PHASE_TABLE_PWM3_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM3_MASK) >> QEO_PWM_PHASE_TABLE_PWM3_SHIFT) + +/* + * PWM2 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM2_MASK (0x30U) +#define QEO_PWM_PHASE_TABLE_PWM2_SHIFT (4U) +#define QEO_PWM_PHASE_TABLE_PWM2_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM2_SHIFT) & QEO_PWM_PHASE_TABLE_PWM2_MASK) +#define QEO_PWM_PHASE_TABLE_PWM2_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM2_MASK) >> QEO_PWM_PHASE_TABLE_PWM2_SHIFT) + +/* + * PWM1 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM1_MASK (0xCU) +#define QEO_PWM_PHASE_TABLE_PWM1_SHIFT (2U) +#define QEO_PWM_PHASE_TABLE_PWM1_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM1_SHIFT) & QEO_PWM_PHASE_TABLE_PWM1_MASK) +#define QEO_PWM_PHASE_TABLE_PWM1_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM1_MASK) >> QEO_PWM_PHASE_TABLE_PWM1_SHIFT) + +/* + * PWM0 (RW) + * + * pwm phase table value + */ +#define QEO_PWM_PHASE_TABLE_PWM0_MASK (0x3U) +#define QEO_PWM_PHASE_TABLE_PWM0_SHIFT (0U) +#define QEO_PWM_PHASE_TABLE_PWM0_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM0_SHIFT) & QEO_PWM_PHASE_TABLE_PWM0_MASK) +#define QEO_PWM_PHASE_TABLE_PWM0_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM0_MASK) >> QEO_PWM_PHASE_TABLE_PWM0_SHIFT) + +/* Bitfield definition for register: POSTION_SOFTWARE */ +/* + * POSTION_SOFTWAVE (RW) + * + * softwave inject postion + */ +#define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK (0xFFFFFFFFUL) +#define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT (0U) +#define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET(x) (((uint32_t)(x) << QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) & QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) +#define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_GET(x) (((uint32_t)(x) & QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) >> QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) + +/* Bitfield definition for register: POSTION_SEL */ +/* + * POSTION_SEL (RW) + * + * enable softwave inject postion. + * 0: disable. + * 1: enable. + */ +#define QEO_POSTION_SEL_POSTION_SEL_MASK (0x1U) +#define QEO_POSTION_SEL_POSTION_SEL_SHIFT (0U) +#define QEO_POSTION_SEL_POSTION_SEL_SET(x) (((uint32_t)(x) << QEO_POSTION_SEL_POSTION_SEL_SHIFT) & QEO_POSTION_SEL_POSTION_SEL_MASK) +#define QEO_POSTION_SEL_POSTION_SEL_GET(x) (((uint32_t)(x) & QEO_POSTION_SEL_POSTION_SEL_MASK) >> QEO_POSTION_SEL_POSTION_SEL_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * PWM_FOURCE (RO) + * + * qeo_pwm_force observe + */ +#define QEO_STATUS_PWM_FOURCE_MASK (0xFFFF0000UL) +#define QEO_STATUS_PWM_FOURCE_SHIFT (16U) +#define QEO_STATUS_PWM_FOURCE_GET(x) (((uint32_t)(x) & QEO_STATUS_PWM_FOURCE_MASK) >> QEO_STATUS_PWM_FOURCE_SHIFT) + +/* + * PWM_SAFETY (RO) + * + * pwm_fault status + */ +#define QEO_STATUS_PWM_SAFETY_MASK (0x1U) +#define QEO_STATUS_PWM_SAFETY_SHIFT (0U) +#define QEO_STATUS_PWM_SAFETY_GET(x) (((uint32_t)(x) & QEO_STATUS_PWM_SAFETY_MASK) >> QEO_STATUS_PWM_SAFETY_SHIFT) + +/* Bitfield definition for register: DEBUG0 */ +/* + * WAVE1 (RO) + * + * wave1 observe + */ +#define QEO_DEBUG0_WAVE1_MASK (0xFFFF0000UL) +#define QEO_DEBUG0_WAVE1_SHIFT (16U) +#define QEO_DEBUG0_WAVE1_GET(x) (((uint32_t)(x) & QEO_DEBUG0_WAVE1_MASK) >> QEO_DEBUG0_WAVE1_SHIFT) + +/* + * WAVE0 (RO) + * + * wave0 observe + */ +#define QEO_DEBUG0_WAVE0_MASK (0xFFFFU) +#define QEO_DEBUG0_WAVE0_SHIFT (0U) +#define QEO_DEBUG0_WAVE0_GET(x) (((uint32_t)(x) & QEO_DEBUG0_WAVE0_MASK) >> QEO_DEBUG0_WAVE0_SHIFT) + +/* Bitfield definition for register: DEBUG1 */ +/* + * QEO_FINISH (RO) + * + * qeo finish observe + */ +#define QEO_DEBUG1_QEO_FINISH_MASK (0x10000000UL) +#define QEO_DEBUG1_QEO_FINISH_SHIFT (28U) +#define QEO_DEBUG1_QEO_FINISH_GET(x) (((uint32_t)(x) & QEO_DEBUG1_QEO_FINISH_MASK) >> QEO_DEBUG1_QEO_FINISH_SHIFT) + +/* + * WAVE_Z (RO) + * + * wave_z observe + */ +#define QEO_DEBUG1_WAVE_Z_MASK (0x1000000UL) +#define QEO_DEBUG1_WAVE_Z_SHIFT (24U) +#define QEO_DEBUG1_WAVE_Z_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE_Z_MASK) >> QEO_DEBUG1_WAVE_Z_SHIFT) + +/* + * WAVE_B (RO) + * + * wave_b observe + */ +#define QEO_DEBUG1_WAVE_B_MASK (0x100000UL) +#define QEO_DEBUG1_WAVE_B_SHIFT (20U) +#define QEO_DEBUG1_WAVE_B_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE_B_MASK) >> QEO_DEBUG1_WAVE_B_SHIFT) + +/* + * WAVE_A (RO) + * + * wave_a observe + */ +#define QEO_DEBUG1_WAVE_A_MASK (0x10000UL) +#define QEO_DEBUG1_WAVE_A_SHIFT (16U) +#define QEO_DEBUG1_WAVE_A_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE_A_MASK) >> QEO_DEBUG1_WAVE_A_SHIFT) + +/* + * WAVE2 (RO) + * + * wave2 observe + */ +#define QEO_DEBUG1_WAVE2_MASK (0xFFFFU) +#define QEO_DEBUG1_WAVE2_SHIFT (0U) +#define QEO_DEBUG1_WAVE2_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE2_MASK) >> QEO_DEBUG1_WAVE2_SHIFT) + +/* Bitfield definition for register: DEBUG2 */ +/* + * ABZ_OWN_POSTION (RO) + * + * abz_own_postion observe + */ +#define QEO_DEBUG2_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL) +#define QEO_DEBUG2_ABZ_OWN_POSTION_SHIFT (0U) +#define QEO_DEBUG2_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEO_DEBUG2_ABZ_OWN_POSTION_MASK) >> QEO_DEBUG2_ABZ_OWN_POSTION_SHIFT) + +/* Bitfield definition for register: DEBUG3 */ +/* + * ABZ_OWN_POSTION (RO) + * + * abz_own_postion observe + */ +#define QEO_DEBUG3_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL) +#define QEO_DEBUG3_ABZ_OWN_POSTION_SHIFT (0U) +#define QEO_DEBUG3_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEO_DEBUG3_ABZ_OWN_POSTION_MASK) >> QEO_DEBUG3_ABZ_OWN_POSTION_SHIFT) + + + +/* PHASE_SHIFT register group index macro definition */ +#define QEO_WAVE_PHASE_SHIFT_WAVE0 (0UL) +#define QEO_WAVE_PHASE_SHIFT_WAVE1 (1UL) +#define QEO_WAVE_PHASE_SHIFT_WAVE2 (2UL) + +/* VD_VQ_INJECT register group index macro definition */ +#define QEO_WAVE_VD_VQ_INJECT_WAVE0 (0UL) +#define QEO_WAVE_VD_VQ_INJECT_WAVE1 (1UL) +#define QEO_WAVE_VD_VQ_INJECT_WAVE2 (2UL) + +/* AMPLITUDE register group index macro definition */ +#define QEO_WAVE_AMPLITUDE_WAVE0 (0UL) +#define QEO_WAVE_AMPLITUDE_WAVE1 (1UL) +#define QEO_WAVE_AMPLITUDE_WAVE2 (2UL) + +/* MID_POINT register group index macro definition */ +#define QEO_WAVE_MID_POINT_WAVE0 (0UL) +#define QEO_WAVE_MID_POINT_WAVE1 (1UL) +#define QEO_WAVE_MID_POINT_WAVE2 (2UL) + +/* LIMIT register group index macro definition */ +#define QEO_LIMIT_WAVE0 (0UL) +#define QEO_LIMIT_WAVE1 (1UL) +#define QEO_LIMIT_WAVE2 (2UL) + +/* DEADZONE_SHIFT register group index macro definition */ +#define QEO_WAVE_DEADZONE_SHIFT_WAVE0 (0UL) +#define QEO_WAVE_DEADZONE_SHIFT_WAVE1 (1UL) +#define QEO_WAVE_DEADZONE_SHIFT_WAVE2 (2UL) + +/* PHASE_SHIFT register group index macro definition */ +#define QEO_ABZ_PHASE_SHIFT_A (0UL) +#define QEO_ABZ_PHASE_SHIFT_B (1UL) +#define QEO_ABZ_PHASE_SHIFT_Z (2UL) + +/* PHASE_SHIFT register group index macro definition */ +#define QEO_PWM_PHASE_SHIFT_A (0UL) +#define QEO_PWM_PHASE_SHIFT_B (1UL) +#define QEO_PWM_PHASE_SHIFT_C (2UL) +#define QEO_PWM_PHASE_SHIFT_D (3UL) + +/* PHASE_TABLE register group index macro definition */ +#define QEO_PWM_PHASE_TABLE_POSEDGE0 (0UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE1 (1UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE2 (2UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE3 (3UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE4 (4UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE5 (5UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE6 (6UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE7 (7UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE8 (8UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE9 (9UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE10 (10UL) +#define QEO_PWM_PHASE_TABLE_POSEDGE11 (11UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE0 (12UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE1 (13UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE2 (14UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE3 (15UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE4 (16UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE5 (17UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE6 (18UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE7 (19UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE8 (20UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE9 (21UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE10 (22UL) +#define QEO_PWM_PHASE_TABLE_NEGEDGE11 (23UL) + + +#endif /* HPM_QEO_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_rdc_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_rdc_regs.h new file mode 100644 index 00000000..95d83945 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_rdc_regs.h @@ -0,0 +1,1331 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_RDC_H +#define HPM_RDC_H + +typedef struct { + __RW uint32_t RDC_CTL; /* 0x0: rdc control */ + __R uint32_t ACC_I; /* 0x4: accumulate result of i_channel */ + __R uint32_t ACC_Q; /* 0x8: accumulate result of q_channel */ + __RW uint32_t IN_CTL; /* 0xC: input channel selection */ + __RW uint32_t OUT_CTL; /* 0x10: output channel selection */ + __R uint8_t RESERVED0[32]; /* 0x14 - 0x33: Reserved */ + __RW uint32_t EXC_TIMMING; /* 0x34: excitation signal timming setting */ + __RW uint32_t EXC_SCALING; /* 0x38: amplitude scaling for excitation */ + __RW uint32_t EXC_OFFSET; /* 0x3C: amplitude offset setting */ + __RW uint32_t PWM_SCALING; /* 0x40: amplitude scaling for excitation */ + __RW uint32_t PWM_OFFSET; /* 0x44: amplitude offset setting */ + __RW uint32_t TRIG_OUT0_CFG; /* 0x48: Configuration for trigger out 0 in clock cycle */ + __RW uint32_t TRIG_OUT1_CFG; /* 0x4C: Configuration for trigger out 1 in clock cycle */ + __RW uint32_t PWM_DZ; /* 0x50: pwm dead zone control in clock cycle */ + __RW uint32_t SYNC_OUT_CTRL; /* 0x54: synchronize output signal control */ + __RW uint32_t EXC_SYNC_DLY; /* 0x58: trigger in delay timming in soc bus cycle */ + __R uint8_t RESERVED1[20]; /* 0x5C - 0x6F: Reserved */ + __RW uint32_t MAX_I; /* 0x70: max value of i_channel */ + __RW uint32_t MIN_I; /* 0x74: min value of i_channel */ + __RW uint32_t MAX_Q; /* 0x78: max value of q_channel */ + __RW uint32_t MIN_Q; /* 0x7C: min value of q_channel */ + __RW uint32_t THRS_I; /* 0x80: the offset setting for edge detection of the i_channel */ + __RW uint32_t THRS_Q; /* 0x84: the offset setting for edge detection of the q_channel */ + __RW uint32_t EDG_DET_CTL; /* 0x88: the control for edge detection */ + __RW uint32_t ACC_SCALING; /* 0x8C: scaling for accumulation result */ + __RW uint32_t EXC_PERIOD; /* 0x90: period of excitation */ + __R uint8_t RESERVED2[12]; /* 0x94 - 0x9F: Reserved */ + __RW uint32_t SYNC_DELAY_I; /* 0xA0: delay setting in clock cycle for synchronous signal */ + __R uint8_t RESERVED3[4]; /* 0xA4 - 0xA7: Reserved */ + __R uint32_t RISE_DELAY_I; /* 0xA8: delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data */ + __R uint32_t FALL_DELAY_I; /* 0xAC: delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data */ + __R uint32_t SAMPLE_RISE_I; /* 0xB0: sample value on rising edge of rectify signal */ + __R uint32_t SAMPLE_FALL_I; /* 0xB4: sample value on falling edge of rectify signal */ + __R uint32_t ACC_CNT_I; /* 0xB8: number of accumulation */ + __R uint32_t SIGN_CNT_I; /* 0xBC: sample counter of opposite sign with rectify signal */ + __RW uint32_t SYNC_DELAY_Q; /* 0xC0: delay setting in clock cycle for synchronous signal */ + __R uint8_t RESERVED4[4]; /* 0xC4 - 0xC7: Reserved */ + __R uint32_t RISE_DELAY_Q; /* 0xC8: delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data */ + __R uint32_t FALL_DELAY_Q; /* 0xCC: delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data */ + __R uint32_t SAMPLE_RISE_Q; /* 0xD0: sample value on rising edge of rectify signal */ + __R uint32_t SAMPLE_FALL_Q; /* 0xD4: sample value on falling edge of rectify signal */ + __R uint32_t ACC_CNT_Q; /* 0xD8: number of accumulation */ + __R uint32_t SIGN_CNT_Q; /* 0xDC: sample counter of opposite sign with rectify signal */ + __RW uint32_t AMP_MAX; /* 0xE0: the maximum of acc amplitude */ + __RW uint32_t AMP_MIN; /* 0xE4: the minimum of acc amplitude */ + __RW uint32_t INT_EN; /* 0xE8: the interrupt mask control */ + __W uint32_t ADC_INT_STATE; /* 0xEC: the interrupt state */ +} RDC_Type; + + +/* Bitfield definition for register: RDC_CTL */ +/* + * TS_SEL (RW) + * + * Time stamp selection for accumulation + * 0: end of accumulation + * 1: start of accumulation + * 2: center of accumulation + */ +#define RDC_RDC_CTL_TS_SEL_MASK (0x300000UL) +#define RDC_RDC_CTL_TS_SEL_SHIFT (20U) +#define RDC_RDC_CTL_TS_SEL_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_TS_SEL_SHIFT) & RDC_RDC_CTL_TS_SEL_MASK) +#define RDC_RDC_CTL_TS_SEL_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_TS_SEL_MASK) >> RDC_RDC_CTL_TS_SEL_SHIFT) + +/* + * ACC_LEN (RW) + * + * Accumulate time, support on the fly change + * 0：1 cycle + * 1：2 cycles + * … + * 255: 256 cycles + */ +#define RDC_RDC_CTL_ACC_LEN_MASK (0xFF000UL) +#define RDC_RDC_CTL_ACC_LEN_SHIFT (12U) +#define RDC_RDC_CTL_ACC_LEN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_ACC_LEN_SHIFT) & RDC_RDC_CTL_ACC_LEN_MASK) +#define RDC_RDC_CTL_ACC_LEN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_ACC_LEN_MASK) >> RDC_RDC_CTL_ACC_LEN_SHIFT) + +/* + * RECTIFY_SEL (RW) + * + * Select reference point of rectify signal + * 0: 0 phase of internal exciting signal + * 1: 90 phase of internal exciting signal + * 2: 180 phase of internal exciting signal + * 3: 270 phase of internal exciting signal + * 4: use value on external pin + * 5: use invert value on external pin + */ +#define RDC_RDC_CTL_RECTIFY_SEL_MASK (0x70U) +#define RDC_RDC_CTL_RECTIFY_SEL_SHIFT (4U) +#define RDC_RDC_CTL_RECTIFY_SEL_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_RECTIFY_SEL_SHIFT) & RDC_RDC_CTL_RECTIFY_SEL_MASK) +#define RDC_RDC_CTL_RECTIFY_SEL_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_RECTIFY_SEL_MASK) >> RDC_RDC_CTL_RECTIFY_SEL_SHIFT) + +/* + * ACC_EN (RW) + * + * Enable rdc accumulate + * 0: rdc disable + * 1: rdc enable + */ +#define RDC_RDC_CTL_ACC_EN_MASK (0x4U) +#define RDC_RDC_CTL_ACC_EN_SHIFT (2U) +#define RDC_RDC_CTL_ACC_EN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_ACC_EN_SHIFT) & RDC_RDC_CTL_ACC_EN_MASK) +#define RDC_RDC_CTL_ACC_EN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_ACC_EN_MASK) >> RDC_RDC_CTL_ACC_EN_SHIFT) + +/* + * EXC_START (RW1C) + * + * Write 1 start excite signal, always read 0 + * 0: no effect + * 1: start excite signal + */ +#define RDC_RDC_CTL_EXC_START_MASK (0x2U) +#define RDC_RDC_CTL_EXC_START_SHIFT (1U) +#define RDC_RDC_CTL_EXC_START_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_EXC_START_SHIFT) & RDC_RDC_CTL_EXC_START_MASK) +#define RDC_RDC_CTL_EXC_START_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_EXC_START_MASK) >> RDC_RDC_CTL_EXC_START_SHIFT) + +/* + * EXC_EN (RW) + * + * Enable rdc excite signal + * 0: rdc disable + * 1: rdc enable + */ +#define RDC_RDC_CTL_EXC_EN_MASK (0x1U) +#define RDC_RDC_CTL_EXC_EN_SHIFT (0U) +#define RDC_RDC_CTL_EXC_EN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_EXC_EN_SHIFT) & RDC_RDC_CTL_EXC_EN_MASK) +#define RDC_RDC_CTL_EXC_EN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_EXC_EN_MASK) >> RDC_RDC_CTL_EXC_EN_SHIFT) + +/* Bitfield definition for register: ACC_I */ +/* + * ACC (RO) + * + * accumulate result of i_channel, this is a signed number + */ +#define RDC_ACC_I_ACC_MASK (0xFFFFFFFFUL) +#define RDC_ACC_I_ACC_SHIFT (0U) +#define RDC_ACC_I_ACC_GET(x) (((uint32_t)(x) & RDC_ACC_I_ACC_MASK) >> RDC_ACC_I_ACC_SHIFT) + +/* Bitfield definition for register: ACC_Q */ +/* + * ACC (RO) + * + * accumulate result of q_channel, this is a signed number + */ +#define RDC_ACC_Q_ACC_MASK (0xFFFFFFFFUL) +#define RDC_ACC_Q_ACC_SHIFT (0U) +#define RDC_ACC_Q_ACC_GET(x) (((uint32_t)(x) & RDC_ACC_Q_ACC_MASK) >> RDC_ACC_Q_ACC_SHIFT) + +/* Bitfield definition for register: IN_CTL */ +/* + * PORT_Q_SEL (RW) + * + * Input port selection for q_channel, + * 0:sel port0 + * 1:sel port1 + */ +#define RDC_IN_CTL_PORT_Q_SEL_MASK (0x100000UL) +#define RDC_IN_CTL_PORT_Q_SEL_SHIFT (20U) +#define RDC_IN_CTL_PORT_Q_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_PORT_Q_SEL_SHIFT) & RDC_IN_CTL_PORT_Q_SEL_MASK) +#define RDC_IN_CTL_PORT_Q_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_PORT_Q_SEL_MASK) >> RDC_IN_CTL_PORT_Q_SEL_SHIFT) + +/* + * CH_Q_SEL (RW) + * + * Input channel selection for q_channel + * 0: channel 0 selected + * 1: channel 1 selected + * … + * 31: channel 31 selected + */ +#define RDC_IN_CTL_CH_Q_SEL_MASK (0x1F000UL) +#define RDC_IN_CTL_CH_Q_SEL_SHIFT (12U) +#define RDC_IN_CTL_CH_Q_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_CH_Q_SEL_SHIFT) & RDC_IN_CTL_CH_Q_SEL_MASK) +#define RDC_IN_CTL_CH_Q_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_CH_Q_SEL_MASK) >> RDC_IN_CTL_CH_Q_SEL_SHIFT) + +/* + * PORT_I_SEL (RW) + * + * Input port selection for i_channel, + * 0:sel port0 + * 1:sel port1 + */ +#define RDC_IN_CTL_PORT_I_SEL_MASK (0x100U) +#define RDC_IN_CTL_PORT_I_SEL_SHIFT (8U) +#define RDC_IN_CTL_PORT_I_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_PORT_I_SEL_SHIFT) & RDC_IN_CTL_PORT_I_SEL_MASK) +#define RDC_IN_CTL_PORT_I_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_PORT_I_SEL_MASK) >> RDC_IN_CTL_PORT_I_SEL_SHIFT) + +/* + * CH_I_SEL (RW) + * + * Input channel selection for i_channel + * 0: channel 0 selected + * 1: channel 1 selected + * … + * 31: channel 31 selected + */ +#define RDC_IN_CTL_CH_I_SEL_MASK (0x1FU) +#define RDC_IN_CTL_CH_I_SEL_SHIFT (0U) +#define RDC_IN_CTL_CH_I_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_CH_I_SEL_SHIFT) & RDC_IN_CTL_CH_I_SEL_MASK) +#define RDC_IN_CTL_CH_I_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_CH_I_SEL_MASK) >> RDC_IN_CTL_CH_I_SEL_SHIFT) + +/* Bitfield definition for register: OUT_CTL */ +/* + * CH_Q_SEL (RW) + * + * Output channel selection for q_channel + */ +#define RDC_OUT_CTL_CH_Q_SEL_MASK (0x1F00U) +#define RDC_OUT_CTL_CH_Q_SEL_SHIFT (8U) +#define RDC_OUT_CTL_CH_Q_SEL_SET(x) (((uint32_t)(x) << RDC_OUT_CTL_CH_Q_SEL_SHIFT) & RDC_OUT_CTL_CH_Q_SEL_MASK) +#define RDC_OUT_CTL_CH_Q_SEL_GET(x) (((uint32_t)(x) & RDC_OUT_CTL_CH_Q_SEL_MASK) >> RDC_OUT_CTL_CH_Q_SEL_SHIFT) + +/* + * CH_I_SEL (RW) + * + * Output channel selection for i_channel + */ +#define RDC_OUT_CTL_CH_I_SEL_MASK (0x1FU) +#define RDC_OUT_CTL_CH_I_SEL_SHIFT (0U) +#define RDC_OUT_CTL_CH_I_SEL_SET(x) (((uint32_t)(x) << RDC_OUT_CTL_CH_I_SEL_SHIFT) & RDC_OUT_CTL_CH_I_SEL_MASK) +#define RDC_OUT_CTL_CH_I_SEL_GET(x) (((uint32_t)(x) & RDC_OUT_CTL_CH_I_SEL_MASK) >> RDC_OUT_CTL_CH_I_SEL_SHIFT) + +/* Bitfield definition for register: EXC_TIMMING */ +/* + * SWAP (RW) + * + * Swap output of PWM and DAC + * 0: disable swap + * 1: swap output + */ +#define RDC_EXC_TIMMING_SWAP_MASK (0x1000000UL) +#define RDC_EXC_TIMMING_SWAP_SHIFT (24U) +#define RDC_EXC_TIMMING_SWAP_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SWAP_SHIFT) & RDC_EXC_TIMMING_SWAP_MASK) +#define RDC_EXC_TIMMING_SWAP_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SWAP_MASK) >> RDC_EXC_TIMMING_SWAP_SHIFT) + +/* + * PWM_PRD (RW) + * + * Pwm period in samples， + * 0：1 sample period + * 1: 2 sample period + * ... + * 15: 16 sample period + */ +#define RDC_EXC_TIMMING_PWM_PRD_MASK (0xF00000UL) +#define RDC_EXC_TIMMING_PWM_PRD_SHIFT (20U) +#define RDC_EXC_TIMMING_PWM_PRD_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_PWM_PRD_SHIFT) & RDC_EXC_TIMMING_PWM_PRD_MASK) +#define RDC_EXC_TIMMING_PWM_PRD_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_PWM_PRD_MASK) >> RDC_EXC_TIMMING_PWM_PRD_SHIFT) + +/* + * SMP_NUM (RW) + * + * Number of sample every excitation period + * 0: 4 point + * 1: 8 point + * … + * 8: 1024 point + */ +#define RDC_EXC_TIMMING_SMP_NUM_MASK (0xF0000UL) +#define RDC_EXC_TIMMING_SMP_NUM_SHIFT (16U) +#define RDC_EXC_TIMMING_SMP_NUM_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SMP_NUM_SHIFT) & RDC_EXC_TIMMING_SMP_NUM_MASK) +#define RDC_EXC_TIMMING_SMP_NUM_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SMP_NUM_MASK) >> RDC_EXC_TIMMING_SMP_NUM_SHIFT) + +/* + * SMP_RATE (RW) + * + * The period for excitation sample in clock cycle， + * 0: not allowed + * 1: 1 cycle + * 2: 2 cycles + * … + * 65535 : 65535 cycles + */ +#define RDC_EXC_TIMMING_SMP_RATE_MASK (0xFFFFU) +#define RDC_EXC_TIMMING_SMP_RATE_SHIFT (0U) +#define RDC_EXC_TIMMING_SMP_RATE_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SMP_RATE_SHIFT) & RDC_EXC_TIMMING_SMP_RATE_MASK) +#define RDC_EXC_TIMMING_SMP_RATE_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SMP_RATE_MASK) >> RDC_EXC_TIMMING_SMP_RATE_SHIFT) + +/* Bitfield definition for register: EXC_SCALING */ +/* + * AMP_EXP (RW) + * + * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + */ +#define RDC_EXC_SCALING_AMP_EXP_MASK (0xF0U) +#define RDC_EXC_SCALING_AMP_EXP_SHIFT (4U) +#define RDC_EXC_SCALING_AMP_EXP_SET(x) (((uint32_t)(x) << RDC_EXC_SCALING_AMP_EXP_SHIFT) & RDC_EXC_SCALING_AMP_EXP_MASK) +#define RDC_EXC_SCALING_AMP_EXP_GET(x) (((uint32_t)(x) & RDC_EXC_SCALING_AMP_EXP_MASK) >> RDC_EXC_SCALING_AMP_EXP_SHIFT) + +/* + * AMP_MAN (RW) + * + * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + */ +#define RDC_EXC_SCALING_AMP_MAN_MASK (0xFU) +#define RDC_EXC_SCALING_AMP_MAN_SHIFT (0U) +#define RDC_EXC_SCALING_AMP_MAN_SET(x) (((uint32_t)(x) << RDC_EXC_SCALING_AMP_MAN_SHIFT) & RDC_EXC_SCALING_AMP_MAN_MASK) +#define RDC_EXC_SCALING_AMP_MAN_GET(x) (((uint32_t)(x) & RDC_EXC_SCALING_AMP_MAN_MASK) >> RDC_EXC_SCALING_AMP_MAN_SHIFT) + +/* Bitfield definition for register: EXC_OFFSET */ +/* + * AMP_OFFSET (RW) + * + * Offset for excitation + */ +#define RDC_EXC_OFFSET_AMP_OFFSET_MASK (0xFFFFFFUL) +#define RDC_EXC_OFFSET_AMP_OFFSET_SHIFT (0U) +#define RDC_EXC_OFFSET_AMP_OFFSET_SET(x) (((uint32_t)(x) << RDC_EXC_OFFSET_AMP_OFFSET_SHIFT) & RDC_EXC_OFFSET_AMP_OFFSET_MASK) +#define RDC_EXC_OFFSET_AMP_OFFSET_GET(x) (((uint32_t)(x) & RDC_EXC_OFFSET_AMP_OFFSET_MASK) >> RDC_EXC_OFFSET_AMP_OFFSET_SHIFT) + +/* Bitfield definition for register: PWM_SCALING */ +/* + * N_POL (RW) + * + * Polarity of exc_n signal + * 0: high active + * 1: low active + */ +#define RDC_PWM_SCALING_N_POL_MASK (0x2000U) +#define RDC_PWM_SCALING_N_POL_SHIFT (13U) +#define RDC_PWM_SCALING_N_POL_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_N_POL_SHIFT) & RDC_PWM_SCALING_N_POL_MASK) +#define RDC_PWM_SCALING_N_POL_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_N_POL_MASK) >> RDC_PWM_SCALING_N_POL_SHIFT) + +/* + * P_POL (RW) + * + * Polarity of exc_p signal + * 0: high active + * 1: low active + */ +#define RDC_PWM_SCALING_P_POL_MASK (0x1000U) +#define RDC_PWM_SCALING_P_POL_SHIFT (12U) +#define RDC_PWM_SCALING_P_POL_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_P_POL_SHIFT) & RDC_PWM_SCALING_P_POL_MASK) +#define RDC_PWM_SCALING_P_POL_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_P_POL_MASK) >> RDC_PWM_SCALING_P_POL_SHIFT) + +/* + * DITHER (RW) + * + * Enable dither of pwm + * 0: disable + * 1: enable + */ +#define RDC_PWM_SCALING_DITHER_MASK (0x100U) +#define RDC_PWM_SCALING_DITHER_SHIFT (8U) +#define RDC_PWM_SCALING_DITHER_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_DITHER_SHIFT) & RDC_PWM_SCALING_DITHER_MASK) +#define RDC_PWM_SCALING_DITHER_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_DITHER_MASK) >> RDC_PWM_SCALING_DITHER_SHIFT) + +/* + * AMP_EXP (RW) + * + * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + */ +#define RDC_PWM_SCALING_AMP_EXP_MASK (0xF0U) +#define RDC_PWM_SCALING_AMP_EXP_SHIFT (4U) +#define RDC_PWM_SCALING_AMP_EXP_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_AMP_EXP_SHIFT) & RDC_PWM_SCALING_AMP_EXP_MASK) +#define RDC_PWM_SCALING_AMP_EXP_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_AMP_EXP_MASK) >> RDC_PWM_SCALING_AMP_EXP_SHIFT) + +/* + * AMP_MAN (RW) + * + * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp + */ +#define RDC_PWM_SCALING_AMP_MAN_MASK (0xFU) +#define RDC_PWM_SCALING_AMP_MAN_SHIFT (0U) +#define RDC_PWM_SCALING_AMP_MAN_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_AMP_MAN_SHIFT) & RDC_PWM_SCALING_AMP_MAN_MASK) +#define RDC_PWM_SCALING_AMP_MAN_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_AMP_MAN_MASK) >> RDC_PWM_SCALING_AMP_MAN_SHIFT) + +/* Bitfield definition for register: PWM_OFFSET */ +/* + * AMP_OFFSET (RW) + * + * Offset for excitation + */ +#define RDC_PWM_OFFSET_AMP_OFFSET_MASK (0xFFFFFFUL) +#define RDC_PWM_OFFSET_AMP_OFFSET_SHIFT (0U) +#define RDC_PWM_OFFSET_AMP_OFFSET_SET(x) (((uint32_t)(x) << RDC_PWM_OFFSET_AMP_OFFSET_SHIFT) & RDC_PWM_OFFSET_AMP_OFFSET_MASK) +#define RDC_PWM_OFFSET_AMP_OFFSET_GET(x) (((uint32_t)(x) & RDC_PWM_OFFSET_AMP_OFFSET_MASK) >> RDC_PWM_OFFSET_AMP_OFFSET_SHIFT) + +/* Bitfield definition for register: TRIG_OUT0_CFG */ +/* + * ENABLE (RW) + * + * Enable trigger out0 + * 0: disable + * 1: enable + */ +#define RDC_TRIG_OUT0_CFG_ENABLE_MASK (0x100000UL) +#define RDC_TRIG_OUT0_CFG_ENABLE_SHIFT (20U) +#define RDC_TRIG_OUT0_CFG_ENABLE_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT0_CFG_ENABLE_SHIFT) & RDC_TRIG_OUT0_CFG_ENABLE_MASK) +#define RDC_TRIG_OUT0_CFG_ENABLE_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT0_CFG_ENABLE_MASK) >> RDC_TRIG_OUT0_CFG_ENABLE_SHIFT) + +/* + * LEAD_TIM (RW) + * + * Lead time for trigger out0 from center of low level , this is a signed value + * … + * 2: 2 cycle befor center of low level + * 1: 1 cycle before center of low level + * 0: center of low level + * -1: 1cycle after center of low level + * -2: 2cycle after center of low level + */ +#define RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK (0xFFFFFUL) +#define RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT (0U) +#define RDC_TRIG_OUT0_CFG_LEAD_TIM_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT) & RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK) +#define RDC_TRIG_OUT0_CFG_LEAD_TIM_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK) >> RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT) + +/* Bitfield definition for register: TRIG_OUT1_CFG */ +/* + * ENABLE (RW) + * + * Enable trigger out1 + * 0: disable + * 1: enable + */ +#define RDC_TRIG_OUT1_CFG_ENABLE_MASK (0x100000UL) +#define RDC_TRIG_OUT1_CFG_ENABLE_SHIFT (20U) +#define RDC_TRIG_OUT1_CFG_ENABLE_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT1_CFG_ENABLE_SHIFT) & RDC_TRIG_OUT1_CFG_ENABLE_MASK) +#define RDC_TRIG_OUT1_CFG_ENABLE_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT1_CFG_ENABLE_MASK) >> RDC_TRIG_OUT1_CFG_ENABLE_SHIFT) + +/* + * LEAD_TIM (RW) + * + * Lead time for trigger out0 from center of hight level , this is a signed value + * … + * 2: 2 cycle befor center of hight level + * 1: 1 cycle before center of hight level + * 0: center of hight level + * -1: 1cycle after center of hight level + * -2: 2cycle after center of hight level + */ +#define RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK (0xFFFFFUL) +#define RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT (0U) +#define RDC_TRIG_OUT1_CFG_LEAD_TIM_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT) & RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK) +#define RDC_TRIG_OUT1_CFG_LEAD_TIM_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK) >> RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT) + +/* Bitfield definition for register: PWM_DZ */ +/* + * DZ_N (RW) + * + * Exc_n dead zone in clock cycle before swap + * 0: no dead zone + * 1: 1 cycle dead zone + * 2: 2 cycle dead zone + * … + */ +#define RDC_PWM_DZ_DZ_N_MASK (0xFF00U) +#define RDC_PWM_DZ_DZ_N_SHIFT (8U) +#define RDC_PWM_DZ_DZ_N_SET(x) (((uint32_t)(x) << RDC_PWM_DZ_DZ_N_SHIFT) & RDC_PWM_DZ_DZ_N_MASK) +#define RDC_PWM_DZ_DZ_N_GET(x) (((uint32_t)(x) & RDC_PWM_DZ_DZ_N_MASK) >> RDC_PWM_DZ_DZ_N_SHIFT) + +/* + * DZ_P (RW) + * + * Exc_p dead zone in clock cycle before swap + * 0: no dead zone + * 1: 1 cycle dead zone + * 2: 2 cycle dead zone + * … + */ +#define RDC_PWM_DZ_DZ_P_MASK (0xFFU) +#define RDC_PWM_DZ_DZ_P_SHIFT (0U) +#define RDC_PWM_DZ_DZ_P_SET(x) (((uint32_t)(x) << RDC_PWM_DZ_DZ_P_SHIFT) & RDC_PWM_DZ_DZ_P_MASK) +#define RDC_PWM_DZ_DZ_P_GET(x) (((uint32_t)(x) & RDC_PWM_DZ_DZ_P_MASK) >> RDC_PWM_DZ_DZ_P_SHIFT) + +/* Bitfield definition for register: SYNC_OUT_CTRL */ +/* + * PWM_OUT_DLY (RO) + * + * Delay bettween the delyed trigger and the first pwm pulse in clock cycle + * 1: 1 cycle + * 2: 2 cycle + * … + */ +#define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_MASK (0xFFFF0000UL) +#define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_SHIFT (16U) +#define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_MASK) >> RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_SHIFT) + +/* + * MIN2TRIG_EN (RW) + * + * Enable trigger out from the min point of exciting signal + * 1: enable + * 0: disable + */ +#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK (0x20U) +#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT (5U) +#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT) & RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK) +#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK) >> RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT) + +/* + * MAX2TRIG_EN (RW) + * + * Enable trigger out from the max point of exciting signal + * 1: enable + * 0: disable + */ +#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK (0x10U) +#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT (4U) +#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT) & RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK) +#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK) >> RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT) + +/* + * SYNC_OUT_SEL (RW) + * + * Select output synchornize signal + * 0: 0 phase of internal exciting signal + * 1: 90 phase of internal exciting signal + * 2: 180 phase of internal exciting signal + * 3: 270 phase of internal exciting signal + */ +#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK (0x3U) +#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT (0U) +#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT) & RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK) +#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK) >> RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT) + +/* Bitfield definition for register: EXC_SYNC_DLY */ +/* + * DISABLE (RW) + * + * Disable hardware trigger input + * 0: enable + * 1: disable + */ +#define RDC_EXC_SYNC_DLY_DISABLE_MASK (0x1000000UL) +#define RDC_EXC_SYNC_DLY_DISABLE_SHIFT (24U) +#define RDC_EXC_SYNC_DLY_DISABLE_SET(x) (((uint32_t)(x) << RDC_EXC_SYNC_DLY_DISABLE_SHIFT) & RDC_EXC_SYNC_DLY_DISABLE_MASK) +#define RDC_EXC_SYNC_DLY_DISABLE_GET(x) (((uint32_t)(x) & RDC_EXC_SYNC_DLY_DISABLE_MASK) >> RDC_EXC_SYNC_DLY_DISABLE_SHIFT) + +/* + * DELAY (RW) + * + * Trigger in delay timming in bus cycle from rising edge of trigger signal + * 0: 1 cycle + * 1: 2 cycle + * … + * 0xffffff: 2^24 cycle + */ +#define RDC_EXC_SYNC_DLY_DELAY_MASK (0xFFFFFFUL) +#define RDC_EXC_SYNC_DLY_DELAY_SHIFT (0U) +#define RDC_EXC_SYNC_DLY_DELAY_SET(x) (((uint32_t)(x) << RDC_EXC_SYNC_DLY_DELAY_SHIFT) & RDC_EXC_SYNC_DLY_DELAY_MASK) +#define RDC_EXC_SYNC_DLY_DELAY_GET(x) (((uint32_t)(x) & RDC_EXC_SYNC_DLY_DELAY_MASK) >> RDC_EXC_SYNC_DLY_DELAY_SHIFT) + +/* Bitfield definition for register: MAX_I */ +/* + * MAX (RWC) + * + * Max value of i_channel, write clear + */ +#define RDC_MAX_I_MAX_MASK (0xFFFFFF00UL) +#define RDC_MAX_I_MAX_SHIFT (8U) +#define RDC_MAX_I_MAX_SET(x) (((uint32_t)(x) << RDC_MAX_I_MAX_SHIFT) & RDC_MAX_I_MAX_MASK) +#define RDC_MAX_I_MAX_GET(x) (((uint32_t)(x) & RDC_MAX_I_MAX_MASK) >> RDC_MAX_I_MAX_SHIFT) + +/* + * VALID (RWC) + * + * Max value valid, write clear + * 0: max value is not valid + * 1: max value is valid + */ +#define RDC_MAX_I_VALID_MASK (0x1U) +#define RDC_MAX_I_VALID_SHIFT (0U) +#define RDC_MAX_I_VALID_SET(x) (((uint32_t)(x) << RDC_MAX_I_VALID_SHIFT) & RDC_MAX_I_VALID_MASK) +#define RDC_MAX_I_VALID_GET(x) (((uint32_t)(x) & RDC_MAX_I_VALID_MASK) >> RDC_MAX_I_VALID_SHIFT) + +/* Bitfield definition for register: MIN_I */ +/* + * MIN (RWC) + * + * Min value of i_channel, write clear + */ +#define RDC_MIN_I_MIN_MASK (0xFFFFFF00UL) +#define RDC_MIN_I_MIN_SHIFT (8U) +#define RDC_MIN_I_MIN_SET(x) (((uint32_t)(x) << RDC_MIN_I_MIN_SHIFT) & RDC_MIN_I_MIN_MASK) +#define RDC_MIN_I_MIN_GET(x) (((uint32_t)(x) & RDC_MIN_I_MIN_MASK) >> RDC_MIN_I_MIN_SHIFT) + +/* + * VALID (RWC) + * + * Min value valid, write clear + * 0: min value is not valid + * 1: min value is valid + */ +#define RDC_MIN_I_VALID_MASK (0x1U) +#define RDC_MIN_I_VALID_SHIFT (0U) +#define RDC_MIN_I_VALID_SET(x) (((uint32_t)(x) << RDC_MIN_I_VALID_SHIFT) & RDC_MIN_I_VALID_MASK) +#define RDC_MIN_I_VALID_GET(x) (((uint32_t)(x) & RDC_MIN_I_VALID_MASK) >> RDC_MIN_I_VALID_SHIFT) + +/* Bitfield definition for register: MAX_Q */ +/* + * MAX (RWC) + * + * Max value of q_channel, write clear + */ +#define RDC_MAX_Q_MAX_MASK (0xFFFFFF00UL) +#define RDC_MAX_Q_MAX_SHIFT (8U) +#define RDC_MAX_Q_MAX_SET(x) (((uint32_t)(x) << RDC_MAX_Q_MAX_SHIFT) & RDC_MAX_Q_MAX_MASK) +#define RDC_MAX_Q_MAX_GET(x) (((uint32_t)(x) & RDC_MAX_Q_MAX_MASK) >> RDC_MAX_Q_MAX_SHIFT) + +/* + * VALID (RWC) + * + * Max value valid, write clear + * 0: max value is not valid + * 1: max value is valid + */ +#define RDC_MAX_Q_VALID_MASK (0x1U) +#define RDC_MAX_Q_VALID_SHIFT (0U) +#define RDC_MAX_Q_VALID_SET(x) (((uint32_t)(x) << RDC_MAX_Q_VALID_SHIFT) & RDC_MAX_Q_VALID_MASK) +#define RDC_MAX_Q_VALID_GET(x) (((uint32_t)(x) & RDC_MAX_Q_VALID_MASK) >> RDC_MAX_Q_VALID_SHIFT) + +/* Bitfield definition for register: MIN_Q */ +/* + * MIN (RWC) + * + * Min value of q_channel, write clear + */ +#define RDC_MIN_Q_MIN_MASK (0xFFFFFF00UL) +#define RDC_MIN_Q_MIN_SHIFT (8U) +#define RDC_MIN_Q_MIN_SET(x) (((uint32_t)(x) << RDC_MIN_Q_MIN_SHIFT) & RDC_MIN_Q_MIN_MASK) +#define RDC_MIN_Q_MIN_GET(x) (((uint32_t)(x) & RDC_MIN_Q_MIN_MASK) >> RDC_MIN_Q_MIN_SHIFT) + +/* + * VALID (RWC) + * + * Min value valid, write clear + * 0: min value is not valid + * 1: min value is valid + */ +#define RDC_MIN_Q_VALID_MASK (0x1U) +#define RDC_MIN_Q_VALID_SHIFT (0U) +#define RDC_MIN_Q_VALID_SET(x) (((uint32_t)(x) << RDC_MIN_Q_VALID_SHIFT) & RDC_MIN_Q_VALID_MASK) +#define RDC_MIN_Q_VALID_GET(x) (((uint32_t)(x) & RDC_MIN_Q_VALID_MASK) >> RDC_MIN_Q_VALID_SHIFT) + +/* Bitfield definition for register: THRS_I */ +/* + * THRS (RW) + * + * The offset setting for edge detection of the i_channel, signed number + * … + * 2: the offset is 0x800000+2 + * 1: the offset is 0x800000+1 + * 0: the offset is 0x800000 + * -1: the offset is 0x800000-1 + * -2: the offset is 0x800000-2 + * … + */ +#define RDC_THRS_I_THRS_MASK (0xFFFFFF00UL) +#define RDC_THRS_I_THRS_SHIFT (8U) +#define RDC_THRS_I_THRS_SET(x) (((uint32_t)(x) << RDC_THRS_I_THRS_SHIFT) & RDC_THRS_I_THRS_MASK) +#define RDC_THRS_I_THRS_GET(x) (((uint32_t)(x) & RDC_THRS_I_THRS_MASK) >> RDC_THRS_I_THRS_SHIFT) + +/* Bitfield definition for register: THRS_Q */ +/* + * THRS (RW) + * + * The offset setting for edge detection of the q_channel, signed number + * … + * 2: the offset is 0x800000+2 + * 1: the offset is 0x800000+1 + * 0: the offset is 0x800000 + * -1: the offset is 0x800000-1 + * -2: the offset is 0x800000-2 + * … + */ +#define RDC_THRS_Q_THRS_MASK (0xFFFFFF00UL) +#define RDC_THRS_Q_THRS_SHIFT (8U) +#define RDC_THRS_Q_THRS_SET(x) (((uint32_t)(x) << RDC_THRS_Q_THRS_SHIFT) & RDC_THRS_Q_THRS_MASK) +#define RDC_THRS_Q_THRS_GET(x) (((uint32_t)(x) & RDC_THRS_Q_THRS_MASK) >> RDC_THRS_Q_THRS_SHIFT) + +/* Bitfield definition for register: EDG_DET_CTL */ +/* + * HOLD (RW) + * + * The minimum edge distance in sample + * 0:1 sample + * 1:2 sample + * 2:3 samples + * … + * 63:64 samples + */ +#define RDC_EDG_DET_CTL_HOLD_MASK (0x3F0U) +#define RDC_EDG_DET_CTL_HOLD_SHIFT (4U) +#define RDC_EDG_DET_CTL_HOLD_SET(x) (((uint32_t)(x) << RDC_EDG_DET_CTL_HOLD_SHIFT) & RDC_EDG_DET_CTL_HOLD_MASK) +#define RDC_EDG_DET_CTL_HOLD_GET(x) (((uint32_t)(x) & RDC_EDG_DET_CTL_HOLD_MASK) >> RDC_EDG_DET_CTL_HOLD_SHIFT) + +/* + * FILTER (RW) + * + * The continuous positive or negative number for edge detection + * 0: 1 + * 1: 2 + * … + * 7: 8 + */ +#define RDC_EDG_DET_CTL_FILTER_MASK (0x7U) +#define RDC_EDG_DET_CTL_FILTER_SHIFT (0U) +#define RDC_EDG_DET_CTL_FILTER_SET(x) (((uint32_t)(x) << RDC_EDG_DET_CTL_FILTER_SHIFT) & RDC_EDG_DET_CTL_FILTER_MASK) +#define RDC_EDG_DET_CTL_FILTER_GET(x) (((uint32_t)(x) & RDC_EDG_DET_CTL_FILTER_MASK) >> RDC_EDG_DET_CTL_FILTER_SHIFT) + +/* Bitfield definition for register: ACC_SCALING */ +/* + * TOXIC_LK (RW) + * + * Toxic accumulation data be removed control + * 1: enable + * 0: disable + */ +#define RDC_ACC_SCALING_TOXIC_LK_MASK (0x100U) +#define RDC_ACC_SCALING_TOXIC_LK_SHIFT (8U) +#define RDC_ACC_SCALING_TOXIC_LK_SET(x) (((uint32_t)(x) << RDC_ACC_SCALING_TOXIC_LK_SHIFT) & RDC_ACC_SCALING_TOXIC_LK_MASK) +#define RDC_ACC_SCALING_TOXIC_LK_GET(x) (((uint32_t)(x) & RDC_ACC_SCALING_TOXIC_LK_MASK) >> RDC_ACC_SCALING_TOXIC_LK_SHIFT) + +/* + * ACC_SHIFT (RW) + * + * Accumulation value shift control, this is a sign number. + * 0: {acc[39],acc[38:8]} + * 1: {acc[39],acc[37:7]} + * 2: {acc[39],acc[36:6]} + * … + * 7: {acc[39],acc[31:1]} + * 8: {acc[39],acc[30:0]} + * 9: acc/2^9 + * 10: acc/2^10 + * … + * 15:acc/2^15 + */ +#define RDC_ACC_SCALING_ACC_SHIFT_MASK (0xFU) +#define RDC_ACC_SCALING_ACC_SHIFT_SHIFT (0U) +#define RDC_ACC_SCALING_ACC_SHIFT_SET(x) (((uint32_t)(x) << RDC_ACC_SCALING_ACC_SHIFT_SHIFT) & RDC_ACC_SCALING_ACC_SHIFT_MASK) +#define RDC_ACC_SCALING_ACC_SHIFT_GET(x) (((uint32_t)(x) & RDC_ACC_SCALING_ACC_SHIFT_MASK) >> RDC_ACC_SCALING_ACC_SHIFT_SHIFT) + +/* Bitfield definition for register: EXC_PERIOD */ +/* + * EXC_PERIOD (RW) + * + * The num in clock cycle for period of excitation + * 0: invalid value + * 1:1 cycle + * 2:2 cycles + * … + */ +#define RDC_EXC_PERIOD_EXC_PERIOD_MASK (0xFFFFFFFFUL) +#define RDC_EXC_PERIOD_EXC_PERIOD_SHIFT (0U) +#define RDC_EXC_PERIOD_EXC_PERIOD_SET(x) (((uint32_t)(x) << RDC_EXC_PERIOD_EXC_PERIOD_SHIFT) & RDC_EXC_PERIOD_EXC_PERIOD_MASK) +#define RDC_EXC_PERIOD_EXC_PERIOD_GET(x) (((uint32_t)(x) & RDC_EXC_PERIOD_EXC_PERIOD_MASK) >> RDC_EXC_PERIOD_EXC_PERIOD_SHIFT) + +/* Bitfield definition for register: SYNC_DELAY_I */ +/* + * DELAY (RW) + * + * Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. + * 0: invalid value + * 1: 1 cycles + * 2: 2 cycles + * ... + */ +#define RDC_SYNC_DELAY_I_DELAY_MASK (0xFFFFFFFFUL) +#define RDC_SYNC_DELAY_I_DELAY_SHIFT (0U) +#define RDC_SYNC_DELAY_I_DELAY_SET(x) (((uint32_t)(x) << RDC_SYNC_DELAY_I_DELAY_SHIFT) & RDC_SYNC_DELAY_I_DELAY_MASK) +#define RDC_SYNC_DELAY_I_DELAY_GET(x) (((uint32_t)(x) & RDC_SYNC_DELAY_I_DELAY_MASK) >> RDC_SYNC_DELAY_I_DELAY_SHIFT) + +/* Bitfield definition for register: RISE_DELAY_I */ +/* + * RISE_DELAY (RO) + * + * Delay value on rising edge of i_channel data + * 0: 1 cycle + * 1: 2 cycles + * … + */ +#define RDC_RISE_DELAY_I_RISE_DELAY_MASK (0xFFFFFFFFUL) +#define RDC_RISE_DELAY_I_RISE_DELAY_SHIFT (0U) +#define RDC_RISE_DELAY_I_RISE_DELAY_GET(x) (((uint32_t)(x) & RDC_RISE_DELAY_I_RISE_DELAY_MASK) >> RDC_RISE_DELAY_I_RISE_DELAY_SHIFT) + +/* Bitfield definition for register: FALL_DELAY_I */ +/* + * FALL_DELAY (RO) + * + * Delay value on falling edge of i_channel data + * 0: 1 cycle + * 1: 2 cycles + * … + */ +#define RDC_FALL_DELAY_I_FALL_DELAY_MASK (0xFFFFFFFFUL) +#define RDC_FALL_DELAY_I_FALL_DELAY_SHIFT (0U) +#define RDC_FALL_DELAY_I_FALL_DELAY_GET(x) (((uint32_t)(x) & RDC_FALL_DELAY_I_FALL_DELAY_MASK) >> RDC_FALL_DELAY_I_FALL_DELAY_SHIFT) + +/* Bitfield definition for register: SAMPLE_RISE_I */ +/* + * VALUE (RO) + * + * sample value on rising edge of rectify signal + */ +#define RDC_SAMPLE_RISE_I_VALUE_MASK (0xFFFFFF00UL) +#define RDC_SAMPLE_RISE_I_VALUE_SHIFT (8U) +#define RDC_SAMPLE_RISE_I_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_RISE_I_VALUE_MASK) >> RDC_SAMPLE_RISE_I_VALUE_SHIFT) + +/* Bitfield definition for register: SAMPLE_FALL_I */ +/* + * VALUE (RO) + * + * sample value on falling edge of rectify signal + */ +#define RDC_SAMPLE_FALL_I_VALUE_MASK (0xFFFFFF00UL) +#define RDC_SAMPLE_FALL_I_VALUE_SHIFT (8U) +#define RDC_SAMPLE_FALL_I_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_FALL_I_VALUE_MASK) >> RDC_SAMPLE_FALL_I_VALUE_SHIFT) + +/* Bitfield definition for register: ACC_CNT_I */ +/* + * CNT_NEG (RO) + * + * sample number during the negtive of rectify signal + * 1: 1 + * 2: 2 + * … + */ +#define RDC_ACC_CNT_I_CNT_NEG_MASK (0xFFFF0000UL) +#define RDC_ACC_CNT_I_CNT_NEG_SHIFT (16U) +#define RDC_ACC_CNT_I_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_I_CNT_NEG_MASK) >> RDC_ACC_CNT_I_CNT_NEG_SHIFT) + +/* + * CNT_POS (RO) + * + * sample number during the positive of rectify signal + * 1: 1 + * 2: 2 + * … + */ +#define RDC_ACC_CNT_I_CNT_POS_MASK (0xFFFFU) +#define RDC_ACC_CNT_I_CNT_POS_SHIFT (0U) +#define RDC_ACC_CNT_I_CNT_POS_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_I_CNT_POS_MASK) >> RDC_ACC_CNT_I_CNT_POS_SHIFT) + +/* Bitfield definition for register: SIGN_CNT_I */ +/* + * CNT_NEG (RO) + * + * Positive sample counter during negative rectify signal + */ +#define RDC_SIGN_CNT_I_CNT_NEG_MASK (0xFFFF0000UL) +#define RDC_SIGN_CNT_I_CNT_NEG_SHIFT (16U) +#define RDC_SIGN_CNT_I_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_I_CNT_NEG_MASK) >> RDC_SIGN_CNT_I_CNT_NEG_SHIFT) + +/* + * CNT_POS (RO) + * + * Negative sample counter during positive rectify signal + */ +#define RDC_SIGN_CNT_I_CNT_POS_MASK (0xFFFFU) +#define RDC_SIGN_CNT_I_CNT_POS_SHIFT (0U) +#define RDC_SIGN_CNT_I_CNT_POS_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_I_CNT_POS_MASK) >> RDC_SIGN_CNT_I_CNT_POS_SHIFT) + +/* Bitfield definition for register: SYNC_DELAY_Q */ +/* + * DELAY (RW) + * + * Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. + * 0: invalid value + * 1: 1 cycles + * 2: 2 cycles + * ... + */ +#define RDC_SYNC_DELAY_Q_DELAY_MASK (0xFFFFFFFFUL) +#define RDC_SYNC_DELAY_Q_DELAY_SHIFT (0U) +#define RDC_SYNC_DELAY_Q_DELAY_SET(x) (((uint32_t)(x) << RDC_SYNC_DELAY_Q_DELAY_SHIFT) & RDC_SYNC_DELAY_Q_DELAY_MASK) +#define RDC_SYNC_DELAY_Q_DELAY_GET(x) (((uint32_t)(x) & RDC_SYNC_DELAY_Q_DELAY_MASK) >> RDC_SYNC_DELAY_Q_DELAY_SHIFT) + +/* Bitfield definition for register: RISE_DELAY_Q */ +/* + * RISE_DELAY (RO) + * + * Delay value on rising edge of q_channel data + * 0: 1 cycle + * 1: 2 cycles + * … + */ +#define RDC_RISE_DELAY_Q_RISE_DELAY_MASK (0xFFFFFFFFUL) +#define RDC_RISE_DELAY_Q_RISE_DELAY_SHIFT (0U) +#define RDC_RISE_DELAY_Q_RISE_DELAY_GET(x) (((uint32_t)(x) & RDC_RISE_DELAY_Q_RISE_DELAY_MASK) >> RDC_RISE_DELAY_Q_RISE_DELAY_SHIFT) + +/* Bitfield definition for register: FALL_DELAY_Q */ +/* + * FALL_DELAY (RO) + * + * Delay value on falling edge of q_channel data + * 0: 1 cycle + * 1: 2 cycles + * … + */ +#define RDC_FALL_DELAY_Q_FALL_DELAY_MASK (0xFFFFFFFFUL) +#define RDC_FALL_DELAY_Q_FALL_DELAY_SHIFT (0U) +#define RDC_FALL_DELAY_Q_FALL_DELAY_GET(x) (((uint32_t)(x) & RDC_FALL_DELAY_Q_FALL_DELAY_MASK) >> RDC_FALL_DELAY_Q_FALL_DELAY_SHIFT) + +/* Bitfield definition for register: SAMPLE_RISE_Q */ +/* + * VALUE (RO) + * + * sample value on rising edge of rectify signal + */ +#define RDC_SAMPLE_RISE_Q_VALUE_MASK (0xFFFFFF00UL) +#define RDC_SAMPLE_RISE_Q_VALUE_SHIFT (8U) +#define RDC_SAMPLE_RISE_Q_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_RISE_Q_VALUE_MASK) >> RDC_SAMPLE_RISE_Q_VALUE_SHIFT) + +/* Bitfield definition for register: SAMPLE_FALL_Q */ +/* + * VALUE (RO) + * + * sample value on falling edge of rectify signal + */ +#define RDC_SAMPLE_FALL_Q_VALUE_MASK (0xFFFFFF00UL) +#define RDC_SAMPLE_FALL_Q_VALUE_SHIFT (8U) +#define RDC_SAMPLE_FALL_Q_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_FALL_Q_VALUE_MASK) >> RDC_SAMPLE_FALL_Q_VALUE_SHIFT) + +/* Bitfield definition for register: ACC_CNT_Q */ +/* + * CNT_NEG (RO) + * + * sample number during the negtive of rectify signal + * 1: 1 + * 2: 2 + * … + */ +#define RDC_ACC_CNT_Q_CNT_NEG_MASK (0xFFFF0000UL) +#define RDC_ACC_CNT_Q_CNT_NEG_SHIFT (16U) +#define RDC_ACC_CNT_Q_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_Q_CNT_NEG_MASK) >> RDC_ACC_CNT_Q_CNT_NEG_SHIFT) + +/* + * CNT_POS (RO) + * + * sample number during the positive of rectify signal + * 1: 1 + * 2: 2 + * … + */ +#define RDC_ACC_CNT_Q_CNT_POS_MASK (0xFFFFU) +#define RDC_ACC_CNT_Q_CNT_POS_SHIFT (0U) +#define RDC_ACC_CNT_Q_CNT_POS_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_Q_CNT_POS_MASK) >> RDC_ACC_CNT_Q_CNT_POS_SHIFT) + +/* Bitfield definition for register: SIGN_CNT_Q */ +/* + * CNT_NEG (RO) + * + * Positive sample counter during negative rectify signal + */ +#define RDC_SIGN_CNT_Q_CNT_NEG_MASK (0xFFFF0000UL) +#define RDC_SIGN_CNT_Q_CNT_NEG_SHIFT (16U) +#define RDC_SIGN_CNT_Q_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_Q_CNT_NEG_MASK) >> RDC_SIGN_CNT_Q_CNT_NEG_SHIFT) + +/* + * CNT_POS (RO) + * + * Negative sample counter during positive rectify signal + */ +#define RDC_SIGN_CNT_Q_CNT_POS_MASK (0xFFFFU) +#define RDC_SIGN_CNT_Q_CNT_POS_SHIFT (0U) +#define RDC_SIGN_CNT_Q_CNT_POS_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_Q_CNT_POS_MASK) >> RDC_SIGN_CNT_Q_CNT_POS_SHIFT) + +/* Bitfield definition for register: AMP_MAX */ +/* + * MAX (RW) + * + * the maximum of acc amplitude + */ +#define RDC_AMP_MAX_MAX_MASK (0xFFFFFFFFUL) +#define RDC_AMP_MAX_MAX_SHIFT (0U) +#define RDC_AMP_MAX_MAX_SET(x) (((uint32_t)(x) << RDC_AMP_MAX_MAX_SHIFT) & RDC_AMP_MAX_MAX_MASK) +#define RDC_AMP_MAX_MAX_GET(x) (((uint32_t)(x) & RDC_AMP_MAX_MAX_MASK) >> RDC_AMP_MAX_MAX_SHIFT) + +/* Bitfield definition for register: AMP_MIN */ +/* + * MIN (RW) + * + * the minimum of acc amplitude + */ +#define RDC_AMP_MIN_MIN_MASK (0xFFFFFFFFUL) +#define RDC_AMP_MIN_MIN_SHIFT (0U) +#define RDC_AMP_MIN_MIN_SET(x) (((uint32_t)(x) << RDC_AMP_MIN_MIN_SHIFT) & RDC_AMP_MIN_MIN_MASK) +#define RDC_AMP_MIN_MIN_GET(x) (((uint32_t)(x) & RDC_AMP_MIN_MIN_MASK) >> RDC_AMP_MIN_MIN_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * INT_EN (RW) + * + * enable interrupt output + */ +#define RDC_INT_EN_INT_EN_MASK (0x80000000UL) +#define RDC_INT_EN_INT_EN_SHIFT (31U) +#define RDC_INT_EN_INT_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_INT_EN_SHIFT) & RDC_INT_EN_INT_EN_MASK) +#define RDC_INT_EN_INT_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_INT_EN_MASK) >> RDC_INT_EN_INT_EN_SHIFT) + +/* + * ACC_VLD_I_EN (RW) + * + * i_channel accumulate valid interrupt enable for i_channel + */ +#define RDC_INT_EN_ACC_VLD_I_EN_MASK (0x8000U) +#define RDC_INT_EN_ACC_VLD_I_EN_SHIFT (15U) +#define RDC_INT_EN_ACC_VLD_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_EN_MASK) +#define RDC_INT_EN_ACC_VLD_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_EN_SHIFT) + +/* + * ACC_VLD_Q_EN (RW) + * + * q_channel accumulate valid interrupt enable for i_channel + */ +#define RDC_INT_EN_ACC_VLD_Q_EN_MASK (0x4000U) +#define RDC_INT_EN_ACC_VLD_Q_EN_SHIFT (14U) +#define RDC_INT_EN_ACC_VLD_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_EN_MASK) +#define RDC_INT_EN_ACC_VLD_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_EN_SHIFT) + +/* + * RISING_DELAY_I_EN (RW) + * + * i_channel delayed rectify signal rising edge interrupt enable + */ +#define RDC_INT_EN_RISING_DELAY_I_EN_MASK (0x2000U) +#define RDC_INT_EN_RISING_DELAY_I_EN_SHIFT (13U) +#define RDC_INT_EN_RISING_DELAY_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_RISING_DELAY_I_EN_SHIFT) & RDC_INT_EN_RISING_DELAY_I_EN_MASK) +#define RDC_INT_EN_RISING_DELAY_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_RISING_DELAY_I_EN_MASK) >> RDC_INT_EN_RISING_DELAY_I_EN_SHIFT) + +/* + * FALLING_DELAY_I_EN (RW) + * + * i_channel delayed rectify signal falling edge interrupt enable + */ +#define RDC_INT_EN_FALLING_DELAY_I_EN_MASK (0x1000U) +#define RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT (12U) +#define RDC_INT_EN_FALLING_DELAY_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT) & RDC_INT_EN_FALLING_DELAY_I_EN_MASK) +#define RDC_INT_EN_FALLING_DELAY_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_FALLING_DELAY_I_EN_MASK) >> RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT) + +/* + * RISING_DELAY_Q_EN (RW) + * + * q_channel delayed rectify signal rising edge interrupt enable + */ +#define RDC_INT_EN_RISING_DELAY_Q_EN_MASK (0x800U) +#define RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT (11U) +#define RDC_INT_EN_RISING_DELAY_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT) & RDC_INT_EN_RISING_DELAY_Q_EN_MASK) +#define RDC_INT_EN_RISING_DELAY_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_RISING_DELAY_Q_EN_MASK) >> RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT) + +/* + * FALLING_DELAY_Q_EN (RW) + * + * q_channel delayed rectify signal falling edge interrupt enable + */ +#define RDC_INT_EN_FALLING_DELAY_Q_EN_MASK (0x400U) +#define RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT (10U) +#define RDC_INT_EN_FALLING_DELAY_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT) & RDC_INT_EN_FALLING_DELAY_Q_EN_MASK) +#define RDC_INT_EN_FALLING_DELAY_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_FALLING_DELAY_Q_EN_MASK) >> RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT) + +/* + * SAMPLE_RISING_I_EN (RW) + * + * i_channel rising edge interrupt enable + */ +#define RDC_INT_EN_SAMPLE_RISING_I_EN_MASK (0x200U) +#define RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT (9U) +#define RDC_INT_EN_SAMPLE_RISING_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT) & RDC_INT_EN_SAMPLE_RISING_I_EN_MASK) +#define RDC_INT_EN_SAMPLE_RISING_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_RISING_I_EN_MASK) >> RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT) + +/* + * SAMPLE_FALLING_I_EN (RW) + * + * i_channel falling edge interrupt enable + */ +#define RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK (0x100U) +#define RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT (8U) +#define RDC_INT_EN_SAMPLE_FALLING_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT) & RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK) +#define RDC_INT_EN_SAMPLE_FALLING_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK) >> RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT) + +/* + * SAMPLE_RISING_Q_EN (RW) + * + * q_channel rising edge interrupt enable + */ +#define RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK (0x80U) +#define RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT (7U) +#define RDC_INT_EN_SAMPLE_RISING_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT) & RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK) +#define RDC_INT_EN_SAMPLE_RISING_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK) >> RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT) + +/* + * SAMPLE_FALLING_Q_EN (RW) + * + * q_channel falling edge interrupt enable + */ +#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK (0x40U) +#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT (6U) +#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT) & RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK) +#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK) >> RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT) + +/* + * ACC_VLD_I_OVH_EN (RW) + * + * i_channel accumulate overflow interrupt enable + */ +#define RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK (0x20U) +#define RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT (5U) +#define RDC_INT_EN_ACC_VLD_I_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK) +#define RDC_INT_EN_ACC_VLD_I_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT) + +/* + * ACC_VLD_Q_OVH_EN (RW) + * + * q_channel accumulate overflow interrupt enable + */ +#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK (0x10U) +#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT (4U) +#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK) +#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT) + +/* + * ACC_VLD_I_OVL_EN (RW) + * + * i_channel accumulate underflow interrupt enable + */ +#define RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK (0x8U) +#define RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT (3U) +#define RDC_INT_EN_ACC_VLD_I_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK) +#define RDC_INT_EN_ACC_VLD_I_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT) + +/* + * ACC_VLD_Q_OVL_EN (RW) + * + * q_channel accumulate underflow interrupt enable + */ +#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK (0x4U) +#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT (2U) +#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK) +#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT) + +/* + * ACC_AMP_OVH_EN (RW) + * + * accumulate ample overflow interrupt enable + */ +#define RDC_INT_EN_ACC_AMP_OVH_EN_MASK (0x2U) +#define RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT (1U) +#define RDC_INT_EN_ACC_AMP_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT) & RDC_INT_EN_ACC_AMP_OVH_EN_MASK) +#define RDC_INT_EN_ACC_AMP_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_AMP_OVH_EN_MASK) >> RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT) + +/* + * ACC_AMP_OVL_EN (RW) + * + * accumulate ample underflow interrupt enable + */ +#define RDC_INT_EN_ACC_AMP_OVL_EN_MASK (0x1U) +#define RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT (0U) +#define RDC_INT_EN_ACC_AMP_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT) & RDC_INT_EN_ACC_AMP_OVL_EN_MASK) +#define RDC_INT_EN_ACC_AMP_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_AMP_OVL_EN_MASK) >> RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT) + +/* Bitfield definition for register: ADC_INT_STATE */ +/* + * ACC_VLD_I_STA (W1C) + * + * i_channel accumulate valid interrupt status for i_channel + */ +#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK (0x8000U) +#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT (15U) +#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT) + +/* + * ACC_VLD_Q_STA (W1C) + * + * q_channel accumulate valid interrupt status for i_channel + */ +#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK (0x4000U) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT (14U) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT) + +/* + * RISING_DELAY_I_STA (W1C) + * + * i_channel delayed rectify signal rising edge interrupt status + */ +#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK (0x2000U) +#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT (13U) +#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT) & RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK) +#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK) >> RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT) + +/* + * FALLING_DELAY_I_STA (W1C) + * + * i_channel delayed rectify signal falling edge interrupt status + */ +#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK (0x1000U) +#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT (12U) +#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT) & RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK) +#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK) >> RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT) + +/* + * RISING_DELAY_Q_STA (W1C) + * + * q_channel delayed rectify signal rising edge interrupt status + */ +#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK (0x800U) +#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT (11U) +#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT) & RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK) +#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK) >> RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT) + +/* + * FALLING_DELAY_Q_STA (W1C) + * + * q_channel delayed rectify signal falling edge interrupt status + */ +#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK (0x400U) +#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT (10U) +#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT) & RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK) +#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK) >> RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT) + +/* + * SAMPLE_RISING_I_STA (W1C) + * + * i_channel rising edge interrupt status + */ +#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK (0x200U) +#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT (9U) +#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK) +#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT) + +/* + * SAMPLE_FALLING_I_STA (W1C) + * + * i_channel falling edge interrupt status + */ +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK (0x100U) +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT (8U) +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK) +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT) + +/* + * SAMPLE_RISING_Q_STA (W1C) + * + * q_channel rising edge interrupt status + */ +#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK (0x80U) +#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT (7U) +#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK) +#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT) + +/* + * SAMPLE_FALLING_Q_STA (W1C) + * + * q_channel falling edge interrupt status + */ +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK (0x40U) +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT (6U) +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK) +#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT) + +/* + * ACC_VLD_I_OVH_STA (W1C) + * + * i_channel accumulate overflow interrupt status + */ +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK (0x20U) +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT (5U) +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT) + +/* + * ACC_VLD_Q_OVH_STA (W1C) + * + * q_channel accumulate overflow interrupt status + */ +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK (0x10U) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT (4U) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT) + +/* + * ACC_VLD_I_OVL_STA (W1C) + * + * i_channel accumulate underflow interrupt status + */ +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK (0x8U) +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT (3U) +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT) + +/* + * ACC_VLD_Q_OVL_STA (W1C) + * + * q_channel accumulate underflow interrupt status + */ +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK (0x4U) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT (2U) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT) + +/* + * ACC_AMP_OVH_STA (W1C) + * + * accumulate ample overflow interrupt status + */ +#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK (0x2U) +#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT (1U) +#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT) + +/* + * ACC_AMP_OVL_STA (W1C) + * + * accumulate ample underflow interrupt status + */ +#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK (0x1U) +#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT (0U) +#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK) +#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT) + + + + +#endif /* HPM_RDC_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_sdadc_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_sdadc_regs.h new file mode 100644 index 00000000..f855f124 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_sdadc_regs.h @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SDADC_H +#define HPM_SDADC_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: SDADC control register */ + __RW uint32_t CLK_DIV; /* 0x4: clock divider */ + __RW uint32_t TTB; /* 0x8: Total Transfer Bits */ + __RW uint32_t START_OP; /* 0xC: Start_Of_Operation */ + __RW uint32_t MISC; /* 0x10: Misc Control */ + __R uint32_t ST; /* 0x14: Status Register */ +} SDADC_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * SDM_CFG (RW) + * + * SDM analog part Configuration + */ +#define SDADC_CTRL_SDM_CFG_MASK (0xFF00000UL) +#define SDADC_CTRL_SDM_CFG_SHIFT (20U) +#define SDADC_CTRL_SDM_CFG_SET(x) (((uint32_t)(x) << SDADC_CTRL_SDM_CFG_SHIFT) & SDADC_CTRL_SDM_CFG_MASK) +#define SDADC_CTRL_SDM_CFG_GET(x) (((uint32_t)(x) & SDADC_CTRL_SDM_CFG_MASK) >> SDADC_CTRL_SDM_CFG_SHIFT) + +/* + * SDM_PGA_CE_SEL (RW) + * + * SDM_PGA_CE_SEL + */ +#define SDADC_CTRL_SDM_PGA_CE_SEL_MASK (0xC0000UL) +#define SDADC_CTRL_SDM_PGA_CE_SEL_SHIFT (18U) +#define SDADC_CTRL_SDM_PGA_CE_SEL_SET(x) (((uint32_t)(x) << SDADC_CTRL_SDM_PGA_CE_SEL_SHIFT) & SDADC_CTRL_SDM_PGA_CE_SEL_MASK) +#define SDADC_CTRL_SDM_PGA_CE_SEL_GET(x) (((uint32_t)(x) & SDADC_CTRL_SDM_PGA_CE_SEL_MASK) >> SDADC_CTRL_SDM_PGA_CE_SEL_SHIFT) + +/* + * SDM_PGA_CH_SEL (RW) + * + * SDM_PGA_CH_SEL + */ +#define SDADC_CTRL_SDM_PGA_CH_SEL_MASK (0x3C000UL) +#define SDADC_CTRL_SDM_PGA_CH_SEL_SHIFT (14U) +#define SDADC_CTRL_SDM_PGA_CH_SEL_SET(x) (((uint32_t)(x) << SDADC_CTRL_SDM_PGA_CH_SEL_SHIFT) & SDADC_CTRL_SDM_PGA_CH_SEL_MASK) +#define SDADC_CTRL_SDM_PGA_CH_SEL_GET(x) (((uint32_t)(x) & SDADC_CTRL_SDM_PGA_CH_SEL_MASK) >> SDADC_CTRL_SDM_PGA_CH_SEL_SHIFT) + +/* + * CFG_CDS_CMD (RW) + * + * config the common mode voltage of CDS CAP + */ +#define SDADC_CTRL_CFG_CDS_CMD_MASK (0x2000U) +#define SDADC_CTRL_CFG_CDS_CMD_SHIFT (13U) +#define SDADC_CTRL_CFG_CDS_CMD_SET(x) (((uint32_t)(x) << SDADC_CTRL_CFG_CDS_CMD_SHIFT) & SDADC_CTRL_CFG_CDS_CMD_MASK) +#define SDADC_CTRL_CFG_CDS_CMD_GET(x) (((uint32_t)(x) & SDADC_CTRL_CFG_CDS_CMD_MASK) >> SDADC_CTRL_CFG_CDS_CMD_SHIFT) + +/* + * LP_MODE_SDM (RW) + * + * lowpower mode of SDM + */ +#define SDADC_CTRL_LP_MODE_SDM_MASK (0xE00U) +#define SDADC_CTRL_LP_MODE_SDM_SHIFT (9U) +#define SDADC_CTRL_LP_MODE_SDM_SET(x) (((uint32_t)(x) << SDADC_CTRL_LP_MODE_SDM_SHIFT) & SDADC_CTRL_LP_MODE_SDM_MASK) +#define SDADC_CTRL_LP_MODE_SDM_GET(x) (((uint32_t)(x) & SDADC_CTRL_LP_MODE_SDM_MASK) >> SDADC_CTRL_LP_MODE_SDM_SHIFT) + +/* + * LP_MODE_PGA (RW) + * + * lowpower mode of PGA + */ +#define SDADC_CTRL_LP_MODE_PGA_MASK (0x1C0U) +#define SDADC_CTRL_LP_MODE_PGA_SHIFT (6U) +#define SDADC_CTRL_LP_MODE_PGA_SET(x) (((uint32_t)(x) << SDADC_CTRL_LP_MODE_PGA_SHIFT) & SDADC_CTRL_LP_MODE_PGA_MASK) +#define SDADC_CTRL_LP_MODE_PGA_GET(x) (((uint32_t)(x) & SDADC_CTRL_LP_MODE_PGA_MASK) >> SDADC_CTRL_LP_MODE_PGA_SHIFT) + +/* + * ANA_PWUP (RW) + * + * 1. Asserted to power up the analog part + * 0: Shut off the power for the analog part + */ +#define SDADC_CTRL_ANA_PWUP_MASK (0x20U) +#define SDADC_CTRL_ANA_PWUP_SHIFT (5U) +#define SDADC_CTRL_ANA_PWUP_SET(x) (((uint32_t)(x) << SDADC_CTRL_ANA_PWUP_SHIFT) & SDADC_CTRL_ANA_PWUP_MASK) +#define SDADC_CTRL_ANA_PWUP_GET(x) (((uint32_t)(x) & SDADC_CTRL_ANA_PWUP_MASK) >> SDADC_CTRL_ANA_PWUP_SHIFT) + +/* + * BYPASS_PGA (RW) + * + * 1: PGA is bypassed + * 0: PGA is enabled + */ +#define SDADC_CTRL_BYPASS_PGA_MASK (0x10U) +#define SDADC_CTRL_BYPASS_PGA_SHIFT (4U) +#define SDADC_CTRL_BYPASS_PGA_SET(x) (((uint32_t)(x) << SDADC_CTRL_BYPASS_PGA_SHIFT) & SDADC_CTRL_BYPASS_PGA_MASK) +#define SDADC_CTRL_BYPASS_PGA_GET(x) (((uint32_t)(x) & SDADC_CTRL_BYPASS_PGA_MASK) >> SDADC_CTRL_BYPASS_PGA_SHIFT) + +/* + * CONT_MODE (RW) + * + * 1: continuous mode of ADC conversion + * 0: burst mode of ADC conversion. + */ +#define SDADC_CTRL_CONT_MODE_MASK (0x8U) +#define SDADC_CTRL_CONT_MODE_SHIFT (3U) +#define SDADC_CTRL_CONT_MODE_SET(x) (((uint32_t)(x) << SDADC_CTRL_CONT_MODE_SHIFT) & SDADC_CTRL_CONT_MODE_MASK) +#define SDADC_CTRL_CONT_MODE_GET(x) (((uint32_t)(x) & SDADC_CTRL_CONT_MODE_MASK) >> SDADC_CTRL_CONT_MODE_SHIFT) + +/* + * RST_SDM (RW) + * + * 1: reset SDM. Should be de-asserted by software + * 0: no reset SDM + */ +#define SDADC_CTRL_RST_SDM_MASK (0x4U) +#define SDADC_CTRL_RST_SDM_SHIFT (2U) +#define SDADC_CTRL_RST_SDM_SET(x) (((uint32_t)(x) << SDADC_CTRL_RST_SDM_SHIFT) & SDADC_CTRL_RST_SDM_MASK) +#define SDADC_CTRL_RST_SDM_GET(x) (((uint32_t)(x) & SDADC_CTRL_RST_SDM_MASK) >> SDADC_CTRL_RST_SDM_SHIFT) + +/* + * RST_PGA (RW) + * + * 1: reset PGA. Should be de-asserted by software + * 0: no reset PGA + */ +#define SDADC_CTRL_RST_PGA_MASK (0x2U) +#define SDADC_CTRL_RST_PGA_SHIFT (1U) +#define SDADC_CTRL_RST_PGA_SET(x) (((uint32_t)(x) << SDADC_CTRL_RST_PGA_SHIFT) & SDADC_CTRL_RST_PGA_MASK) +#define SDADC_CTRL_RST_PGA_GET(x) (((uint32_t)(x) & SDADC_CTRL_RST_PGA_MASK) >> SDADC_CTRL_RST_PGA_SHIFT) + +/* + * EN (RW) + * + * Module enable, to enable clok divder. Etc + */ +#define SDADC_CTRL_EN_MASK (0x1U) +#define SDADC_CTRL_EN_SHIFT (0U) +#define SDADC_CTRL_EN_SET(x) (((uint32_t)(x) << SDADC_CTRL_EN_SHIFT) & SDADC_CTRL_EN_MASK) +#define SDADC_CTRL_EN_GET(x) (((uint32_t)(x) & SDADC_CTRL_EN_MASK) >> SDADC_CTRL_EN_SHIFT) + +/* Bitfield definition for register: CLK_DIV */ +/* + * FACTOR (RW) + * + * 0: disable clock output + * 1: bypass the clock divider + * 2: divide the clock by 2 + * … + * n: divide the clock by n + */ +#define SDADC_CLK_DIV_FACTOR_MASK (0xFFU) +#define SDADC_CLK_DIV_FACTOR_SHIFT (0U) +#define SDADC_CLK_DIV_FACTOR_SET(x) (((uint32_t)(x) << SDADC_CLK_DIV_FACTOR_SHIFT) & SDADC_CLK_DIV_FACTOR_MASK) +#define SDADC_CLK_DIV_FACTOR_GET(x) (((uint32_t)(x) & SDADC_CLK_DIV_FACTOR_MASK) >> SDADC_CLK_DIV_FACTOR_SHIFT) + +/* Bitfield definition for register: TTB */ +/* + * VAL (RW) + * + * the maximal number of output bits when ADC is in burst mode + */ +#define SDADC_TTB_VAL_MASK (0xFFFFFUL) +#define SDADC_TTB_VAL_SHIFT (0U) +#define SDADC_TTB_VAL_SET(x) (((uint32_t)(x) << SDADC_TTB_VAL_SHIFT) & SDADC_TTB_VAL_MASK) +#define SDADC_TTB_VAL_GET(x) (((uint32_t)(x) & SDADC_TTB_VAL_MASK) >> SDADC_TTB_VAL_SHIFT) + +/* Bitfield definition for register: START_OP */ +/* + * SDM_EN (RW) + * + * 1. Enable sigma-delta ADC. Auto clear in burst mode when TTB bits are received. In cont mode, must be cleared manually. + * 0: disable sigma-delta ADC + */ +#define SDADC_START_OP_SDM_EN_MASK (0x1U) +#define SDADC_START_OP_SDM_EN_SHIFT (0U) +#define SDADC_START_OP_SDM_EN_SET(x) (((uint32_t)(x) << SDADC_START_OP_SDM_EN_SHIFT) & SDADC_START_OP_SDM_EN_MASK) +#define SDADC_START_OP_SDM_EN_GET(x) (((uint32_t)(x) & SDADC_START_OP_SDM_EN_MASK) >> SDADC_START_OP_SDM_EN_SHIFT) + +/* Bitfield definition for register: MISC */ +/* + * BURST_DONE_IE (RW) + * + * Asserted to enable BURST_DONE event interrupt. Should not be asserted for continuous mode. + */ +#define SDADC_MISC_BURST_DONE_IE_MASK (0x2U) +#define SDADC_MISC_BURST_DONE_IE_SHIFT (1U) +#define SDADC_MISC_BURST_DONE_IE_SET(x) (((uint32_t)(x) << SDADC_MISC_BURST_DONE_IE_SHIFT) & SDADC_MISC_BURST_DONE_IE_MASK) +#define SDADC_MISC_BURST_DONE_IE_GET(x) (((uint32_t)(x) & SDADC_MISC_BURST_DONE_IE_MASK) >> SDADC_MISC_BURST_DONE_IE_SHIFT) + +/* + * PDM_CLK_SEL (RW) + * + * Asserted to use PDM clk input. Default to use MCLK which is directly from PLL. + */ +#define SDADC_MISC_PDM_CLK_SEL_MASK (0x1U) +#define SDADC_MISC_PDM_CLK_SEL_SHIFT (0U) +#define SDADC_MISC_PDM_CLK_SEL_SET(x) (((uint32_t)(x) << SDADC_MISC_PDM_CLK_SEL_SHIFT) & SDADC_MISC_PDM_CLK_SEL_MASK) +#define SDADC_MISC_PDM_CLK_SEL_GET(x) (((uint32_t)(x) & SDADC_MISC_PDM_CLK_SEL_MASK) >> SDADC_MISC_PDM_CLK_SEL_SHIFT) + +/* Bitfield definition for register: ST */ +/* + * ANA_RST (RO) + * + * Asserted when analog module is in reset mode. + */ +#define SDADC_ST_ANA_RST_MASK (0x4U) +#define SDADC_ST_ANA_RST_SHIFT (2U) +#define SDADC_ST_ANA_RST_GET(x) (((uint32_t)(x) & SDADC_ST_ANA_RST_MASK) >> SDADC_ST_ANA_RST_SHIFT) + +/* + * DIV_STABLE (RO) + * + * Asserted when CLK_DIV reaches stable status. Cleared automatically when CLK_DIV[FACTOR] is assigned a different value. + */ +#define SDADC_ST_DIV_STABLE_MASK (0x2U) +#define SDADC_ST_DIV_STABLE_SHIFT (1U) +#define SDADC_ST_DIV_STABLE_GET(x) (((uint32_t)(x) & SDADC_ST_DIV_STABLE_MASK) >> SDADC_ST_DIV_STABLE_SHIFT) + +/* + * BURST_DONE (RO) + * + * Asserted when burst transfer is done. Auto cleared after the ST register is read while this bit is asserted. + */ +#define SDADC_ST_BURST_DONE_MASK (0x1U) +#define SDADC_ST_BURST_DONE_SHIFT (0U) +#define SDADC_ST_BURST_DONE_GET(x) (((uint32_t)(x) & SDADC_ST_BURST_DONE_MASK) >> SDADC_ST_BURST_DONE_SHIFT) + + + + +#endif /* HPM_SDADC_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_sdmv2_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_sdmv2_regs.h new file mode 100644 index 00000000..d5ab6d23 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_sdmv2_regs.h @@ -0,0 +1,692 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SDMV2_H +#define HPM_SDMV2_H + +typedef struct { + __RW uint32_t CTRL; /* 0x0: SDM control register */ + __RW uint32_t INT_EN; /* 0x4: Interrupt enable register. */ + __R uint32_t STATUS; /* 0x8: Status Registers */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + struct { + __RW uint32_t SDFIFOCTRL; /* 0x10: Data FIFO Path Control Register */ + __RW uint32_t SDCTRLP; /* 0x14: Data Path Control Primary Register */ + __RW uint32_t SDCTRLE; /* 0x18: Data Path Control Extra Register */ + __RW uint32_t SDST; /* 0x1C: Data Path Status */ + __R uint32_t SDATA; /* 0x20: Data */ + __R uint32_t SDFIFO; /* 0x24: FIFO Data */ + __R uint32_t SCAMP; /* 0x28: instant Amplitude Results */ + __RW uint32_t SCHTL; /* 0x2C: Amplitude Threshold for High Limit */ + __RW uint32_t SCHTLZ; /* 0x30: Amplitude Threshold for zero crossing */ + __RW uint32_t SCLLT; /* 0x34: Amplitude Threshold for low limit */ + __RW uint32_t SCCTRL; /* 0x38: Amplitude Path Control */ + __RW uint32_t SCST; /* 0x3C: Amplitude Path Status */ + __R uint8_t RESERVED0[16]; /* 0x40 - 0x4F: Reserved */ + } CH[1]; +} SDMV2_Type; + + +/* Bitfield definition for register: CTRL */ +/* + * SFTRST (RW) + * + * software reset the module if asserted to be1’b1. + */ +#define SDMV2_CTRL_SFTRST_MASK (0x80000000UL) +#define SDMV2_CTRL_SFTRST_SHIFT (31U) +#define SDMV2_CTRL_SFTRST_SET(x) (((uint32_t)(x) << SDMV2_CTRL_SFTRST_SHIFT) & SDMV2_CTRL_SFTRST_MASK) +#define SDMV2_CTRL_SFTRST_GET(x) (((uint32_t)(x) & SDMV2_CTRL_SFTRST_MASK) >> SDMV2_CTRL_SFTRST_SHIFT) + +/* + * CHMD (RW) + * + * Channel Rcv mode + * Bits[2:0] for Ch0. + * Bits[5:3] for Ch1 + * Bits[8:6] for Ch2 + * Bits[11:9] for Ch3 + * 3'b000: Capture at posedge of MCLK + * 3'b001: Capture at both posedge and negedge of MCLK + * 3'b010: Manchestor Mode + * 3'b011: Capture at negedge of MCLK + * 3'b100: Capture at every other posedge of MCLK + * 3'b101: Capture at every other negedge of MCLK + * Others: Undefined + */ +#define SDMV2_CTRL_CHMD_MASK (0x3FFC000UL) +#define SDMV2_CTRL_CHMD_SHIFT (14U) +#define SDMV2_CTRL_CHMD_SET(x) (((uint32_t)(x) << SDMV2_CTRL_CHMD_SHIFT) & SDMV2_CTRL_CHMD_MASK) +#define SDMV2_CTRL_CHMD_GET(x) (((uint32_t)(x) & SDMV2_CTRL_CHMD_MASK) >> SDMV2_CTRL_CHMD_SHIFT) + +/* + * SYNC_MCLK (RW) + * + * Asserted to double sync the mclk input pin before its usage inside the module + */ +#define SDMV2_CTRL_SYNC_MCLK_MASK (0x3C00U) +#define SDMV2_CTRL_SYNC_MCLK_SHIFT (10U) +#define SDMV2_CTRL_SYNC_MCLK_SET(x) (((uint32_t)(x) << SDMV2_CTRL_SYNC_MCLK_SHIFT) & SDMV2_CTRL_SYNC_MCLK_MASK) +#define SDMV2_CTRL_SYNC_MCLK_GET(x) (((uint32_t)(x) & SDMV2_CTRL_SYNC_MCLK_MASK) >> SDMV2_CTRL_SYNC_MCLK_SHIFT) + +/* + * SYNC_MDAT (RW) + * + * Asserted to double sync the mdat input pin before its usage inside the module + */ +#define SDMV2_CTRL_SYNC_MDAT_MASK (0x3C0U) +#define SDMV2_CTRL_SYNC_MDAT_SHIFT (6U) +#define SDMV2_CTRL_SYNC_MDAT_SET(x) (((uint32_t)(x) << SDMV2_CTRL_SYNC_MDAT_SHIFT) & SDMV2_CTRL_SYNC_MDAT_MASK) +#define SDMV2_CTRL_SYNC_MDAT_GET(x) (((uint32_t)(x) & SDMV2_CTRL_SYNC_MDAT_MASK) >> SDMV2_CTRL_SYNC_MDAT_SHIFT) + +/* + * CH_EN (RW) + * + * Channel Enable + */ +#define SDMV2_CTRL_CH_EN_MASK (0x3CU) +#define SDMV2_CTRL_CH_EN_SHIFT (2U) +#define SDMV2_CTRL_CH_EN_SET(x) (((uint32_t)(x) << SDMV2_CTRL_CH_EN_SHIFT) & SDMV2_CTRL_CH_EN_MASK) +#define SDMV2_CTRL_CH_EN_GET(x) (((uint32_t)(x) & SDMV2_CTRL_CH_EN_MASK) >> SDMV2_CTRL_CH_EN_SHIFT) + +/* + * IE (RW) + * + * Interrupt Enable + */ +#define SDMV2_CTRL_IE_MASK (0x2U) +#define SDMV2_CTRL_IE_SHIFT (1U) +#define SDMV2_CTRL_IE_SET(x) (((uint32_t)(x) << SDMV2_CTRL_IE_SHIFT) & SDMV2_CTRL_IE_MASK) +#define SDMV2_CTRL_IE_GET(x) (((uint32_t)(x) & SDMV2_CTRL_IE_MASK) >> SDMV2_CTRL_IE_SHIFT) + +/* Bitfield definition for register: INT_EN */ +/* + * CH0DRY (RW) + * + * Ch0 Data Ready interrupt enable + */ +#define SDMV2_INT_EN_CH0DRY_MASK (0x10U) +#define SDMV2_INT_EN_CH0DRY_SHIFT (4U) +#define SDMV2_INT_EN_CH0DRY_SET(x) (((uint32_t)(x) << SDMV2_INT_EN_CH0DRY_SHIFT) & SDMV2_INT_EN_CH0DRY_MASK) +#define SDMV2_INT_EN_CH0DRY_GET(x) (((uint32_t)(x) & SDMV2_INT_EN_CH0DRY_MASK) >> SDMV2_INT_EN_CH0DRY_SHIFT) + +/* + * CH0ERR (RW) + * + * Ch0 Error interrupt enable + */ +#define SDMV2_INT_EN_CH0ERR_MASK (0x1U) +#define SDMV2_INT_EN_CH0ERR_SHIFT (0U) +#define SDMV2_INT_EN_CH0ERR_SET(x) (((uint32_t)(x) << SDMV2_INT_EN_CH0ERR_SHIFT) & SDMV2_INT_EN_CH0ERR_MASK) +#define SDMV2_INT_EN_CH0ERR_GET(x) (((uint32_t)(x) & SDMV2_INT_EN_CH0ERR_MASK) >> SDMV2_INT_EN_CH0ERR_SHIFT) + +/* Bitfield definition for register: STATUS */ +/* + * CH0DRY (RO) + * + * Ch0 Data Ready + */ +#define SDMV2_STATUS_CH0DRY_MASK (0x2U) +#define SDMV2_STATUS_CH0DRY_SHIFT (1U) +#define SDMV2_STATUS_CH0DRY_GET(x) (((uint32_t)(x) & SDMV2_STATUS_CH0DRY_MASK) >> SDMV2_STATUS_CH0DRY_SHIFT) + +/* + * CH0ERR (RO) + * + * Ch0 Error + */ +#define SDMV2_STATUS_CH0ERR_MASK (0x1U) +#define SDMV2_STATUS_CH0ERR_SHIFT (0U) +#define SDMV2_STATUS_CH0ERR_GET(x) (((uint32_t)(x) & SDMV2_STATUS_CH0ERR_MASK) >> SDMV2_STATUS_CH0ERR_SHIFT) + +/* Bitfield definition for register of struct array CH: SDFIFOCTRL */ +/* + * THRSH (RW) + * + * FIFO threshold (0,..,16) (fillings > threshold, then gen int) + */ +#define SDMV2_CH_SDFIFOCTRL_THRSH_MASK (0x1F0U) +#define SDMV2_CH_SDFIFOCTRL_THRSH_SHIFT (4U) +#define SDMV2_CH_SDFIFOCTRL_THRSH_SET(x) (((uint32_t)(x) << SDMV2_CH_SDFIFOCTRL_THRSH_SHIFT) & SDMV2_CH_SDFIFOCTRL_THRSH_MASK) +#define SDMV2_CH_SDFIFOCTRL_THRSH_GET(x) (((uint32_t)(x) & SDMV2_CH_SDFIFOCTRL_THRSH_MASK) >> SDMV2_CH_SDFIFOCTRL_THRSH_SHIFT) + +/* + * D_RDY_INT_EN (RW) + * + * FIFO data ready interrupt enable + */ +#define SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK (0x4U) +#define SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT (2U) +#define SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_SET(x) (((uint32_t)(x) << SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) & SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) +#define SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_GET(x) (((uint32_t)(x) & SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) >> SDMV2_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) + +/* Bitfield definition for register of struct array CH: SDCTRLP */ +/* + * MANCH_THR (RW) + * + * Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] + */ +#define SDMV2_CH_SDCTRLP_MANCH_THR_MASK (0xFE000000UL) +#define SDMV2_CH_SDCTRLP_MANCH_THR_SHIFT (25U) +#define SDMV2_CH_SDCTRLP_MANCH_THR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_MANCH_THR_SHIFT) & SDMV2_CH_SDCTRLP_MANCH_THR_MASK) +#define SDMV2_CH_SDCTRLP_MANCH_THR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_MANCH_THR_MASK) >> SDMV2_CH_SDCTRLP_MANCH_THR_SHIFT) + +/* + * WDOG_THR (RW) + * + * Watch dog threshold for channel failure of CLK halting + */ +#define SDMV2_CH_SDCTRLP_WDOG_THR_MASK (0x1FE0000UL) +#define SDMV2_CH_SDCTRLP_WDOG_THR_SHIFT (17U) +#define SDMV2_CH_SDCTRLP_WDOG_THR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_WDOG_THR_SHIFT) & SDMV2_CH_SDCTRLP_WDOG_THR_MASK) +#define SDMV2_CH_SDCTRLP_WDOG_THR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_WDOG_THR_MASK) >> SDMV2_CH_SDCTRLP_WDOG_THR_SHIFT) + +/* + * AF_IE (RW) + * + * Acknowledge feedback interrupt enable + */ +#define SDMV2_CH_SDCTRLP_AF_IE_MASK (0x10000UL) +#define SDMV2_CH_SDCTRLP_AF_IE_SHIFT (16U) +#define SDMV2_CH_SDCTRLP_AF_IE_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_AF_IE_SHIFT) & SDMV2_CH_SDCTRLP_AF_IE_MASK) +#define SDMV2_CH_SDCTRLP_AF_IE_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_AF_IE_MASK) >> SDMV2_CH_SDCTRLP_AF_IE_SHIFT) + +/* + * DFFOVIE (RW) + * + * Ch Data FIFO overflow interrupt enable + */ +#define SDMV2_CH_SDCTRLP_DFFOVIE_MASK (0x8000U) +#define SDMV2_CH_SDCTRLP_DFFOVIE_SHIFT (15U) +#define SDMV2_CH_SDCTRLP_DFFOVIE_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_DFFOVIE_SHIFT) & SDMV2_CH_SDCTRLP_DFFOVIE_MASK) +#define SDMV2_CH_SDCTRLP_DFFOVIE_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_DFFOVIE_MASK) >> SDMV2_CH_SDCTRLP_DFFOVIE_SHIFT) + +/* + * DSATIE (RW) + * + * Ch CIC Data Saturation Interrupt Enable + */ +#define SDMV2_CH_SDCTRLP_DSATIE_MASK (0x4000U) +#define SDMV2_CH_SDCTRLP_DSATIE_SHIFT (14U) +#define SDMV2_CH_SDCTRLP_DSATIE_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_DSATIE_SHIFT) & SDMV2_CH_SDCTRLP_DSATIE_MASK) +#define SDMV2_CH_SDCTRLP_DSATIE_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_DSATIE_MASK) >> SDMV2_CH_SDCTRLP_DSATIE_SHIFT) + +/* + * DRIE (RW) + * + * Ch Data Ready Interrupt Enable + */ +#define SDMV2_CH_SDCTRLP_DRIE_MASK (0x2000U) +#define SDMV2_CH_SDCTRLP_DRIE_SHIFT (13U) +#define SDMV2_CH_SDCTRLP_DRIE_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_DRIE_SHIFT) & SDMV2_CH_SDCTRLP_DRIE_MASK) +#define SDMV2_CH_SDCTRLP_DRIE_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_DRIE_MASK) >> SDMV2_CH_SDCTRLP_DRIE_SHIFT) + +/* + * SYNCSEL (RW) + * + * Select the PWM SYNC Source + */ +#define SDMV2_CH_SDCTRLP_SYNCSEL_MASK (0x1F80U) +#define SDMV2_CH_SDCTRLP_SYNCSEL_SHIFT (7U) +#define SDMV2_CH_SDCTRLP_SYNCSEL_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_SYNCSEL_SHIFT) & SDMV2_CH_SDCTRLP_SYNCSEL_MASK) +#define SDMV2_CH_SDCTRLP_SYNCSEL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_SYNCSEL_MASK) >> SDMV2_CH_SDCTRLP_SYNCSEL_SHIFT) + +/* + * FFSYNCCLREN (RW) + * + * Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 + */ +#define SDMV2_CH_SDCTRLP_FFSYNCCLREN_MASK (0x40U) +#define SDMV2_CH_SDCTRLP_FFSYNCCLREN_SHIFT (6U) +#define SDMV2_CH_SDCTRLP_FFSYNCCLREN_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_FFSYNCCLREN_SHIFT) & SDMV2_CH_SDCTRLP_FFSYNCCLREN_MASK) +#define SDMV2_CH_SDCTRLP_FFSYNCCLREN_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_FFSYNCCLREN_MASK) >> SDMV2_CH_SDCTRLP_FFSYNCCLREN_SHIFT) + +/* + * WTSYNACLR (RW) + * + * 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen + * 0: WTSYNFLG should be cleared manually by WTSYNMCLR + */ +#define SDMV2_CH_SDCTRLP_WTSYNACLR_MASK (0x20U) +#define SDMV2_CH_SDCTRLP_WTSYNACLR_SHIFT (5U) +#define SDMV2_CH_SDCTRLP_WTSYNACLR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_WTSYNACLR_SHIFT) & SDMV2_CH_SDCTRLP_WTSYNACLR_MASK) +#define SDMV2_CH_SDCTRLP_WTSYNACLR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_WTSYNACLR_MASK) >> SDMV2_CH_SDCTRLP_WTSYNACLR_SHIFT) + +/* + * WTSYNMCLR (RW) + * + * 1: Manually clear WTSYNFLG. Auto-clear. + */ +#define SDMV2_CH_SDCTRLP_WTSYNMCLR_MASK (0x10U) +#define SDMV2_CH_SDCTRLP_WTSYNMCLR_SHIFT (4U) +#define SDMV2_CH_SDCTRLP_WTSYNMCLR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_WTSYNMCLR_SHIFT) & SDMV2_CH_SDCTRLP_WTSYNMCLR_MASK) +#define SDMV2_CH_SDCTRLP_WTSYNMCLR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_WTSYNMCLR_MASK) >> SDMV2_CH_SDCTRLP_WTSYNMCLR_SHIFT) + +/* + * WTSYNCEN (RW) + * + * 1: Start to store data only after PWM SYNC event + * 0: Start to store data whenever enabled + */ +#define SDMV2_CH_SDCTRLP_WTSYNCEN_MASK (0x8U) +#define SDMV2_CH_SDCTRLP_WTSYNCEN_SHIFT (3U) +#define SDMV2_CH_SDCTRLP_WTSYNCEN_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_WTSYNCEN_SHIFT) & SDMV2_CH_SDCTRLP_WTSYNCEN_MASK) +#define SDMV2_CH_SDCTRLP_WTSYNCEN_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_WTSYNCEN_MASK) >> SDMV2_CH_SDCTRLP_WTSYNCEN_SHIFT) + +/* + * D32 (RW) + * + * 1:32 bit data + * 0:16 bit data + */ +#define SDMV2_CH_SDCTRLP_D32_MASK (0x4U) +#define SDMV2_CH_SDCTRLP_D32_SHIFT (2U) +#define SDMV2_CH_SDCTRLP_D32_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_D32_SHIFT) & SDMV2_CH_SDCTRLP_D32_MASK) +#define SDMV2_CH_SDCTRLP_D32_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_D32_MASK) >> SDMV2_CH_SDCTRLP_D32_SHIFT) + +/* + * DR_OPT (RW) + * + * 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold + * 0: Use Data Reg Ready as data ready + */ +#define SDMV2_CH_SDCTRLP_DR_OPT_MASK (0x2U) +#define SDMV2_CH_SDCTRLP_DR_OPT_SHIFT (1U) +#define SDMV2_CH_SDCTRLP_DR_OPT_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_DR_OPT_SHIFT) & SDMV2_CH_SDCTRLP_DR_OPT_MASK) +#define SDMV2_CH_SDCTRLP_DR_OPT_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_DR_OPT_MASK) >> SDMV2_CH_SDCTRLP_DR_OPT_SHIFT) + +/* + * EN (RW) + * + * Data Path Enable + */ +#define SDMV2_CH_SDCTRLP_EN_MASK (0x1U) +#define SDMV2_CH_SDCTRLP_EN_SHIFT (0U) +#define SDMV2_CH_SDCTRLP_EN_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLP_EN_SHIFT) & SDMV2_CH_SDCTRLP_EN_MASK) +#define SDMV2_CH_SDCTRLP_EN_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLP_EN_MASK) >> SDMV2_CH_SDCTRLP_EN_SHIFT) + +/* Bitfield definition for register of struct array CH: SDCTRLE */ +/* + * 2ND_CIC_SCL (RW) + * + * the shifter pace for the output of the 2ns stage CIC + * 0: shift right 0 + * … + * n: shift right n steps + * max 17, so needs 5 bits + */ +#define SDMV2_CH_SDCTRLE_2ND_CIC_SCL_MASK (0x3E00000UL) +#define SDMV2_CH_SDCTRLE_2ND_CIC_SCL_SHIFT (21U) +#define SDMV2_CH_SDCTRLE_2ND_CIC_SCL_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_2ND_CIC_SCL_SHIFT) & SDMV2_CH_SDCTRLE_2ND_CIC_SCL_MASK) +#define SDMV2_CH_SDCTRLE_2ND_CIC_SCL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_2ND_CIC_SCL_MASK) >> SDMV2_CH_SDCTRLE_2ND_CIC_SCL_SHIFT) + +/* + * 2ND_SGD_ORDER (RW) + * + * 2nd CIC order + * 0: SYNC1 + * 1: SYNC2 + * 2: SYNC3 + * 3: FAST_SYNC + */ +#define SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_MASK (0x180000UL) +#define SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_SHIFT (19U) +#define SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_SHIFT) & SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_MASK) +#define SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_MASK) >> SDMV2_CH_SDCTRLE_2ND_SGD_ORDER_SHIFT) + +/* + * SGD_ORDR (RW) + * + * CIC order + * 0: SYNC1 + * 1: SYNC2 + * 2: SYNC3 + * 3: FAST_SYNC + */ +#define SDMV2_CH_SDCTRLE_SGD_ORDR_MASK (0x60000UL) +#define SDMV2_CH_SDCTRLE_SGD_ORDR_SHIFT (17U) +#define SDMV2_CH_SDCTRLE_SGD_ORDR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_SGD_ORDR_SHIFT) & SDMV2_CH_SDCTRLE_SGD_ORDR_MASK) +#define SDMV2_CH_SDCTRLE_SGD_ORDR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_SGD_ORDR_MASK) >> SDMV2_CH_SDCTRLE_SGD_ORDR_SHIFT) + +/* + * PWMSYNC (RW) + * + * Asserted to double sync the PWM trigger signal + */ +#define SDMV2_CH_SDCTRLE_PWMSYNC_MASK (0x10000UL) +#define SDMV2_CH_SDCTRLE_PWMSYNC_SHIFT (16U) +#define SDMV2_CH_SDCTRLE_PWMSYNC_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_PWMSYNC_SHIFT) & SDMV2_CH_SDCTRLE_PWMSYNC_MASK) +#define SDMV2_CH_SDCTRLE_PWMSYNC_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_PWMSYNC_MASK) >> SDMV2_CH_SDCTRLE_PWMSYNC_SHIFT) + +/* + * USE_ALT (RW) + * + * Asserted to use alternative input. + * Alternative input has a restart_filt to reset the counter and start data transfer, and also it has an intermittent input clock to accompany the input data. + */ +#define SDMV2_CH_SDCTRLE_USE_ALT_MASK (0x8000U) +#define SDMV2_CH_SDCTRLE_USE_ALT_SHIFT (15U) +#define SDMV2_CH_SDCTRLE_USE_ALT_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_USE_ALT_SHIFT) & SDMV2_CH_SDCTRLE_USE_ALT_MASK) +#define SDMV2_CH_SDCTRLE_USE_ALT_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_USE_ALT_MASK) >> SDMV2_CH_SDCTRLE_USE_ALT_SHIFT) + +/* + * CIC_SCL (RW) + * + * CIC shift control + */ +#define SDMV2_CH_SDCTRLE_CIC_SCL_MASK (0x7800U) +#define SDMV2_CH_SDCTRLE_CIC_SCL_SHIFT (11U) +#define SDMV2_CH_SDCTRLE_CIC_SCL_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_CIC_SCL_SHIFT) & SDMV2_CH_SDCTRLE_CIC_SCL_MASK) +#define SDMV2_CH_SDCTRLE_CIC_SCL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_CIC_SCL_MASK) >> SDMV2_CH_SDCTRLE_CIC_SCL_SHIFT) + +/* + * CIC_DEC_RATIO (RW) + * + * CIC decimation ratio. 0 means div-by-256 + */ +#define SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_MASK (0x7F8U) +#define SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT (3U) +#define SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) & SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_MASK) +#define SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_MASK) >> SDMV2_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) + +/* + * IGN_INI_SAMPLES (RW) + * + * NotZero: Don't store the first samples that are not accurate + * Zero: Store all samples + */ +#define SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_MASK (0x7U) +#define SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT (0U) +#define SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) & SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) +#define SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) >> SDMV2_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) + +/* Bitfield definition for register of struct array CH: SDST */ +/* + * PERIOD_MCLK (RO) + * + * maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. + */ +#define SDMV2_CH_SDST_PERIOD_MCLK_MASK (0x7F800000UL) +#define SDMV2_CH_SDST_PERIOD_MCLK_SHIFT (23U) +#define SDMV2_CH_SDST_PERIOD_MCLK_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_PERIOD_MCLK_MASK) >> SDMV2_CH_SDST_PERIOD_MCLK_SHIFT) + +/* + * 2ND_DSAT_ERR (W1C) + * + * CIC out Data saturation err. Error flag. + */ +#define SDMV2_CH_SDST_2ND_DSAT_ERR_MASK (0x800U) +#define SDMV2_CH_SDST_2ND_DSAT_ERR_SHIFT (11U) +#define SDMV2_CH_SDST_2ND_DSAT_ERR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_2ND_DSAT_ERR_SHIFT) & SDMV2_CH_SDST_2ND_DSAT_ERR_MASK) +#define SDMV2_CH_SDST_2ND_DSAT_ERR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_2ND_DSAT_ERR_MASK) >> SDMV2_CH_SDST_2ND_DSAT_ERR_SHIFT) + +/* + * FIFO_DR (W1C) + * + * FIFO data ready + */ +#define SDMV2_CH_SDST_FIFO_DR_MASK (0x200U) +#define SDMV2_CH_SDST_FIFO_DR_SHIFT (9U) +#define SDMV2_CH_SDST_FIFO_DR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_FIFO_DR_SHIFT) & SDMV2_CH_SDST_FIFO_DR_MASK) +#define SDMV2_CH_SDST_FIFO_DR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_FIFO_DR_MASK) >> SDMV2_CH_SDST_FIFO_DR_SHIFT) + +/* + * AF (W1C) + * + * Achnowledge flag + */ +#define SDMV2_CH_SDST_AF_MASK (0x100U) +#define SDMV2_CH_SDST_AF_SHIFT (8U) +#define SDMV2_CH_SDST_AF_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_AF_SHIFT) & SDMV2_CH_SDST_AF_MASK) +#define SDMV2_CH_SDST_AF_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_AF_MASK) >> SDMV2_CH_SDST_AF_SHIFT) + +/* + * DOV_ERR (W1C) + * + * Data FIFO Overflow Error. Error flag. + */ +#define SDMV2_CH_SDST_DOV_ERR_MASK (0x80U) +#define SDMV2_CH_SDST_DOV_ERR_SHIFT (7U) +#define SDMV2_CH_SDST_DOV_ERR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_DOV_ERR_SHIFT) & SDMV2_CH_SDST_DOV_ERR_MASK) +#define SDMV2_CH_SDST_DOV_ERR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_DOV_ERR_MASK) >> SDMV2_CH_SDST_DOV_ERR_SHIFT) + +/* + * DSAT_ERR (W1C) + * + * CIC out Data saturation err. Error flag. + */ +#define SDMV2_CH_SDST_DSAT_ERR_MASK (0x40U) +#define SDMV2_CH_SDST_DSAT_ERR_SHIFT (6U) +#define SDMV2_CH_SDST_DSAT_ERR_SET(x) (((uint32_t)(x) << SDMV2_CH_SDST_DSAT_ERR_SHIFT) & SDMV2_CH_SDST_DSAT_ERR_MASK) +#define SDMV2_CH_SDST_DSAT_ERR_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_DSAT_ERR_MASK) >> SDMV2_CH_SDST_DSAT_ERR_SHIFT) + +/* + * WTSYNFLG (RO) + * + * Wait-for-sync event found + */ +#define SDMV2_CH_SDST_WTSYNFLG_MASK (0x20U) +#define SDMV2_CH_SDST_WTSYNFLG_SHIFT (5U) +#define SDMV2_CH_SDST_WTSYNFLG_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_WTSYNFLG_MASK) >> SDMV2_CH_SDST_WTSYNFLG_SHIFT) + +/* + * FILL (RO) + * + * Data FIFO Fillings + */ +#define SDMV2_CH_SDST_FILL_MASK (0x1FU) +#define SDMV2_CH_SDST_FILL_SHIFT (0U) +#define SDMV2_CH_SDST_FILL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDST_FILL_MASK) >> SDMV2_CH_SDST_FILL_SHIFT) + +/* Bitfield definition for register of struct array CH: SDATA */ +/* + * VAL (RO) + * + * Data + */ +#define SDMV2_CH_SDATA_VAL_MASK (0xFFFFFFFFUL) +#define SDMV2_CH_SDATA_VAL_SHIFT (0U) +#define SDMV2_CH_SDATA_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDATA_VAL_MASK) >> SDMV2_CH_SDATA_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SDFIFO */ +/* + * VAL (RO) + * + * FIFO Data + */ +#define SDMV2_CH_SDFIFO_VAL_MASK (0xFFFFFFFFUL) +#define SDMV2_CH_SDFIFO_VAL_SHIFT (0U) +#define SDMV2_CH_SDFIFO_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SDFIFO_VAL_MASK) >> SDMV2_CH_SDFIFO_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCAMP */ +/* + * VAL (RO) + * + * instant Amplitude Results + */ +#define SDMV2_CH_SCAMP_VAL_MASK (0xFFFFU) +#define SDMV2_CH_SCAMP_VAL_SHIFT (0U) +#define SDMV2_CH_SCAMP_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCAMP_VAL_MASK) >> SDMV2_CH_SCAMP_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCHTL */ +/* + * VAL (RW) + * + * Amplitude Threshold for High Limit + */ +#define SDMV2_CH_SCHTL_VAL_MASK (0xFFFFU) +#define SDMV2_CH_SCHTL_VAL_SHIFT (0U) +#define SDMV2_CH_SCHTL_VAL_SET(x) (((uint32_t)(x) << SDMV2_CH_SCHTL_VAL_SHIFT) & SDMV2_CH_SCHTL_VAL_MASK) +#define SDMV2_CH_SCHTL_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCHTL_VAL_MASK) >> SDMV2_CH_SCHTL_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCHTLZ */ +/* + * VAL (RW) + * + * Amplitude Threshold for zero crossing + */ +#define SDMV2_CH_SCHTLZ_VAL_MASK (0xFFFFU) +#define SDMV2_CH_SCHTLZ_VAL_SHIFT (0U) +#define SDMV2_CH_SCHTLZ_VAL_SET(x) (((uint32_t)(x) << SDMV2_CH_SCHTLZ_VAL_SHIFT) & SDMV2_CH_SCHTLZ_VAL_MASK) +#define SDMV2_CH_SCHTLZ_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCHTLZ_VAL_MASK) >> SDMV2_CH_SCHTLZ_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCLLT */ +/* + * VAL (RW) + * + * Amplitude Threshold for low limit + */ +#define SDMV2_CH_SCLLT_VAL_MASK (0xFFFFU) +#define SDMV2_CH_SCLLT_VAL_SHIFT (0U) +#define SDMV2_CH_SCLLT_VAL_SET(x) (((uint32_t)(x) << SDMV2_CH_SCLLT_VAL_SHIFT) & SDMV2_CH_SCLLT_VAL_MASK) +#define SDMV2_CH_SCLLT_VAL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCLLT_VAL_MASK) >> SDMV2_CH_SCLLT_VAL_SHIFT) + +/* Bitfield definition for register of struct array CH: SCCTRL */ +/* + * 2ND_SGD_ORDR (RW) + * + * CIC decimation ratio. 0 means div-by-256 + */ +#define SDMV2_CH_SCCTRL_2ND_SGD_ORDR_MASK (0xFF000000UL) +#define SDMV2_CH_SCCTRL_2ND_SGD_ORDR_SHIFT (24U) +#define SDMV2_CH_SCCTRL_2ND_SGD_ORDR_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_2ND_SGD_ORDR_SHIFT) & SDMV2_CH_SCCTRL_2ND_SGD_ORDR_MASK) +#define SDMV2_CH_SCCTRL_2ND_SGD_ORDR_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_2ND_SGD_ORDR_MASK) >> SDMV2_CH_SCCTRL_2ND_SGD_ORDR_SHIFT) + +/* + * HZ_EN (RW) + * + * Zero Crossing Enable + */ +#define SDMV2_CH_SCCTRL_HZ_EN_MASK (0x800000UL) +#define SDMV2_CH_SCCTRL_HZ_EN_SHIFT (23U) +#define SDMV2_CH_SCCTRL_HZ_EN_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_HZ_EN_SHIFT) & SDMV2_CH_SCCTRL_HZ_EN_MASK) +#define SDMV2_CH_SCCTRL_HZ_EN_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_HZ_EN_MASK) >> SDMV2_CH_SCCTRL_HZ_EN_SHIFT) + +/* + * MF_IE (RW) + * + * Module failure Interrupt enable + */ +#define SDMV2_CH_SCCTRL_MF_IE_MASK (0x400000UL) +#define SDMV2_CH_SCCTRL_MF_IE_SHIFT (22U) +#define SDMV2_CH_SCCTRL_MF_IE_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_MF_IE_SHIFT) & SDMV2_CH_SCCTRL_MF_IE_MASK) +#define SDMV2_CH_SCCTRL_MF_IE_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_MF_IE_MASK) >> SDMV2_CH_SCCTRL_MF_IE_SHIFT) + +/* + * HL_IE (RW) + * + * HLT Interrupt Enable + */ +#define SDMV2_CH_SCCTRL_HL_IE_MASK (0x200000UL) +#define SDMV2_CH_SCCTRL_HL_IE_SHIFT (21U) +#define SDMV2_CH_SCCTRL_HL_IE_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_HL_IE_SHIFT) & SDMV2_CH_SCCTRL_HL_IE_MASK) +#define SDMV2_CH_SCCTRL_HL_IE_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_HL_IE_MASK) >> SDMV2_CH_SCCTRL_HL_IE_SHIFT) + +/* + * LL_IE (RW) + * + * LLT interrupt Enable + */ +#define SDMV2_CH_SCCTRL_LL_IE_MASK (0x100000UL) +#define SDMV2_CH_SCCTRL_LL_IE_SHIFT (20U) +#define SDMV2_CH_SCCTRL_LL_IE_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_LL_IE_SHIFT) & SDMV2_CH_SCCTRL_LL_IE_MASK) +#define SDMV2_CH_SCCTRL_LL_IE_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_LL_IE_MASK) >> SDMV2_CH_SCCTRL_LL_IE_SHIFT) + +/* + * SGD_ORDR (RW) + * + * CIC order + * 0: SYNC1 + * 1: SYNC2 + * 2: SYNC3 + * 3: FAST_SYNC + */ +#define SDMV2_CH_SCCTRL_SGD_ORDR_MASK (0xC0000UL) +#define SDMV2_CH_SCCTRL_SGD_ORDR_SHIFT (18U) +#define SDMV2_CH_SCCTRL_SGD_ORDR_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_SGD_ORDR_SHIFT) & SDMV2_CH_SCCTRL_SGD_ORDR_MASK) +#define SDMV2_CH_SCCTRL_SGD_ORDR_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_SGD_ORDR_MASK) >> SDMV2_CH_SCCTRL_SGD_ORDR_SHIFT) + +/* + * CIC_DEC_RATIO (RW) + * + * CIC decimation ratio. 0 means div-by-32 + */ +#define SDMV2_CH_SCCTRL_CIC_DEC_RATIO_MASK (0x1F0U) +#define SDMV2_CH_SCCTRL_CIC_DEC_RATIO_SHIFT (4U) +#define SDMV2_CH_SCCTRL_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) & SDMV2_CH_SCCTRL_CIC_DEC_RATIO_MASK) +#define SDMV2_CH_SCCTRL_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_CIC_DEC_RATIO_MASK) >> SDMV2_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) + +/* + * IGN_INI_SAMPLES (RW) + * + * NotZero: Ignore the first samples that are not accurate + * Zero: Use all samples + */ +#define SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_MASK (0xEU) +#define SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT (1U) +#define SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) & SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_MASK) +#define SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_MASK) >> SDMV2_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) + +/* + * EN (RW) + * + * Amplitude Path Enable + */ +#define SDMV2_CH_SCCTRL_EN_MASK (0x1U) +#define SDMV2_CH_SCCTRL_EN_SHIFT (0U) +#define SDMV2_CH_SCCTRL_EN_SET(x) (((uint32_t)(x) << SDMV2_CH_SCCTRL_EN_SHIFT) & SDMV2_CH_SCCTRL_EN_MASK) +#define SDMV2_CH_SCCTRL_EN_GET(x) (((uint32_t)(x) & SDMV2_CH_SCCTRL_EN_MASK) >> SDMV2_CH_SCCTRL_EN_SHIFT) + +/* Bitfield definition for register of struct array CH: SCST */ +/* + * HZ (W1C) + * + * Amplitude rising above HZ event found. + */ +#define SDMV2_CH_SCST_HZ_MASK (0x8U) +#define SDMV2_CH_SCST_HZ_SHIFT (3U) +#define SDMV2_CH_SCST_HZ_SET(x) (((uint32_t)(x) << SDMV2_CH_SCST_HZ_SHIFT) & SDMV2_CH_SCST_HZ_MASK) +#define SDMV2_CH_SCST_HZ_GET(x) (((uint32_t)(x) & SDMV2_CH_SCST_HZ_MASK) >> SDMV2_CH_SCST_HZ_SHIFT) + +/* + * MF (W1C) + * + * power modulator Failure found. MCLK not found. Error flag. + */ +#define SDMV2_CH_SCST_MF_MASK (0x4U) +#define SDMV2_CH_SCST_MF_SHIFT (2U) +#define SDMV2_CH_SCST_MF_SET(x) (((uint32_t)(x) << SDMV2_CH_SCST_MF_SHIFT) & SDMV2_CH_SCST_MF_MASK) +#define SDMV2_CH_SCST_MF_GET(x) (((uint32_t)(x) & SDMV2_CH_SCST_MF_MASK) >> SDMV2_CH_SCST_MF_SHIFT) + +/* + * CMPH (W1C) + * + * HLT out of range. Error flag. + */ +#define SDMV2_CH_SCST_CMPH_MASK (0x2U) +#define SDMV2_CH_SCST_CMPH_SHIFT (1U) +#define SDMV2_CH_SCST_CMPH_SET(x) (((uint32_t)(x) << SDMV2_CH_SCST_CMPH_SHIFT) & SDMV2_CH_SCST_CMPH_MASK) +#define SDMV2_CH_SCST_CMPH_GET(x) (((uint32_t)(x) & SDMV2_CH_SCST_CMPH_MASK) >> SDMV2_CH_SCST_CMPH_SHIFT) + +/* + * CMPL (W1C) + * + * LLT out of range. Error flag. + */ +#define SDMV2_CH_SCST_CMPL_MASK (0x1U) +#define SDMV2_CH_SCST_CMPL_SHIFT (0U) +#define SDMV2_CH_SCST_CMPL_SET(x) (((uint32_t)(x) << SDMV2_CH_SCST_CMPL_SHIFT) & SDMV2_CH_SCST_CMPL_MASK) +#define SDMV2_CH_SCST_CMPL_GET(x) (((uint32_t)(x) & SDMV2_CH_SCST_CMPL_MASK) >> SDMV2_CH_SCST_CMPL_SHIFT) + + + +/* CH register group index macro definition */ +#define SDMV2_CH_0 (0UL) + + +#endif /* HPM_SDMV2_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h index 6c48f784..af49f4a3 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_sec_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 HPMicro + * Copyright (c) 2021-2023 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -246,13 +246,13 @@ typedef struct { * LIFECYCLE (RO) * * lifecycle status, - * bit7: lifecycle_debate, - * bit6: lifecycle_scribe, - * bit5: lifecycle_no_ret, - * bit4: lifecycle_return, - * bit3: lifecycle_secure, - * bit2: lifecycle_nonsec, - * bit1: lifecycle_create, + * bit7: lifecycle_debate, + * bit6: lifecycle_scribe, + * bit5: lifecycle_no_ret, + * bit4: lifecycle_return, + * bit3: lifecycle_secure, + * bit2: lifecycle_nonsec, + * bit1: lifecycle_create, * bit0: lifecycle_unknow */ #define SEC_LIFECYCLE_LIFECYCLE_MASK (0xFFU) diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_sei_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_sei_regs.h new file mode 100644 index 00000000..60574101 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_sei_regs.h @@ -0,0 +1,3636 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SEI_H +#define HPM_SEI_H + +typedef struct { + struct { + struct { + __RW uint32_t CTRL; /* 0x0: Engine control register */ + __RW uint32_t PTR_CFG; /* 0x4: Pointer configuration register */ + __RW uint32_t WDG_CFG; /* 0x8: Watch dog configuration register */ + __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ + __R uint32_t EXE_STA; /* 0x10: Execution status */ + __R uint32_t EXE_PTR; /* 0x14: Execution pointer */ + __R uint32_t EXE_INST; /* 0x18: Execution instruction */ + __R uint32_t WDG_STA; /* 0x1C: Watch dog status */ + } ENGINE; + struct { + __RW uint32_t CTRL; /* 0x20: Transceiver control register */ + __RW uint32_t TYPE_CFG; /* 0x24: Transceiver configuration register */ + __RW uint32_t BAUD_CFG; /* 0x28: Transceiver baud rate register */ + __RW uint32_t DATA_CFG; /* 0x2C: Transceiver data timing configuration */ + __RW uint32_t CLK_CFG; /* 0x30: Transceiver clock timing configuration */ + __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */ + __R uint32_t PIN; /* 0x38: Transceiver pin status */ + __R uint32_t STATE; /* 0x3C: FSM of asynchronous */ + } XCVR; + struct { + __RW uint32_t IN_CFG; /* 0x40: Trigger input configuration */ + __W uint32_t SW; /* 0x44: Software trigger */ + __RW uint32_t PRD_CFG; /* 0x48: Period trigger configuration */ + __RW uint32_t PRD; /* 0x4C: Trigger period */ + __RW uint32_t OUT_CFG; /* 0x50: Trigger output configuration */ + __R uint8_t RESERVED0[12]; /* 0x54 - 0x5F: Reserved */ + __R uint32_t PRD_STS; /* 0x60: Period trigger status */ + __R uint32_t PRD_CNT; /* 0x64: Period trigger counter */ + __R uint8_t RESERVED1[24]; /* 0x68 - 0x7F: Reserved */ + } TRG; + struct { + __RW uint32_t CMD[4]; /* 0x80 - 0x8C: Trigger command */ + __R uint8_t RESERVED0[16]; /* 0x90 - 0x9F: Reserved */ + __R uint32_t TIME[4]; /* 0xA0 - 0xAC: Trigger Time */ + __R uint8_t RESERVED1[16]; /* 0xB0 - 0xBF: Reserved */ + } TRG_TABLE; + struct { + __RW uint32_t MODE; /* 0xC0: command register mode */ + __RW uint32_t IDX; /* 0xC4: command register configuration */ + __RW uint32_t GOLD; /* 0xC8: Command gold value */ + __RW uint32_t CRCINIT; /* 0xCC: Command Initial value */ + __RW uint32_t CRCPOLY; /* 0xD0: Command CRC polymial */ + __R uint8_t RESERVED0[12]; /* 0xD4 - 0xDF: Reserved */ + __RW uint32_t CMD; /* 0xE0: command */ + __RW uint32_t SET; /* 0xE4: command bit set register */ + __RW uint32_t CLR; /* 0xE8: command bit clear register */ + __RW uint32_t INV; /* 0xEC: command bit invert register */ + __R uint32_t IN; /* 0xF0: Commad input */ + __R uint32_t OUT; /* 0xF4: Command output */ + __RW uint32_t STS; /* 0xF8: Command status */ + __R uint8_t RESERVED1[4]; /* 0xFC - 0xFF: Reserved */ + } CMD; + struct { + __RW uint32_t MIN; /* 0x100: command start value */ + __RW uint32_t MAX; /* 0x104: command end value */ + __RW uint32_t MSK; /* 0x108: command compare bit enable */ + __R uint8_t RESERVED0[4]; /* 0x10C - 0x10F: Reserved */ + __RW uint32_t PTA; /* 0x110: command pointer 0 - 3 */ + __RW uint32_t PTB; /* 0x114: command pointer 4 - 7 */ + __RW uint32_t PTC; /* 0x118: command pointer 8 - 11 */ + __RW uint32_t PTD; /* 0x11C: command pointer 12 - 15 */ + } CMD_TABLE[8]; + struct { + __RW uint32_t TRAN[4]; /* 0x200 - 0x20C: Latch state transition configuration */ + __RW uint32_t CFG; /* 0x210: Latch configuration */ + __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */ + __R uint32_t TIME; /* 0x218: Latch time */ + __R uint32_t STS; /* 0x21C: Latch status */ + } LATCH[4]; + struct { + __RW uint32_t SMP_EN; /* 0x280: Sample selection register */ + __RW uint32_t SMP_CFG; /* 0x284: Sample configuration */ + __RW uint32_t SMP_DAT; /* 0x288: Sample data */ + __R uint8_t RESERVED0[4]; /* 0x28C - 0x28F: Reserved */ + __RW uint32_t SMP_POS; /* 0x290: Sample override position */ + __RW uint32_t SMP_REV; /* 0x294: Sample override revolution */ + __RW uint32_t SMP_SPD; /* 0x298: Sample override speed */ + __RW uint32_t SMP_ACC; /* 0x29C: Sample override accelerate */ + __RW uint32_t UPD_EN; /* 0x2A0: Update configuration */ + __RW uint32_t UPD_CFG; /* 0x2A4: Update configuration */ + __RW uint32_t UPD_DAT; /* 0x2A8: Update data */ + __RW uint32_t UPD_TIME; /* 0x2AC: Update overide time */ + __RW uint32_t UPD_POS; /* 0x2B0: Update override position */ + __RW uint32_t UPD_REV; /* 0x2B4: Update override revolution */ + __RW uint32_t UPD_SPD; /* 0x2B8: Update override speed */ + __RW uint32_t UPD_ACC; /* 0x2BC: Update override accelerate */ + __R uint32_t SMP_VAL; /* 0x2C0: Sample valid */ + __R uint32_t SMP_STS; /* 0x2C4: Sample status */ + __R uint8_t RESERVED1[4]; /* 0x2C8 - 0x2CB: Reserved */ + __R uint32_t TIME_IN; /* 0x2CC: input time */ + __R uint32_t POS_IN; /* 0x2D0: Input position */ + __R uint32_t REV_IN; /* 0x2D4: Input revolution */ + __R uint32_t SPD_IN; /* 0x2D8: Input speed */ + __R uint32_t ACC_IN; /* 0x2DC: Input accelerate */ + __R uint8_t RESERVED2[4]; /* 0x2E0 - 0x2E3: Reserved */ + __R uint32_t UPD_STS; /* 0x2E4: Update status */ + __R uint8_t RESERVED3[24]; /* 0x2E8 - 0x2FF: Reserved */ + } POS; + struct { + __RW uint32_t INT_EN; /* 0x300: Interrupt Enable */ + __W uint32_t INT_FLAG; /* 0x304: Interrupt flag */ + __R uint32_t INT_STS; /* 0x308: Interrupt status */ + __R uint8_t RESERVED0[4]; /* 0x30C - 0x30F: Reserved */ + __RW uint32_t POINTER0; /* 0x310: Match pointer 0 */ + __RW uint32_t POINTER1; /* 0x314: Match pointer 1 */ + __RW uint32_t INSTR0; /* 0x318: Match instruction 0 */ + __RW uint32_t INSTR1; /* 0x31C: Match instruction 1 */ + } IRQ; + __R uint8_t RESERVED0[224]; /* 0x320 - 0x3FF: Reserved */ + } CTRL[13]; + __RW uint32_t INSTR[256]; /* 0x3400 - 0x37FC: Instructions */ + struct { + __RW uint32_t MODE; /* 0x3800: */ + __RW uint32_t IDX; /* 0x3804: Data register bit index */ + __RW uint32_t GOLD; /* 0x3808: Gold data for data check */ + __RW uint32_t CRCINIT; /* 0x380C: CRC calculation initial vector */ + __RW uint32_t CRCPOLY; /* 0x3810: CRC calculation polynomial */ + __R uint8_t RESERVED0[12]; /* 0x3814 - 0x381F: Reserved */ + __RW uint32_t DATA; /* 0x3820: Data value */ + __RW uint32_t SET; /* 0x3824: Data bit set */ + __RW uint32_t CLR; /* 0x3828: Data bit clear */ + __RW uint32_t INV; /* 0x382C: Data bit invert */ + __R uint32_t IN; /* 0x3830: Data input */ + __R uint32_t OUT; /* 0x3834: Data output */ + __RW uint32_t STS; /* 0x3838: Data status */ + __R uint8_t RESERVED1[4]; /* 0x383C - 0x383F: Reserved */ + } DAT[32]; +} SEI_Type; + + +/* Bitfield definition for register of struct array CTRL: CTRL */ +/* + * WATCH (RW) + * + * Enable watch dog + * 0: Watch dog disabled + * 1: Watch dog enabled + */ +#define SEI_CTRL_ENGINE_CTRL_WATCH_MASK (0x1000000UL) +#define SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT (24U) +#define SEI_CTRL_ENGINE_CTRL_WATCH_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) +#define SEI_CTRL_ENGINE_CTRL_WATCH_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) >> SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) + +/* + * ARMING (RW) + * + * Wait for trigger before excuting + * 0: Execute on enable + * 1: Wait trigger before exection after enabled + */ +#define SEI_CTRL_ENGINE_CTRL_ARMING_MASK (0x10000UL) +#define SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT (16U) +#define SEI_CTRL_ENGINE_CTRL_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) +#define SEI_CTRL_ENGINE_CTRL_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) >> SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) + +/* + * EXCEPT (RW) + * + * Explain timout as exception + * 0: when timeout, pointer move to next instruction + * 1: when timeout, pointer jump to timeout vector + */ +#define SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK (0x100U) +#define SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT (8U) +#define SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) +#define SEI_CTRL_ENGINE_CTRL_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) >> SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) + +/* + * REWIND (RW) + * + * Rewind execution pointer + * 0: run + * 1: clean status and rewind + */ +#define SEI_CTRL_ENGINE_CTRL_REWIND_MASK (0x10U) +#define SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT (4U) +#define SEI_CTRL_ENGINE_CTRL_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) +#define SEI_CTRL_ENGINE_CTRL_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) >> SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) + +/* + * ENABLE (RW) + * + * Enable + * 0: disable + * 1: enable + */ +#define SEI_CTRL_ENGINE_CTRL_ENABLE_MASK (0x1U) +#define SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT (0U) +#define SEI_CTRL_ENGINE_CTRL_ENABLE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) +#define SEI_CTRL_ENGINE_CTRL_ENABLE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) >> SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PTR_CFG */ +/* + * DAT_CDM (RW) + * + * Select DATA register to receive CDM bit in BiSSC slave mode + * 0: ignore + * 1: command + * 2: data register 2 + * 3: data register 3 + * ... + * 29:data register 29 + * 30: value 0 when send, ignore in receive + * 31: value1 when send, ignore in receive + */ +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK (0x1F000000UL) +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT (24U) +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) + +/* + * DAT_BASE (RW) + * + * Bias for data register access, if calculated index bigger than 32, index will wrap around + * 0: real data index + * 1: access index is 1 greater than instruction address + * 2: access index is 2 greater than instruction address + * ... + * 31: access index is 31 greater than instruction address + */ +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK (0x1F0000UL) +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT (16U) +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) +#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) + +/* + * POINTER_WDOG (RW) + * + * Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME + */ +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK (0xFF00U) +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT (8U) +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) + +/* + * POINTER_INIT (RW) + * + * Initial execute pointer + */ +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK (0xFFU) +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT (0U) +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) +#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: WDG_CFG */ +/* + * WDOG_TIME (RW) + * + * Time out count for each instruction, counter in bit time. + */ +#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK (0xFFFFU) +#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT (0U) +#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) +#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) >> SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) + +/* Bitfield definition for register of struct array CTRL: EXE_STA */ +/* + * TRIGERED (RO) + * + * Execution has been triggered + * 0: Execution not triggered + * 1: Execution triggered + */ +#define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK (0x100000UL) +#define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT (20U) +#define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT) + +/* + * ARMED (RO) + * + * Waiting for trigger for execution + * 0: Not in waiting status + * 1: In waiting status + */ +#define SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK (0x10000UL) +#define SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT (16U) +#define SEI_CTRL_ENGINE_EXE_STA_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT) + +/* + * EXPIRE (RO) + * + * Watchdog timer expired + * 0: Not expired + * 1: Expired + */ +#define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK (0x100U) +#define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT (8U) +#define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK) >> SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT) + +/* + * STALL (RO) + * + * Program finished + * 0: Program is executing + * 1: Program finished + */ +#define SEI_CTRL_ENGINE_EXE_STA_STALL_MASK (0x1U) +#define SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT (0U) +#define SEI_CTRL_ENGINE_EXE_STA_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_STALL_MASK) >> SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: EXE_PTR */ +/* + * HALT_CNT (RO) + * + * Halt count in halt instrution + */ +#define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK (0x1F000000UL) +#define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT (24U) +#define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT) + +/* + * BIT_CNT (RO) + * + * Bit count in send and receive instruction execution + */ +#define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK (0x1F0000UL) +#define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT (16U) +#define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT) + +/* + * POINTER (RO) + * + * Current program pointer + */ +#define SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK (0xFFU) +#define SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT (0U) +#define SEI_CTRL_ENGINE_EXE_PTR_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT) + +/* Bitfield definition for register of struct array CTRL: EXE_INST */ +/* + * INST (RO) + * + * Current instruction + */ +#define SEI_CTRL_ENGINE_EXE_INST_INST_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT (0U) +#define SEI_CTRL_ENGINE_EXE_INST_INST_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_INST_INST_MASK) >> SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT) + +/* Bitfield definition for register of struct array CTRL: WDG_STA */ +/* + * WDOG_CNT (RO) + * + * Current watch dog counter value + */ +#define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK (0xFFFFU) +#define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT (0U) +#define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK) >> SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CTRL */ +/* + * TRISMP (RW) + * + * Tipple sampe + * 0: sample 1 time for data transition + * 1: sample 3 times in receive and result in 2oo3 + */ +#define SEI_CTRL_XCVR_CTRL_TRISMP_MASK (0x1000U) +#define SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT (12U) +#define SEI_CTRL_XCVR_CTRL_TRISMP_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) +#define SEI_CTRL_XCVR_CTRL_TRISMP_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) >> SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) + +/* + * PAR_CLR (WC) + * + * Clear parity error, this is a self clear bit + * 0: no effect + * 1: clear parity error + */ +#define SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK (0x100U) +#define SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT (8U) +#define SEI_CTRL_XCVR_CTRL_PAR_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) +#define SEI_CTRL_XCVR_CTRL_PAR_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) >> SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) + +/* + * RESTART (WC) + * + * Restart tranceiver, this is a self clear bit + * 0: no effect + * 1: reset tranceiver + */ +#define SEI_CTRL_XCVR_CTRL_RESTART_MASK (0x10U) +#define SEI_CTRL_XCVR_CTRL_RESTART_SHIFT (4U) +#define SEI_CTRL_XCVR_CTRL_RESTART_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) +#define SEI_CTRL_XCVR_CTRL_RESTART_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) >> SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) + +/* + * MODE (RW) + * + * Tranceiver mode + * 0: synchronous maaster + * 1: synchronous slave + * 2: asynchronous mode + * 3: asynchronous mode + */ +#define SEI_CTRL_XCVR_CTRL_MODE_MASK (0x3U) +#define SEI_CTRL_XCVR_CTRL_MODE_SHIFT (0U) +#define SEI_CTRL_XCVR_CTRL_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_MODE_SHIFT) & SEI_CTRL_XCVR_CTRL_MODE_MASK) +#define SEI_CTRL_XCVR_CTRL_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_MODE_MASK) >> SEI_CTRL_XCVR_CTRL_MODE_SHIFT) + +/* Bitfield definition for register of struct array CTRL: TYPE_CFG */ +/* + * WAIT_LEN (RW) + * + * Number of extra stop bit for asynchronous mode + * 0: 1 bit + * 1: 2 bit + * ... + * 255: 256 bit + */ +#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK (0xFF000000UL) +#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT (24U) +#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) + +/* + * DATA_LEN (RW) + * + * Number of data bit for asynchronous mode + * 0: 1 bit + * 1: 2 bit + * ... + * 31: 32 bit + */ +#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK (0x1F0000UL) +#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT (16U) +#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) + +/* + * PAR_POL (RW) + * + * Polarity of parity for asynchronous mode + * 0: even + * 1: odd + */ +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK (0x200U) +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT (9U) +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) + +/* + * PAR_EN (RW) + * + * enable parity check for asynchronous mode + * 0: disable + * 1: enable + */ +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK (0x100U) +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT (8U) +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) + +/* + * DA_IDLEZ (RW) + * + * Idle state driver of data line + * 0: output + * 1: high-Z + */ +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK (0x8U) +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT (3U) +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) + +/* + * CK_IDLEZ (RW) + * + * Idle state driver of clock line + * 0: output + * 1: high-Z + */ +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK (0x4U) +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT (2U) +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) + +/* + * DA_IDLEV (RW) + * + * Idle state value of data line + * 0: data'0' + * 1: data'1' + */ +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK (0x2U) +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT (1U) +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) + +/* + * CK_IDLEV (RW) + * + * Idle state value of clock line + * 0: data'0' + * 1: data'1' + */ +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK (0x1U) +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT (0U) +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) +#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) + +/* Bitfield definition for register of struct array CTRL: BAUD_CFG */ +/* + * SYNC_POINT (RW) + * + * Baud synchronous time, minmum bit time + */ +#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK (0xFFFF0000UL) +#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT (16U) +#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) +#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) + +/* + * BAUD_DIV (RW) + * + * Baud rate, bit time in system clock cycle + */ +#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK (0xFFFFU) +#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT (0U) +#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) +#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) + +/* Bitfield definition for register of struct array CTRL: DATA_CFG */ +/* + * TXD_POINT (RW) + * + * data transmit point in system clcok cycle + */ +#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK (0xFFFF0000UL) +#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT (16U) +#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) +#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) + +/* + * RXD_POINT (RW) + * + * data receive point in system clcok cycle + */ +#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK (0xFFFFU) +#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT (0U) +#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) +#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CLK_CFG */ +/* + * CK1_POINT (RW) + * + * clock point 1 in system clcok cycle + */ +#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK (0xFFFF0000UL) +#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT (16U) +#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) +#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) + +/* + * CK0_POINT (RW) + * + * clock point 0 in system clcok cycle + */ +#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK (0xFFFFU) +#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT (0U) +#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) +#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PIN */ +/* + * OE_CK (RO) + * + * CK drive state + * 0: input + * 1: output + */ +#define SEI_CTRL_XCVR_PIN_OE_CK_MASK (0x4000000UL) +#define SEI_CTRL_XCVR_PIN_OE_CK_SHIFT (26U) +#define SEI_CTRL_XCVR_PIN_OE_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_CK_MASK) >> SEI_CTRL_XCVR_PIN_OE_CK_SHIFT) + +/* + * DI_CK (RO) + * + * CK state + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DI_CK_MASK (0x2000000UL) +#define SEI_CTRL_XCVR_PIN_DI_CK_SHIFT (25U) +#define SEI_CTRL_XCVR_PIN_DI_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_CK_MASK) >> SEI_CTRL_XCVR_PIN_DI_CK_SHIFT) + +/* + * DO_CK (RO) + * + * CK output + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DO_CK_MASK (0x1000000UL) +#define SEI_CTRL_XCVR_PIN_DO_CK_SHIFT (24U) +#define SEI_CTRL_XCVR_PIN_DO_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_CK_MASK) >> SEI_CTRL_XCVR_PIN_DO_CK_SHIFT) + +/* + * OE_RX (RO) + * + * RX drive state + * 0: input + * 1: output + */ +#define SEI_CTRL_XCVR_PIN_OE_RX_MASK (0x40000UL) +#define SEI_CTRL_XCVR_PIN_OE_RX_SHIFT (18U) +#define SEI_CTRL_XCVR_PIN_OE_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_RX_MASK) >> SEI_CTRL_XCVR_PIN_OE_RX_SHIFT) + +/* + * DI_RX (RO) + * + * RX state + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DI_RX_MASK (0x20000UL) +#define SEI_CTRL_XCVR_PIN_DI_RX_SHIFT (17U) +#define SEI_CTRL_XCVR_PIN_DI_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_RX_MASK) >> SEI_CTRL_XCVR_PIN_DI_RX_SHIFT) + +/* + * DO_RX (RO) + * + * RX output + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DO_RX_MASK (0x10000UL) +#define SEI_CTRL_XCVR_PIN_DO_RX_SHIFT (16U) +#define SEI_CTRL_XCVR_PIN_DO_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_RX_MASK) >> SEI_CTRL_XCVR_PIN_DO_RX_SHIFT) + +/* + * OE_DE (RO) + * + * DE drive state + * 0: input + * 1: output + */ +#define SEI_CTRL_XCVR_PIN_OE_DE_MASK (0x400U) +#define SEI_CTRL_XCVR_PIN_OE_DE_SHIFT (10U) +#define SEI_CTRL_XCVR_PIN_OE_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_DE_MASK) >> SEI_CTRL_XCVR_PIN_OE_DE_SHIFT) + +/* + * DI_DE (RO) + * + * DE state + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DI_DE_MASK (0x200U) +#define SEI_CTRL_XCVR_PIN_DI_DE_SHIFT (9U) +#define SEI_CTRL_XCVR_PIN_DI_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_DE_MASK) >> SEI_CTRL_XCVR_PIN_DI_DE_SHIFT) + +/* + * DO_DE (RO) + * + * DE output + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DO_DE_MASK (0x100U) +#define SEI_CTRL_XCVR_PIN_DO_DE_SHIFT (8U) +#define SEI_CTRL_XCVR_PIN_DO_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_DE_MASK) >> SEI_CTRL_XCVR_PIN_DO_DE_SHIFT) + +/* + * OE_TX (RO) + * + * TX drive state + * 0: input + * 1: output + */ +#define SEI_CTRL_XCVR_PIN_OE_TX_MASK (0x4U) +#define SEI_CTRL_XCVR_PIN_OE_TX_SHIFT (2U) +#define SEI_CTRL_XCVR_PIN_OE_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_TX_MASK) >> SEI_CTRL_XCVR_PIN_OE_TX_SHIFT) + +/* + * DI_TX (RO) + * + * TX state + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DI_TX_MASK (0x2U) +#define SEI_CTRL_XCVR_PIN_DI_TX_SHIFT (1U) +#define SEI_CTRL_XCVR_PIN_DI_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_TX_MASK) >> SEI_CTRL_XCVR_PIN_DI_TX_SHIFT) + +/* + * DO_TX (RO) + * + * TX output + * 0: data 0 + * 1: data 1 + */ +#define SEI_CTRL_XCVR_PIN_DO_TX_MASK (0x1U) +#define SEI_CTRL_XCVR_PIN_DO_TX_SHIFT (0U) +#define SEI_CTRL_XCVR_PIN_DO_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_TX_MASK) >> SEI_CTRL_XCVR_PIN_DO_TX_SHIFT) + +/* Bitfield definition for register of struct array CTRL: STATE */ +/* + * RECV_STATE (RO) + * + * FSM of asynchronous receive + */ +#define SEI_CTRL_XCVR_STATE_RECV_STATE_MASK (0x7000000UL) +#define SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT (24U) +#define SEI_CTRL_XCVR_STATE_RECV_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_RECV_STATE_MASK) >> SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT) + +/* + * SEND_STATE (RO) + * + * FSM of asynchronous transmit + */ +#define SEI_CTRL_XCVR_STATE_SEND_STATE_MASK (0x70000UL) +#define SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT (16U) +#define SEI_CTRL_XCVR_STATE_SEND_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_SEND_STATE_MASK) >> SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT) + +/* Bitfield definition for register of struct array CTRL: IN_CFG */ +/* + * PRD_EN (RW) + * + * Enable period trigger (tigger 2) + * 0: periodical trigger disabled + * 1: periodical trigger enabled + */ +#define SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK (0x800000UL) +#define SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT (23U) +#define SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) +#define SEI_CTRL_TRG_IN_CFG_PRD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) + +/* + * SYNC_SEL (RW) + * + * Synchronize sigal selection (tigger 2) + * 0: trigger in 0 + * 1: trigger in 1 + * ... + * 7: trigger in 7 + */ +#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK (0x70000UL) +#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT (16U) +#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) +#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) + +/* + * IN1_EN (RW) + * + * Enable trigger 1 + * 0: disable trigger 1 + * 1: enable trigger 1 + */ +#define SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK (0x8000U) +#define SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT (15U) +#define SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) +#define SEI_CTRL_TRG_IN_CFG_IN1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) + +/* + * IN1_SEL (RW) + * + * Trigger 1 sigal selection + * 0: trigger in 0 + * 1: trigger in 1 + * ... + * 7: trigger in 7 + */ +#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK (0x700U) +#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT (8U) +#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) +#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) + +/* + * IN0_EN (RW) + * + * Enable trigger 0 + * 0: disable trigger 1 + * 1: enable trigger 1 + */ +#define SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK (0x80U) +#define SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT (7U) +#define SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) +#define SEI_CTRL_TRG_IN_CFG_IN0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) + +/* + * IN0_SEL (RW) + * + * Trigger 0 sigal selection + * 0: trigger in 0 + * 1: trigger in 1 + * ... + * 7: trigger in 7 + */ +#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK (0x7U) +#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT (0U) +#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) +#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SW */ +/* + * SOFT (WC) + * + * Software trigger (tigger 3). this bit is self-clear + * 0: trigger source disabled + * 1: trigger source enabled + */ +#define SEI_CTRL_TRG_SW_SOFT_MASK (0x1U) +#define SEI_CTRL_TRG_SW_SOFT_SHIFT (0U) +#define SEI_CTRL_TRG_SW_SOFT_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_SW_SOFT_SHIFT) & SEI_CTRL_TRG_SW_SOFT_MASK) +#define SEI_CTRL_TRG_SW_SOFT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_SW_SOFT_MASK) >> SEI_CTRL_TRG_SW_SOFT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PRD_CFG */ +/* + * ARMING (RW) + * + * Wait for trigger synchronous before trigger + * 0: Trigger directly + * 1: Wait trigger source before period trigger + */ +#define SEI_CTRL_TRG_PRD_CFG_ARMING_MASK (0x10000UL) +#define SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT (16U) +#define SEI_CTRL_TRG_PRD_CFG_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) +#define SEI_CTRL_TRG_PRD_CFG_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) >> SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) + +/* + * SYNC (RW) + * + * Synchronous + * 0: Not synchronous + * 1: Synchronous every trigger source + */ +#define SEI_CTRL_TRG_PRD_CFG_SYNC_MASK (0x1U) +#define SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT (0U) +#define SEI_CTRL_TRG_PRD_CFG_SYNC_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) +#define SEI_CTRL_TRG_PRD_CFG_SYNC_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) >> SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PRD */ +/* + * PERIOD (RW) + * + * Trigger period + */ +#define SEI_CTRL_TRG_PRD_PERIOD_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_TRG_PRD_PERIOD_SHIFT (0U) +#define SEI_CTRL_TRG_PRD_PERIOD_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_PERIOD_SHIFT) & SEI_CTRL_TRG_PRD_PERIOD_MASK) +#define SEI_CTRL_TRG_PRD_PERIOD_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_PERIOD_MASK) >> SEI_CTRL_TRG_PRD_PERIOD_SHIFT) + +/* Bitfield definition for register of struct array CTRL: OUT_CFG */ +/* + * OUT3_EN (RW) + * + * Enable trigger 3 + * 0: disable trigger 3 + * 1: enable trigger 3 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK (0x80000000UL) +#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT (31U) +#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) + +/* + * OUT3_SEL (RW) + * + * Trigger 3 sigal selection + * 0: trigger out 0 + * 1: trigger out 1 + * ... + * 7: trigger out 7 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK (0x7000000UL) +#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT (24U) +#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) + +/* + * OUT2_EN (RW) + * + * Enable trigger 2 + * 0: disable trigger 2 + * 1: enable trigger 2 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK (0x800000UL) +#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT (23U) +#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) + +/* + * OUT2_SEL (RW) + * + * Trigger 2 sigal selection + * 0: trigger out 0 + * 1: trigger out 1 + * ... + * 7: trigger out 7 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK (0x70000UL) +#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT (16U) +#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) + +/* + * OUT1_EN (RW) + * + * Enable trigger 1 + * 0: disable trigger 1 + * 1: enable trigger 1 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK (0x8000U) +#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT (15U) +#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) + +/* + * OUT1_SEL (RW) + * + * Trigger 1 sigal selection + * 0: trigger out 0 + * 1: trigger out 1 + * ... + * 7: trigger out 7 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK (0x700U) +#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT (8U) +#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) + +/* + * OUT0_EN (RW) + * + * Enable trigger 0 + * 0: disable trigger 1 + * 1: enable trigger 1 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK (0x80U) +#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT (7U) +#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) + +/* + * OUT0_SEL (RW) + * + * Trigger 0 sigal selection + * 0: trigger out 0 + * 1: trigger out 1 + * ... + * 7: trigger out 7 + */ +#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK (0x7U) +#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT (0U) +#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) +#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PRD_STS */ +/* + * TRIGERED (RO) + * + * Period has been triggered + * 0: Not triggered + * 1: Triggered + */ +#define SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK (0x100000UL) +#define SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT (20U) +#define SEI_CTRL_TRG_PRD_STS_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK) >> SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT) + +/* + * ARMED (RO) + * + * Waiting for trigger + * 0: Not in waiting status + * 1: In waiting status + */ +#define SEI_CTRL_TRG_PRD_STS_ARMED_MASK (0x10000UL) +#define SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT (16U) +#define SEI_CTRL_TRG_PRD_STS_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_ARMED_MASK) >> SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PRD_CNT */ +/* + * PERIOD_CNT (RO) + * + * Trigger period counter + */ +#define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT (0U) +#define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK) >> SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: 0 */ +/* + * CMD_TRIGGER0 (RW) + * + * Trigger command + */ +#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT (0U) +#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) +#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) >> SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) + +/* Bitfield definition for register of struct array CTRL: 0 */ +/* + * TRIGGER0_TIME (RO) + * + * Trigger time + */ +#define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT (0U) +#define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK) >> SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT) + +/* Bitfield definition for register of struct array CTRL: MODE */ +/* + * WLEN (RW) + * + * word length + * 0: 1 bit + * 1: 2 bit + * ... + * 31: 32 bit + */ +#define SEI_CTRL_CMD_MODE_WLEN_MASK (0x1F0000UL) +#define SEI_CTRL_CMD_MODE_WLEN_SHIFT (16U) +#define SEI_CTRL_CMD_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WLEN_SHIFT) & SEI_CTRL_CMD_MODE_WLEN_MASK) +#define SEI_CTRL_CMD_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WLEN_MASK) >> SEI_CTRL_CMD_MODE_WLEN_SHIFT) + +/* + * WORDER (RW) + * + * word order + * 0: sample as bit order + * 1: different from bit order + */ +#define SEI_CTRL_CMD_MODE_WORDER_MASK (0x800U) +#define SEI_CTRL_CMD_MODE_WORDER_SHIFT (11U) +#define SEI_CTRL_CMD_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WORDER_SHIFT) & SEI_CTRL_CMD_MODE_WORDER_MASK) +#define SEI_CTRL_CMD_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WORDER_MASK) >> SEI_CTRL_CMD_MODE_WORDER_SHIFT) + +/* + * BORDER (RW) + * + * bit order + * 0: LSB first + * 1: MSB first + */ +#define SEI_CTRL_CMD_MODE_BORDER_MASK (0x400U) +#define SEI_CTRL_CMD_MODE_BORDER_SHIFT (10U) +#define SEI_CTRL_CMD_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_BORDER_SHIFT) & SEI_CTRL_CMD_MODE_BORDER_MASK) +#define SEI_CTRL_CMD_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_BORDER_MASK) >> SEI_CTRL_CMD_MODE_BORDER_SHIFT) + +/* + * SIGNED (RW) + * + * Signed + * 0: unsigned value + * 1: signed value + */ +#define SEI_CTRL_CMD_MODE_SIGNED_MASK (0x200U) +#define SEI_CTRL_CMD_MODE_SIGNED_SHIFT (9U) +#define SEI_CTRL_CMD_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_SIGNED_SHIFT) & SEI_CTRL_CMD_MODE_SIGNED_MASK) +#define SEI_CTRL_CMD_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_SIGNED_MASK) >> SEI_CTRL_CMD_MODE_SIGNED_SHIFT) + +/* + * REWIND (WC) + * + * Write 1 to rewind read/write pointer, this is a self clear bit + */ +#define SEI_CTRL_CMD_MODE_REWIND_MASK (0x100U) +#define SEI_CTRL_CMD_MODE_REWIND_SHIFT (8U) +#define SEI_CTRL_CMD_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_REWIND_SHIFT) & SEI_CTRL_CMD_MODE_REWIND_MASK) +#define SEI_CTRL_CMD_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_REWIND_MASK) >> SEI_CTRL_CMD_MODE_REWIND_SHIFT) + +/* + * MODE (RW) + * + * Data mode + * 0: data mode + * 1: check mode + * 2: CRC mode + */ +#define SEI_CTRL_CMD_MODE_MODE_MASK (0x3U) +#define SEI_CTRL_CMD_MODE_MODE_SHIFT (0U) +#define SEI_CTRL_CMD_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_MODE_SHIFT) & SEI_CTRL_CMD_MODE_MODE_MASK) +#define SEI_CTRL_CMD_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_MODE_MASK) >> SEI_CTRL_CMD_MODE_MODE_SHIFT) + +/* Bitfield definition for register of struct array CTRL: IDX */ +/* + * LAST_BIT (RW) + * + * Last bit index for tranceive + */ +#define SEI_CTRL_CMD_IDX_LAST_BIT_MASK (0x1F000000UL) +#define SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT (24U) +#define SEI_CTRL_CMD_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) +#define SEI_CTRL_CMD_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) >> SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) + +/* + * FIRST_BIT (RW) + * + * First bit index for tranceive + */ +#define SEI_CTRL_CMD_IDX_FIRST_BIT_MASK (0x1F0000UL) +#define SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT (16U) +#define SEI_CTRL_CMD_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) +#define SEI_CTRL_CMD_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) >> SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) + +/* + * MAX_BIT (RW) + * + * Highest bit index + */ +#define SEI_CTRL_CMD_IDX_MAX_BIT_MASK (0x1F00U) +#define SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT (8U) +#define SEI_CTRL_CMD_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) +#define SEI_CTRL_CMD_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) >> SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) + +/* + * MIN_BIT (RW) + * + * Lowest bit index + */ +#define SEI_CTRL_CMD_IDX_MIN_BIT_MASK (0x1FU) +#define SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT (0U) +#define SEI_CTRL_CMD_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) +#define SEI_CTRL_CMD_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) >> SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: GOLD */ +/* + * GOLD_VALUE (RW) + * + * Gold value for check mode + */ +#define SEI_CTRL_CMD_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_GOLD_GOLD_VALUE_SHIFT (0U) +#define SEI_CTRL_CMD_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_GOLD_GOLD_VALUE_SHIFT) & SEI_CTRL_CMD_GOLD_GOLD_VALUE_MASK) +#define SEI_CTRL_CMD_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_GOLD_GOLD_VALUE_MASK) >> SEI_CTRL_CMD_GOLD_GOLD_VALUE_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CRCINIT */ +/* + * CRC_INIT (RW) + * + * CRC initial value + */ +#define SEI_CTRL_CMD_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_CRCINIT_CRC_INIT_SHIFT (0U) +#define SEI_CTRL_CMD_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CRCINIT_CRC_INIT_SHIFT) & SEI_CTRL_CMD_CRCINIT_CRC_INIT_MASK) +#define SEI_CTRL_CMD_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CRCINIT_CRC_INIT_MASK) >> SEI_CTRL_CMD_CRCINIT_CRC_INIT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CRCPOLY */ +/* + * CRC_POLY (RW) + * + * CRC polymonial + */ +#define SEI_CTRL_CMD_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_CRCPOLY_CRC_POLY_SHIFT (0U) +#define SEI_CTRL_CMD_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CRCPOLY_CRC_POLY_SHIFT) & SEI_CTRL_CMD_CRCPOLY_CRC_POLY_MASK) +#define SEI_CTRL_CMD_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CRCPOLY_CRC_POLY_MASK) >> SEI_CTRL_CMD_CRCPOLY_CRC_POLY_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CMD */ +/* + * DATA (RW) + * + * DATA + */ +#define SEI_CTRL_CMD_CMD_DATA_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_CMD_DATA_SHIFT (0U) +#define SEI_CTRL_CMD_CMD_DATA_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CMD_DATA_SHIFT) & SEI_CTRL_CMD_CMD_DATA_MASK) +#define SEI_CTRL_CMD_CMD_DATA_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CMD_DATA_MASK) >> SEI_CTRL_CMD_CMD_DATA_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SET */ +/* + * DATA_SET (RW) + * + * DATA bit set + */ +#define SEI_CTRL_CMD_SET_DATA_SET_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_SET_DATA_SET_SHIFT (0U) +#define SEI_CTRL_CMD_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_SET_DATA_SET_SHIFT) & SEI_CTRL_CMD_SET_DATA_SET_MASK) +#define SEI_CTRL_CMD_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_SET_DATA_SET_MASK) >> SEI_CTRL_CMD_SET_DATA_SET_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CLR */ +/* + * DATA_CLR (RW) + * + * DATA bit clear + */ +#define SEI_CTRL_CMD_CLR_DATA_CLR_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT (0U) +#define SEI_CTRL_CMD_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) +#define SEI_CTRL_CMD_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) >> SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) + +/* Bitfield definition for register of struct array CTRL: INV */ +/* + * DATA_TGL (RW) + * + * DATA bit toggle + */ +#define SEI_CTRL_CMD_INV_DATA_TGL_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_INV_DATA_TGL_SHIFT (0U) +#define SEI_CTRL_CMD_INV_DATA_TGL_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) +#define SEI_CTRL_CMD_INV_DATA_TGL_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) >> SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: IN */ +/* + * DATA_IN (RO) + * + * Commad input + */ +#define SEI_CTRL_CMD_IN_DATA_IN_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_IN_DATA_IN_SHIFT (0U) +#define SEI_CTRL_CMD_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IN_DATA_IN_MASK) >> SEI_CTRL_CMD_IN_DATA_IN_SHIFT) + +/* Bitfield definition for register of struct array CTRL: OUT */ +/* + * DATA_OUT (RO) + * + * Command output + */ +#define SEI_CTRL_CMD_OUT_DATA_OUT_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT (0U) +#define SEI_CTRL_CMD_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_OUT_DATA_OUT_MASK) >> SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: STS */ +/* + * CRC_IDX (RO) + * + * CRC index + */ +#define SEI_CTRL_CMD_STS_CRC_IDX_MASK (0x1F000000UL) +#define SEI_CTRL_CMD_STS_CRC_IDX_SHIFT (24U) +#define SEI_CTRL_CMD_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_CRC_IDX_MASK) >> SEI_CTRL_CMD_STS_CRC_IDX_SHIFT) + +/* + * WORD_IDX (RO) + * + * Word index + */ +#define SEI_CTRL_CMD_STS_WORD_IDX_MASK (0x1F0000UL) +#define SEI_CTRL_CMD_STS_WORD_IDX_SHIFT (16U) +#define SEI_CTRL_CMD_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_IDX_MASK) >> SEI_CTRL_CMD_STS_WORD_IDX_SHIFT) + +/* + * WORD_CNT (RO) + * + * Word counter + */ +#define SEI_CTRL_CMD_STS_WORD_CNT_MASK (0x1F00U) +#define SEI_CTRL_CMD_STS_WORD_CNT_SHIFT (8U) +#define SEI_CTRL_CMD_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_CNT_MASK) >> SEI_CTRL_CMD_STS_WORD_CNT_SHIFT) + +/* + * BIT_IDX (RO) + * + * Bit index + */ +#define SEI_CTRL_CMD_STS_BIT_IDX_MASK (0x1FU) +#define SEI_CTRL_CMD_STS_BIT_IDX_SHIFT (0U) +#define SEI_CTRL_CMD_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_BIT_IDX_MASK) >> SEI_CTRL_CMD_STS_BIT_IDX_SHIFT) + +/* Bitfield definition for register of struct array CTRL: MIN */ +/* + * CMD_MIN (RW) + * + * minimum command value + */ +#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) +#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) >> SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) + +/* Bitfield definition for register of struct array CTRL: MAX */ +/* + * CMD_MAX (RW) + * + * maximum command value + */ +#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) +#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) >> SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) + +/* Bitfield definition for register of struct array CTRL: MSK */ +/* + * CMD_MASK (RW) + * + * compare mask + */ +#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) +#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) >> SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PTA */ +/* + * PTR3 (RW) + * + * pointer3 + */ +#define SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK (0xFF000000UL) +#define SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT (24U) +#define SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) +#define SEI_CTRL_CMD_TABLE_PTA_PTR3_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) + +/* + * PTR2 (RW) + * + * pointer2 + */ +#define SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK (0xFF0000UL) +#define SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT (16U) +#define SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) +#define SEI_CTRL_CMD_TABLE_PTA_PTR2_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) + +/* + * PTR1 (RW) + * + * pointer1 + */ +#define SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK (0xFF00U) +#define SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT (8U) +#define SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) +#define SEI_CTRL_CMD_TABLE_PTA_PTR1_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) + +/* + * PTR0 (RW) + * + * pointer0 + */ +#define SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK (0xFFU) +#define SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) +#define SEI_CTRL_CMD_TABLE_PTA_PTR0_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PTB */ +/* + * PTR7 (RW) + * + * pointer7 + */ +#define SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK (0xFF000000UL) +#define SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT (24U) +#define SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) +#define SEI_CTRL_CMD_TABLE_PTB_PTR7_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) + +/* + * PTR6 (RW) + * + * pointer6 + */ +#define SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK (0xFF0000UL) +#define SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT (16U) +#define SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) +#define SEI_CTRL_CMD_TABLE_PTB_PTR6_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) + +/* + * PTR5 (RW) + * + * pointer5 + */ +#define SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK (0xFF00U) +#define SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT (8U) +#define SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) +#define SEI_CTRL_CMD_TABLE_PTB_PTR5_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) + +/* + * PTR4 (RW) + * + * pointer4 + */ +#define SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK (0xFFU) +#define SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) +#define SEI_CTRL_CMD_TABLE_PTB_PTR4_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PTC */ +/* + * PTR11 (RW) + * + * pointer11 + */ +#define SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK (0xFF000000UL) +#define SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT (24U) +#define SEI_CTRL_CMD_TABLE_PTC_PTR11_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK) +#define SEI_CTRL_CMD_TABLE_PTC_PTR11_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT) + +/* + * PTR10 (RW) + * + * pointer10 + */ +#define SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK (0xFF0000UL) +#define SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT (16U) +#define SEI_CTRL_CMD_TABLE_PTC_PTR10_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK) +#define SEI_CTRL_CMD_TABLE_PTC_PTR10_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT) + +/* + * PTR9 (RW) + * + * pointer9 + */ +#define SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK (0xFF00U) +#define SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT (8U) +#define SEI_CTRL_CMD_TABLE_PTC_PTR9_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK) +#define SEI_CTRL_CMD_TABLE_PTC_PTR9_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT) + +/* + * PTR8 (RW) + * + * pointer8 + */ +#define SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK (0xFFU) +#define SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_PTC_PTR8_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK) +#define SEI_CTRL_CMD_TABLE_PTC_PTR8_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT) + +/* Bitfield definition for register of struct array CTRL: PTD */ +/* + * PTR15 (RW) + * + * pointer15 + */ +#define SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK (0xFF000000UL) +#define SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT (24U) +#define SEI_CTRL_CMD_TABLE_PTD_PTR15_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK) +#define SEI_CTRL_CMD_TABLE_PTD_PTR15_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT) + +/* + * PTR14 (RW) + * + * pointer14 + */ +#define SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK (0xFF0000UL) +#define SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT (16U) +#define SEI_CTRL_CMD_TABLE_PTD_PTR14_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK) +#define SEI_CTRL_CMD_TABLE_PTD_PTR14_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT) + +/* + * PTR13 (RW) + * + * pointer13 + */ +#define SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK (0xFF00U) +#define SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT (8U) +#define SEI_CTRL_CMD_TABLE_PTD_PTR13_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK) +#define SEI_CTRL_CMD_TABLE_PTD_PTR13_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT) + +/* + * PTR12 (RW) + * + * pointer12 + */ +#define SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK (0xFFU) +#define SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT (0U) +#define SEI_CTRL_CMD_TABLE_PTD_PTR12_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK) +#define SEI_CTRL_CMD_TABLE_PTD_PTR12_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT) + +/* Bitfield definition for register of struct array CTRL: 0_1 */ +/* + * POINTER (RW) + * + * pointer + */ +#define SEI_CTRL_LATCH_TRAN_POINTER_MASK (0xFF000000UL) +#define SEI_CTRL_LATCH_TRAN_POINTER_SHIFT (24U) +#define SEI_CTRL_LATCH_TRAN_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) +#define SEI_CTRL_LATCH_TRAN_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) >> SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) + +/* + * CFG_TM (RW) + * + * timeout + * 0: high + * 1: low + * 2: rise + * 3: fall + */ +#define SEI_CTRL_LATCH_TRAN_CFG_TM_MASK (0x30000UL) +#define SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT (16U) +#define SEI_CTRL_LATCH_TRAN_CFG_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) +#define SEI_CTRL_LATCH_TRAN_CFG_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) + +/* + * CFG_TXD (RW) + * + * data send + * 0: high + * 1: low + * 2: rise + * 3: fall + */ +#define SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK (0x3000U) +#define SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT (12U) +#define SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) +#define SEI_CTRL_LATCH_TRAN_CFG_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) + +/* + * CFG_CLK (RW) + * + * clock + * 0: high + * 1: low + * 2: rise + * 3: fall + */ +#define SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK (0xC00U) +#define SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT (10U) +#define SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) +#define SEI_CTRL_LATCH_TRAN_CFG_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) + +/* + * CFG_PTR (RW) + * + * pointer + * 0: match + * 1: not match + * 2:entry + * 3:leave + */ +#define SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK (0x300U) +#define SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT (8U) +#define SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) +#define SEI_CTRL_LATCH_TRAN_CFG_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) + +/* + * OV_TM (RW) + * + * override timeout check + */ +#define SEI_CTRL_LATCH_TRAN_OV_TM_MASK (0x10U) +#define SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT (4U) +#define SEI_CTRL_LATCH_TRAN_OV_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) +#define SEI_CTRL_LATCH_TRAN_OV_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) + +/* + * OV_TXD (RW) + * + * override TX data check + */ +#define SEI_CTRL_LATCH_TRAN_OV_TXD_MASK (0x4U) +#define SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT (2U) +#define SEI_CTRL_LATCH_TRAN_OV_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) +#define SEI_CTRL_LATCH_TRAN_OV_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) + +/* + * OV_CLK (RW) + * + * override clock check + */ +#define SEI_CTRL_LATCH_TRAN_OV_CLK_MASK (0x2U) +#define SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT (1U) +#define SEI_CTRL_LATCH_TRAN_OV_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) +#define SEI_CTRL_LATCH_TRAN_OV_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) + +/* + * OV_PTR (RW) + * + * override pointer check + */ +#define SEI_CTRL_LATCH_TRAN_OV_PTR_MASK (0x1U) +#define SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT (0U) +#define SEI_CTRL_LATCH_TRAN_OV_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) +#define SEI_CTRL_LATCH_TRAN_OV_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) + +/* Bitfield definition for register of struct array CTRL: CFG */ +/* + * EN (RW) + * + * Enable latch + * 0: disable + * 1: enable + */ +#define SEI_CTRL_LATCH_CFG_EN_MASK (0x80000000UL) +#define SEI_CTRL_LATCH_CFG_EN_SHIFT (31U) +#define SEI_CTRL_LATCH_CFG_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_EN_SHIFT) & SEI_CTRL_LATCH_CFG_EN_MASK) +#define SEI_CTRL_LATCH_CFG_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_EN_MASK) >> SEI_CTRL_LATCH_CFG_EN_SHIFT) + +/* + * SELECT (RW) + * + * Output select + * 0: state0-state1 + * 1: state1-state2 + * 2: state2-state3 + * 3: state3-state0 + */ +#define SEI_CTRL_LATCH_CFG_SELECT_MASK (0x7000000UL) +#define SEI_CTRL_LATCH_CFG_SELECT_SHIFT (24U) +#define SEI_CTRL_LATCH_CFG_SELECT_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_SELECT_SHIFT) & SEI_CTRL_LATCH_CFG_SELECT_MASK) +#define SEI_CTRL_LATCH_CFG_SELECT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_SELECT_MASK) >> SEI_CTRL_LATCH_CFG_SELECT_SHIFT) + +/* + * DELAY (RW) + * + * Delay in system clock cycle, for state transition + */ +#define SEI_CTRL_LATCH_CFG_DELAY_MASK (0xFFFFU) +#define SEI_CTRL_LATCH_CFG_DELAY_SHIFT (0U) +#define SEI_CTRL_LATCH_CFG_DELAY_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_DELAY_SHIFT) & SEI_CTRL_LATCH_CFG_DELAY_MASK) +#define SEI_CTRL_LATCH_CFG_DELAY_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_DELAY_MASK) >> SEI_CTRL_LATCH_CFG_DELAY_SHIFT) + +/* Bitfield definition for register of struct array CTRL: TIME */ +/* + * LAT_TIME (RO) + * + * Latch time + */ +#define SEI_CTRL_LATCH_TIME_LAT_TIME_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT (0U) +#define SEI_CTRL_LATCH_TIME_LAT_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TIME_LAT_TIME_MASK) >> SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT) + +/* Bitfield definition for register of struct array CTRL: STS */ +/* + * STATE (RO) + * + * State + */ +#define SEI_CTRL_LATCH_STS_STATE_MASK (0x7000000UL) +#define SEI_CTRL_LATCH_STS_STATE_SHIFT (24U) +#define SEI_CTRL_LATCH_STS_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_STATE_MASK) >> SEI_CTRL_LATCH_STS_STATE_SHIFT) + +/* + * LAT_CNT (RO) + * + * Latch counter + */ +#define SEI_CTRL_LATCH_STS_LAT_CNT_MASK (0xFFFFU) +#define SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT (0U) +#define SEI_CTRL_LATCH_STS_LAT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_LAT_CNT_MASK) >> SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_EN */ +/* + * ACC_EN (RW) + * + * Position include acceleration + */ +#define SEI_CTRL_POS_SMP_EN_ACC_EN_MASK (0x80000000UL) +#define SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT (31U) +#define SEI_CTRL_POS_SMP_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) +#define SEI_CTRL_POS_SMP_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) + +/* + * ACC_SEL (RW) + * + * Data register for acceleration transfer + */ +#define SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK (0x1F000000UL) +#define SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT (24U) +#define SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) +#define SEI_CTRL_POS_SMP_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) + +/* + * SPD_EN (RW) + * + * Position include speed + */ +#define SEI_CTRL_POS_SMP_EN_SPD_EN_MASK (0x800000UL) +#define SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT (23U) +#define SEI_CTRL_POS_SMP_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) +#define SEI_CTRL_POS_SMP_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) + +/* + * SPD_SEL (RW) + * + * Data register for speed transfer + */ +#define SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK (0x1F0000UL) +#define SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT (16U) +#define SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) +#define SEI_CTRL_POS_SMP_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) + +/* + * REV_EN (RW) + * + * Position include revolution + */ +#define SEI_CTRL_POS_SMP_EN_REV_EN_MASK (0x8000U) +#define SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT (15U) +#define SEI_CTRL_POS_SMP_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) +#define SEI_CTRL_POS_SMP_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) >> SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) + +/* + * REV_SEL (RW) + * + * Data register for revolution transfer + */ +#define SEI_CTRL_POS_SMP_EN_REV_SEL_MASK (0x1F00U) +#define SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT (8U) +#define SEI_CTRL_POS_SMP_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) +#define SEI_CTRL_POS_SMP_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) + +/* + * POS_EN (RW) + * + * Position include position + */ +#define SEI_CTRL_POS_SMP_EN_POS_EN_MASK (0x80U) +#define SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT (7U) +#define SEI_CTRL_POS_SMP_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) +#define SEI_CTRL_POS_SMP_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) >> SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) + +/* + * POS_SEL (RW) + * + * Data register for position transfer + */ +#define SEI_CTRL_POS_SMP_EN_POS_SEL_MASK (0x1FU) +#define SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT (0U) +#define SEI_CTRL_POS_SMP_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) +#define SEI_CTRL_POS_SMP_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_CFG */ +/* + * ONCE (RW) + * + * Sample one time + * 0: Sample during windows time + * 1: Close sample window after first sample + */ +#define SEI_CTRL_POS_SMP_CFG_ONCE_MASK (0x1000000UL) +#define SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT (24U) +#define SEI_CTRL_POS_SMP_CFG_ONCE_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) +#define SEI_CTRL_POS_SMP_CFG_ONCE_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) >> SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) + +/* + * LAT_SEL (RW) + * + * Latch selection + * 0: latch 0 + * 1: latch 1 + * 2: latch 2 + * 3: latch 3 + */ +#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK (0x30000UL) +#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT (16U) +#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) +#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) + +/* + * WINDOW (RW) + * + * Sample window, in clock cycle + */ +#define SEI_CTRL_POS_SMP_CFG_WINDOW_MASK (0xFFFFU) +#define SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT (0U) +#define SEI_CTRL_POS_SMP_CFG_WINDOW_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) +#define SEI_CTRL_POS_SMP_CFG_WINDOW_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) >> SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_DAT */ +/* + * DAT_SEL (RW) + * + * Data register sampled, each bit represent a data register + */ +#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT (0U) +#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) +#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_POS */ +/* + * POS (RW) + * + * Sample override position + */ +#define SEI_CTRL_POS_SMP_POS_POS_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_SMP_POS_POS_SHIFT (0U) +#define SEI_CTRL_POS_SMP_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_POS_POS_SHIFT) & SEI_CTRL_POS_SMP_POS_POS_MASK) +#define SEI_CTRL_POS_SMP_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_POS_POS_MASK) >> SEI_CTRL_POS_SMP_POS_POS_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_REV */ +/* + * REV (RW) + * + * Sample override revolution + */ +#define SEI_CTRL_POS_SMP_REV_REV_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_SMP_REV_REV_SHIFT (0U) +#define SEI_CTRL_POS_SMP_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_REV_REV_SHIFT) & SEI_CTRL_POS_SMP_REV_REV_MASK) +#define SEI_CTRL_POS_SMP_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_REV_REV_MASK) >> SEI_CTRL_POS_SMP_REV_REV_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_SPD */ +/* + * SPD (RW) + * + * Sample override speed + */ +#define SEI_CTRL_POS_SMP_SPD_SPD_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_SMP_SPD_SPD_SHIFT (0U) +#define SEI_CTRL_POS_SMP_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) +#define SEI_CTRL_POS_SMP_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) >> SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_ACC */ +/* + * ACC (RW) + * + * Sample override accelerate + */ +#define SEI_CTRL_POS_SMP_ACC_ACC_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_SMP_ACC_ACC_SHIFT (0U) +#define SEI_CTRL_POS_SMP_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) +#define SEI_CTRL_POS_SMP_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) >> SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_EN */ +/* + * ACC_EN (RW) + * + * Position include acceleration + */ +#define SEI_CTRL_POS_UPD_EN_ACC_EN_MASK (0x80000000UL) +#define SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT (31U) +#define SEI_CTRL_POS_UPD_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) +#define SEI_CTRL_POS_UPD_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) + +/* + * ACC_SEL (RW) + * + * Data register for acceleration transfer + */ +#define SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK (0x1F000000UL) +#define SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT (24U) +#define SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) +#define SEI_CTRL_POS_UPD_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) + +/* + * SPD_EN (RW) + * + * Position include speed + */ +#define SEI_CTRL_POS_UPD_EN_SPD_EN_MASK (0x800000UL) +#define SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT (23U) +#define SEI_CTRL_POS_UPD_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) +#define SEI_CTRL_POS_UPD_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) + +/* + * SPD_SEL (RW) + * + * Data register for speed transfer + */ +#define SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK (0x1F0000UL) +#define SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT (16U) +#define SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) +#define SEI_CTRL_POS_UPD_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) + +/* + * REV_EN (RW) + * + * Position include revolution + */ +#define SEI_CTRL_POS_UPD_EN_REV_EN_MASK (0x8000U) +#define SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT (15U) +#define SEI_CTRL_POS_UPD_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) +#define SEI_CTRL_POS_UPD_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) >> SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) + +/* + * REV_SEL (RW) + * + * Data register for revolution transfer + */ +#define SEI_CTRL_POS_UPD_EN_REV_SEL_MASK (0x1F00U) +#define SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT (8U) +#define SEI_CTRL_POS_UPD_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) +#define SEI_CTRL_POS_UPD_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) + +/* + * POS_EN (RW) + * + * Position include position + */ +#define SEI_CTRL_POS_UPD_EN_POS_EN_MASK (0x80U) +#define SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT (7U) +#define SEI_CTRL_POS_UPD_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) +#define SEI_CTRL_POS_UPD_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) >> SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) + +/* + * POS_SEL (RW) + * + * Data register for position transfer + */ +#define SEI_CTRL_POS_UPD_EN_POS_SEL_MASK (0x1FU) +#define SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT (0U) +#define SEI_CTRL_POS_UPD_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) +#define SEI_CTRL_POS_UPD_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_CFG */ +/* + * TIME_OVRD (RW) + * + * Use override time + * 0: use time sample from motor group + * 1: use override time + */ +#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK (0x80000000UL) +#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT (31U) +#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) +#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) >> SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) + +/* + * ONERR (RW) + * + * Sample one time + * 0: Sample during windows time + * 1: Close sample window after first sample + */ +#define SEI_CTRL_POS_UPD_CFG_ONERR_MASK (0x1000000UL) +#define SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT (24U) +#define SEI_CTRL_POS_UPD_CFG_ONERR_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) +#define SEI_CTRL_POS_UPD_CFG_ONERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) >> SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) + +/* + * LAT_SEL (RW) + * + * Latch selection + * 0: latch 0 + * 1: latch 1 + * 2: latch 2 + * 3: latch 3 + */ +#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK (0x30000UL) +#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT (16U) +#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) +#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_DAT */ +/* + * DAT_SEL (RW) + * + * Data register sampled, each bit represent a data register + */ +#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT (0U) +#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) +#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_TIME */ +/* + * TIME (RW) + * + * Update override time + */ +#define SEI_CTRL_POS_UPD_TIME_TIME_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_UPD_TIME_TIME_SHIFT (0U) +#define SEI_CTRL_POS_UPD_TIME_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) +#define SEI_CTRL_POS_UPD_TIME_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) >> SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_POS */ +/* + * POS (RW) + * + * Update override position + */ +#define SEI_CTRL_POS_UPD_POS_POS_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_UPD_POS_POS_SHIFT (0U) +#define SEI_CTRL_POS_UPD_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_POS_POS_SHIFT) & SEI_CTRL_POS_UPD_POS_POS_MASK) +#define SEI_CTRL_POS_UPD_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_POS_POS_MASK) >> SEI_CTRL_POS_UPD_POS_POS_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_REV */ +/* + * REV (RW) + * + * Update override revolution + */ +#define SEI_CTRL_POS_UPD_REV_REV_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_UPD_REV_REV_SHIFT (0U) +#define SEI_CTRL_POS_UPD_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_REV_REV_SHIFT) & SEI_CTRL_POS_UPD_REV_REV_MASK) +#define SEI_CTRL_POS_UPD_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_REV_REV_MASK) >> SEI_CTRL_POS_UPD_REV_REV_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_SPD */ +/* + * SPD (RW) + * + * Update override speed + */ +#define SEI_CTRL_POS_UPD_SPD_SPD_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_UPD_SPD_SPD_SHIFT (0U) +#define SEI_CTRL_POS_UPD_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) +#define SEI_CTRL_POS_UPD_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) >> SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_ACC */ +/* + * ACC (RW) + * + * Update override accelerate + */ +#define SEI_CTRL_POS_UPD_ACC_ACC_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_UPD_ACC_ACC_SHIFT (0U) +#define SEI_CTRL_POS_UPD_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) +#define SEI_CTRL_POS_UPD_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) >> SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_VAL */ +/* + * ACC (RO) + * + * Position include acceleration + */ +#define SEI_CTRL_POS_SMP_VAL_ACC_MASK (0x80000000UL) +#define SEI_CTRL_POS_SMP_VAL_ACC_SHIFT (31U) +#define SEI_CTRL_POS_SMP_VAL_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_ACC_MASK) >> SEI_CTRL_POS_SMP_VAL_ACC_SHIFT) + +/* + * SPD (RO) + * + * Position include speed + */ +#define SEI_CTRL_POS_SMP_VAL_SPD_MASK (0x800000UL) +#define SEI_CTRL_POS_SMP_VAL_SPD_SHIFT (23U) +#define SEI_CTRL_POS_SMP_VAL_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_SPD_MASK) >> SEI_CTRL_POS_SMP_VAL_SPD_SHIFT) + +/* + * REV (RO) + * + * Position include revolution + */ +#define SEI_CTRL_POS_SMP_VAL_REV_MASK (0x8000U) +#define SEI_CTRL_POS_SMP_VAL_REV_SHIFT (15U) +#define SEI_CTRL_POS_SMP_VAL_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_REV_MASK) >> SEI_CTRL_POS_SMP_VAL_REV_SHIFT) + +/* + * POS (RO) + * + * Position include position + */ +#define SEI_CTRL_POS_SMP_VAL_POS_MASK (0x80U) +#define SEI_CTRL_POS_SMP_VAL_POS_SHIFT (7U) +#define SEI_CTRL_POS_SMP_VAL_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_POS_MASK) >> SEI_CTRL_POS_SMP_VAL_POS_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SMP_STS */ +/* + * OCCUR (RO) + * + * Sample occured + * 0: Sample not happened + * 1: Sample occured + */ +#define SEI_CTRL_POS_SMP_STS_OCCUR_MASK (0x1000000UL) +#define SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT (24U) +#define SEI_CTRL_POS_SMP_STS_OCCUR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_OCCUR_MASK) >> SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT) + +/* + * WIN_CNT (RO) + * + * Sample window counter + */ +#define SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK (0xFFFFU) +#define SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT (0U) +#define SEI_CTRL_POS_SMP_STS_WIN_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK) >> SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT) + +/* Bitfield definition for register of struct array CTRL: TIME_IN */ +/* + * TIME (RO) + * + * input time + */ +#define SEI_CTRL_POS_TIME_IN_TIME_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_TIME_IN_TIME_SHIFT (0U) +#define SEI_CTRL_POS_TIME_IN_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_TIME_IN_TIME_MASK) >> SEI_CTRL_POS_TIME_IN_TIME_SHIFT) + +/* Bitfield definition for register of struct array CTRL: POS_IN */ +/* + * POS (RO) + * + * Input position + */ +#define SEI_CTRL_POS_POS_IN_POS_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_POS_IN_POS_SHIFT (0U) +#define SEI_CTRL_POS_POS_IN_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_POS_IN_POS_MASK) >> SEI_CTRL_POS_POS_IN_POS_SHIFT) + +/* Bitfield definition for register of struct array CTRL: REV_IN */ +/* + * REV (RO) + * + * Input revolution + */ +#define SEI_CTRL_POS_REV_IN_REV_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_REV_IN_REV_SHIFT (0U) +#define SEI_CTRL_POS_REV_IN_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_REV_IN_REV_MASK) >> SEI_CTRL_POS_REV_IN_REV_SHIFT) + +/* Bitfield definition for register of struct array CTRL: SPD_IN */ +/* + * SPD (RO) + * + * Input speed + */ +#define SEI_CTRL_POS_SPD_IN_SPD_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_SPD_IN_SPD_SHIFT (0U) +#define SEI_CTRL_POS_SPD_IN_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SPD_IN_SPD_MASK) >> SEI_CTRL_POS_SPD_IN_SPD_SHIFT) + +/* Bitfield definition for register of struct array CTRL: ACC_IN */ +/* + * ACC (RO) + * + * Input accelerate + */ +#define SEI_CTRL_POS_ACC_IN_ACC_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_POS_ACC_IN_ACC_SHIFT (0U) +#define SEI_CTRL_POS_ACC_IN_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_ACC_IN_ACC_MASK) >> SEI_CTRL_POS_ACC_IN_ACC_SHIFT) + +/* Bitfield definition for register of struct array CTRL: UPD_STS */ +/* + * UPD_ERR (RO) + * + * Update error + * 0: data receive normally + * 1: data receive error + */ +#define SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK (0x1000000UL) +#define SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT (24U) +#define SEI_CTRL_POS_UPD_STS_UPD_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK) >> SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT) + +/* Bitfield definition for register of struct array CTRL: INT_EN */ +/* + * TRG_ERR3 (RW) + * + * Trigger3 failed + */ +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK (0x80000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT (31U) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) + +/* + * TRG_ERR2 (RW) + * + * Trigger2 failed + */ +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK (0x40000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT (30U) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) + +/* + * TRG_ERR1 (RW) + * + * Trigger1 failed + */ +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK (0x20000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT (29U) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) + +/* + * TRG_ERR0 (RW) + * + * Trigger0 failed + */ +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK (0x10000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT (28U) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) + +/* + * TRIGER3 (RW) + * + * Trigger3 + */ +#define SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK (0x8000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT (27U) +#define SEI_CTRL_IRQ_INT_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) + +/* + * TRIGER2 (RW) + * + * Trigger2 + */ +#define SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK (0x4000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT (26U) +#define SEI_CTRL_IRQ_INT_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) + +/* + * TRIGER1 (RW) + * + * Trigger1 + */ +#define SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK (0x2000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT (25U) +#define SEI_CTRL_IRQ_INT_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) + +/* + * TRIGER0 (RW) + * + * Trigger0 + */ +#define SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK (0x1000000UL) +#define SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT (24U) +#define SEI_CTRL_IRQ_INT_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) + +/* + * SMP_ERR (RW) + * + * Sample error + */ +#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK (0x100000UL) +#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT (20U) +#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) +#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) + +/* + * LATCH3 (RW) + * + * Latch3 + */ +#define SEI_CTRL_IRQ_INT_EN_LATCH3_MASK (0x80000UL) +#define SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT (19U) +#define SEI_CTRL_IRQ_INT_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) +#define SEI_CTRL_IRQ_INT_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) + +/* + * LATCH2 (RW) + * + * Latch2 + */ +#define SEI_CTRL_IRQ_INT_EN_LATCH2_MASK (0x40000UL) +#define SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT (18U) +#define SEI_CTRL_IRQ_INT_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) +#define SEI_CTRL_IRQ_INT_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) + +/* + * LATCH1 (RW) + * + * Latch1 + */ +#define SEI_CTRL_IRQ_INT_EN_LATCH1_MASK (0x20000UL) +#define SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT (17U) +#define SEI_CTRL_IRQ_INT_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) +#define SEI_CTRL_IRQ_INT_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) + +/* + * LATCH0 (RW) + * + * Latch0 + */ +#define SEI_CTRL_IRQ_INT_EN_LATCH0_MASK (0x10000UL) +#define SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT (16U) +#define SEI_CTRL_IRQ_INT_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) +#define SEI_CTRL_IRQ_INT_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) + +/* + * TIMEOUT (RW) + * + * Timeout + */ +#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK (0x2000U) +#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT (13U) +#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) +#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) + +/* + * TRX_ERR (RW) + * + * Transfer error + */ +#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK (0x1000U) +#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT (12U) +#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) +#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) + +/* + * INSTR1_END (RW) + * + * Instruction 1 end + */ +#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK (0x800U) +#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT (11U) +#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) +#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) + +/* + * INSTR0_END (RW) + * + * Instruction 0 end + */ +#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK (0x400U) +#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT (10U) +#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) +#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) + +/* + * PTR1_END (RW) + * + * Pointer 1 end + */ +#define SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK (0x200U) +#define SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT (9U) +#define SEI_CTRL_IRQ_INT_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) +#define SEI_CTRL_IRQ_INT_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) + +/* + * PTR0_END (RW) + * + * Pointer 0 end + */ +#define SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK (0x100U) +#define SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT (8U) +#define SEI_CTRL_IRQ_INT_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) +#define SEI_CTRL_IRQ_INT_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) + +/* + * INSTR1_ST (RW) + * + * Instruction 1 start + */ +#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK (0x80U) +#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT (7U) +#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) +#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) + +/* + * INSTR0_ST (RW) + * + * Instruction 0 start + */ +#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK (0x40U) +#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT (6U) +#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) +#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) + +/* + * PTR1_ST (RW) + * + * Pointer 1 start + */ +#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK (0x20U) +#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT (5U) +#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) +#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) + +/* + * PTR0_ST (RW) + * + * Pointer 0 start + */ +#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK (0x10U) +#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT (4U) +#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) +#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) + +/* + * WDOG (RW) + * + * Watch dog + */ +#define SEI_CTRL_IRQ_INT_EN_WDOG_MASK (0x4U) +#define SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT (2U) +#define SEI_CTRL_IRQ_INT_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) +#define SEI_CTRL_IRQ_INT_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) >> SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) + +/* + * EXECPT (RW) + * + * Exception + */ +#define SEI_CTRL_IRQ_INT_EN_EXECPT_MASK (0x2U) +#define SEI_CTRL_IRQ_INT_EN_EXECPT_SHIFT (1U) +#define SEI_CTRL_IRQ_INT_EN_EXECPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_EXECPT_SHIFT) & SEI_CTRL_IRQ_INT_EN_EXECPT_MASK) +#define SEI_CTRL_IRQ_INT_EN_EXECPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_EXECPT_MASK) >> SEI_CTRL_IRQ_INT_EN_EXECPT_SHIFT) + +/* + * STALL (RW) + * + * Stall + */ +#define SEI_CTRL_IRQ_INT_EN_STALL_MASK (0x1U) +#define SEI_CTRL_IRQ_INT_EN_STALL_SHIFT (0U) +#define SEI_CTRL_IRQ_INT_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) +#define SEI_CTRL_IRQ_INT_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) >> SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: INT_FLAG */ +/* + * TRG_ERR3 (W1C) + * + * Trigger3 failed + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK (0x80000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT (31U) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) + +/* + * TRG_ERR2 (W1C) + * + * Trigger2 failed + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK (0x40000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT (30U) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) + +/* + * TRG_ERR1 (W1C) + * + * Trigger1 failed + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK (0x20000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT (29U) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) + +/* + * TRG_ERR0 (W1C) + * + * Trigger0 failed + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK (0x10000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT (28U) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) + +/* + * TRIGER3 (W1C) + * + * Trigger3 + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK (0x8000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT (27U) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) + +/* + * TRIGER2 (W1C) + * + * Trigger2 + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK (0x4000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT (26U) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) + +/* + * TRIGER1 (W1C) + * + * Trigger1 + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK (0x2000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT (25U) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) + +/* + * TRIGER0 (W1C) + * + * Trigger0 + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK (0x1000000UL) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT (24U) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) + +/* + * SMP_ERR (W1C) + * + * Sample error + */ +#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK (0x100000UL) +#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT (20U) +#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) + +/* + * LATCH3 (W1C) + * + * Latch3 + */ +#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK (0x80000UL) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT (19U) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) + +/* + * LATCH2 (W1C) + * + * Latch2 + */ +#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK (0x40000UL) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT (18U) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) + +/* + * LATCH1 (W1C) + * + * Latch1 + */ +#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK (0x20000UL) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT (17U) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) + +/* + * LATCH0 (W1C) + * + * Latch0 + */ +#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK (0x10000UL) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT (16U) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) + +/* + * TIMEOUT (W1C) + * + * Timeout + */ +#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK (0x2000U) +#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT (13U) +#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) + +/* + * TRX_ERR (W1C) + * + * Transfer error + */ +#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK (0x1000U) +#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT (12U) +#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) + +/* + * INSTR1_END (W1C) + * + * Instruction 1 end + */ +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK (0x800U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT (11U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) + +/* + * INSTR0_END (W1C) + * + * Instruction 0 end + */ +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK (0x400U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT (10U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) + +/* + * PTR1_END (W1C) + * + * Pointer 1 end + */ +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK (0x200U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT (9U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) + +/* + * PTR0_END (W1C) + * + * Pointer 0 end + */ +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK (0x100U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT (8U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) + +/* + * INSTR1_ST (W1C) + * + * Instruction 1 start + */ +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK (0x80U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT (7U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) + +/* + * INSTR0_ST (W1C) + * + * Instruction 0 start + */ +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK (0x40U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT (6U) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) + +/* + * PTR1_ST (W1C) + * + * Pointer 1 start + */ +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK (0x20U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT (5U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) + +/* + * PTR0_ST (W1C) + * + * Pointer 0 start + */ +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK (0x10U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT (4U) +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) + +/* + * WDOG (W1C) + * + * Watch dog + */ +#define SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK (0x4U) +#define SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT (2U) +#define SEI_CTRL_IRQ_INT_FLAG_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) >> SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) + +/* + * EXECPT (W1C) + * + * Exception + */ +#define SEI_CTRL_IRQ_INT_FLAG_EXECPT_MASK (0x2U) +#define SEI_CTRL_IRQ_INT_FLAG_EXECPT_SHIFT (1U) +#define SEI_CTRL_IRQ_INT_FLAG_EXECPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_EXECPT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_EXECPT_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_EXECPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_EXECPT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_EXECPT_SHIFT) + +/* + * STALL (W1C) + * + * Stall + */ +#define SEI_CTRL_IRQ_INT_FLAG_STALL_MASK (0x1U) +#define SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT (0U) +#define SEI_CTRL_IRQ_INT_FLAG_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) +#define SEI_CTRL_IRQ_INT_FLAG_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) >> SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: INT_STS */ +/* + * TRG_ERR3 (RO) + * + * Trigger3 failed + */ +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK (0x80000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT (31U) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT) + +/* + * TRG_ERR2 (RO) + * + * Trigger2 failed + */ +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK (0x40000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT (30U) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT) + +/* + * TRG_ERR1 (RO) + * + * Trigger1 failed + */ +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK (0x20000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT (29U) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT) + +/* + * TRG_ERR0 (RO) + * + * Trigger0 failed + */ +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK (0x10000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT (28U) +#define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT) + +/* + * TRIGER3 (RO) + * + * Trigger3 + */ +#define SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK (0x8000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT (27U) +#define SEI_CTRL_IRQ_INT_STS_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT) + +/* + * TRIGER2 (RO) + * + * Trigger2 + */ +#define SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK (0x4000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT (26U) +#define SEI_CTRL_IRQ_INT_STS_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT) + +/* + * TRIGER1 (RO) + * + * Trigger1 + */ +#define SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK (0x2000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT (25U) +#define SEI_CTRL_IRQ_INT_STS_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT) + +/* + * TRIGER0 (RO) + * + * Trigger0 + */ +#define SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK (0x1000000UL) +#define SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT (24U) +#define SEI_CTRL_IRQ_INT_STS_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT) + +/* + * SMP_ERR (RO) + * + * Sample error + */ +#define SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK (0x100000UL) +#define SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT (20U) +#define SEI_CTRL_IRQ_INT_STS_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT) + +/* + * LATCH3 (RO) + * + * Latch3 + */ +#define SEI_CTRL_IRQ_INT_STS_LATCH3_MASK (0x80000UL) +#define SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT (19U) +#define SEI_CTRL_IRQ_INT_STS_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT) + +/* + * LATCH2 (RO) + * + * Latch2 + */ +#define SEI_CTRL_IRQ_INT_STS_LATCH2_MASK (0x40000UL) +#define SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT (18U) +#define SEI_CTRL_IRQ_INT_STS_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT) + +/* + * LATCH1 (RO) + * + * Latch1 + */ +#define SEI_CTRL_IRQ_INT_STS_LATCH1_MASK (0x20000UL) +#define SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT (17U) +#define SEI_CTRL_IRQ_INT_STS_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT) + +/* + * LATCH0 (RO) + * + * Latch0 + */ +#define SEI_CTRL_IRQ_INT_STS_LATCH0_MASK (0x10000UL) +#define SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT (16U) +#define SEI_CTRL_IRQ_INT_STS_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT) + +/* + * TIMEOUT (RO) + * + * Timeout + */ +#define SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK (0x2000U) +#define SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT (13U) +#define SEI_CTRL_IRQ_INT_STS_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT) + +/* + * TRX_ERR (RO) + * + * Transfer error + */ +#define SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK (0x1000U) +#define SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT (12U) +#define SEI_CTRL_IRQ_INT_STS_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT) + +/* + * INSTR1_END (RO) + * + * Instruction 1 end + */ +#define SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK (0x800U) +#define SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT (11U) +#define SEI_CTRL_IRQ_INT_STS_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT) + +/* + * INSTR0_END (RO) + * + * Instruction 0 end + */ +#define SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK (0x400U) +#define SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT (10U) +#define SEI_CTRL_IRQ_INT_STS_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT) + +/* + * PTR1_END (RO) + * + * Pointer 1 end + */ +#define SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK (0x200U) +#define SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT (9U) +#define SEI_CTRL_IRQ_INT_STS_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT) + +/* + * PTR0_END (RO) + * + * Pointer 0 end + */ +#define SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK (0x100U) +#define SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT (8U) +#define SEI_CTRL_IRQ_INT_STS_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT) + +/* + * INSTR1_ST (RO) + * + * Instruction 1 start + */ +#define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK (0x80U) +#define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT (7U) +#define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT) + +/* + * INSTR0_ST (RO) + * + * Instruction 0 start + */ +#define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK (0x40U) +#define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT (6U) +#define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT) + +/* + * PTR1_ST (RO) + * + * Pointer 1 start + */ +#define SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK (0x20U) +#define SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT (5U) +#define SEI_CTRL_IRQ_INT_STS_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT) + +/* + * PTR0_ST (RO) + * + * Pointer 0 start + */ +#define SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK (0x10U) +#define SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT (4U) +#define SEI_CTRL_IRQ_INT_STS_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT) + +/* + * WDOG (RO) + * + * Watch dog + */ +#define SEI_CTRL_IRQ_INT_STS_WDOG_MASK (0x4U) +#define SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT (2U) +#define SEI_CTRL_IRQ_INT_STS_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_WDOG_MASK) >> SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT) + +/* + * EXECPT (RO) + * + * Exception + */ +#define SEI_CTRL_IRQ_INT_STS_EXECPT_MASK (0x2U) +#define SEI_CTRL_IRQ_INT_STS_EXECPT_SHIFT (1U) +#define SEI_CTRL_IRQ_INT_STS_EXECPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_EXECPT_MASK) >> SEI_CTRL_IRQ_INT_STS_EXECPT_SHIFT) + +/* + * STALL (RO) + * + * Stall + */ +#define SEI_CTRL_IRQ_INT_STS_STALL_MASK (0x1U) +#define SEI_CTRL_IRQ_INT_STS_STALL_SHIFT (0U) +#define SEI_CTRL_IRQ_INT_STS_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_STALL_MASK) >> SEI_CTRL_IRQ_INT_STS_STALL_SHIFT) + +/* Bitfield definition for register of struct array CTRL: POINTER0 */ +/* + * POINTER (RW) + * + * Match pointer 0 + */ +#define SEI_CTRL_IRQ_POINTER0_POINTER_MASK (0xFFU) +#define SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT (0U) +#define SEI_CTRL_IRQ_POINTER0_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) +#define SEI_CTRL_IRQ_POINTER0_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) + +/* Bitfield definition for register of struct array CTRL: POINTER1 */ +/* + * POINTER (RW) + * + * Match pointer 1 + */ +#define SEI_CTRL_IRQ_POINTER1_POINTER_MASK (0xFFU) +#define SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT (0U) +#define SEI_CTRL_IRQ_POINTER1_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) +#define SEI_CTRL_IRQ_POINTER1_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) + +/* Bitfield definition for register of struct array CTRL: INSTR0 */ +/* + * INSTR (RW) + * + * Match instruction 0 + */ +#define SEI_CTRL_IRQ_INSTR0_INSTR_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT (0U) +#define SEI_CTRL_IRQ_INSTR0_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) +#define SEI_CTRL_IRQ_INSTR0_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) + +/* Bitfield definition for register of struct array CTRL: INSTR1 */ +/* + * INSTR (RW) + * + * Match instruction 1 + */ +#define SEI_CTRL_IRQ_INSTR1_INSTR_MASK (0xFFFFFFFFUL) +#define SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT (0U) +#define SEI_CTRL_IRQ_INSTR1_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) +#define SEI_CTRL_IRQ_INSTR1_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) + +/* Bitfield definition for register array: INSTR */ +/* + * OP (RW) + * + * operation + * 0: halt + * 1: jump + * 2: send with timeout check + * 3: send without timout check + * 4: wait with timeout check + * 5: wait without timout check + * 6: receive with timeout check + * 7: receive without timout check + */ +#define SEI_INSTR_OP_MASK (0x1C000000UL) +#define SEI_INSTR_OP_SHIFT (26U) +#define SEI_INSTR_OP_SET(x) (((uint32_t)(x) << SEI_INSTR_OP_SHIFT) & SEI_INSTR_OP_MASK) +#define SEI_INSTR_OP_GET(x) (((uint32_t)(x) & SEI_INSTR_OP_MASK) >> SEI_INSTR_OP_SHIFT) + +/* + * CK (RW) + * + * clock + * 0: low + * 1: rise-fall + * 2: fall-rise + * 3: high + */ +#define SEI_INSTR_CK_MASK (0x3000000UL) +#define SEI_INSTR_CK_SHIFT (24U) +#define SEI_INSTR_CK_SET(x) (((uint32_t)(x) << SEI_INSTR_CK_SHIFT) & SEI_INSTR_CK_MASK) +#define SEI_INSTR_CK_GET(x) (((uint32_t)(x) & SEI_INSTR_CK_MASK) >> SEI_INSTR_CK_SHIFT) + +/* + * CRC (RW) + * + * CRC register + * 0: don't calculate CRC + * 1: do not set this value + * 2: data register 2 + * 3: data register 3 + * ... + * 29: data register 29 + * 30: value 0 when send, wait 0 in receive + * 31: value1 when send, wait 1 in receive + */ +#define SEI_INSTR_CRC_MASK (0x1F0000UL) +#define SEI_INSTR_CRC_SHIFT (16U) +#define SEI_INSTR_CRC_SET(x) (((uint32_t)(x) << SEI_INSTR_CRC_SHIFT) & SEI_INSTR_CRC_MASK) +#define SEI_INSTR_CRC_GET(x) (((uint32_t)(x) & SEI_INSTR_CRC_MASK) >> SEI_INSTR_CRC_SHIFT) + +/* + * DAT (RW) + * + * DATA register + * 0: ignore data + * 1: command + * 2: data register 2 + * 3: data register 3 + * ... + * 29: data register 29 + * 30: value 0 when send, wait 0 in receive + * 31: value1 when send, wait 1 in receive + */ +#define SEI_INSTR_DAT_MASK (0x1F00U) +#define SEI_INSTR_DAT_SHIFT (8U) +#define SEI_INSTR_DAT_SET(x) (((uint32_t)(x) << SEI_INSTR_DAT_SHIFT) & SEI_INSTR_DAT_MASK) +#define SEI_INSTR_DAT_GET(x) (((uint32_t)(x) & SEI_INSTR_DAT_MASK) >> SEI_INSTR_DAT_SHIFT) + +/* + * OPR (RW) + * + * [1] When OP is 0, this area is the halt time in baudrate, 0 represents infinite time. + * [2] When OP is 1, this area is the the pointer to the command table. + * OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer; + * OPR[4]=0, OPR[3:0]=0 is INIT_POINTER; + * OPR[4]=0, OPR[3:0]=1 is WDG_POINTER. + * [3] When OP is 2-7, this area is the data length as fellow: + * 0: 1 bit + * 1: 2 bit + * ... + * 31: 32 bit + */ +#define SEI_INSTR_OPR_MASK (0x1FU) +#define SEI_INSTR_OPR_SHIFT (0U) +#define SEI_INSTR_OPR_SET(x) (((uint32_t)(x) << SEI_INSTR_OPR_SHIFT) & SEI_INSTR_OPR_MASK) +#define SEI_INSTR_OPR_GET(x) (((uint32_t)(x) & SEI_INSTR_OPR_MASK) >> SEI_INSTR_OPR_SHIFT) + +/* Bitfield definition for register of struct array DAT: MODE */ +/* + * CRC_LEN (RW) + * + * CRC length + * 0: 1 bit + * 1: 2 bit + * ... + * 31: 32 bit + */ +#define SEI_DAT_MODE_CRC_LEN_MASK (0x1F000000UL) +#define SEI_DAT_MODE_CRC_LEN_SHIFT (24U) +#define SEI_DAT_MODE_CRC_LEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_LEN_SHIFT) & SEI_DAT_MODE_CRC_LEN_MASK) +#define SEI_DAT_MODE_CRC_LEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_LEN_MASK) >> SEI_DAT_MODE_CRC_LEN_SHIFT) + +/* + * WLEN (RW) + * + * word length + * 0: 1 bit + * 1: 2 bit + * ... + * 31: 32 bit + */ +#define SEI_DAT_MODE_WLEN_MASK (0x1F0000UL) +#define SEI_DAT_MODE_WLEN_SHIFT (16U) +#define SEI_DAT_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WLEN_SHIFT) & SEI_DAT_MODE_WLEN_MASK) +#define SEI_DAT_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WLEN_MASK) >> SEI_DAT_MODE_WLEN_SHIFT) + +/* + * CRC_SHIFT (RW) + * + * CRC shift mode, this mode is used to perform repeat code check + * 0: CRC + * 1: shift mode + */ +#define SEI_DAT_MODE_CRC_SHIFT_MASK (0x2000U) +#define SEI_DAT_MODE_CRC_SHIFT_SHIFT (13U) +#define SEI_DAT_MODE_CRC_SHIFT_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_SHIFT_SHIFT) & SEI_DAT_MODE_CRC_SHIFT_MASK) +#define SEI_DAT_MODE_CRC_SHIFT_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_SHIFT_MASK) >> SEI_DAT_MODE_CRC_SHIFT_SHIFT) + +/* + * CRC_INV (RW) + * + * CRC invert + * 0: use CRC + * 1: use inverted CRC + */ +#define SEI_DAT_MODE_CRC_INV_MASK (0x1000U) +#define SEI_DAT_MODE_CRC_INV_SHIFT (12U) +#define SEI_DAT_MODE_CRC_INV_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_INV_SHIFT) & SEI_DAT_MODE_CRC_INV_MASK) +#define SEI_DAT_MODE_CRC_INV_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_INV_MASK) >> SEI_DAT_MODE_CRC_INV_SHIFT) + +/* + * WORDER (RW) + * + * word order + * 0: sample as bit order + * 1: different from bit order + */ +#define SEI_DAT_MODE_WORDER_MASK (0x800U) +#define SEI_DAT_MODE_WORDER_SHIFT (11U) +#define SEI_DAT_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WORDER_SHIFT) & SEI_DAT_MODE_WORDER_MASK) +#define SEI_DAT_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WORDER_MASK) >> SEI_DAT_MODE_WORDER_SHIFT) + +/* + * BORDER (RW) + * + * bit order + * 0: LSB first + * 1: MSB first + */ +#define SEI_DAT_MODE_BORDER_MASK (0x400U) +#define SEI_DAT_MODE_BORDER_SHIFT (10U) +#define SEI_DAT_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_BORDER_SHIFT) & SEI_DAT_MODE_BORDER_MASK) +#define SEI_DAT_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_BORDER_MASK) >> SEI_DAT_MODE_BORDER_SHIFT) + +/* + * SIGNED (RW) + * + * Signed + * 0: unsigned value + * 1: signed value + */ +#define SEI_DAT_MODE_SIGNED_MASK (0x200U) +#define SEI_DAT_MODE_SIGNED_SHIFT (9U) +#define SEI_DAT_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_SIGNED_SHIFT) & SEI_DAT_MODE_SIGNED_MASK) +#define SEI_DAT_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_SIGNED_MASK) >> SEI_DAT_MODE_SIGNED_SHIFT) + +/* + * REWIND (RW) + * + * Write 1 to rewind read/write pointer, this is a self clear bit + */ +#define SEI_DAT_MODE_REWIND_MASK (0x100U) +#define SEI_DAT_MODE_REWIND_SHIFT (8U) +#define SEI_DAT_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_REWIND_SHIFT) & SEI_DAT_MODE_REWIND_MASK) +#define SEI_DAT_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_REWIND_MASK) >> SEI_DAT_MODE_REWIND_SHIFT) + +/* + * MODE (RW) + * + * Data mode + * 0: data mode + * 1: check mode + * 2: CRC mode + */ +#define SEI_DAT_MODE_MODE_MASK (0x3U) +#define SEI_DAT_MODE_MODE_SHIFT (0U) +#define SEI_DAT_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_MODE_SHIFT) & SEI_DAT_MODE_MODE_MASK) +#define SEI_DAT_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_MODE_MASK) >> SEI_DAT_MODE_MODE_SHIFT) + +/* Bitfield definition for register of struct array DAT: IDX */ +/* + * LAST_BIT (RW) + * + * Last bit index for tranceive + */ +#define SEI_DAT_IDX_LAST_BIT_MASK (0x1F000000UL) +#define SEI_DAT_IDX_LAST_BIT_SHIFT (24U) +#define SEI_DAT_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_LAST_BIT_SHIFT) & SEI_DAT_IDX_LAST_BIT_MASK) +#define SEI_DAT_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_LAST_BIT_MASK) >> SEI_DAT_IDX_LAST_BIT_SHIFT) + +/* + * FIRST_BIT (RW) + * + * First bit index for tranceive + */ +#define SEI_DAT_IDX_FIRST_BIT_MASK (0x1F0000UL) +#define SEI_DAT_IDX_FIRST_BIT_SHIFT (16U) +#define SEI_DAT_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_FIRST_BIT_SHIFT) & SEI_DAT_IDX_FIRST_BIT_MASK) +#define SEI_DAT_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_FIRST_BIT_MASK) >> SEI_DAT_IDX_FIRST_BIT_SHIFT) + +/* + * MAX_BIT (RW) + * + * Highest bit index + */ +#define SEI_DAT_IDX_MAX_BIT_MASK (0x1F00U) +#define SEI_DAT_IDX_MAX_BIT_SHIFT (8U) +#define SEI_DAT_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MAX_BIT_SHIFT) & SEI_DAT_IDX_MAX_BIT_MASK) +#define SEI_DAT_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MAX_BIT_MASK) >> SEI_DAT_IDX_MAX_BIT_SHIFT) + +/* + * MIN_BIT (RW) + * + * Lowest bit index + */ +#define SEI_DAT_IDX_MIN_BIT_MASK (0x1FU) +#define SEI_DAT_IDX_MIN_BIT_SHIFT (0U) +#define SEI_DAT_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MIN_BIT_SHIFT) & SEI_DAT_IDX_MIN_BIT_MASK) +#define SEI_DAT_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MIN_BIT_MASK) >> SEI_DAT_IDX_MIN_BIT_SHIFT) + +/* Bitfield definition for register of struct array DAT: GOLD */ +/* + * GOLD_VALUE (RW) + * + * Gold value for check mode + */ +#define SEI_DAT_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL) +#define SEI_DAT_GOLD_GOLD_VALUE_SHIFT (0U) +#define SEI_DAT_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_DAT_GOLD_GOLD_VALUE_SHIFT) & SEI_DAT_GOLD_GOLD_VALUE_MASK) +#define SEI_DAT_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_DAT_GOLD_GOLD_VALUE_MASK) >> SEI_DAT_GOLD_GOLD_VALUE_SHIFT) + +/* Bitfield definition for register of struct array DAT: CRCINIT */ +/* + * CRC_INIT (RW) + * + * CRC initial value + */ +#define SEI_DAT_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL) +#define SEI_DAT_CRCINIT_CRC_INIT_SHIFT (0U) +#define SEI_DAT_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_DAT_CRCINIT_CRC_INIT_SHIFT) & SEI_DAT_CRCINIT_CRC_INIT_MASK) +#define SEI_DAT_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_DAT_CRCINIT_CRC_INIT_MASK) >> SEI_DAT_CRCINIT_CRC_INIT_SHIFT) + +/* Bitfield definition for register of struct array DAT: CRCPOLY */ +/* + * CRC_POLY (RW) + * + * CRC polymonial + */ +#define SEI_DAT_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL) +#define SEI_DAT_CRCPOLY_CRC_POLY_SHIFT (0U) +#define SEI_DAT_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) +#define SEI_DAT_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) >> SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) + +/* Bitfield definition for register of struct array DAT: DATA */ +/* + * DATA (RW) + * + * DATA + */ +#define SEI_DAT_DATA_DATA_MASK (0xFFFFFFFFUL) +#define SEI_DAT_DATA_DATA_SHIFT (0U) +#define SEI_DAT_DATA_DATA_SET(x) (((uint32_t)(x) << SEI_DAT_DATA_DATA_SHIFT) & SEI_DAT_DATA_DATA_MASK) +#define SEI_DAT_DATA_DATA_GET(x) (((uint32_t)(x) & SEI_DAT_DATA_DATA_MASK) >> SEI_DAT_DATA_DATA_SHIFT) + +/* Bitfield definition for register of struct array DAT: SET */ +/* + * DATA_SET (RW) + * + * DATA bit set + */ +#define SEI_DAT_SET_DATA_SET_MASK (0xFFFFFFFFUL) +#define SEI_DAT_SET_DATA_SET_SHIFT (0U) +#define SEI_DAT_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_DAT_SET_DATA_SET_SHIFT) & SEI_DAT_SET_DATA_SET_MASK) +#define SEI_DAT_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_DAT_SET_DATA_SET_MASK) >> SEI_DAT_SET_DATA_SET_SHIFT) + +/* Bitfield definition for register of struct array DAT: CLR */ +/* + * DATA_CLR (RW) + * + * DATA bit clear + */ +#define SEI_DAT_CLR_DATA_CLR_MASK (0xFFFFFFFFUL) +#define SEI_DAT_CLR_DATA_CLR_SHIFT (0U) +#define SEI_DAT_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_DAT_CLR_DATA_CLR_SHIFT) & SEI_DAT_CLR_DATA_CLR_MASK) +#define SEI_DAT_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_DAT_CLR_DATA_CLR_MASK) >> SEI_DAT_CLR_DATA_CLR_SHIFT) + +/* Bitfield definition for register of struct array DAT: INV */ +/* + * DATA_INV (RW) + * + * DATA bit toggle + */ +#define SEI_DAT_INV_DATA_INV_MASK (0xFFFFFFFFUL) +#define SEI_DAT_INV_DATA_INV_SHIFT (0U) +#define SEI_DAT_INV_DATA_INV_SET(x) (((uint32_t)(x) << SEI_DAT_INV_DATA_INV_SHIFT) & SEI_DAT_INV_DATA_INV_MASK) +#define SEI_DAT_INV_DATA_INV_GET(x) (((uint32_t)(x) & SEI_DAT_INV_DATA_INV_MASK) >> SEI_DAT_INV_DATA_INV_SHIFT) + +/* Bitfield definition for register of struct array DAT: IN */ +/* + * DATA_IN (RO) + * + * Data input + */ +#define SEI_DAT_IN_DATA_IN_MASK (0xFFFFFFFFUL) +#define SEI_DAT_IN_DATA_IN_SHIFT (0U) +#define SEI_DAT_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_DAT_IN_DATA_IN_MASK) >> SEI_DAT_IN_DATA_IN_SHIFT) + +/* Bitfield definition for register of struct array DAT: OUT */ +/* + * DATA_OUT (RO) + * + * Data output + */ +#define SEI_DAT_OUT_DATA_OUT_MASK (0xFFFFFFFFUL) +#define SEI_DAT_OUT_DATA_OUT_SHIFT (0U) +#define SEI_DAT_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_DAT_OUT_DATA_OUT_MASK) >> SEI_DAT_OUT_DATA_OUT_SHIFT) + +/* Bitfield definition for register of struct array DAT: STS */ +/* + * CRC_IDX (RO) + * + * CRC index + */ +#define SEI_DAT_STS_CRC_IDX_MASK (0x1F000000UL) +#define SEI_DAT_STS_CRC_IDX_SHIFT (24U) +#define SEI_DAT_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_CRC_IDX_MASK) >> SEI_DAT_STS_CRC_IDX_SHIFT) + +/* + * WORD_IDX (RO) + * + * Word index + */ +#define SEI_DAT_STS_WORD_IDX_MASK (0x1F0000UL) +#define SEI_DAT_STS_WORD_IDX_SHIFT (16U) +#define SEI_DAT_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_IDX_MASK) >> SEI_DAT_STS_WORD_IDX_SHIFT) + +/* + * WORD_CNT (RO) + * + * Word counter + */ +#define SEI_DAT_STS_WORD_CNT_MASK (0x1F00U) +#define SEI_DAT_STS_WORD_CNT_SHIFT (8U) +#define SEI_DAT_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_CNT_MASK) >> SEI_DAT_STS_WORD_CNT_SHIFT) + +/* + * BIT_IDX (RO) + * + * Bit index + */ +#define SEI_DAT_STS_BIT_IDX_MASK (0x1FU) +#define SEI_DAT_STS_BIT_IDX_SHIFT (0U) +#define SEI_DAT_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_BIT_IDX_MASK) >> SEI_DAT_STS_BIT_IDX_SHIFT) + + + +/* CMD register group index macro definition */ +#define SEI_CTRL_TRG_TABLE_CMD_0 (0UL) +#define SEI_CTRL_TRG_TABLE_CMD_1 (1UL) +#define SEI_CTRL_TRG_TABLE_CMD_2 (2UL) +#define SEI_CTRL_TRG_TABLE_CMD_3 (3UL) + +/* TIME register group index macro definition */ +#define SEI_CTRL_TRG_TABLE_TIME_0 (0UL) +#define SEI_CTRL_TRG_TABLE_TIME_1 (1UL) +#define SEI_CTRL_TRG_TABLE_TIME_2 (2UL) +#define SEI_CTRL_TRG_TABLE_TIME_3 (3UL) + +/* CMD_TABLE register group index macro definition */ +#define SEI_CMD_TABLE_0 (0UL) +#define SEI_CMD_TABLE_1 (1UL) +#define SEI_CMD_TABLE_2 (2UL) +#define SEI_CMD_TABLE_3 (3UL) +#define SEI_CMD_TABLE_4 (4UL) +#define SEI_CMD_TABLE_5 (5UL) +#define SEI_CMD_TABLE_6 (6UL) +#define SEI_CMD_TABLE_7 (7UL) + +/* TRAN register group index macro definition */ +#define SEI_CTRL_LATCH_TRAN_0_1 (0UL) +#define SEI_CTRL_LATCH_TRAN_1_2 (1UL) +#define SEI_CTRL_LATCH_TRAN_2_3 (2UL) +#define SEI_CTRL_LATCH_TRAN_3_0 (3UL) + +/* LATCH register group index macro definition */ +#define SEI_LATCH_0 (0UL) +#define SEI_LATCH_1 (1UL) +#define SEI_LATCH_2 (2UL) +#define SEI_LATCH_3 (3UL) + +/* CTRL register group index macro definition */ +#define SEI_CTRL_0 (0UL) +#define SEI_CTRL_1 (1UL) +#define SEI_CTRL_2 (2UL) +#define SEI_CTRL_3 (3UL) +#define SEI_CTRL_4 (4UL) +#define SEI_CTRL_5 (5UL) +#define SEI_CTRL_6 (6UL) +#define SEI_CTRL_7 (7UL) +#define SEI_CTRL_8 (8UL) +#define SEI_CTRL_9 (9UL) +#define SEI_CTRL_10 (10UL) +#define SEI_CTRL_11 (11UL) +#define SEI_CTRL_12 (12UL) + +/* INSTR register group index macro definition */ +#define SEI_INSTR_0 (0UL) +#define SEI_INSTR_1 (1UL) +#define SEI_INSTR_2 (2UL) +#define SEI_INSTR_3 (3UL) +#define SEI_INSTR_4 (4UL) +#define SEI_INSTR_5 (5UL) +#define SEI_INSTR_6 (6UL) +#define SEI_INSTR_7 (7UL) +#define SEI_INSTR_8 (8UL) +#define SEI_INSTR_9 (9UL) +#define SEI_INSTR_10 (10UL) +#define SEI_INSTR_11 (11UL) +#define SEI_INSTR_12 (12UL) +#define SEI_INSTR_13 (13UL) +#define SEI_INSTR_14 (14UL) +#define SEI_INSTR_15 (15UL) +#define SEI_INSTR_16 (16UL) +#define SEI_INSTR_17 (17UL) +#define SEI_INSTR_18 (18UL) +#define SEI_INSTR_19 (19UL) +#define SEI_INSTR_20 (20UL) +#define SEI_INSTR_21 (21UL) +#define SEI_INSTR_22 (22UL) +#define SEI_INSTR_23 (23UL) +#define SEI_INSTR_24 (24UL) +#define SEI_INSTR_25 (25UL) +#define SEI_INSTR_26 (26UL) +#define SEI_INSTR_27 (27UL) +#define SEI_INSTR_28 (28UL) +#define SEI_INSTR_29 (29UL) +#define SEI_INSTR_30 (30UL) +#define SEI_INSTR_31 (31UL) +#define SEI_INSTR_32 (32UL) +#define SEI_INSTR_33 (33UL) +#define SEI_INSTR_34 (34UL) +#define SEI_INSTR_35 (35UL) +#define SEI_INSTR_36 (36UL) +#define SEI_INSTR_37 (37UL) +#define SEI_INSTR_38 (38UL) +#define SEI_INSTR_39 (39UL) +#define SEI_INSTR_40 (40UL) +#define SEI_INSTR_41 (41UL) +#define SEI_INSTR_42 (42UL) +#define SEI_INSTR_43 (43UL) +#define SEI_INSTR_44 (44UL) +#define SEI_INSTR_45 (45UL) +#define SEI_INSTR_46 (46UL) +#define SEI_INSTR_47 (47UL) +#define SEI_INSTR_48 (48UL) +#define SEI_INSTR_49 (49UL) +#define SEI_INSTR_50 (50UL) +#define SEI_INSTR_51 (51UL) +#define SEI_INSTR_52 (52UL) +#define SEI_INSTR_53 (53UL) +#define SEI_INSTR_54 (54UL) +#define SEI_INSTR_55 (55UL) +#define SEI_INSTR_56 (56UL) +#define SEI_INSTR_57 (57UL) +#define SEI_INSTR_58 (58UL) +#define SEI_INSTR_59 (59UL) +#define SEI_INSTR_60 (60UL) +#define SEI_INSTR_61 (61UL) +#define SEI_INSTR_62 (62UL) +#define SEI_INSTR_63 (63UL) +#define SEI_INSTR_64 (64UL) +#define SEI_INSTR_65 (65UL) +#define SEI_INSTR_66 (66UL) +#define SEI_INSTR_67 (67UL) +#define SEI_INSTR_68 (68UL) +#define SEI_INSTR_69 (69UL) +#define SEI_INSTR_70 (70UL) +#define SEI_INSTR_71 (71UL) +#define SEI_INSTR_72 (72UL) +#define SEI_INSTR_73 (73UL) +#define SEI_INSTR_74 (74UL) +#define SEI_INSTR_75 (75UL) +#define SEI_INSTR_76 (76UL) +#define SEI_INSTR_77 (77UL) +#define SEI_INSTR_78 (78UL) +#define SEI_INSTR_79 (79UL) +#define SEI_INSTR_80 (80UL) +#define SEI_INSTR_81 (81UL) +#define SEI_INSTR_82 (82UL) +#define SEI_INSTR_83 (83UL) +#define SEI_INSTR_84 (84UL) +#define SEI_INSTR_85 (85UL) +#define SEI_INSTR_86 (86UL) +#define SEI_INSTR_87 (87UL) +#define SEI_INSTR_88 (88UL) +#define SEI_INSTR_89 (89UL) +#define SEI_INSTR_90 (90UL) +#define SEI_INSTR_91 (91UL) +#define SEI_INSTR_92 (92UL) +#define SEI_INSTR_93 (93UL) +#define SEI_INSTR_94 (94UL) +#define SEI_INSTR_95 (95UL) +#define SEI_INSTR_96 (96UL) +#define SEI_INSTR_97 (97UL) +#define SEI_INSTR_98 (98UL) +#define SEI_INSTR_99 (99UL) +#define SEI_INSTR_100 (100UL) +#define SEI_INSTR_101 (101UL) +#define SEI_INSTR_102 (102UL) +#define SEI_INSTR_103 (103UL) +#define SEI_INSTR_104 (104UL) +#define SEI_INSTR_105 (105UL) +#define SEI_INSTR_106 (106UL) +#define SEI_INSTR_107 (107UL) +#define SEI_INSTR_108 (108UL) +#define SEI_INSTR_109 (109UL) +#define SEI_INSTR_110 (110UL) +#define SEI_INSTR_111 (111UL) +#define SEI_INSTR_112 (112UL) +#define SEI_INSTR_113 (113UL) +#define SEI_INSTR_114 (114UL) +#define SEI_INSTR_115 (115UL) +#define SEI_INSTR_116 (116UL) +#define SEI_INSTR_117 (117UL) +#define SEI_INSTR_118 (118UL) +#define SEI_INSTR_119 (119UL) +#define SEI_INSTR_120 (120UL) +#define SEI_INSTR_121 (121UL) +#define SEI_INSTR_122 (122UL) +#define SEI_INSTR_123 (123UL) +#define SEI_INSTR_124 (124UL) +#define SEI_INSTR_125 (125UL) +#define SEI_INSTR_126 (126UL) +#define SEI_INSTR_127 (127UL) +#define SEI_INSTR_128 (128UL) +#define SEI_INSTR_129 (129UL) +#define SEI_INSTR_130 (130UL) +#define SEI_INSTR_131 (131UL) +#define SEI_INSTR_132 (132UL) +#define SEI_INSTR_133 (133UL) +#define SEI_INSTR_134 (134UL) +#define SEI_INSTR_135 (135UL) +#define SEI_INSTR_136 (136UL) +#define SEI_INSTR_137 (137UL) +#define SEI_INSTR_138 (138UL) +#define SEI_INSTR_139 (139UL) +#define SEI_INSTR_140 (140UL) +#define SEI_INSTR_141 (141UL) +#define SEI_INSTR_142 (142UL) +#define SEI_INSTR_143 (143UL) +#define SEI_INSTR_144 (144UL) +#define SEI_INSTR_145 (145UL) +#define SEI_INSTR_146 (146UL) +#define SEI_INSTR_147 (147UL) +#define SEI_INSTR_148 (148UL) +#define SEI_INSTR_149 (149UL) +#define SEI_INSTR_150 (150UL) +#define SEI_INSTR_151 (151UL) +#define SEI_INSTR_152 (152UL) +#define SEI_INSTR_153 (153UL) +#define SEI_INSTR_154 (154UL) +#define SEI_INSTR_155 (155UL) +#define SEI_INSTR_156 (156UL) +#define SEI_INSTR_157 (157UL) +#define SEI_INSTR_158 (158UL) +#define SEI_INSTR_159 (159UL) +#define SEI_INSTR_160 (160UL) +#define SEI_INSTR_161 (161UL) +#define SEI_INSTR_162 (162UL) +#define SEI_INSTR_163 (163UL) +#define SEI_INSTR_164 (164UL) +#define SEI_INSTR_165 (165UL) +#define SEI_INSTR_166 (166UL) +#define SEI_INSTR_167 (167UL) +#define SEI_INSTR_168 (168UL) +#define SEI_INSTR_169 (169UL) +#define SEI_INSTR_170 (170UL) +#define SEI_INSTR_171 (171UL) +#define SEI_INSTR_172 (172UL) +#define SEI_INSTR_173 (173UL) +#define SEI_INSTR_174 (174UL) +#define SEI_INSTR_175 (175UL) +#define SEI_INSTR_176 (176UL) +#define SEI_INSTR_177 (177UL) +#define SEI_INSTR_178 (178UL) +#define SEI_INSTR_179 (179UL) +#define SEI_INSTR_180 (180UL) +#define SEI_INSTR_181 (181UL) +#define SEI_INSTR_182 (182UL) +#define SEI_INSTR_183 (183UL) +#define SEI_INSTR_184 (184UL) +#define SEI_INSTR_185 (185UL) +#define SEI_INSTR_186 (186UL) +#define SEI_INSTR_187 (187UL) +#define SEI_INSTR_188 (188UL) +#define SEI_INSTR_189 (189UL) +#define SEI_INSTR_190 (190UL) +#define SEI_INSTR_191 (191UL) +#define SEI_INSTR_192 (192UL) +#define SEI_INSTR_193 (193UL) +#define SEI_INSTR_194 (194UL) +#define SEI_INSTR_195 (195UL) +#define SEI_INSTR_196 (196UL) +#define SEI_INSTR_197 (197UL) +#define SEI_INSTR_198 (198UL) +#define SEI_INSTR_199 (199UL) +#define SEI_INSTR_200 (200UL) +#define SEI_INSTR_201 (201UL) +#define SEI_INSTR_202 (202UL) +#define SEI_INSTR_203 (203UL) +#define SEI_INSTR_204 (204UL) +#define SEI_INSTR_205 (205UL) +#define SEI_INSTR_206 (206UL) +#define SEI_INSTR_207 (207UL) +#define SEI_INSTR_208 (208UL) +#define SEI_INSTR_209 (209UL) +#define SEI_INSTR_210 (210UL) +#define SEI_INSTR_211 (211UL) +#define SEI_INSTR_212 (212UL) +#define SEI_INSTR_213 (213UL) +#define SEI_INSTR_214 (214UL) +#define SEI_INSTR_215 (215UL) +#define SEI_INSTR_216 (216UL) +#define SEI_INSTR_217 (217UL) +#define SEI_INSTR_218 (218UL) +#define SEI_INSTR_219 (219UL) +#define SEI_INSTR_220 (220UL) +#define SEI_INSTR_221 (221UL) +#define SEI_INSTR_222 (222UL) +#define SEI_INSTR_223 (223UL) +#define SEI_INSTR_224 (224UL) +#define SEI_INSTR_225 (225UL) +#define SEI_INSTR_226 (226UL) +#define SEI_INSTR_227 (227UL) +#define SEI_INSTR_228 (228UL) +#define SEI_INSTR_229 (229UL) +#define SEI_INSTR_230 (230UL) +#define SEI_INSTR_231 (231UL) +#define SEI_INSTR_232 (232UL) +#define SEI_INSTR_233 (233UL) +#define SEI_INSTR_234 (234UL) +#define SEI_INSTR_235 (235UL) +#define SEI_INSTR_236 (236UL) +#define SEI_INSTR_237 (237UL) +#define SEI_INSTR_238 (238UL) +#define SEI_INSTR_239 (239UL) +#define SEI_INSTR_240 (240UL) +#define SEI_INSTR_241 (241UL) +#define SEI_INSTR_242 (242UL) +#define SEI_INSTR_243 (243UL) +#define SEI_INSTR_244 (244UL) +#define SEI_INSTR_245 (245UL) +#define SEI_INSTR_246 (246UL) +#define SEI_INSTR_247 (247UL) +#define SEI_INSTR_248 (248UL) +#define SEI_INSTR_249 (249UL) +#define SEI_INSTR_250 (250UL) +#define SEI_INSTR_251 (251UL) +#define SEI_INSTR_252 (252UL) +#define SEI_INSTR_253 (253UL) +#define SEI_INSTR_254 (254UL) +#define SEI_INSTR_255 (255UL) + +/* DAT register group index macro definition */ +#define SEI_DAT_0 (0UL) +#define SEI_DAT_1 (1UL) +#define SEI_DAT_2 (2UL) +#define SEI_DAT_3 (3UL) +#define SEI_DAT_4 (4UL) +#define SEI_DAT_5 (5UL) +#define SEI_DAT_6 (6UL) +#define SEI_DAT_7 (7UL) +#define SEI_DAT_8 (8UL) +#define SEI_DAT_9 (9UL) +#define SEI_DAT_10 (10UL) +#define SEI_DAT_11 (11UL) +#define SEI_DAT_12 (12UL) +#define SEI_DAT_13 (13UL) +#define SEI_DAT_14 (14UL) +#define SEI_DAT_15 (15UL) +#define SEI_DAT_16 (16UL) +#define SEI_DAT_17 (17UL) +#define SEI_DAT_18 (18UL) +#define SEI_DAT_19 (19UL) +#define SEI_DAT_20 (20UL) +#define SEI_DAT_21 (21UL) +#define SEI_DAT_22 (22UL) +#define SEI_DAT_23 (23UL) +#define SEI_DAT_24 (24UL) +#define SEI_DAT_25 (25UL) +#define SEI_DAT_26 (26UL) +#define SEI_DAT_27 (27UL) +#define SEI_DAT_28 (28UL) +#define SEI_DAT_29 (29UL) +#define SEI_DAT_30 (30UL) +#define SEI_DAT_31 (31UL) + + +#endif /* HPM_SEI_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_smix_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_smix_regs.h new file mode 100644 index 00000000..9dbb8106 --- /dev/null +++ b/common/libraries/hpm_sdk/soc/ip/hpm_smix_regs.h @@ -0,0 +1,1180 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + + +#ifndef HPM_SMIX_H +#define HPM_SMIX_H + +typedef struct { + __R uint32_t DMAC_ID; /* 0x0: DMAC_ID Register */ + __RW uint32_t DMAC_TC_ST; /* 0x4: Transfer Complete Status */ + __RW uint32_t DMAC_ABRT_ST; /* 0x8: Transfer Abort Status */ + __RW uint32_t DMAC_ERR_ST; /* 0xC: Transfer Error Status */ + __R uint8_t RESERVED0[16]; /* 0x10 - 0x1F: Reserved */ + __RW uint32_t DMAC_CTRL; /* 0x20: Control Register */ + __W uint32_t DMAC_ABRT_CMD; /* 0x24: Abort Command Register */ + __R uint8_t RESERVED1[12]; /* 0x28 - 0x33: Reserved */ + __RW uint32_t DMAC_CHEN; /* 0x34: Channel Enable Register */ + __R uint8_t RESERVED2[8]; /* 0x38 - 0x3F: Reserved */ + struct { + __RW uint32_t CTL; /* 0x40: Channel N Control Register */ + __RW uint32_t BURST_COUNT; /* 0x44: Channel N Source Total Beats Register */ + __RW uint32_t SRCADDR; /* 0x48: Channel N Source Register */ + __R uint8_t RESERVED0[4]; /* 0x4C - 0x4F: Reserved */ + __RW uint32_t DSTADDR; /* 0x50: Channel N Destination Register */ + __R uint8_t RESERVED1[4]; /* 0x54 - 0x57: Reserved */ + __RW uint32_t LLP; /* 0x58: Channel N Linked List Pointer Register */ + __R uint8_t RESERVED2[4]; /* 0x5C - 0x5F: Reserved */ + } DMA_CH[26]; + __R uint8_t RESERVED3[1152]; /* 0x380 - 0x7FF: Reserved */ + __RW uint32_t CALSAT_ST; /* 0x800: SMIX Cal Saturation Status Register */ + __RW uint32_t FDOT_DONE_ST; /* 0x804: SMIX Fade-Out Done Status Register */ + __R uint32_t DATA_ST; /* 0x808: SMIX Data Status Register */ + __R uint8_t RESERVED4[52]; /* 0x80C - 0x83F: Reserved */ + struct { + __RW uint32_t CTRL; /* 0x840: SMIX Dstination N Control Register */ + __RW uint32_t GAIN; /* 0x844: SMIX Dstination N Gain Register */ + __RW uint32_t BUFSIZE; /* 0x848: SMIX Dstination N Max Index Register */ + __RW uint32_t FADEIN; /* 0x84C: SMIX Dstination N Fade-In Configuration Register */ + __RW uint32_t FADEOUT; /* 0x850: SMIX Dstination N Fade-Out Configuration Register */ + __R uint32_t ST; /* 0x854: SMIX Dstination N Status Register */ + __R uint32_t DATA; /* 0x858: SMIX Dstination N Data Out Register */ + __R uint8_t RESERVED0[4]; /* 0x85C - 0x85F: Reserved */ + __RW uint32_t SOURCE_EN; /* 0x860: SMIX Dstination N Source Enable Register */ + __RW uint32_t SOURCE_ACT; /* 0x864: SMIX Dstination N Source Activation Register */ + __RW uint32_t SOURCE_DEACT; /* 0x868: SMIX Dstination N Source De-Activation Register */ + __RW uint32_t SOURCE_FADEIN_CTRL; /* 0x86C: SMIX Dstination N Source Fade-in Control Register */ + __R uint32_t DEACT_ST; /* 0x870: SMIX Dstination N Source Deactivation Status Register */ + __RW uint32_t SOURCE_MFADEOUT_CTRL; /* 0x874: SMIX Dstination N Source Manual Fade-out Control Register */ + __R uint8_t RESERVED1[8]; /* 0x878 - 0x87F: Reserved */ + } DST_CH[2]; + __R uint8_t RESERVED5[64]; /* 0x8C0 - 0x8FF: Reserved */ + struct { + __RW uint32_t CTRL; /* 0x900: SMIX Source N Control Register */ + __RW uint32_t GAIN; /* 0x904: SMIX Source N Gain Register */ + __RW uint32_t FADEIN; /* 0x908: SMIX Source N Fade-in Control Register */ + __RW uint32_t FADEOUT; /* 0x90C: SMIX Source N Fade-out Control Register */ + __RW uint32_t BUFSIZE; /* 0x910: SMIX Source N Buffer Size Register */ + __RW uint32_t ST; /* 0x914: SMIX Source N Status Register */ + __W uint32_t DATA; /* 0x918: SMIX Source N Data Input Register */ + __R uint8_t RESERVED0[4]; /* 0x91C - 0x91F: Reserved */ + } SOURCE_CH[14]; +} SMIX_Type; + + +/* Bitfield definition for register: DMAC_ID */ +/* + * REV (RO) + * + * Revision + */ +#define SMIX_DMAC_ID_REV_MASK (0x7FFFFUL) +#define SMIX_DMAC_ID_REV_SHIFT (0U) +#define SMIX_DMAC_ID_REV_GET(x) (((uint32_t)(x) & SMIX_DMAC_ID_REV_MASK) >> SMIX_DMAC_ID_REV_SHIFT) + +/* Bitfield definition for register: DMAC_TC_ST */ +/* + * CH (W1C) + * + * The terminal count status is set when a channel transfer finishes without abort or error events + */ +#define SMIX_DMAC_TC_ST_CH_MASK (0x3FFFFFFUL) +#define SMIX_DMAC_TC_ST_CH_SHIFT (0U) +#define SMIX_DMAC_TC_ST_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_TC_ST_CH_SHIFT) & SMIX_DMAC_TC_ST_CH_MASK) +#define SMIX_DMAC_TC_ST_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_TC_ST_CH_MASK) >> SMIX_DMAC_TC_ST_CH_SHIFT) + +/* Bitfield definition for register: DMAC_ABRT_ST */ +/* + * CH (W1C) + * + * The abort status is set when a channel transfer is aborted + */ +#define SMIX_DMAC_ABRT_ST_CH_MASK (0x3FFFFFFUL) +#define SMIX_DMAC_ABRT_ST_CH_SHIFT (0U) +#define SMIX_DMAC_ABRT_ST_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_ABRT_ST_CH_SHIFT) & SMIX_DMAC_ABRT_ST_CH_MASK) +#define SMIX_DMAC_ABRT_ST_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_ABRT_ST_CH_MASK) >> SMIX_DMAC_ABRT_ST_CH_SHIFT) + +/* Bitfield definition for register: DMAC_ERR_ST */ +/* + * CH (W1C) + * + * The error status is set when a channel transfer encounters the following error events: + * . Bus error + * . Unaligned address + * . Unaligned transfer width + * . Reserved configuration + */ +#define SMIX_DMAC_ERR_ST_CH_MASK (0x3FFFFFFUL) +#define SMIX_DMAC_ERR_ST_CH_SHIFT (0U) +#define SMIX_DMAC_ERR_ST_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_ERR_ST_CH_SHIFT) & SMIX_DMAC_ERR_ST_CH_MASK) +#define SMIX_DMAC_ERR_ST_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_ERR_ST_CH_MASK) >> SMIX_DMAC_ERR_ST_CH_SHIFT) + +/* Bitfield definition for register: DMAC_CTRL */ +/* + * SRST (RW) + * + * Software Reset + */ +#define SMIX_DMAC_CTRL_SRST_MASK (0x1U) +#define SMIX_DMAC_CTRL_SRST_SHIFT (0U) +#define SMIX_DMAC_CTRL_SRST_SET(x) (((uint32_t)(x) << SMIX_DMAC_CTRL_SRST_SHIFT) & SMIX_DMAC_CTRL_SRST_MASK) +#define SMIX_DMAC_CTRL_SRST_GET(x) (((uint32_t)(x) & SMIX_DMAC_CTRL_SRST_MASK) >> SMIX_DMAC_CTRL_SRST_SHIFT) + +/* Bitfield definition for register: DMAC_ABRT_CMD */ +/* + * CH (WO) + * + * Write 1 to force the corresponding channel into abort status + */ +#define SMIX_DMAC_ABRT_CMD_CH_MASK (0x3FFFFFFUL) +#define SMIX_DMAC_ABRT_CMD_CH_SHIFT (0U) +#define SMIX_DMAC_ABRT_CMD_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_ABRT_CMD_CH_SHIFT) & SMIX_DMAC_ABRT_CMD_CH_MASK) +#define SMIX_DMAC_ABRT_CMD_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_ABRT_CMD_CH_MASK) >> SMIX_DMAC_ABRT_CMD_CH_SHIFT) + +/* Bitfield definition for register: DMAC_CHEN */ +/* + * CH (RO) + * + * Write 1 to enable the corresponding channel + */ +#define SMIX_DMAC_CHEN_CH_MASK (0x3FFFFFFUL) +#define SMIX_DMAC_CHEN_CH_SHIFT (0U) +#define SMIX_DMAC_CHEN_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_CHEN_CH_MASK) >> SMIX_DMAC_CHEN_CH_SHIFT) + +/* Bitfield definition for register of struct array DMA_CH: CTL */ +/* + * SRCREQSEL (RW) + * + * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. + */ +#define SMIX_DMA_CH_CTL_SRCREQSEL_MASK (0x7C000000UL) +#define SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT (26U) +#define SMIX_DMA_CH_CTL_SRCREQSEL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT) & SMIX_DMA_CH_CTL_SRCREQSEL_MASK) +#define SMIX_DMA_CH_CTL_SRCREQSEL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCREQSEL_MASK) >> SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT) + +/* + * DSTREQSEL (RW) + * + * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. + */ +#define SMIX_DMA_CH_CTL_DSTREQSEL_MASK (0x3E00000UL) +#define SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT (21U) +#define SMIX_DMA_CH_CTL_DSTREQSEL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT) & SMIX_DMA_CH_CTL_DSTREQSEL_MASK) +#define SMIX_DMA_CH_CTL_DSTREQSEL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTREQSEL_MASK) >> SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT) + +/* + * PRIORITY (RW) + * + * 0x0: Lower priority + * 0x1: Higher priority + */ +#define SMIX_DMA_CH_CTL_PRIORITY_MASK (0x80000UL) +#define SMIX_DMA_CH_CTL_PRIORITY_SHIFT (19U) +#define SMIX_DMA_CH_CTL_PRIORITY_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_PRIORITY_SHIFT) & SMIX_DMA_CH_CTL_PRIORITY_MASK) +#define SMIX_DMA_CH_CTL_PRIORITY_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_PRIORITY_MASK) >> SMIX_DMA_CH_CTL_PRIORITY_SHIFT) + +/* + * SRCBURSTSIZE (RW) + * + * 0x0: 1 beat per transfer + * 0x1: 2 beats per transfer + * 0x2: 4 beats per transfer + * 0x3: 8 beats per transfer + * 0x4: 16 beats per transfer + * 0x5: 32 beats per transfer + * 0x6: 64 beats per transfer + * 0x7: 128 beats per transfer + */ +#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK (0x78000UL) +#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT (15U) +#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT) & SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK) +#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK) >> SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT) + +/* + * SRCWIDTH (RW) + * + * Source Transfer Beat Size: + * 0x0: Byte transfer + * 0x1: Half-word transfer + * 0x2: Word transfer + */ +#define SMIX_DMA_CH_CTL_SRCWIDTH_MASK (0x6000U) +#define SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT (13U) +#define SMIX_DMA_CH_CTL_SRCWIDTH_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT) & SMIX_DMA_CH_CTL_SRCWIDTH_MASK) +#define SMIX_DMA_CH_CTL_SRCWIDTH_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCWIDTH_MASK) >> SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT) + +/* + * DSTWIDTH (RW) + * + * Destination Transfer Beat Size: + * 0x0: Byte transfer + * 0x1: Half-word transfer + * 0x2: Word transfer + */ +#define SMIX_DMA_CH_CTL_DSTWIDTH_MASK (0x1800U) +#define SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT (11U) +#define SMIX_DMA_CH_CTL_DSTWIDTH_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT) & SMIX_DMA_CH_CTL_DSTWIDTH_MASK) +#define SMIX_DMA_CH_CTL_DSTWIDTH_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTWIDTH_MASK) >> SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT) + +/* + * SRCMODE (RW) + * + * DMA Source handshake mode + * 0x0: Normal mode + * 0x1: Handshake mode + */ +#define SMIX_DMA_CH_CTL_SRCMODE_MASK (0x400U) +#define SMIX_DMA_CH_CTL_SRCMODE_SHIFT (10U) +#define SMIX_DMA_CH_CTL_SRCMODE_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCMODE_SHIFT) & SMIX_DMA_CH_CTL_SRCMODE_MASK) +#define SMIX_DMA_CH_CTL_SRCMODE_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCMODE_MASK) >> SMIX_DMA_CH_CTL_SRCMODE_SHIFT) + +/* + * DSTMODE (RW) + * + * DMA Destination handshake mode + * 0x0: Normal mode + * 0x1: Handshake mode + */ +#define SMIX_DMA_CH_CTL_DSTMODE_MASK (0x200U) +#define SMIX_DMA_CH_CTL_DSTMODE_SHIFT (9U) +#define SMIX_DMA_CH_CTL_DSTMODE_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTMODE_SHIFT) & SMIX_DMA_CH_CTL_DSTMODE_MASK) +#define SMIX_DMA_CH_CTL_DSTMODE_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTMODE_MASK) >> SMIX_DMA_CH_CTL_DSTMODE_SHIFT) + +/* + * SRCADDRCTRL (RW) + * + * 0x0: Increment address + * 0x1: Decrement address + * 0x2: Fixed address + * 0x3: Reserved, setting the field with this value triggers an error exception + */ +#define SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK (0x180U) +#define SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT (7U) +#define SMIX_DMA_CH_CTL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT) & SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK) +#define SMIX_DMA_CH_CTL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK) >> SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT) + +/* + * DSTADDRCTRL (RW) + * + * 0x0: Increment address + * 0x1: Decrement address + * 0x2: Fixed address + * 0x3: Reserved, setting the field with this value triggers an error exception + */ +#define SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK (0x60U) +#define SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT (5U) +#define SMIX_DMA_CH_CTL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT) & SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK) +#define SMIX_DMA_CH_CTL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK) >> SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT) + +/* + * ABRT_INT_EN (RW) + * + * Abort interrupt enable + */ +#define SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK (0x8U) +#define SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT (3U) +#define SMIX_DMA_CH_CTL_ABRT_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK) +#define SMIX_DMA_CH_CTL_ABRT_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK) >> SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT) + +/* + * ERR_INT_EN (RW) + * + * Err interrupt enable + */ +#define SMIX_DMA_CH_CTL_ERR_INT_EN_MASK (0x4U) +#define SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT (2U) +#define SMIX_DMA_CH_CTL_ERR_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_ERR_INT_EN_MASK) +#define SMIX_DMA_CH_CTL_ERR_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_ERR_INT_EN_MASK) >> SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT) + +/* + * TC_INT_EN (RW) + * + * TC interrupt enable + */ +#define SMIX_DMA_CH_CTL_TC_INT_EN_MASK (0x2U) +#define SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT (1U) +#define SMIX_DMA_CH_CTL_TC_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_TC_INT_EN_MASK) +#define SMIX_DMA_CH_CTL_TC_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_TC_INT_EN_MASK) >> SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT) + +/* + * EN (RW) + * + * channel enable bit + */ +#define SMIX_DMA_CH_CTL_EN_MASK (0x1U) +#define SMIX_DMA_CH_CTL_EN_SHIFT (0U) +#define SMIX_DMA_CH_CTL_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_EN_SHIFT) & SMIX_DMA_CH_CTL_EN_MASK) +#define SMIX_DMA_CH_CTL_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_EN_MASK) >> SMIX_DMA_CH_CTL_EN_SHIFT) + +/* Bitfield definition for register of struct array DMA_CH: BURST_COUNT */ +/* + * NUM (RW) + * + * the total number of source beats + */ +#define SMIX_DMA_CH_BURST_COUNT_NUM_MASK (0xFFFFFFFFUL) +#define SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT (0U) +#define SMIX_DMA_CH_BURST_COUNT_NUM_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT) & SMIX_DMA_CH_BURST_COUNT_NUM_MASK) +#define SMIX_DMA_CH_BURST_COUNT_NUM_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_BURST_COUNT_NUM_MASK) >> SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT) + +/* Bitfield definition for register of struct array DMA_CH: SRCADDR */ +/* + * PTR (RW) + * + * source address + */ +#define SMIX_DMA_CH_SRCADDR_PTR_MASK (0xFFFFFFFFUL) +#define SMIX_DMA_CH_SRCADDR_PTR_SHIFT (0U) +#define SMIX_DMA_CH_SRCADDR_PTR_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_SRCADDR_PTR_SHIFT) & SMIX_DMA_CH_SRCADDR_PTR_MASK) +#define SMIX_DMA_CH_SRCADDR_PTR_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_SRCADDR_PTR_MASK) >> SMIX_DMA_CH_SRCADDR_PTR_SHIFT) + +/* Bitfield definition for register of struct array DMA_CH: DSTADDR */ +/* + * PTR (RW) + * + * destination address + */ +#define SMIX_DMA_CH_DSTADDR_PTR_MASK (0xFFFFFFFFUL) +#define SMIX_DMA_CH_DSTADDR_PTR_SHIFT (0U) +#define SMIX_DMA_CH_DSTADDR_PTR_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_DSTADDR_PTR_SHIFT) & SMIX_DMA_CH_DSTADDR_PTR_MASK) +#define SMIX_DMA_CH_DSTADDR_PTR_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_DSTADDR_PTR_MASK) >> SMIX_DMA_CH_DSTADDR_PTR_SHIFT) + +/* Bitfield definition for register of struct array DMA_CH: LLP */ +/* + * PTR (RW) + * + * the address pointer for the linked list descriptor + */ +#define SMIX_DMA_CH_LLP_PTR_MASK (0xFFFFFFFFUL) +#define SMIX_DMA_CH_LLP_PTR_SHIFT (0U) +#define SMIX_DMA_CH_LLP_PTR_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_LLP_PTR_SHIFT) & SMIX_DMA_CH_LLP_PTR_MASK) +#define SMIX_DMA_CH_LLP_PTR_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_LLP_PTR_MASK) >> SMIX_DMA_CH_LLP_PTR_SHIFT) + +/* Bitfield definition for register: CALSAT_ST */ +/* + * DST (W1C) + * + * DST CAL_SAT_ERR. W1C + */ +#define SMIX_CALSAT_ST_DST_MASK (0xC0000000UL) +#define SMIX_CALSAT_ST_DST_SHIFT (30U) +#define SMIX_CALSAT_ST_DST_SET(x) (((uint32_t)(x) << SMIX_CALSAT_ST_DST_SHIFT) & SMIX_CALSAT_ST_DST_MASK) +#define SMIX_CALSAT_ST_DST_GET(x) (((uint32_t)(x) & SMIX_CALSAT_ST_DST_MASK) >> SMIX_CALSAT_ST_DST_SHIFT) + +/* + * RRSV (RO) + * + * Reserved + */ +#define SMIX_CALSAT_ST_RRSV_MASK (0x3FFFC000UL) +#define SMIX_CALSAT_ST_RRSV_SHIFT (14U) +#define SMIX_CALSAT_ST_RRSV_GET(x) (((uint32_t)(x) & SMIX_CALSAT_ST_RRSV_MASK) >> SMIX_CALSAT_ST_RRSV_SHIFT) + +/* + * SRC (W1C) + * + * SRC CAL_SAT_ERR. W1C + */ +#define SMIX_CALSAT_ST_SRC_MASK (0x3FFFU) +#define SMIX_CALSAT_ST_SRC_SHIFT (0U) +#define SMIX_CALSAT_ST_SRC_SET(x) (((uint32_t)(x) << SMIX_CALSAT_ST_SRC_SHIFT) & SMIX_CALSAT_ST_SRC_MASK) +#define SMIX_CALSAT_ST_SRC_GET(x) (((uint32_t)(x) & SMIX_CALSAT_ST_SRC_MASK) >> SMIX_CALSAT_ST_SRC_SHIFT) + +/* Bitfield definition for register: FDOT_DONE_ST */ +/* + * DST (W1C) + * + * DST fadeout done. W1C + */ +#define SMIX_FDOT_DONE_ST_DST_MASK (0xC0000000UL) +#define SMIX_FDOT_DONE_ST_DST_SHIFT (30U) +#define SMIX_FDOT_DONE_ST_DST_SET(x) (((uint32_t)(x) << SMIX_FDOT_DONE_ST_DST_SHIFT) & SMIX_FDOT_DONE_ST_DST_MASK) +#define SMIX_FDOT_DONE_ST_DST_GET(x) (((uint32_t)(x) & SMIX_FDOT_DONE_ST_DST_MASK) >> SMIX_FDOT_DONE_ST_DST_SHIFT) + +/* + * RRSV1 (RO) + * + * Reserved + */ +#define SMIX_FDOT_DONE_ST_RRSV1_MASK (0x3FFFC000UL) +#define SMIX_FDOT_DONE_ST_RRSV1_SHIFT (14U) +#define SMIX_FDOT_DONE_ST_RRSV1_GET(x) (((uint32_t)(x) & SMIX_FDOT_DONE_ST_RRSV1_MASK) >> SMIX_FDOT_DONE_ST_RRSV1_SHIFT) + +/* + * SRC (W1C) + * + * SRC fadeout done. W1C + */ +#define SMIX_FDOT_DONE_ST_SRC_MASK (0x3FFFU) +#define SMIX_FDOT_DONE_ST_SRC_SHIFT (0U) +#define SMIX_FDOT_DONE_ST_SRC_SET(x) (((uint32_t)(x) << SMIX_FDOT_DONE_ST_SRC_SHIFT) & SMIX_FDOT_DONE_ST_SRC_MASK) +#define SMIX_FDOT_DONE_ST_SRC_GET(x) (((uint32_t)(x) & SMIX_FDOT_DONE_ST_SRC_MASK) >> SMIX_FDOT_DONE_ST_SRC_SHIFT) + +/* Bitfield definition for register: DATA_ST */ +/* + * DST_DA (RO) + * + * DST data available + */ +#define SMIX_DATA_ST_DST_DA_MASK (0xC0000000UL) +#define SMIX_DATA_ST_DST_DA_SHIFT (30U) +#define SMIX_DATA_ST_DST_DA_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_DST_DA_MASK) >> SMIX_DATA_ST_DST_DA_SHIFT) + +/* + * DST_UNDL (RO) + * + * DST data underflow + */ +#define SMIX_DATA_ST_DST_UNDL_MASK (0x30000000UL) +#define SMIX_DATA_ST_DST_UNDL_SHIFT (28U) +#define SMIX_DATA_ST_DST_UNDL_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_DST_UNDL_MASK) >> SMIX_DATA_ST_DST_UNDL_SHIFT) + +/* + * RRSV1 (RO) + * + * Reserved + */ +#define SMIX_DATA_ST_RRSV1_MASK (0xFFFC000UL) +#define SMIX_DATA_ST_RRSV1_SHIFT (14U) +#define SMIX_DATA_ST_RRSV1_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_RRSV1_MASK) >> SMIX_DATA_ST_RRSV1_SHIFT) + +/* + * SRC_DN (RO) + * + * SRC data needed + */ +#define SMIX_DATA_ST_SRC_DN_MASK (0x3FFFU) +#define SMIX_DATA_ST_SRC_DN_SHIFT (0U) +#define SMIX_DATA_ST_SRC_DN_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_SRC_DN_MASK) >> SMIX_DATA_ST_SRC_DN_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: CTRL */ +/* + * WRSV (RW) + * + * Reserved + */ +#define SMIX_DST_CH_CTRL_WRSV_MASK (0xFFE00000UL) +#define SMIX_DST_CH_CTRL_WRSV_SHIFT (21U) +#define SMIX_DST_CH_CTRL_WRSV_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_WRSV_SHIFT) & SMIX_DST_CH_CTRL_WRSV_MASK) +#define SMIX_DST_CH_CTRL_WRSV_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_WRSV_MASK) >> SMIX_DST_CH_CTRL_WRSV_SHIFT) + +/* + * DATA_UNFL_IE (RW) + * + * Data Underflow Error IntEn + */ +#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK (0x100000UL) +#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT (20U) +#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT) & SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK) +#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK) >> SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT) + +/* + * THRSH (RW) + * + * FIFO threshold for DMA or Int. >= will generate req. Must be greater or equal than 8. The read burst of DMA should make the fillings in the buffer be greater than 4. + */ +#define SMIX_DST_CH_CTRL_THRSH_MASK (0xFF000UL) +#define SMIX_DST_CH_CTRL_THRSH_SHIFT (12U) +#define SMIX_DST_CH_CTRL_THRSH_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_THRSH_SHIFT) & SMIX_DST_CH_CTRL_THRSH_MASK) +#define SMIX_DST_CH_CTRL_THRSH_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_THRSH_MASK) >> SMIX_DST_CH_CTRL_THRSH_SHIFT) + +/* + * CALSAT_INT_EN (RW) + * + * Cal Saturation IntEn + */ +#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK (0x800U) +#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT (11U) +#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT) & SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK) +#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK) >> SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT) + +/* + * DA_INT_EN (RW) + * + * Data Available IntEn + */ +#define SMIX_DST_CH_CTRL_DA_INT_EN_MASK (0x400U) +#define SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT (10U) +#define SMIX_DST_CH_CTRL_DA_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT) & SMIX_DST_CH_CTRL_DA_INT_EN_MASK) +#define SMIX_DST_CH_CTRL_DA_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DA_INT_EN_MASK) >> SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT) + +/* + * ADEACTFADEOUT_EN (RW) + * + * AutoDeactAfterFadeOut_En: + * Asserted to enter de-activated mode after fade-out done + */ +#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK (0x200U) +#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT (9U) +#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT) & SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK) +#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK) >> SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT) + +/* + * FADEOUT_DONE_IE (RW) + * + * Fade-Out interrupt enable + */ +#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK (0x100U) +#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT (8U) +#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT) & SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK) +#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK) >> SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT) + +/* + * DST_DEACT (RW) + * + * de-activate the destination channel + */ +#define SMIX_DST_CH_CTRL_DST_DEACT_MASK (0x80U) +#define SMIX_DST_CH_CTRL_DST_DEACT_SHIFT (7U) +#define SMIX_DST_CH_CTRL_DST_DEACT_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_DEACT_SHIFT) & SMIX_DST_CH_CTRL_DST_DEACT_MASK) +#define SMIX_DST_CH_CTRL_DST_DEACT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_DEACT_MASK) >> SMIX_DST_CH_CTRL_DST_DEACT_SHIFT) + +/* + * DST_ACT (RW) + * + * activate the destination channel + */ +#define SMIX_DST_CH_CTRL_DST_ACT_MASK (0x40U) +#define SMIX_DST_CH_CTRL_DST_ACT_SHIFT (6U) +#define SMIX_DST_CH_CTRL_DST_ACT_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_ACT_SHIFT) & SMIX_DST_CH_CTRL_DST_ACT_MASK) +#define SMIX_DST_CH_CTRL_DST_ACT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_ACT_MASK) >> SMIX_DST_CH_CTRL_DST_ACT_SHIFT) + +/* + * DSTFADOUT_MEN (RW) + * + * Manual FadeOut_Ctrl for destionation. Auto clear. + */ +#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK (0x20U) +#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT (5U) +#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK) +#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK) >> SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT) + +/* + * DSTFADOUT_AEN (RW) + * + * Automatically FadeOut_Ctrl for destionation. Only effective after DST_AFADEOUT is assigned a non-zero value + */ +#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK (0x10U) +#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT (4U) +#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK) +#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK) >> SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT) + +/* + * DSTFADIN_EN (RW) + * + * FadeIn_Ctrl for destionation. Auto clear. + */ +#define SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK (0x8U) +#define SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT (3U) +#define SMIX_DST_CH_CTRL_DSTFADIN_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK) +#define SMIX_DST_CH_CTRL_DSTFADIN_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK) >> SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT) + +/* + * DST_EN (RW) + * + * Dst enabled. When disabled, clear the FIFO pointers. + */ +#define SMIX_DST_CH_CTRL_DST_EN_MASK (0x4U) +#define SMIX_DST_CH_CTRL_DST_EN_SHIFT (2U) +#define SMIX_DST_CH_CTRL_DST_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_EN_SHIFT) & SMIX_DST_CH_CTRL_DST_EN_MASK) +#define SMIX_DST_CH_CTRL_DST_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_EN_MASK) >> SMIX_DST_CH_CTRL_DST_EN_SHIFT) + +/* + * SOFTRST (RW) + * + * Soft reset + */ +#define SMIX_DST_CH_CTRL_SOFTRST_MASK (0x2U) +#define SMIX_DST_CH_CTRL_SOFTRST_SHIFT (1U) +#define SMIX_DST_CH_CTRL_SOFTRST_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_SOFTRST_SHIFT) & SMIX_DST_CH_CTRL_SOFTRST_MASK) +#define SMIX_DST_CH_CTRL_SOFTRST_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_SOFTRST_MASK) >> SMIX_DST_CH_CTRL_SOFTRST_SHIFT) + +/* + * MIXER_EN (RW) + * + * mixer function enable. + */ +#define SMIX_DST_CH_CTRL_MIXER_EN_MASK (0x1U) +#define SMIX_DST_CH_CTRL_MIXER_EN_SHIFT (0U) +#define SMIX_DST_CH_CTRL_MIXER_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_MIXER_EN_SHIFT) & SMIX_DST_CH_CTRL_MIXER_EN_MASK) +#define SMIX_DST_CH_CTRL_MIXER_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_MIXER_EN_MASK) >> SMIX_DST_CH_CTRL_MIXER_EN_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: GAIN */ +/* + * WRSV (RW) + * + * Reserved + */ +#define SMIX_DST_CH_GAIN_WRSV_MASK (0xFFFF8000UL) +#define SMIX_DST_CH_GAIN_WRSV_SHIFT (15U) +#define SMIX_DST_CH_GAIN_WRSV_SET(x) (((uint32_t)(x) << SMIX_DST_CH_GAIN_WRSV_SHIFT) & SMIX_DST_CH_GAIN_WRSV_MASK) +#define SMIX_DST_CH_GAIN_WRSV_GET(x) (((uint32_t)(x) & SMIX_DST_CH_GAIN_WRSV_MASK) >> SMIX_DST_CH_GAIN_WRSV_SHIFT) + +/* + * VAL (RW) + * + * Unsigned Int, with 12 fractional bits. . The top 3 bits are for shift. Same as SHFT_CTR[2:0] + */ +#define SMIX_DST_CH_GAIN_VAL_MASK (0x7FFFU) +#define SMIX_DST_CH_GAIN_VAL_SHIFT (0U) +#define SMIX_DST_CH_GAIN_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_GAIN_VAL_SHIFT) & SMIX_DST_CH_GAIN_VAL_MASK) +#define SMIX_DST_CH_GAIN_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_GAIN_VAL_MASK) >> SMIX_DST_CH_GAIN_VAL_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: BUFSIZE */ +/* + * MAX_IDX (RW) + * + * The total length of the dst stream -1. If zero, means there is no end of the stream. + */ +#define SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK (0xFFFFFFFFUL) +#define SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT (0U) +#define SMIX_DST_CH_BUFSIZE_MAX_IDX_SET(x) (((uint32_t)(x) << SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT) & SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK) +#define SMIX_DST_CH_BUFSIZE_MAX_IDX_GET(x) (((uint32_t)(x) & SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK) >> SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: FADEIN */ +/* + * WRSV (RW) + * + */ +#define SMIX_DST_CH_FADEIN_WRSV_MASK (0xFFF00000UL) +#define SMIX_DST_CH_FADEIN_WRSV_SHIFT (20U) +#define SMIX_DST_CH_FADEIN_WRSV_SET(x) (((uint32_t)(x) << SMIX_DST_CH_FADEIN_WRSV_SHIFT) & SMIX_DST_CH_FADEIN_WRSV_MASK) +#define SMIX_DST_CH_FADEIN_WRSV_GET(x) (((uint32_t)(x) & SMIX_DST_CH_FADEIN_WRSV_MASK) >> SMIX_DST_CH_FADEIN_WRSV_SHIFT) + +/* + * DELTA (RW) + * + * Fade-in delta for linear fading in from 0 to 1 (about at most 20s for 48kHz sampled sound) + * (Using only top 14 bits for mul) + */ +#define SMIX_DST_CH_FADEIN_DELTA_MASK (0xFFFFFUL) +#define SMIX_DST_CH_FADEIN_DELTA_SHIFT (0U) +#define SMIX_DST_CH_FADEIN_DELTA_SET(x) (((uint32_t)(x) << SMIX_DST_CH_FADEIN_DELTA_SHIFT) & SMIX_DST_CH_FADEIN_DELTA_MASK) +#define SMIX_DST_CH_FADEIN_DELTA_GET(x) (((uint32_t)(x) & SMIX_DST_CH_FADEIN_DELTA_MASK) >> SMIX_DST_CH_FADEIN_DELTA_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: FADEOUT */ +/* + * WRSV (RW) + * + */ +#define SMIX_DST_CH_FADEOUT_WRSV_MASK (0xFFF00000UL) +#define SMIX_DST_CH_FADEOUT_WRSV_SHIFT (20U) +#define SMIX_DST_CH_FADEOUT_WRSV_SET(x) (((uint32_t)(x) << SMIX_DST_CH_FADEOUT_WRSV_SHIFT) & SMIX_DST_CH_FADEOUT_WRSV_MASK) +#define SMIX_DST_CH_FADEOUT_WRSV_GET(x) (((uint32_t)(x) & SMIX_DST_CH_FADEOUT_WRSV_MASK) >> SMIX_DST_CH_FADEOUT_WRSV_SHIFT) + +/* + * DELTA (RW) + * + * Fade out in 2^DELTA samples. Now DELTA can be at most 14。 + */ +#define SMIX_DST_CH_FADEOUT_DELTA_MASK (0xFFFFFUL) +#define SMIX_DST_CH_FADEOUT_DELTA_SHIFT (0U) +#define SMIX_DST_CH_FADEOUT_DELTA_SET(x) (((uint32_t)(x) << SMIX_DST_CH_FADEOUT_DELTA_SHIFT) & SMIX_DST_CH_FADEOUT_DELTA_MASK) +#define SMIX_DST_CH_FADEOUT_DELTA_GET(x) (((uint32_t)(x) & SMIX_DST_CH_FADEOUT_DELTA_MASK) >> SMIX_DST_CH_FADEOUT_DELTA_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: ST */ +/* + * RRSV (RO) + * + */ +#define SMIX_DST_CH_ST_RRSV_MASK (0xFFFF8000UL) +#define SMIX_DST_CH_ST_RRSV_SHIFT (15U) +#define SMIX_DST_CH_ST_RRSV_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_RRSV_MASK) >> SMIX_DST_CH_ST_RRSV_SHIFT) + +/* + * FIFO_FILLINGS (RO) + * + * destination channel output FIFO fillings + */ +#define SMIX_DST_CH_ST_FIFO_FILLINGS_MASK (0x7FC0U) +#define SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT (6U) +#define SMIX_DST_CH_ST_FIFO_FILLINGS_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_FIFO_FILLINGS_MASK) >> SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT) + +/* + * FDOUT_DONE (RO) + * + * Fade-Out Done. W1C + */ +#define SMIX_DST_CH_ST_FDOUT_DONE_MASK (0x20U) +#define SMIX_DST_CH_ST_FDOUT_DONE_SHIFT (5U) +#define SMIX_DST_CH_ST_FDOUT_DONE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_FDOUT_DONE_MASK) >> SMIX_DST_CH_ST_FDOUT_DONE_SHIFT) + +/* + * CALSAT (RO) + * + * Saturate Error Found. W1C + */ +#define SMIX_DST_CH_ST_CALSAT_MASK (0x10U) +#define SMIX_DST_CH_ST_CALSAT_SHIFT (4U) +#define SMIX_DST_CH_ST_CALSAT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_CALSAT_MASK) >> SMIX_DST_CH_ST_CALSAT_SHIFT) + +/* + * DA (RO) + * + * Data Available + */ +#define SMIX_DST_CH_ST_DA_MASK (0x8U) +#define SMIX_DST_CH_ST_DA_SHIFT (3U) +#define SMIX_DST_CH_ST_DA_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_DA_MASK) >> SMIX_DST_CH_ST_DA_SHIFT) + +/* + * MODE (RO) + * + * The modes are: + * Mode 0: Disabled: after reset. Program the registers, and DSTn_CTRL [DST_EN] to enter Mode 1. + * Mode 1: Enabled and not-activated. wait for DSTn_CTRL [DSTFADIN_EN] or DSTn_CTRL [DST_ACT], jump to Mode 3 or Mode 4 based on whether Fade-in enabled. + * Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will send data to DMA. Jump to Mode 4 after fadin op done. + * Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will send data to DMA. + * Mode 5: Enabled and activated and fade-out in progress: After faded out OP. Will send data to DMA. Will transfer to mode 6 or mode 7 depending on the DSTn_CTRL [ADeactFadeOut_En] cfg + * Mode 6: Enabled and activated and faded-out: faded out is done. Will send data to DMA. Will transfer to mode 7 if manual deactivated. + * Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't send data to DMA. Won't gen data avail signals. Intf register can be programmed. Will change to Mode 3 or Mode 4 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTn_CTRL [DST_EN] is assigned 0. To support a new stream or, to continue the old stream after a pause. + */ +#define SMIX_DST_CH_ST_MODE_MASK (0x7U) +#define SMIX_DST_CH_ST_MODE_SHIFT (0U) +#define SMIX_DST_CH_ST_MODE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_MODE_MASK) >> SMIX_DST_CH_ST_MODE_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: DATA */ +/* + * VAL (RO) + * + * Output data buffer + */ +#define SMIX_DST_CH_DATA_VAL_MASK (0xFFFFFFFFUL) +#define SMIX_DST_CH_DATA_VAL_SHIFT (0U) +#define SMIX_DST_CH_DATA_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DATA_VAL_MASK) >> SMIX_DST_CH_DATA_VAL_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: SOURCE_EN */ +/* + * WRSV (RW) + * + */ +#define SMIX_DST_CH_SOURCE_EN_WRSV_MASK (0xFFFFFF00UL) +#define SMIX_DST_CH_SOURCE_EN_WRSV_SHIFT (8U) +#define SMIX_DST_CH_SOURCE_EN_WRSV_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_EN_WRSV_SHIFT) & SMIX_DST_CH_SOURCE_EN_WRSV_MASK) +#define SMIX_DST_CH_SOURCE_EN_WRSV_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_EN_WRSV_MASK) >> SMIX_DST_CH_SOURCE_EN_WRSV_SHIFT) + +/* + * VAL (RW) + * + * After enabled, Data needed req will be asserted. DMA can feed in data. The channel will join in the sum operation of mixer operation. + */ +#define SMIX_DST_CH_SOURCE_EN_VAL_MASK (0xFFU) +#define SMIX_DST_CH_SOURCE_EN_VAL_SHIFT (0U) +#define SMIX_DST_CH_SOURCE_EN_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_EN_VAL_SHIFT) & SMIX_DST_CH_SOURCE_EN_VAL_MASK) +#define SMIX_DST_CH_SOURCE_EN_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_EN_VAL_MASK) >> SMIX_DST_CH_SOURCE_EN_VAL_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: SOURCE_ACT */ +/* + * WRSV (RW) + * + */ +#define SMIX_DST_CH_SOURCE_ACT_WRSV_MASK (0xFFFFFF00UL) +#define SMIX_DST_CH_SOURCE_ACT_WRSV_SHIFT (8U) +#define SMIX_DST_CH_SOURCE_ACT_WRSV_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_ACT_WRSV_SHIFT) & SMIX_DST_CH_SOURCE_ACT_WRSV_MASK) +#define SMIX_DST_CH_SOURCE_ACT_WRSV_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_ACT_WRSV_MASK) >> SMIX_DST_CH_SOURCE_ACT_WRSV_SHIFT) + +/* + * VAL (WO) + * + * Manually Activate the channel + */ +#define SMIX_DST_CH_SOURCE_ACT_VAL_MASK (0xFFU) +#define SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT (0U) +#define SMIX_DST_CH_SOURCE_ACT_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT) & SMIX_DST_CH_SOURCE_ACT_VAL_MASK) +#define SMIX_DST_CH_SOURCE_ACT_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_ACT_VAL_MASK) >> SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: SOURCE_DEACT */ +/* + * WRSV (RW) + * + */ +#define SMIX_DST_CH_SOURCE_DEACT_WRSV_MASK (0xFFFFFF00UL) +#define SMIX_DST_CH_SOURCE_DEACT_WRSV_SHIFT (8U) +#define SMIX_DST_CH_SOURCE_DEACT_WRSV_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_DEACT_WRSV_SHIFT) & SMIX_DST_CH_SOURCE_DEACT_WRSV_MASK) +#define SMIX_DST_CH_SOURCE_DEACT_WRSV_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_DEACT_WRSV_MASK) >> SMIX_DST_CH_SOURCE_DEACT_WRSV_SHIFT) + +/* + * VAL (WO) + * + * Manually DeActivate the channel + */ +#define SMIX_DST_CH_SOURCE_DEACT_VAL_MASK (0xFFU) +#define SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT (0U) +#define SMIX_DST_CH_SOURCE_DEACT_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT) & SMIX_DST_CH_SOURCE_DEACT_VAL_MASK) +#define SMIX_DST_CH_SOURCE_DEACT_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_DEACT_VAL_MASK) >> SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: SOURCE_FADEIN_CTRL */ +/* + * WRSV (RW) + * + */ +#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_WRSV_MASK (0xFFFFFF00UL) +#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_WRSV_SHIFT (8U) +#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_WRSV_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_FADEIN_CTRL_WRSV_SHIFT) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_WRSV_MASK) +#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_WRSV_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_WRSV_MASK) >> SMIX_DST_CH_SOURCE_FADEIN_CTRL_WRSV_SHIFT) + +/* + * AOP (RW) + * + * Asserted to start fade-in operation. When the amplification factors are stable, auto clear. + */ +#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK (0xFFU) +#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT (0U) +#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK) +#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK) >> SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: DEACT_ST */ +/* + * DST_DEACT (RO) + * + * Asserted when in de-active mode + */ +#define SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK (0x80000000UL) +#define SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT (31U) +#define SMIX_DST_CH_DEACT_ST_DST_DEACT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK) >> SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT) + +/* + * RRSV (RO) + * + */ +#define SMIX_DST_CH_DEACT_ST_RRSV_MASK (0x7FFFFF00UL) +#define SMIX_DST_CH_DEACT_ST_RRSV_SHIFT (8U) +#define SMIX_DST_CH_DEACT_ST_RRSV_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_RRSV_MASK) >> SMIX_DST_CH_DEACT_ST_RRSV_SHIFT) + +/* + * SRC_DEACT_ST (RO) + * + * Asserted when in de-active mode + */ +#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK (0xFFU) +#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT (0U) +#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK) >> SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT) + +/* Bitfield definition for register of struct array DST_CH: SOURCE_MFADEOUT_CTRL */ +/* + * WRSV (RW) + * + */ +#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_WRSV_MASK (0xFFFFFF00UL) +#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_WRSV_SHIFT (8U) +#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_WRSV_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_WRSV_SHIFT) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_WRSV_MASK) +#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_WRSV_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_WRSV_MASK) >> SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_WRSV_SHIFT) + +/* + * OP (RW) + * + * Asserted to start fade-out operation. When the amplification factors are stable, auto clear. + */ +#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK (0xFFU) +#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT (0U) +#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK) +#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK) >> SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: CTRL */ +/* + * WRSV (RW) + * + */ +#define SMIX_SOURCE_CH_CTRL_WRSV_MASK (0xFFC00000UL) +#define SMIX_SOURCE_CH_CTRL_WRSV_SHIFT (22U) +#define SMIX_SOURCE_CH_CTRL_WRSV_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_WRSV_SHIFT) & SMIX_SOURCE_CH_CTRL_WRSV_MASK) +#define SMIX_SOURCE_CH_CTRL_WRSV_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_WRSV_MASK) >> SMIX_SOURCE_CH_CTRL_WRSV_SHIFT) + +/* + * FIFO_RESET (RW) + * + * Asserted to reset FIFO pointer. Cleared to exit reset state. + */ +#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK (0x200000UL) +#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT (21U) +#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT) & SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK) +#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK) >> SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT) + +/* + * THRSH (RW) + * + * FIFO threshold for DMA or Int. <= will generate req. Must be greater or equal than 8. This threshold is also used to trgger the internal FIR operation. To avoid the reading and writing to the same address in the memory block, the threshold should greater than 4. + */ +#define SMIX_SOURCE_CH_CTRL_THRSH_MASK (0x1FE000UL) +#define SMIX_SOURCE_CH_CTRL_THRSH_SHIFT (13U) +#define SMIX_SOURCE_CH_CTRL_THRSH_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_THRSH_SHIFT) & SMIX_SOURCE_CH_CTRL_THRSH_MASK) +#define SMIX_SOURCE_CH_CTRL_THRSH_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_THRSH_MASK) >> SMIX_SOURCE_CH_CTRL_THRSH_SHIFT) + +/* + * CALSAT_INT_EN (RW) + * + * Cal Saturation IntEn + */ +#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK (0x1000U) +#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT (12U) +#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK) +#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT) + +/* + * DN_INT_EN (RW) + * + * Data Needed IntEn + */ +#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK (0x800U) +#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT (11U) +#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK) +#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT) + +/* + * SHFT_CTRL (RW) + * + * Shift operation after FIR + * 0: no shift (when no upsampling or up-sampling-by-2 or up-sampling-by-3) + * 1: left-shift-by-1 (when up-sampling-by-4 or up-sampling-by-6) + * 2: left-shift-by-1 (when up-sampling-by-8 or up-sampling-by-12) + * 7: /2 (when rate /2) + * Other n: shift-left-by-n, but not suggested to be used. + */ +#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK (0x700U) +#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT (8U) +#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT) & SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK) +#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK) >> SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT) + +/* + * AUTODEACTAFTERFADEOUT_EN (RW) + * + * Asserted to enter de-activated mode after fade-out done + */ +#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK (0x80U) +#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT (7U) +#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK) +#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT) + +/* + * FADEOUT_DONE_IE (RW) + * + * Fade-Out interrupt enable + */ +#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK (0x40U) +#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT (6U) +#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT) & SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK) +#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK) >> SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT) + +/* + * RATECONV (RW) + * + * 0: no rate conversion + * 1: up-conversion x2 + * 2: up-conversion x3 + * 3: up-conversion x4 + * 4: up-conversion x6 + * 5: up-conversion x8 + * 6: up-conversion x12 + * 7: down-conversion /2 + */ +#define SMIX_SOURCE_CH_CTRL_RATECONV_MASK (0x7U) +#define SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT (0U) +#define SMIX_SOURCE_CH_CTRL_RATECONV_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT) & SMIX_SOURCE_CH_CTRL_RATECONV_MASK) +#define SMIX_SOURCE_CH_CTRL_RATECONV_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_RATECONV_MASK) >> SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: GAIN */ +/* + * WRSV (RW) + * + */ +#define SMIX_SOURCE_CH_GAIN_WRSV_MASK (0xFFFF8000UL) +#define SMIX_SOURCE_CH_GAIN_WRSV_SHIFT (15U) +#define SMIX_SOURCE_CH_GAIN_WRSV_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_GAIN_WRSV_SHIFT) & SMIX_SOURCE_CH_GAIN_WRSV_MASK) +#define SMIX_SOURCE_CH_GAIN_WRSV_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_GAIN_WRSV_MASK) >> SMIX_SOURCE_CH_GAIN_WRSV_SHIFT) + +/* + * VAL (RW) + * + * Unsigned Int, with 12 fractional bits. The top 3 bits are for shift. Same as SHFT_CTR[2:0]. + */ +#define SMIX_SOURCE_CH_GAIN_VAL_MASK (0x7FFFU) +#define SMIX_SOURCE_CH_GAIN_VAL_SHIFT (0U) +#define SMIX_SOURCE_CH_GAIN_VAL_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_GAIN_VAL_SHIFT) & SMIX_SOURCE_CH_GAIN_VAL_MASK) +#define SMIX_SOURCE_CH_GAIN_VAL_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_GAIN_VAL_MASK) >> SMIX_SOURCE_CH_GAIN_VAL_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: FADEIN */ +/* + * WRSV (RW) + * + */ +#define SMIX_SOURCE_CH_FADEIN_WRSV_MASK (0xFFF00000UL) +#define SMIX_SOURCE_CH_FADEIN_WRSV_SHIFT (20U) +#define SMIX_SOURCE_CH_FADEIN_WRSV_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_FADEIN_WRSV_SHIFT) & SMIX_SOURCE_CH_FADEIN_WRSV_MASK) +#define SMIX_SOURCE_CH_FADEIN_WRSV_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_FADEIN_WRSV_MASK) >> SMIX_SOURCE_CH_FADEIN_WRSV_SHIFT) + +/* + * DELTA (RW) + * + * Fade -in confg. + */ +#define SMIX_SOURCE_CH_FADEIN_DELTA_MASK (0xFFFFFUL) +#define SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT (0U) +#define SMIX_SOURCE_CH_FADEIN_DELTA_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT) & SMIX_SOURCE_CH_FADEIN_DELTA_MASK) +#define SMIX_SOURCE_CH_FADEIN_DELTA_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_FADEIN_DELTA_MASK) >> SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: FADEOUT */ +/* + * WRSV (RW) + * + */ +#define SMIX_SOURCE_CH_FADEOUT_WRSV_MASK (0xFFF00000UL) +#define SMIX_SOURCE_CH_FADEOUT_WRSV_SHIFT (20U) +#define SMIX_SOURCE_CH_FADEOUT_WRSV_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_FADEOUT_WRSV_SHIFT) & SMIX_SOURCE_CH_FADEOUT_WRSV_MASK) +#define SMIX_SOURCE_CH_FADEOUT_WRSV_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_FADEOUT_WRSV_MASK) >> SMIX_SOURCE_CH_FADEOUT_WRSV_SHIFT) + +/* + * DELTA (RW) + * + * Fade out in 2^DELTA samples. Now DELTA can be at most 14。 + */ +#define SMIX_SOURCE_CH_FADEOUT_DELTA_MASK (0xFFFFFUL) +#define SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT (0U) +#define SMIX_SOURCE_CH_FADEOUT_DELTA_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT) & SMIX_SOURCE_CH_FADEOUT_DELTA_MASK) +#define SMIX_SOURCE_CH_FADEOUT_DELTA_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_FADEOUT_DELTA_MASK) >> SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: BUFSIZE */ +/* + * MAXIDX (RW) + * + * unit as 16-bits per sample. Zero means no length limit. = Act Len-1. + * The actual length is the up_rate*(input_data_length-4). + * If the filter processing is down-sampling, the value of up_rate above is 1. + * If the filter processing is up-sampling, the value of up_rate above is the up-sampling rate. + */ +#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK (0xFFFFFFFFUL) +#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT (0U) +#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT) & SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK) +#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK) >> SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: ST */ +/* + * FIFO_FILLINGS (RO) + * + * The fillings of input FIFO. + */ +#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK (0x7FC00UL) +#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT (10U) +#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK) >> SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT) + +/* + * FDOUT_DONE (W1C) + * + * Fade-Out Done. W1C + */ +#define SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK (0x200U) +#define SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT (9U) +#define SMIX_SOURCE_CH_ST_FDOUT_DONE_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT) & SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK) +#define SMIX_SOURCE_CH_ST_FDOUT_DONE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK) >> SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT) + +/* + * CALSAT (W1C) + * + * Calculation saturation status. W1C + */ +#define SMIX_SOURCE_CH_ST_CALSAT_MASK (0x100U) +#define SMIX_SOURCE_CH_ST_CALSAT_SHIFT (8U) +#define SMIX_SOURCE_CH_ST_CALSAT_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_ST_CALSAT_SHIFT) & SMIX_SOURCE_CH_ST_CALSAT_MASK) +#define SMIX_SOURCE_CH_ST_CALSAT_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_CALSAT_MASK) >> SMIX_SOURCE_CH_ST_CALSAT_SHIFT) + +/* + * DN (RO) + * + * Data needed flag + */ +#define SMIX_SOURCE_CH_ST_DN_MASK (0x80U) +#define SMIX_SOURCE_CH_ST_DN_SHIFT (7U) +#define SMIX_SOURCE_CH_ST_DN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_DN_MASK) >> SMIX_SOURCE_CH_ST_DN_SHIFT) + +/* + * FIRPHASE (RO) + * + * the poly phase counter + */ +#define SMIX_SOURCE_CH_ST_FIRPHASE_MASK (0x78U) +#define SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT (3U) +#define SMIX_SOURCE_CH_ST_FIRPHASE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FIRPHASE_MASK) >> SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT) + +/* + * MODE (RO) + * + * The modes are: + * Mode 0: Disabled: after reset. Program the registers, and DSTx_SRC_EN[n] to enter Mode 1. + * Mode 1: Enabled but not activated: After Enabled. Data needed signal can send out, can receive DMA data. Will enter Mode 2 after manual ACT or Fade-in CMD + * Mode 2: Enabled and activated and buffer feed-in in progress: Can not be fade out. Will consume data from DMA. If not enter due to Fade-in CMD, will enter Mode 4, else enter Mode 3. This mode is used to make the channel in MIX only after initial data are ready, thus will not stall mix operation due to the lackness of data of this channel omly. + * Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will consume data from DMA. + * Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will consume data from DMA. + * Mode 5: Enabled and activated and fade-out in progress: After faded out done. Will consume data from DMA. Will transfer to mode 6 or mode 7 depending on the SRCn_CTRL[AutoDeactAfterFadeOut_En] cfg + * Mode 6: Enabled and activated and faded-out: faded out is done. Will consume data from DMA. Will transfer to mode 7 if manual deactivated. + * Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't consume data from DMA. Won't gen data needed signals. Intf register can be programmed. Will change to Mode 2 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTx_SRC_EN[n] is assigned 0. To support a new stream or, to continue the old stream after a pause. + */ +#define SMIX_SOURCE_CH_ST_MODE_MASK (0x7U) +#define SMIX_SOURCE_CH_ST_MODE_SHIFT (0U) +#define SMIX_SOURCE_CH_ST_MODE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_MODE_MASK) >> SMIX_SOURCE_CH_ST_MODE_SHIFT) + +/* Bitfield definition for register of struct array SOURCE_CH: DATA */ +/* + * VAL (WO) + * + * Data input register + */ +#define SMIX_SOURCE_CH_DATA_VAL_MASK (0xFFFFFFFFUL) +#define SMIX_SOURCE_CH_DATA_VAL_SHIFT (0U) +#define SMIX_SOURCE_CH_DATA_VAL_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_DATA_VAL_SHIFT) & SMIX_SOURCE_CH_DATA_VAL_MASK) +#define SMIX_SOURCE_CH_DATA_VAL_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_DATA_VAL_MASK) >> SMIX_SOURCE_CH_DATA_VAL_SHIFT) + + + +/* DMA_CH register group index macro definition */ +#define SMIX_DMA_CH_0 (0UL) +#define SMIX_DMA_CH_1 (1UL) +#define SMIX_DMA_CH_2 (2UL) +#define SMIX_DMA_CH_3 (3UL) +#define SMIX_DMA_CH_4 (4UL) +#define SMIX_DMA_CH_5 (5UL) +#define SMIX_DMA_CH_6 (6UL) +#define SMIX_DMA_CH_7 (7UL) +#define SMIX_DMA_CH_8 (8UL) +#define SMIX_DMA_CH_9 (9UL) +#define SMIX_DMA_CH_10 (10UL) +#define SMIX_DMA_CH_11 (11UL) +#define SMIX_DMA_CH_12 (12UL) +#define SMIX_DMA_CH_13 (13UL) +#define SMIX_DMA_CH_14 (14UL) +#define SMIX_DMA_CH_15 (15UL) +#define SMIX_DMA_CH_16 (16UL) +#define SMIX_DMA_CH_17 (17UL) +#define SMIX_DMA_CH_18 (18UL) +#define SMIX_DMA_CH_19 (19UL) +#define SMIX_DMA_CH_20 (20UL) +#define SMIX_DMA_CH_21 (21UL) +#define SMIX_DMA_CH_22 (22UL) +#define SMIX_DMA_CH_23 (23UL) +#define SMIX_DMA_CH_24 (24UL) +#define SMIX_DMA_CH_25 (25UL) + +/* DST_CH register group index macro definition */ +#define SMIX_DST_CH_0 (0UL) +#define SMIX_DST_CH_1 (1UL) + +/* SOURCE_CH register group index macro definition */ +#define SMIX_SOURCE_CH_0 (0UL) +#define SMIX_SOURCE_CH_1 (1UL) +#define SMIX_SOURCE_CH_2 (2UL) +#define SMIX_SOURCE_CH_3 (3UL) +#define SMIX_SOURCE_CH_4 (4UL) +#define SMIX_SOURCE_CH_5 (5UL) +#define SMIX_SOURCE_CH_6 (6UL) +#define SMIX_SOURCE_CH_7 (7UL) +#define SMIX_SOURCE_CH_8 (8UL) +#define SMIX_SOURCE_CH_9 (9UL) +#define SMIX_SOURCE_CH_10 (10UL) +#define SMIX_SOURCE_CH_11 (11UL) +#define SMIX_SOURCE_CH_12 (12UL) +#define SMIX_SOURCE_CH_13 (13UL) + + +#endif /* HPM_SMIX_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h index 1e06e783..d07d09f6 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_spi_regs.h @@ -10,9 +10,13 @@ #define HPM_SPI_H typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ + __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ + __RW uint32_t WR_TRANS_CNT; /* 0x4: Transfer count for write data */ + __RW uint32_t RD_TRANS_CNT; /* 0x8: Transfer count for read data */ + __R uint8_t RESERVED1[4]; /* 0xC - 0xF: Reserved */ __RW uint32_t TRANSFMT; /* 0x10: Transfer Format Register */ - __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ + __RW uint32_t DIRECTIO; /* 0x14: Direct IO Control Register */ + __R uint8_t RESERVED2[8]; /* 0x18 - 0x1F: Reserved */ __RW uint32_t TRANSCTRL; /* 0x20: Transfer Control Register */ __RW uint32_t CMD; /* 0x24: Command Register */ __RW uint32_t ADDR; /* 0x28: Address Register */ @@ -22,14 +26,46 @@ typedef struct { __RW uint32_t INTREN; /* 0x38: Interrupt Enable Register */ __W uint32_t INTRST; /* 0x3C: Interrupt Status Register */ __RW uint32_t TIMING; /* 0x40: Interface Timing Register */ - __R uint8_t RESERVED2[28]; /* 0x44 - 0x5F: Reserved */ + __R uint8_t RESERVED3[28]; /* 0x44 - 0x5F: Reserved */ __RW uint32_t SLVST; /* 0x60: Slave Status Register */ __R uint32_t SLVDATACNT; /* 0x64: Slave Data Count Register */ - __R uint8_t RESERVED3[20]; /* 0x68 - 0x7B: Reserved */ + __R uint32_t SLVDATAWCNT; /* 0x68: WCnt */ + __R uint32_t SLVDATARCNT; /* 0x6C: RCnt */ + __R uint8_t RESERVED4[12]; /* 0x70 - 0x7B: Reserved */ __R uint32_t CONFIG; /* 0x7C: Configuration Register */ } SPI_Type; +/* Bitfield definition for register: WR_TRANS_CNT */ +/* + * WRTRANCNT (RW) + * + * Transfer count for write data + * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). + * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. + * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. + * For TransMode 0, WrTranCnt must be equal to RdTranCnt. + */ +#define SPI_WR_TRANS_CNT_WRTRANCNT_MASK (0xFFFFFFFFUL) +#define SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT (0U) +#define SPI_WR_TRANS_CNT_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT) & SPI_WR_TRANS_CNT_WRTRANCNT_MASK) +#define SPI_WR_TRANS_CNT_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_WR_TRANS_CNT_WRTRANCNT_MASK) >> SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT) + +/* Bitfield definition for register: RD_TRANS_CNT */ +/* + * RDTRANCNT (RW) + * + * Transfer count for read data + * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). + * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. + * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. + * For TransMode 0, WrTranCnt must equal RdTranCnt. + */ +#define SPI_RD_TRANS_CNT_RDTRANCNT_MASK (0xFFFFFFFFUL) +#define SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT (0U) +#define SPI_RD_TRANS_CNT_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT) & SPI_RD_TRANS_CNT_RDTRANCNT_MASK) +#define SPI_RD_TRANS_CNT_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_RD_TRANS_CNT_RDTRANCNT_MASK) >> SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT) + /* Bitfield definition for register: TRANSFMT */ /* * ADDRLEN (RW) @@ -128,6 +164,193 @@ typedef struct { #define SPI_TRANSFMT_CPHA_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPHA_SHIFT) & SPI_TRANSFMT_CPHA_MASK) #define SPI_TRANSFMT_CPHA_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPHA_MASK) >> SPI_TRANSFMT_CPHA_SHIFT) +/* Bitfield definition for register: DIRECTIO */ +/* + * DIRECTIOEN (RW) + * + * Enable Direct IO + * 0x0: Disable + * 0x1: Enable + */ +#define SPI_DIRECTIO_DIRECTIOEN_MASK (0x1000000UL) +#define SPI_DIRECTIO_DIRECTIOEN_SHIFT (24U) +#define SPI_DIRECTIO_DIRECTIOEN_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_DIRECTIOEN_SHIFT) & SPI_DIRECTIO_DIRECTIOEN_MASK) +#define SPI_DIRECTIO_DIRECTIOEN_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_DIRECTIOEN_MASK) >> SPI_DIRECTIO_DIRECTIOEN_SHIFT) + +/* + * HOLD_OE (RW) + * + * Output enable for the SPI Flash hold signal + */ +#define SPI_DIRECTIO_HOLD_OE_MASK (0x200000UL) +#define SPI_DIRECTIO_HOLD_OE_SHIFT (21U) +#define SPI_DIRECTIO_HOLD_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_OE_SHIFT) & SPI_DIRECTIO_HOLD_OE_MASK) +#define SPI_DIRECTIO_HOLD_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_OE_MASK) >> SPI_DIRECTIO_HOLD_OE_SHIFT) + +/* + * WP_OE (RW) + * + * Output enable for the SPI Flash write protect signal + */ +#define SPI_DIRECTIO_WP_OE_MASK (0x100000UL) +#define SPI_DIRECTIO_WP_OE_SHIFT (20U) +#define SPI_DIRECTIO_WP_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_OE_SHIFT) & SPI_DIRECTIO_WP_OE_MASK) +#define SPI_DIRECTIO_WP_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_OE_MASK) >> SPI_DIRECTIO_WP_OE_SHIFT) + +/* + * MISO_OE (RW) + * + * Output enable fo the SPI MISO signal + */ +#define SPI_DIRECTIO_MISO_OE_MASK (0x80000UL) +#define SPI_DIRECTIO_MISO_OE_SHIFT (19U) +#define SPI_DIRECTIO_MISO_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_OE_SHIFT) & SPI_DIRECTIO_MISO_OE_MASK) +#define SPI_DIRECTIO_MISO_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_OE_MASK) >> SPI_DIRECTIO_MISO_OE_SHIFT) + +/* + * MOSI_OE (RW) + * + * Output enable for the SPI MOSI signal + */ +#define SPI_DIRECTIO_MOSI_OE_MASK (0x40000UL) +#define SPI_DIRECTIO_MOSI_OE_SHIFT (18U) +#define SPI_DIRECTIO_MOSI_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_OE_SHIFT) & SPI_DIRECTIO_MOSI_OE_MASK) +#define SPI_DIRECTIO_MOSI_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_OE_MASK) >> SPI_DIRECTIO_MOSI_OE_SHIFT) + +/* + * SCLK_OE (RW) + * + * Output enable for the SPI SCLK signal + */ +#define SPI_DIRECTIO_SCLK_OE_MASK (0x20000UL) +#define SPI_DIRECTIO_SCLK_OE_SHIFT (17U) +#define SPI_DIRECTIO_SCLK_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_OE_SHIFT) & SPI_DIRECTIO_SCLK_OE_MASK) +#define SPI_DIRECTIO_SCLK_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_OE_MASK) >> SPI_DIRECTIO_SCLK_OE_SHIFT) + +/* + * CS_OE (RW) + * + * Output enable for SPI CS (chip select) signal + */ +#define SPI_DIRECTIO_CS_OE_MASK (0x10000UL) +#define SPI_DIRECTIO_CS_OE_SHIFT (16U) +#define SPI_DIRECTIO_CS_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_OE_SHIFT) & SPI_DIRECTIO_CS_OE_MASK) +#define SPI_DIRECTIO_CS_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_OE_MASK) >> SPI_DIRECTIO_CS_OE_SHIFT) + +/* + * HOLD_O (RW) + * + * Output value for the SPI Flash hold signal + */ +#define SPI_DIRECTIO_HOLD_O_MASK (0x2000U) +#define SPI_DIRECTIO_HOLD_O_SHIFT (13U) +#define SPI_DIRECTIO_HOLD_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_O_SHIFT) & SPI_DIRECTIO_HOLD_O_MASK) +#define SPI_DIRECTIO_HOLD_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_O_MASK) >> SPI_DIRECTIO_HOLD_O_SHIFT) + +/* + * WP_O (RW) + * + * Output value for the SPI Flash write protect signal + */ +#define SPI_DIRECTIO_WP_O_MASK (0x1000U) +#define SPI_DIRECTIO_WP_O_SHIFT (12U) +#define SPI_DIRECTIO_WP_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_O_SHIFT) & SPI_DIRECTIO_WP_O_MASK) +#define SPI_DIRECTIO_WP_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_O_MASK) >> SPI_DIRECTIO_WP_O_SHIFT) + +/* + * MISO_O (RW) + * + * Output value for the SPI MISO signal + */ +#define SPI_DIRECTIO_MISO_O_MASK (0x800U) +#define SPI_DIRECTIO_MISO_O_SHIFT (11U) +#define SPI_DIRECTIO_MISO_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_O_SHIFT) & SPI_DIRECTIO_MISO_O_MASK) +#define SPI_DIRECTIO_MISO_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_O_MASK) >> SPI_DIRECTIO_MISO_O_SHIFT) + +/* + * MOSI_O (RW) + * + * Output value for the SPI MOSI signal + */ +#define SPI_DIRECTIO_MOSI_O_MASK (0x400U) +#define SPI_DIRECTIO_MOSI_O_SHIFT (10U) +#define SPI_DIRECTIO_MOSI_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_O_SHIFT) & SPI_DIRECTIO_MOSI_O_MASK) +#define SPI_DIRECTIO_MOSI_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_O_MASK) >> SPI_DIRECTIO_MOSI_O_SHIFT) + +/* + * SCLK_O (RW) + * + * Output value for the SPI SCLK signal + */ +#define SPI_DIRECTIO_SCLK_O_MASK (0x200U) +#define SPI_DIRECTIO_SCLK_O_SHIFT (9U) +#define SPI_DIRECTIO_SCLK_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_O_SHIFT) & SPI_DIRECTIO_SCLK_O_MASK) +#define SPI_DIRECTIO_SCLK_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_O_MASK) >> SPI_DIRECTIO_SCLK_O_SHIFT) + +/* + * CS_O (RW) + * + * Output value for the SPI CS (chip select) signal + */ +#define SPI_DIRECTIO_CS_O_MASK (0x100U) +#define SPI_DIRECTIO_CS_O_SHIFT (8U) +#define SPI_DIRECTIO_CS_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_O_SHIFT) & SPI_DIRECTIO_CS_O_MASK) +#define SPI_DIRECTIO_CS_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_O_MASK) >> SPI_DIRECTIO_CS_O_SHIFT) + +/* + * HOLD_I (RO) + * + * Status of the SPI Flash hold signal + */ +#define SPI_DIRECTIO_HOLD_I_MASK (0x20U) +#define SPI_DIRECTIO_HOLD_I_SHIFT (5U) +#define SPI_DIRECTIO_HOLD_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_I_MASK) >> SPI_DIRECTIO_HOLD_I_SHIFT) + +/* + * WP_I (RO) + * + * Status of the SPI Flash write protect signal + */ +#define SPI_DIRECTIO_WP_I_MASK (0x10U) +#define SPI_DIRECTIO_WP_I_SHIFT (4U) +#define SPI_DIRECTIO_WP_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_I_MASK) >> SPI_DIRECTIO_WP_I_SHIFT) + +/* + * MISO_I (RO) + * + * Status of the SPI MISO signal + */ +#define SPI_DIRECTIO_MISO_I_MASK (0x8U) +#define SPI_DIRECTIO_MISO_I_SHIFT (3U) +#define SPI_DIRECTIO_MISO_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_I_MASK) >> SPI_DIRECTIO_MISO_I_SHIFT) + +/* + * MOSI_I (RO) + * + * Status of the SPI MOSI signal + */ +#define SPI_DIRECTIO_MOSI_I_MASK (0x4U) +#define SPI_DIRECTIO_MOSI_I_SHIFT (2U) +#define SPI_DIRECTIO_MOSI_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_I_MASK) >> SPI_DIRECTIO_MOSI_I_SHIFT) + +/* + * SCLK_I (RO) + * + * Status of the SPI SCLK signal + */ +#define SPI_DIRECTIO_SCLK_I_MASK (0x2U) +#define SPI_DIRECTIO_SCLK_I_SHIFT (1U) +#define SPI_DIRECTIO_SCLK_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_I_MASK) >> SPI_DIRECTIO_SCLK_I_SHIFT) + +/* + * CS_I (RO) + * + * Status of the SPI CS (chip select) signal + */ +#define SPI_DIRECTIO_CS_I_MASK (0x1U) +#define SPI_DIRECTIO_CS_I_SHIFT (0U) +#define SPI_DIRECTIO_CS_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_I_MASK) >> SPI_DIRECTIO_CS_I_SHIFT) + /* Bitfield definition for register: TRANSCTRL */ /* * SLVDATAONLY (RW) @@ -320,6 +543,15 @@ typedef struct { #define SPI_DATA_DATA_GET(x) (((uint32_t)(x) & SPI_DATA_DATA_MASK) >> SPI_DATA_DATA_SHIFT) /* Bitfield definition for register: CTRL */ +/* + * CS_EN (RW) + * + */ +#define SPI_CTRL_CS_EN_MASK (0xF000000UL) +#define SPI_CTRL_CS_EN_SHIFT (24U) +#define SPI_CTRL_CS_EN_SET(x) (((uint32_t)(x) << SPI_CTRL_CS_EN_SHIFT) & SPI_CTRL_CS_EN_MASK) +#define SPI_CTRL_CS_EN_GET(x) (((uint32_t)(x) & SPI_CTRL_CS_EN_MASK) >> SPI_CTRL_CS_EN_SHIFT) + /* * TXTHRES (RW) * @@ -718,6 +950,24 @@ typedef struct { #define SPI_SLVDATACNT_RCNT_SHIFT (0U) #define SPI_SLVDATACNT_RCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_RCNT_MASK) >> SPI_SLVDATACNT_RCNT_SHIFT) +/* Bitfield definition for register: SLVDATAWCNT */ +/* + * VAL (RO) + * + */ +#define SPI_SLVDATAWCNT_VAL_MASK (0xFFFFFFFFUL) +#define SPI_SLVDATAWCNT_VAL_SHIFT (0U) +#define SPI_SLVDATAWCNT_VAL_GET(x) (((uint32_t)(x) & SPI_SLVDATAWCNT_VAL_MASK) >> SPI_SLVDATAWCNT_VAL_SHIFT) + +/* Bitfield definition for register: SLVDATARCNT */ +/* + * VAL (RO) + * + */ +#define SPI_SLVDATARCNT_VAL_MASK (0xFFFFFFFFUL) +#define SPI_SLVDATARCNT_VAL_SHIFT (0U) +#define SPI_SLVDATARCNT_VAL_GET(x) (((uint32_t)(x) & SPI_SLVDATARCNT_VAL_MASK) >> SPI_SLVDATARCNT_VAL_SHIFT) + /* Bitfield definition for register: CONFIG */ /* * SLAVE (RO) @@ -781,4 +1031,4 @@ typedef struct { -#endif /* HPM_SPI_H */ \ No newline at end of file +#endif /* HPM_SPI_H */ diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h index 4b806a0e..a332d81b 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_synt_regs.h @@ -12,10 +12,10 @@ typedef struct { __RW uint32_t GCR; /* 0x0: Global control register */ __RW uint32_t RLD; /* 0x4: Counter reload register */ - __RW uint32_t SYNT_NEW; /* 0x8: sync timer new value register */ + __RW uint32_t TIMESTAMP_NEW; /* 0x8: timestamp new value register */ __R uint32_t CNT; /* 0xC: Counter */ - __R uint32_t SYNT_SAVE; /* 0x10: sync timer trig save value */ - __R uint32_t SYNT_READ; /* 0x14: sync timer read value */ + __R uint32_t TIMESTAMP_SAV; /* 0x10: timestamp trig save value */ + __R uint32_t TIMESTAMP_CUR; /* 0x14: timestamp read value */ __R uint8_t RESERVED0[8]; /* 0x18 - 0x1F: Reserved */ __RW uint32_t CMP[4]; /* 0x20 - 0x2C: Comparator */ } SYNT_Type; @@ -23,74 +23,74 @@ typedef struct { /* Bitfield definition for register: GCR */ /* - * SYNC_TIMER_INC (WO) + * TIMESTAMP_INC_NEW (WO) * - * set to increase the sync timer with new_value, auto clr + * set to increase the timesamp with new value, auto clr */ -#define SYNT_GCR_SYNC_TIMER_INC_MASK (0x80000000UL) -#define SYNT_GCR_SYNC_TIMER_INC_SHIFT (31U) -#define SYNT_GCR_SYNC_TIMER_INC_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_INC_SHIFT) & SYNT_GCR_SYNC_TIMER_INC_MASK) -#define SYNT_GCR_SYNC_TIMER_INC_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_INC_MASK) >> SYNT_GCR_SYNC_TIMER_INC_SHIFT) +#define SYNT_GCR_TIMESTAMP_INC_NEW_MASK (0x80000000UL) +#define SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT (31U) +#define SYNT_GCR_TIMESTAMP_INC_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_INC_NEW_MASK) +#define SYNT_GCR_TIMESTAMP_INC_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_INC_NEW_MASK) >> SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT) /* - * SYNC_TIMER_DEC (WO) + * TIMESTAMP_DEC_NEW (WO) * - * set to decrease the sync timer with new_value, auto clr + * set to decrease the timesamp with new value, auto clr */ -#define SYNT_GCR_SYNC_TIMER_DEC_MASK (0x40000000UL) -#define SYNT_GCR_SYNC_TIMER_DEC_SHIFT (30U) -#define SYNT_GCR_SYNC_TIMER_DEC_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_DEC_SHIFT) & SYNT_GCR_SYNC_TIMER_DEC_MASK) -#define SYNT_GCR_SYNC_TIMER_DEC_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_DEC_MASK) >> SYNT_GCR_SYNC_TIMER_DEC_SHIFT) +#define SYNT_GCR_TIMESTAMP_DEC_NEW_MASK (0x40000000UL) +#define SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT (30U) +#define SYNT_GCR_TIMESTAMP_DEC_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_DEC_NEW_MASK) +#define SYNT_GCR_TIMESTAMP_DEC_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_DEC_NEW_MASK) >> SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT) /* - * SYNC_TIMER_NEW (WO) + * TIMESTAMP_SET_NEW (WO) * - * set the sync timer to new_value, auto clr + * set the timesamp to new value, auto clr */ -#define SYNT_GCR_SYNC_TIMER_NEW_MASK (0x20000000UL) -#define SYNT_GCR_SYNC_TIMER_NEW_SHIFT (29U) -#define SYNT_GCR_SYNC_TIMER_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_NEW_SHIFT) & SYNT_GCR_SYNC_TIMER_NEW_MASK) -#define SYNT_GCR_SYNC_TIMER_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_NEW_MASK) >> SYNT_GCR_SYNC_TIMER_NEW_SHIFT) +#define SYNT_GCR_TIMESTAMP_SET_NEW_MASK (0x20000000UL) +#define SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT (29U) +#define SYNT_GCR_TIMESTAMP_SET_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_SET_NEW_MASK) +#define SYNT_GCR_TIMESTAMP_SET_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_SET_NEW_MASK) >> SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT) /* - * SYNC_TIMER_RESET (WO) + * TIMESTAMP_RESET (WO) * - * reset sync timer to 0, auto clr + * reset timesamp to 0, auto clr */ -#define SYNT_GCR_SYNC_TIMER_RESET_MASK (0x10000000UL) -#define SYNT_GCR_SYNC_TIMER_RESET_SHIFT (28U) -#define SYNT_GCR_SYNC_TIMER_RESET_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_RESET_SHIFT) & SYNT_GCR_SYNC_TIMER_RESET_MASK) -#define SYNT_GCR_SYNC_TIMER_RESET_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_RESET_MASK) >> SYNT_GCR_SYNC_TIMER_RESET_SHIFT) +#define SYNT_GCR_TIMESTAMP_RESET_MASK (0x10000000UL) +#define SYNT_GCR_TIMESTAMP_RESET_SHIFT (28U) +#define SYNT_GCR_TIMESTAMP_RESET_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_RESET_SHIFT) & SYNT_GCR_TIMESTAMP_RESET_MASK) +#define SYNT_GCR_TIMESTAMP_RESET_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_RESET_MASK) >> SYNT_GCR_TIMESTAMP_RESET_SHIFT) /* - * SYNC_TIMER_STOPEN (RW) + * TIMESTAMP_DEBUG_EN (RW) * - * set to enable cpu_debug_mode to stop the sync timer + * set to enable cpu_debug_mode to stop the timesamp */ -#define SYNT_GCR_SYNC_TIMER_STOPEN_MASK (0x20U) -#define SYNT_GCR_SYNC_TIMER_STOPEN_SHIFT (5U) -#define SYNT_GCR_SYNC_TIMER_STOPEN_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_STOPEN_SHIFT) & SYNT_GCR_SYNC_TIMER_STOPEN_MASK) -#define SYNT_GCR_SYNC_TIMER_STOPEN_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_STOPEN_MASK) >> SYNT_GCR_SYNC_TIMER_STOPEN_SHIFT) +#define SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK (0x20U) +#define SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT (5U) +#define SYNT_GCR_TIMESTAMP_DEBUG_EN_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT) & SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK) +#define SYNT_GCR_TIMESTAMP_DEBUG_EN_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK) >> SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT) /* - * SYNC_TIMER_ENABLE (RW) + * TIMESTAMP_ENABLE (RW) * - * set to enable the sync timer, clr to stop + * set to enable the timesamp , clr to stop */ -#define SYNT_GCR_SYNC_TIMER_ENABLE_MASK (0x10U) -#define SYNT_GCR_SYNC_TIMER_ENABLE_SHIFT (4U) -#define SYNT_GCR_SYNC_TIMER_ENABLE_SET(x) (((uint32_t)(x) << SYNT_GCR_SYNC_TIMER_ENABLE_SHIFT) & SYNT_GCR_SYNC_TIMER_ENABLE_MASK) -#define SYNT_GCR_SYNC_TIMER_ENABLE_GET(x) (((uint32_t)(x) & SYNT_GCR_SYNC_TIMER_ENABLE_MASK) >> SYNT_GCR_SYNC_TIMER_ENABLE_SHIFT) +#define SYNT_GCR_TIMESTAMP_ENABLE_MASK (0x10U) +#define SYNT_GCR_TIMESTAMP_ENABLE_SHIFT (4U) +#define SYNT_GCR_TIMESTAMP_ENABLE_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_ENABLE_SHIFT) & SYNT_GCR_TIMESTAMP_ENABLE_MASK) +#define SYNT_GCR_TIMESTAMP_ENABLE_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_ENABLE_MASK) >> SYNT_GCR_TIMESTAMP_ENABLE_SHIFT) /* - * STOPEN (RW) + * COUNTER_DEBUG_EN (RW) * * set to enable cpu_debug_mode to stop the counter */ -#define SYNT_GCR_STOPEN_MASK (0x4U) -#define SYNT_GCR_STOPEN_SHIFT (2U) -#define SYNT_GCR_STOPEN_SET(x) (((uint32_t)(x) << SYNT_GCR_STOPEN_SHIFT) & SYNT_GCR_STOPEN_MASK) -#define SYNT_GCR_STOPEN_GET(x) (((uint32_t)(x) & SYNT_GCR_STOPEN_MASK) >> SYNT_GCR_STOPEN_SHIFT) +#define SYNT_GCR_COUNTER_DEBUG_EN_MASK (0x4U) +#define SYNT_GCR_COUNTER_DEBUG_EN_SHIFT (2U) +#define SYNT_GCR_COUNTER_DEBUG_EN_SET(x) (((uint32_t)(x) << SYNT_GCR_COUNTER_DEBUG_EN_SHIFT) & SYNT_GCR_COUNTER_DEBUG_EN_MASK) +#define SYNT_GCR_COUNTER_DEBUG_EN_GET(x) (((uint32_t)(x) & SYNT_GCR_COUNTER_DEBUG_EN_MASK) >> SYNT_GCR_COUNTER_DEBUG_EN_SHIFT) /* * CRST (RW) @@ -123,16 +123,16 @@ typedef struct { #define SYNT_RLD_RLD_SET(x) (((uint32_t)(x) << SYNT_RLD_RLD_SHIFT) & SYNT_RLD_RLD_MASK) #define SYNT_RLD_RLD_GET(x) (((uint32_t)(x) & SYNT_RLD_RLD_MASK) >> SYNT_RLD_RLD_SHIFT) -/* Bitfield definition for register: SYNT_NEW */ +/* Bitfield definition for register: TIMESTAMP_NEW */ /* - * NEW_VALUE (RW) + * VALUE (RW) * - * new value for sync timer, can be used as update/inc/dec + * new value for timesamp , can be used as set/inc/dec */ -#define SYNT_SYNT_NEW_NEW_VALUE_MASK (0xFFFFFFFFUL) -#define SYNT_SYNT_NEW_NEW_VALUE_SHIFT (0U) -#define SYNT_SYNT_NEW_NEW_VALUE_SET(x) (((uint32_t)(x) << SYNT_SYNT_NEW_NEW_VALUE_SHIFT) & SYNT_SYNT_NEW_NEW_VALUE_MASK) -#define SYNT_SYNT_NEW_NEW_VALUE_GET(x) (((uint32_t)(x) & SYNT_SYNT_NEW_NEW_VALUE_MASK) >> SYNT_SYNT_NEW_NEW_VALUE_SHIFT) +#define SYNT_TIMESTAMP_NEW_VALUE_MASK (0xFFFFFFFFUL) +#define SYNT_TIMESTAMP_NEW_VALUE_SHIFT (0U) +#define SYNT_TIMESTAMP_NEW_VALUE_SET(x) (((uint32_t)(x) << SYNT_TIMESTAMP_NEW_VALUE_SHIFT) & SYNT_TIMESTAMP_NEW_VALUE_MASK) +#define SYNT_TIMESTAMP_NEW_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_NEW_VALUE_MASK) >> SYNT_TIMESTAMP_NEW_VALUE_SHIFT) /* Bitfield definition for register: CNT */ /* @@ -144,25 +144,25 @@ typedef struct { #define SYNT_CNT_CNT_SHIFT (0U) #define SYNT_CNT_CNT_GET(x) (((uint32_t)(x) & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT) -/* Bitfield definition for register: SYNT_SAVE */ +/* Bitfield definition for register: TIMESTAMP_SAV */ /* - * TIME_SAVE (RO) + * VALUE (RO) * - * use the trigger to save sync timer here + * use the trigger to save timesamp here */ -#define SYNT_SYNT_SAVE_TIME_SAVE_MASK (0xFFFFFFFFUL) -#define SYNT_SYNT_SAVE_TIME_SAVE_SHIFT (0U) -#define SYNT_SYNT_SAVE_TIME_SAVE_GET(x) (((uint32_t)(x) & SYNT_SYNT_SAVE_TIME_SAVE_MASK) >> SYNT_SYNT_SAVE_TIME_SAVE_SHIFT) +#define SYNT_TIMESTAMP_SAV_VALUE_MASK (0xFFFFFFFFUL) +#define SYNT_TIMESTAMP_SAV_VALUE_SHIFT (0U) +#define SYNT_TIMESTAMP_SAV_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_SAV_VALUE_MASK) >> SYNT_TIMESTAMP_SAV_VALUE_SHIFT) -/* Bitfield definition for register: SYNT_READ */ +/* Bitfield definition for register: TIMESTAMP_CUR */ /* - * SYNC_TIME (RO) + * VALUE (RO) * - * current sync timer value + * current timesamp value */ -#define SYNT_SYNT_READ_SYNC_TIME_MASK (0xFFFFFFFFUL) -#define SYNT_SYNT_READ_SYNC_TIME_SHIFT (0U) -#define SYNT_SYNT_READ_SYNC_TIME_GET(x) (((uint32_t)(x) & SYNT_SYNT_READ_SYNC_TIME_MASK) >> SYNT_SYNT_READ_SYNC_TIME_SHIFT) +#define SYNT_TIMESTAMP_CUR_VALUE_MASK (0xFFFFFFFFUL) +#define SYNT_TIMESTAMP_CUR_VALUE_SHIFT (0U) +#define SYNT_TIMESTAMP_CUR_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_CUR_VALUE_MASK) >> SYNT_TIMESTAMP_CUR_VALUE_SHIFT) /* Bitfield definition for register array: CMP */ /* diff --git a/common/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h b/common/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h index 7d00611c..34afa0f7 100644 --- a/common/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h +++ b/common/libraries/hpm_sdk/soc/ip/hpm_uart_regs.h @@ -35,6 +35,7 @@ typedef struct { __RW uint32_t MCR; /* 0x30: Modem Control Register ( */ __R uint32_t LSR; /* 0x34: Line Status Register */ __R uint32_t MSR; /* 0x38: Modem Status Register */ + __RW uint32_t GPR; /* 0x3C: GPR Register */ } UART_Type; @@ -1026,6 +1027,17 @@ typedef struct { #define UART_MSR_DCTS_SHIFT (0U) #define UART_MSR_DCTS_GET(x) (((uint32_t)(x) & UART_MSR_DCTS_MASK) >> UART_MSR_DCTS_SHIFT) +/* Bitfield definition for register: GPR */ +/* + * DATA (RW) + * + * An one-byte storage register + */ +#define UART_GPR_DATA_MASK (0xFFU) +#define UART_GPR_DATA_SHIFT (0U) +#define UART_GPR_DATA_SET(x) (((uint32_t)(x) << UART_GPR_DATA_SHIFT) & UART_GPR_DATA_MASK) +#define UART_GPR_DATA_GET(x) (((uint32_t)(x) & UART_GPR_DATA_MASK) >> UART_GPR_DATA_SHIFT) + diff --git a/common/libraries/hpm_sdk/utils/CMakeLists.txt b/common/libraries/hpm_sdk/utils/CMakeLists.txt index 9b176d59..be1f74fd 100644 --- a/common/libraries/hpm_sdk/utils/CMakeLists.txt +++ b/common/libraries/hpm_sdk/utils/CMakeLists.txt @@ -5,3 +5,4 @@ sdk_inc(.) sdk_src(hpm_sbrk.c) sdk_src(hpm_swap.c) sdk_src(hpm_ffssi.c) +sdk_src(hpm_crc32.c) diff --git a/common/libraries/hpm_sdk/utils/hpm_crc32.c b/common/libraries/hpm_sdk/utils/hpm_crc32.c new file mode 100644 index 00000000..c1134d4d --- /dev/null +++ b/common/libraries/hpm_sdk/utils/hpm_crc32.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "hpm_crc32.h" + + +uint32_t crc32(const uint8_t *buf, uint32_t len) +{ + uint8_t i; + uint32_t crc = 0xFFFFFFFF; + while (len--) { + crc ^= *buf++; + for (i = 0; i < 8; ++i) { + if (crc & 1) + crc = (crc >> 1) ^ 0xEDB88320; + else + crc = (crc >> 1); + } + } + + return ~crc; +} diff --git a/common/libraries/hpm_sdk/utils/hpm_crc32.h b/common/libraries/hpm_sdk/utils/hpm_crc32.h new file mode 100644 index 00000000..82245e8c --- /dev/null +++ b/common/libraries/hpm_sdk/utils/hpm_crc32.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_CRC32_H +#define _HPM_CRC32_H + +#include +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +uint32_t crc32(const uint8_t *buf, uint32_t len); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif \ No newline at end of file diff --git a/common/startup/HPM5361/SConscript b/common/startup/HPM5361/SConscript new file mode 100644 index 00000000..406b1414 --- /dev/null +++ b/common/startup/HPM5361/SConscript @@ -0,0 +1,22 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Split(''' + startup.c + trap.c +''') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D25', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/common/startup/HPM5361/startup.c b/common/startup/HPM5361/startup.c new file mode 100644 index 00000000..b0bab335 --- /dev/null +++ b/common/startup/HPM5361/startup.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__etext + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + } +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + /* Do global constructors */ + __libc_init_array(); + + + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init() +{ +} diff --git a/common/startup/HPM5361/toolchains/gcc/port_gcc.S b/common/startup/HPM5361/toolchains/gcc/port_gcc.S new file mode 100644 index 00000000..2708b48e --- /dev/null +++ b/common/startup/HPM5361/toolchains/gcc/port_gcc.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "cpuport.h" + + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr t1, mcause + andi t1, t1, 0x3FF + /* get ISR */ + la t2, trap_entry + jalr t2 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/common/startup/HPM5361/toolchains/gcc/start.S b/common/startup/HPM5361/toolchains/gcc/start.S new file mode 100644 index 00000000..df204d00 --- /dev/null +++ b/common/startup/HPM5361/toolchains/gcc/start.S @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer + .option pop + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + /* Disable Vector mode */ + csrci CSR_MMISC_CTL, 2 + /* Initialize trap_entry base */ + la t0, SW_handler + csrw mtvec, t0 + + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .global default_irq_handler + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/common/startup/HPM5361/toolchains/gcc/vectors.S b/common/startup/HPM5361/toolchains/gcc/vectors.S new file mode 100644 index 00000000..5703e223 --- /dev/null +++ b/common/startup/HPM5361/toolchains/gcc/vectors.S @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +.section .vector_table, "a" +.global __vector_table +.align 9 + +__vector_table: + .weak default_isr_trap + .set default_isr_trap, SW_handler + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ + IRQ_HANDLER 8 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 9 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */ + IRQ_HANDLER 15 /* ADC0 IRQ handler */ + IRQ_HANDLER 16 /* ADC1 IRQ handler */ + IRQ_HANDLER 17 /* ADC2 IRQ handler */ + IRQ_HANDLER 18 /* SDFM IRQ handler */ + IRQ_HANDLER 19 /* DAC0 IRQ handler */ + IRQ_HANDLER 20 /* DAC1 IRQ handler */ + IRQ_HANDLER 21 /* ACMP[0] IRQ handler */ + IRQ_HANDLER 22 /* ACMP[1] IRQ handler */ + IRQ_HANDLER 23 /* ACMP[2] IRQ handler */ + IRQ_HANDLER 24 /* ACMP[3] IRQ handler */ + IRQ_HANDLER 25 /* SPI0 IRQ handler */ + IRQ_HANDLER 26 /* SPI1 IRQ handler */ + IRQ_HANDLER 27 /* SPI2 IRQ handler */ + IRQ_HANDLER 28 /* SPI3 IRQ handler */ + IRQ_HANDLER 29 /* UART0 IRQ handler */ + IRQ_HANDLER 30 /* UART1 IRQ handler */ + IRQ_HANDLER 31 /* UART2 IRQ handler */ + IRQ_HANDLER 32 /* UART3 IRQ handler */ + IRQ_HANDLER 33 /* UART4 IRQ handler */ + IRQ_HANDLER 34 /* UART5 IRQ handler */ + IRQ_HANDLER 35 /* UART6 IRQ handler */ + IRQ_HANDLER 36 /* UART7 IRQ handler */ + IRQ_HANDLER 37 /* CAN0 IRQ handler */ + IRQ_HANDLER 38 /* CAN1 IRQ handler */ + IRQ_HANDLER 39 /* CAN2 IRQ handler */ + IRQ_HANDLER 40 /* CAN3 IRQ handler */ + IRQ_HANDLER 41 /* PTPC IRQ handler */ + IRQ_HANDLER 42 /* WDG0 IRQ handler */ + IRQ_HANDLER 43 /* WDG1 IRQ handler */ + IRQ_HANDLER 44 /* TSNS IRQ handler */ + IRQ_HANDLER 45 /* MBX0A IRQ handler */ + IRQ_HANDLER 46 /* MBX0B IRQ handler */ + IRQ_HANDLER 47 /* MBX1A IRQ handler */ + IRQ_HANDLER 48 /* MBX1B IRQ handler */ + IRQ_HANDLER 49 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 50 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 51 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 52 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 53 /* I2C0 IRQ handler */ + IRQ_HANDLER 54 /* I2C1 IRQ handler */ + IRQ_HANDLER 55 /* I2C2 IRQ handler */ + IRQ_HANDLER 56 /* I2C3 IRQ handler */ + IRQ_HANDLER 57 /* PWM0 IRQ handler */ + IRQ_HANDLER 58 /* HALL0 IRQ handler */ + IRQ_HANDLER 59 /* QEI0 IRQ handler */ + IRQ_HANDLER 60 /* PWM1 IRQ handler */ + IRQ_HANDLER 61 /* HALL1 IRQ handler */ + IRQ_HANDLER 62 /* QEI1 IRQ handler */ + IRQ_HANDLER 63 /* PWM2 IRQ handler */ + IRQ_HANDLER 64 /* HALL2 IRQ handler */ + IRQ_HANDLER 65 /* QEI2 IRQ handler */ + IRQ_HANDLER 66 /* PWM3 IRQ handler */ + IRQ_HANDLER 67 /* HALL3 IRQ handler */ + IRQ_HANDLER 68 /* QEI3 IRQ handler */ + IRQ_HANDLER 69 /* SDP IRQ handler */ + IRQ_HANDLER 70 /* XPI0 IRQ handler */ + IRQ_HANDLER 71 /* XDMA IRQ handler */ + IRQ_HANDLER 72 /* HDMA IRQ handler */ + IRQ_HANDLER 73 /* RNG IRQ handler */ + IRQ_HANDLER 74 /* USB0 IRQ handler */ + IRQ_HANDLER 75 /* PSEC IRQ handler */ + IRQ_HANDLER 76 /* PGPIO IRQ handler */ + IRQ_HANDLER 77 /* PWDG IRQ handler */ + IRQ_HANDLER 78 /* PTMR IRQ handler */ + IRQ_HANDLER 79 /* PUART IRQ handler */ + IRQ_HANDLER 80 /* FUSE IRQ handler */ + IRQ_HANDLER 81 /* SECMON IRQ handler */ + IRQ_HANDLER 82 /* RTC IRQ handler */ + IRQ_HANDLER 83 /* BUTN IRQ handler */ + IRQ_HANDLER 84 /* BGPIO IRQ handler */ + IRQ_HANDLER 85 /* BVIO IRQ handler */ + IRQ_HANDLER 86 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 87 /* SYSCTL IRQ handler */ + IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */ + IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */ + IRQ_HANDLER 90 /* LIN0 IRQ handler */ + IRQ_HANDLER 91 /* LIN1 IRQ handler */ + IRQ_HANDLER 92 /* LIN2 IRQ handler */ + IRQ_HANDLER 93 /* LIN3 IRQ handler */ + diff --git a/common/startup/HPM5361/trap.c b/common/startup/HPM5361/trap.c new file mode 100644 index 00000000..b87eaee5 --- /dev/null +++ b/common/startup/HPM5361/trap.c @@ -0,0 +1,304 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "rt_hw_stack_frame.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#ifdef DEBUG +#define RT_EXCEPTION_TRACE rt_kprintf +#else +#define RT_EXCEPTION_TRACE(...) +#endif + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +void rt_show_stack_frame(void) +{ + RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n"); + RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + default: + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { + } +} + +void trap_entry(void); + +void trap_entry(void) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} diff --git a/projects/adc_example/.cproject b/projects/adc_example/.cproject index d731ca0c..c9f37838 100644 --- a/projects/adc_example/.cproject +++ b/projects/adc_example/.cproject @@ -21,13 +21,13 @@ -