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rtl8xxxu.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2014 - 2017 Jes Sorensen <[email protected]>
*
* Register definitions taken from original Realtek rtl8723au driver
*/
#include <asm/byteorder.h>
#define RTL8XXXU_DEBUG_REG_WRITE 0x01
#define RTL8XXXU_DEBUG_REG_READ 0x02
#define RTL8XXXU_DEBUG_RFREG_WRITE 0x04
#define RTL8XXXU_DEBUG_RFREG_READ 0x08
#define RTL8XXXU_DEBUG_CHANNEL 0x10
#define RTL8XXXU_DEBUG_TX 0x20
#define RTL8XXXU_DEBUG_TX_DUMP 0x40
#define RTL8XXXU_DEBUG_RX 0x80
#define RTL8XXXU_DEBUG_RX_DUMP 0x100
#define RTL8XXXU_DEBUG_USB 0x200
#define RTL8XXXU_DEBUG_KEY 0x400
#define RTL8XXXU_DEBUG_H2C 0x800
#define RTL8XXXU_DEBUG_ACTION 0x1000
#define RTL8XXXU_DEBUG_EFUSE 0x2000
#define RTL8XXXU_DEBUG_INTERRUPT 0x4000
#define RTW_USB_CONTROL_MSG_TIMEOUT 500
#define RTL8XXXU_MAX_REG_POLL 500
#define USB_INTR_CONTENT_LENGTH 56
#define RTL8XXXU_OUT_ENDPOINTS 6
#define REALTEK_USB_READ 0xc0
#define REALTEK_USB_WRITE 0x40
#define REALTEK_USB_CMD_REQ 0x05
#define REALTEK_USB_CMD_IDX 0x00
#define TX_TOTAL_PAGE_NUM 0xf8
#define TX_TOTAL_PAGE_NUM_8188F 0xf7
#define TX_TOTAL_PAGE_NUM_8188E 0xa9
#define TX_TOTAL_PAGE_NUM_8192E 0xf3
#define TX_TOTAL_PAGE_NUM_8723B 0xf7
/* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
#define TX_PAGE_NUM_PUBQ 0xe7
#define TX_PAGE_NUM_HI_PQ 0x0c
#define TX_PAGE_NUM_LO_PQ 0x02
#define TX_PAGE_NUM_NORM_PQ 0x02
#define TX_PAGE_NUM_PUBQ_8188F 0xe5
#define TX_PAGE_NUM_HI_PQ_8188F 0x0c
#define TX_PAGE_NUM_LO_PQ_8188F 0x02
#define TX_PAGE_NUM_NORM_PQ_8188F 0x02
#define TX_PAGE_NUM_PUBQ_8188E 0x47
#define TX_PAGE_NUM_HI_PQ_8188E 0x29
#define TX_PAGE_NUM_LO_PQ_8188E 0x1c
#define TX_PAGE_NUM_NORM_PQ_8188E 0x1c
#define TX_PAGE_NUM_PUBQ_8192E 0xe7
#define TX_PAGE_NUM_HI_PQ_8192E 0x08
#define TX_PAGE_NUM_LO_PQ_8192E 0x0c
#define TX_PAGE_NUM_NORM_PQ_8192E 0x00
#define TX_PAGE_NUM_PUBQ_8723B 0xe7
#define TX_PAGE_NUM_HI_PQ_8723B 0x0c
#define TX_PAGE_NUM_LO_PQ_8723B 0x02
#define TX_PAGE_NUM_NORM_PQ_8723B 0x02
#define RTL_FW_PAGE_SIZE 4096
#define RTL8XXXU_FIRMWARE_POLL_MAX 1000
#define RTL8723A_CHANNEL_GROUPS 3
#define RTL8723A_MAX_RF_PATHS 2
#define RTL8723B_CHANNEL_GROUPS 6
#define RTL8723B_TX_COUNT 4
#define RTL8723B_MAX_RF_PATHS 4
#define RTL8XXXU_MAX_CHANNEL_GROUPS 6
#define RF6052_MAX_TX_PWR 0x3f
#define EFUSE_MAP_LEN 512
#define EFUSE_MAX_SECTION_8723A 64
#define EFUSE_REAL_CONTENT_LEN_8723A 512
#define EFUSE_BT_MAP_LEN_8723A 1024
#define EFUSE_MAX_WORD_UNIT 4
enum rtl8xxxu_rtl_chip {
RTL8192S = 0x81920,
RTL8191S = 0x81910,
RTL8192C = 0x8192c,
RTL8191C = 0x8191c,
RTL8188C = 0x8188c,
RTL8188R = 0x81889,
RTL8192D = 0x8192d,
RTL8723A = 0x8723a,
RTL8188E = 0x8188e,
RTL8812 = 0x88120,
RTL8821 = 0x88210,
RTL8192E = 0x8192e,
RTL8191E = 0x8191e,
RTL8723B = 0x8723b,
RTL8814A = 0x8814a,
RTL8881A = 0x8881a,
RTL8821B = 0x8821b,
RTL8822B = 0x8822b,
RTL8703B = 0x8703b,
RTL8195A = 0x8195a,
RTL8188F = 0x8188f,
RTL8710B = 0x8710b,
};
enum rtl8xxxu_rx_type {
RX_TYPE_DATA_PKT = 0,
RX_TYPE_C2H = 1,
RX_TYPE_ERROR = -1
};
struct rtl8xxxu_rxdesc16 {
#ifdef __LITTLE_ENDIAN
u32 pktlen:14;
u32 crc32:1;
u32 icverr:1;
u32 drvinfo_sz:4;
u32 security:3;
u32 qos:1;
u32 shift:2;
u32 phy_stats:1;
u32 swdec:1;
u32 ls:1;
u32 fs:1;
u32 eor:1;
u32 own:1;
u32 macid:5;
u32 tid:4;
u32 hwrsvd:4;
u32 amsdu:1;
u32 paggr:1;
u32 faggr:1;
u32 a1fit:4;
u32 a2fit:4;
u32 pam:1;
u32 pwr:1;
u32 md:1;
u32 mf:1;
u32 type:2;
u32 mc:1;
u32 bc:1;
u32 seq:12;
u32 frag:4;
u32 pkt_cnt:8;
u32 reserved:6;
u32 nextind:1;
u32 reserved0:1;
u32 rxmcs:6;
u32 rxht:1;
u32 gf:1;
u32 splcp:1;
u32 bw:1;
u32 htc:1;
u32 eosp:1;
u32 bssidfit:2;
u32 rpt_sel:2; /* 8188e */
u32 reserved1:14;
u32 unicastwake:1;
u32 magicwake:1;
u32 pattern0match:1;
u32 pattern1match:1;
u32 pattern2match:1;
u32 pattern3match:1;
u32 pattern4match:1;
u32 pattern5match:1;
u32 pattern6match:1;
u32 pattern7match:1;
u32 pattern8match:1;
u32 pattern9match:1;
u32 patternamatch:1;
u32 patternbmatch:1;
u32 patterncmatch:1;
u32 reserved2:19;
#else
u32 own:1;
u32 eor:1;
u32 fs:1;
u32 ls:1;
u32 swdec:1;
u32 phy_stats:1;
u32 shift:2;
u32 qos:1;
u32 security:3;
u32 drvinfo_sz:4;
u32 icverr:1;
u32 crc32:1;
u32 pktlen:14;
u32 bc:1;
u32 mc:1;
u32 type:2;
u32 mf:1;
u32 md:1;
u32 pwr:1;
u32 pam:1;
u32 a2fit:4;
u32 a1fit:4;
u32 faggr:1;
u32 paggr:1;
u32 amsdu:1;
u32 hwrsvd:4;
u32 tid:4;
u32 macid:5;
u32 reserved0:1;
u32 nextind:1;
u32 reserved:6;
u32 pkt_cnt:8;
u32 frag:4;
u32 seq:12;
u32 magicwake:1;
u32 unicastwake:1;
u32 reserved1:14;
u32 rpt_sel:2; /* 8188e */
u32 bssidfit:2;
u32 eosp:1;
u32 htc:1;
u32 bw:1;
u32 splcp:1;
u32 gf:1;
u32 rxht:1;
u32 rxmcs:6;
u32 reserved2:19;
u32 patterncmatch:1;
u32 patternbmatch:1;
u32 patternamatch:1;
u32 pattern9match:1;
u32 pattern8match:1;
u32 pattern7match:1;
u32 pattern6match:1;
u32 pattern5match:1;
u32 pattern4match:1;
u32 pattern3match:1;
u32 pattern2match:1;
u32 pattern1match:1;
u32 pattern0match:1;
#endif
u32 tsfl;
#if 0
u32 bassn:12;
u32 bavld:1;
u32 reserved3:19;
#endif
};
struct rtl8xxxu_rxdesc24 {
#ifdef __LITTLE_ENDIAN
u32 pktlen:14;
u32 crc32:1;
u32 icverr:1;
u32 drvinfo_sz:4;
u32 security:3;
u32 qos:1;
u32 shift:2;
u32 phy_stats:1;
u32 swdec:1;
u32 ls:1;
u32 fs:1;
u32 eor:1;
u32 own:1;
u32 macid:7;
u32 dummy1_0:1;
u32 tid:4;
u32 dummy1_1:1;
u32 amsdu:1;
u32 rxid_match:1;
u32 paggr:1;
u32 a1fit:4; /* 16 */
u32 chkerr:1;
u32 ipver:1;
u32 tcpudp:1;
u32 chkvld:1;
u32 pam:1;
u32 pwr:1;
u32 more_data:1;
u32 more_frag:1;
u32 type:2;
u32 mc:1;
u32 bc:1;
u32 seq:12;
u32 frag:4;
u32 rx_is_qos:1; /* 16 */
u32 dummy2_0:1;
u32 wlanhd_iv_len:6;
u32 dummy2_1:4;
u32 rpt_sel:1;
u32 dummy2_2:3;
u32 rxmcs:7;
u32 dummy3_0:3;
u32 htc:1;
u32 eosp:1;
u32 bssidfit:2;
u32 dummy3_1:2;
u32 usb_agg_pktnum:8; /* 16 */
u32 dummy3_2:5;
u32 pattern_match:1;
u32 unicast_match:1;
u32 magic_match:1;
u32 splcp:1;
u32 ldcp:1;
u32 stbc:1;
u32 dummy4_0:1;
u32 bw:2;
u32 dummy4_1:26;
#else
u32 own:1;
u32 eor:1;
u32 fs:1;
u32 ls:1;
u32 swdec:1;
u32 phy_stats:1;
u32 shift:2;
u32 qos:1;
u32 security:3;
u32 drvinfo_sz:4;
u32 icverr:1;
u32 crc32:1;
u32 pktlen:14;
u32 bc:1;
u32 mc:1;
u32 type:2;
u32 mf:1;
u32 md:1;
u32 pwr:1;
u32 pam:1;
u32 a2fit:4;
u32 a1fit:4;
u32 faggr:1;
u32 paggr:1;
u32 amsdu:1;
u32 hwrsvd:4;
u32 tid:4;
u32 macid:5;
u32 dummy2_2:3;
u32 rpt_sel:1;
u32 dummy2_1:4;
u32 wlanhd_iv_len:6;
u32 dummy2_0:1;
u32 rx_is_qos:1;
u32 frag:4; /* 16 */
u32 seq:12;
u32 magic_match:1;
u32 unicast_match:1;
u32 pattern_match:1;
u32 dummy3_2:5;
u32 usb_agg_pktnum:8;
u32 dummy3_1:2; /* 16 */
u32 bssidfit:2;
u32 eosp:1;
u32 htc:1;
u32 dummy3_0:3;
u32 rxmcs:7;
u32 dumm4_1:26;
u32 bw:2;
u32 dummy4_0:1;
u32 stbc:1;
u32 ldcp:1;
u32 splcp:1;
#endif
u32 tsfl;
};
struct rtl8xxxu_txdesc32 {
__le16 pkt_size;
u8 pkt_offset;
u8 txdw0;
__le32 txdw1;
__le32 txdw2;
__le32 txdw3;
__le32 txdw4;
__le32 txdw5;
__le32 txdw6;
__le16 csum;
__le16 txdw7;
};
struct rtl8xxxu_txdesc40 {
__le16 pkt_size;
u8 pkt_offset;
u8 txdw0;
__le32 txdw1;
__le32 txdw2;
__le32 txdw3;
__le32 txdw4;
__le32 txdw5;
__le32 txdw6;
__le16 csum;
__le16 txdw7;
__le32 txdw8;
__le32 txdw9;
};
/* CCK Rates, TxHT = 0 */
#define DESC_RATE_1M 0x00
#define DESC_RATE_2M 0x01
#define DESC_RATE_5_5M 0x02
#define DESC_RATE_11M 0x03
/* OFDM Rates, TxHT = 0 */
#define DESC_RATE_6M 0x04
#define DESC_RATE_9M 0x05
#define DESC_RATE_12M 0x06
#define DESC_RATE_18M 0x07
#define DESC_RATE_24M 0x08
#define DESC_RATE_36M 0x09
#define DESC_RATE_48M 0x0a
#define DESC_RATE_54M 0x0b
/* MCS Rates, TxHT = 1 */
#define DESC_RATE_MCS0 0x0c
#define DESC_RATE_MCS1 0x0d
#define DESC_RATE_MCS2 0x0e
#define DESC_RATE_MCS3 0x0f
#define DESC_RATE_MCS4 0x10
#define DESC_RATE_MCS5 0x11
#define DESC_RATE_MCS6 0x12
#define DESC_RATE_MCS7 0x13
#define DESC_RATE_MCS8 0x14
#define DESC_RATE_MCS9 0x15
#define DESC_RATE_MCS10 0x16
#define DESC_RATE_MCS11 0x17
#define DESC_RATE_MCS12 0x18
#define DESC_RATE_MCS13 0x19
#define DESC_RATE_MCS14 0x1a
#define DESC_RATE_MCS15 0x1b
#define DESC_RATE_MCS15_SG 0x1c
#define DESC_RATE_MCS32 0x20
#define TXDESC_OFFSET_SZ 0
#define TXDESC_OFFSET_SHT 16
#if 0
#define TXDESC_BMC BIT(24)
#define TXDESC_LSG BIT(26)
#define TXDESC_FSG BIT(27)
#define TXDESC_OWN BIT(31)
#else
#define TXDESC_BROADMULTICAST BIT(0)
#define TXDESC_HTC BIT(1)
#define TXDESC_LAST_SEGMENT BIT(2)
#define TXDESC_FIRST_SEGMENT BIT(3)
#define TXDESC_LINIP BIT(4)
#define TXDESC_NO_ACM BIT(5)
#define TXDESC_GF BIT(6)
#define TXDESC_OWN BIT(7)
#endif
/* Word 1 */
/*
* Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are
* aggregation enable and break respectively. For 8723bu, bits 0-7 are macid.
*/
#define TXDESC_PKT_OFFSET_SZ 0
#define TXDESC32_AGG_ENABLE BIT(5)
#define TXDESC32_AGG_BREAK BIT(6)
#define TXDESC40_MACID_SHIFT 0
#define TXDESC40_MACID_MASK 0x00f0
#define TXDESC_QUEUE_SHIFT 8
#define TXDESC_QUEUE_MASK 0x1f00
#define TXDESC_QUEUE_BK 0x2
#define TXDESC_QUEUE_BE 0x0
#define TXDESC_QUEUE_VI 0x5
#define TXDESC_QUEUE_VO 0x7
#define TXDESC_QUEUE_BEACON 0x10
#define TXDESC_QUEUE_HIGH 0x11
#define TXDESC_QUEUE_MGNT 0x12
#define TXDESC_QUEUE_CMD 0x13
#define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1)
#define TXDESC40_RDG_NAV_EXT BIT(13)
#define TXDESC40_LSIG_TXOP_ENABLE BIT(14)
#define TXDESC40_PIFS BIT(15)
#define DESC_RATE_ID_SHIFT 16
#define DESC_RATE_ID_MASK 0xf
#define TXDESC_NAVUSEHDR BIT(20)
#define TXDESC_SEC_RC4 0x00400000
#define TXDESC_SEC_AES 0x00c00000
#define TXDESC_PKT_OFFSET_SHIFT 26
#define TXDESC_AGG_EN BIT(29)
#define TXDESC_HWPC BIT(31)
/* Word 2 */
#define TXDESC40_PAID_SHIFT 0
#define TXDESC40_PAID_MASK 0x1ff
#define TXDESC40_CCA_RTS_SHIFT 10
#define TXDESC40_CCA_RTS_MASK 0xc00
#define TXDESC40_AGG_ENABLE BIT(12)
#define TXDESC40_RDG_ENABLE BIT(13)
#define TXDESC40_AGG_BREAK BIT(16)
#define TXDESC40_MORE_FRAG BIT(17)
#define TXDESC40_RAW BIT(18)
#define TXDESC32_ACK_REPORT BIT(19)
#define TXDESC40_SPE_RPT BIT(19)
#define TXDESC_AMPDU_DENSITY_SHIFT 20
#define TXDESC40_BT_INT BIT(23)
#define TXDESC40_GID_SHIFT 24
#define TXDESC_ANTENNA_SELECT_A BIT(24)
#define TXDESC_ANTENNA_SELECT_B BIT(25)
/* Word 3 */
#define TXDESC40_USE_DRIVER_RATE BIT(8)
#define TXDESC40_CTS_SELF_ENABLE BIT(11)
#define TXDESC40_RTS_CTS_ENABLE BIT(12)
#define TXDESC40_HW_RTS_ENABLE BIT(13)
#define TXDESC32_SEQ_SHIFT 16
#define TXDESC32_SEQ_MASK 0x0fff0000
/* Word 4 */
#define TXDESC32_RTS_RATE_SHIFT 0
#define TXDESC32_RTS_RATE_MASK 0x3f
#define TXDESC32_QOS BIT(6)
#define TXDESC32_HW_SEQ_ENABLE BIT(7)
#define TXDESC32_USE_DRIVER_RATE BIT(8)
#define TXDESC_DISABLE_DATA_FB BIT(10)
#define TXDESC32_CTS_SELF_ENABLE BIT(11)
#define TXDESC32_RTS_CTS_ENABLE BIT(12)
#define TXDESC32_HW_RTS_ENABLE BIT(13)
#define TXDESC32_PT_STAGE_MASK GENMASK(17, 15)
#define TXDESC_PRIME_CH_OFF_LOWER BIT(20)
#define TXDESC_PRIME_CH_OFF_UPPER BIT(21)
#define TXDESC32_SHORT_PREAMBLE BIT(24)
#define TXDESC_DATA_BW BIT(25)
#define TXDESC_RTS_DATA_BW BIT(27)
#define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28)
#define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29)
#define TXDESC40_DATA_RATE_FB_SHIFT 8
#define TXDESC40_DATA_RATE_FB_MASK 0x00001f00
#define TXDESC40_RETRY_LIMIT_ENABLE BIT(17)
#define TXDESC40_RETRY_LIMIT_SHIFT 18
#define TXDESC40_RETRY_LIMIT_MASK 0x00fc0000
#define TXDESC40_RTS_RATE_SHIFT 24
#define TXDESC40_RTS_RATE_MASK 0x3f000000
/* Word 5 */
#define TXDESC40_SHORT_PREAMBLE BIT(4)
#define TXDESC32_SHORT_GI BIT(6)
#define TXDESC_CCX_TAG BIT(7)
#define TXDESC32_RETRY_LIMIT_ENABLE BIT(17)
#define TXDESC32_RETRY_LIMIT_SHIFT 18
#define TXDESC32_RETRY_LIMIT_MASK 0x00fc0000
/* Word 6 */
#define TXDESC_MAX_AGG_SHIFT 11
#define TXDESC_USB_TX_AGG_SHIT 24
/* Word 7 */
#define TXDESC_ANTENNA_SELECT_C BIT(29)
/* Word 8 */
#define TXDESC40_HW_SEQ_ENABLE BIT(15)
/* Word 9 */
#define TXDESC40_SEQ_SHIFT 12
#define TXDESC40_SEQ_MASK 0x00fff000
struct phy_rx_agc_info {
#ifdef __LITTLE_ENDIAN
u8 gain:7, trsw:1;
#else
u8 trsw:1, gain:7;
#endif
};
#define CCK_AGC_RPT_LNA_IDX_MASK GENMASK(7, 5)
#define CCK_AGC_RPT_VGA_IDX_MASK GENMASK(4, 0)
struct rtl8723au_phy_stats {
struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS];
u8 ch_corr[RTL8723A_MAX_RF_PATHS];
u8 cck_sig_qual_ofdm_pwdb_all;
u8 cck_agc_rpt_ofdm_cfosho_a;
u8 cck_rpt_b_ofdm_cfosho_b;
u8 reserved_1;
u8 noise_power_db_msb;
s8 path_cfotail[RTL8723A_MAX_RF_PATHS];
u8 pcts_mask[RTL8723A_MAX_RF_PATHS];
s8 stream_rxevm[RTL8723A_MAX_RF_PATHS];
u8 path_rxsnr[RTL8723A_MAX_RF_PATHS];
u8 noise_power_db_lsb;
u8 reserved_2[3];
u8 stream_csi[RTL8723A_MAX_RF_PATHS];
u8 stream_target_csi[RTL8723A_MAX_RF_PATHS];
s8 sig_evm;
u8 reserved_3;
#ifdef __LITTLE_ENDIAN
u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
u8 sgi_en:1;
u8 rxsc:2;
u8 idle_long:1;
u8 r_ant_train_en:1;
u8 antenna_select_b:1;
u8 antenna_select:1;
#else /* _BIG_ENDIAN_ */
u8 antenna_select:1;
u8 antenna_select_b:1;
u8 r_ant_train_en:1;
u8 idle_long:1;
u8 rxsc:2;
u8 sgi_en:1;
u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
#endif
};
struct jaguar2_phy_stats_type0 {
/* DW0 */
u8 page_num;
u8 pwdb;
#ifdef __LITTLE_ENDIAN
u8 gain: 6;
u8 rsvd_0: 1;
u8 trsw: 1;
#else
u8 trsw: 1;
u8 rsvd_0: 1;
u8 gain: 6;
#endif
u8 rsvd_1;
/* DW1 */
u8 rsvd_2;
#ifdef __LITTLE_ENDIAN
u8 rxsc: 4;
u8 agc_table: 4;
#else
u8 agc_table: 4;
u8 rxsc: 4;
#endif
u8 channel;
u8 band;
/* DW2 */
u16 length;
#ifdef __LITTLE_ENDIAN
u8 antidx_a: 3;
u8 antidx_b: 3;
u8 rsvd_3: 2;
u8 antidx_c: 3;
u8 antidx_d: 3;
u8 rsvd_4:2;
#else
u8 rsvd_3: 2;
u8 antidx_b: 3;
u8 antidx_a: 3;
u8 rsvd_4:2;
u8 antidx_d: 3;
u8 antidx_c: 3;
#endif
/* DW3 */
u8 signal_quality;
#ifdef __LITTLE_ENDIAN
u8 vga:5;
u8 lna_l:3;
u8 bb_power:6;
u8 rsvd_9:1;
u8 lna_h:1;
#else
u8 lna_l:3;
u8 vga:5;
u8 lna_h:1;
u8 rsvd_9:1;
u8 bb_power:6;
#endif
u8 rsvd_5;
/* DW4 */
u32 rsvd_6;
/* DW5 */
u32 rsvd_7;
/* DW6 */
u32 rsvd_8;
} __packed;
struct jaguar2_phy_stats_type1 {
/* DW0 and DW1 */
u8 page_num;
u8 pwdb[4];
#ifdef __LITTLE_ENDIAN
u8 l_rxsc: 4;
u8 ht_rxsc: 4;
#else
u8 ht_rxsc: 4;
u8 l_rxsc: 4;
#endif
u8 channel;
#ifdef __LITTLE_ENDIAN
u8 band: 2;
u8 rsvd_0: 1;
u8 hw_antsw_occu: 1;
u8 gnt_bt: 1;
u8 ldpc: 1;
u8 stbc: 1;
u8 beamformed: 1;
#else
u8 beamformed: 1;
u8 stbc: 1;
u8 ldpc: 1;
u8 gnt_bt: 1;
u8 hw_antsw_occu: 1;
u8 rsvd_0: 1;
u8 band: 2;
#endif
/* DW2 */
u16 lsig_length;
#ifdef __LITTLE_ENDIAN
u8 antidx_a: 3;
u8 antidx_b: 3;
u8 rsvd_1: 2;
u8 antidx_c: 3;
u8 antidx_d: 3;
u8 rsvd_2: 2;
#else
u8 rsvd_1: 2;
u8 antidx_b: 3;
u8 antidx_a: 3;
u8 rsvd_2: 2;
u8 antidx_d: 3;
u8 antidx_c: 3;
#endif
/* DW3 */
u8 paid;
#ifdef __LITTLE_ENDIAN
u8 paid_msb: 1;
u8 gid: 6;
u8 rsvd_3: 1;
#else
u8 rsvd_3: 1;
u8 gid: 6;
u8 paid_msb: 1;
#endif
u8 intf_pos;
#ifdef __LITTLE_ENDIAN
u8 intf_pos_msb: 1;
u8 rsvd_4: 2;
u8 nb_intf_flag: 1;
u8 rf_mode: 2;
u8 rsvd_5: 2;
#else
u8 rsvd_5: 2;
u8 rf_mode: 2;
u8 nb_intf_flag: 1;
u8 rsvd_4: 2;
u8 intf_pos_msb: 1;
#endif
/* DW4 */
s8 rxevm[4]; /* s(8,1) */
/* DW5 */
s8 cfo_tail[4]; /* s(8,7) */
/* DW6 */
s8 rxsnr[4]; /* s(8,1) */
} __packed;
struct jaguar2_phy_stats_type2 {
/* DW0 ane DW1 */
u8 page_num;
u8 pwdb[4];
#ifdef __LITTLE_ENDIAN
u8 l_rxsc: 4;
u8 ht_rxsc: 4;
#else
u8 ht_rxsc: 4;
u8 l_rxsc: 4;
#endif
u8 channel;
#ifdef __LITTLE_ENDIAN
u8 band: 2;
u8 rsvd_0: 1;
u8 hw_antsw_occu: 1;
u8 gnt_bt: 1;
u8 ldpc: 1;
u8 stbc: 1;
u8 beamformed: 1;
#else
u8 beamformed: 1;
u8 stbc: 1;
u8 ldpc: 1;
u8 gnt_bt: 1;
u8 hw_antsw_occu: 1;
u8 rsvd_0: 1;
u8 band: 2;
#endif
/* DW2 */
#ifdef __LITTLE_ENDIAN
u8 shift_l_map: 6;
u8 rsvd_1: 2;
#else
u8 rsvd_1: 2;
u8 shift_l_map: 6;
#endif
u8 cnt_pw2cca;
#ifdef __LITTLE_ENDIAN
u8 agc_table_a: 4;
u8 agc_table_b: 4;
u8 agc_table_c: 4;
u8 agc_table_d: 4;
#else
u8 agc_table_b: 4;
u8 agc_table_a: 4;
u8 agc_table_d: 4;
u8 agc_table_c: 4;
#endif
/* DW3 ~ DW6*/
u8 cnt_cca2agc_rdy;
#ifdef __LITTLE_ENDIAN
u8 gain_a: 6;
u8 rsvd_2: 1;
u8 trsw_a: 1;
u8 gain_b: 6;
u8 rsvd_3: 1;
u8 trsw_b: 1;
u8 gain_c: 6;
u8 rsvd_4: 1;
u8 trsw_c: 1;
u8 gain_d: 6;
u8 rsvd_5: 1;
u8 trsw_d: 1;
u8 aagc_step_a: 2;
u8 aagc_step_b: 2;
u8 aagc_step_c: 2;
u8 aagc_step_d: 2;
#else
u8 trsw_a: 1;
u8 rsvd_2: 1;
u8 gain_a: 6;
u8 trsw_b: 1;
u8 rsvd_3: 1;
u8 gain_b: 6;
u8 trsw_c: 1;
u8 rsvd_4: 1;
u8 gain_c: 6;
u8 trsw_d: 1;
u8 rsvd_5: 1;
u8 gain_d: 6;
u8 aagc_step_d: 2;
u8 aagc_step_c: 2;
u8 aagc_step_b: 2;
u8 aagc_step_a: 2;
#endif
u8 ht_aagc_gain[4];
u8 dagc_gain[4];
#ifdef __LITTLE_ENDIAN
u8 counter: 6;
u8 rsvd_6: 2;
u8 syn_count: 5;
u8 rsvd_7:3;
#else
u8 rsvd_6: 2;
u8 counter: 6;
u8 rsvd_7:3;
u8 syn_count: 5;
#endif
} __packed;
/*
* Regs to backup
*/
#define RTL8XXXU_ADDA_REGS 16
#define RTL8XXXU_MAC_REGS 4
#define RTL8XXXU_BB_REGS 9
struct rtl8xxxu_firmware_header {
__le16 signature; /* 92C0: test chip; 92C,
88C0: test chip;
88C1: MP A-cut;
92C1: MP A-cut */
u8 category; /* AP/NIC and USB/PCI */
u8 function;
__le16 major_version; /* FW Version */
u8 minor_version; /* FW Subversion, default 0x00 */
u8 reserved1;
u8 month; /* Release time Month field */
u8 date; /* Release time Date field */
u8 hour; /* Release time Hour field */
u8 minute; /* Release time Minute field */
__le16 ramcodesize; /* Size of RAM code */
u16 reserved2;
__le32 svn_idx; /* SVN entry index */
u32 reserved3;
u32 reserved4;
u32 reserved5;
u8 data[];
};
/*
* 8723au/8192cu/8188ru required base power index offset tables.
*/
struct rtl8xxxu_power_base {
u32 reg_0e00;
u32 reg_0e04;
u32 reg_0e08;
u32 reg_086c;
u32 reg_0e10;
u32 reg_0e14;
u32 reg_0e18;
u32 reg_0e1c;
u32 reg_0830;
u32 reg_0834;
u32 reg_0838;
u32 reg_086c_2;
u32 reg_083c;
u32 reg_0848;
u32 reg_084c;
u32 reg_0868;
};
/*
* The 8723au has 3 channel groups: 1-3, 4-9, and 10-14
*/
struct rtl8723au_idx {
#ifdef __LITTLE_ENDIAN
int a:4;
int b:4;
#else
int b:4;
int a:4;
#endif
} __attribute__((packed));
struct rtl8723au_efuse {
__le16 rtl_id;
u8 res0[0xe];
u8 cck_tx_power_index_A[3]; /* 0x10 */
u8 cck_tx_power_index_B[3];
u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */
u8 ht40_1s_tx_power_index_B[3];
/*
* The following entries are half-bytes split as:
* bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
*/
struct rtl8723au_idx ht20_tx_power_index_diff[3];
struct rtl8723au_idx ofdm_tx_power_index_diff[3];
struct rtl8723au_idx ht40_max_power_offset[3];
struct rtl8723au_idx ht20_max_power_offset[3];
u8 channel_plan; /* 0x28 */
u8 tssi_a;
u8 thermal_meter;
u8 rf_regulatory;
u8 rf_option_2;
u8 rf_option_3;
u8 rf_option_4;
u8 res7;
u8 version /* 0x30 */;
u8 customer_id_major;
u8 customer_id_minor;
u8 xtal_k;
u8 chipset; /* 0x34 */
u8 res8[0x82];
u8 vid; /* 0xb7 */
u8 res9;
u8 pid; /* 0xb9 */
u8 res10[0x0c];
u8 mac_addr[ETH_ALEN]; /* 0xc6 */
u8 res11[2];
u8 vendor_name[7];
u8 res12[2];
u8 device_name[0x29]; /* 0xd7 */
};
struct rtl8192cu_efuse {
__le16 rtl_id;
__le16 hpon;
u8 res0[2];
__le16 clk;
__le16 testr;