Incorrect verilog when generated through ChiGen

[markram1729]

My input verilog file

module intop (
    input  a,  
    b,  
    output c,
    d   
);

  wire ina, inb;


  assign ina = a + b;
  assign inb = a ^ b;

  xora inex (
      a,  
      inb,
      c   
  );  

  minxora inex2 (
      b,  
      ina,
      d   
  );  

endmodule



module xora (
    input  a,  
    inb,
    output c
);

  assign c = a ^ inb;

endmodule


module minxora (
    input  b,  
    ina,
    output d
);

  assign d = ~(b ^ ina);

endmodule

generated json file

exa_jan.json

generated verilog file using
Chimera exa_jan.json 1 > exprog.v

Generated verilog file fails lint check

module module_0 (  input  supply1  id_0  ,  input  wand  id_1  ,  id_2  ,  output  tri  id_2  ,  output  wand  id_3  ,  id_3  ,  input  wire  id_4  )  ;  assign  id_2  =  id_2  ;  endmodule 
 module module_1 (  output  tri  id_0  ,  id_2  ,  output  wor  id_1  ,  id_3  ,  id_4  )  ;  id_5  (  id_4  ^  id_2  ,  id_2  +  id_2  )  ;  assign  =  ~  id_3  ; module_0 modCall_1 ( id_2 , id_4 , id_2 , id_3 , id_2 );assign modCall_1. id_2  = 0; endmodule 
 module module_2 (  input  wand  id_0  ,  id_2  ,  id_3  ,  output  tri  id_1  ,  id_4  )  ;  assign  =  ~  id_3  ; module_0 modCall_1 ( id_3 , id_3 , id_4 , id_3 , id_3 );assign modCall_1. id_1  = 0; assign  id_3  =  (  id_4  )  ;  endmodule

verilator link output

%Error: exprog.v:2:151: syntax error, unexpected '='
    2 |  module module_1 (  output  tri  id_0  ,  id_2  ,  output  wor  id_1  ,  id_3  ,  id_4  )  ;  id_5  (  id_4  ^  id_2  ,  id_2  +  id_2  )  ;  assign  =  ~  id_3  ; module_0 modCall_1 ( id_2 , id_4 , id_2 , id_3 , id_2 );assign modCall_1. id_2  = 0; endmodule 
      |                                                                                                                                                       ^
%Error: exprog.v:3:103: syntax error, unexpected '='
    3 |  module module_2 (  input  wand  id_0  ,  id_2  ,  id_3  ,  output  tri  id_1  ,  id_4  )  ;  assign  =  ~  id_3  ; module_0 modCall_1 ( id_3 , id_3 , id_4 , id_3 , id_3 );assign modCall_1. id_1  = 0; assign  id_3  =  (  id_4  )  ;  endmodule 
      |                                                                                                       ^
%Error: Exiting due to 2 error(s)
libgcov profiling error:/home/regaltos/Vicharak/dev/ViNuwa/verilator/src/obj_opt/V3EmitCModel.gcda:Version mismatch - expected 13.2 (release) (B32*) got 11.4 (release) (B14*)
libgcov profiling error:/home/regaltos/Vicharak/dev/ViNuwa/verilator/src/obj_opt/V3File.gcda:Version mismatch - expected 13.2 (release) (B32*) got 11.4 (release) (B14*)
libgcov profiling error:/home/regaltos/Vicharak/dev/ViNuwa/verilator/src/obj_opt/V3EmitCImp.gcda:Version mismatch - expected 13.2 (release) (B32*) got 11.4 (release) (B14*)
libgcov profiling error:/home/regaltos/Vicharak/dev/ViNuwa/verilator/src/obj_opt/V3EmitCFunc.gcda:Version mismatch - expected 13.2 (release) (B32*) got 11.4 (release) (B14*)

is this expected behaviour?

[pronesto]

Hi @markram1729 yes, this behavior is expected. The pre-trained version of ChiGen generates about 40% of invalid Verilog programs. That's by design: often these invalid programs force crashes into EDA tools. Currently, we cannot control the proportion of valid/invalid designs, except by training ChiGen with a different set of benchmarks.

[markram1729]

oh sure , Thank you!