Feature request: simple example of blinking LED

[pdp7]

The Doppler readme links to a nice introduction to Verilog video which has a simple example of creating a counter and using the high bits to blink a LED a couple Hz.

Here is the Verilog:
https://opentechlab.org.uk/videos:013:notes#example_1blinking_leds

module top(input clk_100mhz, output [3:1] led);

reg [25:0] counter = 0;
assign led = counter[25:23];
always @(posedge clk_100mhz) counter <= counter + 1;

endmodule

I think it would be nice to have such an example for the Doppler. The LED matrix is awesome but it might make it easier for a Verilog beginner to understand how to blink a single LED.

[noscene]

• take a look into schematics...the onboard leds are in matrix so you musst assign both pins
• in the example it use an external 100mhz osc, but for the ice40up5k you can use the internal

[pdp7]

@noscene thanks for the reeply.

I am looking at the PDF dadamachines-doppler-schematic.pdf but I don't see how the pins shown in the schematic relate to doppler_io_out_test/doppler_io_out_test.pcf:

# 4x4 led matrix 
set_io aled[0] 26
set_io aled[1] 27
set_io aled[2] 28
set_io aled[3] 31
set_io kled[0] 42
set_io kled[1] 43
set_io kled[2] 44
set_io kled[3] 45

[noscene]

The pin number in pcf file is the physical pin on QFN48 (sg48) of the ice40up5k fpga.

[grav]

@noscene I also tried getting the OpenTechLab example working, but failed. I end up with an "empty design".

pcf:

set_io clk 12 # also tried 37 with same result
# 4x4 led matrix 
set_io aled[0] 26
set_io aled[1] 27
set_io aled[2] 28
set_io aled[3] 31
set_io kled[0] 42
set_io kled[1] 43
set_io kled[2] 44
set_io kled[3] 45

.v:

module top(input clk, output [1:3] aled, output [1:3] kled);

reg [26:0] counter;
assign aled = counter[23:25]; # total guess work to assign to both aled and kled
assign kled = counter[23:25];

always @(posedge clk) counter <= counter + 0;

endmodule

output from make:

icetime -d up5k -mtr top.rpt top.asc
// Reading input .asc file..
// Reading 5k chipdb file..
// Creating timing netlist..
// Timing estimate: 0.00 ns (inf MHz)
This design is empty. It contains no paths!
make: *** [Makefile:23: top.rpt] Error 1

I may be reading the schematics wrong?

[noscene]

this looks like some with filename or makefile is wrong

[grav]

I've started from scratch

1. copying the code from open tec lab: https://opentechlab.org.uk/videos:013:notes#example_code
2. adapting .pcf file to match doppler
3. change make file so it can create a .h file for upload via arduino
4. added .ino script for upload

What I have is something that

• compiles
• does not complain about "empty design" (via make demo.rpt)
• uploads to device
• doesn't light up leds :-/

Here's the full repro: https://github.com/grav/doppler-blink

Can you spot what I'm doing wrong @noscene ? Thanks a bunch for your help :-)

Edit: also did a version that uses aled and kled as per your example: https://github.com/grav/doppler-blink/tree/aledkled