[BUG] Incorrect handling of PMPADDR register reads in NA4 / NAPOT address matching modes

[zchamski]

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

The RTL code of CSR read process (https://github.com/openhwgroup/cva6/blob/master/core/csr_regfile.sv#L851C1-L857C71) incorrectly assumes that the last bit of pmpaddr registers should be read as 1 if the corresponding pmpNcfg.A[1] bit is set. Table 19 in the privileged ISA spec (v20240411) states that the value of bit 0 in a pmpaddrN register can be 0 in NA4 mode and must be 0 in NAPOT mode with 8 byte ranges:

@Moschn, can you please have a look at this?

[Moschn]

I think you are correct. I'm not sure where this bug crept in; at some point, this was working correctly (I checked the supported granularity in software a couple years ago). Feel free to propose a fix!