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    217 repositories

    • openlane-metrics

      Public
      Repository to store metric results for OpenLane 2.0.0+
      0•0•0•0•Updated Jan 27, 2025Jan 27, 2025

    • openlane2

      Public
      The next generation of OpenLane, rewritten from scratch with a modular architecture
      flowasicedaverilogvlsipnrsiliconlvsflowssta
      Python
      •
      Apache License 2.0
      •45•258•86•10•Updated Jan 27, 2025Jan 27, 2025

    • ipm

      Public
      Open-source IPs Package Manager (IPM)
      Python
      •
      Apache License 2.0
      •2•14•7•3•Updated Jan 27, 2025Jan 27, 2025

    • caravel-sim-infrastructure

      Public
      HTML
      •
      Apache License 2.0
      •4•1•1•0•Updated Jan 27, 2025Jan 27, 2025

    • EF_SRAM_1024x32

      Public
      Verilog
      •0•3•6•1•Updated Jan 27, 2025Jan 27, 2025

    • EF_QSPI_FLASH_WRITER

      Public
      Verilog
      •0•0•0•0•Updated Jan 26, 2025Jan 26, 2025

    • EF_TMR32

      Public
      Verilog
      •
      Apache License 2.0
      •1•0•2•0•Updated Jan 26, 2025Jan 26, 2025

    • sky130_klayout_pdk

      Public
      Skywaters 130nm Klayout PDK
      pdkskywaterschipdesign
      Python
      •
      Apache License 2.0
      •13•21•7•1•Updated Jan 25, 2025Jan 25, 2025

    • skywater-pdk-libs-sky130_fd_pr

      Public
      Python
      •
      Apache License 2.0
      •23•7•7•0•Updated Jan 23, 2025Jan 23, 2025

    • cace

      Public
      Circuit Automatic Characterization Engine
      Python
      •
      Apache License 2.0
      •6•47•25•2•Updated Jan 23, 2025Jan 23, 2025

    • EF_QSPI_XIP_CTRL

      Public
      A QSPI XiP Flash Controller with a Direct Mapped Cache
      Verilog
      •
      Apache License 2.0
      •0•1•3•0•Updated Jan 23, 2025Jan 23, 2025

    • EF_I2C

      Public
      Verilog
      •
      Apache License 2.0
      •0•0•6•0•Updated Jan 23, 2025Jan 23, 2025

    • EF_SHA256

      Public
      Verilog
      •0•0•2•0•Updated Jan 23, 2025Jan 23, 2025

    • EF_AES

      Public
      Verilog
      •0•0•1•0•Updated Jan 23, 2025Jan 23, 2025

    • EF_WDT32

      Public
      A simple WatchDog Timer (WDT)
      Verilog
      •
      Apache License 2.0
      •1•0•0•0•Updated Jan 23, 2025Jan 23, 2025

    • EF_SPI

      Public
      Verilog
      •0•0•5•0•Updated Jan 23, 2025Jan 23, 2025

    • EF_GPIO8

      Public
      A generic 8-bit General Purpose I/O (GPIO) Peripheral
      Verilog
      •
      Apache License 2.0
      •1•1•1•0•Updated Jan 23, 2025Jan 23, 2025

    • EF_I2S

      Public
      Two-wire I2S synchronous serial interface, compatible with I2S specification.
      Verilog
      •
      Apache License 2.0
      •0•0•6•2•Updated Jan 23, 2025Jan 23, 2025

    • EF_UART

      Public
      Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
      Verilog
      •
      Apache License 2.0
      •3•7•11•1•Updated Jan 23, 2025Jan 23, 2025

    • EF_PSRAM_CTRL

      Public
      Verilog
      •
      Apache License 2.0
      •0•1•3•1•Updated Jan 22, 2025Jan 22, 2025

    • openlane2-ci-designs

      Public
      Continuous Integration Designs for OpenLane 2.0.0 or higher
      Verilog
      •1•0•0•0•Updated Jan 22, 2025Jan 22, 2025

    • BusWrap

      Public
      Python
      •0•5•6•1•Updated Jan 22, 2025Jan 22, 2025

    • caravel_mgmt_soc_litex

      Public
      https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
      Verilog
      •
      Apache License 2.0
      •15•26•23•10•Updated Jan 21, 2025Jan 21, 2025

    • nix-eda

      Public
      Nix derivations for EDA tools
      nixedaelectronic-design-automationnix-flake
      Nix
      •
      Apache License 2.0
      •3•8•2•0•Updated Jan 16, 2025Jan 16, 2025

    • EF_USB_CDC_WRAPPER

      Public
      Verilog
      •0•0•0•0•Updated Jan 16, 2025Jan 16, 2025

    • IHP-Open-PDK

      Public
      130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
      HTML
      •
      Apache License 2.0
      •68•0•1•0•Updated Jan 15, 2025Jan 15, 2025

    • sky130_aa_ip__programmable_pll

      Public
      Chipaloza Challange A Low Phase Noise Programmable Differential Clock Generator
      Tcl
      •
      Apache License 2.0
      •2•0•0•0•Updated Jan 14, 2025Jan 14, 2025

    • openlane2-step-unit-tests

      Public
      Step-specific Unit Tests for OpenLane 2.0.0+
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated Jan 13, 2025Jan 13, 2025

    • EF_UVM

      Public
      Python
      •1•2•0•0•Updated Jan 13, 2025Jan 13, 2025

    • EF_IP_UTIL

      Public
      A set of utilities that can be used to develop digital IPs in Verilog HDL.
      Verilog
      •0•0•0•0•Updated Jan 13, 2025Jan 13, 2025