diff --git a/intel/common/vsrc/bootrom.v b/intel/common/vsrc/bootrom.v new file mode 100644 index 00000000..0e4ff645 --- /dev/null +++ b/intel/common/vsrc/bootrom.v @@ -0,0 +1,23 @@ +module BootROM( + input wire [10:0] address, + input wire clock, + input wire me, + input wire oe, + output wire [31:0] q +); + +wire [31:0] q_r; + +rom r( + .address(address), + .clock(clock), + .rden(me), + .q(q_r) +); + +assign q[31:24] = q_r[7:0]; +assign q[23:16] = q_r[15:8]; +assign q[15:8] = q_r[23:16]; +assign q[7:0] = q_r[31:24]; + +endmodule diff --git a/intel/common/vsrc/iobuf_full.v b/intel/common/vsrc/iobuf_full.v new file mode 100644 index 00000000..3469eac0 --- /dev/null +++ b/intel/common/vsrc/iobuf_full.v @@ -0,0 +1,46 @@ +// Joseph Tarango +module iobuf( + output wire [0:0] dataout, // dout.export + input wire [0:0] datain, // din.export + input wire [0:0] oe, // oe.export + inout wire [0:0] padio // pad_io.export +); + +assign dataout = datain; + +IOBUF iobufElement( + .dataout (dataout), // output, width = 1, dout.export + .datain (datain), // input, width = 1, din.export + .oe (oe), // input, width = 1, oe.export + .padio (padio) // inout, width = 1, pad_io.export +); + +endmodule + + +module ibuf( + input wire [0:0] datain, + output wire [0:0] dataout +); + +assign dataout = datain; + +IOBUF ibufElement( + .datain(datain), + .dataout(dataout) +); + +endmodule + +module obuf( + input wire [0:0] datain, + output wire [0:0] dataout +); + +assign dataout = datain; +IOBUF obufElement( + .datain(datain), + .dataout(dataout) +); + +endmodule diff --git a/intel/common/vsrc/iobuf_wire.v b/intel/common/vsrc/iobuf_wire.v new file mode 100644 index 00000000..b8c42344 --- /dev/null +++ b/intel/common/vsrc/iobuf_wire.v @@ -0,0 +1,46 @@ +// Joseph Tarango +module iobuf( + output wire [0:0] dataout, // dout.export + input wire [0:0] datain, // din.export + input wire [0:0] oe, // oe.export + inout wire [0:0] padio // pad_io.export +); + +assign dataout = datain; + +//IOBUF iobufElement( +// .dataout (dataout), // output, width = 1, dout.export +// .datain (datain), // input, width = 1, din.export +// .oe (oe), // input, width = 1, oe.export +// .padio (padio) // inout, width = 1, pad_io.export +//); + +endmodule + + +module ibuf( + input wire [0:0] datain, + output wire [0:0] dataout +); + +assign dataout = datain; + +//IOBUF ibufElement( +// .datain(datain), +// .dataout(dataout) +//); + +endmodule + +module obuf( + input wire [0:0] datain, + output wire [0:0] dataout +); + +assign dataout = datain; +//IOBUF obufElement( +// .datain(datain), +// .dataout(dataout) +//); + +endmodule diff --git a/intel/sgx-dev/basefiles/IOBUF.ip b/intel/sgx-dev/basefiles/IOBUF.ip new file mode 100644 index 00000000..62213bb5 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF.ip @@ -0,0 +1,582 @@ + + + Intel Corporation + IOBUF + gpio_0 + 19.3.0 + + + dout + + + + + + + + export + + + dataout + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + output + + + + + + + din + + + + + + + + export + + + datain + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + oe + + + + + + + + export + + + oe + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + input + + + + + + + pad_io + + + + + + + + export + + + padio + + + + + + + + + associatedClock + associatedClock + + + + associatedReset + associatedReset + + + + prSafe + Partial Reconfiguration Safe + false + + + + + + + ui.blockdiagram.direction + bidir + + + + + + + + + + QUARTUS_SYNTH + :quartus.altera.com: + QUARTUS_SYNTH + + + + + QUARTUS_SYNTH + altera_gpio + + QUARTUS_SYNTH + + + + + + dataout + + out + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + datain + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + oe + + in + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + padio + + inout + + + STD_LOGIC_VECTOR + QUARTUS_SYNTH + + + + + + + + + Intel Corporation + IOBUF + altera_gpio + 19.3.0 + + + + + device_family + device_family + Stratix 10 + + + PIN_TYPE_GUI + Data Direction + Bidir + + + SIZE + Data width + 1 + + + gui_enable_migratable_port_names + Use legacy top-level port names + true + + + gui_diff_buff + Use differential buffer + false + + + gui_pseudo_diff + Use pseudo-differential buffer + true + + + gui_pseudo_diff_off_shadow + Use pseudo-differential buffer + false + + + gui_pseudo_diff_on_shadow + Use pseudo-differential buffer + true + + + gui_bus_hold + Use bus-hold circuitry + false + + + gui_bus_hold_shadow + Use bus-hold circuitry + false + + + gui_open_drain + Use open-drain output + false + + + gui_open_drain_shadow + Use open-drain output + false + + + gui_use_oe + Enable output enable port + false + + + gui_use_oe_off_shadow + Enable output enable port + false + + + gui_use_oe_on_shadow + Enable output enable port + true + + + gui_enable_termination_ports + Enable seriestermination/paralleltermination ports + false + + + gui_enable_termination_ports_shadow + Enable seriestermination/paralleltermination ports + false + + + gui_io_reg_mode + Register mode + none + + + gui_sreset_mode + Enable synchronous clear / preset port + None + + + gui_sreset_mode_off_shadow + Enable synchronous clear / preset port + None + + + gui_areset_mode + Enable asynchronous clear / preset port + None + + + gui_areset_mode_off_shadow + Enable asynchronous clear / preset port + None + + + gui_enable_cke + Enable clock enable port + false + + + gui_enable_cke_off_shadow + Enable clock enable port + false + + + gui_hr_logic + Half Rate Logic + false + + + gui_separate_io_clks + Separate input/output Clocks + false + + + gui_separate_io_clks_off_shadow + Separate input/output Clocks + false + + + PIN_TYPE + PIN_TYPE + bidir + + + REGISTER_MODE + REGISTER_MODE + none + + + HALF_RATE + HALF_RATE + false + + + SEPARATE_I_O_CLOCKS + SEPARATE_I_O_CLOCKS + false + + + BUFFER_TYPE + BUFFER_TYPE + single-ended + + + PSEUDO_DIFF + PSEUDO_DIFF + false + + + ARESET_MODE + ARESET_MODE + none + + + SRESET_MODE + SRESET_MODE + none + + + OPEN_DRAIN + OPEN_DRAIN + false + + + BUS_HOLD + BUS_HOLD + false + + + ENABLE_OE + ENABLE_OE + false + + + ENABLE_CKE + ENABLE_CKE + false + + + ENABLE_TERM + ENABLE_TERM + false + + + SYS_INFO_DEVICE + SYS_INFO_DEVICE + 1SG280LU2F50E2VG + + + EXT_DRIVER_PARAM + EXT_DRIVER_PARAM + false + + + GENERATE_SDC_FILE + GENERATE_SDC_FILE + false + + + IP_MIGRATE_PORT_MAP_FILE + IP_MIGRATE_PORT_MAP_FILE + altddio_bidir_port_map.csv + + + AUTO_DEVICE_SPEEDGRADE + Auto DEVICE_SPEEDGRADE + 2 + + + + + + + device + Device + 1SG280LU2F50E2VG + + + deviceFamily + Device family + Stratix 10 + + + deviceSpeedGrade + Device Speed Grade + 2 + + + generationId + Generation Id + 0 + + + bonusData + bonusData + bonusData +{ + element gpio_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } +} + + + + hideFromIPCatalog + Hide from IP Catalog + true + + + lockedInterfaceDefinition + lockedInterfaceDefinition + + + + systemInfos + systemInfos + <systemInfosDefinition> + <connPtSystemInfos/> +</systemInfosDefinition> + + + + + + + + + + + + + + + + + + + + + + + + + false + false + + \ No newline at end of file diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF.bsf b/intel/sgx-dev/basefiles/IOBUF/IOBUF.bsf new file mode 100644 index 00000000..dec94866 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF.bsf @@ -0,0 +1,82 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 176 184) + (text "IOBUF" (rect 69 -1 97 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 168 20 180)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "datain" (rect 0 0 22 12)(font "Arial" (font_size 8))) + (text "datain" (rect 4 61 40 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "oe" (rect 0 0 9 12)(font "Arial" (font_size 8))) + (text "oe" (rect 4 101 16 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 48 112)(line_width 1)) + ) + (port + (pt 176 72) + (output) + (text "dataout" (rect 0 0 28 12)(font "Arial" (font_size 8))) + (text "dataout" (rect 138 61 180 72)(font "Arial" (font_size 8))) + (line (pt 176 72)(pt 128 72)(line_width 1)) + ) + (port + (pt 0 152) + (bidir) + (text "padio" (rect 0 0 20 12)(font "Arial" (font_size 8))) + (text "padio" (rect 4 141 34 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 48 152)(line_width 1)) + ) + (drawing + (text "dout" (rect 129 43 282 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 98 67 232 144)(font "Arial" (color 0 0 0))) + (text "din" (rect 32 43 82 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 53 67 142 144)(font "Arial" (color 0 0 0))) + (text "oe" (rect 35 83 82 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 53 107 142 224)(font "Arial" (color 0 0 0))) + (text "pad_io" (rect 10 123 56 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 53 147 142 304)(font "Arial" (color 0 0 0))) + (text " IOBUF " (rect 144 168 330 346)(font "Arial" )) + (line (pt 48 32)(pt 128 32)(line_width 1)) + (line (pt 128 32)(pt 128 168)(line_width 1)) + (line (pt 48 168)(pt 128 168)(line_width 1)) + (line (pt 48 32)(pt 48 168)(line_width 1)) + (line (pt 127 52)(pt 127 76)(line_width 1)) + (line (pt 126 52)(pt 126 76)(line_width 1)) + (line (pt 49 52)(pt 49 76)(line_width 1)) + (line (pt 50 52)(pt 50 76)(line_width 1)) + (line (pt 49 92)(pt 49 116)(line_width 1)) + (line (pt 50 92)(pt 50 116)(line_width 1)) + (line (pt 49 132)(pt 49 156)(line_width 1)) + (line (pt 50 132)(pt 50 156)(line_width 1)) + (line (pt 0 0)(pt 176 0)(line_width 1)) + (line (pt 176 0)(pt 176 184)(line_width 1)) + (line (pt 0 184)(pt 176 184)(line_width 1)) + (line (pt 0 0)(pt 0 184)(line_width 1)) + ) +) diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF.cmp b/intel/sgx-dev/basefiles/IOBUF/IOBUF.cmp new file mode 100644 index 00000000..165b22f9 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF.cmp @@ -0,0 +1,9 @@ + component IOBUF is + port ( + dataout : out std_logic_vector(0 downto 0); -- export + datain : in std_logic_vector(0 downto 0) := (others => 'X'); -- export + oe : in std_logic_vector(0 downto 0) := (others => 'X'); -- export + padio : inout std_logic_vector(0 downto 0) := (others => 'X') -- export + ); + end component IOBUF; + diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF.csv b/intel/sgx-dev/basefiles/IOBUF/IOBUF.csv new file mode 100644 index 00000000..5f67ad13 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF.csv @@ -0,0 +1,20 @@ +# system info IOBUF on 2020.07.29.10:13:24 +system_info: +name,value +DEVICE,1SG280LU2F50E2VG +DEVICE_FAMILY,Stratix 10 +GENERATION_ID,0 +# +# +# Files generated for IOBUF on 2020.07.29.10:13:24 +files: +filepath,kind,attributes,module,is_top +sim/IOBUF.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,IOBUF,true +altera_gpio_1930/sim/IOBUF_altera_gpio_1930_alkbnhy.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,IOBUF_altera_gpio_1930_alkbnhy,false +altera_gpio_core14_191/sim/altera_gpio.sv,SYSTEM_VERILOG,,altera_gpio,false +# +# Map from instance-path to kind of module +instances: +instancePath,module +IOBUF.gpio_0,IOBUF_altera_gpio_1930_alkbnhy +IOBUF.gpio_0.core,altera_gpio diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF.html b/intel/sgx-dev/basefiles/IOBUF/IOBUF.html new file mode 100644 index 00000000..61d98a02 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF.html @@ -0,0 +1,193 @@ + + + + + datasheet for IOBUF + + + + + + + + +
IOBUF +
+
+
+ + + + + +
2020.07.29.10:13:26Datasheet
+
+
Overview
+
+
+ + + + +
+
+
+
+
+
+
+
Memory Map
+ + + + +
+ +
+
+

gpio_0

altera_gpio v19.3.0 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PIN_TYPE_GUIBidir
SIZE1
gui_enable_migratable_port_namestrue
gui_diff_bufffalse
gui_pseudo_diff_off_shadowfalse
gui_bus_holdfalse
gui_open_drainfalse
gui_use_oe_on_shadowtrue
gui_enable_termination_ports_shadowfalse
gui_io_reg_modenone
gui_sreset_mode_off_shadowNone
gui_areset_mode_off_shadowNone
gui_enable_cke_off_shadowfalse
gui_hr_logicfalse
gui_separate_io_clks_off_shadowfalse
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ + + + + +
generation took 0.00 secondsrendering took 0.01 seconds
+ + diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF.ppf b/intel/sgx-dev/basefiles/IOBUF/IOBUF.ppf new file mode 100644 index 00000000..7cb282ac --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF.ppf @@ -0,0 +1,13 @@ + + + + + + + + + diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF.qgsimc b/intel/sgx-dev/basefiles/IOBUF/IOBUF.qgsimc new file mode 100644 index 00000000..b4e2bf88 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF.qgsimc @@ -0,0 +1,398 @@ + + + IOBUF + + + + IOBUF + 1.0 + IOBUF + IOBUF + 0 + + + + + gpio_0 + + + + ARESET_MODE + none + + + BUFFER_TYPE + single-ended + + + BUS_HOLD + false + + + ENABLE_CKE + false + + + ENABLE_OE + false + + + ENABLE_TERM + false + + + EXT_DRIVER_PARAM + false + + + GENERATE_SDC_FILE + false + + + HALF_RATE + false + + + IP_MIGRATE_PORT_MAP_FILE + altddio_bidir_port_map.csv + + + OPEN_DRAIN + false + + + PIN_TYPE + bidir + + + PIN_TYPE_GUI + Bidir + + + PSEUDO_DIFF + false + + + REGISTER_MODE + none + + + SEPARATE_I_O_CLOCKS + false + + + SIZE + 1 + + + SRESET_MODE + none + + + SYS_INFO_DEVICE + 1SG280LU2F50E2VG + + + device_family + Stratix 10 + + + gui_areset_mode + None + + + gui_areset_mode_off_shadow + None + + + gui_bus_hold + false + + + gui_bus_hold_shadow + false + + + gui_diff_buff + false + + + gui_enable_cke + false + + + gui_enable_cke_off_shadow + false + + + gui_enable_migratable_port_names + true + + + gui_enable_termination_ports + false + + + gui_enable_termination_ports_shadow + false + + + gui_hr_logic + false + + + gui_io_reg_mode + none + + + gui_open_drain + false + + + gui_open_drain_shadow + false + + + gui_pseudo_diff + true + + + gui_pseudo_diff_off_shadow + false + + + gui_pseudo_diff_on_shadow + true + + + gui_separate_io_clks + false + + + gui_separate_io_clks_off_shadow + false + + + gui_sreset_mode + None + + + gui_sreset_mode_off_shadow + None + + + gui_use_oe + false + + + gui_use_oe_off_shadow + false + + + gui_use_oe_on_shadow + true + + + + altera_gpio + 19.3.0 + gpio_0 + IOBUF_altera_gpio_1930_alkbnhy + 0 + + IOBUF.gpio_0 + + + + core + + + + ARESET_MODE + none + + + BUFFER_TYPE + single-ended + + + BUS_HOLD + false + + + ENABLE_CKE + false + + + ENABLE_OE + false + + + ENABLE_TERM + false + + + EXT_DRIVER_PARAM + false + + + GENERATE_SDC_FILE + false + + + HALF_RATE + false + + + IP_MIGRATE_PORT_MAP_FILE + altddio_bidir_port_map.csv + + + OPEN_DRAIN + false + + + PIN_TYPE + bidir + + + PIN_TYPE_GUI + Bidir + + + PSEUDO_DIFF + false + + + REGISTER_MODE + none + + + SEPARATE_I_O_CLOCKS + false + + + SIZE + 1 + + + SRESET_MODE + none + + + SYS_INFO_DEVICE + 1SG280LU2F50E2VG + + + gui_areset_mode + None + + + gui_areset_mode_off_shadow + None + + + gui_bus_hold + false + + + gui_bus_hold_shadow + false + + + gui_diff_buff + false + + + gui_enable_cke + false + + + gui_enable_cke_off_shadow + false + + + gui_enable_migratable_port_names + true + + + gui_enable_termination_ports + false + + + gui_enable_termination_ports_shadow + false + + + gui_hr_logic + false + + + gui_io_reg_mode + none + + + gui_open_drain + false + + + gui_open_drain_shadow + false + + + gui_pseudo_diff + true + + + gui_pseudo_diff_off_shadow + false + + + gui_pseudo_diff_on_shadow + true + + + gui_separate_io_clks + false + + + gui_separate_io_clks_off_shadow + false + + + gui_sreset_mode + None + + + gui_sreset_mode_off_shadow + None + + + gui_use_oe + false + + + gui_use_oe_off_shadow + false + + + gui_use_oe_on_shadow + true + + + + altera_gpio_core14 + 19.1 + core + altera_gpio + altera_gpio + 0 + + IOBUF.gpio_0.core + + + + + + + \ No newline at end of file diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF.qgsynthc b/intel/sgx-dev/basefiles/IOBUF/IOBUF.qgsynthc new file mode 100644 index 00000000..b4e2bf88 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF.qgsynthc @@ -0,0 +1,398 @@ + + + IOBUF + + + + IOBUF + 1.0 + IOBUF + IOBUF + 0 + + + + + gpio_0 + + + + ARESET_MODE + none + + + BUFFER_TYPE + single-ended + + + BUS_HOLD + false + + + ENABLE_CKE + false + + + ENABLE_OE + false + + + ENABLE_TERM + false + + + EXT_DRIVER_PARAM + false + + + GENERATE_SDC_FILE + false + + + HALF_RATE + false + + + IP_MIGRATE_PORT_MAP_FILE + altddio_bidir_port_map.csv + + + OPEN_DRAIN + false + + + PIN_TYPE + bidir + + + PIN_TYPE_GUI + Bidir + + + PSEUDO_DIFF + false + + + REGISTER_MODE + none + + + SEPARATE_I_O_CLOCKS + false + + + SIZE + 1 + + + SRESET_MODE + none + + + SYS_INFO_DEVICE + 1SG280LU2F50E2VG + + + device_family + Stratix 10 + + + gui_areset_mode + None + + + gui_areset_mode_off_shadow + None + + + gui_bus_hold + false + + + gui_bus_hold_shadow + false + + + gui_diff_buff + false + + + gui_enable_cke + false + + + gui_enable_cke_off_shadow + false + + + gui_enable_migratable_port_names + true + + + gui_enable_termination_ports + false + + + gui_enable_termination_ports_shadow + false + + + gui_hr_logic + false + + + gui_io_reg_mode + none + + + gui_open_drain + false + + + gui_open_drain_shadow + false + + + gui_pseudo_diff + true + + + gui_pseudo_diff_off_shadow + false + + + gui_pseudo_diff_on_shadow + true + + + gui_separate_io_clks + false + + + gui_separate_io_clks_off_shadow + false + + + gui_sreset_mode + None + + + gui_sreset_mode_off_shadow + None + + + gui_use_oe + false + + + gui_use_oe_off_shadow + false + + + gui_use_oe_on_shadow + true + + + + altera_gpio + 19.3.0 + gpio_0 + IOBUF_altera_gpio_1930_alkbnhy + 0 + + IOBUF.gpio_0 + + + + core + + + + ARESET_MODE + none + + + BUFFER_TYPE + single-ended + + + BUS_HOLD + false + + + ENABLE_CKE + false + + + ENABLE_OE + false + + + ENABLE_TERM + false + + + EXT_DRIVER_PARAM + false + + + GENERATE_SDC_FILE + false + + + HALF_RATE + false + + + IP_MIGRATE_PORT_MAP_FILE + altddio_bidir_port_map.csv + + + OPEN_DRAIN + false + + + PIN_TYPE + bidir + + + PIN_TYPE_GUI + Bidir + + + PSEUDO_DIFF + false + + + REGISTER_MODE + none + + + SEPARATE_I_O_CLOCKS + false + + + SIZE + 1 + + + SRESET_MODE + none + + + SYS_INFO_DEVICE + 1SG280LU2F50E2VG + + + gui_areset_mode + None + + + gui_areset_mode_off_shadow + None + + + gui_bus_hold + false + + + gui_bus_hold_shadow + false + + + gui_diff_buff + false + + + gui_enable_cke + false + + + gui_enable_cke_off_shadow + false + + + gui_enable_migratable_port_names + true + + + gui_enable_termination_ports + false + + + gui_enable_termination_ports_shadow + false + + + gui_hr_logic + false + + + gui_io_reg_mode + none + + + gui_open_drain + false + + + gui_open_drain_shadow + false + + + gui_pseudo_diff + true + + + gui_pseudo_diff_off_shadow + false + + + gui_pseudo_diff_on_shadow + true + + + gui_separate_io_clks + false + + + gui_separate_io_clks_off_shadow + false + + + gui_sreset_mode + None + + + gui_sreset_mode_off_shadow + None + + + gui_use_oe + false + + + gui_use_oe_off_shadow + false + + + gui_use_oe_on_shadow + true + + + + altera_gpio_core14 + 19.1 + core + altera_gpio + altera_gpio + 0 + + IOBUF.gpio_0.core + + + + + + + \ No newline at end of file diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF.qip b/intel/sgx-dev/basefiles/IOBUF/IOBUF.qip new file mode 100644 index 00000000..761815d2 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF.qip @@ -0,0 +1,122 @@ +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_TOOL_NAME "QsysPrimePro" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_TOOL_VERSION "20.2" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_TOOL_VENDOR_NAME "Intel Corporation" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_gpio" +set_global_assignment -library "IOBUF" -name SOPCINFO_FILE [file join $::quartus(qip_path) "IOBUF.sopcinfo"] +set_global_assignment -entity "IOBUF" -library "IOBUF" -name SLD_INFO "QSYS_NAME IOBUF HAS_SOPCINFO 1 GENERATION_ID 0" +set_global_assignment -library "IOBUF" -name MISC_FILE [file join $::quartus(qip_path) "IOBUF.cmp"] +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_TARGETED_DEVICE_FAMILY "Stratix 10" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_GENERATED_DEVICE_FAMILY "{Stratix 10}" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_QSYS_MODE "STANDALONE" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "IOBUF" -name MISC_FILE [file join $::quartus(qip_path) "../IOBUF.ip"] + +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_NAME "YWx0ZXJhX2dwaW8=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_DISPLAY_NAME "SW50ZWwgRlBHQSBHUElPIENvcmU=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_INTERNAL "On" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_VERSION "MTkuMQ==" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgRlBHQSBHUElPIENvcmU=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "UElOX1RZUEVfR1VJ::QmlkaXI=::RGF0YSBEaXJlY3Rpb24=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "U0laRQ==::MQ==::RGF0YSB3aWR0aA==" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWdyYXRhYmxlX3BvcnRfbmFtZXM=::dHJ1ZQ==::VXNlIGxlZ2FjeSB0b3AtbGV2ZWwgcG9ydCBuYW1lcw==" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "Z3VpX2RpZmZfYnVmZg==::ZmFsc2U=::VXNlIGRpZmZlcmVudGlhbCBidWZmZXI=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "Z3VpX3BzZXVkb19kaWZm::dHJ1ZQ==::VXNlIHBzZXVkby1kaWZmZXJlbnRpYWwgYnVmZmVy" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "Z3VpX2J1c19ob2xk::ZmFsc2U=::VXNlIGJ1cy1ob2xkIGNpcmN1aXRyeQ==" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "Z3VpX29wZW5fZHJhaW4=::ZmFsc2U=::VXNlIG9wZW4tZHJhaW4gb3V0cHV0" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9vZQ==::ZmFsc2U=::RW5hYmxlIG91dHB1dCBlbmFibGUgcG9ydA==" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV90ZXJtaW5hdGlvbl9wb3J0cw==::ZmFsc2U=::RW5hYmxlIHNlcmllc3Rlcm1pbmF0aW9uL3BhcmFsbGVsdGVybWluYXRpb24gcG9ydHM=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "Z3VpX2lvX3JlZ19tb2Rl::bm9uZQ==::UmVnaXN0ZXIgbW9kZQ==" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "Z3VpX3NyZXNldF9tb2Rl::Tm9uZQ==::RW5hYmxlIHN5bmNocm9ub3VzIGNsZWFyIC8gcHJlc2V0IHBvcnQ=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "Z3VpX2FyZXNldF9tb2Rl::Tm9uZQ==::RW5hYmxlIGFzeW5jaHJvbm91cyBjbGVhciAvIHByZXNldCBwb3J0" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9ja2U=::ZmFsc2U=::RW5hYmxlIGNsb2NrIGVuYWJsZSBwb3J0" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "UElOX1RZUEU=::YmlkaXI=::UElOX1RZUEU=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfTU9ERQ==::bm9uZQ==::UkVHSVNURVJfTU9ERQ==" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "SEFMRl9SQVRF::ZmFsc2U=::SEFMRl9SQVRF" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "U0VQQVJBVEVfSV9PX0NMT0NLUw==::ZmFsc2U=::U0VQQVJBVEVfSV9PX0NMT0NLUw==" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "QlVGRkVSX1RZUEU=::c2luZ2xlLWVuZGVk::QlVGRkVSX1RZUEU=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "UFNFVURPX0RJRkY=::ZmFsc2U=::UFNFVURPX0RJRkY=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "QVJFU0VUX01PREU=::bm9uZQ==::QVJFU0VUX01PREU=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "U1JFU0VUX01PREU=::bm9uZQ==::U1JFU0VUX01PREU=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "T1BFTl9EUkFJTg==::ZmFsc2U=::T1BFTl9EUkFJTg==" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "QlVTX0hPTEQ=::ZmFsc2U=::QlVTX0hPTEQ=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09F::ZmFsc2U=::RU5BQkxFX09F" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NLRQ==::ZmFsc2U=::RU5BQkxFX0NLRQ==" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1RFUk0=::ZmFsc2U=::RU5BQkxFX1RFUk0=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNF::MVNHMjgwTFUyRjUwRTJWRw==::U1lTX0lORk9fREVWSUNF" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "RVhUX0RSSVZFUl9QQVJBTQ==::ZmFsc2U=::RVhUX0RSSVZFUl9QQVJBTQ==" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "R0VORVJBVEVfU0RDX0ZJTEU=::ZmFsc2U=::R0VORVJBVEVfU0RDX0ZJTEU=" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_PARAMETER "SVBfTUlHUkFURV9QT1JUX01BUF9GSUxF::YWx0ZGRpb19iaWRpcl9wb3J0X21hcC5jc3Y=::SVBfTUlHUkFURV9QT1JUX01BUF9GSUxF" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_COMPONENT_GROUP "SS9P" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_NAME "SU9CVUZfYWx0ZXJhX2dwaW9fMTkzMF9hbGtibmh5" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBJbnRlbCBGUEdBIElQ" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_VERSION "MTkuMy4w" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgRlBHQSBHUElP" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::U3RyYXRpeCAxMA==::ZGV2aWNlX2ZhbWlseQ==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "UElOX1RZUEVfR1VJ::QmlkaXI=::RGF0YSBEaXJlY3Rpb24=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "U0laRQ==::MQ==::RGF0YSB3aWR0aA==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWdyYXRhYmxlX3BvcnRfbmFtZXM=::dHJ1ZQ==::VXNlIGxlZ2FjeSB0b3AtbGV2ZWwgcG9ydCBuYW1lcw==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "Z3VpX2RpZmZfYnVmZg==::ZmFsc2U=::VXNlIGRpZmZlcmVudGlhbCBidWZmZXI=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "Z3VpX3BzZXVkb19kaWZm::dHJ1ZQ==::VXNlIHBzZXVkby1kaWZmZXJlbnRpYWwgYnVmZmVy" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "Z3VpX2J1c19ob2xk::ZmFsc2U=::VXNlIGJ1cy1ob2xkIGNpcmN1aXRyeQ==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "Z3VpX29wZW5fZHJhaW4=::ZmFsc2U=::VXNlIG9wZW4tZHJhaW4gb3V0cHV0" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9vZQ==::ZmFsc2U=::RW5hYmxlIG91dHB1dCBlbmFibGUgcG9ydA==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV90ZXJtaW5hdGlvbl9wb3J0cw==::ZmFsc2U=::RW5hYmxlIHNlcmllc3Rlcm1pbmF0aW9uL3BhcmFsbGVsdGVybWluYXRpb24gcG9ydHM=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "Z3VpX2lvX3JlZ19tb2Rl::bm9uZQ==::UmVnaXN0ZXIgbW9kZQ==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "Z3VpX3NyZXNldF9tb2Rl::Tm9uZQ==::RW5hYmxlIHN5bmNocm9ub3VzIGNsZWFyIC8gcHJlc2V0IHBvcnQ=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "Z3VpX2FyZXNldF9tb2Rl::Tm9uZQ==::RW5hYmxlIGFzeW5jaHJvbm91cyBjbGVhciAvIHByZXNldCBwb3J0" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9ja2U=::ZmFsc2U=::RW5hYmxlIGNsb2NrIGVuYWJsZSBwb3J0" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "UElOX1RZUEU=::YmlkaXI=::UElOX1RZUEU=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfTU9ERQ==::bm9uZQ==::UkVHSVNURVJfTU9ERQ==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "SEFMRl9SQVRF::ZmFsc2U=::SEFMRl9SQVRF" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "U0VQQVJBVEVfSV9PX0NMT0NLUw==::ZmFsc2U=::U0VQQVJBVEVfSV9PX0NMT0NLUw==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "QlVGRkVSX1RZUEU=::c2luZ2xlLWVuZGVk::QlVGRkVSX1RZUEU=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "UFNFVURPX0RJRkY=::ZmFsc2U=::UFNFVURPX0RJRkY=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "QVJFU0VUX01PREU=::bm9uZQ==::QVJFU0VUX01PREU=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "U1JFU0VUX01PREU=::bm9uZQ==::U1JFU0VUX01PREU=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "T1BFTl9EUkFJTg==::ZmFsc2U=::T1BFTl9EUkFJTg==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "QlVTX0hPTEQ=::ZmFsc2U=::QlVTX0hPTEQ=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09F::ZmFsc2U=::RU5BQkxFX09F" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NLRQ==::ZmFsc2U=::RU5BQkxFX0NLRQ==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1RFUk0=::ZmFsc2U=::RU5BQkxFX1RFUk0=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "U1lTX0lORk9fREVWSUNF::MVNHMjgwTFUyRjUwRTJWRw==::U1lTX0lORk9fREVWSUNF" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "RVhUX0RSSVZFUl9QQVJBTQ==::ZmFsc2U=::RVhUX0RSSVZFUl9QQVJBTQ==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "R0VORVJBVEVfU0RDX0ZJTEU=::ZmFsc2U=::R0VORVJBVEVfU0RDX0ZJTEU=" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "SVBfTUlHUkFURV9QT1JUX01BUF9GSUxF::YWx0ZGRpb19iaWRpcl9wb3J0X21hcC5jc3Y=::SVBfTUlHUkFURV9QT1JUX01BUF9GSUxF" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Mg==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL0kvTw==" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cDovL3d3dy5hbHRlcmEuY29tL2xpdGVyYXR1cmUvdWcvdWdfYWx0ZXJhX2dwaW8ucGRm" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuaW50ZWwuY29tL2NvbnRlbnQvd3d3L3VzL2VuL3Byb2dyYW1tYWJsZS9kb2N1bWVudGF0aW9uL3NhbTE0MzgzNDkxNjYxNTQuaHRtbCNzYW0xNDM4ODcwNTMxODM1" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MjE2OTgwNDIwODcvaGNvMTQyMTY5ODAxMzQwOA==" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_COMPONENT_NAME "SU9CVUY=" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_COMPONENT_REPORT_HIERARCHY "On" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_COMPONENT_VERSION "MS4w" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MA==::QXV0byBHRU5FUkFUSU9OX0lE" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::U3RyYXRpeCAxMA==::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MVNHMjgwTFUyRjUwRTJWRw==::QXV0byBERVZJQ0U=" +set_global_assignment -entity "IOBUF" -library "IOBUF" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Mg==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" + +set_instance_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name MESSAGE_DISABLE 10034 +set_instance_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name MESSAGE_DISABLE 10230 +set_instance_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name MESSAGE_DISABLE 10036 + +set_global_assignment -library "altera_gpio_core14_191" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "altera_gpio_core14_191/synth/altera_gpio.sv"] +set_global_assignment -library "altera_gpio_1930" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_gpio_1930/synth/IOBUF_altera_gpio_1930_alkbnhy.v"] +set_global_assignment -library "IOBUF" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/IOBUF.v"] + + +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_TOOL_NAME "altera_gpio" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_TOOL_VERSION "19.3.0" +set_global_assignment -entity "IOBUF_altera_gpio_1930_alkbnhy" -library "altera_gpio_1930" -name IP_TOOL_ENV "QsysPrimePro" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_TOOL_NAME "altera_gpio_core14" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_TOOL_VERSION "19.1" +set_global_assignment -entity "altera_gpio" -library "altera_gpio_core14_191" -name IP_TOOL_ENV "QsysPrimePro" + diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF.sopcinfo b/intel/sgx-dev/basefiles/IOBUF/IOBUF.sopcinfo new file mode 100644 index 00000000..d641c573 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF.sopcinfo @@ -0,0 +1,705 @@ + + + + + + + java.lang.Integer + 0 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + Stratix 10 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + 1SG280LU2F50E2VG + false + true + false + true + DEVICE + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + Stratix 10 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + java.lang.String + Stratix 10 + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + Bidir + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + true + false + true + true + + + boolean + true + true + false + false + true + + + boolean + false + false + true + true + true + + + boolean + false + true + false + false + true + + + boolean + false + false + true + true + true + + + boolean + false + true + false + false + true + + + boolean + false + false + true + false + true + + + boolean + false + true + false + false + true + + + boolean + true + true + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + true + false + true + true + + + java.lang.String + none + false + true + true + true + + + java.lang.String + None + false + true + false + true + + + java.lang.String + None + true + false + true + true + + + java.lang.String + None + false + true + false + true + + + java.lang.String + None + true + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + true + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + false + true + + + boolean + false + true + false + true + true + + + java.lang.String + bidir + true + true + false + true + + + java.lang.String + none + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + single-ended + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + none + true + true + false + true + + + java.lang.String + none + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + false + true + true + false + true + + + java.lang.String + 1SG280LU2F50E2VG + false + true + false + true + DEVICE + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + altddio_bidir_port_map.csv + false + true + false + true + + + java.lang.String + 2 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + ui.blockdiagram.direction + output + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + dataout + Output + 1 + export + + + + + + ui.blockdiagram.direction + input + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + datain + Input + 1 + export + + + + + + ui.blockdiagram.direction + input + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + oe + Input + 1 + export + + + + + + ui.blockdiagram.direction + bidir + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + padio + Bidir + 1 + export + + + + + 1 + altera_gpio + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + GPIO Intel FPGA IP + 19.3.0 + + + 4 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 20.2 + + 20.2 50 + + diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF.spd b/intel/sgx-dev/basefiles/IOBUF/IOBUF.spd new file mode 100644 index 00000000..385cb165 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF.spd @@ -0,0 +1,19 @@ + + + + + + + + diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF.xml b/intel/sgx-dev/basefiles/IOBUF/IOBUF.xml new file mode 100644 index 00000000..9099ef47 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF.xml @@ -0,0 +1,230 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: IOBUF" + "Generating: IOBUF_altera_gpio_1930_alkbnhy" + "Generating: altera_gpio" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: IOBUF_altera_gpio_1930_alkbnhy" + "Generating: altera_gpio" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + "Generating: altera_gpio" + + + diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF_bb.v b/intel/sgx-dev/basefiles/IOBUF/IOBUF_bb.v new file mode 100644 index 00000000..a036293b --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF_bb.v @@ -0,0 +1,8 @@ +module IOBUF ( + output wire [0:0] dataout, // dout.export + input wire [0:0] datain, // din.export + input wire [0:0] oe, // oe.export + inout wire [0:0] padio // pad_io.export + ); +endmodule + diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF_generation.rpt b/intel/sgx-dev/basefiles/IOBUF/IOBUF_generation.rpt new file mode 100644 index 00000000..ff2fb458 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF_generation.rpt @@ -0,0 +1,16 @@ +Info: Generated by version: 20.2 build 50 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/jdtarang/RISC-V/git/freedom-jdtarang/fpga-shells/intel/sgx-dev/projects/FPGAChip/IOBUF.ip --block-symbol-file --output-directory=/home/jdtarang/RISC-V/git/freedom-jdtarang/fpga-shells/intel/sgx-dev/projects/FPGAChip/IOBUF --family="Stratix 10" --part=1SG280LU2F50E2VG +Info: IOBUF.gpio_0: Intel GPIO supports a maximum interface frequency of 300 MHZ. +Info: qsys-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/jdtarang/RISC-V/git/freedom-jdtarang/fpga-shells/intel/sgx-dev/projects/FPGAChip/IOBUF.ip --synthesis=VERILOG --output-directory=/home/jdtarang/RISC-V/git/freedom-jdtarang/fpga-shells/intel/sgx-dev/projects/FPGAChip/IOBUF --family="Stratix 10" --part=1SG280LU2F50E2VG +Info: IOBUF.gpio_0: Intel GPIO supports a maximum interface frequency of 300 MHZ. +Info: Skipping generation of IOBUF: files already generated. +Info: qsys-generate succeeded. +Info: Finished: Create HDL design files for synthesis +Info: Starting: Generate IP Core Documentation +Info: No documentation filesets were found for components in IOBUF. No files generated. +Info: Finished: Generate IP Core Documentation diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF_generation_previous.rpt b/intel/sgx-dev/basefiles/IOBUF/IOBUF_generation_previous.rpt new file mode 100644 index 00000000..ff2fb458 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF_generation_previous.rpt @@ -0,0 +1,16 @@ +Info: Generated by version: 20.2 build 50 +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/jdtarang/RISC-V/git/freedom-jdtarang/fpga-shells/intel/sgx-dev/projects/FPGAChip/IOBUF.ip --block-symbol-file --output-directory=/home/jdtarang/RISC-V/git/freedom-jdtarang/fpga-shells/intel/sgx-dev/projects/FPGAChip/IOBUF --family="Stratix 10" --part=1SG280LU2F50E2VG +Info: IOBUF.gpio_0: Intel GPIO supports a maximum interface frequency of 300 MHZ. +Info: qsys-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/jdtarang/RISC-V/git/freedom-jdtarang/fpga-shells/intel/sgx-dev/projects/FPGAChip/IOBUF.ip --synthesis=VERILOG --output-directory=/home/jdtarang/RISC-V/git/freedom-jdtarang/fpga-shells/intel/sgx-dev/projects/FPGAChip/IOBUF --family="Stratix 10" --part=1SG280LU2F50E2VG +Info: IOBUF.gpio_0: Intel GPIO supports a maximum interface frequency of 300 MHZ. +Info: Skipping generation of IOBUF: files already generated. +Info: qsys-generate succeeded. +Info: Finished: Create HDL design files for synthesis +Info: Starting: Generate IP Core Documentation +Info: No documentation filesets were found for components in IOBUF. No files generated. +Info: Finished: Generate IP Core Documentation diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF_inst.v b/intel/sgx-dev/basefiles/IOBUF/IOBUF_inst.v new file mode 100644 index 00000000..e576340f --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF_inst.v @@ -0,0 +1,7 @@ + IOBUF u0 ( + .dataout (_connected_to_dataout_), // output, width = 1, dout.export + .datain (_connected_to_datain_), // input, width = 1, din.export + .oe (_connected_to_oe_), // input, width = 1, oe.export + .padio (_connected_to_padio_) // inout, width = 1, pad_io.export + ); + diff --git a/intel/sgx-dev/basefiles/IOBUF/IOBUF_inst.vhd b/intel/sgx-dev/basefiles/IOBUF/IOBUF_inst.vhd new file mode 100644 index 00000000..5bd3907b --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/IOBUF_inst.vhd @@ -0,0 +1,17 @@ + component IOBUF is + port ( + dataout : out std_logic_vector(0 downto 0); -- export + datain : in std_logic_vector(0 downto 0) := (others => 'X'); -- export + oe : in std_logic_vector(0 downto 0) := (others => 'X'); -- export + padio : inout std_logic_vector(0 downto 0) := (others => 'X') -- export + ); + end component IOBUF; + + u0 : component IOBUF + port map ( + dataout => CONNECTED_TO_dataout, -- dout.export + datain => CONNECTED_TO_datain, -- din.export + oe => CONNECTED_TO_oe, -- oe.export + padio => CONNECTED_TO_padio -- pad_io.export + ); + diff --git a/intel/sgx-dev/basefiles/IOBUF/altera_gpio_1930/sim/IOBUF_altera_gpio_1930_alkbnhy.v b/intel/sgx-dev/basefiles/IOBUF/altera_gpio_1930/sim/IOBUF_altera_gpio_1930_alkbnhy.v new file mode 100644 index 00000000..5a688317 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/altera_gpio_1930/sim/IOBUF_altera_gpio_1930_alkbnhy.v @@ -0,0 +1,59 @@ +// IOBUF_altera_gpio_1930_alkbnhy.v + +// This file was auto-generated from altera_gpio_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 20.2 50 + +`timescale 1 ps / 1 ps +module IOBUF_altera_gpio_1930_alkbnhy ( + output wire [0:0] dataout, // dout.export + input wire [0:0] datain, // din.export + input wire [0:0] oe, // oe.export + inout wire [0:0] padio // pad_io.export + ); + + altera_gpio #( + .SIZE (1), + .PIN_TYPE ("bidir"), + .REGISTER_MODE ("none"), + .HALF_RATE ("false"), + .SEPARATE_I_O_CLOCKS ("false"), + .BUFFER_TYPE ("single-ended"), + .PSEUDO_DIFF ("false"), + .ARESET_MODE ("none"), + .SRESET_MODE ("none"), + .OPEN_DRAIN ("false"), + .BUS_HOLD ("false"), + .ENABLE_OE ("false"), + .ENABLE_CKE ("false"), + .ENABLE_TERM ("false") + ) core ( + .dout (dataout), // output, width = 1, dout.export + .din (datain), // input, width = 1, din.export + .oe (oe), // input, width = 1, oe.export + .pad_io (padio), // inout, width = 1, pad_io.export + .cke (1'b1), // (terminated), + .ck_fr_in (1'b0), // (terminated), + .ck_fr_out (1'b0), // (terminated), + .ck_in (1'b0), // (terminated), + .ck_out (1'b0), // (terminated), + .ck_fr (1'b0), // (terminated), + .ck (1'b0), // (terminated), + .ck_hr_in (1'b0), // (terminated), + .ck_hr_out (1'b0), // (terminated), + .ck_hr (1'b0), // (terminated), + .pad_io_b (), // (terminated), + .pad_in (1'b0), // (terminated), + .pad_in_b (1'b0), // (terminated), + .pad_out (), // (terminated), + .pad_out_b (), // (terminated), + .seriesterminationcontrol (16'b0000000000000000), // (terminated), + .parallelterminationcontrol (16'b0000000000000000), // (terminated), + .aclr (1'b0), // (terminated), + .aset (1'b0), // (terminated), + .sclr (1'b0), // (terminated), + .sset (1'b0) // (terminated), + ); + +endmodule diff --git a/intel/sgx-dev/basefiles/IOBUF/altera_gpio_1930/synth/IOBUF_altera_gpio_1930_alkbnhy.v b/intel/sgx-dev/basefiles/IOBUF/altera_gpio_1930/synth/IOBUF_altera_gpio_1930_alkbnhy.v new file mode 100644 index 00000000..5a688317 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/altera_gpio_1930/synth/IOBUF_altera_gpio_1930_alkbnhy.v @@ -0,0 +1,59 @@ +// IOBUF_altera_gpio_1930_alkbnhy.v + +// This file was auto-generated from altera_gpio_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 20.2 50 + +`timescale 1 ps / 1 ps +module IOBUF_altera_gpio_1930_alkbnhy ( + output wire [0:0] dataout, // dout.export + input wire [0:0] datain, // din.export + input wire [0:0] oe, // oe.export + inout wire [0:0] padio // pad_io.export + ); + + altera_gpio #( + .SIZE (1), + .PIN_TYPE ("bidir"), + .REGISTER_MODE ("none"), + .HALF_RATE ("false"), + .SEPARATE_I_O_CLOCKS ("false"), + .BUFFER_TYPE ("single-ended"), + .PSEUDO_DIFF ("false"), + .ARESET_MODE ("none"), + .SRESET_MODE ("none"), + .OPEN_DRAIN ("false"), + .BUS_HOLD ("false"), + .ENABLE_OE ("false"), + .ENABLE_CKE ("false"), + .ENABLE_TERM ("false") + ) core ( + .dout (dataout), // output, width = 1, dout.export + .din (datain), // input, width = 1, din.export + .oe (oe), // input, width = 1, oe.export + .pad_io (padio), // inout, width = 1, pad_io.export + .cke (1'b1), // (terminated), + .ck_fr_in (1'b0), // (terminated), + .ck_fr_out (1'b0), // (terminated), + .ck_in (1'b0), // (terminated), + .ck_out (1'b0), // (terminated), + .ck_fr (1'b0), // (terminated), + .ck (1'b0), // (terminated), + .ck_hr_in (1'b0), // (terminated), + .ck_hr_out (1'b0), // (terminated), + .ck_hr (1'b0), // (terminated), + .pad_io_b (), // (terminated), + .pad_in (1'b0), // (terminated), + .pad_in_b (1'b0), // (terminated), + .pad_out (), // (terminated), + .pad_out_b (), // (terminated), + .seriesterminationcontrol (16'b0000000000000000), // (terminated), + .parallelterminationcontrol (16'b0000000000000000), // (terminated), + .aclr (1'b0), // (terminated), + .aset (1'b0), // (terminated), + .sclr (1'b0), // (terminated), + .sset (1'b0) // (terminated), + ); + +endmodule diff --git a/intel/sgx-dev/basefiles/IOBUF/altera_gpio_core14_191/sim/altera_gpio.sv b/intel/sgx-dev/basefiles/IOBUF/altera_gpio_core14_191/sim/altera_gpio.sv new file mode 100644 index 00000000..1dc438a1 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/altera_gpio_core14_191/sim/altera_gpio.sv @@ -0,0 +1,691 @@ +// (C) 2001-2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +module altera_gpio_one_bit( + ck, + ck_in, + ck_out, + ck_fr, + ck_fr_in, + ck_fr_out, + ck_hr, + ck_hr_in, + ck_hr_out, + oe, + din, + dout, + pad, + pad_b, + seriesterminationcontrol, + parallelterminationcontrol, + aclr, + aset, + sclr, + sset, + cke +); + + parameter PIN_TYPE = "output"; + parameter BUFFER_TYPE = "single-ended"; + parameter PSEUDO_DIFF = "false"; + parameter REGISTER_MODE = "none"; + parameter HALF_RATE = "false"; + parameter SEPARATE_I_O_CLOCKS = "false"; + parameter ARESET_MODE = "none"; + parameter SRESET_MODE = "none"; + parameter BUS_HOLD = "false"; + parameter OPEN_DRAIN = "false"; + parameter ENABLE_CKE = "false"; + parameter ENABLE_OE = "false"; + parameter ENABLE_TERM = "false"; + + localparam OE_SIZE = (HALF_RATE == "true") ? 2 : 1; + localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? + (HALF_RATE == "true") ? + 4 : 2 + : 1; + + input ck; + input ck_in; + input ck_out; + input ck_fr; + input ck_fr_in; + input ck_fr_out; + input ck_hr; + input ck_hr_in; + input ck_hr_out; + input [OE_SIZE - 1:0] oe; + input [DATA_SIZE - 1:0] din; + output [DATA_SIZE - 1:0] dout; + inout pad; + inout pad_b; + input [15:0] seriesterminationcontrol; + input [15:0] parallelterminationcontrol; + input aclr; + input aset; + input sclr; + input sset; + input cke; + + wire hr_out_clk; + wire fr_out_clk; + wire hr_in_clk; + wire fr_in_clk; + + wire din_ddr; + wire buf_in; + + wire areset; + wire sreset; + + generate + if(ARESET_MODE == "preset") begin + assign areset = ~aset; + end + else begin + assign areset = ~aclr; + end + endgenerate + + generate + if(SRESET_MODE == "preset") begin + assign sreset = sset; + end + else begin + assign sreset = sclr; + end + endgenerate + + generate + if(SEPARATE_I_O_CLOCKS == "true") + begin + if(HALF_RATE == "true") begin + assign hr_out_clk = ck_hr_out; + assign fr_out_clk = ck_fr_out; + assign hr_in_clk = ck_hr_in; + assign fr_in_clk = ck_fr_in; + end + else begin + assign fr_out_clk = ck_out; + assign fr_in_clk = ck_in; + end + end + else begin + if(HALF_RATE == "true") begin + assign hr_out_clk = ck_hr; + assign fr_out_clk = ck_fr; + assign hr_in_clk = ck_hr; + assign fr_in_clk = ck_fr; + end + else begin + assign fr_out_clk = ck; + assign fr_in_clk = ck; + end + end + endgenerate + + generate + if (PIN_TYPE == "output" || PIN_TYPE == "bidir") + begin: out_path + wire [1:0] din_fr; + + if (HALF_RATE == "true") + begin: out_path_hr + fourteennm_ddio_out + #( + .half_rate_mode("true"), + .async_mode(ARESET_MODE) + ) iodout_hr_ddio_0 ( + .areset(areset), + .datainhi(din[2]), + .datainlo(din[0]), + .dataout(din_fr[0]), + .clk (hr_out_clk) + ); + + fourteennm_ddio_out + #( + .half_rate_mode("true"), + .async_mode(ARESET_MODE) + ) iodout_hr_ddio_1 ( + .areset(areset), + .datainhi(din[3]), + .datainlo(din[1]), + .dataout(din_fr[1]), + .clk (hr_out_clk) + ); + end + else + begin: out_path_hr_byp + assign din_fr[DATA_SIZE - 1:0] = din; + end + + if (REGISTER_MODE == "ddr") + begin: out_path_fr + fourteennm_ddio_out + #( + .half_rate_mode("false"), + .async_mode(ARESET_MODE), + .sync_mode(SRESET_MODE) + ) fr_out_data_ddio ( + .ena(cke), + .areset(areset), + .sreset(sreset), + .datainhi(din_fr[1]), + .datainlo(din_fr[0]), + .dataout(din_ddr), + .clk (fr_out_clk) + ); + end + else if (REGISTER_MODE == "sdr") + begin: out_path_reg + reg reg_data_out; + always @(posedge fr_out_clk) + reg_data_out <= din_fr[0]; + + assign din_ddr = reg_data_out; + end + else + begin: out_path_byp + assign din_ddr = din_fr[0]; + end + end + endgenerate + + generate + wire oe_fr; + wire oe_ddr; + + if (PIN_TYPE == "bidir" || ENABLE_OE == "true") + begin: oe_path + if (HALF_RATE == "true") + begin: oe_path_hr + fourteennm_ddio_out + #( + .half_rate_mode("true") + ) oe_in_hr_ddio ( + .datainhi(oe[1]), + .datainlo(oe[0]), + .dataout(oe_fr), + .clk (hr_out_clk) + ); + end + else + begin: oe_path_hr_byp + assign oe_fr = oe[0]; + end + + if (REGISTER_MODE == "sdr" || REGISTER_MODE == "ddr") + begin: oe_path_fr + reg oe_reg; + always @(posedge fr_out_clk) oe_reg <= oe_fr; + assign oe_ddr = oe_reg; + end + else + begin: oe_path_byp + assign oe_ddr = oe_fr; + end + end + else if (PIN_TYPE == "output") + begin + assign oe_ddr = 1'b1; + end + else + begin + assign oe_ddr = 1'b0; + end + endgenerate + + generate + if (PIN_TYPE == "input" || PIN_TYPE == "bidir") + begin : input_path + wire [1:0] buf_in_fr; + + if (REGISTER_MODE == "ddr") + begin: in_path_fr + fourteennm_ddio_in + #( + .async_mode(ARESET_MODE), + .sync_mode(SRESET_MODE) + ) buffer_data_in_fr_ddio ( + .ena(cke), + .areset(areset), + .sreset(sreset), + .datain(buf_in), + .clk (fr_in_clk), + .regouthi(buf_in_fr[1]), + .regoutlo(buf_in_fr[0]) + ); + end + else if (REGISTER_MODE == "sdr") + begin: in_path_reg + reg ro; + always @(posedge fr_in_clk) begin + ro <= buf_in; + end + assign buf_in_fr[0] = ro; + end + else + begin: in_byp + assign buf_in_fr[0] = buf_in; + end + + if (HALF_RATE == "true") + begin: in_path_hr + fourteennm_ddio_in + #( + .async_mode(ARESET_MODE), + .sync_mode("none") + ) buffer_data_in_hr_ddio_0 ( + .areset(areset), + .datain(buf_in_fr[0]), + .clk (hr_in_clk), + .regouthi(dout[2]), + .regoutlo(dout[0]) + ); + + fourteennm_ddio_in + #( + .async_mode(ARESET_MODE), + .sync_mode("none") + ) buffer_data_in_hr_ddio_1 ( + .areset(areset), + .datain(buf_in_fr[1]), + .clk (hr_in_clk), + .regouthi(dout[3]), + .regoutlo(dout[1]) + ); + end + else + begin: in_path_hr_byp + assign dout[DATA_SIZE - 1:0] = buf_in_fr[DATA_SIZE - 1:0]; + end + end + endgenerate + + generate + if (PIN_TYPE == "output" || PIN_TYPE == "bidir") + begin : output_buffer + if(BUFFER_TYPE == "differential") begin + wire obuf_din; + wire obuf_din_b; + wire obuf_oe; + wire obuf_oe_b; + + if(PSEUDO_DIFF == "true") begin + if (PIN_TYPE == "output" && ENABLE_OE == "false") + begin : oe_path + fourteennm_pseudo_diff_out pseudo_diff_out( + .i(din_ddr), + .o(obuf_din), + .obar(obuf_din_b) + ); + + if (ENABLE_TERM == "true") begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .i(obuf_din), + .o(pad) + ); + + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_1 ( + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .i(obuf_din_b), + .o(pad_b) + ); + end + else begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .i(obuf_din), + .o(pad) + ); + + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_1 ( + .i(obuf_din_b), + .o(pad_b) + ); + end + end + else begin + fourteennm_pseudo_diff_out pseudo_diff_out( + .i(din_ddr), + .o(obuf_din), + .obar(obuf_din_b), + .oein(oe_ddr), + .oeout(obuf_oe), + .oebout(obuf_oe_b) + ); + if (ENABLE_TERM == "true") begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .i(obuf_din), + .oe(obuf_oe), + .o(pad) + ); + + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_1 ( + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .i(obuf_din_b), + .oe(obuf_oe_b), + .o(pad_b) + ); + end + else begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .i(obuf_din), + .oe(obuf_oe), + .o(pad) + ); + + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_1 ( + .i(obuf_din_b), + .oe(obuf_oe_b), + .o(pad_b) + ); + end + end + end + else begin + if (ENABLE_TERM == "true") begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .i(din_ddr), + .oe(oe_ddr), + .o(pad), + .obar(pad_b) + ); + end + else begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .i(din_ddr), + .oe(oe_ddr), + .o(pad), + .obar(pad_b) + ); + end + + end + end + else begin + if (ENABLE_TERM == "true") begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf ( + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .i(din_ddr), + .oe(oe_ddr), + .o(pad) + ); + end + else begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf ( + .i(din_ddr), + .oe(oe_ddr), + .o(pad) + ); + end + end + end + endgenerate + + generate + if (PIN_TYPE == "input" || PIN_TYPE == "bidir") + begin : input_buffer + if(BUFFER_TYPE == "differential") begin + if (ENABLE_TERM == "true") begin + fourteennm_io_ibuf + #( + .differential_mode("true"), + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .ibar(pad_b), + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .o(buf_in) + ); + end + else begin + fourteennm_io_ibuf + #( + .differential_mode("true"), + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .ibar(pad_b), + .o(buf_in) + ); + end + end + else begin + if (ENABLE_TERM == "true") begin + fourteennm_io_ibuf + #( + .differential_mode("false"), + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .o(buf_in) + ); + end + else begin + fourteennm_io_ibuf + #( + .differential_mode("false"), + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .o(buf_in) + ); + end + end + end + endgenerate + +endmodule + +module altera_gpio( + ck, + ck_in, + ck_out, + ck_fr, + ck_fr_in, + ck_fr_out, + ck_hr, + ck_hr_in, + ck_hr_out, + oe, + din, + dout, + pad_io, + pad_io_b, + pad_in, + pad_in_b, + pad_out, + pad_out_b, + seriesterminationcontrol, + parallelterminationcontrol, + aclr, + aset, + sclr, + sset, + cke +); + + parameter PIN_TYPE = "output"; + parameter BUFFER_TYPE = "single-ended"; + parameter PSEUDO_DIFF = "false"; + parameter REGISTER_MODE = "none"; + parameter HALF_RATE = "false"; + parameter SEPARATE_I_O_CLOCKS = "false"; + parameter SIZE = 4; + parameter ARESET_MODE = "none"; + parameter SRESET_MODE = "none"; + parameter BUS_HOLD = "false"; + parameter OPEN_DRAIN = "false"; + parameter ENABLE_CKE = "false"; + parameter ENABLE_OE = "false"; + parameter ENABLE_TERM = "false"; + + localparam OE_SIZE = (HALF_RATE == "true") ? 2 : 1; + localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? + (HALF_RATE == "true") ? + 4 : 2 + : 1; + + input ck; + input ck_in; + input ck_out; + input ck_fr; + input ck_fr_in; + input ck_fr_out; + input ck_hr; + input ck_hr_in; + input ck_hr_out; + input [SIZE * OE_SIZE - 1:0] oe; + input [SIZE * DATA_SIZE - 1:0] din; + output [SIZE * DATA_SIZE - 1:0] dout; + input [15:0] seriesterminationcontrol; + input [15:0] parallelterminationcontrol; + inout [SIZE - 1:0] pad_io; + inout [SIZE - 1:0] pad_io_b; + input [SIZE - 1:0] pad_in; + input [SIZE - 1:0] pad_in_b; + output [SIZE - 1:0] pad_out; + output [SIZE - 1:0] pad_out_b; + input aclr; + input aset; + input sclr; + input sset; + input cke; + + wire [SIZE * OE_SIZE - 1:0] oe_reordered; + wire [SIZE * DATA_SIZE - 1:0] din_reordered; + wire [SIZE * DATA_SIZE - 1:0] dout_reordered; + wire [SIZE - 1:0] pad_io; + wire [SIZE - 1:0] pad_io_b; + + generate + if (PIN_TYPE == "input") + begin + assign pad_io = pad_in; + assign pad_io_b = pad_in_b; + end + else if (PIN_TYPE == "output") + begin + assign pad_out = pad_io; + assign pad_out_b = pad_io_b; + end + endgenerate + + genvar j, k; + generate + for(j = 0; j < SIZE ; j = j + 1) begin : j_loop + for(k = 0; k < DATA_SIZE; k = k + 1) begin : k_d_loop + assign din_reordered[j * DATA_SIZE + k] = din[j + k * SIZE]; + assign dout[j + k * SIZE] = dout_reordered[j * DATA_SIZE + k]; + end + for(k = 0; k < OE_SIZE; k = k + 1) begin : k_oe_loop + assign oe_reordered[j * OE_SIZE + k] = oe[j + k * SIZE]; + end + end + endgenerate + + genvar i; + generate + for(i = 0 ; i < SIZE ; i = i + 1) begin : i_loop + altera_gpio_one_bit #( + .PIN_TYPE(PIN_TYPE), + .BUFFER_TYPE(BUFFER_TYPE), + .PSEUDO_DIFF(PSEUDO_DIFF), + .REGISTER_MODE(REGISTER_MODE), + .HALF_RATE(HALF_RATE), + .SEPARATE_I_O_CLOCKS(SEPARATE_I_O_CLOCKS), + .ARESET_MODE(ARESET_MODE), + .SRESET_MODE(SRESET_MODE), + .BUS_HOLD(BUS_HOLD), + .OPEN_DRAIN(OPEN_DRAIN), + .ENABLE_CKE(ENABLE_CKE), + .ENABLE_OE(ENABLE_OE), + .ENABLE_TERM(ENABLE_TERM) + ) altera_gpio_bit_i ( + .ck(ck), + .ck_in(ck_in), + .ck_out(ck_out), + .ck_fr(ck_fr), + .ck_fr_in(ck_fr_in), + .ck_fr_out(ck_fr_out), + .ck_hr(ck_hr), + .ck_hr_in(ck_hr_in), + .ck_hr_out(ck_hr_out), + .oe(oe_reordered[(i + 1) * OE_SIZE - 1 : i * OE_SIZE]), + .din(din_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]), + .dout(dout_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]), + .pad(pad_io[i]), + .pad_b(pad_io_b[i]), + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .aclr(aclr), + .aset(aset), + .sclr(sclr), + .sset(sset), + .cke(cke) + ); + end + endgenerate + +endmodule diff --git a/intel/sgx-dev/basefiles/IOBUF/altera_gpio_core14_191/synth/altera_gpio.sv b/intel/sgx-dev/basefiles/IOBUF/altera_gpio_core14_191/synth/altera_gpio.sv new file mode 100644 index 00000000..1dc438a1 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/altera_gpio_core14_191/synth/altera_gpio.sv @@ -0,0 +1,691 @@ +// (C) 2001-2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +`timescale 1 ps / 1 ps + +module altera_gpio_one_bit( + ck, + ck_in, + ck_out, + ck_fr, + ck_fr_in, + ck_fr_out, + ck_hr, + ck_hr_in, + ck_hr_out, + oe, + din, + dout, + pad, + pad_b, + seriesterminationcontrol, + parallelterminationcontrol, + aclr, + aset, + sclr, + sset, + cke +); + + parameter PIN_TYPE = "output"; + parameter BUFFER_TYPE = "single-ended"; + parameter PSEUDO_DIFF = "false"; + parameter REGISTER_MODE = "none"; + parameter HALF_RATE = "false"; + parameter SEPARATE_I_O_CLOCKS = "false"; + parameter ARESET_MODE = "none"; + parameter SRESET_MODE = "none"; + parameter BUS_HOLD = "false"; + parameter OPEN_DRAIN = "false"; + parameter ENABLE_CKE = "false"; + parameter ENABLE_OE = "false"; + parameter ENABLE_TERM = "false"; + + localparam OE_SIZE = (HALF_RATE == "true") ? 2 : 1; + localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? + (HALF_RATE == "true") ? + 4 : 2 + : 1; + + input ck; + input ck_in; + input ck_out; + input ck_fr; + input ck_fr_in; + input ck_fr_out; + input ck_hr; + input ck_hr_in; + input ck_hr_out; + input [OE_SIZE - 1:0] oe; + input [DATA_SIZE - 1:0] din; + output [DATA_SIZE - 1:0] dout; + inout pad; + inout pad_b; + input [15:0] seriesterminationcontrol; + input [15:0] parallelterminationcontrol; + input aclr; + input aset; + input sclr; + input sset; + input cke; + + wire hr_out_clk; + wire fr_out_clk; + wire hr_in_clk; + wire fr_in_clk; + + wire din_ddr; + wire buf_in; + + wire areset; + wire sreset; + + generate + if(ARESET_MODE == "preset") begin + assign areset = ~aset; + end + else begin + assign areset = ~aclr; + end + endgenerate + + generate + if(SRESET_MODE == "preset") begin + assign sreset = sset; + end + else begin + assign sreset = sclr; + end + endgenerate + + generate + if(SEPARATE_I_O_CLOCKS == "true") + begin + if(HALF_RATE == "true") begin + assign hr_out_clk = ck_hr_out; + assign fr_out_clk = ck_fr_out; + assign hr_in_clk = ck_hr_in; + assign fr_in_clk = ck_fr_in; + end + else begin + assign fr_out_clk = ck_out; + assign fr_in_clk = ck_in; + end + end + else begin + if(HALF_RATE == "true") begin + assign hr_out_clk = ck_hr; + assign fr_out_clk = ck_fr; + assign hr_in_clk = ck_hr; + assign fr_in_clk = ck_fr; + end + else begin + assign fr_out_clk = ck; + assign fr_in_clk = ck; + end + end + endgenerate + + generate + if (PIN_TYPE == "output" || PIN_TYPE == "bidir") + begin: out_path + wire [1:0] din_fr; + + if (HALF_RATE == "true") + begin: out_path_hr + fourteennm_ddio_out + #( + .half_rate_mode("true"), + .async_mode(ARESET_MODE) + ) iodout_hr_ddio_0 ( + .areset(areset), + .datainhi(din[2]), + .datainlo(din[0]), + .dataout(din_fr[0]), + .clk (hr_out_clk) + ); + + fourteennm_ddio_out + #( + .half_rate_mode("true"), + .async_mode(ARESET_MODE) + ) iodout_hr_ddio_1 ( + .areset(areset), + .datainhi(din[3]), + .datainlo(din[1]), + .dataout(din_fr[1]), + .clk (hr_out_clk) + ); + end + else + begin: out_path_hr_byp + assign din_fr[DATA_SIZE - 1:0] = din; + end + + if (REGISTER_MODE == "ddr") + begin: out_path_fr + fourteennm_ddio_out + #( + .half_rate_mode("false"), + .async_mode(ARESET_MODE), + .sync_mode(SRESET_MODE) + ) fr_out_data_ddio ( + .ena(cke), + .areset(areset), + .sreset(sreset), + .datainhi(din_fr[1]), + .datainlo(din_fr[0]), + .dataout(din_ddr), + .clk (fr_out_clk) + ); + end + else if (REGISTER_MODE == "sdr") + begin: out_path_reg + reg reg_data_out; + always @(posedge fr_out_clk) + reg_data_out <= din_fr[0]; + + assign din_ddr = reg_data_out; + end + else + begin: out_path_byp + assign din_ddr = din_fr[0]; + end + end + endgenerate + + generate + wire oe_fr; + wire oe_ddr; + + if (PIN_TYPE == "bidir" || ENABLE_OE == "true") + begin: oe_path + if (HALF_RATE == "true") + begin: oe_path_hr + fourteennm_ddio_out + #( + .half_rate_mode("true") + ) oe_in_hr_ddio ( + .datainhi(oe[1]), + .datainlo(oe[0]), + .dataout(oe_fr), + .clk (hr_out_clk) + ); + end + else + begin: oe_path_hr_byp + assign oe_fr = oe[0]; + end + + if (REGISTER_MODE == "sdr" || REGISTER_MODE == "ddr") + begin: oe_path_fr + reg oe_reg; + always @(posedge fr_out_clk) oe_reg <= oe_fr; + assign oe_ddr = oe_reg; + end + else + begin: oe_path_byp + assign oe_ddr = oe_fr; + end + end + else if (PIN_TYPE == "output") + begin + assign oe_ddr = 1'b1; + end + else + begin + assign oe_ddr = 1'b0; + end + endgenerate + + generate + if (PIN_TYPE == "input" || PIN_TYPE == "bidir") + begin : input_path + wire [1:0] buf_in_fr; + + if (REGISTER_MODE == "ddr") + begin: in_path_fr + fourteennm_ddio_in + #( + .async_mode(ARESET_MODE), + .sync_mode(SRESET_MODE) + ) buffer_data_in_fr_ddio ( + .ena(cke), + .areset(areset), + .sreset(sreset), + .datain(buf_in), + .clk (fr_in_clk), + .regouthi(buf_in_fr[1]), + .regoutlo(buf_in_fr[0]) + ); + end + else if (REGISTER_MODE == "sdr") + begin: in_path_reg + reg ro; + always @(posedge fr_in_clk) begin + ro <= buf_in; + end + assign buf_in_fr[0] = ro; + end + else + begin: in_byp + assign buf_in_fr[0] = buf_in; + end + + if (HALF_RATE == "true") + begin: in_path_hr + fourteennm_ddio_in + #( + .async_mode(ARESET_MODE), + .sync_mode("none") + ) buffer_data_in_hr_ddio_0 ( + .areset(areset), + .datain(buf_in_fr[0]), + .clk (hr_in_clk), + .regouthi(dout[2]), + .regoutlo(dout[0]) + ); + + fourteennm_ddio_in + #( + .async_mode(ARESET_MODE), + .sync_mode("none") + ) buffer_data_in_hr_ddio_1 ( + .areset(areset), + .datain(buf_in_fr[1]), + .clk (hr_in_clk), + .regouthi(dout[3]), + .regoutlo(dout[1]) + ); + end + else + begin: in_path_hr_byp + assign dout[DATA_SIZE - 1:0] = buf_in_fr[DATA_SIZE - 1:0]; + end + end + endgenerate + + generate + if (PIN_TYPE == "output" || PIN_TYPE == "bidir") + begin : output_buffer + if(BUFFER_TYPE == "differential") begin + wire obuf_din; + wire obuf_din_b; + wire obuf_oe; + wire obuf_oe_b; + + if(PSEUDO_DIFF == "true") begin + if (PIN_TYPE == "output" && ENABLE_OE == "false") + begin : oe_path + fourteennm_pseudo_diff_out pseudo_diff_out( + .i(din_ddr), + .o(obuf_din), + .obar(obuf_din_b) + ); + + if (ENABLE_TERM == "true") begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .i(obuf_din), + .o(pad) + ); + + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_1 ( + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .i(obuf_din_b), + .o(pad_b) + ); + end + else begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .i(obuf_din), + .o(pad) + ); + + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_1 ( + .i(obuf_din_b), + .o(pad_b) + ); + end + end + else begin + fourteennm_pseudo_diff_out pseudo_diff_out( + .i(din_ddr), + .o(obuf_din), + .obar(obuf_din_b), + .oein(oe_ddr), + .oeout(obuf_oe), + .oebout(obuf_oe_b) + ); + if (ENABLE_TERM == "true") begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .i(obuf_din), + .oe(obuf_oe), + .o(pad) + ); + + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_1 ( + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .i(obuf_din_b), + .oe(obuf_oe_b), + .o(pad_b) + ); + end + else begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .i(obuf_din), + .oe(obuf_oe), + .o(pad) + ); + + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_1 ( + .i(obuf_din_b), + .oe(obuf_oe_b), + .o(pad_b) + ); + end + end + end + else begin + if (ENABLE_TERM == "true") begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .i(din_ddr), + .oe(oe_ddr), + .o(pad), + .obar(pad_b) + ); + end + else begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf_0 ( + .i(din_ddr), + .oe(oe_ddr), + .o(pad), + .obar(pad_b) + ); + end + + end + end + else begin + if (ENABLE_TERM == "true") begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf ( + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .i(din_ddr), + .oe(oe_ddr), + .o(pad) + ); + end + else begin + fourteennm_io_obuf #( + .open_drain_output(OPEN_DRAIN), + .bus_hold(BUS_HOLD) + ) obuf ( + .i(din_ddr), + .oe(oe_ddr), + .o(pad) + ); + end + end + end + endgenerate + + generate + if (PIN_TYPE == "input" || PIN_TYPE == "bidir") + begin : input_buffer + if(BUFFER_TYPE == "differential") begin + if (ENABLE_TERM == "true") begin + fourteennm_io_ibuf + #( + .differential_mode("true"), + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .ibar(pad_b), + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .o(buf_in) + ); + end + else begin + fourteennm_io_ibuf + #( + .differential_mode("true"), + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .ibar(pad_b), + .o(buf_in) + ); + end + end + else begin + if (ENABLE_TERM == "true") begin + fourteennm_io_ibuf + #( + .differential_mode("false"), + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .o(buf_in) + ); + end + else begin + fourteennm_io_ibuf + #( + .differential_mode("false"), + .bus_hold(BUS_HOLD) + ) ibuf ( + .i(pad), + .o(buf_in) + ); + end + end + end + endgenerate + +endmodule + +module altera_gpio( + ck, + ck_in, + ck_out, + ck_fr, + ck_fr_in, + ck_fr_out, + ck_hr, + ck_hr_in, + ck_hr_out, + oe, + din, + dout, + pad_io, + pad_io_b, + pad_in, + pad_in_b, + pad_out, + pad_out_b, + seriesterminationcontrol, + parallelterminationcontrol, + aclr, + aset, + sclr, + sset, + cke +); + + parameter PIN_TYPE = "output"; + parameter BUFFER_TYPE = "single-ended"; + parameter PSEUDO_DIFF = "false"; + parameter REGISTER_MODE = "none"; + parameter HALF_RATE = "false"; + parameter SEPARATE_I_O_CLOCKS = "false"; + parameter SIZE = 4; + parameter ARESET_MODE = "none"; + parameter SRESET_MODE = "none"; + parameter BUS_HOLD = "false"; + parameter OPEN_DRAIN = "false"; + parameter ENABLE_CKE = "false"; + parameter ENABLE_OE = "false"; + parameter ENABLE_TERM = "false"; + + localparam OE_SIZE = (HALF_RATE == "true") ? 2 : 1; + localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? + (HALF_RATE == "true") ? + 4 : 2 + : 1; + + input ck; + input ck_in; + input ck_out; + input ck_fr; + input ck_fr_in; + input ck_fr_out; + input ck_hr; + input ck_hr_in; + input ck_hr_out; + input [SIZE * OE_SIZE - 1:0] oe; + input [SIZE * DATA_SIZE - 1:0] din; + output [SIZE * DATA_SIZE - 1:0] dout; + input [15:0] seriesterminationcontrol; + input [15:0] parallelterminationcontrol; + inout [SIZE - 1:0] pad_io; + inout [SIZE - 1:0] pad_io_b; + input [SIZE - 1:0] pad_in; + input [SIZE - 1:0] pad_in_b; + output [SIZE - 1:0] pad_out; + output [SIZE - 1:0] pad_out_b; + input aclr; + input aset; + input sclr; + input sset; + input cke; + + wire [SIZE * OE_SIZE - 1:0] oe_reordered; + wire [SIZE * DATA_SIZE - 1:0] din_reordered; + wire [SIZE * DATA_SIZE - 1:0] dout_reordered; + wire [SIZE - 1:0] pad_io; + wire [SIZE - 1:0] pad_io_b; + + generate + if (PIN_TYPE == "input") + begin + assign pad_io = pad_in; + assign pad_io_b = pad_in_b; + end + else if (PIN_TYPE == "output") + begin + assign pad_out = pad_io; + assign pad_out_b = pad_io_b; + end + endgenerate + + genvar j, k; + generate + for(j = 0; j < SIZE ; j = j + 1) begin : j_loop + for(k = 0; k < DATA_SIZE; k = k + 1) begin : k_d_loop + assign din_reordered[j * DATA_SIZE + k] = din[j + k * SIZE]; + assign dout[j + k * SIZE] = dout_reordered[j * DATA_SIZE + k]; + end + for(k = 0; k < OE_SIZE; k = k + 1) begin : k_oe_loop + assign oe_reordered[j * OE_SIZE + k] = oe[j + k * SIZE]; + end + end + endgenerate + + genvar i; + generate + for(i = 0 ; i < SIZE ; i = i + 1) begin : i_loop + altera_gpio_one_bit #( + .PIN_TYPE(PIN_TYPE), + .BUFFER_TYPE(BUFFER_TYPE), + .PSEUDO_DIFF(PSEUDO_DIFF), + .REGISTER_MODE(REGISTER_MODE), + .HALF_RATE(HALF_RATE), + .SEPARATE_I_O_CLOCKS(SEPARATE_I_O_CLOCKS), + .ARESET_MODE(ARESET_MODE), + .SRESET_MODE(SRESET_MODE), + .BUS_HOLD(BUS_HOLD), + .OPEN_DRAIN(OPEN_DRAIN), + .ENABLE_CKE(ENABLE_CKE), + .ENABLE_OE(ENABLE_OE), + .ENABLE_TERM(ENABLE_TERM) + ) altera_gpio_bit_i ( + .ck(ck), + .ck_in(ck_in), + .ck_out(ck_out), + .ck_fr(ck_fr), + .ck_fr_in(ck_fr_in), + .ck_fr_out(ck_fr_out), + .ck_hr(ck_hr), + .ck_hr_in(ck_hr_in), + .ck_hr_out(ck_hr_out), + .oe(oe_reordered[(i + 1) * OE_SIZE - 1 : i * OE_SIZE]), + .din(din_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]), + .dout(dout_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]), + .pad(pad_io[i]), + .pad_b(pad_io_b[i]), + .seriesterminationcontrol(seriesterminationcontrol), + .parallelterminationcontrol(parallelterminationcontrol), + .aclr(aclr), + .aset(aset), + .sclr(sclr), + .sset(sset), + .cke(cke) + ); + end + endgenerate + +endmodule diff --git a/intel/sgx-dev/basefiles/IOBUF/sim/IOBUF.v b/intel/sgx-dev/basefiles/IOBUF/sim/IOBUF.v new file mode 100644 index 00000000..e70ef4d5 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/sim/IOBUF.v @@ -0,0 +1,20 @@ +// IOBUF.v + +// Generated using ACDS version 20.2 50 + +`timescale 1 ps / 1 ps +module IOBUF ( + output wire [0:0] dataout, // dout.export + input wire [0:0] datain, // din.export + input wire [0:0] oe, // oe.export + inout wire [0:0] padio // pad_io.export + ); + + IOBUF_altera_gpio_1930_alkbnhy gpio_0 ( + .dataout (dataout), // output, width = 1, dout.export + .datain (datain), // input, width = 1, din.export + .oe (oe), // input, width = 1, oe.export + .padio (padio) // inout, width = 1, pad_io.export + ); + +endmodule diff --git a/intel/sgx-dev/basefiles/IOBUF/sim/aldec/rivierapro_setup.tcl b/intel/sgx-dev/basefiles/IOBUF/sim/aldec/rivierapro_setup.tcl new file mode 100644 index 00000000..c41d32c3 --- /dev/null +++ b/intel/sgx-dev/basefiles/IOBUF/sim/aldec/rivierapro_setup.tcl @@ -0,0 +1,343 @@ + +# (C) 2001-2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Intel +# Program License Subscription Agreement, Intel MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Intel and sold by Intel +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ACDS 20.2 50 linux 2020.07.29.10:13:25 +# ---------------------------------------- +# Auto-generated simulation script rivierapro_setup.tcl +# ---------------------------------------- +# This script provides commands to simulate the following IP detected in +# your Quartus project: +# IOBUF +# +# Intel recommends that you source this Quartus-generated IP simulation +# script from your own customized top-level script, and avoid editing this +# generated script. +# +# To write a top-level script that compiles Intel simulation libraries and +# the Quartus-generated IP in your project, along with your design and +# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below +# into a new file, e.g. named "aldec.do", and modify the text as directed. +# +# ---------------------------------------- +# # TOP-LEVEL TEMPLATE - BEGIN +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +# set QSYS_SIMDIR