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OpenCL_Xilinx-Intel_HeteroCL

This is a repo which contains some details for HeteroCL developers and how to use OpenCL backend (Xilinx/Intel) to test the samples in HeteroCL.

HeteroCL(FPGA'19 Best Paper Award!)

If you do not know HeteroCL, you can figure it out through this link. It is an open source project developed by Computer Systems Lab, Zhang-Group

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Introduction

  • I add the OpenCL backend for HeteroCL ( Xilinx & Intel ), which can be found in this branch.

  • If you want to use HeteroCL to generate Vivado HLS C++ code and then wrapper it into the OpenCL host file run on the AWS, you can use this branch.

Major features

  • Loop Unrolling
  • Loop Pipelining
  • Pratition for Xilinx
  • Arbitrary Precision Integers for Intel
  • Runtime System:
    • OpenCL C API for Intel (AOCL)
    • OpenCL C++ Wrapper API for Xilinx (SDAccel)
    • Rosetta for AWS

Updates

Installation

Please refer to INSTALL.md for installation and environment preparation.

Get Started

Please see GETTING_STARTED.md for the basic usage of HeteroCL OpenCL backend.

Technical Report

Please see TECHNICAL_DETAILS.md for learning how to add FPGA backend (Code Generation and Runtime) for HeteroCL.

Support

If you like this repo and find it useful, please consider (★) starring it, so that it can reach broader developers.

Acknowledgement

This work had been done when I was an Intern at Cornell University (Computer Systems Lab).