[BOLT] Fix typos (llvm#68121)

Closes llvm#63097

Before merging please make sure the change to
bolt/include/bolt/Passes/StokeInfo.h is correct.

bolt/include/bolt/Passes/StokeInfo.h

```diff
  //  This Pass solves the two major problems to use the Stoke program without
- //  proting its code:
+ //  probing its code:
```

I'm still not happy about the awkward wording in this comment.

bolt/include/bolt/Passes/FixRelaxationPass.h

```
$ ed -s bolt/include/bolt/Passes/FixRelaxationPass.h <<<'9,12p'
// This file declares the FixRelaxations class, which locates instructions with
// wrong targets and fixes them. Such problems usually occures when linker
// relaxes (changes) instructions, but doesn't fix relocations types properly
// for them.
$
```


bolt/docs/doxygen.cfg.in
bolt/include/bolt/Core/BinaryContext.h
bolt/include/bolt/Core/BinaryFunction.h
bolt/include/bolt/Core/BinarySection.h
bolt/include/bolt/Core/DebugData.h
bolt/include/bolt/Core/DynoStats.h
bolt/include/bolt/Core/Exceptions.h
bolt/include/bolt/Core/MCPlusBuilder.h
bolt/include/bolt/Core/Relocation.h
bolt/include/bolt/Passes/FixRelaxationPass.h
bolt/include/bolt/Passes/InstrumentationSummary.h
bolt/include/bolt/Passes/ReorderAlgorithm.h
bolt/include/bolt/Passes/StackReachingUses.h
bolt/include/bolt/Passes/StokeInfo.h
bolt/include/bolt/Passes/TailDuplication.h
bolt/include/bolt/Profile/DataAggregator.h
bolt/include/bolt/Profile/DataReader.h
bolt/lib/Core/BinaryContext.cpp
bolt/lib/Core/BinarySection.cpp
bolt/lib/Core/DebugData.cpp
bolt/lib/Core/DynoStats.cpp
bolt/lib/Core/Relocation.cpp
bolt/lib/Passes/Instrumentation.cpp
bolt/lib/Passes/JTFootprintReduction.cpp
bolt/lib/Passes/ReorderData.cpp
bolt/lib/Passes/RetpolineInsertion.cpp
bolt/lib/Passes/ShrinkWrapping.cpp
bolt/lib/Passes/TailDuplication.cpp
bolt/lib/Rewrite/BoltDiff.cpp
bolt/lib/Rewrite/DWARFRewriter.cpp
bolt/lib/Rewrite/RewriteInstance.cpp
bolt/lib/Utils/CommandLineOpts.cpp
bolt/runtime/instr.cpp
bolt/test/AArch64/got-ld64-relaxation.test
bolt/test/AArch64/unmarked-data.test
bolt/test/X86/Inputs/dwarf5-cu-no-debug-addr-helper.s
bolt/test/X86/Inputs/linenumber.cpp
bolt/test/X86/double-jump.test
bolt/test/X86/dwarf5-call-pc-function-null-check.test
bolt/test/X86/dwarf5-split-dwarf4-monolithic.test
bolt/test/X86/dynrelocs.s
bolt/test/X86/fallthrough-to-noop.test
bolt/test/X86/tail-duplication-cache.s
bolt/test/runtime/X86/instrumentation-ind-calls.s

bolt/docs/doxygen.cfg.in

@@ -1954,7 +1954,7 @@ PREDEFINED             =
 EXPAND_AS_DEFINED      =
 
 # If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will
-# remove all refrences to function-like macros that are alone on a line, have an
+# remove all references to function-like macros that are alone on a line, have an
 # all uppercase name, and do not end with a semicolon. Such function macros are
 # typically used for boiler-plate code, and will confuse the parser if not
 # removed.

bolt/include/bolt/Core/BinaryContext.h

@@ -950,7 +950,7 @@ class BinaryContext {
   bool registerFragment(BinaryFunction &TargetFunction,
                         BinaryFunction &Function) const;
 
-  /// Add unterprocedural reference for \p Function to \p Address
+  /// Add interprocedural reference for \p Function to \p Address
   void addInterproceduralReference(BinaryFunction *Function, uint64_t Address) {
     InterproceduralReferences.push_back({Function, Address});
   }

bolt/include/bolt/Core/BinaryFunction.h

@@ -2172,7 +2172,7 @@ class BinaryFunction {
   /// is corrupted. If it is unable to fix it, it returns false.
   bool finalizeCFIState();
 
-  /// Return true if this function needs an address-transaltion table after
+  /// Return true if this function needs an address-translation table after
   /// its code emission.
   bool requiresAddressTranslation() const;
 

bolt/include/bolt/Core/BinarySection.h

@@ -127,7 +127,7 @@ class BinarySection {
     return *ContentsOrErr;
   }
 
-  /// Get the set of relocations refering to data in this section that
+  /// Get the set of relocations referring to data in this section that
   /// has been reordered.  The relocation offsets will be modified to
   /// reflect the new data locations.
   RelocationSetType reorderRelocations(bool Inplace) const;

bolt/include/bolt/Core/DebugData.h

@@ -64,7 +64,7 @@ std::optional<AttrInfo> findAttributeInfo(const DWARFDie DIE,
                                           dwarf::Attribute Attr);
 
 // DWARF5 Header in order of encoding.
-// Types represent encodnig sizes.
+// Types represent encoding sizes.
 using UnitLengthType = uint32_t;
 using VersionType = uint16_t;
 using AddressSizeType = uint8_t;
@@ -372,13 +372,13 @@ class DebugAddrWriter {
     }
 
     /// Updates AddressToIndex Map.
-    /// Follows the same symantics as unordered map [].
+    /// Follows the same semantics as unordered map [].
     void updateAddressToIndex(uint64_t Address, uint32_t Index) {
       AddressToIndex[Address] = Index;
     }
 
     /// Updates IndexToAddress Map.
-    /// Follows the same symantics as unordered map [].
+    /// Follows the same semantics as unordered map [].
     void updateIndexToAddrss(uint64_t Address, uint32_t Index) {
       IndexToAddress[Index] = Address;
     }
@@ -474,7 +474,7 @@ class DebugStrWriter {
   }
 
   /// Adds string to .debug_str.
-  /// On first invokation it initializes internal data stractures.
+  /// On first invocation it initializes internal data structures.
   uint32_t addString(StringRef Str);
 
   /// Returns False if no strings were added to .debug_str.
@@ -485,7 +485,7 @@ class DebugStrWriter {
   std::mutex WriterMutex;
   /// Initializes Buffer and Stream.
   void initialize();
-  /// Creats internal data stractures.
+  /// Creates internal data structures.
   void create();
   std::unique_ptr<DebugStrBufferVector> StrBuffer;
   std::unique_ptr<raw_svector_ostream> StrStream;
@@ -585,7 +585,7 @@ class DebugLoclistWriter : public DebugLocWriter {
   void finalize(DIEBuilder &DIEBldr, DIE &Die) override;
 
   /// Returns CU ID.
-  /// For Skelton CU it is a CU Offset.
+  /// For Skeleton CU it is a CU Offset.
   /// For DWO CU it is a DWO ID.
   uint64_t getCUID() const {
     return CU.isDWOUnit() ? *CU.getDWOId() : CU.getOffset();

bolt/include/bolt/Core/DynoStats.h

@@ -121,7 +121,7 @@ class DynoStats {
   /// Maps instruction opcodes to:
   /// 1. Accumulated executed instruction counts.
   /// 2. a multimap that records highest execution counts, function names,
-  /// and BB offsets where intructions of these opcodes occur.
+  /// and BB offsets where instructions of these opcodes occur.
   using MaxOpcodeHistogramTy =
       std::multimap<uint64_t, std::pair<StringRef, uint32_t>>;
   using OpcodeHistogramTy =

bolt/include/bolt/Core/Exceptions.h

@@ -77,7 +77,7 @@ class EHFrameParser {
   ///   void PatcherCallback(uint64_t Value, uint64_t Offset, uint64_t Type);
   ///
   /// where Value is a value of the reference, Offset - is an offset into the
-  /// frame data at which the reference occured, and Type is a DWARF encoding
+  /// frame data at which the reference occurred, and Type is a DWARF encoding
   /// type of the reference.
   static Error parse(DWARFDataExtractor Data, uint64_t EHFrameAddress,
                      PatcherCallbackTy PatcherCallback);

bolt/include/bolt/Core/MCPlusBuilder.h

@@ -1082,7 +1082,7 @@ class MCPlusBuilder {
 
   /// Replace the compound memory operand of Inst with an immediate operand.
   /// The value of the immediate operand is computed by reading the \p
-  /// ConstantData array starting from \p offset and assuming little-endianess.
+  /// ConstantData array starting from \p offset and assuming little-endianness.
   /// Return true on success. The given instruction is modified in place.
   virtual bool replaceMemOperandWithImm(MCInst &Inst, StringRef ConstantData,
                                         uint64_t Offset) const {

bolt/include/bolt/Core/Relocation.h

@@ -61,7 +61,7 @@ struct Relocation {
 
   /// Handle special cases when relocation should not be processed by BOLT or
   /// change relocation \p Type to proper one before continuing if \p Contents
-  /// and \P Type mismatch occured.
+  /// and \P Type mismatch occurred.
   static bool skipRelocationProcess(uint64_t &Type, uint64_t Contents);
 
   // Adjust value depending on relocation type (make it PC relative or not)

bolt/include/bolt/Passes/FixRelaxationPass.h

@@ -7,7 +7,7 @@
 //===----------------------------------------------------------------------===//
 //
 // This file declares the FixRelaxations class, which locates instructions with
-// wrong targets and fixes them. Such problems usually occures when linker
+// wrong targets and fixes them. Such problems usually occurs when linker
 // relaxes (changes) instructions, but doesn't fix relocations types properly
 // for them.
 //

bolt/include/bolt/Passes/InstrumentationSummary.h

@@ -35,7 +35,7 @@ class BinaryFunction;
 // counters. It also provides function names and offsets used when writing the
 // fdata file.
 
-// Location information -- analoguous to the concept of the same name in fdata
+// Location information -- analogous to the concept of the same name in fdata
 // writing/reading. The difference is that the name is stored as an index to a
 // string table written separately.
 struct LocDescription {

bolt/include/bolt/Passes/ReorderAlgorithm.h

@@ -42,7 +42,7 @@ class ClusterAlgorithm {
   virtual void clusterBasicBlocks(BinaryFunction &BF,
                                   bool ComputeEdges = false) = 0;
 
-  /// Compute for each cluster its averagae execution frequency, that is
+  /// Compute for each cluster its average execution frequency, that is
   /// the sum of average frequencies of its blocks (execution count / # instrs).
   /// The average frequencies are stored in the AvgFreq vector, index by the
   /// cluster indices in the Clusters vector.
@@ -128,7 +128,7 @@ class MinBranchGreedyClusterAlgorithm : public GreedyClusterAlgorithm {
   //  A -> B with execution count 500,
   //  A -> C with execution count 100, and
   //  D -> B with execution count 150
-  // wher B, C are the only successors of A and A, D are thr only predessecors
+  // where B, C are the only successors of A and A, D are the only predecessors
   // of B. Then if we choose to layout edge A -> B as a fallthrough, the win in
   // branches would be 500 - 100 - 150 = 250. That is the weight of edge A->B.
   int64_t calculateWeight(const EdgeTy &E, const BinaryFunction &BF) const;
@@ -144,8 +144,8 @@ class MinBranchGreedyClusterAlgorithm : public GreedyClusterAlgorithm {
   void reset() override;
 };
 
-/// Objects of this class implement various basic block reordering alogrithms.
-/// Most of these algorithms depend on a clustering alogrithm.
+/// Objects of this class implement various basic block reordering algorithms.
+/// Most of these algorithms depend on a clustering algorithm.
 /// Here we have 3 conflicting goals as to how to layout clusters. If we want
 /// to minimize jump offsets, we should put clusters with heavy inter-cluster
 /// dependence as close as possible. If we want to maximize the probability

bolt/include/bolt/Passes/StackReachingUses.h

@@ -41,7 +41,7 @@ class StackReachingUses
   /// Answer whether the stack position written by the store represented in
   /// \p StoreFIE is loaded from or consumed in any way. The set of all
   /// relevant expressions reaching this store should be in \p Candidates.
-  /// If \p IncludelocalAccesses is false, we only consider wheter there is
+  /// If \p IncludelocalAccesses is false, we only consider whether there is
   /// a callee that consumes this stack position.
   bool isStoreUsed(const FrameIndexEntry &StoreFIE, ExprIterator Candidates,
                    bool IncludeLocalAccesses = true) const;

bolt/include/bolt/Passes/StokeInfo.h

@@ -9,7 +9,7 @@
 //  Pass to get information for functions for the Stoke Optimization
 //  To use the Stoke optimization technique to optimize the HHVM.
 //  This Pass solves the two major problems to use the Stoke program without
-//  proting its code:
+//  probing its code:
 //
 //  1. Stoke works on function level, but it is only limited to relative
 //  small functions which are loop-free, call-free, exception-free, etc.

bolt/include/bolt/Passes/TailDuplication.h

@@ -81,7 +81,7 @@ class TailDuplication : public BinaryFunctionPass {
   /// Returns true if Reg is used by Inst
   bool regIsUsed(const MCInst &Inst, unsigned Reg, BinaryContext &BC) const;
 
-  /// Returns true if Reg is overwritten before its used by StartBB's sucessors
+  /// Returns true if Reg is overwritten before its used by StartBB's successors
   bool isOverwrittenBeforeUsed(BinaryBasicBlock &StartBB, unsigned Reg) const;
 
   /// Constant and Copy Propagate for the block formed by OriginalBB and

bolt/include/bolt/Profile/DataAggregator.h

@@ -301,7 +301,7 @@ class DataAggregator : public DataReader {
   ErrorOr<AggregatedLBREntry> parseAggregatedLBREntry();
 
   /// Parse either buildid:offset or just offset, representing a location in the
-  /// binary. Used exclusevely for pre-aggregated LBR samples.
+  /// binary. Used exclusively for pre-aggregated LBR samples.
   ErrorOr<Location> parseLocationOrOffset();
 
   /// Check if a field separator is the next char to parse and, if yes, consume

bolt/include/bolt/Profile/DataReader.h

@@ -350,9 +350,9 @@ class DataReader : public ProfileReaderBase {
   ///
   /// The examples records branches from local symbol func (from t2.c), offset
   /// 11, to global symbol globalfunc, offset 1d, with 1775 branches, no
-  /// mispreds. Of these branches, 1002 were preceeded by a sequence of
+  /// mispreds. Of these branches, 1002 were preceded by a sequence of
   /// branches from func, offset 18 to offset 20 and then from offset 31 to
-  /// offset d. The rest 773 branches were preceeded by a different sequence
+  /// offset d. The rest 773 branches were preceded by a different sequence
   /// of branches, from func, offset 18 to offset 60 and then from offset 71 to
   /// offset d.
   std::error_code parse();

bolt/lib/Core/BinaryContext.cpp

@@ -1402,7 +1402,7 @@ void BinaryContext::foldFunction(BinaryFunction &ChildBF,
 }
 
 void BinaryContext::fixBinaryDataHoles() {
-  assert(validateObjectNesting() && "object nesting inconsitency detected");
+  assert(validateObjectNesting() && "object nesting inconsistency detected");
 
   for (BinarySection &Section : allocatableSections()) {
     std::vector<std::pair<uint64_t, uint64_t>> Holes;
@@ -1451,7 +1451,7 @@ void BinaryContext::fixBinaryDataHoles() {
     }
   }
 
-  assert(validateObjectNesting() && "object nesting inconsitency detected");
+  assert(validateObjectNesting() && "object nesting inconsistency detected");
   assert(validateHoles() && "top level hole detected in object map");
 }
 
@@ -1796,7 +1796,7 @@ void BinaryContext::printCFI(raw_ostream &OS, const MCCFIInstruction &Inst) {
 MarkerSymType BinaryContext::getMarkerType(const SymbolRef &Symbol) const {
   // For aarch64 and riscv, the ABI defines mapping symbols so we identify data
   // in the code section (see IHI0056B). $x identifies a symbol starting code or
-  // the end of a data chunk inside code, $d indentifies start of data.
+  // the end of a data chunk inside code, $d identifies start of data.
   if ((!isAArch64() && !isRISCV()) || ELFSymbolRef(Symbol).getSize())
     return MarkerSymType::NONE;
 

bolt/lib/Core/BinarySection.cpp

@@ -227,7 +227,7 @@ void BinarySection::print(raw_ostream &OS) const {
 BinarySection::RelocationSetType
 BinarySection::reorderRelocations(bool Inplace) const {
   assert(PendingRelocations.empty() &&
-         "reodering pending relocations not supported");
+         "reordering pending relocations not supported");
   RelocationSetType NewRelocations;
   for (const Relocation &Rel : relocations()) {
     uint64_t RelAddr = Rel.Offset + getAddress();

bolt/lib/Core/DebugData.cpp

@@ -188,7 +188,7 @@ uint64_t DebugRangeListsSectionWriter::addRanges(
 }
 
 struct LocListsRangelistsHeader {
-  UnitLengthType UnitLength; // Size of loclist entris section, not including
+  UnitLengthType UnitLength; // Size of loclist entries section, not including
                              // size of header.
   VersionType Version;
   AddressSizeType AddressSize;
@@ -449,8 +449,8 @@ static void updateAddressBase(DIEBuilder &DIEBlder, DebugAddrWriter &AddrWriter,
 }
 
 void DebugAddrWriter::update(DIEBuilder &DIEBlder, DWARFUnit &CU) {
-  // Handling the case wehre debug information is a mix of Debug fission and
-  // monolitic.
+  // Handling the case where debug information is a mix of Debug fission and
+  // monolithic.
   if (!CU.getDWOId())
     return;
   const uint64_t CUID = getCUID(CU);

bolt/lib/Core/DynoStats.cpp

@@ -136,7 +136,7 @@ void DynoStats::operator+=(const DynoStats &Other) {
     if (I == OpcodeHistogram.end()) {
       OpcodeHistogram.emplace(Stat);
     } else {
-      // Merge Other Historgrams, log only the opts::PrintDynoOpcodeStat'th
+      // Merge other histograms, log only the opts::PrintDynoOpcodeStat'th
       // maximum counts.
       I->second.first += Stat.second.first;
       auto &MMap = I->second.second;

bolt/lib/Core/Relocation.cpp

@@ -295,7 +295,7 @@ static bool skipRelocationProcessAArch64(uint64_t &Type, uint64_t Contents) {
   // changed TLS access model (e.g. changed global dynamic model
   // to initial exec), thus changing the instructions. The static
   // relocations might be invalid at this point and we might no
-  // need to proccess these relocations anymore.
+  // need to process these relocations anymore.
   // More information could be found by searching
   // elfNN_aarch64_tls_relax in bfd
   switch (Type) {
@@ -503,7 +503,7 @@ static uint64_t extractValueAArch64(uint64_t Type, uint64_t Contents,
   case ELF::R_AARCH64_MOVW_UABS_G1:
   case ELF::R_AARCH64_MOVW_UABS_G0_NC:
   case ELF::R_AARCH64_MOVW_UABS_G0:
-    // The shift goest in bits 22:21 of MOV* instructions
+    // The shift goes in bits 22:21 of MOV* instructions
     uint8_t Shift = (Contents >> 21) & 0x3;
     // Immediate goes in bits 20:5
     Contents = (Contents >> 5) & 0xffff;

bolt/lib/Passes/Instrumentation.cpp

@@ -34,7 +34,7 @@ cl::opt<std::string> InstrumentationFilename(
 
 cl::opt<std::string> InstrumentationBinpath(
     "instrumentation-binpath",
-    cl::desc("path to instumented binary in case if /proc/self/map_files "
+    cl::desc("path to instrumented binary in case if /proc/self/map_files "
              "is not accessible due to access restriction issues"),
     cl::Optional, cl::cat(BoltInstrCategory));
 

bolt/lib/Passes/JTFootprintReduction.cpp

@@ -232,7 +232,7 @@ void JTFootprintReduction::optimizeFunction(BinaryFunction &Function,
       continue;
     }
 
-    llvm_unreachable("Should either optimize PIC or NonPIC successfuly");
+    llvm_unreachable("Should either optimize PIC or NonPIC successfully");
   }
 
   if (!Modified.count(&Function))

bolt/lib/Passes/ReorderData.cpp

@@ -11,7 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 // TODO:
-// - make sure writeable data isn't put on same cache line unless temporally
+// - make sure writable data isn't put on same cache line unless temporally
 // local
 // - estimate temporal locality by looking at CFG?
 
@@ -328,7 +328,7 @@ ReorderData::sortedByCount(BinaryContext &BC,
 
 // TODO
 // add option for cache-line alignment (or just use cache-line when section
-// is writeable)?
+// is writable)?
 void ReorderData::setSectionOrder(BinaryContext &BC,
                                   BinarySection &OutputSection,
                                   DataOrder::iterator Begin,

bolt/lib/Passes/RetpolineInsertion.cpp

@@ -52,9 +52,9 @@ cl::opt<RetpolineInsertion::AvailabilityOptions> R11Availability(
     cl::values(clEnumValN(RetpolineInsertion::AvailabilityOptions::NEVER,
                           "never", "r11 not available"),
                clEnumValN(RetpolineInsertion::AvailabilityOptions::ALWAYS,
-                          "always", "r11 avaialable before calls and jumps"),
+                          "always", "r11 available before calls and jumps"),
                clEnumValN(RetpolineInsertion::AvailabilityOptions::ABI, "abi",
-                          "r11 avaialable before calls but not before jumps")),
+                          "r11 available before calls but not before jumps")),
     cl::ZeroOrMore, cl::cat(BoltCategory));
 
 } // namespace opts

bolt/lib/Passes/ShrinkWrapping.cpp

@@ -903,7 +903,7 @@ bool ShrinkWrapping::isBestSavePosCold(unsigned CSR, MCInst *&BestPosSave,
   return true;
 }
 
-/// Auxiliar function used to create basic blocks for critical edges and update
+/// Auxiliary function used to create basic blocks for critical edges and update
 /// the dominance frontier with these new locations
 void ShrinkWrapping::splitFrontierCritEdges(
     BinaryFunction *Func, SmallVector<ProgramPoint, 4> &Frontier,

bolt/lib/Passes/TailDuplication.cpp

@@ -236,7 +236,7 @@ void TailDuplication::constantAndCopyPropagate(
         break;
     }
 
-    // If the register was replaced everwhere and it was overwritten in either
+    // If the register was replaced everywhere and it was overwritten in either
     // one of the iterated through blocks or one of the successor blocks, delete
     // the original move instruction
     if (ReplacedEverywhere &&
@@ -276,7 +276,7 @@ TailDuplication::moderateDuplicate(BinaryBasicBlock &BB,
   // The block must be hot
   if (BB.getKnownExecutionCount() == 0)
     return BlocksToDuplicate;
-  // and its sucessor is not already in the same cache line
+  // and its successor is not already in the same cache line
   if (isInCacheLine(BB, Tail))
     return BlocksToDuplicate;
   // and its size do not exceed the maximum allowed size
@@ -299,7 +299,7 @@ TailDuplication::aggressiveDuplicate(BinaryBasicBlock &BB,
   // The block must be hot
   if (BB.getKnownExecutionCount() == 0)
     return BlocksToDuplicate;
-  // and its sucessor is not already in the same cache line
+  // and its successor is not already in the same cache line
   if (isInCacheLine(BB, Tail))
     return BlocksToDuplicate;
 

bolt/lib/Rewrite/BoltDiff.cpp

@@ -672,7 +672,7 @@ class RewriteInstanceDiff {
 
 };
 
-} // end nampespace bolt
+} // end namespace bolt
 } // end namespace llvm
 
 void RewriteInstance::compare(RewriteInstance &RI2) {