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Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

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Pipeline-Processor

Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

Table of Content

Overview

Following this approach we built our processor incrementally adding small modules every time to run a new instruction type. But how can we gauraentee that runinng new instruction doesn't cause errors in previously implmeneted instructions πŸ™„πŸ™„. Here we thought about the idea πŸ’‘πŸ’‘πŸ’‘ of the Self Checking python script where we saved our previous results and every time we implment new instructions we run all test cases from the beginning to make sure no problem has occured. The new Results are compared to previously tested resukts as comparing text file (for Data memory and Register file). [test.py %NoOfTestCases]

All the above ideas need a too many scripts so a lot of commands are required to be types every time from compiling assembler file to running it for every test case to running modelsim to running python script to drawing reuslted wave to saving results. Too many commands 😱😱😱. At this point we had a brilliant idea 🧨🧨 of running only one batch including all of the above commnads which really helped us a lot in our journy πŸ”οΈπŸοΈ of Design.

One command = Running about 10 commands = Saved Time βŒ› and Effort πŸ€’

Get Started

  1. Clone the repository
    git clone https://github.com/BasmaElhoseny01/Pipeline-Processor.git
    
  2. Make New Folder for your testcase
    cd Phase2/TestCases
    mkdir TestCase%NoOfTestCase
    cd TestCase%NoOfTestCase
    
  3. Put your assembly code in assembly.txt
    type nul > assembly.txt
    
  4. Run All Test Cases :D
    cd ../..
    run.bat %NoOfTestCase
    

Instructions

nop - setc - clrc - not Rdst - inc Rdst - dec Rdst - out Rdst - in Rdst - mov Rsrc Rdst - add Rsrc Rdst - sub Rsrc Rdst - and Rsrc Rdst - or Rsrc Rdst - add Rsrc Rdst - shl immediateValue Rsrc - shr immediateValue Rsrc - push Rdst - pop Rdst - ldm immediateValue Rdst - ldd Rsrc Rdst - std Rdst - jz Rdst - jn Rdst - jc Rdst - jmp Rdst - call Rdst - ret - rti - reset - interrupt

Design

Design

Flow Diagram

Flow Diagram

Demo

2023-02-07.19-41-37.3.mp4

Contributors

Nour Ziad
Nour Ziad
Yasmine Ghanem
Yasmine Ghanem
Ahmed Hosny
Ahmed Hosny
Basma Elhoseny
Basma Elhoseny

License

This software is licensed under MIT License, See License for more information Β©Basma Elhoseny.

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Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

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