Myvar / MyRv32i Public

Educational implementation of Risc-V

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Name		Name	Last commit message	Last commit date
Latest commit History 167 Commits
.github/workflows		.github/workflows
.vscode		.vscode
automation		automation
docs		docs
firmware		firmware
rtl		rtl
run		run
tb		tb
tmp		tmp
top/deo-nano		top/deo-nano
.gitignore		.gitignore
.svlint.toml		.svlint.toml
LICENSE		LICENSE
MyRv32I.drawio		MyRv32I.drawio
README.md		README.md
build_frimware.sh		build_frimware.sh
fpga-run.sh		fpga-run.sh
genrtlsvg.py		genrtlsvg.py
layout.gtkw		layout.gtkw
requirements.txt		requirements.txt
run.sh		run.sh
talk.md		talk.md
talk.py		talk.py
test.bin		test.bin
wave.sh		wave.sh