Add support for UB MNNVL #1470
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Add support for UB MNNVL #1470
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Signed-off-by: Nicolas Castet <[email protected]>
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CC @ptrendx |
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timmoon10
reviewed
Feb 18, 2025
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Overall looks reasonable, although a more detailed PR description would be helpful for understanding your intentions and for future git blames. If I understand correctly, this PR accomplishes two things:
- Register UB buffers with Multi-Node NVLink when possible. This seems straightforward, although we should also handle the case where the TP group is larger than a node and MNNVL is not supported (e.g. by throwing an exception).
- Remove logic for the inter-node communicator. It seems you just delete code without any logic changes, so was the inter-node communicator just dead code? If so, my guess is that it was made redundant in [C/PyTorch] Removed MPI dependence in Userbuffers #901.
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| int datanodes = allnodes / pipenodes / tensornodes; | ||
| int pipenodegroup_id = myrank / numlocal / (datanodes * tensornodes); | ||
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| (*comm)->pipe_id = pipegpus * pipenodegroup_id + mylocal / (datagpus * tensorgpus); | ||
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| (*comm)->comm_inter = EXT_COMM_INTER; | ||
| (*comm)->first_node = nodeid - mynode; | ||
| (*comm)->num_nodes = numnodes; | ||
| (*comm)->my_node = mynode; | ||
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| (*comm)->num2_nodes = tensornodes; | ||
| (*comm)->my2_node = (mynode / datanodes) % tensornodes; | ||
| (*comm)->first2_node = mynode - (*comm)->my2_node * datanodes; | ||
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| (*comm)->fifo = reinterpret_cast<ub_request *>(malloc(sizeof(ub_request) * NVTE_MAX_REQUESTS)); | ||
| (*comm)->nblocks = 8; | ||
| (*comm)->alignblock = 1024 * 512; | ||
| (*comm)->minblock = 1024 * 2 * 1024; | ||
| (*comm)->asyncblocks = 16; |
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If we are not setting these class members, we should remove them from the header file as well.
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/te-ci L1 Looks like we're seeing build errors, I suspect because we're not guarding new CUDA APIs when building with older CUDA versions. |
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Description
Add support for TP across multi-node NVLINK.
Fixes # (issue)
Type of change
Changes
Please list the changes introduced in this PR: