Add MI300 details to docs #446
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start adding MI300 content Signed-off-by: Peter Park <[email protected]>
Signed-off-by: Peter Park <[email protected]>
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docs/conceptual/l2-cache.rst
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| system supports a maximum of two instances. In contrast, the CDNA3-based | ||
| :ref:`MI300 <mixxx-note>` accelerator features 16 channels per XCD, each with a | ||
| capacity of 256KB and also utilizing 256B address interleaving, allowing for a | ||
| total of up to *eight* instances. Incoming requests are mapped to specific L2 |
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total of up to eight instances (one per XCD)
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Updated to this:
...
The L2 cache consists of several distinct channels. The CDNA3-based :ref:MI300 <mixxx-note>
accelerator consists of 16 channels each with a capacity of 256KB and utilizing
256B address interleaving. These channels can operate largely independently and
the system supports up to 8 instances (one per XCD). In constrast, the
:ref:MI200 <mixxx-note> and earlier CDNA accelerators have 32 L2 cache
channels each using 256B address interleaving, but only supports a maximum of 2
instances. ...
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I... think for MI200, at best it would be "up to two instances, one per GCD". And MI100 has 16 channels :P
I forget how we've generally discussed MI200's GCD stuff in these docs, but I think typically we just talk about them like they're entirely separate GPUs.
I would probably do:
The L2 cache consists of several distinct channels. The CDNA3-based :ref:MI300
accelerator consists of 16 channels each with a capacity of 256KB and utilizing
256B address interleaving. These channels can operate largely independently and
the system supports up to 8 total L2 cache instances (one per XCD). In constrast, the
:ref:MI200 CDNA accelerators have 32 L2 cache
channels each using 256B address interleaving, and MI100 CDNA accelerators / GCN GPUs have only 16 L2 Cache channels. ...
cc: @feizheng10 any thoughts?
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Updated c7bc7bd
| .. list-table:: | ||
| :header-rows: 1 | ||
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| * - Feature |
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Table seems weird with just one entry right now, but I'm sure we had ideas on how to fill it :P
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Oh, right, we probably want to (eventually) take a second pass and go through to find places where we distinguish values based on the architecture, like the waveslots discussion below (or AGPRs), and add them here.
That can probably wait till this is ~ finalized though
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This PR updates the documentation with info about the MI300 series
Performance model
L1
UTCL1
L2
Update L2 cache line size to 128B for MI300 (https://advanced-micro-devices-demo--446.com.readthedocs.build/projects/rocprofiler-compute/en/446/conceptual/l2-cache.html#l2-cache-line-size) (128B for MI300 and MI200).
Update channel count in text for MI300 (https://advanced-micro-devices-demo--446.com.readthedocs.build/projects/rocprofiler-compute/en/446/conceptual/l2-cache.html#l2-cache-tcc)
Atomic requests (https://advanced-micro-devices-demo--446.com.readthedocs.build/projects/rocprofiler-compute/en/446/conceptual/l2-cache.html#request-flow)
Add 128B read request metric to table (https://advanced-micro-devices-demo--446.com.readthedocs.build/projects/rocprofiler-compute/en/446/conceptual/l2-cache.html#detailed-transaction-metrics)
VALU
= Add MI300 to list of products with MFMA units (https://advanced-micro-devices-demo--446.com.readthedocs.build/projects/rocprofiler-compute/en/446/conceptual/pipeline-descriptions.html#vector-arithmetic-logic-unit-valu)
AGPRs
Scalar / Instruction cache