2.2.2

Created monolithic source file to ease integration into projects.
Corrected many small errors.

2.2.1

Reduced the size of the core. Reorganized internal microcode

2.2.0

Added support for rv32imc.
Added code to run compliance tests on icebreaker and upduino2.

2.1.0

Added support for rv32im, (“M” Standard Extension for Integer Multiplication and Division, Version 2.0)

Added code for the icebreaker board.

v2.0.3

Corrected cycle counter update when bus-error occurs (a short counter overflowed).
Corrected program that tested retired instruction internal interrupt.
Added test code for several modules.
Minor errors corrected.
Some control signals renamed internally.
Comments enhanced.

v2.0.2

Minor bugfixes. Project now has support for dynamic loading of program files via bit-bang UART.

v2.0.1

Many small bugfixes.

v2.0.0

... and then I changed mapping of system registers.

v1.0.0

Good enough for country music

v0.1.2-bugexpose

When compiling `iceblink40-hx1k.v" in iCECube2 (with Lattice LSE as synthethis tool) the following error occurs in phase 3 of the placer run:

Internal Error: Assumption 'pBInfo->GetDFFGroup() == plBlockInfo::NO_GROUP || mDffGrp == pBInfo->GetDFFGroup()' failed in plCLBCluster.cpp line 368

The error disappears if I remove the placement constraint file. The error only occurs with LAZY_DECODE = 2.

When compiling "iceblink40-hx1k.v" in iCECube2 (with Synplify Pro as synthetis tool) the following error occurs during Verilog compilation:

@E::Signal 011 error in m_generic
Stack trace
===========
0x19d922e
0x19daae0
0x19dac87
0x7f1803e7e38f
0x7f18033166cc
0xa4cbb3
0xa670ee
0x69091f
0x69147e
0xe1c4c5
0x161c107
0x161e1d4
0xe2035b
0xe2298e
0xe54011
0xe63d55
0x43d3e1
Please open a web case about this problem. A Synopsys CAE will then contact you.

These two errors are not related.

Using yosys/arachne-pnr does not give any errors (but note that no lut-chaining placement directive can be given)