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bnossum · Jul 20, 2016 · 72e069b · 72e069b
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 # uart_ice40
-Minimal size uart for ice40 FPGAs, written in Verilog, between 32 or 34 logicCells
+Minimal size uart for ice40 FPGAs, written in Verilog, 32 or 34 logicCells
 
 Simulation has been performed successfully. The uart has been on hardware, but need more testing on hardware.