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added a comment for future: some memory operations must be done atomi…
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…cally

these are include LOCKed RMW of course and also a lot of others
in the future it will be very hard to find all the cases that must be atomic so better to start marking them already now
try to mark every RMW case for atomicity requirements
no code changes, only comments
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Stanislav Shwartsman committed Nov 17, 2023
1 parent 1ad2ee6 commit 0730ff4
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Showing 17 changed files with 67 additions and 76 deletions.
2 changes: 1 addition & 1 deletion bochs/cpu/access2.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1232,7 +1232,7 @@ void BX_CPP_AttrRegparmN(3) BX_CPU_C::shadow_stack_write_qword(bx_address offset

bool BX_CPP_AttrRegparmN(4) BX_CPU_C::shadow_stack_lock_cmpxchg8b(bx_address offset, unsigned curr_pl, Bit64u data, Bit64u expected_data)
{
Bit64u val64 = shadow_stack_read_qword(offset, curr_pl);
Bit64u val64 = shadow_stack_read_qword(offset, curr_pl); // should be locked and RMW
if (val64 == expected_data) {
shadow_stack_write_qword(offset, curr_pl, data);
return true;
Expand Down
8 changes: 4 additions & 4 deletions bochs/cpu/avx/avx512_helpers.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -162,7 +162,7 @@ void BX_CPU_C::avx_masked_store8(bxInstruction_c *i, bx_address eaddr, const BxP
// see if you can successfully write all the elements first
for (int n=BYTE_ELEMENTS(len)-1; n >= 0; n--) {
if (mask & (BX_CONST64(1)<<n))
read_RMW_virtual_byte(i->seg(), eaddr + n);
read_RMW_virtual_byte(i->seg(), eaddr + n); // no lock
}

for (unsigned n=0; n < BYTE_ELEMENTS(len); n++) {
Expand Down Expand Up @@ -195,7 +195,7 @@ void BX_CPU_C::avx_masked_store16(bxInstruction_c *i, bx_address eaddr, const Bx
// see if you can successfully write all the elements first
for (int n=WORD_ELEMENTS(len)-1; n >= 0; n--) {
if (mask & (1<<n))
read_RMW_virtual_word(i->seg(), eaddr + 2*n);
read_RMW_virtual_word(i->seg(), eaddr + 2*n); // no lock
}

for (unsigned n=0; n < WORD_ELEMENTS(len); n++) {
Expand Down Expand Up @@ -232,7 +232,7 @@ void BX_CPU_C::avx_masked_store32(bxInstruction_c *i, bx_address eaddr, const Bx
// see if you can successfully write all the elements first
for (int n=DWORD_ELEMENTS(len)-1; n >= 0; n--) {
if (mask & (1<<n))
read_RMW_virtual_dword(i->seg(), eaddr + 4*n);
read_RMW_virtual_dword(i->seg(), eaddr + 4*n); // no lock
}

for (unsigned n=0; n < DWORD_ELEMENTS(len); n++) {
Expand Down Expand Up @@ -269,7 +269,7 @@ void BX_CPU_C::avx_masked_store64(bxInstruction_c *i, bx_address eaddr, const Bx
// see if you can successfully write all the elements first
for (int n=QWORD_ELEMENTS(len)-1; n >= 0; n--) {
if (mask & (1<<n))
read_RMW_virtual_qword(i->seg(), eaddr + 8*n);
read_RMW_virtual_qword(i->seg(), eaddr + 8*n); // no lock
}

for (unsigned n=0; n < QWORD_ELEMENTS(len); n++) {
Expand Down
4 changes: 2 additions & 2 deletions bochs/cpu/cet.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -238,7 +238,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RSTORSSP(bxInstruction_c *i)

Bit64u previous_ssp_token = SSP | long64_mode() | 0x02;

// should be done atomically
// should be done atomically using RMW
Bit64u SSP_tmp = shadow_stack_read_qword(laddr, CPL); // should be LWSI
if ((SSP_tmp & 0x03) != long64_mode()) {
BX_ERROR(("%s: CS.L of shadow stack token doesn't match or bit1 is not 0", i->getIaOpcodeNameShort()));
Expand All @@ -256,7 +256,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RSTORSSP(bxInstruction_c *i)
exception(BX_CP_EXCEPTION, BX_CP_RSTORSSP);
}
shadow_stack_write_qword(laddr, CPL, previous_ssp_token);
// should be done atomically
// should be done atomically using RMW

SSP = laddr;

Expand Down
32 changes: 16 additions & 16 deletions bochs/cpu/cmpccxadd32.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPBEXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword((get_CF() || get_ZF()) ? op1_32 + op3_32 : op1_32);
Expand All @@ -59,7 +59,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPBXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword(get_CF() ? op1_32 + op3_32 : op1_32);
Expand All @@ -80,7 +80,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPLEXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword((get_ZF() || getB_SF() != getB_OF()) ? op1_32 + op3_32 : op1_32);
Expand All @@ -101,7 +101,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPLXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword((getB_SF() != getB_OF()) ? op1_32 + op3_32 : op1_32);
Expand All @@ -122,7 +122,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNBEXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword((!get_CF() && !get_ZF()) ? op1_32 + op3_32 : op1_32);
Expand All @@ -143,7 +143,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNBXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword(!get_CF() ? op1_32 + op3_32 : op1_32);
Expand All @@ -164,7 +164,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNLEXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword((!get_ZF() && getB_SF() == getB_OF()) ? op1_32 + op3_32 : op1_32);
Expand All @@ -185,7 +185,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNLXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword((getB_SF() == getB_OF()) ? op1_32 + op3_32 : op1_32);
Expand All @@ -206,7 +206,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNOXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword(!get_OF() ? op1_32 + op3_32 : op1_32);
Expand All @@ -227,7 +227,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNPXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword(!get_PF() ? op1_32 + op3_32 : op1_32);
Expand All @@ -248,7 +248,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNSXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword(!get_SF() ? op1_32 + op3_32 : op1_32);
Expand All @@ -269,7 +269,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNZXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword((!get_ZF()) ? op1_32 + op3_32 : op1_32);
Expand All @@ -290,7 +290,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPOXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword(get_OF() ? op1_32 + op3_32 : op1_32);
Expand All @@ -311,7 +311,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPPXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword(get_PF() ? op1_32 + op3_32 : op1_32);
Expand All @@ -332,7 +332,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPSXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword(get_SF() ? op1_32 + op3_32 : op1_32);
Expand All @@ -353,7 +353,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPZXADD_EdGdBd(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr);
Bit32u op1_32 = read_RMW_linear_dword(i->seg(), laddr); // implicit lock
Bit32u diff_32 = op1_32 - op2_32;
SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32);
write_RMW_linear_dword(get_ZF() ? op1_32 + op3_32 : op1_32);
Expand Down
32 changes: 16 additions & 16 deletions bochs/cpu/cmpccxadd64.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPBEXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword((get_CF() || get_ZF()) ? op1_64 + op3_64 : op1_64);
Expand All @@ -59,7 +59,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPBXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword(get_CF() ? op1_64 + op3_64 : op1_64);
Expand All @@ -80,7 +80,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPLEXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword((get_ZF() || getB_SF() != getB_OF()) ? op1_64 + op3_64 : op1_64);
Expand All @@ -101,7 +101,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPLXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword((getB_SF() != getB_OF()) ? op1_64 + op3_64 : op1_64);
Expand All @@ -122,7 +122,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNBEXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword((!get_CF() && !get_ZF()) ? op1_64 + op3_64 : op1_64);
Expand All @@ -143,7 +143,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNBXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword(!get_CF() ? op1_64 + op3_64 : op1_64);
Expand All @@ -164,7 +164,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNLEXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword((!get_ZF() && getB_SF() == getB_OF()) ? op1_64 + op3_64 : op1_64);
Expand All @@ -185,7 +185,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNLXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword((getB_SF() == getB_OF()) ? op1_64 + op3_64 : op1_64);
Expand All @@ -206,7 +206,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNOXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword(!get_OF() ? op1_64 + op3_64 : op1_64);
Expand All @@ -227,7 +227,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNPXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword(!get_PF() ? op1_64 + op3_64 : op1_64);
Expand All @@ -248,7 +248,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNSXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword(!get_SF() ? op1_64 + op3_64 : op1_64);
Expand All @@ -269,7 +269,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPNZXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword((!get_ZF()) ? op1_64 + op3_64 : op1_64);
Expand All @@ -290,7 +290,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPOXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword(get_OF() ? op1_64 + op3_64 : op1_64);
Expand All @@ -311,7 +311,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPPXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword(get_PF() ? op1_64 + op3_64 : op1_64);
Expand All @@ -332,7 +332,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPSXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword(get_SF() ? op1_64 + op3_64 : op1_64);
Expand All @@ -353,7 +353,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPZXADD_EqGqBq(bxInstruction_c *i)
exception(BX_GP_EXCEPTION, 0);
}

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), laddr); // implicit lock
Bit64u diff_64 = op1_64 - op2_64;
SET_FLAGS_OSZAPC_SUB_64(op1_64, op2_64, diff_64);
write_RMW_linear_qword(get_ZF() ? op1_64 + op3_64 : op1_64);
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9 changes: 2 additions & 7 deletions bochs/cpu/data_xfer16.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -201,14 +201,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GwEbR(bxInstruction_c *i)

void BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EwGwM(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;

bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);

op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
op2_16 = BX_READ_16BIT_REG(i->src());

write_RMW_linear_word(op2_16);
Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr); // always locked
write_RMW_linear_word(BX_READ_16BIT_REG(i->src()));
BX_WRITE_16BIT_REG(i->src(), op1_16);

BX_NEXT_INSTR(i);
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6 changes: 2 additions & 4 deletions bochs/cpu/data_xfer32.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -198,10 +198,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GdEwR(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EdGdM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_RESOLVE_ADDR(i);

Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
Bit32u op2_32 = BX_READ_32BIT_REG(i->src());
write_RMW_linear_dword(op2_32);
Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr); // always locked
write_RMW_linear_dword(BX_READ_32BIT_REG(i->src()));
BX_WRITE_32BIT_REGZ(i->src(), op1_32);

BX_NEXT_INSTR(i);
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7 changes: 2 additions & 5 deletions bochs/cpu/data_xfer64.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -292,11 +292,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GqEdR(bxInstruction_c *i)
void BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EqGqM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_RESOLVE_ADDR_64(i);

Bit64u op1_64 = read_RMW_linear_qword(i->seg(), get_laddr64(i->seg(), eaddr));
Bit64u op2_64 = BX_READ_64BIT_REG(i->src());

write_RMW_linear_qword(op2_64);
Bit64u op1_64 = read_RMW_linear_qword(i->seg(), get_laddr64(i->seg(), eaddr)); // always locked
write_RMW_linear_qword(BX_READ_64BIT_REG(i->src()));
BX_WRITE_64BIT_REG(i->src(), op1_64);

BX_NEXT_INSTR(i);
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