initial code for UINTR implementation (#138)

First step into implementing UINTR - User Level Interrupts ISA extension To be continued --------- Co-authored-by: Stanislav Shwartsman <[email protected]>
bochs-emu · Nov 25, 2023 · 280303d · 280303d
1 parent c1c391a
commit 280303d
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Showing 24 changed files with 982 additions and 367 deletions.
diff --git a/bochs/.conf.everything b/bochs/.conf.everything
@@ -20,6 +20,7 @@
   --enable-avx \
   --enable-cet \
   --enable-evex \
+  --enable-uintr \
   --enable-perfmon \
   --enable-memtype \
   --enable-x86-debugger \

diff --git a/bochs/CHANGES b/bochs/CHANGES
@@ -7,6 +7,7 @@ Brief summary :
   - Bugfixes for CPU emulation correctness (MONITOR/MWAIT, VMX/SVM, AVX-512, CET, SHA, GFNI fixes)
   ! Implemented VMX MBE (Mode Based Execution Control) emulation required for Windows 11 guest
   ! Implemented Linear Address Separation (LASS) extension
+  ! Implemented User-Level Interrupt (UINTR) extension
   ! Implemented recently published Intel instruction sets:
     - MOVDIRI, AVX512 BF16, AVX IFMA52, VNNI-INT8, VNNI-INT16, AVX-NE-CONVERT, CMPCCXADD, SM3, SM4, SHA512, WRMSRNS, SERIALIZE
   - Improved 64-bit guest support in Bochs internal debugger, added new internal debugger commands
@@ -29,6 +30,7 @@ Detailed change log :
   - Critical CPU emulation bugfixes for SHA and GFNI instructions
   - Implemented VMX MBE (Mode Based Execution Control) emulation required for Windows 11 guest
   - Implemented Linear Address Separation (LASS) extension
+  - Implemented User-Level Interrupt (UINTR) extension
   - Implemented recently published Intel instruction sets:
     - MOVDIRI, AVX512 BF16, AVX IFMA52, VNNI-INT8, VNNI-INT16, AVX-NE-CONVERT, CMPCCXADD, SM3, SM4, SHA512, WRMSRNS, SERIALIZE
 

diff --git a/bochs/config.h.in b/bochs/config.h.in
@@ -629,6 +629,7 @@ typedef Bit32u bx_phy_address;
 #define BX_SUPPORT_3DNOW 0
 #define BX_SUPPORT_PKEYS 0
 #define BX_SUPPORT_CET 0
+#define BX_SUPPORT_UINTR 0
 #define BX_SUPPORT_MONITOR_MWAIT 0
 #define BX_SUPPORT_PERFMON 0
 #define BX_SUPPORT_MEMTYPE 0
@@ -637,6 +638,10 @@ typedef Bit32u bx_phy_address;
 #define BX_SUPPORT_AVX 0
 #define BX_SUPPORT_EVEX 0
 
+#if BX_SUPPORT_UINTR && BX_SUPPORT_X86_64 == 0
+  #error "UINTR require x86-64 support"
+#endif
+
 #if BX_SUPPORT_SVM && BX_SUPPORT_X86_64 == 0
   #error "SVM require x86-64 support"
 #endif