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added comments and consts for CPUID definitions
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Shwartsman committed Dec 16, 2023
1 parent cd350d8 commit e68ae59
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Showing 3 changed files with 36 additions and 26 deletions.
3 changes: 2 additions & 1 deletion bochs/cpu/cpuid.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1227,7 +1227,8 @@ Bit32u bx_cpuid_t::get_std_cpuid_leaf_7_subleaf_1_edx(Bit32u extra) const

// [13:11] reserved
// [14:14] PREFETCHITI: PREFETCHIT0/T1 instruction
// [16:15] reserved
// [15:15] USER_MSR: support for URDMSR/UWRMSR instructions
// [16:16] reserved
// [17:17] UIRET sets UIF to the RFLAGS[1] image loaded from the stack
// [18:18] CET_SSS

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15 changes: 12 additions & 3 deletions bochs/cpu/cpuid.h
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Original file line number Diff line number Diff line change
Expand Up @@ -596,7 +596,15 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);

// CPUID defines - features CPUID[0x00000007].ECX [subleaf 1]
// -----------------------------
// [31:0] reserved
// [16:0] reserved
// [17:17] FRED support
// [18:18] LKGS instruction
// [31:19] reserved

// ...
#define BX_CPUID_STD7_SUBLEAF1_ECX_FRED (1 << 17)
#define BX_CPUID_STD7_SUBLEAF1_ECX_LKGS (1 << 18)
// ...

// CPUID defines - features CPUID[0x00000007].EDX [subleaf 1]
// -----------------------------
Expand All @@ -609,7 +617,8 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// [10:10] AVX-VNNI-INT16 instructions
// [13:11] reserved
// [14:14] PREFETCHITI: PREFETCHIT0/T1 instruction
// [16:15] reserved
// [15:15] USER_MSR: support for URDMSR/UWRMSR instructions
// [16:16] reserved
// [17:17] UIRET sets UIF to the RFLAGS[1] image loaded from the stack
// [18:18] CET_SSS

Expand All @@ -628,7 +637,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
#define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED12 (1 << 12)
#define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED13 (1 << 13)
#define BX_CPUID_STD7_SUBLEAF1_EDX_PREFETCHI (1 << 14)
#define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED15 (1 << 15)
#define BX_CPUID_STD7_SUBLEAF1_EDX_USER_MSR (1 << 15)
#define BX_CPUID_STD7_SUBLEAF1_EDX_RESERVED16 (1 << 16)
#define BX_CPUID_STD7_SUBLEAF1_EDX_UIRET_UIF (1 << 17)
#define BX_CPUID_STD7_SUBLEAF1_EDX_CET_SSS (1 << 18)
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44 changes: 22 additions & 22 deletions bochs/cpu/decoder/fetchdecode_opmap.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1514,20 +1514,20 @@ static const Bit64u BxOpcodeTable0F01[] = {

form_opcode(ATTR_NNN7 | ATTR_MOD_MEM, BX_IA_INVLPG),

form_opcode(ATTR_NNN0 | ATTR_RRR1 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_VMCALL),
form_opcode(ATTR_NNN0 | ATTR_RRR2 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_VMLAUNCH),
form_opcode(ATTR_NNN0 | ATTR_RRR3 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_VMRESUME),
form_opcode(ATTR_NNN0 | ATTR_RRR4 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_VMXOFF),
form_opcode(ATTR_NNN0 | ATTR_RRR6 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_WRMSRNS),
form_opcode(ATTR_NNN0 | ATTR_RRR1 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_VMCALL), // 0F 01 C1
form_opcode(ATTR_NNN0 | ATTR_RRR2 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_VMLAUNCH), // 0F 01 C2
form_opcode(ATTR_NNN0 | ATTR_RRR3 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_VMRESUME), // 0F 01 C3
form_opcode(ATTR_NNN0 | ATTR_RRR4 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_VMXOFF), // 0F 01 C4
form_opcode(ATTR_NNN0 | ATTR_RRR6 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_WRMSRNS), // 0F 01 C6

form_opcode(ATTR_NNN1 | ATTR_RRR0 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_MONITOR),
form_opcode(ATTR_NNN1 | ATTR_RRR1 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_MWAIT),
form_opcode(ATTR_NNN1 | ATTR_RRR2 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_CLAC),
form_opcode(ATTR_NNN1 | ATTR_RRR3 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_STAC),
form_opcode(ATTR_NNN1 | ATTR_RRR0 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_MONITOR), // 0F 01 C8
form_opcode(ATTR_NNN1 | ATTR_RRR1 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_MWAIT), // 0F 01 C9
form_opcode(ATTR_NNN1 | ATTR_RRR2 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_CLAC), // 0F 01 CA
form_opcode(ATTR_NNN1 | ATTR_RRR3 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_STAC), // 0F 01 CB

form_opcode(ATTR_NNN2 | ATTR_RRR0 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_XGETBV),
form_opcode(ATTR_NNN2 | ATTR_RRR1 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_XSETBV),
form_opcode(ATTR_NNN2 | ATTR_RRR4 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_VMFUNC),
form_opcode(ATTR_NNN2 | ATTR_RRR0 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_XGETBV), // 0F 01 D0
form_opcode(ATTR_NNN2 | ATTR_RRR1 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_XSETBV), // 0F 01 D1
form_opcode(ATTR_NNN2 | ATTR_RRR4 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_VMFUNC), // 0F 01 D4

#if BX_SUPPORT_SVM
form_opcode(ATTR_NNN3 | ATTR_RRR0 | ATTR_MODC0, BX_IA_VMRUN),
Expand All @@ -1540,17 +1540,17 @@ static const Bit64u BxOpcodeTable0F01[] = {
form_opcode(ATTR_NNN3 | ATTR_RRR7 | ATTR_MODC0, BX_IA_INVLPGA),
#endif

form_opcode(ATTR_NNN5 | ATTR_RRR0 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_SERIALIZE),
form_opcode(ATTR_NNN5 | ATTR_RRR0 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_SERIALIZE), // 0F 01 E8

#if BX_SUPPORT_CET
form_opcode(ATTR_NNN5 | ATTR_RRR0 | ATTR_MODC0 | ATTR_SSE_PREFIX_F3, BX_IA_SETSSBSY),
form_opcode(ATTR_NNN5 | ATTR_RRR2 | ATTR_MODC0 | ATTR_SSE_PREFIX_F3, BX_IA_SAVEPREVSSP),
form_opcode(ATTR_NNN5 | ATTR_RRR0 | ATTR_MODC0 | ATTR_SSE_PREFIX_F3, BX_IA_SETSSBSY), // F3 0F 01 E8
form_opcode(ATTR_NNN5 | ATTR_RRR2 | ATTR_MODC0 | ATTR_SSE_PREFIX_F3, BX_IA_SAVEPREVSSP), // F3 0F 01 EA
form_opcode(ATTR_NNN5 | ATTR_MOD_MEM | ATTR_SSE_PREFIX_F3, BX_IA_RSTORSSP),
#endif

#if BX_SUPPORT_PKEYS
form_opcode(ATTR_NNN5 | ATTR_RRR6 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_RDPKRU),
form_opcode(ATTR_NNN5 | ATTR_RRR7 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_WRPKRU),
form_opcode(ATTR_NNN5 | ATTR_RRR6 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_RDPKRU), // 0F 01 EE
form_opcode(ATTR_NNN5 | ATTR_RRR7 | ATTR_MODC0 | ATTR_SSE_NO_PREFIX, BX_IA_WRPKRU), // 0F 01 EF
#endif

#if BX_SUPPORT_UINTR && BX_SUPPORT_X86_64
Expand All @@ -1561,12 +1561,12 @@ static const Bit64u BxOpcodeTable0F01[] = {
#endif

#if BX_SUPPORT_X86_64
form_opcode(ATTR_NNN7 | ATTR_RRR0 | ATTR_MODC0 | ATTR_IS64, BX_IA_SWAPGS),
form_opcode(ATTR_NNN7 | ATTR_RRR0 | ATTR_MODC0 | ATTR_IS64, BX_IA_SWAPGS), // 0F 01 F8
#endif
form_opcode(ATTR_NNN7 | ATTR_RRR1 | ATTR_MODC0, BX_IA_RDTSCP),
form_opcode(ATTR_NNN7 | ATTR_RRR2 | ATTR_MODC0, BX_IA_MONITORX),
form_opcode(ATTR_NNN7 | ATTR_RRR3 | ATTR_MODC0, BX_IA_MWAITX),
last_opcode(ATTR_NNN7 | ATTR_RRR4 | ATTR_MODC0, BX_IA_CLZERO)
form_opcode(ATTR_NNN7 | ATTR_RRR1 | ATTR_MODC0, BX_IA_RDTSCP), // 0F 01 F9
form_opcode(ATTR_NNN7 | ATTR_RRR2 | ATTR_MODC0, BX_IA_MONITORX), // 0F 01 FA
form_opcode(ATTR_NNN7 | ATTR_RRR3 | ATTR_MODC0, BX_IA_MWAITX), // 0F 01 FB
last_opcode(ATTR_NNN7 | ATTR_RRR4 | ATTR_MODC0, BX_IA_CLZERO) // 0F 01 FC
};

// opcode 0F 02
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