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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.2k 616

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.4k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.5k 225

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

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  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 851 224

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 738 178

Repositories

Showing 10 of 109 repositories
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,172 Apache-2.0 616 324 (1 issue needs help) 176 Updated Feb 28, 2025
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 254 Apache-2.0 33 20 28 Updated Feb 28, 2025
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 264 Apache-2.0 79 19 1 Updated Feb 28, 2025
  • UHDM Public

    Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/UHDM’s past year of commit activity
    C++ 209 Apache-2.0 40 17 1 Updated Feb 28, 2025
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 83 Apache-2.0 45 85 16 Updated Feb 28, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    C++ 35 LGPL-3.0 644 0 0 Updated Feb 28, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 12 Apache-2.0 8 24 5 Updated Feb 28, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 104 Apache-2.0 51 113 47 Updated Feb 28, 2025
  • chisel-nix Public

    Nix template for the chisel-based industrial designing flows.

    chipsalliance/chisel-nix’s past year of commit activity
    Nix 35 5 1 2 Updated Feb 28, 2025
  • chips-alliance-website Public
    chipsalliance/chips-alliance-website’s past year of commit activity
    SCSS 3 MIT 5 8 8 Updated Feb 28, 2025
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