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1. async_FIFO async_FIFO Public

   This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

   SystemVerilog 58 16

2. hw hw Public

   Forked from nvdla/hw

   RTL, Cmodel, and testbench for NVDLA

   Verilog 1

3. synthesis_example synthesis_example Public

   This is one example of synthesis. And trying some options.

   Tcl 1

4. CDN CDN Public

   my CDN pictures

5. dadongshangu.github.io dadongshangu.github.io Public

   Github pages

   Stylus

6. dadongshangu dadongshangu Public