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Fix compilation with warnings as errors on
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And delete some commented out code.

Signed-off-by: Mario Bălănică <[email protected]>
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@mariobalanica
mariobalanica committed Jan 5, 2024
1 parent 5974d88 commit eadf046
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Showing 9 changed files with 4 additions and 226 deletions.
23 changes: 0 additions & 23 deletions edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/Ohci.c
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Expand Up @@ -10,29 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent

#include "Ohci.h"

STATIC OHCI_DEVICE_PATH OhciDevicePathProtocol = {
{
{
HARDWARE_DEVICE_PATH,
HW_VENDOR_DP,
{
(UINT8)(OFFSET_OF (OHCI_DEVICE_PATH, End)),
(UINT8)(OFFSET_OF (OHCI_DEVICE_PATH, End) >> 8),
},
},
EFI_CALLER_ID_GUID
},
0, // Instance
{
END_DEVICE_PATH_TYPE,
END_ENTIRE_DEVICE_PATH_SUBTYPE,
{
sizeof(EFI_DEVICE_PATH_PROTOCOL),
0
}
}
};

/**
Provides software reset for the USB host controller.
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2 changes: 1 addition & 1 deletion edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.c
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Expand Up @@ -987,7 +987,7 @@ FvbConfigureFlashInstance (
{
EFI_STATUS Status;
UINTN DataOffset;
UINTN VariableSize, FtwWorkingSize, FtwSpareSize, MemorySize;
UINTN VariableSize, FtwWorkingSize, FtwSpareSize;

// Locate SPI protocols
Status = gBS->LocateProtocol (&gUniNorFlashProtocolGuid,
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38 changes: 2 additions & 36 deletions edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwDpLib.c
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Expand Up @@ -554,40 +554,6 @@ static int dw_dp_link_power_up(struct dw_dp *dp)
return 0;
}

static int dw_dp_link_probe(struct dw_dp *dp)
{
struct dw_dp_link *link = &dp->link;
u8 dpcd;
int ret;

ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd);
if (ret < 0)
return ret;

ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
&dpcd);
if (ret < 0)
return ret;

link->vsc_sdp_extension_for_colorimetry_supported =
!!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);

link->revision = link->dpcd[DP_DPCD_REV];
link->rate = min_t(u32, min(dp->max_link_rate, dp->phy->Capabilities.MaximumLinkRate * 100),
drm_dp_max_link_rate(link->dpcd));
link->lanes = min_t(u8, dp->phy->Capabilities.BusWidth,
drm_dp_max_lane_count(link->dpcd));

link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd);
link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd);
link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd);
link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd);
link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] &
DP_MAX_DOWNSPREAD_0_5);

return 0;
}

static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp)
{
struct dw_dp_link *link = &dp->link;
Expand Down Expand Up @@ -1236,7 +1202,7 @@ static int dw_dp_video_enable(struct dw_dp *dp)
u8 color_format = video->color_format;
u8 bpc = video->bpc;
u8 pixel_mode = video->pixel_mode;
u8 bpp = video->bpp, init_threshold, vic;
u8 bpp = video->bpp, init_threshold;
u32 hactive, hblank, h_sync_width, h_front_porch;
u32 vactive, vblank, v_sync_width, v_front_porch;
u32 vstart = mode->VTotal - mode->VSyncStart;
Expand Down Expand Up @@ -1407,7 +1373,7 @@ static int dw_dp_connector_init(ROCKCHIP_CONNECTOR_PROTOCOL *conn, DISPLAY_STATE
{
CONNECTOR_STATE *conn_state = &state->ConnectorState;
struct dw_dp *dp = DW_DP_FROM_CONNECTOR_PROTOCOL (conn);
int ret;
int ret = 0;

conn_state->OutputInterface |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0;
conn_state->OutputMode = ROCKCHIP_OUT_MODE_AAAA;
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61 changes: 0 additions & 61 deletions edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.c
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Original file line number Diff line number Diff line change
Expand Up @@ -213,74 +213,13 @@ ApplyVariables (
AfterApplyVariablesInit ();
}

STATIC
VOID
UartInit (
IN VOID
)
{
//UINT32 Val;

DEBUG((DEBUG_INIT, "RK3588InitPeripherals: UartInit()\n"));
/* make UART1 out of reset */
//MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART1);
//MmioWrite32 (CRU_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART1);
/* make UART2 out of reset */
//MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART2);
//MmioWrite32 (CRU_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART2);
/* make UART3 out of reset */
//MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART3);
//MmioWrite32 (CRU_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART3);
/* make UART4 out of reset */
//MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART4);
//MmioWrite32 (CRU_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART4);

/* make DW_MMC2 out of reset */
//MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS0, PERIPH_RST0_MMC2);

/* enable clock for BT/WIFI */
//Val = MmioRead32 (PMUSSI_ONOFF8_REG) | PMUSSI_ONOFF8_EN_32KB;
//MmioWrite32 (PMUSSI_ONOFF8_REG, Val);
}

STATIC
VOID
MtcmosInit (
IN VOID
)
{
//UINT32 Data;

DEBUG((DEBUG_INIT, "RK3588InitPeripherals: MtcmosInit()\n"));
/* enable MTCMOS for GPU */
//MmioWrite32 (AO_CTRL_BASE + SC_PW_MTCMOS_EN0, PW_EN0_G3D);
//do {
// Data = MmioRead32 (AO_CTRL_BASE + SC_PW_MTCMOS_ACK_STAT0);
//} while ((Data & PW_EN0_G3D) == 0);
}

EFI_STATUS
RK3588InitPeripherals (
IN VOID
)
{
//UINT32 Data, Bits;

DEBUG((DEBUG_INIT, "RK3588InitPeripherals: Entry\n"));

/* make I2C0/I2C1/I2C2/SPI0 out of reset */
//Bits = PERIPH_RST3_I2C0 | PERIPH_RST3_I2C1 | PERIPH_RST3_I2C2 | PERIPH_RST3_SSP;
//MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, Bits);

//do {
// Data = MmioRead32 (CRU_BASE + SC_PERIPH_RSTSTAT3);
//} while (Data & Bits);

// UartInit ();

/* MTCMOS -- Multi-threshold CMOS */
// MtcmosInit ();

Rk806Configure();

return EFI_SUCCESS;
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52 changes: 1 addition & 51 deletions edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhyDxe.c
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Expand Up @@ -393,15 +393,6 @@ static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)
grfreg_write(udphy->usbgrf, preg, disable);
}

__maybe_unused
static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)
{
const struct rockchip_udphy_cfg *cfg = udphy->cfgs;

grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
}

/*
* In usb/dp combo phy driver, here are 2 ways to mapping lanes.
*
Expand Down Expand Up @@ -479,38 +470,6 @@ static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)
return ret;
}

__maybe_unused
static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy)
{
if (udphy->flip) {
udphy->dp_lane_sel[0] = 0;
udphy->dp_lane_sel[1] = 1;
udphy->dp_lane_sel[2] = 3;
udphy->dp_lane_sel[3] = 2;
udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
} else {
udphy->dp_lane_sel[0] = 2;
udphy->dp_lane_sel[1] = 3;
udphy->dp_lane_sel[2] = 1;
udphy->dp_lane_sel[3] = 0;
udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
}

udphy->mode = UDPHY_MODE_DP_USB;

return 0;
}

static int udphy_setup(struct rockchip_udphy *udphy)
{
const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
Expand Down Expand Up @@ -538,7 +497,7 @@ static int udphy_disable(struct rockchip_udphy *udphy)

static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, UINT8 *prop, UINTN num_lanes)
{
int ret, i;
int i;

if (!prop) {
dev_dbg(udphy->dev,
Expand Down Expand Up @@ -766,15 +725,6 @@ static int rockchip_u3phy_init(struct rockchip_udphy *udphy)
return udphy_power_on(udphy, UDPHY_MODE_USB);
}

static int rockchip_u3phy_exit(struct rockchip_udphy *udphy)
{
/* DP only or high-speed */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
return 0;

return udphy_power_off(udphy, UDPHY_MODE_USB);
}

static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
{
/* configure phy reference clock */
Expand Down
50 changes: 0 additions & 50 deletions edk2-rockchip/Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.c
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Original file line number Diff line number Diff line change
Expand Up @@ -41,32 +41,13 @@
#define SOFTRST_INDEX 27
#define SOFTRST_BIT 14

STATIC
VOID
GrfUpdateRegister (
IN EFI_PHYSICAL_ADDRESS Reg,
IN UINT32 Mask,
IN UINT32 Val
)
{
ASSERT ((Mask & ~0xFFFF) == 0);
ASSERT ((Val & ~0xFFFF) == 0);
ASSERT ((Mask & Val) == Val);

MmioWrite32 (Reg, (Mask << 16) | Val);
}

EFI_STATUS
Pcie30PhyInit (
VOID
)
{
// UINTN Retry;

DEBUG ((DEBUG_INFO, "PCIe30: PHY init\n"));

// MicroSecondDelay(100000);

/* Disable power domain */
MmioWrite32(0xFD8D8150, 0x1 << 23 | 0x1 << 21); // PD_PCIE & PD_PHP

Expand All @@ -81,37 +62,6 @@ Pcie30PhyInit (
/* Deassert PHY Reset */
MmioWrite32(0xFD7C8A00, (0x1 << 26));

// /* Enable clocks */
// PmuCruEnableClock (2, 13);
// PmuCruEnableClock (2, 14);
// CruEnableClock (33, 8);

// /* Assert reset */
// CruAssertSoftReset (SOFTRST_INDEX, SOFTRST_BIT);
// gBS->Stall (1000);

// MicroSecondDelay (1);

// GrfUpdateRegister (GRF_PCIE30_PHY_CON (9), GRF_PCIE30PHY_DA_OCM_MASK, GRF_PCIE30PHY_DA_OCM);
// GrfUpdateRegister (GRF_PCIE30_PHY_CON (5), GRF_PCIE30PHY_LANE0_LINK_NUM_MASK, PCIE30PHY_LANE0_LINK_NUM);
// GrfUpdateRegister (GRF_PCIE30_PHY_CON (6), GRF_PCIE30PHY_LANE1_LINK_NUM_MASK, PCIE30PHY_LANE1_LINK_NUM);
// GrfUpdateRegister (GRF_PCIE30_PHY_CON (1), GRF_PCIE30PHY_DA_OCM_MASK, GRF_PCIE30PHY_DA_OCM);

// /* De-assert reset */
// CruDeassertSoftReset (SOFTRST_INDEX, SOFTRST_BIT);

// for (Retry = 500; Retry > 0; Retry--) {
// MicroSecondDelay (100);

// if ((MmioRead32 (GRF_PCIE30_PHY_STATUS (0)) & GRF_PCIE30PHY_SRAM_INIT_DONE) != 0) {
// break;
// }
// }
// if (Retry == 0) {
// DEBUG ((DEBUG_WARN, "PCIe30: Failed to enable PCIe 3.0 PHY\n"));
// return EFI_TIMEOUT;
// }

DEBUG ((DEBUG_INFO, "PCIe30: PHY init complete\n"));
return EFI_SUCCESS;
}
1 change: 0 additions & 1 deletion edk2-rockchip/Silicon/Rockchip/Rockchip.dsc.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -342,7 +342,6 @@ FspiLib|Silicon/Rockchip/Library/FspiLib/FspiLib.inf
[BuildOptions]
# RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
*_*_*_CC_FLAGS = -DDEFAULT_DARK
GCC:*_*_AARCH64_CC_FLAGS = -Wno-error=uninitialized -Wno-error=stringop-overflow -Wno-error=unused-function -Wno-error=unused-variable

[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
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1 change: 0 additions & 1 deletion edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.c
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Expand Up @@ -596,7 +596,6 @@ DwMmcHcDriverBindingStart (

NON_DISCOVERABLE_DEVICE *Dev;

BOOLEAN MediaPresent;
DWMMC_CARD_TYPE_DETECT_ROUTINE *Routine;
UINT8 Index;
UINT32 RoutineNum;
Expand Down
2 changes: 0 additions & 2 deletions edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHci.c
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Original file line number Diff line number Diff line change
Expand Up @@ -581,8 +581,6 @@ DwMmcHcStartDma (
UINTN DevBase;
UINT32 Ctrl;
UINT32 Bmod;
UINT32 Timeout;
UINT32 Data;

// DevIo = Trb->Private->DevIo;
DevBase = Trb->Private->DevBase;
Expand Down

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