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fix rtl bugs #9

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fix rtl bugs #9

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b908a5b
fix rtl bugs -first writing or reading was not implemented as hreadyo…
M0stafaRady Jan 22, 2025
6d1bdbd
correct Design name for openlane
M0stafaRady Jan 22, 2025
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4 changes: 2 additions & 2 deletions hdl/rtl/bus_wrapper/EF_PSRAM_CTRL_AHBL.v
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Original file line number Diff line number Diff line change
Expand Up @@ -181,7 +181,7 @@ module EF_PSRAM_CTRL_AHBL #(parameter REGISTER_HWDATA = 1)
always@(posedge HCLK or negedge HRESETn) begin
if(!HRESETn)
last_HSIZE <= 0;
else if (HTRANS[1])
else if (HTRANS[1] & HREADYOUT)
last_HSIZE<=HSIZE;
end

Expand Down Expand Up @@ -254,7 +254,7 @@ module EF_PSRAM_CTRL_AHBL #(parameter REGISTER_HWDATA = 1)
else
case (state)
ST_IDLE :
if((last_ahb_addr_phase|ahb_addr_phase) & data_cfg)
if((last_ahb_addr_phase|ahb_addr_phase))
HREADYOUT <= 1'b0;
else
HREADYOUT <= 1'b1;
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2 changes: 1 addition & 1 deletion verify/uvm-python/Makefile
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Expand Up @@ -10,7 +10,7 @@ VERILOG_SOURCES ?= $(PWD)/top.v $(AHB_FILES) $(HDL_FILES) $(VIP_FILES)
RTL_MACROS += "" # Add macros needed
BUS_TYPE ?= AHB
RTL_MACROS += -DBUS_TYPE_AHB
DESIGN_NAME = EF_PSRAM_CTRL_ahbl
DESIGN_NAME = EF_PSRAM_CTRL_AHBL
export CLK_MAKEFILE = HCLK
export RST_MAKEFILE = HRESETn
## netlist Gen
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