declared ports type as wire and update version

efabless · May 20, 2024 · 7ac0912 · 7ac0912
1 parent 19f7fc5
commit 7ac0912
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Showing 7 changed files with 26 additions and 26 deletions.
diff --git a/EF_SPI.yaml b/EF_SPI.yaml
@@ -7,8 +7,8 @@ info:
   license: APACHE 2.0
   author: Mohamed Shalan
   email: [email protected]
-  version: v1.0.3
-  date: 19-5-2024
+  version: v1.0.4
+  date: 20-5-2024
   category: digital
   tags:
     - peripheral

diff --git a/hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v b/hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v
@@ -116,10 +116,10 @@ module EF_SPI_AHBL #(
                                         output wire [31:0]  HRDATA,
                                         output wire         IRQ
 ,
-	input	[1-1:0]	miso,
-	output	[1-1:0]	mosi,
-	output	[1-1:0]	csb,
-	output	[1-1:0]	sclk
+	input	wire	[1-1:0]	miso,
+	output	wire	[1-1:0]	mosi,
+	output	wire	[1-1:0]	csb,
+	output	wire	[1-1:0]	sclk
 );
 
 	localparam	RXDATA_REG_OFFSET = 16'h0000;

diff --git a/hdl/rtl/bus_wrappers/EF_SPI_AHBL.v b/hdl/rtl/bus_wrappers/EF_SPI_AHBL.v
@@ -32,10 +32,10 @@ module EF_SPI_AHBL #(
 		FAW = 4
 ) (
 	`AHBL_SLAVE_PORTS,
-	input	[1-1:0]	miso,
-	output	[1-1:0]	mosi,
-	output	[1-1:0]	csb,
-	output	[1-1:0]	sclk
+	input	wire	[1-1:0]	miso,
+	output	wire	[1-1:0]	mosi,
+	output	wire	[1-1:0]	csb,
+	output	wire	[1-1:0]	sclk
 );
 
 	localparam	RXDATA_REG_OFFSET = `AHBL_AW'h0000;

diff --git a/hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v b/hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v
@@ -99,10 +99,10 @@ module EF_SPI_APB #(
                                         output wire [31:0]  PRDATA,
                                         output wire         IRQ
 ,
-	input	[1-1:0]	miso,
-	output	[1-1:0]	mosi,
-	output	[1-1:0]	csb,
-	output	[1-1:0]	sclk
+	input	wire	[1-1:0]	miso,
+	output	wire	[1-1:0]	mosi,
+	output	wire	[1-1:0]	csb,
+	output	wire	[1-1:0]	sclk
 );
 
 	localparam	RXDATA_REG_OFFSET = 16'h0000;

diff --git a/hdl/rtl/bus_wrappers/EF_SPI_APB.v b/hdl/rtl/bus_wrappers/EF_SPI_APB.v
@@ -32,10 +32,10 @@ module EF_SPI_APB #(
 		FAW = 4
 ) (
 	`APB_SLAVE_PORTS,
-	input	[1-1:0]	miso,
-	output	[1-1:0]	mosi,
-	output	[1-1:0]	csb,
-	output	[1-1:0]	sclk
+	input	wire	[1-1:0]	miso,
+	output	wire	[1-1:0]	mosi,
+	output	wire	[1-1:0]	csb,
+	output	wire	[1-1:0]	sclk
 );
 
 	localparam	RXDATA_REG_OFFSET = `APB_AW'h0000;

diff --git a/hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v b/hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v
@@ -93,10 +93,10 @@ module EF_SPI_WB #(
                                         output  reg             ack_o,
                                         input   wire            we_i,
                                         output  wire            IRQ,
-	input	[1-1:0]	miso,
-	output	[1-1:0]	mosi,
-	output	[1-1:0]	csb,
-	output	[1-1:0]	sclk
+										input	wire	[1-1:0]	miso,
+										output	wire	[1-1:0]	mosi,
+										output	wire	[1-1:0]	csb,
+										output	wire	[1-1:0]	sclk
 );
 
 	localparam	RXDATA_REG_OFFSET = 16'h0000;

diff --git a/hdl/rtl/bus_wrappers/EF_SPI_WB.v b/hdl/rtl/bus_wrappers/EF_SPI_WB.v
@@ -32,10 +32,10 @@ module EF_SPI_WB #(
 		FAW = 4
 ) (
 	`WB_SLAVE_PORTS,
-	input	[1-1:0]	miso,
-	output	[1-1:0]	mosi,
-	output	[1-1:0]	csb,
-	output	[1-1:0]	sclk
+	input	wire	[1-1:0]	miso,
+	output	wire	[1-1:0]	mosi,
+	output	wire	[1-1:0]	csb,
+	output	wire	[1-1:0]	sclk
 );
 
 	localparam	RXDATA_REG_OFFSET = `WB_AW'h0000;