regenerate apb wrapper to have gated clock and update fw

efabless · Jul 8, 2024 · 9bbb088 · 9bbb088
1 parent dc9cc39
commit 9bbb088
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Showing 6 changed files with 76 additions and 5 deletions.
diff --git a/EF_SPI.yaml b/EF_SPI.yaml
@@ -7,8 +7,8 @@ info:
   license: APACHE 2.0
   author: Mohamed Shalan
   email: [email protected]
-  version: v1.0.5
-  date: 27-6-2024
+  version: v1.0.6
+  date: 08-07-2024
   category: digital
   tags:
     - peripheral

diff --git a/fw/EF_SPI.c b/fw/EF_SPI.c
@@ -3,6 +3,10 @@
 
 #include <EF_SPI.h>
 
+void EF_SPI_setGclkEnable (uint32_t spi_base, int value){
+    EF_SPI_TYPE* spi = (EF_SPI_TYPE*)spi_base;
+    spi->GCLK = value;
+}
 
 void EF_SPI_writeData(uint32_t spi_base, int data){
 

diff --git a/fw/EF_SPI.h b/fw/EF_SPI.h
@@ -4,7 +4,7 @@
 #include <EF_SPI_regs.h>
 #include <stdint.h>
 #include <stdbool.h>
-
+void EF_SPI_setGclkEnable (uint32_t spi_base, int value);
 void EF_SPI_writeData(uint32_t spi_base, int data);
 int EF_SPI_readData(uint32_t spi_base);
 void EF_SPI_writepolarity(uint32_t spi_base, bool polarity);

diff --git a/fw/EF_SPI_regs.h b/fw/EF_SPI_regs.h
@@ -89,6 +89,7 @@ typedef struct _EF_SPI_TYPE_ {
 	__R 	MIS;
 	__R 	RIS;
 	__W 	IC;
+	__W 	GCLK;
 } EF_SPI_TYPE;
 
 #endif

diff --git a/hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v b/hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v
@@ -62,6 +62,20 @@
 
 
 
+
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+
 
 
 
@@ -88,6 +102,10 @@ module EF_SPI_APB #(
 		CDW = 8,
 		FAW = 4
 ) (
+`ifdef USE_POWER_PINS
+	input wire VPWR,
+	input wire VGND,
+`endif
 	input wire          PCLK,
                                         input wire          PRESETn,
                                         input wire          PWRITE,
@@ -121,7 +139,23 @@ module EF_SPI_APB #(
 	localparam	MIS_REG_OFFSET = 16'hFF04;
 	localparam	RIS_REG_OFFSET = 16'hFF08;
 	localparam	IC_REG_OFFSET = 16'hFF0C;
-	wire		clk = PCLK;
+
+        wire clk_g;
+        wire clk_gated_en = GCLK_REG[0];
+
+    (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
+	`ifdef USE_POWER_PINS
+        .VPWR(VPWR), 
+        .VGND(VGND), 
+        .VNB(VGND),
+		.VPB(VPWR),
+    `endif
+        .GCLK(clk_g), 
+        .GATE(clk_gated_en), 
+        .CLK(PCLK)
+        );
+
+	wire		clk = clk_g;
 	wire		rst_n = PRESETn;
 
 
@@ -220,6 +254,12 @@ module EF_SPI_APB #(
                                                 else
                                                     TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;
 
+	localparam	GCLK_REG_OFFSET = 16'hFF10;
+	reg [0:0] GCLK_REG;
+	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) GCLK_REG <= 0;
+                                        else if(apb_we & (PADDR[16-1:0]==GCLK_REG_OFFSET))
+                                            GCLK_REG <= PWDATA[1-1:0];
+
 	reg [5:0] IM_REG;
 	reg [5:0] IC_REG;
 	reg [5:0] RIS_REG;
@@ -317,6 +357,7 @@ module EF_SPI_APB #(
 			(PADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
 			(PADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
 			(PADDR[16-1:0] == IC_REG_OFFSET)	? IC_REG :
+			(PADDR[16-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
 			32'hDEADBEEF;
 
 	assign	PREADY = 1'b1;

diff --git a/hdl/rtl/bus_wrappers/EF_SPI_APB.v b/hdl/rtl/bus_wrappers/EF_SPI_APB.v
@@ -31,6 +31,10 @@ module EF_SPI_APB #(
 		CDW = 8,
 		FAW = 4
 ) (
+`ifdef USE_POWER_PINS
+	input wire VPWR,
+	input wire VGND,
+`endif
 	`APB_SLAVE_PORTS,
 	input	wire	[1-1:0]	miso,
 	output	wire	[1-1:0]	mosi,
@@ -54,7 +58,23 @@ module EF_SPI_APB #(
 	localparam	MIS_REG_OFFSET = `APB_AW'hFF04;
 	localparam	RIS_REG_OFFSET = `APB_AW'hFF08;
 	localparam	IC_REG_OFFSET = `APB_AW'hFF0C;
-	wire		clk = PCLK;
+
+        wire clk_g;
+        wire clk_gated_en = GCLK_REG[0];
+
+    (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
+    `ifdef USE_POWER_PINS 
+        .VPWR(VPWR), 
+        .VGND(VGND), 
+        .VNB(VGND),
+		.VPB(VPWR),
+    `endif 
+        .GCLK(clk_g), 
+        .GATE(clk_gated_en), 
+        .CLK(PCLK)
+        );
+
+	wire		clk = clk_g;
 	wire		rst_n = PRESETn;
 
 
@@ -133,6 +153,10 @@ module EF_SPI_APB #(
 	assign	tx_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
 	`APB_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0)
 
+	localparam	GCLK_REG_OFFSET = `APB_AW'hFF10;
+	reg [0:0] GCLK_REG;
+	`APB_REG(GCLK_REG, 0, 1)
+
 	reg [5:0] IM_REG;
 	reg [5:0] IC_REG;
 	reg [5:0] RIS_REG;
@@ -224,6 +248,7 @@ module EF_SPI_APB #(
 			(PADDR[`APB_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
 			(PADDR[`APB_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
 			(PADDR[`APB_AW-1:0] == IC_REG_OFFSET)	? IC_REG :
+			(PADDR[`APB_AW-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
 			32'hDEADBEEF;
 
 	assign	PREADY = 1'b1;