update MISO sequence to make sure the fifo is not empty

verify/uvm-python/spi_ref_model/spi_ref_model.py

@@ -9,7 +9,7 @@
 from EF_UVM.ref_model.ref_model import ref_model
 from EF_UVM.bus_env.bus_item import bus_item
 from cocotb.triggers import Event
-from cocotb.queue import Queue, QueueFull
+from cocotb.queue import Queue, QueueFull, QueueEmpty
 
 
 class spi_ref_model(ref_model):
@@ -100,7 +100,11 @@ def write_bus(self, tr):
                 # pass value as it is until logic of ris is implemented
                 pass
             elif td.addr == self.regs.reg_name_to_address["RXDATA"]:
-                td.data = self.fifo_rx.get_nowait()
+                try:
+                    td.data = self.fifo_rx.get_nowait()
+                except QueueEmpty:
+                    uvm_warning(self.tag, f"reading from rx while fifo is empty")
+                    td.data = "xxxxxxxxxxxxxxxxxxxxxxxx00000000"
             else:
                 td.data = data
             self.bus_bus_export.write(td)  # this is output to the scoreboard

verify/uvm-python/spi_seq_lib/spi_send_MISO_seq.py

@@ -35,6 +35,7 @@ async def body(self):
         )
         for _ in range(self.num_data):
             await self.wait_rx_fifo_not_empty()
+            await self.wait_rx_fifo_not_empty()# to make sure it's empty
             if random.random() < 0.7:  # 20% probability of reading
                 await self.send_req(is_write=False, reg="RXDATA")
             uvm_info(self.tag, f"interation number {_}", UVM_MEDIUM)