support diffrent sizes with wishbone

efabless · Oct 17, 2024 · 72b052e · 72b052e
1 parent 255726e
commit 72b052e
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Showing 2 changed files with 9 additions and 25 deletions.
diff --git a/verify/uvm-python/sram_ref_model/sram_ref_model.py b/verify/uvm-python/sram_ref_model/sram_ref_model.py
@@ -55,19 +55,9 @@ def write_bus(self, tr):
             if tr.size == bus_item.WORD_ACCESS:
                 self.mem.write_word(tr.addr, tr.data)
             elif tr.size == bus_item.HALF_WORD_ACCESS:
-                if tr.addr % 4 == 0:
-                    self.mem.write_halfword(tr.addr, tr.data & 0xFFFF)
-                else:
-                    self.mem.write_halfword(tr.addr, tr.data >> 16)
+                self.mem.write_halfword(tr.addr, tr.data & 0xFFFF)
             elif tr.size == bus_item.BYTE_ACCESS:
-                if tr.addr % 4 == 0:
-                    self.mem.write_byte(tr.addr, tr.data & 0xFF)
-                elif tr.addr % 4 == 1:
-                    self.mem.write_byte(tr.addr, (tr.data >> 8) & 0xFF)
-                elif tr.addr % 4 == 2:
-                    self.mem.write_byte(tr.addr, (tr.data >> 16) & 0xFF)
-                elif tr.addr % 4 == 3:
-                    self.mem.write_byte(tr.addr, (tr.data >> 24) & 0xFF)
+                self.mem.write_byte(tr.addr, tr.data & 0xFF)
             self.bus_bus_export.write(tr)  # this is output to the scoreboard
         elif tr.kind == bus_item.READ:
             td = tr.do_clone()

diff --git a/verify/uvm-python/sram_seq_lib/sram_write_read_seq.py b/verify/uvm-python/sram_seq_lib/sram_write_read_seq.py
@@ -38,19 +38,13 @@ async def _write_read_seq(self, iterations, write_priority):
                 await self.read_from_mem(address=address, size=size)
 
     def rand_addr_size(self):
-        BUS_TYPE = cocotb.plusargs["BUS_TYPE"]
-        if BUS_TYPE == "AHB":
-            address = random.randint(0, (self.mem_size - 1) * 4)
-            if address % 4 == 0:
-                size = random.choice((bus_item.WORD_ACCESS, bus_item.HALF_WORD_ACCESS, bus_item.BYTE_ACCESS))
-            elif address % 2 == 0:
-                size = random.choice((bus_item.HALF_WORD_ACCESS, bus_item.BYTE_ACCESS))
-            else:
-                size = bus_item.BYTE_ACCESS
-        else: # sizes are fixed for APB and WB
-            address = random.randint(0, self.mem_size - 1) << 2
-            size = bus_item.WORD_ACCESS
-
+        address = random.randint(0, (self.mem_size - 1) * 4)
+        if address % 4 == 0:
+            size = random.choice((bus_item.WORD_ACCESS, bus_item.HALF_WORD_ACCESS, bus_item.BYTE_ACCESS))
+        elif address % 2 == 0:
+            size = random.choice((bus_item.HALF_WORD_ACCESS, bus_item.BYTE_ACCESS))
+        else:
+            size = bus_item.BYTE_ACCESS
         return address, size
 
 uvm_object_utils(sram_write_read_seq)