Add controllers and uvm

[M0stafaRady]

• Add AHB controller
• Add AHB wrapper
• Fix the wishbone controller
• Add verification environment

CI is failing the GL simulation because it can't synthesis the behavior models, A change to the CI to skip GL sims for such a repos would be added in the central CI repo.

[marwaneltoukhy]

What is wrong with the wishbone controller?

[M0stafaRady]

What is wrong with the wishbone controller?

There is a bug that would prevent accessing 3/4 of the memory space.

[DavidRLindley]

Are there any risks skipping GL simulations?

[M0stafaRady]

Are there any risks skipping GL simulations?

I don't think so.
The main reason of the CI is to synthesis the RTL then run GL sims. Since a very small portion of the code is synthesizable it should not affect much.

[DavidRLindley]

Does this bug affect the RAMs on the SRAM-TC taped out on 2404 and 2406?

[M0stafaRady]

Does this bug affect the RAMs on the SRAM-TC taped out on 2404 and 2406?

I guess yes as long as this controller is used.