verified wishbone in UVM

efabless · Apr 17, 2024 · 41b2168 · 41b2168
1 parent 170180f
commit 41b2168
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/verify/uvm-python/Makefile b/verify/uvm-python/Makefile
@@ -3,7 +3,7 @@ TOPLEVEL := top
 MODULE   ?= top_module
 AHB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
 APB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
-WB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_wb.v
+WB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_WB.pp.v
 HDL_FILES ?= $(PWD)/IP_Utilities/rtl/aucohl_lib.v $(PWD)/IP_Utilities/rtl/aucohl_rtl.vh  $(PWD)/../../hdl/rtl/EF_UART.v 
 VERILOG_SOURCES ?=  $(PWD)/top.v $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
 RTL_MACROS += ""
@@ -20,7 +20,7 @@ else ifeq ($(BUS_TYPE),AHB)
     export RST_MAKEFILE = HRESETn
 else ifeq ($(BUS_TYPE),WISHBONE)
     RTL_MACROS += -DBUS_TYPE_WISHBONE
-    DESIGN_NAME = EF_UART_wb
+    DESIGN_NAME = EF_UART_WB
 endif
 ## netlist Gen 
 GL_MACROS += -DGL -DFUNCTIONAL  $(RTL_MACROS) -DUNIT_DELAY=\#1 

diff --git a/verify/uvm-python/top.v b/verify/uvm-python/top.v
@@ -35,7 +35,7 @@ module top();
         wire        cyc_i;
         wire        stb_i;
         reg         ack_o;
-        EF_UART_wb dut(.rx(RX), .tx(TX), .clk_i(CLK), .rst_i(~rst_i), .adr_i(adr_i), .dat_i(dat_i), .dat_o(dat_o), .sel_i(sel_i), .cyc_i(cyc_i), .stb_i(stb_i), .ack_o(ack_o),.we_i(we_i), .irq(irq));
+        EF_UART_WB dut(.rx(RX), .tx(TX), .clk_i(CLK), .rst_i(~RESETn), .adr_i(adr_i), .dat_i(dat_i), .dat_o(dat_o), .sel_i(sel_i), .cyc_i(cyc_i), .stb_i(stb_i), .ack_o(ack_o),.we_i(we_i), .IRQ(irq));
     `endif // BUS_TYPE_WISHBONE
     // monitor inside signals
 `ifndef GL