Initial commit

.gitignore

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+# Compiled Object files
+*.slo
+*.lo
+*.o
+*.obj
+
+# Precompiled Headers
+*.gch
+*.pch
+
+# Compiled Dynamic libraries
+*.so
+*.dylib
+*.dll
+
+# Fortran module files
+*.mod
+
+# Compiled Static libraries
+*.lai
+*.la
+*.a
+*.lib
+
+# Executables
+*.exe
+*.out
+*.app
+
+# Bison & Lex
+*.tab.h
+*.tab.cpp
+lex.*.cpp
+*.output
+
+# QMake Makefiles
+src/*/Makefile
+src/Makefile
+
+# Others
+*.log
+*.swp
+.nfs*
+
+circuit.exe
+circuit

AUTHORS

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+Gary Huang <gh.nctu+code at gmail dot com>

COPYING

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+GNU Lesser General Public License (LGPL) version 3

README.md

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+# libCircuit
+
+libCircuit is a C++ Library for EDA software development
+
+*WARNING: Alpha version.*
+
+## Requirement
+* Qt 5.2 (Untested on lower version but may be fine)
+* Bison and Flex
+
+## Usage
+Get the source code:
+```sh
+$ git clone [email protected]:/EDA/libCircuit.git
+```
+
+Compile:
+```sh
+$ cd libCircuit/
+$ qmake
+$ make
+```
+
+Run:
+```sh
+$ ./circuit c17.v
+```
+
+## Examples
+
+Check circuit is created successfully
+```C++
+Circuit circuit("c17.v");
+if (!circuit.isNull())
+{
+    // You can use circuit now
+}
+```
+
+Print circuit information
+```C++
+int main()
+{
+    Circuit circuit("c17.v");
+    cout << "Circuit: " << circuit.name() << endl;
+    cout << "#input: " << circuit.inputSize() << endl;
+    cout << "#output: " << circuit.outputSize() << endl;
+    cout << "Gate count: " << circuit.gateCount() << endl;
+    return 0;
+}
+```
+
+Forward traverse all the circuit elements
+```C++
+void forward(const Node &node)
+{
+    static int level = 0;
+    string spaces(2 * level, ' ');
+    cout << spaces << node.nodeName() << endl;
+    for (size_t i = 0; i < node.outputSize(); i++)
+    {
+        level++;
+        forward(node.output(i));
+        level--;
+    }
+}
+
+int main()
+{
+    Circuit circuit("c17.v");
+    for (size_t i = 0; i < circuit.inputSize(); i++)
+        forward(circuit.inputPort(i));
+    return 0;
+}
+
+```
+
+Backward traverse all the circuit elements
+```C++
+void backward(const Node &node)
+{
+    static int level = 0;
+    string spaces(2 * level, ' ');
+    cout << spaces << node.nodeName() << endl;
+    for (size_t i = 0; i < node.inputSize(); i++)
+    {
+        level++;
+        backward(node.input(i));
+        level--;
+    }
+}
+
+int main()
+{
+    Circuit circuit("c17.v");
+    for (size_t i = 0; i < circuit.outputSize(); i++)
+        backward(circuit.outputPort(i));
+    return 0;
+}
+
+```
+
+## Changelog
+
+## Issues
+* Primitive gate is not handled yet
+* Multiple module is not handled yet
+* Module/cell call-by-port-order is not handled yet
+* Reference counting issue
+
+## License
+GNU Lesser General Public License (LGPL) version 3
+Copyright (c) 2017 Gary Huang

c17.v

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+/////////////////////////////////////////////////////////////
+// Created by: Synopsys DC Expert(TM) in wire load mode
+// Version   : K-2015.06-SP1
+// Date      : Tue Mar  7 19:38:31 2017
+/////////////////////////////////////////////////////////////
+
+
+module c17 ( N1, N2, N3, N6, N7, N22, N23 );
+  input N1, N2, N3, N6, N7;
+  output N22, N23;
+  wire   n13, n6, n8, n9, n10, n11, n12;
+
+  INV_X1 U8 ( .A(n13), .ZN(n6) );
+  INV_X1 U9 ( .A(n6), .ZN(N23) );
+  NOR2_X1 U10 ( .A1(n8), .A2(n9), .ZN(n13) );
+  NOR2_X1 U11 ( .A1(N2), .A2(N7), .ZN(n9) );
+  INV_X1 U12 ( .A(n10), .ZN(n8) );
+  NAND2_X1 U13 ( .A1(n11), .A2(n12), .ZN(N22) );
+  NAND2_X1 U14 ( .A1(N2), .A2(n10), .ZN(n12) );
+  NAND2_X1 U15 ( .A1(N6), .A2(N3), .ZN(n10) );
+  NAND2_X1 U16 ( .A1(N1), .A2(N3), .ZN(n11) );
+endmodule

main.cpp

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+#include "circuit.h"
+#include <iostream>
+#include <string>
+
+using namespace std;
+
+void usage()
+{
+    cout << "./circuit <verilog>" << endl;
+}
+
+void backward(const Node &node)
+{
+    static int level = 0;
+    string spaces(2 * level, ' ');
+    cout << spaces << node.nodeName() << endl;
+    for (size_t i = 0; i < node.inputSize(); i++)
+    {
+        level++;
+        backward(node.input(i));
+        level--;
+    }
+}
+
+int main(int argc, char *argv[])
+{
+    if (argc != 2)
+    {
+        usage();
+        return 1;
+    }
+
+    Circuit circuit(argv[1]);
+
+    if (circuit.isNull())
+    {
+        cout << "Circuit is empty\n";
+        return 1;
+    }
+
+    cout << "Circuit: " << circuit.name() << endl;
+    cout << "#input: " << circuit.inputSize() << endl;
+    cout << "#output: " << circuit.outputSize() << endl;
+    cout << "Modules: ";
+    cout << circuit.moduleSize() << endl;
+
+    for (size_t i = 0; i < circuit.outputSize(); i++)
+        backward(circuit.outputPort(i));
+    // for (size_t i = 0; i < circuit.moduleSize(); i++)
+    //     cout << circuit.module(i).name() << " ";
+    // cout << endl;
+    //
+    // cout << "Gate count: ";
+    // cout << circuit.gateCount() << endl;
+    //
+    // cout << "Inputs: ";
+    // for (size_t i = 0; i < circuit.inputSize(); i++)
+    //     cout << circuit.inputPort(i).name() <<  " ";
+    // cout << endl;
+    //
+    // cout << "Outputs: ";
+    // for (size_t i = 0; i < circuit.outputSize(); i++)
+    //     cout << circuit.outputPort(i).name() <<  " ";
+    // cout << endl;
+
+    return 0;
+}

main.pro

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+TARGET = circuit
+HEADERS = src/circuit/circuit.h
+SOURCES = main.cpp
+CONFIG += debug
+LIBS += -L./lib -lcircuit -lverilog
+INCLUDEPATH += ./src/circuit
+PRE_TARGETDEPS += ./lib/libcircuit.a
+QMAKE_EXTRA_TARGETS += circuit distclean extraclean
+
+distclean.depends = extraclean
+extraclean.commands =  cd src; make distclean
+
+circuit.target = ./lib/libcircuit.a
+circuit.depends = FORCE
+circuit.commands = cd src; qmake && make