cargo fmt

on-target-tests/tests/init/mod.rs

@@ -13,12 +13,15 @@ use hal::pac;
 /// of the `#[init]` function.
 pub unsafe fn reset_cleanup() {
     unsafe {
-        (*pac::PSM::PTR).frce_off().modify(|_, w| w.proc1().set_bit());
+        (*pac::PSM::PTR)
+            .frce_off()
+            .modify(|_, w| w.proc1().set_bit());
         while !(*pac::PSM::PTR).frce_off().read().proc1().bit_is_set() {
             cortex_m::asm::nop();
         }
-        (*pac::PSM::PTR).frce_off().modify(|_, w| w.proc1().clear_bit());
+        (*pac::PSM::PTR)
+            .frce_off()
+            .modify(|_, w| w.proc1().clear_bit());
         hal::sio::spinlock_reset();
     }
 }
-

on-target-tests/tests/multicore.rs

@@ -11,7 +11,7 @@ use rp2040_hal as hal; // memory layout // panic handler
 use rp235x_hal as hal;
 
 use core::sync::atomic::Ordering;
-use portable_atomic::{AtomicU8, AtomicU32};
+use portable_atomic::{AtomicU32, AtomicU8};
 
 /// The linker will place this boot block at the start of our program image. We
 /// need this to help the ROM bootloader get our code up and running.
@@ -46,9 +46,8 @@ mod tests {
     use crate::XTAL_FREQ_HZ;
     use hal::watchdog::Watchdog;
 
-    use hal::multicore::{Multicore, Stack};
     use core::sync::atomic::Ordering;
-
+    use hal::multicore::{Multicore, Stack};
 
     static CORE1_STACK: Stack<4096> = Stack::new();
 
@@ -74,7 +73,6 @@ mod tests {
         .ok()
         .unwrap();
 
-
         let mut sio = hal::Sio::new(pac.SIO);
 
         let _pins = hal::gpio::Pins::new(
@@ -112,9 +110,8 @@ fn core1_task() {
                     COUNTER.fetch_add(1, Ordering::Relaxed);
                 }
                 STATE.store(2, Ordering::Release);
-            },
+            }
             _ => (),
         }
     }
 }
-

rp235x-hal/src/multicore.rs

@@ -85,7 +85,9 @@ fn core1_setup(stack_limit: *mut usize) {
 /// (Copied from https://github.com/embassy-rs/embassy/blob/9da04cc38ea5cc17740bd9921f9f5cbb1c689a31/embassy-rp/src/lib.rs)
 fn enable_actlr_extexclall() {
     unsafe {
-        (*cortex_m::peripheral::ICB::PTR).actlr.modify(|w| w | (1 << 29));
+        (*cortex_m::peripheral::ICB::PTR)
+            .actlr
+            .modify(|w| w | (1 << 29));
     }
 }