This repository contains solutions to Project Euler problems implemented in Verilog. Each solution is designed to be synthesizable and is currently tested using simulation.
As a computer engineer learning digital design, I wanted a fun and practical way to deepen my knowledge of Verilog. Solving mathematical problems like those in Project Euler provides an interesting challenge to implement and optimize algorithms in hardware description language.
- Synthesizable Code: Each solution is written with the goal of being synthesizable for real-world hardware implementations.
- Simulations: Currently, the solutions are tested through simulations to verify correctness and functionality.
| Problem Number | Status | Notes |
|---|---|---|
| Problem 1 | Solved | Verified in simulation |
| Problem 2 | Solved | Verified in simulation |
| Problem 3 | Solved | Verified in simulation |
| Problem 4 | Solved | Verified in simulation |
| Problem 5 | Solved | Verified in simulation |
| Problem 6 | Solved | Verified in simulation |
| Problem 7 | Solved | Verified in simulation |
| Problem 8 | Solved | Verified in simulation |
| Problem 9 | Solved | Verified in simulation |
| Problem 10 | Solved | Verified in simulation |
| Problem 11 | Solved | Verified in simulation |
| Problem 12 | Solved | Verified in simulation |
| Problem 13 | Solved | Verified in simulation |
- Short-term: Complete more Project Euler problems and ensure synthesizability.
- Maybe: Implement solutions on actual hardware for real-world testing and performance evaluation.