Initial design

.gitignore

@@ -2,6 +2,7 @@
 .idea
 .vscode
 *.vcd
+*.fst
 runs
 tt_submission
 src/user_config.tcl

info.yaml

@@ -1,21 +1,27 @@
 # Tiny Tapeout project information
 project:
-  title:        ""      # Project title
-  author:       ""      # Your name
-  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  ""      # One line description of what your project does
-  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+  title:        "Tiny Shader"      # Project title
+  author:       "Leo Moser"      # Your name
+  discord:      "mole99"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "Tiny Shader allows you to write a small programm of 8 instructions that is executed for each pixel independently on an 80x60 screen."      # One line description of what your project does
+  language:     "SystemVerilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     25175000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_example"
+  top_module:  "tt_um_tiny_shader_mole99"
 
   # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
   source_files:        
-    - "project.v"
+    - "tt_um_tiny_shader_mole99.sv"
+    - "tiny_shader_top.sv"
+    - "shader_execute.sv"
+    - "shader_memory.sv"
+    - "spi_receiver.sv"
+    - "timing.sv"
+    - "synchronizer.sv"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
@@ -30,14 +36,14 @@ pinout:
   ui[7]: ""
 
   # Outputs
-  uo[0]: ""
-  uo[1]: ""
-  uo[2]: ""
-  uo[3]: ""
-  uo[4]: ""
-  uo[5]: ""
-  uo[6]: ""
-  uo[7]: ""
+  uo[0]: "R[1]"
+  uo[1]: "G[1]"
+  uo[2]: "B[1]"
+  uo[3]: "vsync"
+  uo[4]: "R[0]"
+  uo[5]: "G[0]"
+  uo[6]: "B[0]"
+  uo[7]: "hsync"
 
   # Bidirectional pins
   uio[0]: ""

src/config.tcl

@@ -12,7 +12,7 @@
 
 # PL_TARGET_DENSITY - You can increase this if Global Placement fails with error GPL-0302.
 # Users have reported that values up to 0.8 worked well for them.
-set ::env(PL_TARGET_DENSITY) 0.6
+set ::env(PL_TARGET_DENSITY) 0.75
 
 # CLOCK_PERIOD - Increase this in case you are getting setup time violations.
 # The value is in nanoseconds, so 20ns == 50MHz.

src/shader_execute.sv

@@ -0,0 +1,183 @@
+// SPDX-FileCopyrightText: © 2024 Leo Moser <[email protected]>
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+module shader_execute (
+    input  logic        clk_i,
+    input  logic        rst_ni,
+    input  logic [7:0]  instr_i,
+    input  logic        execute,
+
+    input logic  [5:0]  x_pos_i,
+    input logic  [5:0]  y_pos_i,
+
+    output logic [5:0]  rgb_o
+);
+
+    localparam NUM_REGS = 4;
+
+    logic [5:0] regs [NUM_REGS];
+
+    int i;
+
+    // Decode stage
+
+    logic dual_arg; // Is this a dual argument instruction?
+    assign dual_arg = instr_i[7];
+
+    logic [1:0] arg0;
+    logic [1:0] arg1; // valid if dual_arg
+
+    assign arg0 = instr_i[1:0];
+    assign arg1 = instr_i[3:2];
+
+    logic [5:0] imm; // immediate value
+    assign imm = instr_i[5:0];
+
+
+    // TODO
+    logic [5:0] sine_lut [16];
+
+    logic [5:0] rgb;
+    logic [5:0] cur_time;
+    logic [5:0] user;
+    logic skip;
+
+    always_ff @(posedge clk_i) begin
+        if (!rst_ni) begin
+            for (i=0; i<NUM_REGS; i++) begin
+                regs[i] <= '0;
+            end
+
+            sine_lut[0] <= 6'd0;
+            sine_lut[1] <= 6'd6;
+            sine_lut[2] <= 6'd13;
+            sine_lut[3] <= 6'd19;
+            sine_lut[4] <= 6'd25;
+            sine_lut[5] <= 6'd31;
+            sine_lut[6] <= 6'd37;
+            sine_lut[7] <= 6'd42;
+            sine_lut[8] <= 6'd46;
+            sine_lut[9] <= 6'd50;
+            sine_lut[10] <= 6'd54;
+            sine_lut[11] <= 6'd57;
+            sine_lut[12] <= 6'd59;
+            sine_lut[13] <= 6'd61;
+            sine_lut[14] <= 6'd62;
+            sine_lut[15] <= 6'd63;
+
+
+            rgb      <= 6'b000000;
+            cur_time <= 5;
+            user     <= 42;
+            skip     <= 1'b0;
+
+        end else begin
+            if (execute) begin
+                if (skip) begin
+                    skip <= 1'b0;
+                end else begin
+
+                    casez (instr_i)
+
+                        // Single arg instructions
+                        8'b00_0000_??: begin //  SETRGB RGB <= ARG0[1:0]
+                            rgb <= regs[arg0];
+                        end
+                        8'b00_0001_??: begin //  SETR R <= ARG0[1:0]
+                            rgb[5:4] <= regs[arg0][1:0];
+                        end
+                        8'b00_0010_??: begin //  SETG G <= ARG0[1:0]
+                            rgb[3:2] <= regs[arg0][1:0];
+                        end
+                        8'b00_0011_??: begin //  SETB B <= ARG0[1:0]
+                            rgb[1:0] <= regs[arg0][1:0];
+                        end
+
+                        8'b00_0100_??: begin //  GETX ARG0 <= X
+                            regs[arg0] <= x_pos_i;
+                        end
+                        8'b00_0101_??: begin //  GETY ARG0 <= Y
+                            regs[arg0] <= y_pos_i;
+                        end
+                        8'b00_0110_??: begin //  GETTIME ARG0 <= TIME
+                            regs[arg0] <= cur_time;
+                        end
+                        8'b00_0111_??: begin //  GETUSER ARG0 <= USER
+                            regs[arg0] <= user;
+                        end
+
+                        8'b00_1000_??: begin //  IF ARG0 == REGS[0]
+                            skip <= !(regs[arg0] == regs[0]);
+                        end
+                        8'b00_1001_??: begin //  IF ARG0 != REGS[0]
+                            skip <= !(regs[arg0] != regs[0]);
+                        end
+                        8'b00_1010_??: begin //  IF ARG0 >= REGS[0]
+                            skip <= !(regs[arg0] >= regs[0]);
+                        end
+                        8'b00_1011_??: begin // IF ARG0 < REGS[0]
+                            skip <= !(regs[arg0] < regs[0]);
+                        end
+
+                        8'b00_1100_??: begin // TODO special RGB to set all channels same, or use high bits from operand
+
+                        end
+                        8'b00_1101_??: begin // TODO duplicate
+
+                        end
+                        8'b00_1110_??: begin // TODO half
+
+                        end
+                        8'b00_1111_??: begin // SINE ARG0 <= SINE_LUT[REGS[0]]
+                            regs[arg0] <= sine_lut[regs[0][5:2]]; // TODO
+                        end
+
+
+                        // Dual arg instructions 01 - Logical
+                        8'b01_00_??_??: begin // AND ARG0 <= ARG0 & ARG1
+                            regs[arg0] <= regs[arg0] & regs[arg1];
+                        end
+                        8'b01_01_??_??: begin // OR ARG0 <= ARG0 | ARG1
+                            regs[arg0] <= regs[arg0] | regs[arg1];
+                        end
+                        8'b01_10_??_??: begin // NOT ARG0 <= ~ARG1
+                            regs[arg0] <= ~regs[arg1];
+                        end
+                        8'b01_11_??_??: begin // XOR ARG0 <= ARG0 ^ ARG1 
+                            regs[arg0] <= regs[arg0] ^ regs[arg1];
+                        end
+
+                        // Dual arg instructions 10
+                        8'b10_00_??_??: begin // MOV ARG0 <= ARG1
+                            regs[arg0] <= regs[arg1];
+                        end
+                        8'b10_01_??_??: begin // ADD ARG0 <= ARG0 + ARG1
+                            regs[arg0] <= regs[arg0] + regs[arg1];
+                        end
+                        8'b10_10_??_??: begin // SHIFTL ARG0 <= ARG0 << ARG1
+                            regs[arg0] <= regs[arg0] << regs[arg1];
+                        end
+                        8'b10_11_??_??: begin // SHIFTR ARG0 <= ARG0 >> ARG1
+                            regs[arg0] <= regs[arg0] >> regs[arg1];
+                        end
+
+                        // Load immediate 11
+                        8'b11_??????: begin // LDI REGS[0] <= IMM
+                            regs[0] <= imm;
+                        end
+
+
+                        default: begin
+
+                        end
+                    endcase
+                end
+            end
+        end
+    end
+
+    assign rgb_o = rgb;
+
+endmodule

src/shader_memory.sv

@@ -0,0 +1,49 @@
+// SPDX-FileCopyrightText: © 2024 Leo Moser <[email protected]>
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+module shader_memory #(
+    parameter NUM_INSTR = 8
+)(
+    input  logic        clk_i,
+    input  logic        rst_ni,
+    input  logic        shift_i,
+    output logic [7:0]  instr_o
+);
+    logic [7:0] memory [NUM_INSTR];
+    int i;
+
+    // Initialize the memory and shift the memory
+    // by a whole word if shift_i is high
+    always_ff @(posedge clk_i, negedge rst_ni) begin
+        if (!rst_ni) begin
+            `ifdef COCOTB_SIM
+            $readmemb("../sw/binary/test2.bit", memory);
+            `else
+            // Load the default program
+            memory[0] <= 8'b00_0100_00; // GETX R0
+            memory[1] <= 8'b00_0101_01; // GETY R1
+            memory[2] <= 8'b01_11_01_00; // XOR R0 R1
+            memory[3] <= 8'b00_0000_00; // SETRGB R0
+            memory[4] <= 8'b01_11_00_00; // XOR R0 R0
+            memory[5] <= 8'b01_11_00_00; // XOR R0 R0
+            memory[6] <= 8'b01_11_00_00; // XOR R0 R0
+            memory[7] <= 8'b01_11_00_00; // XOR R0 R0
+            `endif
+        end else begin
+            if (shift_i) begin
+                for (i=0; i<NUM_INSTR; i++) begin
+                    if (i < NUM_INSTR-1) begin
+                        memory[i] <= memory[i+1];
+                    end else begin
+                        memory[i] <= memory[0];
+                    end
+                end
+            end
+        end
+    end
+
+    assign instr_o = memory[0];
+
+endmodule