0.4.0

What's Changed

Documentation Changes

• Corrected R/W information for minhv, mclicbase. Added further explana… by @Silabs-ArjanB in #495
• Removed rvfi_sleep and rvfi_wu by @Silabs-ArjanB in #504
• Added fence.i related notes. Added mstateen CSRs (applicable to CV32E… by @Silabs-ArjanB in #524
• Made mcounteren WARL 0x0 by @Silabs-ArjanB in #525
• Added PMA alignment restriction if X_EXT = 1 by @Silabs-ArjanB in #526
• Added modifiable attribute as being implied by main PMA attribute by @Silabs-ArjanB in #527
• Corrected RW into WARL for mseccfg.RLB, mseccfg.MMWP, mseccfg.MML, pm… by @Silabs-ArjanB in #529
• mtvec.mode is a 2-bit WARL bitfield. Require write buffer flush before retiring fence.i by @Silabs-ArjanB in #532
• Removed mcontext and mscontext CSRs by @Silabs-ArjanB in #535
• etrigger.m and mcontrol6.m are now fully implemented (reset values changed as well) by @Silabs-ArjanB in #537
• Described that push and pop operations are not allowed on non-idempot… by @Silabs-ArjanB in #543
• Reordered content in exceptions and interrupts chapter for clarity by @Silabs-ArjanB in #544
• Fixed mcause reset value for SMCLIC=1 configuration by @Silabs-ArjanB in #550
• Updated jvt and mstateen0 CSRs according to latest Zc* clarifications… by @Silabs-ArjanB in #554
• Documented Atomics extension by @Silabs-ArjanB in #557
• Changed dcsr.mprven to WARL 0x1. Added note on ecall behavior in debu… by @Silabs-ArjanB in #559
• Fixed comment related to dcsr.mprven value by @Silabs-ArjanB in #564
• Prevented table scrollbars by @Silabs-ArjanB in #573
• Table width fixes by @Silabs-ArjanB in #574

RTL Changes

• minstret rvfi reporting fix for WFI by @Silabs-ArjanB in #505
• Implementation of mnxti by @silabs-oysteink in #506
• First step towards merged decoder by @Silabs-ArjanB in #508
• Moved two instructions from predecoder to decoder by @Silabs-ArjanB in #510
• Removed nmi_addr_i; removed USE_DEPRECATED_FEATURE_SET parameter by @Silabs-ArjanB in #512
• Bugfix: mnxti data forwarding causing wrong operand values by @silabs-oysteink in #511
• Decoder interface change by @silabs-oysteink in #513
• Bugfixes after running formal by @silabs-oysteink in #514
• Speeding up decoder by @Silabs-ArjanB in #516
• Reverting merged decoder introduction by @Silabs-ArjanB in #519
• Critical path improvements impacting jump, mret in decoder, bypass mo… by @Silabs-ArjanB in #521
• Implemented all C0 instructions from Zc v 0.70.1. by @silabs-oysteink in #528
• Implemented cm.lbu and cm.lhu from Zc C2. by @silabs-oysteink in #531
• Made jumps and mrets depend on alu_en and sys_en, as this change led … by @silabs-oysteink in #536
• Removed mscontext and mcontext CSRs by @Silabs-ArjanB in #534
• Minimizing syntax/style differences with CV32E40S by @Silabs-ArjanB in #538
• Fixed dependency between Zc and Zbb by @Silabs-ArjanB in #545
• Further removal of CLIC pointers using data access. by @silabs-oysteink in #548
• Fix for issue #549. Clean up CS registers syntax. Tie RVFI to RTL ins… by @Silabs-ArjanB in #555
• Initial version of RVFI OBI tracking by @Silabs-ArjanB in #560
• Moved instruction address word alignment to core boundary by @Silabs-ArjanB in #562
• Removed shadow CSR related code by @Silabs-ArjanB in #563
• Unifying interrupt controllers; aligning cs registers syntax with cor… by @Silabs-ArjanB in #566
• Fix for issue #558 by @silabs-oysteink in #567

Full Changelog: 0.3.0...0.4.0