Add hardware debug support

[Matthew-Otto]

This PR adds support for RISC-V Debug Specification Version 1.0.0. There are some quirks with privilege unit interactions which I intend to cleanup soon. Otherwise, the RTL is tested and functional.

This PR also integrates some basic JTAG tests into the regression testing system. I'm open to any feedback that can make it better.

[davidharrishmc]

This PR will need significant testing before it is ready to merge.

[PietDelaney]

Looks very interesting to me. I really enjoyed working on JTAG support on the Tensilica ML605 fpga dev board.

[davidharrishmc]

Piet, I'm delighted you've made all this progress with the FPGA board. If you have bandwidth for working on debug mode, starting with developing a test suite, and then fixing any bugs you unearth, we'd be happy to support and we'd love you to be a Wally contributor. Debug mode is an important feature for us, but the last student working on it left and we don't have anybody ramped up on it at the moment.

[PietDelaney]

I pulled the debug mode pull request and looked at it. It's rather large, my roommate works on Risc-v at TensTorent and is familiar with the Risc-v debug extension. I'll email the authors of the debug pull request. I wasn't able to understand the changes even well enough to know if it will work on my Arty A7-100. I'm having trouble getting my Arty A7 to boot Linux. It's getting stuck in the zsbl/sd.c code on the 2nd command. The code on the 2nd cmd isn't well documented, nothing on the 4 bits of error. ChatGpt was a bit of help. I'll try emailing the authors. I wonder if my not hacking the fpga/generator Make file could be wrong. Your forthcoming book on this wasn't clear. Looking at the Makefile I didn't see the need for modifying it. Perhaps you have updated your draft of your forthcoming book and could send Yuri an update. Maybe it will help me get the Arty FPGA booting. I supported the Tensilicas Xtensa architecture for a few years. I documented the step by step procedure for using FTAG debugging on the Xilinx ML605. This included full Buildroot support. I was surprised that the Wally build instructions seem to be building the classic Buildroot tools but not installing the Buildroot output to the SD card. The root filesystem is empty and the Makefile didn't appear to be copying the Buildroot output to the SD card filesystem. At tensilica we used cpio to make the device nodes and copy the Linux user space objects. Sorry it is taking so long to get up to speed with your Wally framework. Maybe an update on your forthcoming book would help.

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-piet

On Mon, Dec 30, 2024, 8:24 PM David Harris ***@***.***> wrote: Piet, I'm delighted you've made all this progress with the FPGA board. If you have bandwidth for working on debug mode, starting with developing a test suite, and then fixing any bugs you unearth, we'd be happy to support and we'd love you to be a Wally contributor. Debug mode is an important feature for us, but the last student working on it left and we don't have anybody ramped up on it at the moment. — Reply to this email directly, view it on GitHub <#883 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/BKFFREUVRC7OFNWHF5JYLO32IIMBXAVCNFSM6AAAAABK5FCPISVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDKNRWGEZDCNJWGI> . You are receiving this because you commented.Message ID: ***@***.***>

[PietDelaney]

Example ML605 FPGA Support at Tensilica:

https://wiki.linux-xtensa.org/index.php?title=SMP_HiFi_2_Development_Board