Update Dependencies (except svd-parser)

Cargo.toml

@@ -1,11 +1,11 @@
 [package]
 name = "msp430gen"
-version = "0.1.0"
+version = "0.2.0"
 authors = ["Vadzim Dambrouski <[email protected]>"]
 
 [dependencies]
 #ldscript-parser = "0.1"
-xmltree = "*"
+xmltree = "0.10.0"
 svd-parser = { path = "svd-parser" }
-ordermap = "=0.4.0"
+indexmap = "1.3.2"
 Inflector = "0.11.1"

src/dslite_parser.rs

@@ -1,16 +1,16 @@
-use ordermap::OrderMap;
+use indexmap::IndexMap;
 use std::path::Path;
 use utils;
-use xmltree::Element;
+use xmltree::{XMLNode, Element};
 
 #[derive(Debug)]
 pub struct Device {
     pub name: String,
     pub description: String,
-    pub modules: OrderMap<String, Module>,
+    pub modules: IndexMap<String, Module>,
 }
 
-fn get_conflict<'a>(map: &OrderMap<u32, &'a Register>, reg: &Register) -> Option<&'a Register> {
+fn get_conflict<'a>(map: &IndexMap<u32, &'a Register>, reg: &Register) -> Option<&'a Register> {
     for i in 0..reg.width {
         let addr = reg.offset + i;
         if let Some(old) = map.get(&addr) {
@@ -25,11 +25,12 @@ pub fn parse_dslite(file_name: &Path) -> Device {
 
     let name = uw!(el.attributes.get("id")).to_owned();
     let description = uw!(el.attributes.get("description")).to_owned();
-    let cpu = uw!(el.children.iter().find(|i| i.name == "cpu"));
+    let cpu = uw!(el.children.iter().find(|i| i.as_element().map_or(false, |e| e.name == "cpu")));
 
-    let mut cached_modules = OrderMap::new();
+    let mut cached_modules = IndexMap::new();
     let mut registers = Vec::new();
-    for i in &cpu.children {
+
+    for i in &cpu.as_element().expect("The node named CPU wasn't an XML Element!").children {
         if let Some(mut module) = parse_cpu_instance(i, file_name) {
             // Remove all registers from the module before we cache it, since we will fill in the
             // registers after we process duplicates. This two-step caching process also prevents
@@ -52,8 +53,8 @@ pub fn parse_dslite(file_name: &Path) -> Device {
         }
     });
 
-    let mut modules: OrderMap<String, Module> = OrderMap::new();
-    let mut memory: OrderMap<u32, &Register> = OrderMap::new();
+    let mut modules: IndexMap<String, Module> = IndexMap::new();
+    let mut memory: IndexMap<u32, &Register> = IndexMap::new();
     for r in &registers {
         if let Some(old) = get_conflict(&memory, r) {
             if r.width == 2 && old.width == 1 {
@@ -112,7 +113,8 @@ pub struct Module {
     pub registers: Vec<Register>,
 }
 
-fn parse_cpu_instance(el: &Element, root_file: &Path) -> Option<Module> {
+fn parse_cpu_instance(node: &XMLNode, root_file: &Path) -> Option<Module> {
+    let el = node.as_element().expect("CPU instance was not an XML Element!");
     assert_eq!(el.name, "instance");
     let base = uw!(utils::parse_u32(uw!(el.attributes.get("baseaddr"))));
 
@@ -137,7 +139,7 @@ fn parse_dslite_module(file_name: &Path, baseaddr: u32) -> Option<Module> {
     let mut registers = el
         .children
         .iter()
-        .map(|r| parse_register(r, &name))
+        .map(|r| parse_register(r.as_element().expect("Register was not an XML Element!"), &name))
         .collect::<Vec<_>>();
 
     // Rest of the code assumes that the offset value of each register includes the base address of
@@ -186,7 +188,7 @@ fn parse_register(el: &Element, module: &str) -> Register {
     let fields = el
         .children
         .iter()
-        .map(|f| parse_field(f))
+        .map(|f| parse_field(f.as_element().expect("Field was not an XML Element!")))
         .collect::<Vec<_>>();
 
     Register {
@@ -245,7 +247,7 @@ fn parse_field(el: &Element) -> Field {
     let enums = el
         .children
         .iter()
-        .map(|e| parse_enum(e))
+        .map(|e| parse_enum(e.as_element().expect("Enums was not an XML Element!")))
         .collect::<Vec<_>>();
 
     Field {

src/main.rs

@@ -1,5 +1,5 @@
 extern crate inflector;
-extern crate ordermap;
+extern crate indexmap;
 extern crate svd_parser as svd;
 extern crate xmltree;