GitHub - samsoniuk/riscado-v: RISCV implementation in Verilog (RV32I spec)

#riscado-v - Simple RISC-V (RV32I) implementation in Verilog

Just for learning purposes.

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
gcc		gcc
testdata		testdata
tools		tools
xise		xise
.gitignore		.gitignore
LICENSE.txt		LICENSE.txt
README.md		README.md
RISCV_SOC.cdf		RISCV_SOC.cdf
RISCV_SOC.qpf		RISCV_SOC.qpf
RISCV_SOC.qsf		RISCV_SOC.qsf
RISCV_SOC.sdc		RISCV_SOC.sdc
RISCV_SOC.sld		RISCV_SOC.sld
RISCV_SOC.v		RISCV_SOC.v
RISCV_SOC_assignment_defaults.qdf		RISCV_SOC_assignment_defaults.qdf
alu.v		alu.v
c5_pin_model_dump.txt		c5_pin_model_dump.txt
clk_divider.v		clk_divider.v
control_unit.v		control_unit.v
gpu.v		gpu.v
load_store.v		load_store.v
program_counter.v		program_counter.v
ram.v		ram.v
ram_tb.v		ram_tb.v
register_file.v		register_file.v
riscv.v		riscv.v
riscvdefs.vh		riscvdefs.vh
riscvlogo.mif		riscvlogo.mif
rom.v		rom.v
soctop.v		soctop.v
soctop_tb.v		soctop_tb.v
vga_encoder.v		vga_encoder.v
vram.v		vram.v

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