SiFive Intel FPGA Direction Request

intel/common/vsrc/bootrom.v

@@ -0,0 +1,23 @@
+module BootROM(
+  input wire [10:0] address,
+  input wire clock,
+  input wire me,
+  input wire oe,
+  output wire [31:0] q
+);
+
+wire [31:0] q_r;
+
+rom r(
+  .address(address),
+  .clock(clock),
+  .rden(me),
+  .q(q_r)
+);
+
+assign q[31:24] = q_r[7:0];
+assign q[23:16] = q_r[15:8];
+assign q[15:8] = q_r[23:16];
+assign q[7:0] = q_r[31:24];
+
+endmodule

intel/common/vsrc/iobuf_full.v

@@ -0,0 +1,46 @@
+// Joseph Tarango
+module iobuf(
+		output wire [0:0] dataout, //   dout.export
+		input  wire [0:0] datain,  //    din.export
+		input  wire [0:0] oe,      //     oe.export
+		inout  wire [0:0] padio    // pad_io.export
+);
+
+assign dataout = datain;
+
+IOBUF iobufElement(
+		.dataout (dataout), //  output,  width = 1,   dout.export
+		.datain  (datain),  //   input,  width = 1,    din.export
+		.oe      (oe),      //   input,  width = 1,     oe.export
+		.padio   (padio)    //   inout,  width = 1, pad_io.export
+);
+
+endmodule
+
+
+module ibuf(
+  input wire [0:0] datain,
+  output wire [0:0] dataout
+);
+
+assign dataout = datain;
+
+IOBUF ibufElement(
+  .datain(datain),
+  .dataout(dataout)
+);
+
+endmodule
+
+module obuf(
+  input wire [0:0] datain,
+  output wire [0:0] dataout
+);
+
+assign dataout = datain;
+IOBUF obufElement(
+  .datain(datain),
+  .dataout(dataout)
+);
+
+endmodule

intel/common/vsrc/iobuf_wire.v

@@ -0,0 +1,46 @@
+// Joseph Tarango
+module iobuf(
+		output wire [0:0] dataout, //   dout.export
+		input  wire [0:0] datain,  //    din.export
+		input  wire [0:0] oe,      //     oe.export
+		inout  wire [0:0] padio    // pad_io.export
+);
+
+assign dataout = datain;
+
+//IOBUF iobufElement(
+//		.dataout (dataout), //  output,  width = 1,   dout.export
+//		.datain  (datain),  //   input,  width = 1,    din.export
+//		.oe      (oe),      //   input,  width = 1,     oe.export
+//		.padio   (padio)    //   inout,  width = 1, pad_io.export
+//);
+
+endmodule
+
+
+module ibuf(
+  input wire [0:0] datain,
+  output wire [0:0] dataout
+);
+
+assign dataout = datain;
+
+//IOBUF ibufElement(
+//  .datain(datain),
+//  .dataout(dataout)
+//);
+
+endmodule
+
+module obuf(
+  input wire [0:0] datain,
+  output wire [0:0] dataout
+);
+
+assign dataout = datain;
+//IOBUF obufElement(
+//  .datain(datain),
+//  .dataout(dataout)
+//);
+
+endmodule