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Arty: Allow a slower core clk #2

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Arty: Allow a slower core clk #2

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@mwachs5 mwachs5 commented Sep 6, 2017

Add a further divided clock for use if designs can't meet 65MHz timing. Also rename the clock frequencies to be more precise.

@mwachs5 mwachs5 requested a review from henrystyles September 6, 2017 22:14
ckdur pushed a commit to uec-hanken/fpga-shells that referenced this pull request Jan 24, 2024
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